ADRDY

Bit 0: ADC ready This bit is set by hardware after the ADC has been enabled (ADEN = 1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it..

Allowed values:
0: NotReady: ADC not yet ready to start conversion
1: Ready: ADC ready to start conversion

EOSMP

Bit 1: End of sampling flag This bit is set by hardware during the conversion, at the end of the sampling phase.It is cleared by software by programming it to 1..

Allowed values:
0: NotAtEnd: Not at the end of the samplings phase
1: AtEnd: End of sampling phase reached

EOC

Bit 2: End of conversion flag This bit is set by hardware at the end of each conversion of a channel when a new data result is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register..

Allowed values:
0: NotComplete: Channel conversion is not complete
1: Complete: Channel conversion complete

EOS

Bit 3: End of sequence flag This bit is set by hardware at the end of the conversion of a sequence of channels selected by the CHSEL bits. It is cleared by software writing 1 to it..

Allowed values:
0: NotComplete: Conversion sequence is not complete
1: Complete: Conversion sequence complete

OVR

Bit 4: ADC overrun This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete while the EOC flag was already set. It is cleared by software writing 1 to it..

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

AWD[1]

Bit 7: Analog watchdog 1 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD[2]

Bit 8: Analog watchdog 2 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD[3]

Bit 9: Analog watchdog 3 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

EOCAL

Bit 11: End Of Calibration flag This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it..

Allowed values:
0: NotComplete: Calibration is not complete
1: Complete: Calibration complete

CCRDY

Bit 13: Channel Configuration Ready flag This flag bit is set by hardware when the channel configuration is applied after programming to ADC_CHSELR register or changing CHSELRMOD or SCANDIR. It is cleared by software by programming it to it. Note: When the software configures the channels (by programming ADC_CHSELR or changing CHSELRMOD or SCANDIR), it must wait until the CCRDY flag rises before configuring again or starting conversions, otherwise the new configuration (or the START bit) is ignored. Once the flag is asserted, if the software needs to configure again the channels, it must clear the CCRDY flag before proceeding with a new configuration..

Allowed values:
0: NotComplete: Channel configuration update not applied
1: Complete: Channel configuration update is applied

ADRDYIE

Bit 0: ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: ADRDY interrupt disabled
1: Enabled: ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.

EOSMPIE

Bit 1: End of sampling flag interrupt enable This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: EOSMP interrupt disabled
1: Enabled: EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.

EOCIE

Bit 2: End of conversion interrupt enable This bit is set and cleared by software to enable/disable the end of conversion interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: EOC interrupt disabled
1: Enabled: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.

EOSIE

Bit 3: End of conversion sequence interrupt enable This bit is set and cleared by software to enable/disable the end of sequence of conversions interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: EOS interrupt disabled
1: Enabled: EOS interrupt enabled. An interrupt is generated when the EOS bit is set.

OVRIE

Bit 4: Overrun interrupt enable This bit is set and cleared by software to enable/disable the overrun interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: Overrun interrupt disabled
1: Enabled: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.

AWD[1]IE

Bit 7: Analog watchdog 1 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

AWD[2]IE

Bit 8: Analog watchdog 2 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

AWD[3]IE

Bit 9: Analog watchdog 3 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

EOCALIE

Bit 11: End of calibration interrupt enable This bit is set and cleared by software to enable/disable the end of calibration interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: End of calibration interrupt disabled
1: Enabled: End of calibration interrupt enabled

CCRDYIE

Bit 13: Channel Configuration Ready Interrupt enable This bit is set and cleared by software to enable/disable the channel configuration ready interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: Channel configuration ready interrupt disabled
1: Enabled: Channel configuration ready interrupt enabled

ADEN

Bit 0: ADC enable command This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the ADRDY flag has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL = 0, ADSTP = 0, ADSTART = 0, ADDIS = 0 and ADEN = 0).

Allowed values:
0: Disabled: ADC disabled
1: Enabled: ADC enabled

ADDIS

Bit 1: ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: Setting ADDIS to 1 is only effective when ADEN = 1 and ADSTART = 0 (which ensures that no conversion is ongoing).

Allowed values:
0: NotDisabling: No disable command active
1: Disabling: ADC disabling

ADSTART

Bit 2: ADC start conversion command This bit is set by software to start ADC conversion. Depending on the EXTEN [1:0] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: In single conversion mode (CONT = 0, DISCEN = 0), when software trigger is selected (EXTEN = 00): at the assertion of the end of Conversion Sequence (EOS) flag. In discontinuous conversion mode(CONT = 0, DISCEN = 1), when the software trigger is selected (EXTEN = 00): at the assertion of the end of Conversion (EOC) flag. In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is cleared by hardware. Note: The software is allowed to set ADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC). After writing to ADC_CHSELR register or changing CHSELRMOD or SCANDIRW, it is mandatory to wait until CCRDY flag is asserted before setting ADSTART, otherwise, the value written to ADSTART is ignored..

Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting

ADSTP

Bit 4: ADC stop conversion command This bit is set by software to stop and discard an ongoing conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to accept a new start conversion command. Note: Setting ADSTP to 1 is only effective when ADSTART = 1 and ADDIS = 0 (ADC is enabled and may be converting and there is no pending request to disable the ADC).

Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion

ADVREGEN

Bit 28: ADC Voltage Regulator Enable This bit is set by software, to enable the ADC internal voltage regulator. The voltage regulator output is available after tADCVREG_SETUP. It is cleared by software to disable the voltage regulator. It can be cleared only if ADEN is et to 0. Note: The software is allowed to program this bit field only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)..

Allowed values:
0: Disabled: ADC voltage regulator disabled
1: Enabled: ADC voltage regulator enabled

ADCAL

Bit 31: ADC calibration This bit is set by software to start the calibration of the ADC. It is cleared by hardware after calibration is complete. Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN = 1 and ADSTART = 0 (ADC enabled and no conversion is ongoing)..

Allowed values:
0: NotCalibrating: ADC calibration either not yet performed or completed
1: Calibrating: ADC calibration in progress

DMAEN

Bit 0: Direct memory access enable This bit is set and cleared by software to enable the generation of DMA requests. This allows the DMA controller to be used to manage automatically the converted data. For more details, refer to . Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

DMACFG

Bit 1: Direct memory access configuration This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN = 1. For more details, refer to page 355 Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0: OneShot: DMA one shot mode selected
1: Circular: DMA circular mode selected

SCANDIR

Bit 2: Scan sequence direction This bit is set and cleared by software to select the direction in which the channels is scanned in the sequence. It is effective only if CHSELMOD bit is cleared to 0. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0: Upward: Upward scan (from CHSEL0 to CHSEL17)
1: Backward: Backward scan (from CHSEL17 to CHSEL0)

RES

Bits 3-4: Data resolution These bits are written by software to select the resolution of the conversion. Note: The software is allowed to write these bits only when ADEN = 0..

Allowed values:
0: Bits12: 12 bits
1: Bits10: 10 bits
2: Bits8: 8 bits
3: Bits6: 6 bits

ALIGN

Bit 5: Data alignment This bit is set and cleared by software to select right or left alignment. Refer to Data alignment and resolution (oversampling disabled: OVSE = 0) on page 353 Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0: Right: Right alignment
1: Left: Left alignment

EXTSEL

Bits 6-8: External trigger selection These bits select the external event used to trigger the start of conversion (refer to External triggers for details): Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0: TIM1_TRGO: Timer 1 TRGO event
1: TIM1_CC4: Timer 1 CC4 event
2: TIM2_TRGO: Timer 2 TRGO event
3: TIM2_CH4: Timer 2 CH4 event
5: TIM2_CH3: Timer 2 CH3 event
7: EXTI_LINE11: EXTI line 11 event

EXTEN

Bits 10-11: External trigger enable and polarity selection These bits are set and cleared by software to select the external trigger polarity and enable the trigger. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: Hardware trigger detection disabled
1: RisingEdge: Hardware trigger detection on the rising edge
2: FallingEdge: Hardware trigger detection on the falling edge
3: BothEdges: Hardware trigger detection on both the rising and falling edges

OVRMOD

Bit 12: Overrun management mode This bit is set and cleared by software and configure the way data overruns are managed. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0: Preserve: ADC_DR register is preserved with the old data when an overrun is detected
1: Overwrite: ADC_DR register is overwritten with the last conversion result when an overrun is detected

CONT

Bit 13: Single / continuous conversion mode This bit is set and cleared by software. If it is set, conversion takes place continuously until it is cleared. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

WAIT

Bit 14: Wait conversion mode This bit is set and cleared by software to enable/disable wait conversion mode.. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: Wait conversion mode off
1: Enabled: Wait conversion mode on

AUTOFF

Bit 15: Auto-off mode This bit is set and cleared by software to enable/disable auto-off mode.. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: Auto-off mode disabled
1: Enabled: Auto-off mode enabled

DISCEN

Bit 16: Discontinuous mode This bit is set and cleared by software to enable/disable discontinuous mode. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: Discontinuous mode disabled
1: Enabled: Discontinuous mode enabled

CHSELRMOD

Bit 21: Mode selection of the ADC_CHSELR register This bit is set and cleared by software to control the ADC_CHSELR feature: Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0: BitPerInput: Each bit of the ADC_CHSELR register enables an input
1: Sequence: ADC_CHSELR register is able to sequence up to 8 channels

AWD1SGL

Bit 22: Enable the watchdog on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWDCH[4:0] bits or on all the channels Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0: AllChannels: Analog watchdog 1 enabled on all channels
1: SingleChannel: Analog watchdog 1 enabled on a single channel

AWD1EN

Bit 23: Analog watchdog enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: Analog watchdog 1 disabled
1: Enabled: Analog watchdog 1 enabled

AWD1CH

Bits 26-30: Analog watchdog channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. ..... Others: Reserved Note: The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR register. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values: 0x0-0x11

OVSE

Bit 0: Oversampler Enable This bit is set and cleared by software. Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: Oversampler disabled
1: Enabled: Oversampler enabled

OVSR

Bits 2-4: Oversampling ratio This bit filed defines the number of oversampling ratio. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Mul2: 2x
1: Mul4: 4x
2: Mul8: 8x
3: Mul16: 16x
4: Mul32: 32x
5: Mul64: 64x
6: Mul128: 128x
7: Mul256: 256x

OVSS

Bits 5-8: Oversampling shift This bit is set and cleared by software. Others: Reserved Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NoShift: No shift
1: Shift1: Shift 1-bit
2: Shift2: Shift 2-bits
3: Shift3: Shift 3-bits
4: Shift4: Shift 4-bits
5: Shift5: Shift 5-bits
6: Shift6: Shift 6-bits
7: Shift7: Shift 7-bits
8: Shift8: Shift 8-bits

TOVS

Bit 9: Triggered Oversampling This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: TriggerAll: All oversampled conversions for a channel are done consecutively after a trigger
1: TriggerEach: Each oversampled conversion for a channel needs a trigger

LFTRIG

Bit 29: Low frequency trigger mode enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: Low Frequency Trigger Mode disabled
1: Enabled: Low Frequency Trigger Mode enabled

CKMODE

Bits 30-31: ADC clock mode These bits are set and cleared by software to define how the analog ADC is clocked: In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)..

Allowed values:
0: ADCLK: ADCCLK (Asynchronous clock mode)
1: PCLK_Div2: PCLK/2 (Synchronous clock mode)
2: PCLK_Div4: PCLK/4 (Synchronous clock mode)
3: PCLK: PCLK (Synchronous clock mode)

SMP[1]

Bits 0-2: Sampling time selection 1.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles3_5: 3.5 ADC clock cycles
2: Cycles7_5: 7.5 ADC clock cycles
3: Cycles12_5: 12.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles39_5: 39.5 ADC clock cycles
6: Cycles79_5: 79.5 ADC clock cycles
7: Cycles160_5: 160.5 ADC clock cycles

SMP[2]

Bits 4-6: Sampling time selection 2.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles3_5: 3.5 ADC clock cycles
2: Cycles7_5: 7.5 ADC clock cycles
3: Cycles12_5: 12.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles39_5: 39.5 ADC clock cycles
6: Cycles79_5: 79.5 ADC clock cycles
7: Cycles160_5: 160.5 ADC clock cycles

SMPSEL[0]

Bit 8: Channel-0 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[1]

Bit 9: Channel-1 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[2]

Bit 10: Channel-2 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[3]

Bit 11: Channel-3 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[4]

Bit 12: Channel-4 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[5]

Bit 13: Channel-5 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[6]

Bit 14: Channel-6 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[7]

Bit 15: Channel-7 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[8]

Bit 16: Channel-8 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[9]

Bit 17: Channel-9 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[10]

Bit 18: Channel-10 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[11]

Bit 19: Channel-11 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[12]

Bit 20: Channel-12 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[13]

Bit 21: Channel-13 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[14]

Bit 22: Channel-14 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[15]

Bit 23: Channel-15 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[16]

Bit 24: Channel-16 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[17]

Bit 25: Channel-17 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[18]

Bit 26: Channel-18 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[19]

Bit 27: Channel-19 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[20]

Bit 28: Channel-20 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[21]

Bit 29: Channel-21 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

SMPSEL[22]

Bit 30: Channel-22 sampling time selection.

Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register

LT1

Bits 0-11: Analog watchdog 1 lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 359..

Allowed values: 0x0-0xfff

HT1

Bits 16-27: Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 359..

Allowed values: 0x0-0xfff

LT2

Bits 0-11: Analog watchdog 2 lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 359..

Allowed values: 0x0-0xfff

HT2

Bits 16-27: Analog watchdog 2 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 359..

Allowed values: 0x0-0xfff

CHSEL[0]

Bit 0: Channel-0 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[1]

Bit 1: Channel-1 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[2]

Bit 2: Channel-2 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[3]

Bit 3: Channel-3 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[4]

Bit 4: Channel-4 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[5]

Bit 5: Channel-5 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[6]

Bit 6: Channel-6 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[7]

Bit 7: Channel-7 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[8]

Bit 8: Channel-8 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[9]

Bit 9: Channel-9 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[10]

Bit 10: Channel-10 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[11]

Bit 11: Channel-11 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[12]

Bit 12: Channel-12 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[13]

Bit 13: Channel-13 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[14]

Bit 14: Channel-14 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[15]

Bit 15: Channel-15 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[16]

Bit 16: Channel-16 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[17]

Bit 17: Channel-17 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[18]

Bit 18: Channel-18 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[19]

Bit 19: Channel-19 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[20]

Bit 20: Channel-20 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[21]

Bit 21: Channel-21 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL[22]

Bit 22: Channel-22 selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

SQ[1]

Bits 0-3: 1 conversion of the sequence.

Allowed values:
0: Ch0: Channel 0 selected for the Nth conversion
1: Ch1: Channel 1 selected for the Nth conversion
2: Ch2: Channel 2 selected for the Nth conversion
3: Ch3: Channel 3 selected for the Nth conversion
4: Ch4: Channel 4 selected for the Nth conversion
5: Ch5: Channel 5 selected for the Nth conversion
6: Ch6: Channel 6 selected for the Nth conversion
7: Ch7: Channel 7 selected for the Nth conversion
8: Ch8: Channel 8 selected for the Nth conversion
9: Ch9: Channel 9 selected for the Nth conversion
10: Ch10: Channel 10 selected for the Nth conversion
11: Ch11: Channel 11 selected for the Nth conversion
12: Ch12: Channel 12 selected for the Nth conversion
13: Ch13: Channel 13 selected for the Nth conversion
14: Ch14: Channel 14 selected for the Nth conversion
15: EOS: End of sequence

SQ[2]

Bits 4-7: 2 conversion of the sequence.

Allowed values:
0: Ch0: Channel 0 selected for the Nth conversion
1: Ch1: Channel 1 selected for the Nth conversion
2: Ch2: Channel 2 selected for the Nth conversion
3: Ch3: Channel 3 selected for the Nth conversion
4: Ch4: Channel 4 selected for the Nth conversion
5: Ch5: Channel 5 selected for the Nth conversion
6: Ch6: Channel 6 selected for the Nth conversion
7: Ch7: Channel 7 selected for the Nth conversion
8: Ch8: Channel 8 selected for the Nth conversion
9: Ch9: Channel 9 selected for the Nth conversion
10: Ch10: Channel 10 selected for the Nth conversion
11: Ch11: Channel 11 selected for the Nth conversion
12: Ch12: Channel 12 selected for the Nth conversion
13: Ch13: Channel 13 selected for the Nth conversion
14: Ch14: Channel 14 selected for the Nth conversion
15: EOS: End of sequence

SQ[3]

Bits 8-11: 3 conversion of the sequence.

Allowed values:
0: Ch0: Channel 0 selected for the Nth conversion
1: Ch1: Channel 1 selected for the Nth conversion
2: Ch2: Channel 2 selected for the Nth conversion
3: Ch3: Channel 3 selected for the Nth conversion
4: Ch4: Channel 4 selected for the Nth conversion
5: Ch5: Channel 5 selected for the Nth conversion
6: Ch6: Channel 6 selected for the Nth conversion
7: Ch7: Channel 7 selected for the Nth conversion
8: Ch8: Channel 8 selected for the Nth conversion
9: Ch9: Channel 9 selected for the Nth conversion
10: Ch10: Channel 10 selected for the Nth conversion
11: Ch11: Channel 11 selected for the Nth conversion
12: Ch12: Channel 12 selected for the Nth conversion
13: Ch13: Channel 13 selected for the Nth conversion
14: Ch14: Channel 14 selected for the Nth conversion
15: EOS: End of sequence

SQ[4]

Bits 12-15: 4 conversion of the sequence.

Allowed values:
0: Ch0: Channel 0 selected for the Nth conversion
1: Ch1: Channel 1 selected for the Nth conversion
2: Ch2: Channel 2 selected for the Nth conversion
3: Ch3: Channel 3 selected for the Nth conversion
4: Ch4: Channel 4 selected for the Nth conversion
5: Ch5: Channel 5 selected for the Nth conversion
6: Ch6: Channel 6 selected for the Nth conversion
7: Ch7: Channel 7 selected for the Nth conversion
8: Ch8: Channel 8 selected for the Nth conversion
9: Ch9: Channel 9 selected for the Nth conversion
10: Ch10: Channel 10 selected for the Nth conversion
11: Ch11: Channel 11 selected for the Nth conversion
12: Ch12: Channel 12 selected for the Nth conversion
13: Ch13: Channel 13 selected for the Nth conversion
14: Ch14: Channel 14 selected for the Nth conversion
15: EOS: End of sequence

SQ[5]

Bits 16-19: 5 conversion of the sequence.

Allowed values:
0: Ch0: Channel 0 selected for the Nth conversion
1: Ch1: Channel 1 selected for the Nth conversion
2: Ch2: Channel 2 selected for the Nth conversion
3: Ch3: Channel 3 selected for the Nth conversion
4: Ch4: Channel 4 selected for the Nth conversion
5: Ch5: Channel 5 selected for the Nth conversion
6: Ch6: Channel 6 selected for the Nth conversion
7: Ch7: Channel 7 selected for the Nth conversion
8: Ch8: Channel 8 selected for the Nth conversion
9: Ch9: Channel 9 selected for the Nth conversion
10: Ch10: Channel 10 selected for the Nth conversion
11: Ch11: Channel 11 selected for the Nth conversion
12: Ch12: Channel 12 selected for the Nth conversion
13: Ch13: Channel 13 selected for the Nth conversion
14: Ch14: Channel 14 selected for the Nth conversion
15: EOS: End of sequence

SQ[6]

Bits 20-23: 6 conversion of the sequence.

Allowed values:
0: Ch0: Channel 0 selected for the Nth conversion
1: Ch1: Channel 1 selected for the Nth conversion
2: Ch2: Channel 2 selected for the Nth conversion
3: Ch3: Channel 3 selected for the Nth conversion
4: Ch4: Channel 4 selected for the Nth conversion
5: Ch5: Channel 5 selected for the Nth conversion
6: Ch6: Channel 6 selected for the Nth conversion
7: Ch7: Channel 7 selected for the Nth conversion
8: Ch8: Channel 8 selected for the Nth conversion
9: Ch9: Channel 9 selected for the Nth conversion
10: Ch10: Channel 10 selected for the Nth conversion
11: Ch11: Channel 11 selected for the Nth conversion
12: Ch12: Channel 12 selected for the Nth conversion
13: Ch13: Channel 13 selected for the Nth conversion
14: Ch14: Channel 14 selected for the Nth conversion
15: EOS: End of sequence

SQ[7]

Bits 24-27: 7 conversion of the sequence.

Allowed values:
0: Ch0: Channel 0 selected for the Nth conversion
1: Ch1: Channel 1 selected for the Nth conversion
2: Ch2: Channel 2 selected for the Nth conversion
3: Ch3: Channel 3 selected for the Nth conversion
4: Ch4: Channel 4 selected for the Nth conversion
5: Ch5: Channel 5 selected for the Nth conversion
6: Ch6: Channel 6 selected for the Nth conversion
7: Ch7: Channel 7 selected for the Nth conversion
8: Ch8: Channel 8 selected for the Nth conversion
9: Ch9: Channel 9 selected for the Nth conversion
10: Ch10: Channel 10 selected for the Nth conversion
11: Ch11: Channel 11 selected for the Nth conversion
12: Ch12: Channel 12 selected for the Nth conversion
13: Ch13: Channel 13 selected for the Nth conversion
14: Ch14: Channel 14 selected for the Nth conversion
15: EOS: End of sequence

SQ[8]

Bits 28-31: 8 conversion of the sequence.

Allowed values:
0: Ch0: Channel 0 selected for the Nth conversion
1: Ch1: Channel 1 selected for the Nth conversion
2: Ch2: Channel 2 selected for the Nth conversion
3: Ch3: Channel 3 selected for the Nth conversion
4: Ch4: Channel 4 selected for the Nth conversion
5: Ch5: Channel 5 selected for the Nth conversion
6: Ch6: Channel 6 selected for the Nth conversion
7: Ch7: Channel 7 selected for the Nth conversion
8: Ch8: Channel 8 selected for the Nth conversion
9: Ch9: Channel 9 selected for the Nth conversion
10: Ch10: Channel 10 selected for the Nth conversion
11: Ch11: Channel 11 selected for the Nth conversion
12: Ch12: Channel 12 selected for the Nth conversion
13: Ch13: Channel 13 selected for the Nth conversion
14: Ch14: Channel 14 selected for the Nth conversion
15: EOS: End of sequence

LT3

Bits 0-11: Analog watchdog 3lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 359..

Allowed values: 0x0-0xfff

HT3

Bits 16-27: Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 359..

Allowed values: 0x0-0xfff

DATA

Bits 0-15: Converted data These bits are read-only. They contain the conversion result from the last converted channel. The data are left- or right-aligned as shown in OVSE = 0) on page 353. Just after a calibration is complete, DATA[6:0] contains the calibration factor..

Allowed values: 0x0-0xffff

AWD2CH[0]

Bit 0: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[1]

Bit 1: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[2]

Bit 2: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[3]

Bit 3: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[4]

Bit 4: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[5]

Bit 5: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[6]

Bit 6: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[7]

Bit 7: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[8]

Bit 8: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[9]

Bit 9: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[10]

Bit 10: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[11]

Bit 11: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[12]

Bit 12: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[13]

Bit 13: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[14]

Bit 14: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[15]

Bit 15: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[16]

Bit 16: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[17]

Bit 17: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[18]

Bit 18: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[19]

Bit 19: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[20]

Bit 20: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[21]

Bit 21: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD2CH[22]

Bit 22: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2

AWD3CH[0]

Bit 0: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[1]

Bit 1: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[2]

Bit 2: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[3]

Bit 3: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[4]

Bit 4: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[5]

Bit 5: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[6]

Bit 6: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[7]

Bit 7: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[8]

Bit 8: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[9]

Bit 9: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[10]

Bit 10: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[11]

Bit 11: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[12]

Bit 12: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[13]

Bit 13: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[14]

Bit 14: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[15]

Bit 15: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[16]

Bit 16: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[17]

Bit 17: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[18]

Bit 18: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[19]

Bit 19: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[20]

Bit 20: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[21]

Bit 21: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

AWD3CH[22]

Bit 22: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3

CALFACT

Bits 0-6: Calibration factor These bits are written by hardware or by software. Once a calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new calibration is launched. Just after a calibration is complete, DATA[6:0] contains the calibration factor. Note: Software can write these bits only when ADEN=1 (ADC is enabled and no calibration is ongoing and no conversion is ongoing). Refer to SQ8[3:0] for a definition of channel selection..

Allowed values: 0x0-0x7f

PRESC

Bits 18-21: ADC prescaler Set and cleared by software to select the frequency of the clock to the ADC. Other: Reserved Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)..

Allowed values:
0: Div1: Input ADC clock not divided
1: Div2: Input ADC clock divided by 2
2: Div4: Input ADC clock divided by 4
3: Div6: Input ADC clock divided by 6
4: Div8: Input ADC clock divided by 8
5: Div10: Input ADC clock divided by 10
6: Div12: Input ADC clock divided by 12
7: Div16: Input ADC clock divided by 16
8: Div32: Input ADC clock divided by 32
9: Div64: Input ADC clock divided by 64
10: Div128: Input ADC clock divided by 128
11: Div256: Input ADC clock divided by 256

VREFEN

Bit 22: VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT. Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: The selected ADC channel disabled
1: Enabled: The selected ADC channel enabled

TSEN

Bit 23: Temperature sensor enable This bit is set and cleared by software to enable/disable the temperature sensor. Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: The selected ADC channel disabled
1: Enabled: The selected ADC channel enabled

DR

Bits 0-31: Data register bits This register is used to write new data to the CRC calculator. It holds the previous CRC calculation result when it is read. If the data size is less than 32 bits, the least significant bits are used to write/read the correct value..

GPDR

Bits 0-31: General-purpose 32-bit data register bits These bits can be used as a temporary storage location for four bytes. This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register.

RESET

Bit 0: RESET bit This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware.

POLYSIZE

Bits 3-4: Polynomial size These bits control the size of the polynomial..

REV_IN

Bits 5-6: Reverse input data These bits control the reversal of the bit order of the input data.

REV_OUT

Bit 7: Reverse output data This bit controls the reversal of the bit order of the output data..

CRC_INIT

Bits 0-31: Programmable initial CRC value This register is used to write the CRC initial value..

POL

Bits 0-31: Programmable polynomial This register is used to write the coefficients of the polynomial to be used for CRC calculation. If the polynomial size is less than 32 bits, the least significant bits have to be used to program the correct value..

DEV_ID

Bits 0-11: Device identifier This bitfield indicates the device ID..

REV_ID

Bits 16-31: Revision identifier This bitfield indicates the revision of the device..

DBG_STOP

Bit 1: Debug Stop mode.

DBG_STANDBY

Bit 2: Debug Standby and Shutdown modes.

DBG_TIM3_STOP

Bit 1: Clocking of TIM3 counter when the core is halted This bit enables/disables the clock to the counter of TIM3 when the core is halted:.

DBG_RTC_STOP

Bit 10: Clocking of RTC counter when the core is halted This bit enables/disables the clock to the counter of RTC when the core is halted:.

DBG_WWDG_STOP

Bit 11: Clocking of WWDG counter when the core is halted This bit enables/disables the clock to the counter of WWDG when the core is halted:.

DBG_IWDG_STOP

Bit 12: Clocking of IWDG counter when the core is halted This bit enables/disables the clock to the counter of IWDG when the core is halted:.

DBG_I2C1_SMBUS_TIMEOUT

Bit 21: SMBUS timeout when core is halted.

DBG_TIM1_STOP

Bit 11: Clocking of TIM1 counter when the core is halted This bit enables/disables the clock to the counter of TIM1 when the core is halted:.

DBG_TIM14_STOP

Bit 15: Clocking of TIM14 counter when the core is halted This bit enables/disables the clock to the counter of TIM14 when the core is halted:.

DBG_TIM16_STOP

Bit 17: Clocking of TIM16 counter when the core is halted This bit enables/disables the clock to the counter of TIM16 when the core is halted:.

DBG_TIM17_STOP

Bit 18: Clocking of TIM17 counter when the core is halted This bit enables/disables the clock to the counter of TIM17 when the core is halted:.

GIF[1]

Bit 0: Channel 1 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[1]

Bit 1: Channel 1 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[1]

Bit 2: Channel 1 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[1]

Bit 3: Channel 1 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[2]

Bit 4: Channel 2 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[2]

Bit 5: Channel 2 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[2]

Bit 6: Channel 2 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[2]

Bit 7: Channel 2 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[3]

Bit 8: Channel 3 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[3]

Bit 9: Channel 3 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[3]

Bit 10: Channel 3 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[3]

Bit 11: Channel 3 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

CGIF[1]

Bit 0: Channel 1 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[1]

Bit 1: Channel 1 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[1]

Bit 2: Channel 1 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[1]

Bit 3: Channel 1 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[2]

Bit 4: Channel 2 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[2]

Bit 5: Channel 2 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[2]

Bit 6: Channel 2 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[2]

Bit 7: Channel 2 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[3]

Bit 8: Channel 3 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[3]

Bit 9: Channel 3 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[3]

Bit 10: Channel 3 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[3]

Bit 11: Channel 3 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

EN

Bit 0: channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software..

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDT

Bits 0-15: number of data to transfer (0 to 216 - 1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA read followed by write transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values: 0x0-0xffff

PA

Bits 0-31: peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

MA

Bits 0-31: peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

EN

Bit 0: channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software..

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDT

Bits 0-15: number of data to transfer (0 to 216 - 1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA read followed by write transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values: 0x0-0xffff

PA

Bits 0-31: peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

MA

Bits 0-31: peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

EN

Bit 0: channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software..

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDT

Bits 0-15: number of data to transfer (0 to 216 - 1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA read followed by write transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values: 0x0-0xffff

PA

Bits 0-31: peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

MA

Bits 0-31: peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

DMAREQ_ID

Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..

SOIE

Bit 8: Synchronization overrun interrupt enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources)..

DMAREQ_ID

Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..

SOIE

Bit 8: Synchronization overrun interrupt enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources)..

DMAREQ_ID

Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..

SOIE

Bit 8: Synchronization overrun interrupt enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources)..

SOF[0]

Bit 0: Synchronization Overrun Flag 0.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[1]

Bit 1: Synchronization Overrun Flag 1.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[2]

Bit 2: Synchronization Overrun Flag 2.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

CSOF[0]

Bit 0: Synchronization Clear Overrun Flag 0.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[1]

Bit 1: Synchronization Clear Overrun Flag 1.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[2]

Bit 2: Synchronization Clear Overrun Flag 2.

Allowed values:
1: Clear: Clear synchronization flag