STM32C031 Peripheral Coverage

ADC

0x40012400: Analog to Digital Converter

1/161 fields covered.

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Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	ISR																			CCRDY		EOCAL		AWD3	AWD2	AWD1			OVR	EOS	EOC	EOSMP	ADRDY
0x4	IER																			CCRDYIE		EOCALIE		AWD3IE	AWD2IE	AWD1IE			OVRIE	EOSIE	EOCIE	EOSMPIE	ADRDYIE
0x8	CR	ADCAL			ADVREGEN																								ADSTP		ADSTART	ADDIS	ADEN
0xc	CFGR1		AWD1CH							AWD1EN	AWD1SGL	CHSELRMOD					DISCEN	AUTOFF	WAIT	CONT	OVRMOD	EXTEN			EXTSEL			ALIGN	RES		SCANDIR	DMACFG	DMAEN
0x10	CFGR2	CKMODE		LFTRIG																				TOVS	OVSS				OVSR				OVSE
0x14	SMPR		SMPSEL22	SMPSEL21	SMPSEL20	SMPSEL19	SMPSEL18	SMPSEL17	SMPSEL16	SMPSEL15	SMPSEL14	SMPSEL13	SMPSEL12	SMPSEL11	SMPSEL10	SMPSEL9	SMPSEL8	SMPSEL7	SMPSEL6	SMPSEL5	SMPSEL4	SMPSEL3	SMPSEL2	SMPSEL1	SMPSEL0		SMP2				SMP1
0x20	AWD1TR					HT1																LT1
0x24	AWD2TR					HT2																LT2
0x28	CHSELR0										CHSEL22	CHSEL21	CHSEL20	CHSEL19	CHSEL18	CHSEL17	CHSEL16	CHSEL15	CHSEL14	CHSEL13	CHSEL12	CHSEL11	CHSEL10	CHSEL9	CHSEL8	CHSEL7	CHSEL6	CHSEL5	CHSEL4	CHSEL3	CHSEL2	CHSEL1	CHSEL0
0x28	CHSELR1	SQ8				SQ7				SQ6				SQ5				SQ4				SQ3				SQ2				SQ1
0x2c	AWD3TR					HT3																LT3
0x40	DR																	DATA
0xa0	AWD2CR										AWD2CH22	AWD2CH21	AWD2CH20	AWD2CH19	AWD2CH18	AWD2CH17	AWD2CH16	AWD2CH15	AWD2CH14	AWD2CH13	AWD2CH12	AWD2CH11	AWD2CH10	AWD2CH9	AWD2CH8	AWD2CH7	AWD2CH6	AWD2CH5	AWD2CH4	AWD2CH3	AWD2CH2	AWD2CH1	AWD2CH0
0xa4	AWD3CR										AWD3CH22	AWD3CH21	AWD3CH20	AWD3CH19	AWD3CH18	AWD3CH17	AWD3CH16	AWD3CH15	AWD3CH14	AWD3CH13	AWD3CH12	AWD3CH11	AWD3CH10	AWD3CH9	AWD3CH8	AWD3CH7	AWD3CH6	AWD3CH5	AWD3CH4	AWD3CH3	AWD3CH2	AWD3CH1	AWD3CH0
0xb4	CALFACT																										CALFACT
0x308	CCR									TSEN	VREFEN	PRESC

Toggle registers

ISR

ADC interrupt and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CCRDY rw		EOCAL rw		AWD3 rw	AWD2 rw	AWD1 rw			OVR rw	EOS rw	EOC rw	EOSMP rw	ADRDY rw

Toggle fields

ADRDY

Bit 0: ADC ready This bit is set by hardware after the ADC has been enabled (ADEN = 1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it..

EOSMP

Bit 1: End of sampling flag This bit is set by hardware during the conversion, at the end of the sampling phase.It is cleared by software by programming it to 1..

EOC

Bit 2: End of conversion flag This bit is set by hardware at the end of each conversion of a channel when a new data result is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register..

EOS

Bit 3: End of sequence flag This bit is set by hardware at the end of the conversion of a sequence of channels selected by the CHSEL bits. It is cleared by software writing 1 to it..

OVR

Bit 4: ADC overrun This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete while the EOC flag was already set. It is cleared by software writing 1 to it..

AWD1

Bit 7: Analog watchdog 1 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_TR1 and ADC_HR1 registers. It is cleared by software by programming it to 1..

AWD2

Bit 8: Analog watchdog 2 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD2TR and ADC_AWD2TR registers. It is cleared by software programming it it..

AWD3

Bit 9: Analog watchdog 3 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD3TR and ADC_AWD3TR registers. It is cleared by software by programming it to 1..

EOCAL

Bit 11: End Of Calibration flag This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it..

CCRDY

Bit 13: Channel Configuration Ready flag This flag bit is set by hardware when the channel configuration is applied after programming to ADC_CHSELR register or changing CHSELRMOD or SCANDIR. It is cleared by software by programming it to it. Note: When the software configures the channels (by programming ADC_CHSELR or changing CHSELRMOD or SCANDIR), it must wait until the CCRDY flag rises before configuring again or starting conversions, otherwise the new configuration (or the START bit) is ignored. Once the flag is asserted, if the software needs to configure again the channels, it must clear the CCRDY flag before proceeding with a new configuration..

IER

ADC interrupt enable register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CCRDYIE rw		EOCALIE rw		AWD3IE rw	AWD2IE rw	AWD1IE rw			OVRIE rw	EOSIE rw	EOCIE rw	EOSMPIE rw	ADRDYIE rw

Toggle fields

ADRDYIE

Bit 0: ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

EOSMPIE

Bit 1: End of sampling flag interrupt enable This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

EOCIE

Bit 2: End of conversion interrupt enable This bit is set and cleared by software to enable/disable the end of conversion interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

EOSIE

Bit 3: End of conversion sequence interrupt enable This bit is set and cleared by software to enable/disable the end of sequence of conversions interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

OVRIE

Bit 4: Overrun interrupt enable This bit is set and cleared by software to enable/disable the overrun interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

AWD1IE

Bit 7: Analog watchdog 1 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

AWD2IE

Bit 8: Analog watchdog 2 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

AWD3IE

Bit 9: Analog watchdog 3 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

EOCALIE

Bit 11: End of calibration interrupt enable This bit is set and cleared by software to enable/disable the end of calibration interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

CCRDYIE

Bit 13: Channel Configuration Ready Interrupt enable This bit is set and cleared by software to enable/disable the channel configuration ready interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

CR

ADC control register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADCAL rw			ADVREGEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											ADSTP rw		ADSTART rw	ADDIS rw	ADEN rw

Toggle fields

ADEN

Bit 0: ADC enable command This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the ADRDY flag has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL = 0, ADSTP = 0, ADSTART = 0, ADDIS = 0 and ADEN = 0).

ADDIS

Bit 1: ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: Setting ADDIS to 1 is only effective when ADEN = 1 and ADSTART = 0 (which ensures that no conversion is ongoing).

ADSTART

Bit 2: ADC start conversion command This bit is set by software to start ADC conversion. Depending on the EXTEN [1:0] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: In single conversion mode (CONT = 0, DISCEN = 0), when software trigger is selected (EXTEN = 00): at the assertion of the end of Conversion Sequence (EOS) flag. In discontinuous conversion mode(CONT = 0, DISCEN = 1), when the software trigger is selected (EXTEN = 00): at the assertion of the end of Conversion (EOC) flag. In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is cleared by hardware. Note: The software is allowed to set ADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC). After writing to ADC_CHSELR register or changing CHSELRMOD or SCANDIRW, it is mandatory to wait until CCRDY flag is asserted before setting ADSTART, otherwise, the value written to ADSTART is ignored..

ADSTP

Bit 4: ADC stop conversion command This bit is set by software to stop and discard an ongoing conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to accept a new start conversion command. Note: Setting ADSTP to 1 is only effective when ADSTART = 1 and ADDIS = 0 (ADC is enabled and may be converting and there is no pending request to disable the ADC).

ADVREGEN

Bit 28: ADC Voltage Regulator Enable This bit is set by software, to enable the ADC internal voltage regulator. The voltage regulator output is available after tADCVREG_SETUP. It is cleared by software to disable the voltage regulator. It can be cleared only if ADEN is et to 0. Note: The software is allowed to program this bit field only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)..

ADCAL

Bit 31: ADC calibration This bit is set by software to start the calibration of the ADC. It is cleared by hardware after calibration is complete. Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN = 1 and ADSTART = 0 (ADC enabled and no conversion is ongoing)..

CFGR1

ADC configuration register 1

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	AWD1CH rw							AWD1EN rw	AWD1SGL rw	CHSELRMOD rw					DISCEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AUTOFF rw	WAIT rw	CONT rw	OVRMOD rw	EXTEN rw			EXTSEL rw			ALIGN rw	RES rw		SCANDIR rw	DMACFG rw	DMAEN rw

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DMAEN

Bit 0: Direct memory access enable This bit is set and cleared by software to enable the generation of DMA requests. This allows the DMA controller to be used to manage automatically the converted data. For more details, refer to . Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

DMACFG

Bit 1: Direct memory access configuration This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN = 1. For more details, refer to page 355 Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

SCANDIR

Bit 2: Scan sequence direction This bit is set and cleared by software to select the direction in which the channels is scanned in the sequence. It is effective only if CHSELMOD bit is cleared to 0. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

RES

Bits 3-4: Data resolution These bits are written by software to select the resolution of the conversion. Note: The software is allowed to write these bits only when ADEN = 0..

ALIGN

Bit 5: Data alignment This bit is set and cleared by software to select right or left alignment. Refer to Data alignment and resolution (oversampling disabled: OVSE = 0) on page 353 Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

EXTSEL

Bits 6-8: External trigger selection These bits select the external event used to trigger the start of conversion (refer to External triggers for details): Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

EXTEN

Bits 10-11: External trigger enable and polarity selection These bits are set and cleared by software to select the external trigger polarity and enable the trigger. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

OVRMOD

Bit 12: Overrun management mode This bit is set and cleared by software and configure the way data overruns are managed. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

CONT

Bit 13: Single / continuous conversion mode This bit is set and cleared by software. If it is set, conversion takes place continuously until it is cleared. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

WAIT

Bit 14: Wait conversion mode This bit is set and cleared by software to enable/disable wait conversion mode.. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

AUTOFF

Bit 15: Auto-off mode This bit is set and cleared by software to enable/disable auto-off mode.. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

DISCEN

Bit 16: Discontinuous mode This bit is set and cleared by software to enable/disable discontinuous mode. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

CHSELRMOD

Bit 21: Mode selection of the ADC_CHSELR register This bit is set and cleared by software to control the ADC_CHSELR feature: Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

AWD1SGL

Bit 22: Enable the watchdog on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWDCH[4:0] bits or on all the channels Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

AWD1EN

Bit 23: Analog watchdog enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

AWD1CH

Bits 26-30: Analog watchdog channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. ..... Others: Reserved Note: The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR register. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

CFGR2

ADC configuration register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CKMODE rw		LFTRIG rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						TOVS rw	OVSS rw				OVSR rw				OVSE rw

Toggle fields

OVSE

Bit 0: Oversampler Enable This bit is set and cleared by software. Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

OVSR

Bits 2-4: Oversampling ratio This bit filed defines the number of oversampling ratio. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

OVSS

Bits 5-8: Oversampling shift This bit is set and cleared by software. Others: Reserved Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

TOVS

Bit 9: Triggered Oversampling This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

LFTRIG

Bit 29: Low frequency trigger mode enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

CKMODE

Bits 30-31: ADC clock mode These bits are set and cleared by software to define how the analog ADC is clocked: In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)..

SMPR

ADC sampling time register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/25 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	SMPSEL22 rw	SMPSEL21 rw	SMPSEL20 rw	SMPSEL19 rw	SMPSEL18 rw	SMPSEL17 rw	SMPSEL16 rw	SMPSEL15 rw	SMPSEL14 rw	SMPSEL13 rw	SMPSEL12 rw	SMPSEL11 rw	SMPSEL10 rw	SMPSEL9 rw	SMPSEL8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SMPSEL7 rw	SMPSEL6 rw	SMPSEL5 rw	SMPSEL4 rw	SMPSEL3 rw	SMPSEL2 rw	SMPSEL1 rw	SMPSEL0 rw		SMP2 rw				SMP1 rw

Toggle fields

SMP1

Bits 0-2: Sampling time selection 1 These bits are written by software to select the sampling time that applies to all channels. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

SMP2

Bits 4-6: Sampling time selection 2 These bits are written by software to select the sampling time that applies to all channels. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

SMPSEL0

Bit 8: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels..

SMPSEL1

Bit 9: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels..

SMPSEL2

Bit 10: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels..

SMPSEL3

Bit 11: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels..

SMPSEL4

Bit 12: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels..

SMPSEL5

Bit 13: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels..

SMPSEL6

Bit 14: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels..

SMPSEL7

Bit 15: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels..

SMPSEL8

Bit 16: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels..

SMPSEL9

Bit 17: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels..

SMPSEL10

Bit 18: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels..

SMPSEL11

Bit 19: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels..

SMPSEL12

Bit 20: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels..

SMPSEL13

Bit 21: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels..

SMPSEL14

Bit 22: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels..

SMPSEL15

Bit 23: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels..

SMPSEL16

Bit 24: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels..

SMPSEL17

Bit 25: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels..

SMPSEL18

Bit 26: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels..

SMPSEL19

Bit 27: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels..

SMPSEL20

Bit 28: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels..

SMPSEL21

Bit 29: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels..

SMPSEL22

Bit 30: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Refer to for the maximum number of channels..

AWD1TR

ADC watchdog threshold register

Offset: 0x20, size: 32, reset: 0x0FFF0000, access: Unspecified

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HT1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				LT1 rw

Toggle fields

LT1

Bits 0-11: Analog watchdog 1 lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 359..

HT1

Bits 16-27: Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 359..

AWD2TR

ADC watchdog threshold register

Offset: 0x24, size: 32, reset: 0x0FFF0000, access: Unspecified

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HT2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				LT2 rw

Toggle fields

LT2

Bits 0-11: Analog watchdog 2 lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 359..

HT2

Bits 16-27: Analog watchdog 2 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 359..

CHSELR0

ADC channel selection register [alternate]

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

0/23 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									CHSEL22 rw	CHSEL21 rw	CHSEL20 rw	CHSEL19 rw	CHSEL18 rw	CHSEL17 rw	CHSEL16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CHSEL15 rw	CHSEL14 rw	CHSEL13 rw	CHSEL12 rw	CHSEL11 rw	CHSEL10 rw	CHSEL9 rw	CHSEL8 rw	CHSEL7 rw	CHSEL6 rw	CHSEL5 rw	CHSEL4 rw	CHSEL3 rw	CHSEL2 rw	CHSEL1 rw	CHSEL0 rw

Toggle fields

CHSEL0

Bit 0: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL1

Bit 1: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL2

Bit 2: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL3

Bit 3: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL4

Bit 4: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL5

Bit 5: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL6

Bit 6: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL7

Bit 7: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL8

Bit 8: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL9

Bit 9: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL10

Bit 10: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL11

Bit 11: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL12

Bit 12: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL13

Bit 13: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL14

Bit 14: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL15

Bit 15: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL16

Bit 16: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL17

Bit 17: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL18

Bit 18: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL19

Bit 19: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL20

Bit 20: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL21

Bit 21: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL22

Bit 22: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSELR1

ADC channel selection register [alternate]

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SQ8 rw				SQ7 rw				SQ6 rw				SQ5 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SQ4 rw				SQ3 rw				SQ2 rw				SQ1 rw

Toggle fields

SQ1

Bits 0-3: 1st conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

SQ2

Bits 4-7: 2nd conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

SQ3

Bits 8-11: 3rd conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

SQ4

Bits 12-15: 4th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

SQ5

Bits 16-19: 5th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

SQ6

Bits 20-23: 6th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

SQ7

Bits 24-27: 7th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

SQ8

Bits 28-31: 8th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates the end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. ... Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

AWD3TR

ADC watchdog threshold register

Offset: 0x2c, size: 32, reset: 0x0FFF0000, access: Unspecified

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HT3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				LT3 rw

Toggle fields

LT3

Bits 0-11: Analog watchdog 3lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 359..

HT3

Bits 16-27: Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 359..

DR

ADC data register

Offset: 0x40, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATA r

Toggle fields

DATA

Bits 0-15: Converted data These bits are read-only. They contain the conversion result from the last converted channel. The data are left- or right-aligned as shown in OVSE = 0) on page 353. Just after a calibration is complete, DATA[6:0] contains the calibration factor..

AWD2CR

ADC Analog Watchdog 2 Configuration register

Offset: 0xa0, size: 32, reset: 0x00000000, access: Unspecified

0/23 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									AWD2CH22 rw	AWD2CH21 rw	AWD2CH20 rw	AWD2CH19 rw	AWD2CH18 rw	AWD2CH17 rw	AWD2CH16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AWD2CH15 rw	AWD2CH14 rw	AWD2CH13 rw	AWD2CH12 rw	AWD2CH11 rw	AWD2CH10 rw	AWD2CH9 rw	AWD2CH8 rw	AWD2CH7 rw	AWD2CH6 rw	AWD2CH5 rw	AWD2CH4 rw	AWD2CH3 rw	AWD2CH2 rw	AWD2CH1 rw	AWD2CH0 rw

Toggle fields

AWD2CH0

Bit 0: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

AWD2CH1

Bit 1: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

AWD2CH2

Bit 2: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

AWD2CH3

Bit 3: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

AWD2CH4

Bit 4: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

AWD2CH5

Bit 5: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

AWD2CH6

Bit 6: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

AWD2CH7

Bit 7: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

AWD2CH8

Bit 8: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

AWD2CH9

Bit 9: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

AWD2CH10

Bit 10: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

AWD2CH11

Bit 11: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

AWD2CH12

Bit 12: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

AWD2CH13

Bit 13: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

AWD2CH14

Bit 14: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

AWD2CH15

Bit 15: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

AWD2CH16

Bit 16: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

AWD2CH17

Bit 17: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

AWD2CH18

Bit 18: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

AWD2CH19

Bit 19: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

AWD2CH20

Bit 20: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

AWD2CH21

Bit 21: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

AWD2CH22

Bit 22: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

AWD3CR

ADC Analog Watchdog 3 Configuration register

Offset: 0xa4, size: 32, reset: 0x00000000, access: Unspecified

0/23 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									AWD3CH22 rw	AWD3CH21 rw	AWD3CH20 rw	AWD3CH19 rw	AWD3CH18 rw	AWD3CH17 rw	AWD3CH16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AWD3CH15 rw	AWD3CH14 rw	AWD3CH13 rw	AWD3CH12 rw	AWD3CH11 rw	AWD3CH10 rw	AWD3CH9 rw	AWD3CH8 rw	AWD3CH7 rw	AWD3CH6 rw	AWD3CH5 rw	AWD3CH4 rw	AWD3CH3 rw	AWD3CH2 rw	AWD3CH1 rw	AWD3CH0 rw

Toggle fields

AWD3CH0

Bit 0: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH1

Bit 1: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH2

Bit 2: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH3

Bit 3: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH4

Bit 4: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH5

Bit 5: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH6

Bit 6: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH7

Bit 7: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH8

Bit 8: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH9

Bit 9: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH10

Bit 10: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH11

Bit 11: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH12

Bit 12: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH13

Bit 13: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH14

Bit 14: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH15

Bit 15: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH16

Bit 16: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH17

Bit 17: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH18

Bit 18: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH19

Bit 19: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH20

Bit 20: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH21

Bit 21: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH22

Bit 22: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

CALFACT

ADC Calibration factor

Offset: 0xb4, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									CALFACT rw

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CALFACT

Bits 0-6: Calibration factor These bits are written by hardware or by software. Once a calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new calibration is launched. Just after a calibration is complete, DATA[6:0] contains the calibration factor. Note: Software can write these bits only when ADEN=1 (ADC is enabled and no calibration is ongoing and no conversion is ongoing). Refer to SQ8[3:0] for a definition of channel selection..

CCR

ADC common configuration register

Offset: 0x308, size: 32, reset: 0x00000000, access: Unspecified

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								TSEN rw	VREFEN rw	PRESC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

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PRESC

Bits 18-21: ADC prescaler Set and cleared by software to select the frequency of the clock to the ADC. Other: Reserved Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)..

VREFEN

Bit 22: VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT. Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

TSEN

Bit 23: Temperature sensor enable This bit is set and cleared by software to enable/disable the temperature sensor. Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

CRC

0x40023000: Cyclic redundancy check calculation unit

0/8 fields covered.

Toggle register map

Offset	Name	31	15	7	6	4	0
0x0	DR	DR	DR
0x4	IDR	GPDR	GPDR
0x8	CR			REV_OUT	REV_IN	POLYSIZE	RESET
0x10	INIT	CRC_INIT	CRC_INIT
0x14	POL	POL	POL

Toggle registers

DR

CRC data register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: Unspecified

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR rw

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DR

Bits 0-31: Data register bits This register is used to write new data to the CRC calculator. It holds the previous CRC calculation result when it is read. If the data size is less than 32 bits, the least significant bits are used to write/read the correct value..

IDR

CRC independent data register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
GPDR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
GPDR rw

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GPDR

Bits 0-31: General-purpose 32-bit data register bits These bits can be used as a temporary storage location for four bytes. This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register.

CR

CRC control register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REV_OUT rw	REV_IN rw		POLYSIZE rw				RESET rw

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RESET

Bit 0: RESET bit This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware.

POLYSIZE

Bits 3-4: Polynomial size These bits control the size of the polynomial..

REV_IN

Bits 5-6: Reverse input data These bits control the reversal of the bit order of the input data.

REV_OUT

Bit 7: Reverse output data This bit controls the reversal of the bit order of the output data..

INIT

CRC initial value

Offset: 0x10, size: 32, reset: 0xFFFFFFFF, access: Unspecified

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CRC_INIT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRC_INIT rw

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CRC_INIT

Bits 0-31: Programmable initial CRC value This register is used to write the CRC initial value..

POL

CRC polynomial

Offset: 0x14, size: 32, reset: 0x04C11DB7, access: Unspecified

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
POL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
POL rw

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POL

Bits 0-31: Programmable polynomial This register is used to write the coefficients of the polynomial to be used for CRC calculation. If the polynomial size is less than 32 bits, the least significant bits have to be used to program the correct value..

DBG

0x40015800: DBG register block

2/13 fields covered.

Toggle register map

Offset	Name	31	21	18	17	15	12	11	10	2	1
0x0	IDCODE	REV_ID						DEV_ID
0x4	CR									DBG_STANDBY	DBG_STOP
0x8	APB_FZ1		DBG_I2C1_SMBUS_TIMEOUT				DBG_IWDG_STOP	DBG_WWDG_STOP	DBG_RTC_STOP		DBG_TIM3_STOP
0xc	APB_FZ2			DBG_TIM17_STOP	DBG_TIM16_STOP	DBG_TIM14_STOP		DBG_TIM1_STOP

Toggle registers

IDCODE

DBG device ID code register

Offset: 0x0, size: 32, reset: 0x10000453, access: Unspecified

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
REV_ID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				DEV_ID r

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DEV_ID

Bits 0-11: Device identifier This bitfield indicates the device ID..

REV_ID

Bits 16-31: Revision identifier This bitfield indicates the revision of the device..

CR

DBG configuration register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													DBG_STANDBY rw	DBG_STOP rw

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DBG_STOP

Bit 1: Debug Stop mode.

DBG_STANDBY

Bit 2: Debug Standby and Shutdown modes.

APB_FZ1

DBG APB freeze register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										DBG_I2C1_SMBUS_TIMEOUT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBG_IWDG_STOP rw	DBG_WWDG_STOP rw	DBG_RTC_STOP rw									DBG_TIM3_STOP rw

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DBG_TIM3_STOP

Bit 1: Clocking of TIM3 counter when the core is halted This bit enables/disables the clock to the counter of TIM3 when the core is halted:.

DBG_RTC_STOP

Bit 10: Clocking of RTC counter when the core is halted This bit enables/disables the clock to the counter of RTC when the core is halted:.

DBG_WWDG_STOP

Bit 11: Clocking of WWDG counter when the core is halted This bit enables/disables the clock to the counter of WWDG when the core is halted:.

DBG_IWDG_STOP

Bit 12: Clocking of IWDG counter when the core is halted This bit enables/disables the clock to the counter of IWDG when the core is halted:.

DBG_I2C1_SMBUS_TIMEOUT

Bit 21: SMBUS timeout when core is halted.

APB_FZ2

DBG APB freeze register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													DBG_TIM17_STOP rw	DBG_TIM16_STOP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DBG_TIM14_STOP rw				DBG_TIM1_STOP rw

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DBG_TIM1_STOP

Bit 11: Clocking of TIM1 counter when the core is halted This bit enables/disables the clock to the counter of TIM1 when the core is halted:.

DBG_TIM14_STOP

Bit 15: Clocking of TIM14 counter when the core is halted This bit enables/disables the clock to the counter of TIM14 when the core is halted:.

DBG_TIM16_STOP

Bit 17: Clocking of TIM16 counter when the core is halted This bit enables/disables the clock to the counter of TIM16 when the core is halted:.

DBG_TIM17_STOP

Bit 18: Clocking of TIM17 counter when the core is halted This bit enables/disables the clock to the counter of TIM17 when the core is halted:.

DMA

0x40020000: DMA controller

12/69 fields covered.

Toggle register map

Offset	Name	31	15	14	13	11	10	9	8	7	6	5	4	3	2	1	0
0x0	ISR					TEIF3	HTIF3	TCIF3	GIF3	TEIF2	HTIF2	TCIF2	GIF2	TEIF1	HTIF1	TCIF1	GIF1
0x4	IFCR					CTEIF3	CHTIF3	CTCIF3	CGIF3	CTEIF2	CHTIF2	CTCIF2	CGIF2	CTEIF1	CHTIF1	CTCIF1	CGIF1
0x8	CCR1			MEM2MEM	PL	MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0xc	CNDTR1		NDT
0x10	CPAR1	PA	PA
0x14	CMAR1	MA	MA
0x1c	CCR2			MEM2MEM	PL	MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x20	CNDTR2		NDT
0x24	CPAR2	PA	PA
0x28	CMAR2	MA	MA
0x30	CCR3			MEM2MEM	PL	MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x34	CNDTR3		NDT
0x38	CPAR3	PA	PA
0x3c	CMAR3	MA	MA

Toggle registers

ISR

DMA interrupt status register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				TEIF3 r	HTIF3 r	TCIF3 r	GIF3 r	TEIF2 r	HTIF2 r	TCIF2 r	GIF2 r	TEIF1 r	HTIF1 r	TCIF1 r	GIF1 r

Toggle fields

GIF1

Bit 0: global interrupt flag for channel 1.

TCIF1

Bit 1: transfer complete (TC) flag for channel 1.

HTIF1

Bit 2: half transfer (HT) flag for channel 1.

TEIF1

Bit 3: transfer error (TE) flag for channel 1.

GIF2

Bit 4: global interrupt flag for channel 2.

TCIF2

Bit 5: transfer complete (TC) flag for channel 2.

HTIF2

Bit 6: half transfer (HT) flag for channel 2.

TEIF2

Bit 7: transfer error (TE) flag for channel 2.

GIF3

Bit 8: global interrupt flag for channel 3.

TCIF3

Bit 9: transfer complete (TC) flag for channel 3.

HTIF3

Bit 10: half transfer (HT) flag for channel 3.

TEIF3

Bit 11: transfer error (TE) flag for channel 3.

IFCR

DMA interrupt flag clear register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				CTEIF3 w	CHTIF3 w	CTCIF3 w	CGIF3 w	CTEIF2 w	CHTIF2 w	CTCIF2 w	CGIF2 w	CTEIF1 w	CHTIF1 w	CTCIF1 w	CGIF1 w

Toggle fields

CGIF1

Bit 0: global interrupt flag clear for channel 1.

CTCIF1

Bit 1: transfer complete flag clear for channel 1.

CHTIF1

Bit 2: half transfer flag clear for channel 1.

CTEIF1

Bit 3: transfer error flag clear for channel 1.

CGIF2

Bit 4: global interrupt flag clear for channel 2.

CTCIF2

Bit 5: transfer complete flag clear for channel 2.

CHTIF2

Bit 6: half transfer flag clear for channel 2.

CTEIF2

Bit 7: transfer error flag clear for channel 2.

CGIF3

Bit 8: global interrupt flag clear for channel 3.

CTCIF3

Bit 9: transfer complete flag clear for channel 3.

CHTIF3

Bit 10: half transfer flag clear for channel 3.

CTEIF3

Bit 11: transfer error flag clear for channel 3.

CCR1

DMA channel 1 configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

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EN

Bit 0: channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software..

TCIE

Bit 1: transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

HTIE

Bit 2: half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

TEIE

Bit 3: transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

DIR

Bit 4: data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

CIRC

Bit 5: circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

PINC

Bit 6: peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

MINC

Bit 7: memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

PSIZE

Bits 8-9: peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

MSIZE

Bits 10-11: memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

PL

Bits 12-13: priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

MEM2MEM

Bit 14: memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

CNDTR1

DMA channel 1 number of data to transfer register

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

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NDT

Bits 0-15: number of data to transfer (0 to 216 - 1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA read followed by write transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

CPAR1

DMA channel 1 peripheral address register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

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PA

Bits 0-31: peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

CMAR1

DMA channel 1 memory address register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

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MA

Bits 0-31: peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

CCR2

DMA channel 2 configuration register

Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software..

TCIE

Bit 1: transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

HTIE

Bit 2: half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

TEIE

Bit 3: transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

DIR

Bit 4: data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

CIRC

Bit 5: circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

PINC

Bit 6: peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

MINC

Bit 7: memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

PSIZE

Bits 8-9: peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

MSIZE

Bits 10-11: memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

PL

Bits 12-13: priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

MEM2MEM

Bit 14: memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

CNDTR2

DMA channel 2 number of data to transfer register

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

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NDT

Bits 0-15: number of data to transfer (0 to 216 - 1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA read followed by write transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

CPAR2

DMA channel 2 peripheral address register

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

CMAR2

DMA channel 2 memory address register

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

CCR3

DMA channel 3 configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: Unspecified

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software..

TCIE

Bit 1: transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

HTIE

Bit 2: half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

TEIE

Bit 3: transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

DIR

Bit 4: data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

CIRC

Bit 5: circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

PINC

Bit 6: peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

MINC

Bit 7: memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

PSIZE

Bits 8-9: peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

MSIZE

Bits 10-11: memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

PL

Bits 12-13: priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

MEM2MEM

Bit 14: memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

CNDTR3

DMA channel 3 number of data to transfer register

Offset: 0x34, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: number of data to transfer (0 to 216 - 1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA read followed by write transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

CPAR3

DMA channel 3 peripheral address register

Offset: 0x38, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

CMAR3

DMA channel 3 memory address register

Offset: 0x3c, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

DMAMUX

0x40020800: DMAMUX register block

7/55 fields covered.

Toggle register map

Offset	Name	28	23	18	16	9	8	5	4	3	2	1	0
0x0	CCR[0]	SYNC_ID	NBREQ	SPOL	SE	EGE	SOIE	DMAREQ_ID
0x4	CCR[1]	SYNC_ID	NBREQ	SPOL	SE	EGE	SOIE	DMAREQ_ID
0x8	CCR[2]	SYNC_ID	NBREQ	SPOL	SE	EGE	SOIE	DMAREQ_ID
0x80	CSR										SOF2	SOF1	SOF0
0x84	CFR										CSOF2	CSOF1	CSOF0
0x100	RGCR[0]		GNBREQ	GPOL	GE		OIE		SIG_ID
0x104	RGCR[1]		GNBREQ	GPOL	GE		OIE		SIG_ID
0x108	RGCR[2]		GNBREQ	GPOL	GE		OIE		SIG_ID
0x10c	RGCR[3]		GNBREQ	GPOL	GE		OIE		SIG_ID
0x140	RGSR									OF3	OF2	OF1	OF0
0x144	RGCFR									COF3	COF2	COF1	COF0

Toggle registers

CCR[0]

DMA Multiplexer Channel 0 Control register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SYNC_ID rw					NBREQ rw					SPOL rw		SE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EGE rw	SOIE rw			DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..

SOIE

Bit 8: Synchronization overrun interrupt enable.

EGE

Bit 9: Event generation enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..

SYNC_ID

Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources)..

CCR[1]

DMA Multiplexer Channel 1 Control register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SYNC_ID rw					NBREQ rw					SPOL rw		SE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EGE rw	SOIE rw			DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..

SOIE

Bit 8: Synchronization overrun interrupt enable.

EGE

Bit 9: Event generation enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..

SYNC_ID

Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources)..

CCR[2]

DMA Multiplexer Channel 2 Control register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SYNC_ID rw					NBREQ rw					SPOL rw		SE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EGE rw	SOIE rw			DMAREQ_ID rw

Toggle fields

DMAREQ_ID

Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..

SOIE

Bit 8: Synchronization overrun interrupt enable.

EGE

Bit 9: Event generation enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..

SYNC_ID

Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources)..

CSR

DMAMUX request line multiplexer interrupt channel status register

Offset: 0x80, size: 32, reset: 0x00000000, access: Unspecified

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													SOF2 r	SOF1 r	SOF0 r

Toggle fields

SOF0

Bit 0: Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register..

SOF1

Bit 1: Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register..

SOF2

Bit 2: Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register..

CFR

DMAMUX request line multiplexer interrupt clear flag register

Offset: 0x84, size: 32, reset: 0x00000000, access: Unspecified

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													CSOF2 w	CSOF1 w	CSOF0 w

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CSOF0

Bit 0: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register..

CSOF1

Bit 1: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register..

CSOF2

Bit 2: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register..

RGCR[0]

DMAMUX request generator channel 0 configuration register

Offset: 0x100, size: 32, reset: 0x00000000, access: Unspecified

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								GNBREQ rw					GPOL rw		GE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							OIE rw				SIG_ID rw

Toggle fields

SIG_ID

Bits 0-4: Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator.

OIE

Bit 8: Trigger overrun interrupt enable.

GE

Bit 16: DMA request generator channel x enable.

GPOL

Bits 17-18: DMA request generator trigger polarity Defines the edge polarity of the selected trigger input.

GNBREQ

Bits 19-23: Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field must be written only when GE bit is disabled..

RGCR[1]

DMAMUX request generator channel 1 configuration register

Offset: 0x104, size: 32, reset: 0x00000000, access: Unspecified

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								GNBREQ rw					GPOL rw		GE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							OIE rw				SIG_ID rw

Toggle fields

SIG_ID

Bits 0-4: Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator.

OIE

Bit 8: Trigger overrun interrupt enable.

GE

Bit 16: DMA request generator channel x enable.

GPOL

Bits 17-18: DMA request generator trigger polarity Defines the edge polarity of the selected trigger input.

GNBREQ

Bits 19-23: Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field must be written only when GE bit is disabled..

RGCR[2]

DMAMUX request generator channel 2 configuration register

Offset: 0x108, size: 32, reset: 0x00000000, access: Unspecified

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								GNBREQ rw					GPOL rw		GE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							OIE rw				SIG_ID rw

Toggle fields

SIG_ID

Bits 0-4: Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator.

OIE

Bit 8: Trigger overrun interrupt enable.

GE

Bit 16: DMA request generator channel x enable.

GPOL

Bits 17-18: DMA request generator trigger polarity Defines the edge polarity of the selected trigger input.

GNBREQ

Bits 19-23: Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field must be written only when GE bit is disabled..

RGCR[3]

DMAMUX request generator channel 3 configuration register

Offset: 0x10c, size: 32, reset: 0x00000000, access: Unspecified

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								GNBREQ rw					GPOL rw		GE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							OIE rw				SIG_ID rw

Toggle register map

Offset	Name	31	25	23	19	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	RTSR1					RT15	RT14	RT13	RT12	RT11	RT10	RT9	RT8	RT7	RT6	RT5	RT4	RT3	RT2	RT1	RT0
0x4	FTSR1					FT15	FT14	FT13	FT12	FT11	FT10	FT9	FT8	FT7	FT6	FT5	FT4	FT3	FT2	FT1	FT0
0x8	SWIER1					SWI15	SWI14	SWI13	SWI12	SWI11	SWI10	SWI9	SWI8	SWI7	SWI6	SWI5	SWI4	SWI3	SWI2	SWI1	SWI0
0xc	RPR1					RPIF15	RPIF14	RPIF13	RPIF12	RPIF11	RPIF10	RPIF9	RPIF8	RPIF7	RPIF6	RPIF5	RPIF4	RPIF3	RPIF2	RPIF1	RPIF0
0x10	FPR1					FPIF15	FPIF14	FPIF13	FPIF12	FPIF11	FPIF10	FPIF9	FPIF8	FPIF7	FPIF6	FPIF5	FPIF4	FPIF3	FPIF2	FPIF1	FPIF0
0x60	EXTICR1	EXTI3		EXTI2		EXTI1								EXTI0
0x64	EXTICR2	EXTI3		EXTI2		EXTI1								EXTI0
0x68	EXTICR3	EXTI3		EXTI2		EXTI1								EXTI0
0x6c	EXTICR4	EXTI3		EXTI2		EXTI1								EXTI0
0x80	IMR1	IM31	IM25	IM23	IM19	IM
0x84	EMR1	EM31	EM25	EM23	EM19	EM

Toggle registers

RTSR1

EXTI rising trigger selection register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RT15 rw	RT14 rw	RT13 rw	RT12 rw	RT11 rw	RT10 rw	RT9 rw	RT8 rw	RT7 rw	RT6 rw	RT5 rw	RT4 rw	RT3 rw	RT2 rw	RT1 rw	RT0 rw

Toggle fields

RT0

Bit 0: Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line..

RT1

Bit 1: Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line..

RT2

Bit 2: Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line..

RT3

Bit 3: Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line..

RT4

Bit 4: Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line..

RT5

Bit 5: Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line..

RT6

Bit 6: Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line..

RT7

Bit 7: Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line..

RT8

Bit 8: Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line..

RT9

Bit 9: Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line..

RT10

Bit 10: Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line..

RT11

Bit 11: Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line..

RT12

Bit 12: Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line..

RT13

Bit 13: Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line..

RT14

Bit 14: Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line..

RT15

Bit 15: Rising trigger event configuration bit of configurable line x (x = 15 to 0) Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line..

FTSR1

EXTI falling trigger selection register 1

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FT15 rw	FT14 rw	FT13 rw	FT12 rw	FT11 rw	FT10 rw	FT9 rw	FT8 rw	FT7 rw	FT6 rw	FT5 rw	FT4 rw	FT3 rw	FT2 rw	FT1 rw	FT0 rw

Toggle fields

FT0

Bit 0: Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line..

FT1

Bit 1: Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line..

FT2

Bit 2: Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line..

FT3

Bit 3: Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line..

FT4

Bit 4: Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line..

FT5

Bit 5: Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line..

FT6

Bit 6: Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line..

FT7

Bit 7: Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line..

FT8

Bit 8: Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line..

FT9

Bit 9: Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line..

FT10

Bit 10: Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line..

FT11

Bit 11: Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line..

FT12

Bit 12: Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line..

FT13

Bit 13: Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line..

FT14

Bit 14: Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line..

FT15

Bit 15: Falling trigger event configuration bit of configurable line x (x = 15 to 0). Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line..

SWIER1

EXTI software interrupt event register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWI15 rw	SWI14 rw	SWI13 rw	SWI12 rw	SWI11 rw	SWI10 rw	SWI9 rw	SWI8 rw	SWI7 rw	SWI6 rw	SWI5 rw	SWI4 rw	SWI3 rw	SWI2 rw	SWI1 rw	SWI0 rw

Toggle fields

SWI0

Bit 0: Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0..

SWI1

Bit 1: Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0..

SWI2

Bit 2: Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0..

SWI3

Bit 3: Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0..

SWI4

Bit 4: Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0..

SWI5

Bit 5: Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0..

SWI6

Bit 6: Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0..

SWI7

Bit 7: Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0..

SWI8

Bit 8: Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0..

SWI9

Bit 9: Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0..

SWI10

Bit 10: Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0..

SWI11

Bit 11: Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0..

SWI12

Bit 12: Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0..

SWI13

Bit 13: Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0..

SWI14

Bit 14: Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0..

SWI15

Bit 15: Software rising edge event trigger on line x (x = 15 to 0) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0..

RPR1

EXTI rising edge pending register 1

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RPIF15 rw	RPIF14 rw	RPIF13 rw	RPIF12 rw	RPIF11 rw	RPIF10 rw	RPIF9 rw	RPIF8 rw	RPIF7 rw	RPIF6 rw	RPIF5 rw	RPIF4 rw	RPIF3 rw	RPIF2 rw	RPIF1 rw	RPIF0 rw

Toggle fields

RPIF0

Bit 0: Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it..

RPIF1

Bit 1: Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it..

RPIF2

Bit 2: Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it..

RPIF3

Bit 3: Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it..

RPIF4

Bit 4: Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it..

RPIF5

Bit 5: Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it..

RPIF6

Bit 6: Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it..

RPIF7

Bit 7: Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it..

RPIF8

Bit 8: Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it..

RPIF9

Bit 9: Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it..

RPIF10

Bit 10: Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it..

RPIF11

Bit 11: Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it..

RPIF12

Bit 12: Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it..

RPIF13

Bit 13: Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it..

RPIF14

Bit 14: Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it..

RPIF15

Bit 15: Rising edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it..

FPR1

EXTI falling edge pending register 1

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FPIF15 rw	FPIF14 rw	FPIF13 rw	FPIF12 rw	FPIF11 rw	FPIF10 rw	FPIF9 rw	FPIF8 rw	FPIF7 rw	FPIF6 rw	FPIF5 rw	FPIF4 rw	FPIF3 rw	FPIF2 rw	FPIF1 rw	FPIF0 rw

Toggle fields

FPIF0

Bit 0: Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it..

FPIF1

Bit 1: Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it..

FPIF2

Bit 2: Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it..

FPIF3

Bit 3: Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it..

FPIF4

Bit 4: Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it..

FPIF5

Bit 5: Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it..

FPIF6

Bit 6: Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it..

FPIF7

Bit 7: Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it..

FPIF8

Bit 8: Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it..

FPIF9

Bit 9: Falling edge event pending for configurable line x (x = 15 to 0) Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it..

FPIF10

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IM31 rw						IM25 rw		IM23 rw				IM19 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IM rw

Toggle fields

IM

Bits 0-15: CPU wakeup with interrupt mask.

IM19

Bit 19: IM19.

IM23

Bit 23: IM23.

IM25

Bit 25: IM25.

IM31

Bit 31: IM31.

EMR1

EXTI CPU wakeup with event mask register

Offset: 0x84, size: 32, reset: 0x00000000, access: Unspecified

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EM31 rw						EM25 rw		EM23 rw				EM19 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EM rw

Toggle fields

EM

Bits 0-15: CPU wakeup with event generation mask.

EM19

Bit 19: EM19.

EM23

Bit 23: EM23.

EM25

Bit 25: EM25.

EM31

Bit 31: EM31.

FLASH

0x40022000: Spider_FLASH register block

2/65 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	ACR													DBG_SWEN		EMPTY					ICRST		ICEN	PRFTEN						LATENCY
0x8	KEYR	KEY															KEY
0xc	OPTKEYR	OPTKEY															OPTKEY
0x10	SR													CFGBSY		BSY1	OPTVERR	RDERR					FASTERR	MISSERR	PGSERR	SIZERR	PGAERR	WRPERR	PROGERR		OPERR	EOP
0x14	CR	LOCK	OPTLOCK		SEC_PROT	OBL_LAUNCH	RDERRIE	ERRIE	EOPIE					FSTPG	OPTSTRT	STRT								PNB						MER1	PER	PG
0x20	OPTR			IRHEN	NRST_MODE		NBOOT0	NBOOT1	NBOOT_SEL	SECURE_MUXING_EN	RAM_PARITY_CHECK	HSE_NOT_REMAPPED	WWDG_SW	IWGD_STDBY	IWDG_STOP	IWDG_SW	NRST_SHDW	NRST_STDBY	NRST_STOP	BORF_LEV		BORR_LEV		BOR_EN	RDP
0x24	PCROP1ASR																								PCROP1A_STRT
0x28	PCROP1AER	PCROP_RDP																							PCROP1A_END
0x2c	WRP1AR											WRP1A_END															WRP1A_STRT
0x30	WRP1BR											WRP1B_END															WRP1B_STRT
0x34	PCROP1BSR																								PCROP1B_STRT
0x38	PCROP1BER																								PCROP1B_END
0x80	SECR															BOOT_LOCK									SEC_SIZE

Toggle registers

ACR

FLASH access control register

Offset: 0x0, size: 32, reset: 0x00040600, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													DBG_SWEN rw		EMPTY rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				ICRST rw		ICEN rw	PRFTEN rw						LATENCY rw

Toggle fields

LATENCY

Bits 0-2: Flash memory access latency The value in this bitfield represents the number of CPU wait states when accessing the flash memory. Other: Reserved A new write into the bitfield becomes effective when it returns the same value upon read..

PRFTEN

Bit 8: CPU Prefetch enable.

ICEN

Bit 9: CPU Instruction cache enable.

ICRST

Bit 11: CPU Instruction cache reset This bit can be written only when the instruction cache is disabled..

EMPTY

Bit 16: Main flash memory area empty This bit indicates whether the first location of the Main flash memory area was read as erased or as programmed during OBL. It is not affected by the system reset. Software may need to change this bit value after a flash memory program or erase operation. The bit can be set and reset by software..

DBG_SWEN

Bit 18: Debug access software enable Software may use this bit to enable/disable the debugger read access..

KEYR

FLASH key register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
KEY w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY w

Toggle fields

KEY

Bits 0-31: FLASH key The following values must be written consecutively to unlock the FLASH control register (FLASH_CR), thus enabling programming/erasing operations: KEY1: 0x4567 0123 KEY2: 0xCDEF 89AB.

OPTKEYR

FLASH option key register

Offset: 0xc, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OPTKEY w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OPTKEY w

Toggle fields

OPTKEY

Bits 0-31: Option byte key The following values must be written consecutively to unlock the flash memory option registers, enabling option byte programming/erasing operations: KEY1: 0x0819 2A3B KEY2: 0x4C5D 6E7F.

SR

FLASH status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													CFGBSY r		BSY1 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OPTVERR rw	RDERR rw					FASTERR rw	MISSERR rw	PGSERR rw	SIZERR rw	PGAERR rw	WRPERR rw	PROGERR rw		OPERR rw	EOP rw

Toggle fields

EOP

Bit 0: End of operation Set by hardware when one or more flash memory operation (programming / erase) has been completed successfully. This bit is set only if the end of operation interrupts are enabled (EOPIE=1). Cleared by writing 1..

OPERR

Bit 1: Operation error Set by hardware when a flash memory operation (program / erase) completes unsuccessfully. This bit is set only if error interrupts are enabled (ERRIE=1). Cleared by writing '1'..

PROGERR

Bit 3: Programming error Set by hardware when a double-word address to be programmed contains a value different from '0xFFFF FFFF' before programming, except if the data to write is '0x0000 0000'. Cleared by writing 1..

WRPERR

Bit 4: Write protection error Set by hardware when an address to be erased/programmed belongs to a write-protected part (by WRP, PCROP or RDP Level 1) of the flash memory. Cleared by writing 1..

PGAERR

Bit 5: Programming alignment error Set by hardware when the data to program cannot be contained in the same double word (64-bit) flash memory in case of standard programming, or if there is a change of page during fast programming. Cleared by writing 1..

SIZERR

Bit 6: Size error Set by hardware when the size of the access is a byte or half-word during a program or a fast program sequence. Only double word programming is allowed (consequently: word access). Cleared by writing 1..

PGSERR

Bit 7: Programming sequence error Set by hardware when a write access to the flash memory is performed by the code while PG or FSTPG have not been set previously. Set also by hardware when PROGERR, SIZERR, PGAERR, WRPERR, MISSERR or FASTERR is set due to a previous programming error. Cleared by writing 1..

MISSERR

Bit 8: Fast programming data miss error In Fast programming mode, 16 double words (128 bytes) must be sent to flash memory successively, and the new data must be sent to the logic control before the current data is fully programmed. MISSERR is set by hardware when the new data is not present in time. Cleared by writing 1..

FASTERR

Bit 9: Fast programming error Set by hardware when a fast programming sequence (activated by FSTPG) is interrupted due to an error (alignment, size, write protection or data miss). The corresponding status bit (PGAERR, SIZERR, WRPERR or MISSERR) is set at the same time. Cleared by writing 1..

RDERR

Bit 14: PCROP read error Set by hardware when an address to be read belongs to a read protected area of the flash memory (PCROP protection). An interrupt is generated if RDERRIE is set in FLASH_CR. Cleared by writing 1..

OPTVERR

Bit 15: Option and Engineering bits loading validity error Set by hardware when the options and engineering bits read may not be the one configured by the user or production. If options and engineering bits haven't been properly loaded, OPTVERR is set again after each system reset. Option bytes that fail loading are forced to a safe value, see Section4.4.2: FLASH option byte programming. Cleared by writing 1..

BSY1

Bit 16: Busy This flag indicates that a flash memory operation requested by FLASH control register (FLASH_CR) is in progress. This bit is set at the beginning of the flash memory operation, and cleared when the operation finishes or when an error occurs..

CFGBSY

Bit 18: Programming or erase configuration busy. This flag is set and reset by hardware. For flash program operation, it is set when the first word is sent, and cleared after the second word is sent when the operation completes or ends with an error. For flash erase operation, it is set when setting the STRT bit of the FLASH_CR register and cleared when the operation completes or ends with an error. When set, a programming or erase operation is ongoing and the corresponding settings in the FLASH control register (FLASH_CR) are used (busy) and cannot be changed. Any other flash operation launch must be postponed. When cleared, the programming and erase settings in the FLASH control register (FLASH_CR) can be modified. Note: The CFGBSY bit is also set when attempting to write locked flash memory (with the first byte sent). When the CFGBSY bit is set, writing into the FLASH_CR register causes HardFault.To clear the CFGBSY bit, send a double word to the flash memory and wait until the access is finished (otherwise the CFGBSY bit remains set)..

CR

FLASH control register

Offset: 0x14, size: 32, reset: 0xC0000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw	OPTLOCK rw		SEC_PROT rw	OBL_LAUNCH rw	RDERRIE rw	ERRIE rw	EOPIE rw						FSTPG rw	OPTSTRT rw	STRT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							PNB rw						MER1 rw	PER rw	PG rw

Toggle fields

PG

Bit 0: Flash memory programming enable.

PER

Bit 1: Page erase enable.

MER1

Bit 2: Mass erase When set, this bit triggers the mass erase, that is, all user pages..

PNB

Bits 3-8: Page number selection These bits select the page to erase: ... Note: Values corresponding to addresses outside the Main memory are not allowed. See Table6 and Table7..

STRT

Bit 16: Start erase operation This bit triggers an erase operation when set. This bit is possible to set only by software and to clear only by hardware. The hardware clears it when one of BSY1 and BSY2 flags in the FLASH_SR register transits to zero..

OPTSTRT

Bit 17: Start of modification of option bytes This bit triggers an options operation when set. This bit is set only by software, and is cleared when the BSY1 bit is cleared in FLASH_SR..

FSTPG

Bit 18: Fast programming enable.

EOPIE

Bit 24: End-of-operation interrupt enable This bit enables the interrupt generation upon setting the EOP flag in the FLASH_SR register..

ERRIE

Bit 25: Error interrupt enable This bit enables the interrupt generation upon setting the OPERR flag in the FLASH_SR register..

RDERRIE

Bit 26: PCROP read error interrupt enable This bit enables the interrupt generation upon setting the RDERR flag in the FLASH_SR register..

OBL_LAUNCH

Bit 27: Option byte load launch When set, this bit triggers the load of option bytes into option registers. It is automatically cleared upon the completion of the load. The high state of the bit indicates pending option byte load. The bit cannot be cleared by software. It cannot be written as long as OPTLOCK is set..

SEC_PROT

Bit 28: Securable memory area protection enable This bit enables the protection on securable area, provided that a non-null securable memory area size (SEC_SIZE[4:0]) is defined in option bytes. This bit is possible to set only by software and to clear only through a system reset..

OPTLOCK

Bit 30: Options Lock This bit is set only. When set, all bits concerning user option in FLASH_CR register and so option page are locked. This bit is cleared by hardware after detecting the unlock sequence. The LOCK bit must be cleared before doing the unlock sequence for OPTLOCK bit. In case of an unsuccessful unlock operation, this bit remains set until the next reset..

LOCK

Bit 31: FLASH_CR Lock This bit is set only. When set, the FLASH_CR register is locked. It is cleared by hardware after detecting the unlock sequence. In case of an unsuccessful unlock operation, this bit remains set until the next system reset..

OPTR

FLASH option register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		IRHEN rw	NRST_MODE rw		NBOOT0 rw	NBOOT1 rw	NBOOT_SEL rw	SECURE_MUXING_EN rw	RAM_PARITY_CHECK rw	HSE_NOT_REMAPPED rw		WWDG_SW rw	IWGD_STDBY rw	IWDG_STOP rw	IWDG_SW rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NRST_SHDW rw	NRST_STDBY rw	NRST_STOP rw	BORF_LEV rw		BORR_LEV rw		BOR_EN rw	RDP rw

Toggle fields

RDP

Bits 0-7: Read protection level Other: Level 1, memories read protection active.

BOR_EN

Bit 8: Brown out reset enable.

BORR_LEV

Bits 9-10: BOR threshold at rising VDD supply Rising VDD crossings this threshold releases the reset signal..

BORF_LEV

Bits 11-12: BOR threshold at falling VDD supply Falling VDD crossings this threshold activates the reset signal..

NRST_STOP

Bit 13: None.

NRST_STDBY

Bit 14: None.

NRST_SHDW

Bit 15: None.

IWDG_SW

Bit 16: None.

IWDG_STOP

Bit 17: Independent watchdog counter freeze in Stop mode.

IWGD_STDBY

Bit 18: None.

WWDG_SW

Bit 19: Window watchdog selection.

HSE_NOT_REMAPPED

Bit 21: HSE remapping enable/disable When cleared, the bit remaps the HSE clock source from PF0-OSC_IN/PF1-OSC_OUT pins to PC14-OSCX_IN/PC15-OSCX_OUT. Thus PC14-OSCX_IN/PC15-OSCX_OUT are shared by both LSE and HSE and the two clock sources cannot be use simultaneously. On packages with less than 48 pins, the remapping is always enabled (PF0-OSC_IN/PF1-OSC_OUT are not available), regardless of this bit. As all STM32C011xx packages have less than 48 pins, this bit is only applicable to STM32C031xx. Note: On 48 pins packages, when HSE_NOT_REMAPPED is reset, HSE cannot be used in bypass mode. Refer to product errata sheet for more details..

RAM_PARITY_CHECK

Bit 22: SRAM parity check control enable/disable.

SECURE_MUXING_EN

Bit 23: Multiple-bonding security The bit allows enabling automatic I/O configuration to prevent conflicts on I/Os connected (bonded) onto the same pin. If the software sets one of the I/Os connected to the same pin as active by configuring the SYSCFG_CFGR3 register, enabling this bit automatically forces the other I/Os in digital input mode, regardless of their software configuration. When the bit is disabled, the SYSCFG_CFGR3 register setting is ignored, all GPIOs linked to a given pin are active and can be set in the mode specified by the corresponding GPIOx_MODER register. The user software must ensure that there is no conflict between GPIOs..

NBOOT_SEL

Bit 24: BOOT0 signal source selection This option bit defines the source of the BOOT0 signal..

NBOOT1

Bit 25: Boot configuration Together with the BOOT0 pin or option bit nBOOT0 (depending on nBOOT_SEL option bit configuration), this bit selects boot mode from the Main flash memory, SRAM or the System memory. Refer to Section3: Boot configuration..

NBOOT0

Bit 26: nBOOT0 option bit.

NRST_MODE

Bits 27-28: NRST pin configuration.

IRHEN

Bit 29: Internal reset holder enable bit.

PCROP1ASR

FLASH PCROP area A start address register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PCROP1A_STRT rw

Toggle fields

PCROP1A_STRT

Bits 0-7: PCROP1A area start offset Contains the offset of the first subpage of the PCROP1A area. Note: The number of effective bits depends on the size of the flash memory in the device..

PCROP1AER

FLASH PCROP area A end address register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PCROP_RDP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PCROP1A_END rw

Toggle fields

PCROP1A_END

Bits 0-7: PCROP1A area end offset Contains the offset of the last subpage of the PCROP1A area. Note: The number of effective bits depends on the size of the flash memory in the device..

PCROP_RDP

Bit 31: PCROP area erase upon RDP level regression This bit determines whether the PCROP area (and the totality of the PCROP area boundary pages) is erased by the mass erase triggered by the RDP level regression from Level 1 to Level 0: The software can only set this bit. It is automatically reset upon mass erase following the RDP regression from Level 1 to Level 0..

WRP1AR

FLASH WRP area A address register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										WRP1A_END rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										WRP1A_STRT rw

Toggle fields

WRP1A_STRT

Bits 0-5: WRP area A start offset This bitfield contains the offset of the first page of the WRP area A. Note: The number of effective bits depends on the size of the flash memory in the device..

WRP1A_END

Bits 16-21: WRP area A end offset This bitfield contains the offset of the last page of the WRP area A. Note: The number of effective bits depends on the size of the flash memory in the device..

WRP1BR

FLASH WRP area B address register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										WRP1B_END rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										WRP1B_STRT rw

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															BOOT_LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								SEC_SIZE rw

Toggle fields

SEC_SIZE

Bits 0-7: Securable memory area size Contains the number of securable flash memory pages. Note: The number of effective bits depends on the size of the flash memory in the device..

BOOT_LOCK

Bit 16: used to force boot from user area If the bit is set in association with RDP level 1, the debug capabilities are disabled, except in the case of a bad OBL (mismatch)..

GPIOA

0x50000000: GPIOA address block description

16/177 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	MODER	MODE15		MODE14		MODE13		MODE12		MODE11		MODE10		MODE9		MODE8		MODE7		MODE6		MODE5		MODE4		MODE3		MODE2		MODE1		MODE0
0x4	OTYPER																	OT15	OT14	OT13	OT12	OT11	OT10	OT9	OT8	OT7	OT6	OT5	OT4	OT3	OT2	OT1	OT0
0x8	OSPEEDR	OSPEED15		OSPEED14		OSPEED13		OSPEED12		OSPEED11		OSPEED10		OSPEED9		OSPEED8		OSPEED7		OSPEED6		OSPEED5		OSPEED4		OSPEED3		OSPEED2		OSPEED1		OSPEED0
0xc	PUPDR	PUPD15		PUPD14		PUPD13		PUPD12		PUPD11		PUPD10		PUPD9		PUPD8		PUPD7		PUPD6		PUPD5		PUPD4		PUPD3		PUPD2		PUPD1		PUPD0
0x10	IDR																	ID15	ID14	ID13	ID12	ID11	ID10	ID9	ID8	ID7	ID6	ID5	ID4	ID3	ID2	ID1	ID0
0x14	ODR																	OD15	OD14	OD13	OD12	OD11	OD10	OD9	OD8	OD7	OD6	OD5	OD4	OD3	OD2	OD1	OD0
0x18	BSRR	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0	BS15	BS14	BS13	BS12	BS11	BS10	BS9	BS8	BS7	BS6	BS5	BS4	BS3	BS2	BS1	BS0
0x1c	LCKR																LCKK	LCK15	LCK14	LCK13	LCK12	LCK11	LCK10	LCK9	LCK8	LCK7	LCK6	LCK5	LCK4	LCK3	LCK2	LCK1	LCK0
0x20	AFRL	AFSEL7				AFSEL6				AFSEL5				AFSEL4				AFSEL3				AFSEL2				AFSEL1				AFSEL0
0x24	AFRH	AFSEL15				AFSEL14				AFSEL13				AFSEL12				AFSEL11				AFSEL10				AFSEL9				AFSEL8
0x28	BRR																	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0

Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xEBFFFFFF, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODE15 rw		MODE14 rw		MODE13 rw		MODE12 rw		MODE11 rw		MODE10 rw		MODE9 rw		MODE8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODE7 rw		MODE6 rw		MODE5 rw		MODE4 rw		MODE3 rw		MODE2 rw		MODE1 rw		MODE0 rw

Toggle fields

MODE0

Bits 0-1: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE1

Bits 2-3: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE2

Bits 4-5: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE3

Bits 6-7: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE4

Bits 8-9: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE5

Bits 10-11: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE6

Bits 12-13: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE7

Bits 14-15: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE8

Bits 16-17: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE9

Bits 18-19: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE10

Bits 20-21: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE11

Bits 22-23: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE12

Bits 24-25: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE13

Bits 26-27: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE14

Bits 28-29: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE15

Bits 30-31: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT15 rw	OT14 rw	OT13 rw	OT12 rw	OT11 rw	OT10 rw	OT9 rw	OT8 rw	OT7 rw	OT6 rw	OT5 rw	OT4 rw	OT3 rw	OT2 rw	OT1 rw	OT0 rw

Toggle fields

OT0

Bit 0: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT1

Bit 1: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT2

Bit 2: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT3

Bit 3: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT4

Bit 4: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT5

Bit 5: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT6

Bit 6: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT7

Bit 7: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT8

Bit 8: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT9

Bit 9: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT10

Bit 10: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT11

Bit 11: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT12

Bit 12: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT13

Bit 13: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT14

Bit 14: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT15

Bit 15: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x0C000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEED15 rw		OSPEED14 rw		OSPEED13 rw		OSPEED12 rw		OSPEED11 rw		OSPEED10 rw		OSPEED9 rw		OSPEED8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEED7 rw		OSPEED6 rw		OSPEED5 rw		OSPEED4 rw		OSPEED3 rw		OSPEED2 rw		OSPEED1 rw		OSPEED0 rw

Toggle fields

OSPEED0

Bits 0-1: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED1

Bits 2-3: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED2

Bits 4-5: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED3

Bits 6-7: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED4

Bits 8-9: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED5

Bits 10-11: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED6

Bits 12-13: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED7

Bits 14-15: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED8

Bits 16-17: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED9

Bits 18-19: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED10

Bits 20-21: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED11

Bits 22-23: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED12

Bits 24-25: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED13

Bits 26-27: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED14

Bits 28-29: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED15

Bits 30-31: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x24000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPD15 rw		PUPD14 rw		PUPD13 rw		PUPD12 rw		PUPD11 rw		PUPD10 rw		PUPD9 rw		PUPD8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPD7 rw		PUPD6 rw		PUPD5 rw		PUPD4 rw		PUPD3 rw		PUPD2 rw		PUPD1 rw		PUPD0 rw

Toggle fields

PUPD0

Bits 0-1: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD1

Bits 2-3: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD2

Bits 4-5: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD3

Bits 6-7: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD4

Bits 8-9: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD5

Bits 10-11: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD6

Bits 12-13: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD7

Bits 14-15: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD8

Bits 16-17: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD9

Bits 18-19: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD10

Bits 20-21: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD11

Bits 22-23: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD12

Bits 24-25: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD13

Bits 26-27: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD14

Bits 28-29: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD15

Bits 30-31: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID15 r	ID14 r	ID13 r	ID12 r	ID11 r	ID10 r	ID9 r	ID8 r	ID7 r	ID6 r	ID5 r	ID4 r	ID3 r	ID2 r	ID1 r	ID0 r

Toggle fields

ID0

Bit 0: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID1

Bit 1: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID2

Bit 2: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID3

Bit 3: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID4

Bit 4: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID5

Bit 5: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID6

Bit 6: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID7

Bit 7: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID8

Bit 8: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID9

Bit 9: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID10

Bit 10: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID11

Bit 11: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID12

Bit 12: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID13

Bit 13: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID14

Bit 14: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID15

Bit 15: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OD15 rw	OD14 rw	OD13 rw	OD12 rw	OD11 rw	OD10 rw	OD9 rw	OD8 rw	OD7 rw	OD6 rw	OD5 rw	OD4 rw	OD3 rw	OD2 rw	OD1 rw	OD0 rw

Toggle fields

OD0

Bit 0: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD1

Bit 1: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD2

Bit 2: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD3

Bit 3: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD4

Bit 4: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD5

Bit 5: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD6

Bit 6: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD7

Bit 7: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD8

Bit 8: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD9

Bit 9: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD10

Bit 10: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD11

Bit 11: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD12

Bit 12: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD13

Bit 13: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD14

Bit 14: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD15

Bit 15: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS15 w	BS14 w	BS13 w	BS12 w	BS11 w	BS10 w	BS9 w	BS8 w	BS7 w	BS6 w	BS5 w	BS4 w	BS3 w	BS2 w	BS1 w	BS0 w

Toggle fields

BS0

Bit 0: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS1

Bit 1: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS2

Bit 2: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS3

Bit 3: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS4

Bit 4: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS5

Bit 5: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS6

Bit 6: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS7

Bit 7: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS8

Bit 8: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS9

Bit 9: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS10

Bit 10: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS11

Bit 11: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS12

Bit 12: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS13

Bit 13: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS14

Bit 14: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS15

Bit 15: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR0

Bit 16: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR1

Bit 17: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR2

Bit 18: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR3

Bit 19: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR4

Bit 20: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR5

Bit 21: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR6

Bit 22: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR7

Bit 23: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR8

Bit 24: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR9

Bit 25: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR10

Bit 26: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR11

Bit 27: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR12

Bit 28: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR13

Bit 29: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR14

Bit 30: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR15

Bit 31: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK15 rw	LCK14 rw	LCK13 rw	LCK12 rw	LCK11 rw	LCK10 rw	LCK9 rw	LCK8 rw	LCK7 rw	LCK6 rw	LCK5 rw	LCK4 rw	LCK3 rw	LCK2 rw	LCK1 rw	LCK0 rw

Toggle fields

LCK0

Bit 0: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK1

Bit 1: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK2

Bit 2: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK3

Bit 3: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK4

Bit 4: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK5

Bit 5: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK6

Bit 6: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK7

Bit 7: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK8

Bit 8: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK9

Bit 9: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK10

Bit 10: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK11

Bit 11: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK12

Bit 12: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK13

Bit 13: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK14

Bit 14: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK15

Bit 15: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCKK

Bit 16: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset..

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL7 rw				AFSEL6 rw				AFSEL5 rw				AFSEL4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL3 rw				AFSEL2 rw				AFSEL1 rw				AFSEL0 rw

Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFSEL1

Bits 4-7: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFSEL2

Bits 8-11: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFSEL3

Bits 12-15: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFSEL4

Bits 16-19: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFSEL5

Bits 20-23: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFSEL6

Bits 24-27: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFSEL7

Bits 28-31: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL15 rw				AFSEL14 rw				AFSEL13 rw				AFSEL12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL11 rw				AFSEL10 rw				AFSEL9 rw				AFSEL8 rw

Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

AFSEL9

Bits 4-7: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

AFSEL10

Bits 8-11: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

AFSEL11

Bits 12-15: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

AFSEL12

Bits 16-19: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

AFSEL13

Bits 20-23: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

AFSEL14

Bits 24-27: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

AFSEL15

Bits 28-31: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w

Toggle fields

BR0

Bit 0: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR1

Bit 1: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR2

Bit 2: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR3

Bit 3: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR4

Bit 4: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR5

Bit 5: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR6

Bit 6: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR7

Bit 7: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR8

Bit 8: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR9

Bit 9: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR10

Bit 10: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR11

Bit 11: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR12

Bit 12: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR13

Bit 13: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR14

Bit 14: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR15

Bit 15: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

GPIOB

0x50000400: GPIOB address block description

16/177 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	MODER	MODE15		MODE14		MODE13		MODE12		MODE11		MODE10		MODE9		MODE8		MODE7		MODE6		MODE5		MODE4		MODE3		MODE2		MODE1		MODE0
0x4	OTYPER																	OT15	OT14	OT13	OT12	OT11	OT10	OT9	OT8	OT7	OT6	OT5	OT4	OT3	OT2	OT1	OT0
0x8	OSPEEDR	OSPEED15		OSPEED14		OSPEED13		OSPEED12		OSPEED11		OSPEED10		OSPEED9		OSPEED8		OSPEED7		OSPEED6		OSPEED5		OSPEED4		OSPEED3		OSPEED2		OSPEED1		OSPEED0
0xc	PUPDR	PUPD15		PUPD14		PUPD13		PUPD12		PUPD11		PUPD10		PUPD9		PUPD8		PUPD7		PUPD6		PUPD5		PUPD4		PUPD3		PUPD2		PUPD1		PUPD0
0x10	IDR																	ID15	ID14	ID13	ID12	ID11	ID10	ID9	ID8	ID7	ID6	ID5	ID4	ID3	ID2	ID1	ID0
0x14	ODR																	OD15	OD14	OD13	OD12	OD11	OD10	OD9	OD8	OD7	OD6	OD5	OD4	OD3	OD2	OD1	OD0
0x18	BSRR	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0	BS15	BS14	BS13	BS12	BS11	BS10	BS9	BS8	BS7	BS6	BS5	BS4	BS3	BS2	BS1	BS0
0x1c	LCKR																LCKK	LCK15	LCK14	LCK13	LCK12	LCK11	LCK10	LCK9	LCK8	LCK7	LCK6	LCK5	LCK4	LCK3	LCK2	LCK1	LCK0
0x20	AFRL	AFSEL7				AFSEL6				AFSEL5				AFSEL4				AFSEL3				AFSEL2				AFSEL1				AFSEL0
0x24	AFRH	AFSEL15				AFSEL14				AFSEL13				AFSEL12				AFSEL11				AFSEL10				AFSEL9				AFSEL8
0x28	BRR																	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0

Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xEBFFFFFF, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODE15 rw		MODE14 rw		MODE13 rw		MODE12 rw		MODE11 rw		MODE10 rw		MODE9 rw		MODE8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODE7 rw		MODE6 rw		MODE5 rw		MODE4 rw		MODE3 rw		MODE2 rw		MODE1 rw		MODE0 rw

Toggle fields

MODE0

Bits 0-1: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE1

Bits 2-3: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE2

Bits 4-5: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE3

Bits 6-7: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE4

Bits 8-9: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE5

Bits 10-11: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE6

Bits 12-13: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE7

Bits 14-15: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE8

Bits 16-17: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE9

Bits 18-19: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE10

Bits 20-21: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE11

Bits 22-23: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE12

Bits 24-25: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE13

Bits 26-27: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE14

Bits 28-29: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE15

Bits 30-31: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT15 rw	OT14 rw	OT13 rw	OT12 rw	OT11 rw	OT10 rw	OT9 rw	OT8 rw	OT7 rw	OT6 rw	OT5 rw	OT4 rw	OT3 rw	OT2 rw	OT1 rw	OT0 rw

Toggle fields

OT0

Bit 0: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT1

Bit 1: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT2

Bit 2: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT3

Bit 3: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT4

Bit 4: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT5

Bit 5: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT6

Bit 6: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT7

Bit 7: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT8

Bit 8: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT9

Bit 9: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT10

Bit 10: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT11

Bit 11: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT12

Bit 12: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT13

Bit 13: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT14

Bit 14: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT15

Bit 15: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x0C000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEED15 rw		OSPEED14 rw		OSPEED13 rw		OSPEED12 rw		OSPEED11 rw		OSPEED10 rw		OSPEED9 rw		OSPEED8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEED7 rw		OSPEED6 rw		OSPEED5 rw		OSPEED4 rw		OSPEED3 rw		OSPEED2 rw		OSPEED1 rw		OSPEED0 rw

Toggle fields

OSPEED0

Bits 0-1: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED1

Bits 2-3: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED2

Bits 4-5: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED3

Bits 6-7: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED4

Bits 8-9: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED5

Bits 10-11: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED6

Bits 12-13: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED7

Bits 14-15: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED8

Bits 16-17: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED9

Bits 18-19: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED10

Bits 20-21: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED11

Bits 22-23: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED12

Bits 24-25: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED13

Bits 26-27: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED14

Bits 28-29: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED15

Bits 30-31: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x24000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPD15 rw		PUPD14 rw		PUPD13 rw		PUPD12 rw		PUPD11 rw		PUPD10 rw		PUPD9 rw		PUPD8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPD7 rw		PUPD6 rw		PUPD5 rw		PUPD4 rw		PUPD3 rw		PUPD2 rw		PUPD1 rw		PUPD0 rw

Toggle fields

PUPD0

Bits 0-1: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD1

Bits 2-3: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD2

Bits 4-5: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD3

Bits 6-7: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD4

Bits 8-9: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD5

Bits 10-11: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD6

Bits 12-13: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD7

Bits 14-15: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD8

Bits 16-17: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD9

Bits 18-19: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD10

Bits 20-21: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD11

Bits 22-23: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD12

Bits 24-25: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD13

Bits 26-27: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD14

Bits 28-29: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD15

Bits 30-31: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID15 r	ID14 r	ID13 r	ID12 r	ID11 r	ID10 r	ID9 r	ID8 r	ID7 r	ID6 r	ID5 r	ID4 r	ID3 r	ID2 r	ID1 r	ID0 r

Toggle fields

ID0

Bit 0: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID1

Bit 1: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID2

Bit 2: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID3

Bit 3: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID4

Bit 4: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID5

Bit 5: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID6

Bit 6: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID7

Bit 7: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID8

Bit 8: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID9

Bit 9: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID10

Bit 10: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID11

Bit 11: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID12

Bit 12: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID13

Bit 13: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID14

Bit 14: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID15

Bit 15: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OD15 rw	OD14 rw	OD13 rw	OD12 rw	OD11 rw	OD10 rw	OD9 rw	OD8 rw	OD7 rw	OD6 rw	OD5 rw	OD4 rw	OD3 rw	OD2 rw	OD1 rw	OD0 rw

Toggle fields

OD0

Bit 0: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD1

Bit 1: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD2

Bit 2: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD3

Bit 3: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD4

Bit 4: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD5

Bit 5: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD6

Bit 6: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD7

Bit 7: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD8

Bit 8: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD9

Bit 9: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD10

Bit 10: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD11

Bit 11: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD12

Bit 12: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD13

Bit 13: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD14

Bit 14: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD15

Bit 15: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS15 w	BS14 w	BS13 w	BS12 w	BS11 w	BS10 w	BS9 w	BS8 w	BS7 w	BS6 w	BS5 w	BS4 w	BS3 w	BS2 w	BS1 w	BS0 w

Toggle fields

BS0

Bit 0: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS1

Bit 1: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS2

Bit 2: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS3

Bit 3: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS4

Bit 4: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS5

Bit 5: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS6

Bit 6: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS7

Bit 7: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS8

Bit 8: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS9

Bit 9: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS10

Bit 10: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS11

Bit 11: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS12

Bit 12: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS13

Bit 13: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS14

Bit 14: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS15

Bit 15: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR0

Bit 16: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR1

Bit 17: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR2

Bit 18: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR3

Bit 19: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR4

Bit 20: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR5

Bit 21: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR6

Bit 22: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR7

Bit 23: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR8

Bit 24: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR9

Bit 25: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR10

Bit 26: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR11

Bit 27: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR12

Bit 28: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR13

Bit 29: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR14

Bit 30: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR15

Bit 31: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK15 rw	LCK14 rw	LCK13 rw	LCK12 rw	LCK11 rw	LCK10 rw	LCK9 rw	LCK8 rw	LCK7 rw	LCK6 rw	LCK5 rw	LCK4 rw	LCK3 rw	LCK2 rw	LCK1 rw	LCK0 rw

Toggle fields

LCK0

Bit 0: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK1

Bit 1: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK2

Bit 2: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK3

Bit 3: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK4

Bit 4: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK5

Bit 5: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK6

Bit 6: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK7

Bit 7: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK8

Bit 8: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK9

Bit 9: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK10

Bit 10: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK11

Bit 11: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK12

Bit 12: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK13

Bit 13: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK14

Bit 14: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK15

Bit 15: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCKK

Bit 16: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset..

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL7 rw				AFSEL6 rw				AFSEL5 rw				AFSEL4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL3 rw				AFSEL2 rw				AFSEL1 rw				AFSEL0 rw

Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFSEL1

Bits 4-7: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFSEL2

Bits 8-11: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFSEL3

Bits 12-15: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFSEL4

Bits 16-19: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFSEL5

Bits 20-23: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFSEL6

Bits 24-27: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFSEL7

Bits 28-31: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL15 rw				AFSEL14 rw				AFSEL13 rw				AFSEL12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL11 rw				AFSEL10 rw				AFSEL9 rw				AFSEL8 rw

Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

AFSEL9

Bits 4-7: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

AFSEL10

Bits 8-11: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

AFSEL11

Bits 12-15: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

AFSEL12

Bits 16-19: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

AFSEL13

Bits 20-23: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

AFSEL14

Bits 24-27: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

AFSEL15

Bits 28-31: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w

Toggle fields

BR0

Bit 0: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR1

Bit 1: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR2

Bit 2: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR3

Bit 3: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR4

Bit 4: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR5

Bit 5: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR6

Bit 6: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR7

Bit 7: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR8

Bit 8: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR9

Bit 9: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR10

Bit 10: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR11

Bit 11: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR12

Bit 12: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR13

Bit 13: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR14

Bit 14: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR15

Bit 15: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

GPIOC

0x50000800: GPIOC address block description

16/177 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	MODER	MODE15		MODE14		MODE13		MODE12		MODE11		MODE10		MODE9		MODE8		MODE7		MODE6		MODE5		MODE4		MODE3		MODE2		MODE1		MODE0
0x4	OTYPER																	OT15	OT14	OT13	OT12	OT11	OT10	OT9	OT8	OT7	OT6	OT5	OT4	OT3	OT2	OT1	OT0
0x8	OSPEEDR	OSPEED15		OSPEED14		OSPEED13		OSPEED12		OSPEED11		OSPEED10		OSPEED9		OSPEED8		OSPEED7		OSPEED6		OSPEED5		OSPEED4		OSPEED3		OSPEED2		OSPEED1		OSPEED0
0xc	PUPDR	PUPD15		PUPD14		PUPD13		PUPD12		PUPD11		PUPD10		PUPD9		PUPD8		PUPD7		PUPD6		PUPD5		PUPD4		PUPD3		PUPD2		PUPD1		PUPD0
0x10	IDR																	ID15	ID14	ID13	ID12	ID11	ID10	ID9	ID8	ID7	ID6	ID5	ID4	ID3	ID2	ID1	ID0
0x14	ODR																	OD15	OD14	OD13	OD12	OD11	OD10	OD9	OD8	OD7	OD6	OD5	OD4	OD3	OD2	OD1	OD0
0x18	BSRR	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0	BS15	BS14	BS13	BS12	BS11	BS10	BS9	BS8	BS7	BS6	BS5	BS4	BS3	BS2	BS1	BS0
0x1c	LCKR																LCKK	LCK15	LCK14	LCK13	LCK12	LCK11	LCK10	LCK9	LCK8	LCK7	LCK6	LCK5	LCK4	LCK3	LCK2	LCK1	LCK0
0x20	AFRL	AFSEL7				AFSEL6				AFSEL5				AFSEL4				AFSEL3				AFSEL2				AFSEL1				AFSEL0
0x24	AFRH	AFSEL15				AFSEL14				AFSEL13				AFSEL12				AFSEL11				AFSEL10				AFSEL9				AFSEL8
0x28	BRR																	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0

Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xEBFFFFFF, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODE15 rw		MODE14 rw		MODE13 rw		MODE12 rw		MODE11 rw		MODE10 rw		MODE9 rw		MODE8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODE7 rw		MODE6 rw		MODE5 rw		MODE4 rw		MODE3 rw		MODE2 rw		MODE1 rw		MODE0 rw

Toggle fields

MODE0

Bits 0-1: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE1

Bits 2-3: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE2

Bits 4-5: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE3

Bits 6-7: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE4

Bits 8-9: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE5

Bits 10-11: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE6

Bits 12-13: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE7

Bits 14-15: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE8

Bits 16-17: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE9

Bits 18-19: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE10

Bits 20-21: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE11

Bits 22-23: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE12

Bits 24-25: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE13

Bits 26-27: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE14

Bits 28-29: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE15

Bits 30-31: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT15 rw	OT14 rw	OT13 rw	OT12 rw	OT11 rw	OT10 rw	OT9 rw	OT8 rw	OT7 rw	OT6 rw	OT5 rw	OT4 rw	OT3 rw	OT2 rw	OT1 rw	OT0 rw

Toggle fields

OT0

Bit 0: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT1

Bit 1: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT2

Bit 2: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT3

Bit 3: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT4

Bit 4: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT5

Bit 5: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT6

Bit 6: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT7

Bit 7: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT8

Bit 8: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT9

Bit 9: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT10

Bit 10: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT11

Bit 11: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT12

Bit 12: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT13

Bit 13: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT14

Bit 14: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT15

Bit 15: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x0C000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEED15 rw		OSPEED14 rw		OSPEED13 rw		OSPEED12 rw		OSPEED11 rw		OSPEED10 rw		OSPEED9 rw		OSPEED8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEED7 rw		OSPEED6 rw		OSPEED5 rw		OSPEED4 rw		OSPEED3 rw		OSPEED2 rw		OSPEED1 rw		OSPEED0 rw

Toggle fields

OSPEED0

Bits 0-1: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED1

Bits 2-3: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED2

Bits 4-5: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED3

Bits 6-7: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED4

Bits 8-9: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED5

Bits 10-11: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED6

Bits 12-13: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED7

Bits 14-15: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED8

Bits 16-17: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED9

Bits 18-19: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED10

Bits 20-21: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED11

Bits 22-23: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED12

Bits 24-25: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED13

Bits 26-27: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED14

Bits 28-29: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED15

Bits 30-31: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x24000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPD15 rw		PUPD14 rw		PUPD13 rw		PUPD12 rw		PUPD11 rw		PUPD10 rw		PUPD9 rw		PUPD8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPD7 rw		PUPD6 rw		PUPD5 rw		PUPD4 rw		PUPD3 rw		PUPD2 rw		PUPD1 rw		PUPD0 rw

Toggle fields

PUPD0

Bits 0-1: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD1

Bits 2-3: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD2

Bits 4-5: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD3

Bits 6-7: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD4

Bits 8-9: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD5

Bits 10-11: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD6

Bits 12-13: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD7

Bits 14-15: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD8

Bits 16-17: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD9

Bits 18-19: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD10

Bits 20-21: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD11

Bits 22-23: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD12

Bits 24-25: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD13

Bits 26-27: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD14

Bits 28-29: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD15

Bits 30-31: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID15 r	ID14 r	ID13 r	ID12 r	ID11 r	ID10 r	ID9 r	ID8 r	ID7 r	ID6 r	ID5 r	ID4 r	ID3 r	ID2 r	ID1 r	ID0 r

Toggle fields

ID0

Bit 0: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID1

Bit 1: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID2

Bit 2: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID3

Bit 3: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID4

Bit 4: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID5

Bit 5: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID6

Bit 6: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID7

Bit 7: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID8

Bit 8: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID9

Bit 9: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID10

Bit 10: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID11

Bit 11: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID12

Bit 12: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID13

Bit 13: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID14

Bit 14: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID15

Bit 15: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OD15 rw	OD14 rw	OD13 rw	OD12 rw	OD11 rw	OD10 rw	OD9 rw	OD8 rw	OD7 rw	OD6 rw	OD5 rw	OD4 rw	OD3 rw	OD2 rw	OD1 rw	OD0 rw

Toggle fields

OD0

Bit 0: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD1

Bit 1: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD2

Bit 2: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD3

Bit 3: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD4

Bit 4: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD5

Bit 5: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD6

Bit 6: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD7

Bit 7: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD8

Bit 8: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD9

Bit 9: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD10

Bit 10: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD11

Bit 11: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD12

Bit 12: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD13

Bit 13: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD14

Bit 14: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD15

Bit 15: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS15 w	BS14 w	BS13 w	BS12 w	BS11 w	BS10 w	BS9 w	BS8 w	BS7 w	BS6 w	BS5 w	BS4 w	BS3 w	BS2 w	BS1 w	BS0 w

Toggle fields

BS0

Bit 0: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS1

Bit 1: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS2

Bit 2: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS3

Bit 3: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS4

Bit 4: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS5

Bit 5: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS6

Bit 6: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS7

Bit 7: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS8

Bit 8: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS9

Bit 9: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS10

Bit 10: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS11

Bit 11: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS12

Bit 12: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS13

Bit 13: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS14

Bit 14: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS15

Bit 15: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR0

Bit 16: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR1

Bit 17: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR2

Bit 18: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR3

Bit 19: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR4

Bit 20: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR5

Bit 21: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR6

Bit 22: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR7

Bit 23: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR8

Bit 24: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR9

Bit 25: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR10

Bit 26: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR11

Bit 27: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR12

Bit 28: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR13

Bit 29: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR14

Bit 30: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR15

Bit 31: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK15 rw	LCK14 rw	LCK13 rw	LCK12 rw	LCK11 rw	LCK10 rw	LCK9 rw	LCK8 rw	LCK7 rw	LCK6 rw	LCK5 rw	LCK4 rw	LCK3 rw	LCK2 rw	LCK1 rw	LCK0 rw

Toggle fields

LCK0

Bit 0: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK1

Bit 1: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK2

Bit 2: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK3

Bit 3: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK4

Bit 4: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK5

Bit 5: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK6

Bit 6: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK7

Bit 7: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK8

Bit 8: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK9

Bit 9: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK10

Bit 10: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK11

Bit 11: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK12

Bit 12: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK13

Bit 13: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK14

Bit 14: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK15

Bit 15: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCKK

Bit 16: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset..

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL7 rw				AFSEL6 rw				AFSEL5 rw				AFSEL4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL3 rw				AFSEL2 rw				AFSEL1 rw				AFSEL0 rw

Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFSEL1

Bits 4-7: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFSEL2

Bits 8-11: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFSEL3

Bits 12-15: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFSEL4

Bits 16-19: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFSEL5

Bits 20-23: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFSEL6

Bits 24-27: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFSEL7

Bits 28-31: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL15 rw				AFSEL14 rw				AFSEL13 rw				AFSEL12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL11 rw				AFSEL10 rw				AFSEL9 rw				AFSEL8 rw

Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

AFSEL9

Bits 4-7: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

AFSEL10

Bits 8-11: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

AFSEL11

Bits 12-15: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

AFSEL12

Bits 16-19: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

AFSEL13

Bits 20-23: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

AFSEL14

Bits 24-27: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

AFSEL15

Bits 28-31: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w

Toggle fields

BR0

Bit 0: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR1

Bit 1: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR2

Bit 2: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR3

Bit 3: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR4

Bit 4: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR5

Bit 5: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR6

Bit 6: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR7

Bit 7: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR8

Bit 8: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR9

Bit 9: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR10

Bit 10: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR11

Bit 11: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR12

Bit 12: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR13

Bit 13: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR14

Bit 14: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR15

Bit 15: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

GPIOD

0x50000c00: GPIOD address block description

16/177 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	MODER	MODE15		MODE14		MODE13		MODE12		MODE11		MODE10		MODE9		MODE8		MODE7		MODE6		MODE5		MODE4		MODE3		MODE2		MODE1		MODE0
0x4	OTYPER																	OT15	OT14	OT13	OT12	OT11	OT10	OT9	OT8	OT7	OT6	OT5	OT4	OT3	OT2	OT1	OT0
0x8	OSPEEDR	OSPEED15		OSPEED14		OSPEED13		OSPEED12		OSPEED11		OSPEED10		OSPEED9		OSPEED8		OSPEED7		OSPEED6		OSPEED5		OSPEED4		OSPEED3		OSPEED2		OSPEED1		OSPEED0
0xc	PUPDR	PUPD15		PUPD14		PUPD13		PUPD12		PUPD11		PUPD10		PUPD9		PUPD8		PUPD7		PUPD6		PUPD5		PUPD4		PUPD3		PUPD2		PUPD1		PUPD0
0x10	IDR																	ID15	ID14	ID13	ID12	ID11	ID10	ID9	ID8	ID7	ID6	ID5	ID4	ID3	ID2	ID1	ID0
0x14	ODR																	OD15	OD14	OD13	OD12	OD11	OD10	OD9	OD8	OD7	OD6	OD5	OD4	OD3	OD2	OD1	OD0
0x18	BSRR	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0	BS15	BS14	BS13	BS12	BS11	BS10	BS9	BS8	BS7	BS6	BS5	BS4	BS3	BS2	BS1	BS0
0x1c	LCKR																LCKK	LCK15	LCK14	LCK13	LCK12	LCK11	LCK10	LCK9	LCK8	LCK7	LCK6	LCK5	LCK4	LCK3	LCK2	LCK1	LCK0
0x20	AFRL	AFSEL7				AFSEL6				AFSEL5				AFSEL4				AFSEL3				AFSEL2				AFSEL1				AFSEL0
0x24	AFRH	AFSEL15				AFSEL14				AFSEL13				AFSEL12				AFSEL11				AFSEL10				AFSEL9				AFSEL8
0x28	BRR																	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0

Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xEBFFFFFF, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODE15 rw		MODE14 rw		MODE13 rw		MODE12 rw		MODE11 rw		MODE10 rw		MODE9 rw		MODE8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODE7 rw		MODE6 rw		MODE5 rw		MODE4 rw		MODE3 rw		MODE2 rw		MODE1 rw		MODE0 rw

Toggle fields

MODE0

Bits 0-1: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE1

Bits 2-3: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE2

Bits 4-5: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE3

Bits 6-7: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE4

Bits 8-9: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE5

Bits 10-11: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE6

Bits 12-13: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE7

Bits 14-15: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE8

Bits 16-17: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE9

Bits 18-19: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE10

Bits 20-21: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE11

Bits 22-23: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE12

Bits 24-25: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE13

Bits 26-27: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE14

Bits 28-29: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE15

Bits 30-31: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT15 rw	OT14 rw	OT13 rw	OT12 rw	OT11 rw	OT10 rw	OT9 rw	OT8 rw	OT7 rw	OT6 rw	OT5 rw	OT4 rw	OT3 rw	OT2 rw	OT1 rw	OT0 rw

Toggle fields

OT0

Bit 0: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT1

Bit 1: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT2

Bit 2: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT3

Bit 3: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT4

Bit 4: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT5

Bit 5: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT6

Bit 6: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT7

Bit 7: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT8

Bit 8: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT9

Bit 9: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT10

Bit 10: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT11

Bit 11: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT12

Bit 12: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT13

Bit 13: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT14

Bit 14: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT15

Bit 15: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x0C000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEED15 rw		OSPEED14 rw		OSPEED13 rw		OSPEED12 rw		OSPEED11 rw		OSPEED10 rw		OSPEED9 rw		OSPEED8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEED7 rw		OSPEED6 rw		OSPEED5 rw		OSPEED4 rw		OSPEED3 rw		OSPEED2 rw		OSPEED1 rw		OSPEED0 rw

Toggle fields

OSPEED0

Bits 0-1: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED1

Bits 2-3: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED2

Bits 4-5: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED3

Bits 6-7: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED4

Bits 8-9: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED5

Bits 10-11: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED6

Bits 12-13: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED7

Bits 14-15: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED8

Bits 16-17: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED9

Bits 18-19: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED10

Bits 20-21: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED11

Bits 22-23: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED12

Bits 24-25: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED13

Bits 26-27: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED14

Bits 28-29: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED15

Bits 30-31: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x24000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPD15 rw		PUPD14 rw		PUPD13 rw		PUPD12 rw		PUPD11 rw		PUPD10 rw		PUPD9 rw		PUPD8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPD7 rw		PUPD6 rw		PUPD5 rw		PUPD4 rw		PUPD3 rw		PUPD2 rw		PUPD1 rw		PUPD0 rw

Toggle fields

PUPD0

Bits 0-1: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD1

Bits 2-3: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD2

Bits 4-5: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD3

Bits 6-7: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD4

Bits 8-9: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD5

Bits 10-11: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD6

Bits 12-13: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD7

Bits 14-15: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD8

Bits 16-17: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD9

Bits 18-19: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD10

Bits 20-21: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD11

Bits 22-23: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD12

Bits 24-25: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD13

Bits 26-27: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD14

Bits 28-29: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD15

Bits 30-31: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID15 r	ID14 r	ID13 r	ID12 r	ID11 r	ID10 r	ID9 r	ID8 r	ID7 r	ID6 r	ID5 r	ID4 r	ID3 r	ID2 r	ID1 r	ID0 r

Toggle fields

ID0

Bit 0: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID1

Bit 1: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID2

Bit 2: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID3

Bit 3: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID4

Bit 4: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID5

Bit 5: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID6

Bit 6: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID7

Bit 7: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID8

Bit 8: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID9

Bit 9: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID10

Bit 10: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID11

Bit 11: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID12

Bit 12: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID13

Bit 13: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID14

Bit 14: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID15

Bit 15: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OD15 rw	OD14 rw	OD13 rw	OD12 rw	OD11 rw	OD10 rw	OD9 rw	OD8 rw	OD7 rw	OD6 rw	OD5 rw	OD4 rw	OD3 rw	OD2 rw	OD1 rw	OD0 rw

Toggle fields

OD0

Bit 0: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD1

Bit 1: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD2

Bit 2: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD3

Bit 3: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD4

Bit 4: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD5

Bit 5: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD6

Bit 6: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD7

Bit 7: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD8

Bit 8: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD9

Bit 9: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD10

Bit 10: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD11

Bit 11: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD12

Bit 12: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD13

Bit 13: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD14

Bit 14: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD15

Bit 15: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS15 w	BS14 w	BS13 w	BS12 w	BS11 w	BS10 w	BS9 w	BS8 w	BS7 w	BS6 w	BS5 w	BS4 w	BS3 w	BS2 w	BS1 w	BS0 w

Toggle fields

BS0

Bit 0: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS1

Bit 1: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS2

Bit 2: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS3

Bit 3: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS4

Bit 4: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS5

Bit 5: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS6

Bit 6: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS7

Bit 7: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS8

Bit 8: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS9

Bit 9: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS10

Bit 10: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS11

Bit 11: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS12

Bit 12: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS13

Bit 13: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS14

Bit 14: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS15

Bit 15: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR0

Bit 16: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR1

Bit 17: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR2

Bit 18: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR3

Bit 19: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR4

Bit 20: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR5

Bit 21: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR6

Bit 22: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR7

Bit 23: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR8

Bit 24: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR9

Bit 25: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR10

Bit 26: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR11

Bit 27: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR12

Bit 28: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR13

Bit 29: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR14

Bit 30: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR15

Bit 31: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK15 rw	LCK14 rw	LCK13 rw	LCK12 rw	LCK11 rw	LCK10 rw	LCK9 rw	LCK8 rw	LCK7 rw	LCK6 rw	LCK5 rw	LCK4 rw	LCK3 rw	LCK2 rw	LCK1 rw	LCK0 rw

Toggle fields

LCK0

Bit 0: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK1

Bit 1: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK2

Bit 2: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK3

Bit 3: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK4

Bit 4: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK5

Bit 5: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK6

Bit 6: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK7

Bit 7: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK8

Bit 8: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK9

Bit 9: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK10

Bit 10: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK11

Bit 11: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK12

Bit 12: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK13

Bit 13: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK14

Bit 14: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK15

Bit 15: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCKK

Bit 16: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset..

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL7 rw				AFSEL6 rw				AFSEL5 rw				AFSEL4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL3 rw				AFSEL2 rw				AFSEL1 rw				AFSEL0 rw

Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFSEL1

Bits 4-7: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFSEL2

Bits 8-11: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFSEL3

Bits 12-15: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFSEL4

Bits 16-19: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFSEL5

Bits 20-23: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFSEL6

Bits 24-27: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFSEL7

Bits 28-31: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL15 rw				AFSEL14 rw				AFSEL13 rw				AFSEL12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL11 rw				AFSEL10 rw				AFSEL9 rw				AFSEL8 rw

Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

AFSEL9

Bits 4-7: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

AFSEL10

Bits 8-11: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

AFSEL11

Bits 12-15: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

AFSEL12

Bits 16-19: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

AFSEL13

Bits 20-23: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

AFSEL14

Bits 24-27: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

AFSEL15

Bits 28-31: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w

Toggle fields

BR0

Bit 0: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR1

Bit 1: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR2

Bit 2: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR3

Bit 3: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR4

Bit 4: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR5

Bit 5: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR6

Bit 6: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR7

Bit 7: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR8

Bit 8: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR9

Bit 9: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR10

Bit 10: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR11

Bit 11: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR12

Bit 12: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR13

Bit 13: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR14

Bit 14: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR15

Bit 15: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

GPIOF

0x50001400: GPIOF address block description

16/177 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	MODER	MODE15		MODE14		MODE13		MODE12		MODE11		MODE10		MODE9		MODE8		MODE7		MODE6		MODE5		MODE4		MODE3		MODE2		MODE1		MODE0
0x4	OTYPER																	OT15	OT14	OT13	OT12	OT11	OT10	OT9	OT8	OT7	OT6	OT5	OT4	OT3	OT2	OT1	OT0
0x8	OSPEEDR	OSPEED15		OSPEED14		OSPEED13		OSPEED12		OSPEED11		OSPEED10		OSPEED9		OSPEED8		OSPEED7		OSPEED6		OSPEED5		OSPEED4		OSPEED3		OSPEED2		OSPEED1		OSPEED0
0xc	PUPDR	PUPD15		PUPD14		PUPD13		PUPD12		PUPD11		PUPD10		PUPD9		PUPD8		PUPD7		PUPD6		PUPD5		PUPD4		PUPD3		PUPD2		PUPD1		PUPD0
0x10	IDR																	ID15	ID14	ID13	ID12	ID11	ID10	ID9	ID8	ID7	ID6	ID5	ID4	ID3	ID2	ID1	ID0
0x14	ODR																	OD15	OD14	OD13	OD12	OD11	OD10	OD9	OD8	OD7	OD6	OD5	OD4	OD3	OD2	OD1	OD0
0x18	BSRR	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0	BS15	BS14	BS13	BS12	BS11	BS10	BS9	BS8	BS7	BS6	BS5	BS4	BS3	BS2	BS1	BS0
0x1c	LCKR																LCKK	LCK15	LCK14	LCK13	LCK12	LCK11	LCK10	LCK9	LCK8	LCK7	LCK6	LCK5	LCK4	LCK3	LCK2	LCK1	LCK0
0x20	AFRL	AFSEL7				AFSEL6				AFSEL5				AFSEL4				AFSEL3				AFSEL2				AFSEL1				AFSEL0
0x24	AFRH	AFSEL15				AFSEL14				AFSEL13				AFSEL12				AFSEL11				AFSEL10				AFSEL9				AFSEL8
0x28	BRR																	BR15	BR14	BR13	BR12	BR11	BR10	BR9	BR8	BR7	BR6	BR5	BR4	BR3	BR2	BR1	BR0

Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xEBFFFFFF, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODE15 rw		MODE14 rw		MODE13 rw		MODE12 rw		MODE11 rw		MODE10 rw		MODE9 rw		MODE8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODE7 rw		MODE6 rw		MODE5 rw		MODE4 rw		MODE3 rw		MODE2 rw		MODE1 rw		MODE0 rw

Toggle fields

MODE0

Bits 0-1: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE1

Bits 2-3: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE2

Bits 4-5: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE3

Bits 6-7: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE4

Bits 8-9: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE5

Bits 10-11: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE6

Bits 12-13: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE7

Bits 14-15: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE8

Bits 16-17: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE9

Bits 18-19: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE10

Bits 20-21: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE11

Bits 22-23: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE12

Bits 24-25: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE13

Bits 26-27: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE14

Bits 28-29: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

MODE15

Bits 30-31: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to set the I/O to one of four operating modes..

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT15 rw	OT14 rw	OT13 rw	OT12 rw	OT11 rw	OT10 rw	OT9 rw	OT8 rw	OT7 rw	OT6 rw	OT5 rw	OT4 rw	OT3 rw	OT2 rw	OT1 rw	OT0 rw

Toggle fields

OT0

Bit 0: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT1

Bit 1: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT2

Bit 2: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT3

Bit 3: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT4

Bit 4: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT5

Bit 5: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT6

Bit 6: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT7

Bit 7: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT8

Bit 8: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT9

Bit 9: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT10

Bit 10: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT11

Bit 11: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT12

Bit 12: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT13

Bit 13: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT14

Bit 14: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OT15

Bit 15: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output type..

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x0C000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEED15 rw		OSPEED14 rw		OSPEED13 rw		OSPEED12 rw		OSPEED11 rw		OSPEED10 rw		OSPEED9 rw		OSPEED8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEED7 rw		OSPEED6 rw		OSPEED5 rw		OSPEED4 rw		OSPEED3 rw		OSPEED2 rw		OSPEED1 rw		OSPEED0 rw

Toggle fields

OSPEED0

Bits 0-1: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED1

Bits 2-3: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED2

Bits 4-5: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED3

Bits 6-7: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED4

Bits 8-9: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED5

Bits 10-11: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED6

Bits 12-13: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED7

Bits 14-15: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED8

Bits 16-17: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED9

Bits 18-19: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED10

Bits 20-21: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED11

Bits 22-23: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED12

Bits 24-25: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED13

Bits 26-27: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED14

Bits 28-29: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

OSPEED15

Bits 30-31: Port x configuration for I/O y (y = 15 to 0) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.. The FT_c GPIOs cannot be set to high speed..

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x24000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPD15 rw		PUPD14 rw		PUPD13 rw		PUPD12 rw		PUPD11 rw		PUPD10 rw		PUPD9 rw		PUPD8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPD7 rw		PUPD6 rw		PUPD5 rw		PUPD4 rw		PUPD3 rw		PUPD2 rw		PUPD1 rw		PUPD0 rw

Toggle fields

PUPD0

Bits 0-1: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD1

Bits 2-3: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD2

Bits 4-5: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD3

Bits 6-7: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD4

Bits 8-9: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD5

Bits 10-11: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD6

Bits 12-13: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD7

Bits 14-15: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD8

Bits 16-17: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD9

Bits 18-19: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD10

Bits 20-21: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD11

Bits 22-23: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD12

Bits 24-25: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD13

Bits 26-27: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD14

Bits 28-29: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

PUPD15

Bits 30-31: Port x configuration I/O y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down.

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID15 r	ID14 r	ID13 r	ID12 r	ID11 r	ID10 r	ID9 r	ID8 r	ID7 r	ID6 r	ID5 r	ID4 r	ID3 r	ID2 r	ID1 r	ID0 r

Toggle fields

ID0

Bit 0: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID1

Bit 1: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID2

Bit 2: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID3

Bit 3: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID4

Bit 4: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID5

Bit 5: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID6

Bit 6: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID7

Bit 7: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID8

Bit 8: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID9

Bit 9: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID10

Bit 10: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID11

Bit 11: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID12

Bit 12: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID13

Bit 13: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID14

Bit 14: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ID15

Bit 15: Port x input data I/O y (y = 15 to 0) These bits are read-only. They contain the input value of the corresponding I/O port..

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OD15 rw	OD14 rw	OD13 rw	OD12 rw	OD11 rw	OD10 rw	OD9 rw	OD8 rw	OD7 rw	OD6 rw	OD5 rw	OD4 rw	OD3 rw	OD2 rw	OD1 rw	OD0 rw

Toggle fields

OD0

Bit 0: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD1

Bit 1: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD2

Bit 2: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD3

Bit 3: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD4

Bit 4: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD5

Bit 5: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD6

Bit 6: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD7

Bit 7: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD8

Bit 8: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD9

Bit 9: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD10

Bit 10: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD11

Bit 11: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD12

Bit 12: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD13

Bit 13: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD14

Bit 14: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

OD15

Bit 15: Port output data I/O y (y = 15 to 0) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR register (x = A, B, C, D, F)..

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS15 w	BS14 w	BS13 w	BS12 w	BS11 w	BS10 w	BS9 w	BS8 w	BS7 w	BS6 w	BS5 w	BS4 w	BS3 w	BS2 w	BS1 w	BS0 w

Toggle fields

BS0

Bit 0: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS1

Bit 1: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS2

Bit 2: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS3

Bit 3: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS4

Bit 4: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS5

Bit 5: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS6

Bit 6: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS7

Bit 7: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS8

Bit 8: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS9

Bit 9: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS10

Bit 10: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS11

Bit 11: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS12

Bit 12: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS13

Bit 13: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS14

Bit 14: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BS15

Bit 15: Port x set I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR0

Bit 16: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR1

Bit 17: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR2

Bit 18: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR3

Bit 19: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR4

Bit 20: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR5

Bit 21: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR6

Bit 22: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR7

Bit 23: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR8

Bit 24: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR9

Bit 25: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR10

Bit 26: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR11

Bit 27: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR12

Bit 28: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR13

Bit 29: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR14

Bit 30: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

BR15

Bit 31: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000. Note: If both BSx and BRx are set, BSx has priority..

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK15 rw	LCK14 rw	LCK13 rw	LCK12 rw	LCK11 rw	LCK10 rw	LCK9 rw	LCK8 rw	LCK7 rw	LCK6 rw	LCK5 rw	LCK4 rw	LCK3 rw	LCK2 rw	LCK1 rw	LCK0 rw

Toggle fields

LCK0

Bit 0: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK1

Bit 1: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK2

Bit 2: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK3

Bit 3: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK4

Bit 4: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK5

Bit 5: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK6

Bit 6: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK7

Bit 7: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK8

Bit 8: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK9

Bit 9: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK10

Bit 10: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK11

Bit 11: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK12

Bit 12: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK13

Bit 13: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK14

Bit 14: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCK15

Bit 15: Port x lock I/O pin y (y = 15 to 0) These bits are read/write but can only be written when the LCKK bit is 0..

LCKK

Bit 16: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset..

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL7 rw				AFSEL6 rw				AFSEL5 rw				AFSEL4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL3 rw				AFSEL2 rw				AFSEL1 rw				AFSEL0 rw

Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFSEL1

Bits 4-7: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFSEL2

Bits 8-11: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFSEL3

Bits 12-15: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFSEL4

Bits 16-19: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFSEL5

Bits 20-23: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFSEL6

Bits 24-27: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFSEL7

Bits 28-31: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os.

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL15 rw				AFSEL14 rw				AFSEL13 rw				AFSEL12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL11 rw				AFSEL10 rw				AFSEL9 rw				AFSEL8 rw

Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

AFSEL9

Bits 4-7: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

AFSEL10

Bits 8-11: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

AFSEL11

Bits 12-15: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

AFSEL12

Bits 16-19: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

AFSEL13

Bits 20-23: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

AFSEL14

Bits 24-27: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

AFSEL15

Bits 28-31: Alternate function selection for port x, I/O y (y = 8 to 15) These bits are written by software to configure alternate function I/Os.

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w

Toggle fields

BR0

Bit 0: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR1

Bit 1: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR2

Bit 2: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR3

Bit 3: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR4

Bit 4: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR5

Bit 5: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR6

Bit 6: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR7

Bit 7: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR8

Bit 8: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR9

Bit 9: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR10

Bit 10: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR11

Bit 11: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR12

Bit 12: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR13

Bit 13: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR14

Bit 14: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

BR15

Bit 15: Port x reset I/O y (y = 15 to 0) These bits are write-only. A read operation always returns 0x0000..

I2C1

0x40005400: I2C register block

17/76 fields covered.

Toggle register map

Offset	Name	31	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1						PECEN	ALERTEN	SMBDEN	SMBHEN	GCEN	WUPEN	NOSTRETCH	SBC	RXDMAEN	TXDMAEN		ANFOFF	DNF				ERRIE	TCIE	STOPIE	NACKIE	ADDRIE	RXIE	TXIE	PE
0x4	CR2			PECBYTE	AUTOEND	RELOAD	NBYTES								NACK	STOP	START	HEAD10R	ADD10	RD_WRN	SADD
0x8	OAR1														OA1EN					OA1MODE	OA1
0xc	OAR2														OA2EN					OA2MSK			OA2
0x10	TIMINGR	PRESC					SCLDEL				SDADEL				SCLH								SCLL
0x14	TIMEOUTR	TEXTEN	TIMEOUTB												TIMOUTEN			TIDLE	TIMEOUTA
0x18	ISR						ADDCODE							DIR	BUSY		ALERT	TIMEOUT	PECERR	OVR	ARLO	BERR	TCR	TC	STOPF	NACKF	ADDR	RXNE	TXIS	TXE
0x1c	ICR																ALERTCF	TIMOUTCF	PECCF	OVRCF	ARLOCF	BERRCF			STOPCF	NACKCF	ADDRCF
0x20	PECR																						PEC
0x24	RXDR																						RXDATA
0x28	TXDR																						TXDATA

Toggle registers

CR1

I2C control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PECEN rw	ALERTEN rw	SMBDEN rw	SMBHEN rw	GCEN rw	WUPEN rw	NOSTRETCH rw	SBC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXDMAEN rw	TXDMAEN rw		ANFOFF rw	DNF rw				ERRIE rw	TCIE rw	STOPIE rw	NACKIE rw	ADDRIE rw	RXIE rw	TXIE rw	PE rw

Toggle fields

PE

Bit 0: Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles..

TXIE

Bit 1: TX Interrupt enable.

RXIE

Bit 2: RX Interrupt enable.

ADDRIE

Bit 3: Address match Interrupt enable (slave only).

NACKIE

Bit 4: Not acknowledge received Interrupt enable.

STOPIE

Bit 5: Stop detection Interrupt enable.

TCIE

Bit 6: Transfer Complete interrupt enable Note: Any of these events generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR).

ERRIE

Bit 7: Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT).

DNF

Bits 8-11: Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * tI2CCLK ... Note: If the analog filter is also enabled, the digital filter is added to the analog filter. This filter can only be programmed when the I2C is disabled (PE = 0)..

ANFOFF

Bit 12: Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0)..

TXDMAEN

Bit 14: DMA transmission requests enable.

RXDMAEN

Bit 15: DMA reception requests enable.

SBC

Bit 16: Slave byte control This bit is used to enable hardware byte control in slave mode..

NOSTRETCH

Bit 17: Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0)..

WUPEN

Bit 18: Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to 0. Refer to . Note: WUPEN can be set only when DNF = 0000.

GCEN

Bit 19: General call enable.

SMBHEN

Bit 20: SMBus host address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to ..

SMBDEN

Bit 21: SMBus device default address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to ..

ALERTEN

Bit 22: SMBus alert enable Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to ..

PECEN

Bit 23: PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to ..

CR2

I2C control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					PECBYTE rw	AUTOEND rw	RELOAD rw	NBYTES rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NACK rw	STOP rw	START rw	HEAD10R rw	ADD10 rw	RD_WRN rw	SADD rw

Toggle fields

SADD

Bits 0-9: Slave address (master mode) In 7-bit addressing mode (ADD10 = 0): SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9], SADD[8] and SADD[0] are don't care. In 10-bit addressing mode (ADD10 = 1): SADD[9:0] should be written with the 10-bit slave address to be sent. Note: Changing these bits when the START bit is set is not allowed..

RD_WRN

Bit 10: Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed..

ADD10

Bit 11: 10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed..

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed..

START

Bit 13: Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by an address matched in slave mode, by a timeout error detection, or when PE = 0. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit generates a START condition once the bus is free. Note: Writing 0 to this bit has no effect. The START bit can be set even if the bus is BUSY or I2C is in slave mode. This bit has no effect when RELOAD is set..

STOP

Bit 14: Stop generation (master mode) The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. In Master Mode: Note: Writing 0 to this bit has no effect..

NACK

Bit 15: NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. Note: Writing 0 to this bit has no effect. This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value..

NBYTES

Bits 16-23: Number of bytes The number of bytes to be transmitted/received is programmed there. This field is dont care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed..

RELOAD

Bit 24: NBYTES reload mode This bit is set and cleared by software..

AUTOEND

Bit 25: Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set..

PECBYTE

Bit 26: Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. Note: Writing 0 to this bit has no effect. This bit has no effect when RELOAD is set. This bit has no effect is slave mode when SBC=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to ..

OAR1

I2C own address 1 register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA1EN rw					OA1MODE rw	OA1 rw

Toggle fields

OA1

Bits 0-9: Interface own slave address 7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. The bits OA1[9], OA1[8] and OA1[0] are don't care. 10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address. Note: These bits can be written only when OA1EN=0..

OA1MODE

Bit 10: Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0..

OA1EN

Bit 15: Own Address 1 enable.

OAR2

I2C own address 2 register

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA2EN rw					OA2MSK rw			OA2 rw

Toggle fields

OA2

Bits 1-7: Interface address 7-bit addressing mode: 7-bit address Note: These bits can be written only when OA2EN=0..

OA2MSK

Bits 8-10: Own Address 2 masks Note: These bits can be written only when OA2EN=0. As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches..

OA2EN

Bit 15: Own Address 2 enable.

TIMINGR

I2C timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRESC rw								SCLDEL rw				SDADEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SCLH rw								SCLL rw

Toggle fields

SCLL

Bits 0-7: SCL low period (master mode) This field is used to generate the SCL low period in master mode. tSCLL = (SCLL+1) x tPRESC Note: SCLL is also used to generate tBUF and tSU:STA timings..

SCLH

Bits 8-15: SCL high period (master mode) This field is used to generate the SCL high period in master mode. tSCLH = (SCLH+1) x tPRESC Note: SCLH is also used to generate tSU:STO and tHD:STA timing..

SDADEL

Bits 16-19: Data hold time This field is used to generate the delay tSDADEL between SCL falling edge and SDA edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSDADEL. tSDADEL= SDADEL x tPRESC Note: SDADEL is used to generate tHD:DAT timing..

SCLDEL

Bits 20-23: Data setup time This field is used to generate a delay tSCLDEL between SDA edge and SCL rising edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSCLDEL. tSCLDEL = (SCLDEL+1) x tPRESC Note: tSCLDEL is used to generate tSU:DAT timing..

PRESC

Bits 28-31: Timing prescaler This field is used to prescale I2CCLK in order to generate the clock period tPRESC used for data setup and hold counters (refer to ) and for SCL high and low level counters (refer to ). tPRESC = (PRESC+1) x tI2CCLK.

TIMEOUTR

I2C timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TEXTEN rw				TIMEOUTB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIMOUTEN rw			TIDLE rw	TIMEOUTA rw

Toggle fields

TIMEOUTA

Bits 0-11: Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0..

TIDLE

Bit 12: Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0..

TIMOUTEN

Bit 15: Clock timeout enable.

TIMEOUTB

Bits 16-27: Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0..

TEXTEN

Bit 31: Extended clock timeout enable.

ISR

I2C interrupt and status register

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								ADDCODE r							DIR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BUSY r		ALERT r	TIMEOUT r	PECERR r	OVR r	ARLO r	BERR r	TCR r	TC r	STOPF r	NACKF r	ADDR r	RXNE r	TXIS rw	TXE rw

Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters) This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software in order to flush the transmit data register I2C_TXDR. Note: This bit is set by hardware when PE=0..

TXIS

Bit 1: Transmit interrupt status (transmitters) This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software when NOSTRETCH=1 only, in order to generate a TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN=1). Note: This bit is cleared by hardware when PE=0..

RXNE

Bit 2: Receive data register not empty (receivers) This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. Note: This bit is cleared by hardware when PE=0..

ADDR

Bit 3: Address matched (slave mode) This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. Note: This bit is cleared by hardware when PE=0..

NACKF

Bit 4: Not Acknowledge received flag This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. Note: This bit is cleared by hardware when PE=0..

STOPF

Bit 5: Stop detection flag This flag is set by hardware when a STOP condition is detected on the bus and the peripheral is involved in this transfer: either as a master, provided that the STOP condition is generated by the peripheral. or as a slave, provided that the peripheral has been addressed previously during this transfer. It is cleared by software by setting the STOPCF bit. Note: This bit is cleared by hardware when PE=0..

TC

Bit 6: Transfer Complete (master mode) This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. Note: This bit is cleared by hardware when PE=0..

TCR

Bit 7: Transfer Complete Reload This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. Note: This bit is cleared by hardware when PE=0. This flag is only for master mode, or for slave mode when the SBC bit is set..

BERR

Bit 8: Bus error This flag is set by hardware when a misplaced Start or STOP condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting BERRCF bit. Note: This bit is cleared by hardware when PE=0..

ARLO

Bit 9: Arbitration lost This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. Note: This bit is cleared by hardware when PE=0..

OVR

Bit 10: Overrun/Underrun (slave mode) This flag is set by hardware in slave mode with NOSTRETCH=1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. Note: This bit is cleared by hardware when PE=0..

PECERR

Bit 11: PEC Error in reception This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to ..

TIMEOUT

Bit 12: Timeout or tLOW detection flag This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared by software by setting the TIMEOUTCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to ..

ALERT

Bit 13: SMBus alert This flag is set by hardware when SMBHEN=1 (SMBus host configuration), ALERTEN=1 and a SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by setting the ALERTCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to ..

BUSY

Bit 15: Bus busy This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected, or when PE=0..

DIR

Bit 16: Transfer direction (Slave mode) This flag is updated when an address match event occurs (ADDR=1)..

ADDCODE

Bits 17-23: Address match code (Slave mode) These bits are updated with the received address when an address match event occurs (ADDR = 1). In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the 2 MSBs of the address..

ICR

I2C interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ALERTCF w	TIMOUTCF w	PECCF w	OVRCF w	ARLOCF w	BERRCF w			STOPCF w	NACKCF w	ADDRCF w

Toggle fields

ADDRCF

Bit 3: Address matched flag clear Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears the START bit in the I2C_CR2 register..

NACKCF

Bit 4: Not Acknowledge flag clear Writing 1 to this bit clears the NACKF flag in I2C_ISR register..

STOPCF

Bit 5: STOP detection flag clear Writing 1 to this bit clears the STOPF flag in the I2C_ISR register..

BERRCF

Bit 8: Bus error flag clear Writing 1 to this bit clears the BERRF flag in the I2C_ISR register..

ARLOCF

Bit 9: Arbitration lost flag clear Writing 1 to this bit clears the ARLO flag in the I2C_ISR register..

OVRCF

Bit 10: Overrun/Underrun flag clear Writing 1 to this bit clears the OVR flag in the I2C_ISR register..

PECCF

Bit 11: PEC Error flag clear Writing 1 to this bit clears the PECERR flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to ..

TIMOUTCF

Bit 12: Timeout detection flag clear Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to ..

ALERTCF

Bit 13: Alert flag clear Writing 1 to this bit clears the ALERT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to ..

PECR

I2C PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PEC r

Toggle fields

PEC

Bits 0-7: Packet error checking register This field contains the internal PEC when PECEN=1. The PEC is cleared by hardware when PE=0..

RXDR

I2C receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RXDATA r

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RXDATA

Bits 0-7: 8-bit receive data Data byte received from the I2C bus.

TXDR

I2C transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TXDATA rw

Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data Data byte to be transmitted to the I2C bus Note: These bits can be written only when TXE=1..

IWDG

0x40003000: IWDG register block

3/7 fields covered.

Toggle register map

Offset	Name	15	11	2	1	0
0x0	KR	KEY
0x4	PR			PR
0x8	RLR		RL
0xc	SR			WVU	RVU	PVU
0x10	WINR		WIN

Toggle registers

KR

IWDG key register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY w

Toggle fields

KEY

Bits 0-15: Key value (write only, read 0x0000) These bits must be written by software at regular intervals with the key value 0xAAAA, otherwise the watchdog generates a reset when the counter reaches 0. Writing the key value 0x5555 to enable access to the IWDG_PR, IWDG_RLR and IWDG_WINR registers (see ) Writing the key value 0xCCCC starts the watchdog (except if the hardware watchdog option is selected).

PR

IWDG prescaler register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													PR rw

Toggle fields

PR

Bits 0-2: Prescaler divider These bits are write access protected see . They are written by software to select the prescaler divider feeding the counter clock. PVU bit of the must be reset in order to be able to change the prescaler divider. Note: Reading this register returns the prescaler value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the PVU bit in the status register (IWDG_SR) is reset..

RLR

IWDG reload register

Offset: 0x8, size: 32, reset: 0x00000FFF, access: Unspecified

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				RL rw

Toggle fields

RL

Bits 0-11: Watchdog counter reload value These bits are write access protected see . They are written by software to define the value to be loaded in the watchdog counter each time the value 0xAAAA is written in the . The watchdog counter counts down from this value. The timeout period is a function of this value and the clock prescaler. Refer to the datasheet for the timeout information. The RVU bit in the must be reset to be able to change the reload value. Note: Reading this register returns the reload value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing on it. For this reason the value read from this register is valid only when the RVU bit in the status register (IWDG_SR) is reset..

SR

IWDG status register

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													WVU r	RVU r	PVU r

Toggle fields

PVU

Bit 0: Watchdog prescaler value update This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by hardware when the prescaler update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Prescaler value can be updated only when PVU bit is reset..

RVU

Bit 1: Watchdog counter reload value update This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Reload value can be updated only when RVU bit is reset..

WVU

Bit 2: Watchdog counter window value update This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Window value can be updated only when WVU bit is reset..

WINR

IWDG window register

Offset: 0x10, size: 32, reset: 0x00000FFF, access: Unspecified

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				WIN rw

Toggle fields

WIN

Bits 0-11: Watchdog counter window value These bits are write access protected, see , they contain the high limit of the window value to be compared with the downcounter. To prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 0x0 The WVU bit in the must be reset in order to be able to change the reload value. Note: Reading this register returns the reload value from the VDD voltage domain. This value may not be valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the WVU bit in the (IWDG_SR) is reset..

PWR

0x40007000: PWR address block description

8/117 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1											FPD_SLP		FPD_STOP	LPMS
0x8	CR3	EIWUL					APC					EWUP6		EWUP4	EWUP3	EWUP2	EWUP1
0xc	CR4											WP6		WP4	WP3	WP2	WP1
0x10	SR1	WUFI							SBF			WUF6		WUF4	WUF3	WUF2	WUF1
0x14	SR2									FLASH_RDY
0x18	SCR								CSBF			CWUF6		CWUF4	CWUF3	CWUF2	CWUF1
0x20	PUCRA	PU15	PU14	PU13	PU12	PU11	PU10	PU9	PU8	PU7	PU6	PU5	PU4	PU3	PU2	PU1	PU0
0x24	PDCRA	PD15	PD14	PD13	PD12	PD11	PD10	PD9	PD8	PD7	PD6	PD5	PD4	PD3	PD2	PD1	PD0
0x28	PUCRB	PU15	PU14	PU13	PU12	PU11	PU10	PU9	PU8	PU7	PU6	PU5	PU4	PU3	PU2	PU1	PU0
0x2c	PDCRB	PD15	PD14	PD13	PD12	PD11	PD10	PD9	PD8	PD7	PD6	PD5	PD4	PD3	PD2	PD1	PD0
0x30	PUCRC	PU15	PU14	PU13						PU7	PU6
0x34	PDCRC	PD15	PD14	PD13						PD7	PD6
0x38	PUCRD													PU3	PU2	PU1	PU0
0x3c	PDCRD													PD3	PD2	PD1	PD0
0x48	PUCRF														PU2	PU1	PU0
0x4c	PDCRF														PD2	PD1	PD0

Toggle registers

CR1

PWR control register 1

Offset: 0x0, size: 32, reset: 0x00000208, access: Unspecified

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										FPD_SLP rw		FPD_STOP rw	LPMS rw

Toggle fields

LPMS

Bits 0-2: Low-power mode selection These bits select the low-power mode entered when CPU enters deepsleep mode. 1XX: Shutdown mode.

FPD_STOP

Bit 3: Flash memory powered down during Stop mode This bit determines whether the Flash memory is put in power-down mode or remains in idle mode when the device enters Stop mode..

FPD_SLP

Bit 5: Flash memory powered down during Sleep mode This bit determines whether the Flash memory is put in power-down mode or remains in idle mode when the device enters Sleep mode..

CR3

PWR control register 3

Offset: 0x8, size: 32, reset: 0x00008000, access: Unspecified

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EIWUL rw					APC rw					EWUP6 rw		EWUP4 rw	EWUP3 rw	EWUP2 rw	EWUP1 rw

Toggle fields

EWUP1

Bit 0: Enable WKUP1 wakeup pin When this bit is set, the WKUP1 external wakeup pin is enabled and triggers a wakeup event when a rising or a falling edge occurs. The active edge is configured via the WP1 bit of the PWR_CR4 register..

EWUP2

Bit 1: Enable WKUP2 wakeup pin When this bit is set, the WKUP2 external wakeup pin is enabled and triggers a wakeup event when a rising or a falling edge occurs. The active edge is configured via the WP2 bit of the PWR_CR4 register..

EWUP3

Bit 2: Enable WKUP3 wakeup pin When this bit is set, the WKUP3 external wakeup pin is enabled and triggers a wakeup event when a rising or a falling edge occurs. The active edge is configured via the WP3 bit of the PWR_CR4 register..

EWUP4

Bit 3: Enable WKUP4 wakeup pin When this bit is set, the WKUP4 external wakeup pin is enabled and triggers a wakeup event when a rising or a falling edge occurs. The active edge is configured via the WP4 bit in the PWR_CR4 register..

EWUP6

Bit 5: Enable WKUP6 wakeup pin When this bit is set, the WKUP6 external wakeup pin is enabled and triggers a wakeup event when a rising or a falling edge occurs. The active edge is configured through WP6 bit in the PWR_CR4 register..

APC

Bit 10: Apply pull-up and pull-down configuration This bit determines whether the I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied..

EIWUL

Bit 15: Enable internal wakeup line When set, a rising edge on the internal wakeup line triggers a wakeup event..

CR4

PWR control register 4

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										WP6 rw		WP4 rw	WP3 rw	WP2 rw	WP1 rw

Toggle fields

WP1

Bit 0: WKUP1 wakeup pin polarity WKUP1 external wakeup signal polarity (level or edge) to generate wakeup condition:.

WP2

Bit 1: WKUP2 wakeup pin polarity WKUP2 external wakeup signal polarity (level or edge) to generate wakeup condition:.

WP3

Bit 2: WKUP3 wakeup pin polarity WKUP3 external wakeup signal polarity (level or edge) to generate wakeup condition:.

WP4

Bit 3: WKUP4 wakeup pin polarity WKUP4 external wakeup signal polarity (level or edge) to generate wakeup condition:.

WP6

Bit 5: WKUP6 wakeup pin polarity WKUP6 external wakeup signal polarity (level or edge) to generate wakeup condition:.

SR1

PWR status register 1

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WUFI r							SBF r			WUF6 r		WUF4 r	WUF3 r	WUF2 r	WUF1 r

Toggle fields

WUF1

Bit 0: Wakeup flag 1 This bit is set when a wakeup condition is detected on WKUP1 wakeup pin. It is cleared by setting the CWUF1 bit of the PWR_SCR register..

WUF2

Bit 1: Wakeup flag 2 This bit is set when a wakeup condition is detected on WKUP2 wakeup pin. It is cleared by setting the CWUF2 bit of the PWR_SCR register..

WUF3

Bit 2: Wakeup flag 3 This bit is set when a wakeup condition is detected on WKUP3 wakeup pin. It is cleared by setting the CWUF3 bit of the PWR_SCR register..

WUF4

Bit 3: Wakeup flag 4 This bit is set when a wakeup condition is detected on WKUP4 wakeup pin. It is cleared by setting the CWUF4 bit of the PWR_SCR register..

WUF6

Bit 5: Wakeup flag 6 This bit is set when a wakeup condition is detected on WKUP6 wakeup pin. It is cleared by setting the CWUF6 bit of the PWR_SCR register..

SBF

Bit 8: Standby/Shutdown flag This bit is set by hardware when the device enters Standby or Shutdown mode and is cleared by setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the system reset..

WUFI

Bit 15: Wakeup flag internal This bit is set when a wakeup condition is detected on the internal wakeup line. It is cleared when all internal wakeup sources are cleared..

SR2

PWR status register 2

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								FLASH_RDY r

Toggle fields

FLASH_RDY

Bit 7: Flash ready flag This bit is set by hardware to indicate when the Flash memory is ready to be accessed after wakeup from power-down. To place the Flash memory in power-down, set either FPD_SLP or FPD_STP bit. Note: If the system boots from SRAM, the user application must wait till FLASH_RDY bit is set, prior to jumping to Flash memory..

SCR

PWR status clear register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							CSBF w			CWUF6 w		CWUF4 w	CWUF3 w	CWUF2 w	CWUF1 w

Toggle fields

CWUF1

Bit 0: Clear wakeup flag 1 Setting this bit clears the WUF1 flag in the PWR_SR1 register..

CWUF2

Bit 1: Clear wakeup flag 2 Setting this bit clears the WUF2 flag in the PWR_SR1 register..

CWUF3

Bit 2: Clear wakeup flag 3 Setting this bit clears the WUF3 flag in the PWR_SR1 register..

CWUF4

Bit 3: Clear wakeup flag 4 Setting this bit clears the WUF4 flag in the PWR_SR1 register..

CWUF6

Bit 5: Clear wakeup flag 6 Setting this bit clears the WUF6 flag in the PWR_SR1 register..

CSBF

Bit 8: Clear standby flag Setting this bit clears the SBF flag in the PWR_SR1 register..

PUCRA

PWR Port A pull-up control register

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PU15 rw	PU14 rw	PU13 rw	PU12 rw	PU11 rw	PU10 rw	PU9 rw	PU8 rw	PU7 rw	PU6 rw	PU5 rw	PU4 rw	PU3 rw	PU2 rw	PU1 rw	PU0 rw

Toggle fields

PU0

Bit 0: Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O..

PU1

Bit 1: Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O..

PU2

Bit 2: Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O..

PU3

Bit 3: Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O..

PU4

Bit 4: Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O..

PU5

Bit 5: Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O..

PU6

Bit 6: Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O..

PU7

Bit 7: Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O..

PU8

Bit 8: Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O..

PU9

Bit 9: Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O..

PU10

Bit 10: Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O..

PU11

Bit 11: Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O..

PU12

Bit 12: Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O..

PU13

Bit 13: Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O..

PU14

Bit 14: Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O..

PU15

Bit 15: Port A pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[i] I/O..

PDCRA

PWR Port A pull-down control register

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PD15 rw	PD14 rw	PD13 rw	PD12 rw	PD11 rw	PD10 rw	PD9 rw	PD8 rw	PD7 rw	PD6 rw	PD5 rw	PD4 rw	PD3 rw	PD2 rw	PD1 rw	PD0 rw

Toggle fields

PD0

Bit 0: Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O..

PD1

Bit 1: Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O..

PD2

Bit 2: Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O..

PD3

Bit 3: Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O..

PD4

Bit 4: Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O..

PD5

Bit 5: Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O..

PD6

Bit 6: Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O..

PD7

Bit 7: Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O..

PD8

Bit 8: Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O..

PD9

Bit 9: Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O..

PD10

Bit 10: Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O..

PD11

Bit 11: Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O..

PD12

Bit 12: Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O..

PD13

Bit 13: Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O..

PD14

Bit 14: Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O..

PD15

Bit 15: Port A pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[i] I/O..

PUCRB

PWR Port B pull-up control register

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PU15 rw	PU14 rw	PU13 rw	PU12 rw	PU11 rw	PU10 rw	PU9 rw	PU8 rw	PU7 rw	PU6 rw	PU5 rw	PU4 rw	PU3 rw	PU2 rw	PU1 rw	PU0 rw

Toggle fields

PU0

Bit 0: Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available.

PU1

Bit 1: Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available.

PU2

Bit 2: Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available.

PU3

Bit 3: Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available.

PU4

Bit 4: Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available.

PU5

Bit 5: Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available.

PU6

Bit 6: Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available.

PU7

Bit 7: Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available.

PU8

Bit 8: Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available.

PU9

Bit 9: Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available.

PU10

Bit 10: Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available.

PU11

Bit 11: Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available.

PU12

Bit 12: Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available.

PU13

Bit 13: Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available.

PU14

Bit 14: Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available.

PU15

Bit 15: Port B pull-up bit i (i = 15 to 0) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[i] I/O. On STM32C011xx, only PU7 and PU6 are available.

PDCRB

PWR Port B pull-down control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PD15 rw	PD14 rw	PD13 rw	PD12 rw	PD11 rw	PD10 rw	PD9 rw	PD8 rw	PD7 rw	PD6 rw	PD5 rw	PD4 rw	PD3 rw	PD2 rw	PD1 rw	PD0 rw

Toggle fields

PD0

Bit 0: Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available.

PD1

Bit 1: Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available.

PD2

Bit 2: Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available.

PD3

Bit 3: Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available.

PD4

Bit 4: Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available.

PD5

Bit 5: Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available.

PD6

Bit 6: Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available.

PD7

Bit 7: Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available.

PD8

Bit 8: Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available.

PD9

Bit 9: Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available.

PD10

Bit 10: Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available.

PD11

Bit 11: Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available.

PD12

Bit 12: Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available.

PD13

Bit 13: Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available.

PD14

Bit 14: Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available.

PD15

Bit 15: Port B pull-down bit i (i = 15 to 0) Setting PDi bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[i] I/O. On STM32C011xx, only PD7 and PD6 are available.

PUCRC

PWR Port C pull-up control register

Offset: 0x30, size: 32, reset: 0x00000000, access: Unspecified

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PU15 rw	PU14 rw	PU13 rw						PU7 rw	PU6 rw

Toggle fields

PU6

Bit 6: Port C pull-up bit i (i = 15 to 13, 7 to 6) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PC[i] I/O. On STM32C011xx, only PU15 and PU14 are available.

PU7

Bit 7: Port C pull-up bit i (i = 15 to 13, 7 to 6) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PC[i] I/O. On STM32C011xx, only PU15 and PU14 are available.

PU13

Bit 13: Port C pull-up bit i (i = 15 to 13, 7 to 6) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PC[i] I/O. On STM32C011xx, only PU15 and PU14 are available.

PU14

Bit 14: Port C pull-up bit i (i = 15 to 13, 7 to 6) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PC[i] I/O. On STM32C011xx, only PU15 and PU14 are available.

PU15

Bit 15: Port C pull-up bit i (i = 15 to 13, 7 to 6) Setting PUi bit while the corresponding PDi bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PC[i] I/O. On STM32C011xx, only PU15 and PU14 are available.

PDCRC

PWR Port C pull-down control register

Offset: 0x34, size: 32, reset: 0x00000000, access: Unspecified

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PD15 rw	PD14 rw	PD13 rw						PD7 rw	PD6 rw

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR												CSSON	HSEBYP	HSERDY	HSEON			HSIDIV			HSIRDY	HSIKERON	HSION	HSIKERDIV			SYSDIV
0x4	ICSCR																	HSITRIM							HSICAL
0x8	CFGR	MCOPRE				MCOSEL				MCO2PRE			MCO2SEL					PPRE			HPRE						SWS			SW
0x18	CIER																											HSERDYIE	HSIRDYIE		LSERDYIE	LSIRDYIE
0x1c	CIFR																						LSECSSF	CSSF				HSERDYF	HSIRDYF		LSERDYF	LSIRDYF
0x20	CICR																						LSECSSC	CSSC				HSERDYC	HSIRDYC		LSERDYC	LSIRDYC
0x24	IOPRSTR																										GPIOFRST		GPIODRST	GPIOCRST	GPIOBRST	GPIOARST
0x28	AHBRSTR																			CRCRST				FLASHRST								DMA1RST
0x2c	APBRSTR1				PWRRST	DBGRST					I2C1RST				USART2RST																TIM3RST
0x30	APBRSTR2											ADCRST		TIM17RST	TIM16RST		TIM14RST	USART1RST		SPI1RST	TIM1RST											SYSCFGRST
0x34	IOPENR																										GPIOFEN		GPIODEN	GPIOCEN	GPIOBEN	GPIOAEN
0x38	AHBENR																			CRCEN				FLASHEN								DMA1EN
0x3c	APBENR1				PWREN	DBGEN					I2C1EN				USART2EN						WWDGEN	RTCAPBEN									TIM3EN
0x40	APBENR2											ADCEN		TIM17EN	TIM16EN		TIM14EN	USART1EN		SPI1EN	TIM1EN											SYSCFGEN
0x44	IOPSMENR																										GPIOFSMEN		GPIODSMEN	GPIOCSMEN	GPIOBSMEN	GPIOASMEN
0x48	AHBSMENR																			CRCSMEN			SRAMSMEN	FLASHSMEN								DMA1SMEN
0x4c	APBSMENR1				PWRSMEN	DBGSMEN					I2C1SMEN				USART2SMEN						WWDGSMEN	RTCAPBSMEN									TIM3SMEN
0x50	APBSMENR2											ADCSMEN		TIM17SMEN	TIM16SMEN		TIM14SMEN	USART1SMEN		SPI1SMEN	TIM1SMEN											SYSCFGSMEN
0x54	CCIPR	ADCSEL															I2S1SEL		I2C1SEL												USART1SEL
0x5c	CSR1							LSCOSEL	LSCOEN							RTCRST	RTCEN						RTCSEL			LSECSSD	LSECSSON	LSEDRV		LSEBYP	LSERDY	LSEON
0x60	CSR2	LPWRRSTF	WWDGRSTF	IWDGRSTF	SFTRSTF	PWRRSTF	PINRSTF	OBLRSTF		RMVF																					LSIRDY	LSION

Toggle registers

CR

RCC clock control register

Offset: 0x0, size: 32, reset: 0x00000500, access: Unspecified

2/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												CSSON rw	HSEBYP rw	HSERDY r	HSEON rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		HSIDIV rw			HSIRDY r	HSIKERON rw	HSION rw	HSIKERDIV rw			SYSDIV rw

Toggle fields

SYSDIV

Bits 2-4: System clock division factor This bitfield controlled by software sets the division factor of the system clock divider to produce SYSCLK clock:.

HSIKERDIV

Bits 5-7: HSI48 kernel clock division factor This bitfield controlled by software sets the division factor of the kernel clock divider to produce HSIKER clock:.

HSION

Bit 8: HSI48 clock enable Set and cleared by software and hardware, with hardware taking priority. Kept low by hardware as long as the device is in a low-power mode. Kept high by hardware as long as the system is clocked with a clock derived from HSI48. This includes the exit from low-power modes and the system clock fall-back to HSI48 upon failing HSE oscillator clock selected as system clock source..

HSIKERON

Bit 9: HSI48 always-enable for peripheral kernels. Set and cleared by software. Setting the bit activates the HSI48 oscillator in Run and Stop modes, regardless of the HSION bit state. The HSI48 clock can only feed USART1, USART2, and I2C1 peripherals configured with HSI48 as kernel clock. Note: Keeping the HSI48 active in Stop mode allows speeding up the serial interface communication as the HSI48 clock is ready immediately upon exiting Stop mode..

HSIRDY

Bit 10: HSI48 clock ready flag Set by hardware when the HSI48 oscillator is enabled through HSION and ready to use (stable). Note: Upon clearing HSION, HSIRDY goes low after six HSI48 clock cycles..

HSIDIV

Bits 11-13: HSI48 clock division factor This bitfield controlled by software sets the division factor of the HSI48 clock divider to produce HSISYS clock:.

HSEON

Bit 16: HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE oscillator when entering Stop, or Standby, or Shutdown mode. This bit cannot be cleared if the HSE oscillator is used directly or indirectly as the system clock..

HSERDY

Bit 17: HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable and ready for use. Note: Upon clearing HSEON, HSERDY goes low after six HSE clock cycles..

HSEBYP

Bit 18: HSE crystal oscillator bypass Set and cleared by software. When the bit is set, the internal HSE oscillator is bypassed for use of an external clock. The external clock must then be enabled with the HSEON bit set. Write access to the bit is only effective when the HSE oscillator is disabled..

CSSON

Bit 19: Clock security system enable Set by software to enable the clock security system. When the bit is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. The bit is cleared by hardware upon reset..

ICSCR

RCC internal clock source calibration register

Offset: 0x4, size: 32, reset: 0x00004000, access: Unspecified

1/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	HSITRIM rw							HSICAL r

Toggle fields

HSICAL

Bits 0-7: HSI48 clock calibration This bitfield directly acts on the HSI48 clock frequency. Its value is a sum of an internal factory-programmed number and the value of the HSITRIM[6:0] bitfield. In the factory, the internal number is set to calibrate the HSI48 clock frequency to 48 MHz (with HSITRIM[6:0] left at its reset value). Refer to the device datasheet for HSI48 calibration accuracy and for the frequency trimming granularity. Note: The trimming effect presents discontinuities at HSICAL[7:0] multiples of 64..

HSITRIM

Bits 8-14: HSI48 clock trimming The value of this bitfield contributes to the HSICAL[7:0] bitfield value. It allows HSI48 clock frequency user trimming. The HSI48 frequency accuracy as stated in the device datasheet applies when this bitfield is left at its reset value..

CFGR

RCC clock configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

1/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MCOPRE rw				MCOSEL rw				MCO2PRE rw				MCO2SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	PPRE rw			HPRE rw						SWS r			SW rw

Toggle fields

SW

Bits 0-2: System clock switch This bitfield is controlled by software and hardware. The bitfield selects the clock for SYSCLK as follows: Others: Reserved The setting is forced by hardware to 000 (HSISYS selected) when the MCU exits Stop, or Standby, or Shutdown mode, or when the setting is 001 (HSE selected) and HSE oscillator failure is detected..

SWS

Bits 3-5: System clock switch status This bitfield is controlled by hardware to indicate the clock source used as system clock: Others: Reserved.

HPRE

Bits 8-11: AHB prescaler This bitfield is controlled by software. To produce HCLK clock, it sets the division factor of SYSCLK clock as follows: 0xxx: 1.

PPRE

Bits 12-14: APB prescaler This bitfield is controlled by software. To produce PCLK clock, it sets the division factor of HCLK clock as follows: 0xx: 1.

MCO2SEL

Bits 16-19: Microcontroller clock output 2 clock selector This bitfield is controlled by software. It sets the clock selector for MCO2 output as follows: This bitfield is controlled by software. It sets the clock selector for MCO output as follows: Note: This clock output may have some truncated cycles at startup or during MCO2 clock source switching..

MCO2PRE

Bits 20-23: Microcontroller clock output 2 prescaler This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO2 output as follows: ... It is highly recommended to set this field before the MCO2 output is enabled..

MCOSEL

Bits 24-27: Microcontroller clock output clock selector This bitfield is controlled by software. It sets the clock selector for MCO output as follows: Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. Any other value means no clock on MCO..

MCOPRE

Bits 28-31: Microcontroller clock output prescaler This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO output as follows: ... It is highly recommended to set this field before the MCO output is enabled..

CIER

RCC clock interrupt enable register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											HSERDYIE rw	HSIRDYIE rw		LSERDYIE rw	LSIRDYIE rw

Toggle fields

LSIRDYIE

Bit 0: LSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization:.

LSERDYIE

Bit 1: LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization:.

HSIRDYIE

Bit 3: HSI16 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization:.

HSERDYIE

Bit 4: HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization:.

CIFR

RCC clock interrupt flag register

Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						LSECSSF r	CSSF r				HSERDYF r	HSIRDYF r		LSERDYF r	LSIRDYF r

Toggle fields

LSIRDYF

Bit 0: LSI ready interrupt flag This flag indicates a pending interrupt upon LSE clock getting ready. Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set. Cleared by software setting the LSIRDYC bit..

LSERDYF

Bit 1: LSE ready interrupt flag This flag indicates a pending interrupt upon LSE clock getting ready. Set by hardware when the LSE clock becomes stable and LSERDYDIE is set. Cleared by software setting the LSERDYC bit..

HSIRDYF

Bit 3: HSI16 ready interrupt flag This flag indicates a pending interrupt upon HSI16 clock getting ready. Set by hardware when the HSI16 clock becomes stable and HSIRDYIE is set in response to setting the HSION (refer to ). When HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. Cleared by software setting the HSIRDYC bit..

HSERDYF

Bit 4: HSE ready interrupt flag This flag indicates a pending interrupt upon HSE clock getting ready. Set by hardware when the HSE clock becomes stable and HSERDYIE is set. Cleared by software setting the HSERDYC bit..

CSSF

Bit 8: HSE clock security system interrupt flag This flag indicates a pending interrupt upon HSE clock failure. Set by hardware when a failure is detected in the HSE oscillator. Cleared by software setting the CSSC bit..

LSECSSF

Bit 9: LSE clock security system interrupt flag This flag indicates a pending interrupt upon LSE clock failure. Set by hardware when a failure is detected in the LSE oscillator. Cleared by software by setting the LSECSSC bit..

CICR

RCC clock interrupt clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						LSECSSC w	CSSC w				HSERDYC w	HSIRDYC w		LSERDYC w	LSIRDYC w

Toggle fields

LSIRDYC

Bit 0: LSI ready interrupt clear This bit is set by software to clear the LSIRDYF flag..

LSERDYC

Bit 1: LSE ready interrupt clear This bit is set by software to clear the LSERDYF flag..

HSIRDYC

Bit 3: HSI16 ready interrupt clear This bit is set software to clear the HSIRDYF flag..

HSERDYC

Bit 4: HSE ready interrupt clear This bit is set by software to clear the HSERDYF flag..

CSSC

Bit 8: Clock security system interrupt clear This bit is set by software to clear the HSECSSF flag..

LSECSSC

Bit 9: LSE Clock security system interrupt clear This bit is set by software to clear the LSECSSF flag..

IOPRSTR

RCC I/O port reset register

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										GPIOFRST rw		GPIODRST rw	GPIOCRST rw	GPIOBRST rw	GPIOARST rw

Toggle fields

GPIOARST

Bit 0: I/O port A reset This bit is set and cleared by software..

GPIOBRST

Bit 1: I/O port B reset This bit is set and cleared by software..

GPIOCRST

Bit 2: I/O port C reset This bit is set and cleared by software..

GPIODRST

Bit 3: I/O port D reset This bit is set and cleared by software..

GPIOFRST

Bit 5: I/O port F reset This bit is set and cleared by software..

AHBRSTR

RCC AHB peripheral reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CRCRST rw				FLASHRST rw								DMA1RST rw

Toggle fields

DMA1RST

Bit 0: DMA1 and DMAMUX reset Set and cleared by software..

FLASHRST

Bit 8: Flash memory interface reset Set and cleared by software. This bit can only be set when the Flash memory is in power down mode..

CRCRST

Bit 12: CRC reset Set and cleared by software..

APBRSTR1

RCC APB peripheral reset register 1

Offset: 0x2c, size: 32, reset: 0x00000000, access: Unspecified

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			PWRRST rw	DBGRST rw						I2C1RST rw				USART2RST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														TIM3RST rw

Toggle fields

TIM3RST

Bit 1: TIM3 timer reset Set and cleared by software..

USART2RST

Bit 17: USART2 reset Set and cleared by software..

I2C1RST

Bit 21: I2C1 reset Set and cleared by software..

DBGRST

Bit 27: Debug support reset Set and cleared by software..

PWRRST

Bit 28: Power interface reset Set and cleared by software..

APBRSTR2

RCC APB peripheral reset register 2

Offset: 0x30, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											ADCRST rw		TIM17RST rw	TIM16RST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIM14RST rw	USART1RST rw		SPI1RST rw	TIM1RST rw											SYSCFGRST rw

Toggle fields

SYSCFGRST

Bit 0: SYSCFG reset Set and cleared by software..

TIM1RST

Bit 11: TIM1 timer reset Set and cleared by software..

SPI1RST

Bit 12: SPI1 reset Set and cleared by software..

USART1RST

Bit 14: USART1 reset Set and cleared by software..

TIM14RST

Bit 15: TIM14 timer reset Set and cleared by software..

TIM16RST

Bit 17: TIM16 timer reset Set and cleared by software..

TIM17RST

Bit 18: TIM16 timer reset Set and cleared by software..

ADCRST

Bit 20: ADC reset Set and cleared by software..

IOPENR

RCC I/O port clock enable register

Offset: 0x34, size: 32, reset: 0x00000000, access: Unspecified

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										GPIOFEN rw		GPIODEN rw	GPIOCEN rw	GPIOBEN rw	GPIOAEN rw

Toggle fields

GPIOAEN

Bit 0: I/O port A clock enable This bit is set and cleared by software..

GPIOBEN

Bit 1: I/O port B clock enable This bit is set and cleared by software..

GPIOCEN

Bit 2: I/O port C clock enable This bit is set and cleared by software..

GPIODEN

Bit 3: I/O port D clock enable This bit is set and cleared by software..

GPIOFEN

Bit 5: I/O port F clock enable This bit is set and cleared by software..

AHBENR

RCC AHB peripheral clock enable register

Offset: 0x38, size: 32, reset: 0x00000100, access: Unspecified

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CRCEN rw				FLASHEN rw								DMA1EN rw

Toggle fields

DMA1EN

Bit 0: DMA1 and DMAMUX clock enable Set and cleared by software. DMAMUX is enabled as long as at least one DMA peripheral is enabled..

FLASHEN

Bit 8: Flash memory interface clock enable Set and cleared by software. This bit can only be cleared when the Flash memory is in power down mode..

CRCEN

Bit 12: CRC clock enable Set and cleared by software..

APBENR1

RCC APB peripheral clock enable register 1

Offset: 0x3c, size: 32, reset: 0x00000000, access: Unspecified

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			PWREN rw	DBGEN rw						I2C1EN rw				USART2EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				WWDGEN rw	RTCAPBEN rw									TIM3EN rw

Toggle fields

TIM3EN

Bit 1: TIM3 timer clock enable Set and cleared by software..

RTCAPBEN

Bit 10: RTC APB clock enable Set and cleared by software..

WWDGEN

Bit 11: WWDG clock enable Set by software to enable the window watchdog clock. Cleared by hardware system reset This bit can also be set by hardware if the WWDG_SW option bit is 0..

USART2EN

Bit 17: USART2 clock enable Set and cleared by software..

I2C1EN

Bit 21: I2C1 clock enable Set and cleared by software..

DBGEN

Bit 27: Debug support clock enable Set and cleared by software..

PWREN

Bit 28: Power interface clock enable Set and cleared by software..

APBENR2

RCC APB peripheral clock enable register 2

Offset: 0x40, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											ADCEN rw		TIM17EN rw	TIM16EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIM14EN rw	USART1EN rw		SPI1EN rw	TIM1EN rw											SYSCFGEN rw

Toggle fields

SYSCFGEN

Bit 0: SYSCFG clock enable Set and cleared by software..

TIM1EN

Bit 11: TIM1 timer clock enable Set and cleared by software..

SPI1EN

Bit 12: SPI1 clock enable Set and cleared by software..

USART1EN

Bit 14: USART1 clock enable Set and cleared by software..

TIM14EN

Bit 15: TIM14 timer clock enable Set and cleared by software..

TIM16EN

Bit 17: TIM16 timer clock enable Set and cleared by software..

TIM17EN

Bit 18: TIM16 timer clock enable Set and cleared by software..

ADCEN

Bit 20: ADC clock enable Set and cleared by software..

IOPSMENR

RCC I/O port in Sleep mode clock enable register

Offset: 0x44, size: 32, reset: 0x0000003F, access: Unspecified

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										GPIOFSMEN rw		GPIODSMEN rw	GPIOCSMEN rw	GPIOBSMEN rw	GPIOASMEN rw

Toggle fields

GPIOASMEN

Bit 0: I/O port A clock enable during Sleep mode Set and cleared by software..

GPIOBSMEN

Bit 1: I/O port B clock enable during Sleep mode Set and cleared by software..

GPIOCSMEN

Bit 2: I/O port C clock enable during Sleep mode Set and cleared by software..

GPIODSMEN

Bit 3: I/O port D clock enable during Sleep mode Set and cleared by software..

GPIOFSMEN

Bit 5: I/O port F clock enable during Sleep mode Set and cleared by software..

AHBSMENR

RCC AHB peripheral clock enable in Sleep/Stop mode register

Offset: 0x48, size: 32, reset: 0x00051303, access: Unspecified

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CRCSMEN rw			SRAMSMEN rw	FLASHSMEN rw								DMA1SMEN rw

Toggle fields

DMA1SMEN

Bit 0: DMA1 and DMAMUX clock enable during Sleep mode Set and cleared by software. Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is enabled to at least one DMA peripheral..

FLASHSMEN

Bit 8: Flash memory interface clock enable during Sleep mode Set and cleared by software. This bit can be activated only when the Flash memory is in power down mode..

SRAMSMEN

Bit 9: SRAM clock enable during Sleep mode Set and cleared by software..

CRCSMEN

Bit 12: CRC clock enable during Sleep mode Set and cleared by software..

APBSMENR1

RCC APB peripheral clock enable in Sleep/Stop mode register 1

Offset: 0x4c, size: 32, reset: 0x18EF7F36, access: Unspecified

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			PWRSMEN rw	DBGSMEN rw						I2C1SMEN rw				USART2SMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				WWDGSMEN rw	RTCAPBSMEN rw									TIM3SMEN rw

Toggle fields

TIM3SMEN

Bit 1: TIM3 timer clock enable during Sleep mode Set and cleared by software..

RTCAPBSMEN

Bit 10: RTC APB clock enable during Sleep mode Set and cleared by software..

WWDGSMEN

Bit 11: WWDG clock enable during Sleep and Stop modes Set and cleared by software..

USART2SMEN

Bit 17: USART2 clock enable during Sleep and Stop modes Set and cleared by software..

I2C1SMEN

Bit 21: I2C1 clock enable during Sleep and Stop modes Set and cleared by software..

DBGSMEN

Bit 27: Debug support clock enable during Sleep mode Set and cleared by software..

PWRSMEN

Bit 28: Power interface clock enable during Sleep mode Set and cleared by software..

APBSMENR2

RCC APB peripheral clock enable in Sleep/Stop mode register 2

Offset: 0x50, size: 32, reset: 0x0017D801, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											ADCSMEN rw		TIM17SMEN rw	TIM16SMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIM14SMEN rw	USART1SMEN rw		SPI1SMEN rw	TIM1SMEN rw											SYSCFGSMEN rw

Toggle fields

SYSCFGSMEN

Bit 0: SYSCFG clock enable during Sleep and Stop modes Set and cleared by software..

TIM1SMEN

Bit 11: TIM1 timer clock enable during Sleep mode Set and cleared by software..

SPI1SMEN

Bit 12: SPI1 clock enable during Sleep mode Set and cleared by software..

USART1SMEN

Bit 14: USART1 clock enable during Sleep and Stop modes Set and cleared by software..

TIM14SMEN

Bit 15: TIM14 timer clock enable during Sleep mode Set and cleared by software..

TIM16SMEN

Bit 17: TIM16 timer clock enable during Sleep mode Set and cleared by software..

TIM17SMEN

Bit 18: TIM16 timer clock enable during Sleep mode Set and cleared by software..

ADCSMEN

Bit 20: ADC clock enable during Sleep mode Set and cleared by software..

CCIPR

RCC peripherals independent clock configuration register

Offset: 0x54, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADCSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
I2S1SEL rw		I2C1SEL rw												USART1SEL rw

Toggle fields

USART1SEL

Bits 0-1: USART1 clock source selection This bitfield is controlled by software to select USART1 clock source as follows:.

I2C1SEL

Bits 12-13: I2C1 clock source selection This bitfield is controlled by software to select I2C1 clock source as follows:.

I2S1SEL

Bits 14-15: I2S1 clock source selection This bitfield is controlled by software to select I2S1 clock source as follows:.

ADCSEL

Bits 30-31: ADCs clock source selection This bitfield is controlled by software to select the clock source for ADC:.

CSR1

RCC control/status register 1

Offset: 0x5c, size: 32, reset: 0x00000000, access: Unspecified

2/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						LSCOSEL rw	LSCOEN rw								RTCRST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RTCEN rw						RTCSEL rw			LSECSSD r	LSECSSON rw	LSEDRV rw		LSEBYP rw	LSERDY r	LSEON rw

Toggle fields

LSEON

Bit 0: LSE oscillator enable Set and cleared by software to enable LSE oscillator:.

LSERDY

Bit 1: LSE oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is ready (stable): After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles..

LSEBYP

Bit 2: LSE oscillator bypass Set and cleared by software to bypass the LSE oscillator (in debug mode). This bit can be written only when the external 32 kHz oscillator is disabled (LSEON=0 and LSERDY=0)..

LSEDRV

Bits 3-4: LSE oscillator drive capability Set by software to select the LSE oscillator drive capability as follows: Applicable when the LSE oscillator is in Xtal mode, as opposed to bypass mode..

LSECSSON

Bit 5: CSS on LSE enable Set by software to enable the clock security system on LSE (32 kHz) oscillator as follows: LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD =1). In that case the software must disable the LSECSSON bit..

LSECSSD

Bit 6: CSS on LSE failure Detection Set by hardware to indicate when a failure is detected by the clock security system on the external 32 kHz oscillator (LSE):.

RTCSEL

Bits 8-9: RTC clock source selection Set by software to select the clock source for the RTC as follows: Once the RTC clock source is selected, it cannot be changed anymore unless the RTC domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The RTCRST bit can be used to reset this bitfield to 00..

RTCEN

Bit 15: RTC clock enable Set and cleared by software. The bit enables clock to RTC and TAMP..

RTCRST

Bit 16: RTC domain software reset Set and cleared by software to reset the RTC domain:.

LSCOEN

Bit 24: Low-speed clock output (LSCO) enable Set and cleared by software..

LSCOSEL

Bit 25: Low-speed clock output selection Set and cleared by software to select the low-speed output clock:.

CSR2

RCC control/status register 2

Offset: 0x60, size: 32, reset: 0x00000000, access: Unspecified

8/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LPWRRSTF r	WWDGRSTF r	IWDGRSTF r	SFTRSTF r	PWRRSTF r	PINRSTF r	OBLRSTF r		RMVF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														LSIRDY r	LSION rw

Toggle fields

LSION

Bit 0: LSI oscillator enable Set and cleared by software to enable/disable the LSI oscillator:.

LSIRDY

Bit 1: LSI oscillator ready Set and cleared by hardware to indicate when the LSI oscillator is ready (stable): After the LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit can be set even if LSION = 0 if the LSI is requested by the Clock Security System on LSE, by the Independent Watchdog or by the RTC..

RMVF

Bit 23: Remove reset flags Set by software to clear the reset flags..

OBLRSTF

Bit 25: Option byte loader reset flag Set by hardware when a reset from the Option byte loading occurs. Cleared by setting the RMVF bit..

PINRSTF

Bit 26: Pin reset flag Set by hardware when a reset from the NRST pin occurs. Cleared by setting the RMVF bit..

PWRRSTF

Bit 27: BOR or POR/PDR flag Set by hardware when a BOR or POR/PDR occurs. Cleared by setting the RMVF bit..

SFTRSTF

Bit 28: Software reset flag Set by hardware when a software reset occurs. Cleared by setting the RMVF bit..

IWDGRSTF

Bit 29: Independent window watchdog reset flag Set by hardware when an independent watchdog reset domain occurs. Cleared by setting the RMVF bit..

WWDGRSTF

Bit 30: Window watchdog reset flag Set by hardware when a window watchdog reset occurs. Cleared by setting the RMVF bit..

LPWRRSTF

Bit 31: Low-power reset flag Set by hardware when a reset occurs due to illegal Stop, or Standby, or Shutdown mode entry. Cleared by setting the RMVF bit. This operates only if nRST_STOP, or nRST_STDBY or nRST_SHDW option bits are cleared..

RTC

0x40002800: RTC register block

25/87 fields covered.

Toggle register map

Offset	Name	31	30	29	27	23	22	21	20	19	18	17	16	15	14	13	12	11	8	7	6	5	4	3	0
0x0	TR						PM	HT		HU					MNT			MNU			ST			SU
0x4	DR					YT				YU				WDU			MT	MU				DT		DU
0x8	SSR													SS
0xc	ICSR												RECALPF							INIT	INITF	RSF	INITS	SHPF	ALRAWF
0x10	PRER						PREDIV_A								PREDIV_S
0x18	CR	OUT2EN	TAMPALRM_TYPE	TAMPALRM_PU		COE	OSEL		POL	COSEL	BKP	SUB1H	ADD1H	TSIE			ALRAIE	TSE	ALRAE		FMT	BYPSHAD	REFCKON	TSEDGE
0x24	WPR																			KEY
0x28	CALR													CALP	CALW8	CALW16			CALM
0x2c	SHIFTR	ADD1S													SUBFS
0x30	TSTR						PM	HT		HU					MNT			MNU			ST			SU
0x34	TSDR													WDU			MT	MU				DT		DU
0x38	TSSSR													SS
0x40	ALRMAR	MSK4	WDSEL	DT	DU	MSK3	PM	HT		HU				MSK2	MNT			MNU		MSK1	ST			SU
0x44	ALRMASSR				MASKSS										SS
0x50	SR																						TSOVF	TSF	ALRAF
0x54	MISR																						TSOVMF	TSMF	ALRAMF
0x5c	SCR																						CTSOVF	CTSF	CALRAF

Toggle registers

TR

RTC time register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									PM rw	HT rw		HU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MNT rw			MNU rw					ST rw			SU rw

Toggle fields

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

DR

RTC date register

Offset: 0x4, size: 32, reset: 0x00002101, access: Unspecified

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								YT rw				YU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WDU rw			MT rw	MU rw						DT rw		DU rw

Toggle fields

DU

Bits 0-3: Date units in BCD format.

DT

Bits 4-5: Date tens in BCD format.

MU

Bits 8-11: Month units in BCD format.

MT

Bit 12: Month tens in BCD format.

WDU

Bits 13-15: Week day units ....

YU

Bits 16-19: Year units in BCD format.

YT

Bits 20-23: Year tens in BCD format.

SSR

RTC sub second register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SS r

Toggle fields

SS

Bits 0-15: Sub second value SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given by the formula below: Second fraction = (PREDIV_S - SS) / (PREDIV_S + 1) Note: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct time/date is one second less than as indicated by RTC_TR/RTC_DR..

ICSR

RTC initialization control and status register

Offset: 0xc, size: 32, reset: 0x00000007, access: Unspecified

5/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															RECALPF r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								INIT rw	INITF r	RSF rw	INITS r	SHPF r			ALRAWF r

Toggle fields

ALRAWF

Bit 0: Alarm A write flag This bit is set by hardware when alarm A values can be changed, after the ALRAE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode..

SHPF

Bit 3: Shift operation pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect..

INITS

Bit 4: Initialization status flag This bit is set by hardware when the calendar year field is different from 0 (Power-on reset state)..

RSF

Bit 5: Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSR, RTC_TR and RTC_DR). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF = 1), or when in bypass shadow register mode (BYPSHAD = 1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode..

INITF

Bit 6: Initialization flag When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated..

INIT

Bit 7: Initialization mode.

RECALPF

Bit 16: Recalibration pending Flag The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0. Refer to ..

PRER

RTC prescaler register

Offset: 0x10, size: 32, reset: 0x007F00FF, access: Unspecified

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									PREDIV_A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	PREDIV_S rw

Toggle fields

PREDIV_S

Bits 0-14: Synchronous prescaler factor This is the synchronous division factor: ck_spre frequency = ck_apre frequency/(PREDIV_S+1).

PREDIV_A

Bits 16-22: Asynchronous prescaler factor This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1).

CR

RTC control register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/18 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OUT2EN rw	TAMPALRM_TYPE rw	TAMPALRM_PU rw						COE rw	OSEL rw		POL rw	COSEL rw	BKP rw	SUB1H w	ADD1H w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TSIE rw			ALRAIE rw	TSE rw			ALRAE rw		FMT rw	BYPSHAD rw	REFCKON rw	TSEDGE rw

Toggle fields

TSEDGE

Bit 3: Timestamp event active edge TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting..

REFCKON

Bit 4: RTC_REFIN reference clock detection enable (50 or 60 Hz) Note: PREDIV_S must be 0x00FF..

BYPSHAD

Bit 5: Bypass the shadow registers Note: If the frequency of the APB1 clock is less than seven times the frequency of RTCCLK, BYPSHAD must be set to 1..

FMT

Bit 6: Hour format.

ALRAE

Bit 8: Alarm A enable.

TSE

Bit 11: timestamp enable.

ALRAIE

Bit 12: Alarm A interrupt enable.

TSIE

Bit 15: Timestamp interrupt enable.

ADD1H

Bit 16: Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0..

SUB1H

Bit 17: Subtract 1 hour (winter time change) When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. Setting this bit has no effect when current hour is 0..

BKP

Bit 18: Backup This bit can be written by the user to memorize whether the daylight saving time change has been performed or not..

COSEL

Bit 19: Calibration output selection When COE = 1, this bit selects which signal is output on CALIB. These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values (PREDIV_A = 127 and PREDIV_S = 255). Refer to ..

POL

Bit 20: Output polarity This bit is used to configure the polarity of TAMPALRM output..

OSEL

Bits 21-22: Output selection These bits are used to select the flag to be routed to TAMPALRM output..

COE

Bit 23: Calibration output enable This bit enables the CALIB output.

TAMPALRM_PU

Bit 29: TAMPALRM pull-up enable.

TAMPALRM_TYPE

Bit 30: TAMPALRM output type.

OUT2EN

Bit 31: RTC_OUT2 output enable Setting this bit allows to remap the RTC outputs on RTC_OUT2 as follows: OUT2EN = 0: RTC output 2 disable If OSEL different of 00 or TAMPOE = 1: TAMPALRM is output on RTC_OUT1 If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT1 OUT2EN = 1: RTC output 2 enable If (OSEL different of 00 or TAMPOE = 1) and COE = 0: TAMPALRM is output on RTC_OUT2 If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT2 If (OSELdifferent of 00 or TAMPOE = 1) and COE = 1: CALIB is output on RTC_OUT2 and TAMPALRM is output on RTC_OUT1..

WPR

RTC write protection register

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								KEY w

Toggle fields

KEY

Bits 0-7: Write protection key This byte is written by software. Reading this byte always returns 0x00. Refer to for a description of how to unlock RTC register write protection..

CALR

RTC calibration register

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CALP rw	CALW8 rw	CALW16 rw					CALM rw

Toggle fields

CALM

Bits 0-8: Calibration minus The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32 seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar with a resolution of 0.9537 ppm. To increase the frequency of the calendar, this feature should be used in conjunction with CALP. See ..

CALW16

Bit 13: Use a 16-second calibration cycle period When CALW16 is set to 1, the 16-second calibration cycle period is selected. This bit must not be set to 1 if CALW8 = 1. Note: CALM[0] is stuck at 0 when CALW16 = 1. Refer to calibration..

CALW8

Bit 14: Use an 8-second calibration cycle period When CALW8 is set to 1, the 8-second calibration cycle period is selected. Note: CALM[1:0] are stuck at 00 when CALW8 = 1. Refer to digital calibration..

CALP

Bit 15: Increase frequency of RTC by 488.5 ppm This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of RTCCLK pulses added during a 32-second window is calculated as follows: (512 CALP) - CALM. Refer to ..

SHIFTR

RTC shift control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD1S w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SUBFS w

Toggle fields

SUBFS

Bits 0-14: Subtract a fraction of a second These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). The value which is written to SUBFS is added to the synchronous prescaler counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by: Delay (seconds) = SUBFS / (PREDIV_S + 1) A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by: Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))). Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF = 1 to be sure that the shadow registers have been updated with the shifted time..

ADD1S

Bit 31: Add one second This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation..

TSTR

RTC timestamp time register

Offset: 0x30, size: 32, reset: 0x00000000, access: Unspecified

7/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									PM r	HT r		HU r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MNT r			MNU r					ST r			SU r

Toggle fields

SU

Bits 0-3: Second units in BCD format..

ST

Bits 4-6: Second tens in BCD format..

MNU

Bits 8-11: Minute units in BCD format..

MNT

Bits 12-14: Minute tens in BCD format..

HU

Bits 16-19: Hour units in BCD format..

HT

Bits 20-21: Hour tens in BCD format..

PM

Bit 22: AM/PM notation.

TSDR

RTC timestamp date register

Offset: 0x34, size: 32, reset: 0x00000000, access: Unspecified

5/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WDU r			MT r	MU r						DT r		DU r

Toggle fields

DU

Bits 0-3: Date units in BCD format.

DT

Bits 4-5: Date tens in BCD format.

MU

Bits 8-11: Month units in BCD format.

MT

Bit 12: Month tens in BCD format.

WDU

Bits 13-15: Week day units.

TSSSR

RTC timestamp sub second register

Offset: 0x38, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SS r

Toggle fields

SS

Bits 0-15: Sub second value SS[15:0] is the value of the synchronous prescaler counter when the timestamp event occurred..

ALRMAR

RTC alarm A register

Offset: 0x40, size: 32, reset: 0x00000000, access: Unspecified

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MSK4 rw	WDSEL rw	DT rw		DU rw				MSK3 rw	PM rw	HT rw		HU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MSK2 rw	MNT rw			MNU rw				MSK1 rw	ST rw			SU rw

Toggle fields

SU

Bits 0-3: Second units in BCD format..

ST

Bits 4-6: Second tens in BCD format..

MSK1

Bit 7: Alarm A seconds mask.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

MSK2

Bit 15: Alarm A minutes mask.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

MSK3

Bit 23: Alarm A hours mask.

DU

Bits 24-27: Date units or day in BCD format.

DT

Bits 28-29: Date tens in BCD format.

WDSEL

Bit 30: Week day selection.

MSK4

Bit 31: Alarm A date mask.

ALRMASSR

RTC alarm A sub second register

Offset: 0x44, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				MASKSS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SS rw

Toggle fields

SS

Bits 0-14: Sub seconds value This value is compared with the contents of the synchronous prescaler counter to determine if alarm A is to be activated. Only bits 0 up MASKSS-1 are compared..

MASKSS

Bits 24-27: Mask the most-significant bits starting at this bit 2: SS[14:2] are dont care in alarm A comparison. Only SS[1:0] are compared. 3: SS[14:3] are dont care in alarm A comparison. Only SS[2:0] are compared. ... 12: SS[14:12] are dont care in alarm A comparison. SS[11:0] are compared. 13: SS[14:13] are dont care in alarm A comparison. SS[12:0] are compared. 14: SS[14] is dont care in alarm A comparison. SS[13:0] are compared. 15: All 15 SS bits are compared and must match to activate alarm. The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. Note: The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation..

SR

RTC status register

Offset: 0x50, size: 32, reset: 0x00000000, access: Unspecified

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											TSOVF r	TSF r			ALRAF r

Toggle fields

ALRAF

Bit 0: Alarm A flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the alarm A register (RTC_ALRMAR)..

TSF

Bit 3: Timestamp flag This flag is set by hardware when a timestamp event occurs..

TSOVF

Bit 4: Timestamp overflow flag This flag is set by hardware when a timestamp event occurs while TSF is already set. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared..

MISR

RTC masked interrupt status register

Offset: 0x54, size: 32, reset: 0x00000000, access: Unspecified

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											TSOVMF r	TSMF r			ALRAMF r

Toggle fields

ALRAMF

Bit 0: Alarm A masked flag This flag is set by hardware when the alarm A interrupt occurs..

TSMF

Bit 3: Timestamp masked flag This flag is set by hardware when a timestamp interrupt occurs..

TSOVMF

Bit 4: Timestamp overflow masked flag This flag is set by hardware when a timestamp interrupt occurs while TSMF is already set. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared..

SCR

RTC status clear register

Offset: 0x5c, size: 32, reset: 0x00000000, access: Unspecified

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											CTSOVF w	CTSF w			CALRAF w

Toggle fields

CALRAF

Bit 0: Clear alarm A flag Writing 1 in this bit clears the ALRAF bit in the RTC_SR register..

CTSF

Bit 3: Clear timestamp flag Writing 1 in this bit clears the TSOVF bit in the RTC_SR register..

CTSOVF

Bit 4: Clear timestamp overflow flag Writing 1 in this bit clears the TSOVF bit in the RTC_SR register. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared..

SPI1

0x40013000: Serial peripheral interface

13/54 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0 (16-bit)	CR1	BIDIMODE	BIDIOE	CRCEN	CRCNEXT	CRCL	RXONLY	SSM	SSI	LSBFIRST	SPE	BR			MSTR	CPOL	CPHA
0x4 (16-bit)	CR2		LDMA_TX	LDMA_RX	FRXTH	DS				TXEIE	RXNEIE	ERRIE	FRF	NSSP	SSOE	TXDMAEN	RXDMAEN
0x8 (16-bit)	SR				FTLVL		FRLVL		FRE	BSY	OVR	MODF	CRCERR	UDR	CHSIDE	TXE	RXNE
0xc (16-bit)	DR	DR
0xc (8-bit)	DR8									DR
0x10 (16-bit)	CRCPR	CRCPOLY
0x14 (16-bit)	RXCRCR	RXCRC
0x18 (16-bit)	TXCRCR	TXCRC
0x1c (16-bit)	I2SCFGR				ASTRTEN	I2SMOD	I2SE	I2SCFG		PCMSYNC		I2SSTD		CKPOL	DATLEN		CHLEN
0x20 (16-bit)	I2SPR							MCKOE	ODD	I2SDIV

Toggle registers

CR1

SPI control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: Unspecified

0/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIDIMODE rw	BIDIOE rw	CRCEN rw	CRCNEXT rw	CRCL rw	RXONLY rw	SSM rw	SSI rw	LSBFIRST rw	SPE rw	BR rw			MSTR rw	CPOL rw	CPHA rw

Toggle fields

CPHA

Bit 0: Clock phase Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode and SPI TI mode except the case when CRC is applied at TI mode..

CPOL

Bit 1: Clock polarity Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode and SPI TI mode except the case when CRC is applied at TI mode..

MSTR

Bit 2: Master selection Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode..

BR

Bits 3-5: Baud rate control Note: These bits should not be changed when communication is ongoing. These bits are not used in I2S mode..

SPE

Bit 6: SPI enable Note: When disabling the SPI, follow the procedure described in SPI on page 1349. This bit is not used in I2S mode..

LSBFIRST

Bit 7: Frame format Note: 1. This bit should not be changed when communication is ongoing. 2. This bit is not used in I2S mode and SPI TI mode..

SSI

Bit 8: Internal slave select This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored. Note: This bit is not used in I2S mode and SPI TI mode..

SSM

Bit 9: Software slave management When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. Note: This bit is not used in I2S mode and SPI TI mode..

RXONLY

Bit 10: Receive only mode enabled. This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. Note: This bit is not used in I2S mode..

CRCL

Bit 11: CRC length This bit is set and cleared by software to select the CRC length. Note: This bit should be written only when SPI is disabled (SPE = 0) for correct operation. This bit is not used in I2S mode..

CRCNEXT

Bit 12: Transmit CRC next Note: This bit has to be written as soon as the last data is written in the SPI_DR register. This bit is not used in I2S mode..

CRCEN

Bit 13: Hardware CRC calculation enable Note: This bit should be written only when SPI is disabled (SPE = 0) for correct operation. This bit is not used in I2S mode..

BIDIOE

Bit 14: Output enable in bidirectional mode This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode. Note: In master mode, the MOSI pin is used and in slave mode, the MISO pin is used. This bit is not used in I2S mode..

BIDIMODE

Bit 15: Bidirectional data mode enable. This bit enables half-duplex communication using common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is active. Note: This bit is not used in I2S mode..

CR2

SPI control register 2

Offset: 0x4, size: 16, reset: 0x00000700, access: Unspecified

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	LDMA_TX rw	LDMA_RX rw	FRXTH rw	DS rw				TXEIE rw	RXNEIE rw	ERRIE rw	FRF rw	NSSP rw	SSOE rw	TXDMAEN rw	RXDMAEN rw

Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable When this bit is set, a DMA request is generated whenever the RXNE flag is set..

TXDMAEN

Bit 1: Tx buffer DMA enable When this bit is set, a DMA request is generated whenever the TXE flag is set..

SSOE

Bit 2: SS output enable Note: This bit is not used in I2S mode and SPI TI mode..

NSSP

Bit 3: NSS pulse management This bit is used in master mode only. it allows the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. It has no meaning if CPHA = 1, or FRF = 1. Note: 1. This bit must be written only when the SPI is disabled (SPE=0). 2. This bit is not used in I2S mode and SPI TI mode..

FRF

Bit 4: Frame format 1 SPI TI mode Note: This bit must be written only when the SPI is disabled (SPE=0). This bit is not used in I2S mode..

ERRIE

Bit 5: Error interrupt enable This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode and UDR, OVR, and FRE in I2S mode)..

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

TXEIE

Bit 7: Tx buffer empty interrupt enable.

DS

Bits 8-11: Data size These bits configure the data length for SPI transfers. If software attempts to write one of the Not used values, they are forced to the value 0111 (8-bit) Note: These bits are not used in I2S mode..

FRXTH

Bit 12: FIFO reception threshold This bit is used to set the threshold of the RXFIFO that triggers an RXNE event Note: This bit is not used in I2S mode..

LDMA_RX

Bit 13: Last DMA transfer for reception This bit is used in data packing mode, to define if the total number of data to receive by DMA is odd or even. It has significance only if the RXDMAEN bit in the SPI_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPI_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPI_CR1 register). Note: Refer to if the CRCEN bit is set. This bit is not used in IS mode..

LDMA_TX

Bit 14: Last DMA transfer for transmission This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even. It has significance only if the TXDMAEN bit in the SPI_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPI_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPI_CR1 register). Note: Refer to if the CRCEN bit is set. This bit is not used in IS mode..

SR

SPI status register

Offset: 0x8, size: 16, reset: 0x00000002, access: Unspecified

10/11 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			FTLVL r		FRLVL r		FRE r	BSY r	OVR r	MODF r	CRCERR rw	UDR r	CHSIDE r	TXE r	RXNE r

Toggle fields

RXNE

Bit 0: Receive buffer not empty.

TXE

Bit 1: Transmit buffer empty.

CHSIDE

Bit 2: Channel side Note: This bit is not used in SPI mode. It has no significance in PCM mode..

UDR

Bit 3: Underrun flag This flag is set by hardware and reset by a software sequence. Refer to page 1385 for the software sequence. Note: This bit is not used in SPI mode..

CRCERR

Bit 4: CRC error flag Note: This flag is set by hardware and cleared by software writing 0. This bit is not used in I2S mode..

MODF

Bit 5: Mode fault This flag is set by hardware and reset by a software sequence. Refer to (MODF) on page 1359 for the software sequence. Note: This bit is not used in I2S mode..

OVR

Bit 6: Overrun flag This flag is set by hardware and reset by a software sequence. Refer to page 1385 for the software sequence..

BSY

Bit 7: Busy flag This flag is set and cleared by hardware. Note: The BSY flag must be used with caution: refer to and ..

FRE

Bit 8: Frame format error This flag is used for SPI in TI slave mode and I2S slave mode. Refer to error flags and . This flag is set by hardware and reset when SPI_SR is read by software..

FRLVL

Bits 9-10: FIFO reception level These bits are set and cleared by hardware. Note: These bits are not used in IS mode and in SPI receive-only mode while CRC calculation is enabled..

FTLVL

Bits 11-12: FIFO transmission level These bits are set and cleared by hardware. Note: This bit is not used in I2S mode..

DR

SPI data register

Offset: 0xc, size: 16, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR rw

Toggle fields

DR

Bits 0-15: Data register Data received or to be transmitted The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See ). Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used..

DR8

Direct 8-bit access to data register

Offset: 0xc, size: 8, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								DR rw

Toggle fields

DR

Bits 0-7: Data register.

Allowed values: 0x0-0xff

CRCPR

SPI CRC polynomial register

Offset: 0x10, size: 16, reset: 0x00000007, access: Unspecified

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRCPOLY rw

Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register This register contains the polynomial for the CRC calculation. The CRC polynomial (0x0007) is the reset value of this register. Another polynomial can be configured as required..

RXCRCR

SPI Rx CRC register

Offset: 0x14, size: 16, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXCRC r

Toggle fields

RXCRC

Bits 0-15: Rx CRC register When CRC calculation is enabled, the RXCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPI_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPR register. Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPI_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPI_CR1 register is set). CRC calculation is done based on any CRC16 standard. Note: A read to this register when the BSY Flag is set could return an incorrect value. These bits are not used in I2S mode..

TXCRCR

SPI Tx CRC register

Offset: 0x18, size: 16, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TXCRC r

Toggle fields

TXCRC

Bits 0-15: Tx CRC register When CRC calculation is enabled, the TXCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPI_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPR register. Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPI_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPI_CR1 register is set). CRC calculation is done based on any CRC16 standard. Note: A read to this register when the BSY flag is set could return an incorrect value. These bits are not used in I2S mode..

I2SCFGR

SPI_I2S configuration register

Offset: 0x1c, size: 16, reset: 0x00000000, access: Unspecified

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ASTRTEN rw	I2SMOD rw	I2SE rw	I2SCFG rw		PCMSYNC rw		I2SSTD rw		CKPOL rw	DATLEN rw		CHLEN rw

Toggle fields

CHLEN

Bit 0: Channel length (number of bits per audio channel) The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. Note: For correct operation, this bit should be configured when the I2S is disabled. It is not used in SPI mode..

DATLEN

Bits 1-2: Data length to be transferred Note: For correct operation, these bits should be configured when the I2S is disabled. They are not used in SPI mode..

CKPOL

Bit 3: Inactive state clock polarity Note: For correct operation, this bit should be configured when the I2S is disabled. It is not used in SPI mode. The bit CKPOL does not affect the CK edge sensitivity used to receive or transmit the SD and WS signals..

I2SSTD

Bits 4-5: I2S standard selection For more details on I2S standards, refer to Note: For correct operation, these bits should be configured when the I2S is disabled. They are not used in SPI mode..

PCMSYNC

Bit 7: PCM frame synchronization Note: This bit has a meaning only if I2SSTD = 11 (PCM standard is used). It is not used in SPI mode..

I2SCFG

Bits 8-9: I2S configuration mode Note: These bits should be configured when the I2S is disabled. They are not used in SPI mode..

I2SE

Bit 10: I2S enable Note: This bit is not used in SPI mode..

I2SMOD

Bit 11: I2S mode selection Note: This bit should be configured when the SPI is disabled..

ASTRTEN

Bit 12: Asynchronous start enable. When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and an appropriate transition is detected on the WS signal. When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and the appropriate level is detected on the WS signal. Note: The appropriate transition is a falling edge on WS signal when I2S Philips Standard is used, or a rising edge for other standards. The appropriate level is a low level on WS signal when I2S Philips Standard is used, or a high level for other standards. Please refer to for additional information..

I2SPR

SPI_I2S prescaler register

Offset: 0x20, size: 16, reset: 0x00000002, access: Unspecified

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						MCKOE rw	ODD rw	I2SDIV rw

Toggle fields

I2SDIV

Bits 0-7: I2S linear prescaler I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values. Refer to . Note: These bits should be configured when the I2S is disabled. They are used only when the I2S is in master mode. They are not used in SPI mode..

ODD

Bit 8: Odd factor for the prescaler Refer to . Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. It is not used in SPI mode..

MCKOE

Bit 9: Master clock output enable Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. It is not used in SPI mode..

SYSCFG

0x40010000: SYSCFG register block

38/58 fields covered.

Toggle register map

Offset	Name	24	23	22	20	19	18	17	16	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CFGR1	I2C_PC14_FMP	I2C_PA10_FMP	I2C_PA9_FMP	I2C1_FMP	I2C_PB9_FMP	I2C_PB8_FMP	I2C_PB7_FMP	I2C_PB6_FMP					IR_MOD		IR_POL	PA12_RMP	PA11_RMP		MEM_MODE
0x18	CFGR2																				LOCKUP_LOCK
0x3c	CFGR3									PINMUX5		PINMUX4		PINMUX3		PINMUX2		PINMUX1		PINMUX0
0x80	ITLINE0																				WWDG
0x88	ITLINE2																			RTC
0x8c	ITLINE3																			FLASH_ITF
0x90	ITLINE4																				RCC
0x94	ITLINE5																			EXTI1	EXTI0
0x98	ITLINE6																			EXTI3	EXTI2
0x9c	ITLINE7									EXTI15	EXTI14	EXTI13	EXTI12	EXTI11	EXTI10	EXTI9	EXTI8	EXTI7	EXTI6	EXTI5	EXTI4
0xa4	ITLINE9																				DMA1_CH1
0xa8	ITLINE10																			DMA1_CH3	DMA1_CH2
0xac	ITLINE11																				DMAMUX
0xb0	ITLINE12																				ADC
0xb4	ITLINE13																	TIM1_BRK	TIM1_UPD	TIM1_TRG	TIM1_CCU
0xb8	ITLINE14																				TIM1_CC
0xc0	ITLINE16																				TIM3
0xcc	ITLINE19																				TIM14
0xd4	ITLINE21																				TIM16
0xd8	ITLINE22																				TIM17
0xdc	ITLINE23																				I2C1
0xe4	ITLINE25																				SPI1
0xec	ITLINE27																				USART1
0xf0	ITLINE28																				USART2

Toggle registers

CFGR1

SYSCFG configuration register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							I2C_PC14_FMP rw	I2C_PA10_FMP rw	I2C_PA9_FMP rw		I2C1_FMP rw	I2C_PB9_FMP rw	I2C_PB8_FMP rw	I2C_PB7_FMP rw	I2C_PB6_FMP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IR_MOD rw		IR_POL rw	PA12_RMP rw	PA11_RMP rw		MEM_MODE rw

Toggle fields

MEM_MODE

Bits 0-1: Memory mapping selection bits This bitfield controlled by software selects the memory internally mapped at the address 0x0000 0000. Its reset value is determined by the boot mode configuration. Refer to for more details. x0: Main Flash memory.

PA11_RMP

Bit 3: PA11 pin remapping This bit is set and cleared by software. When set, it remaps the PA11 pin to operate as PA9 GPIO port, instead as PA11 GPIO port..

PA12_RMP

Bit 4: PA12 pin remapping This bit is set and cleared by software. When set, it remaps the PA12 pin to operate as PA10 GPIO port, instead as PA12 GPIO port..

IR_POL

Bit 5: IR output polarity selection.

IR_MOD

Bits 6-7: IR Modulation Envelope signal selection This bitfield selects the signal for IR modulation envelope:.

I2C_PB6_FMP

Bit 16: Fast Mode Plus (FM+) enable for PB6 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB6 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored..

I2C_PB7_FMP

Bit 17: Fast Mode Plus (FM+) enable for PB7 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB7 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored..

I2C_PB8_FMP

Bit 18: Fast Mode Plus (FM+) enable for PB8 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB8 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored..

I2C_PB9_FMP

Bit 19: Fast Mode Plus (FM+) enable for PB9 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB9 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored..

I2C1_FMP

Bit 20: Fast Mode Plus (FM+) enable for I2C1 This bit is set and cleared by software. It enables I2C FM+ driving capability on I/O ports configured as I2C1 through GPIOx_AFR registers. With this bit in disable state, the I2C FM+ driving capability on I/O ports configured as I2C1 can be enabled through their corresponding I2Cx_FMP bit. When I2C FM+ is enabled, the speed control is ignored..

I2C_PA9_FMP

Bit 22: Fast Mode Plus (FM+) enable for PA9 This bit is set and cleared by software. It enables I2C FM+ driving capability on PA9 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored..

I2C_PA10_FMP

Bit 23: Fast Mode Plus (FM+) enable for PA10 This bit is set and cleared by software. It enables I2C FM+ driving capability on PA10 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored..

I2C_PC14_FMP

Bit 24: Fast Mode Plus (FM+) enable for PC14 This bit is set and cleared by software. It enables I2C FM+ driving capability on PC14 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored..

CFGR2

SYSCFG configuration register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															LOCKUP_LOCK rw

Toggle fields

LOCKUP_LOCK

Bit 0: Cortex<Superscript><Default Font>-M0+ LOCKUP enable This bit is set by software and cleared by system reset. When set, it enables the connection of Cortex<Superscript><Default Font>-M0+ LOCKUP (HardFault) output to the TIM1/16/17 Break input..

CFGR3

SYSCFG configuration register 3

Offset: 0x3c, size: 32, reset: 0x00000000, access: Unspecified

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				PINMUX5 rw		PINMUX4 rw		PINMUX3 rw		PINMUX2 rw		PINMUX1 rw		PINMUX0 rw

Toggle fields

PINMUX0

Bits 0-1: Pin GPIO multiplexer 0 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. 1x: Reserved Pin F2 of WLCSP14 package GPIO assignment 1x: Reserved.

PINMUX1

Bits 2-3: Pin GPIO multiplexer 1 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. 1x: Reserved.

PINMUX2

Bits 4-5: Pin GPIO multiplexer 2 This bit is set by software and cleared by system reset. It assigns a GPIO to a pin. 1x: Reserved 1x: Reserved.

PINMUX3

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														EXTI1 r	EXTI0 r

Toggle fields

EXTI0

Bit 0: EXTI line 0 interrupt request pending.

EXTI1

Bit 1: EXTI line 1 interrupt request pending.

ITLINE6

SYSCFG interrupt line 6 status register

Offset: 0x98, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														EXTI3 r	EXTI2 r

Toggle fields

EXTI2

Bit 0: EXTI line 2 interrupt request pending.

EXTI3

Bit 1: EXTI line 3 interrupt request pending.

ITLINE7

SYSCFG interrupt line 7 status register

Offset: 0x9c, size: 32, reset: 0x00000000, access: Unspecified

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				EXTI15 r	EXTI14 r	EXTI13 r	EXTI12 r	EXTI11 r	EXTI10 r	EXTI9 r	EXTI8 r	EXTI7 r	EXTI6 r	EXTI5 r	EXTI4 r

Toggle fields

EXTI4

Bit 0: EXTI line 4 interrupt request pending.

EXTI5

Bit 1: EXTI line 5 interrupt request pending.

EXTI6

Bit 2: EXTI line 6 interrupt request pending.

EXTI7

Bit 3: EXTI line 7 interrupt request pending.

EXTI8

Bit 4: EXTI line 8 interrupt request pending.

EXTI9

Bit 5: EXTI line 9 interrupt request pending.

EXTI10

Bit 6: EXTI line 10 interrupt request pending.

EXTI11

Bit 7: EXTI line 11 interrupt request pending.

EXTI12

Bit 8: EXTI line 12 interrupt request pending.

EXTI13

Bit 9: EXTI line 13 interrupt request pending.

EXTI14

Bit 10: EXTI line 14 interrupt request pending.

EXTI15

Bit 11: EXTI line 15 interrupt request pending.

ITLINE9

SYSCFG interrupt line 9 status register

Offset: 0xa4, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															DMA1_CH1 r

Toggle fields

DMA1_CH1

Bit 0: DMA1 channel 1interrupt request pending.

ITLINE10

SYSCFG interrupt line 10 status register

Offset: 0xa8, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														DMA1_CH3 r	DMA1_CH2 r

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												TIM1_BRK r	TIM1_UPD r	TIM1_TRG r	TIM1_CCU r

Toggle fields

TIM1_CCU

Bit 0: Timer 1 commutation interrupt request pending.

TIM1_TRG

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0 (16-bit)	CR1																				UIFREMAP		CKD		ARPE	CMS		DIR	OPM	URS	UDIS	CEN
0x4	CR2									MMS2				OIS6		OIS5		OIS4	OIS3N	OIS3	OIS2N	OIS2	OIS1N	OIS1	TI1S	MMS			CCDS	CCUS		CCPC
0x8	SMCR										TS2					SMS2	ETP	ECE	ETPS		ETF				MSM	TS1			OCCS	SMS1
0xc (16-bit)	DIER																	TDE	COMDE	CC4DE	CC3DE	CC2DE	CC1DE	UDE	BIE	TIE	COMIE	CC4IE	CC3IE	CC2IE	CC1IE	UIE
0x10	SR														CC6IF	CC5IF			SBIF	CC4OF	CC3OF	CC2OF	CC1OF	B2IF	BIF	TIF	COMIF	CC4IF	CC3IF	CC2IF	CC1IF	UIF
0x14 (16-bit)	EGR																							B2G	BG	TG	COMG	CC4G	CC3G	CC2G	CC1G	UG
0x18	CCMR1_Input																IC2F				IC2PSC		CC2S		IC1F				IC1PSC		CC1S
0x18	CCMR1_Output								OC2M_3							OC1M_3	OC2CE	OC2M			OC2PE	OC2FE	CC2S		OC1CE	OC1M			OC1PE	OC1FE	CC1S
0x1c	CCMR2_Input																IC4F				IC4PSC		CC4S		IC3F				IC3PSC		CC3S
0x1c	CCMR2_Output								OC4M2							OC3M2	OC4CE	OC4M1			OC4PE	OC4FE	CC4S		OC3CE	OC3M1			OC3PE	OC3FE	CC3S
0x20	CCER										CC6P	CC6E			CC5P	CC5E	CC4NP		CC4P	CC4E	CC3NP	CC3NE	CC3P	CC3E	CC2NP	CC2NE	CC2P	CC2E	CC1NP	CC1NE	CC1P	CC1E
0x24	CNT	UIFCPY															CNT
0x28 (16-bit)	PSC																PSC
0x2c (16-bit)	ARR																ARR
0x30 (16-bit)	RCR																REP
0x34 (16-bit)	CCR1																CCR1
0x38 (16-bit)	CCR2																CCR2
0x3c (16-bit)	CCR3																CCR3
0x40 (16-bit)	CCR4																CCR4
0x44	BDTR			BK2BID	BKBID	BK2DSRM	BKDSRM	BK2P	BK2E	BK2F			BKF				MOE	AOE	BKP	BKE	OSSR	OSSI	LOCK		DTG
0x48 (16-bit)	DCR																			DBL								DBA
0x4c	DMAR	DMAB															DMAB
0x54	CCMR3								OC6M2							OC5M2	OC6CE	OC6M1			OC6PE	OC6FE			OC5CE	OC5M1			OC5PE	OC5FE
0x58	CCR5	GC5C3	GC5C2	GC5C1													CCR5
0x5c (16-bit)	CCR6																CCR6
0x60	AF1														ETRSEL		ETRSEL						BKINP									BKINE
0x64	AF2																						BK2INP									BK2INE
0x68	TISEL					TI4SEL							TI3SEL								TI2SEL								TI1SEL

Toggle registers

CR1

TIM1 control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: Unspecified

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				UIFREMAP rw		CKD rw		ARPE rw	CMS rw		DIR rw	OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware..

UDIS

Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..

URS

Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.

OPM

Bit 3: One pulse mode.

DIR

Bit 4: Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode..

CMS

Bits 5-6: Center-aligned mode selection Note: Switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) is not allowed.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (ETR, TIx): Note: tDTS = 1/fDTS, tCK_INT = 1/fCK_INT..

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

TIM1 control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								MMS2 rw					OIS6 rw		OIS5 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	OIS4 rw	OIS3N rw	OIS3 rw	OIS2N rw	OIS2 rw	OIS1N rw	OIS1 rw	TI1S rw	MMS rw			CCDS rw	CCUS rw		CCPC rw

Toggle fields

CCPC

Bit 0: Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output..

CCUS

Bit 2: Capture/compare control update selection Note: This bit acts only on channels that have a complementary output..

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection These bits allow selected information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer..

TI1S

Bit 7: TI1 selection.

OIS1

Bit 8: Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..

OIS1N

Bit 9: Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..

OIS2

Bit 10: Output Idle state 2 (OC2 output) Refer to OIS1 bit.

OIS2N

Bit 11: Output Idle state 2 (OC2N output) Refer to OIS1N bit.

OIS3

Bit 12: Output Idle state 3 (OC3 output) Refer to OIS1 bit.

OIS3N

Bit 13: Output Idle state 3 (OC3N output) Refer to OIS1N bit.

OIS4

Bit 14: Output Idle state 4 (OC4 output) Refer to OIS1 bit.

OIS5

Bit 16: Output Idle state 5 (OC5 output) Refer to OIS1 bit.

OIS6

Bit 18: Output Idle state 6 (OC6 output) Refer to OIS1 bit.

MMS2

Bits 20-23: Master mode selection 2 These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer..

SMCR

TIM1 slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										TS2 rw					SMS2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETP rw	ECE rw	ETPS rw		ETF rw				MSM rw	TS1 rw			OCCS rw	SMS1 rw

Toggle fields

SMS1

Bits 0-2: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..

OCCS

Bit 3: OCREF clear selection This bit is used to select the OCREF clear source..

TS1

Bits 4-6: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..

MSM

Bit 7: Master/slave mode.

ETF

Bits 8-11: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.

ETPS

Bits 12-13: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of fCK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks..

ECE

Bit 14: External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF..

ETP

Bit 15: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations.

SMS2

Bit 16: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..

TS2

Bits 20-21: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..

DIER

TIM1 DMA/interrupt enable register

Offset: 0xc, size: 16, reset: 0x00000000, access: Unspecified

0/15 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDE rw	COMDE rw	CC4DE rw	CC3DE rw	CC2DE rw	CC1DE rw	UDE rw	BIE rw	TIE rw	COMIE rw	CC4IE rw	CC3IE rw	CC2IE rw	CC1IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

TIM1 status register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														CC6IF rw	CC5IF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SBIF rw	CC4OF rw	CC3OF rw	CC2OF rw	CC1OF rw	B2IF rw	BIF rw	TIF rw	COMIF rw	CC4IF rw	CC3IF rw	CC2IF rw	CC1IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM1_SMCRTIMx_SMCR)N/A), if URS=0 and UDIS=0 in the TIMx_CR1 register..

CC1IF

Bit 1: Capture/Compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when he content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER)..

CC2IF

Bit 2: Capture/Compare 2 interrupt flag Refer to CC1IF description.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag Refer to CC1IF description.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag Refer to CC1IF description.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software..

BIF

Bit 7: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active..

B2IF

Bit 8: Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active..

CC1OF

Bit 9: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to 0..

CC2OF

Bit 10: Capture/Compare 2 overcapture flag Refer to CC1OF description.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag Refer to CC1OF description.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag Refer to CC1OF description.

SBIF

Bit 13: System Break interrupt flag This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. This flag must be reset to re-start PWM operation..

CC5IF

Bit 16: Compare 5 interrupt flag Refer to CC1IF description (Note: Channel 5 can only be configured as output).

CC6IF

Bit 17: Compare 6 interrupt flag Refer to CC1IF description (Note: Channel 6 can only be configured as output).

EGR

TIM1 event generation register

Offset: 0x14, size: 16, reset: 0x00000000, access: Unspecified

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							B2G w	BG w	TG w	COMG w	CC4G w	CC3G w	CC2G w	CC1G w	UG w

Toggle fields

UG

Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..

CC1G

Bit 1: Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high..

CC2G

Bit 2: Capture/Compare 2 generation Refer to CC1G description.

CC3G

Bit 3: Capture/Compare 3 generation Refer to CC1G description.

CC4G

Bit 4: Capture/Compare 4 generation Refer to CC1G description.

COMG

Bit 5: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware Note: This bit acts only on channels having a complementary output..

TG

Bit 6: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..

BG

Bit 7: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..

B2G

Bit 8: Break 2 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..

CCMR1_Input

TIM1 capture/compare mode register 1 [alternate]

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC2F rw				IC2PSC rw		CC2S rw		IC1F rw				IC1PSC rw		CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER)..

IC1PSC

Bits 2-3: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=0 (TIMx_CCER register)..

IC1F

Bits 4-7: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.

CC2S

Bits 8-9: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER)..

IC2PSC

Bits 10-11: Input capture 2 prescaler Refer to IC1PSC[1:0] description..

IC2F

Bits 12-15: Input capture 2 filter Refer to IC1F[3:0] description..

CCMR1_Output

TIM1 capture/compare mode register 1 [alternate]

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC2M_3 rw								OC1M_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC2CE rw	OC2M rw			OC2PE rw	OC2FE rw	CC2S rw		OC1CE rw	OC1M rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER)..

OC1FE

Bit 2: Output Compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger..

OC1PE

Bit 3: Output Compare 1 preload enable Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in output). The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed..

OC1M

Bits 4-6: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in output). Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from frozen mode to PWM mode. Note: On channels having a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. Note: The OC1M[3] bit is not contiguous, located in bit 16..

OC1CE

Bit 7: Output Compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER)..

OC2FE

Bit 10: Output Compare 2 fast enable Refer to OC1FE description..

OC2PE

Bit 11: Output Compare 2 preload enable Refer to OC1PE description..

OC2M

Bits 12-14: Output Compare 2 mode Refer to OC1M[3:0] description..

OC2CE

Bit 15: Output Compare 2 clear enable Refer to OC1CE description..

OC1M_3

Bit 16: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in output). Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from frozen mode to PWM mode. Note: On channels having a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. Note: The OC1M[3] bit is not contiguous, located in bit 16..

OC2M_3

Bit 24: Output Compare 2 mode Refer to OC1M[3:0] description..

CCMR2_Input

TIM1 capture/compare mode register 2 [alternate]

Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC4F rw				IC4PSC rw		CC4S rw		IC3F rw				IC3PSC rw		CC3S rw

Toggle fields

CC3S

Bits 0-1: Capture/compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER)..

IC3PSC

Bits 2-3: Input capture 3 prescaler Refer to IC1PSC[1:0] description..

IC3F

Bits 4-7: Input capture 3 filter Refer to IC1F[3:0] description..

CC4S

Bits 8-9: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER)..

IC4PSC

Bits 10-11: Input capture 4 prescaler Refer to IC1PSC[1:0] description..

IC4F

Bits 12-15: Input capture 4 filter Refer to IC1F[3:0] description..

CCMR2_Output

TIM1 capture/compare mode register 2 [alternate]

Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC4M2 rw								OC3M2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC4CE rw	OC4M1 rw			OC4PE rw	OC4FE rw	CC4S rw		OC3CE rw	OC3M1 rw			OC3PE rw	OC3FE rw	CC3S rw

Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER)..

OC3FE

Bit 2: Output compare 3 fast enable Refer to OC1FE description..

OC3PE

Bit 3: Output compare 3 preload enable Refer to OC1PE description..

OC3M1

Bits 4-6: Output compare 3 mode Refer to OC1M[3:0] description..

OC3CE

Bit 7: Output compare 3 clear enable Refer to OC1CE description..

CC4S

Bits 8-9: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER)..

OC4FE

Bit 10: Output compare 4 fast enable Refer to OC1FE description..

OC4PE

Bit 11: Output compare 4 preload enable Refer to OC1PE description..

OC4M1

Bits 12-14: Output compare 4 mode Refer to OC3M[3:0] description..

OC4CE

Bit 15: Output compare 4 clear enable Refer to OC1CE description..

OC3M2

Bit 16: Output compare 3 mode Refer to OC1M[3:0] description..

OC4M2

Bit 24: Output compare 4 mode Refer to OC3M[3:0] description..

CCER

TIM1 capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

0/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										CC6P rw	CC6E rw			CC5P rw	CC5E rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CC4NP rw		CC4P rw	CC4E rw	CC3NP rw	CC3NE rw	CC3P rw	CC3E rw	CC2NP rw	CC2NE rw	CC2P rw	CC2E rw	CC1NP rw	CC1NE rw	CC1P rw	CC1E rw

Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to for details. Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1E active bit takes the new value from the preloaded bit only when a Commutation event is generated..

CC1P

Bit 1: Capture/Compare 1 output polarity When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: The configuration is reserved, it must not be used. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated..

CC1NE

Bit 2: Capture/Compare 1 complementary output enable On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NE active bit takes the new value from the preloaded bit only when a Commutation event is generated..

CC1NP

Bit 3: Capture/Compare 1 complementary output polarity CC1 channel configured as output: CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to CC1P description. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=00 (channel configured as output). On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation event is generated..

CC2E

Bit 4: Capture/Compare 2 output enable Refer to CC1E description.

CC2P

Bit 5: Capture/Compare 2 output polarity Refer to CC1P description.

CC2NE

Bit 6: Capture/Compare 2 complementary output enable Refer to CC1NE description.

CC2NP

Bit 7: Capture/Compare 2 complementary output polarity Refer to CC1NP description.

CC3E

Bit 8: Capture/Compare 3 output enable Refer to CC1E description.

CC3P

Bit 9: Capture/Compare 3 output polarity Refer to CC1P description.

CC3NE

Bit 10: Capture/Compare 3 complementary output enable Refer to CC1NE description.

CC3NP

Bit 11: Capture/Compare 3 complementary output polarity Refer to CC1NP description.

CC4E

Bit 12: Capture/Compare 4 output enable Refer to CC1E description.

CC4P

Bit 13: Capture/Compare 4 output polarity Refer to CC1P description.

CC4NP

Bit 15: Capture/Compare 4 complementary output polarity Refer to CC1NP description.

CC5E

Bit 16: Capture/Compare 5 output enable Refer to CC1E description.

CC5P

Bit 17: Capture/Compare 5 output polarity Refer to CC1P description.

CC6E

Bit 20: Capture/Compare 6 output enable Refer to CC1E description.

CC6P

Bit 21: Capture/Compare 6 output polarity Refer to CC1P description.

CNT

TIM1 counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIFCPY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		BK2BID rw	BKBID rw	BK2DSRM rw	BKDSRM rw	BK2P rw	BK2E rw	BK2F rw				BKF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MOE rw	AOE rw	BKP rw	BKE rw	OSSR rw	OSSI rw	LOCK rw		DTG rw

Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset..

OSSI

Bit 10: Off-state selection for Idle mode This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..

OSSR

Bit 11: Off-state selection for Run mode This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..

BKE

Bit 12: Break enable This bit enables the complete break protection (including all sources connected to bk_acth and BKIN sources, as per ). Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

BKP

Bit 13: Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

AOE

Bit 14: Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

MOE

Bit 15: Main output enable This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. In response to a break event or if MOE is written to 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A)..

BKF

Bits 16-19: Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

BK2F

Bits 20-23: Break 2 filter This bit-field defines the frequency used to sample BRK2 input and the length of the digital filter applied to BRK2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

BK2E

Bit 24: Break 2 enable Note: The BRK2 must only be used with OSSR = OSSI = 1. Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

BK2P

Bit 25: Break 2 polarity Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

BKDSRM

Bit 26: Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

BK2DSRM

Bit 27: Break2 Disarm Refer to BKDSRM description.

BKBID

Bit 28: Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

BK2BID

Bit 29: Break2 bidirectional Refer to BKBID description.

DCR

TIM1 DMA control register

Offset: 0x48, size: 16, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ....

DBL

Bits 8-12: DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ... Example: Let us consider the following transfer: DBL = 7 bytes & DBA = TIMx_CR1. If DBL = 7 bytes and DBA = TIMx_CR1 represents the address of the byte to be transferred, the address of the transfer should be given by the following equation: (TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL In this example, 7 bytes are added to (TIMx_CR1 address) + DBA, which gives us the address from/to which the data is copied. In this case, the transfer is done to 7 registers starting from the following address: (TIMx_CR1 address) + DBA According to the configuration of the DMA Data Size, several cases may occur: If the DMA Data Size is configured in half-words, 16-bit data is transferred to each of the 7 registers. If the DMA Data Size is configured in bytes, the data is also transferred to 7 registers: the first register contains the first MSB byte, the second register, the first LSB byte and so on. So with the transfer Timer, one also has to specify the size of data transferred by DMA..

DMAR

TIM1 DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DMAB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle fields

DMAB

Bits 0-31: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR)..

CCMR3

TIM1 capture/compare mode register 3

Offset: 0x54, size: 32, reset: 0x00000000, access: Unspecified

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC6M2 rw								OC5M2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC6CE rw	OC6M1 rw			OC6PE rw	OC6FE rw			OC5CE rw	OC5M1 rw			OC5PE rw	OC5FE rw

Toggle fields

OC5FE

Bit 2: Output compare 5 fast enable Refer to OC1FE description..

OC5PE

Bit 3: Output compare 5 preload enable Refer to OC1PE description..

OC5M1

Bits 4-6: Output compare 5 mode Refer to OC1M description..

OC5CE

Bit 7: Output compare 5 clear enable Refer to OC1CE description..

OC6FE

Bit 10: Output compare 6 fast enable Refer to OC1FE description..

OC6PE

Bit 11: Output compare 6 preload enable Refer to OC1PE description..

OC6M1

Bits 12-14: Output compare 6 mode Refer to OC1M description..

OC6CE

Bit 15: Output compare 6 clear enable Refer to OC1CE description..

OC5M2

Bit 16: Output compare 5 mode Refer to OC1M description..

OC6M2

Bit 24: Output compare 6 mode Refer to OC1M description..

CCR5

TIM1 capture/compare register 5

Offset: 0x58, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
GC5C3 rw	GC5C2 rw	GC5C1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR5 rw

Toggle fields

CCR5

Bits 0-15: Capture/Compare 5 value CCR5 is the value to be loaded in the actual capture/compare 5 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC5PE). Else the preload value is copied in the active capture/compare 5 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC5 output..

GC5C1

Bit 29: Group Channel 5 and Channel 1 Distortion on Channel 1 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals..

GC5C2

Bit 30: Group Channel 5 and Channel 2 Distortion on Channel 2 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals..

GC5C3

Bit 31: Group Channel 5 and Channel 3 Distortion on Channel 3 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2). Note: it is also possible to apply this distortion on combined PWM signals..

CCR6

TIM1 capture/compare register 6

Offset: 0x5c, size: 16, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR6 rw

Toggle fields

CCR6

Bits 0-15: Capture/Compare 6 value CCR6 is the value to be loaded in the actual capture/compare 6 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC6PE). Else the preload value is copied in the active capture/compare 6 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC6 output..

AF1

TIM1 alternate function option register 1

Offset: 0x60, size: 32, reset: 0x00000001, access: Unspecified

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														ETRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETRSEL rw						BKINP rw									BKINE rw

Toggle fields

BKINE

Bit 0: BRK BKIN input enable This bit enables the BKIN alternate function input for the timers BRK input. BKIN input is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

BKINP

Bit 9: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

ETRSEL

Bits 14-17: ETR source selection These bits select the ETR input source. Others: Reserved Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

AF2

TIM1 Alternate function register 2

Offset: 0x64, size: 32, reset: 0x00000001, access: Unspecified

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						BK2INP rw									BK2INE rw

Toggle fields

BK2INE

Bit 0: BRK2 BKIN input enable This bit enables the BKIN2 alternate function input for the timers BRK2 input. BKIN2 input is ORed with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

BK2INP

Bit 9: BRK2 BKIN2 input polarity This bit selects the BKIN2 alternate function input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

TISEL

TIM1 timer input selection register

Offset: 0x68, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TI4SEL rw								TI3SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				TI2SEL rw								TI1SEL rw

Toggle fields

TI1SEL

Bits 0-3: selects TI1[0] to TI1[15] input Others: Reserved.

TI2SEL

Bits 8-11: selects TI2[0] to TI2[15] input Others: Reserved.

TI3SEL

Bits 16-19: selects TI3[0] to TI3[15] input Others: Reserved.

TI4SEL

Bits 24-27: selects TI4[0] to TI4[15] input Others: Reserved.

TIM14

0x40002000: General-purpose timers

0/31 fields covered.

Toggle register map

Offset	Name	31	16	15	11	9	7	6	3	2	1	0
0x0 (16-bit)	CR1				UIFREMAP	CKD	ARPE		OPM	URS	UDIS	CEN
0xc (16-bit)	DIER										CC1IE	UIE
0x10 (16-bit)	SR					CC1OF					CC1IF	UIF
0x14 (16-bit)	EGR										CC1G	UG
0x18	CCMR1_Input						IC1F		IC1PSC		CC1S
0x18	CCMR1_Output		OC1M_3					OC1M	OC1PE	OC1FE	CC1S
0x20 (16-bit)	CCER								CC1NP		CC1P	CC1E
0x24	CNT	UIFCPY		CNT
0x28 (16-bit)	PSC			PSC
0x2c (16-bit)	ARR			ARR
0x34 (16-bit)	CCR1			CCR1
0x68 (16-bit)	TISEL								TI1SEL

Toggle registers

CR1

TIM14 control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: Unspecified

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				UIFREMAP rw		CKD rw		ARPE rw				OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware..

UDIS

Bit 1: Update disable This bit is set and cleared by software to enable/disable update interrupt (UEV) event generation. Counter overflow Setting the UG bit. Buffered registers are then loaded with their preload values..

URS

Bit 2: Update request source This bit is set and cleared by software to select the update interrupt (UEV) sources. Counter overflow Setting the UG bit.

OPM

Bit 3: One-pulse mode.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (TIx),.

UIFREMAP

Bit 11: UIF status bit remapping.

DIER

TIM14 Interrupt enable register

Offset: 0xc, size: 16, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CC1IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

SR

TIM14 status register

Offset: 0x10, size: 16, reset: 0x00000000, access: Unspecified

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC1OF rw								CC1IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow and if UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register..

CC1IF

Bit 1: Capture/compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when he content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER)..

CC1OF

Bit 9: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to 0..

EGR

TIM14 event generation register

Offset: 0x14, size: 16, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CC1G w	UG w

Toggle fields

UG

Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..

CC1G

Bit 1: Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high..

CCMR1_Input

TIM14 capture/compare mode register 1 [alternate]

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IC1F rw				IC1PSC rw		CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER)..

IC1PSC

Bits 2-3: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=0 (TIMx_CCER register)..

IC1F

Bits 4-7: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.

CCMR1_Output

TIM14 capture/compare mode register 1 [alternate]

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															OC1M_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OC1M rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER)..

OC1FE

Bit 2: Output compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger..

OC1PE

Bit 3: Output compare 1 preload enable Note: The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed..

OC1M

Bits 4-6: Output compare 1 mode (refer to bit 16 for OC1M[3]) These bits define the behavior of the output reference signal OC1REF from which OC1 is derived. OC1REF is active high whereas OC1 active level depends on CC1P bit. Others: Reserved Note: In PWM mode 1 or 2, the OCREF level changes when the result of the comparison changes or when the output compare mode switches from frozen to PWM mode. Note: The OC1M[3] bit is not contiguous, located in bit 16..

OC1M_3

Bit 16: Output compare 1 mode (refer to bit 16 for OC1M[3]) These bits define the behavior of the output reference signal OC1REF from which OC1 is derived. OC1REF is active high whereas OC1 active level depends on CC1P bit. Others: Reserved Note: In PWM mode 1 or 2, the OCREF level changes when the result of the comparison changes or when the output compare mode switches from frozen to PWM mode. Note: The OC1M[3] bit is not contiguous, located in bit 16..

CCER

TIM14 capture/compare enable register

Offset: 0x20, size: 16, reset: 0x00000000, access: Unspecified

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												CC1NP rw		CC1P rw	CC1E rw

Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable..

CC1P

Bit 1: Capture/Compare 1 output Polarity. When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: This configuration is reserved, it must not be used..

CC1NP

Bit 3: Capture/Compare 1 complementary output Polarity. CC1 channel configured as output: CC1NP must be kept cleared. CC1 channel configured as input: CC1NP bit is used in conjunction with CC1P to define TI1FP1 polarity (refer to CC1P description)..

CNT

TIM14 counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIFCPY rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle register map

Offset	Name	31	28	26	19	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0 (16-bit)	CR1										UIFREMAP		CKD		ARPE				OPM	URS	UDIS	CEN
0x4 (16-bit)	CR2												OIS1N	OIS1					CCDS	CCUS		CCPC
0xc (16-bit)	DIER												CC1DE	UDE	BIE		COMIE				CC1IE	UIE
0x10 (16-bit)	SR												CC1OF		BIF		COMIF				CC1IF	UIF
0x14 (16-bit)	EGR														BG		COMG				CC1G	UG
0x18	CCMR1_Input														IC1F				IC1PSC		CC1S
0x18	CCMR1_Output					OC1M_3										OC1M			OC1PE	OC1FE	CC1S
0x20 (16-bit)	CCER																		CC1NP	CC1NE	CC1P	CC1E
0x24	CNT	UIFCPY					CNT
0x28 (16-bit)	PSC						PSC
0x2c (16-bit)	ARR						ARR
0x30 (16-bit)	RCR														REP
0x34 (16-bit)	CCR1						CCR1
0x44	BDTR		BKBID	BKDSRM	BKF		MOE	AOE	BKP	BKE	OSSR	OSSI	LOCK		DTG
0x48 (16-bit)	DCR									DBL								DBA
0x4c (16-bit)	DMAR						DMAB
0x60	AF1												BKINP									BKINE
0x68	TISEL																		TI1SEL

Toggle registers

CR1

TIM16 control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: Unspecified

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				UIFREMAP rw		CKD rw		ARPE rw				OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware..

UDIS

Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..

URS

Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.

OPM

Bit 3: One pulse mode.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (TIx),.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

TIM16 control register 2

Offset: 0x4, size: 16, reset: 0x00000000, access: Unspecified

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						OIS1N rw	OIS1 rw					CCDS rw	CCUS rw		CCPC rw

Toggle fields

CCPC

Bit 0: Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output..

CCUS

Bit 2: Capture/compare control update selection Note: This bit acts only on channels that have a complementary output..

CCDS

Bit 3: Capture/compare DMA selection.

OIS1

Bit 8: Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..

OIS1N

Bit 9: Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..

DIER

TIM16 DMA/interrupt enable register

Offset: 0xc, size: 16, reset: 0x00000000, access: Unspecified

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC1DE rw	UDE rw	BIE rw		COMIE rw				CC1IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

SR

TIM16 status register

Offset: 0x10, size: 16, reset: 0x00000000, access: Unspecified

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC1OF rw		BIF rw		COMIF rw				CC1IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register..

CC1IF

Bit 1: Capture/Compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER)..

COMIF

Bit 5: COM interrupt flag.

BIF

Bit 7: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active..

CC1OF

Bit 9: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to 0..

EGR

TIM16 event generation register

Offset: 0x14, size: 16, reset: 0x00000000, access: Unspecified

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								BG w		COMG w				CC1G w	UG w

Toggle fields

UG

Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..

CC1G

Bit 1: Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high..

COMG

Bit 5: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output..

BG

Bit 7: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..

CCMR1_Input

TIM16 capture/compare mode register 1 [alternate]

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IC1F rw				IC1PSC rw		CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER)..

IC1PSC

Bits 2-3: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=0 (TIMx_CCER register)..

IC1F

Bits 4-7: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.

CCMR1_Output

TIM16 capture/compare mode register 1 [alternate]

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															OC1M_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OC1M rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER)..

OC1FE

Bit 2: Output Compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger..

OC1PE

Bit 3: Output Compare 1 preload enable Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in output). The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed..

OC1M

Bits 4-6: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. All other values: Reserved Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in output). In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from frozen mode to PWM mode. The OC1M[3] bit is not contiguous, located in bit 16..

OC1M_3

Bit 16: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. All other values: Reserved Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in output). In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from frozen mode to PWM mode. The OC1M[3] bit is not contiguous, located in bit 16..

CCER

TIM16 capture/compare enable register

Offset: 0x20, size: 16, reset: 0x00000000, access: Unspecified

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												CC1NP rw	CC1NE rw	CC1P rw	CC1E rw

Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to for details..

CC1P

Bit 1: Capture/Compare 1 output polarity When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: this configuration is reserved, it must not be used. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated..

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 complementary output polarity CC1 channel configured as output: CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to the description of CC1P. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in output). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a commutation event is generated..

CNT

TIM16 counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIFCPY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			BKBID rw		BKDSRM rw							BKF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MOE rw	AOE rw	BKP rw	BKE rw	OSSR rw	OSSI rw	LOCK rw		DTG rw

Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset..

OSSI

Bit 10: Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 1793). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..

OSSR

Bit 11: Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 1793). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..

BKE

Bit 12: Break enable 1; Break inputs (BRK and CCS clock failure event) enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

BKP

Bit 13: Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

AOE

Bit 14: Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

MOE

Bit 15: Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 1793)..

BKF

Bits 16-19: Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

BKDSRM

Bit 26: Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

BKBID

Bit 28: Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

DCR

TIM16 DMA control register

Offset: 0x48, size: 16, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address..

DBL

Bits 8-12: DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ....

DMAR

TIM16 DMA address for full transfer

Offset: 0x4c, size: 16, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR)..

AF1

TIM16 alternate function register 1

Offset: 0x60, size: 32, reset: 0x00000001, access: Unspecified

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						BKINP rw									BKINE rw

Toggle fields

BKINE

Bit 0: BRK BKIN input enable This bit enables the BKIN alternate function input for the timers BRK input. BKIN input is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

BKINP

Bit 9: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

TISEL

TIM16 input selection register

Offset: 0x68, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												TI1SEL rw

Toggle fields

TI1SEL

Bits 0-3: selects TI1[0] to TI1[15] input Others: Reserved.

TIM17

0x40014800: General-purpose timers

1/62 fields covered.

Toggle register map

Offset	Name	31	28	26	19	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0 (16-bit)	CR1										UIFREMAP		CKD		ARPE				OPM	URS	UDIS	CEN
0x4 (16-bit)	CR2												OIS1N	OIS1					CCDS	CCUS		CCPC
0xc (16-bit)	DIER												CC1DE	UDE	BIE		COMIE				CC1IE	UIE
0x10 (16-bit)	SR												CC1OF		BIF		COMIF				CC1IF	UIF
0x14 (16-bit)	EGR														BG		COMG				CC1G	UG
0x18	CCMR1_Input														IC1F				IC1PSC		CC1S
0x18	CCMR1_Output					OC1M_3										OC1M			OC1PE	OC1FE	CC1S
0x20 (16-bit)	CCER																		CC1NP	CC1NE	CC1P	CC1E
0x24	CNT	UIFCPY					CNT
0x28 (16-bit)	PSC						PSC
0x2c (16-bit)	ARR						ARR
0x30 (16-bit)	RCR														REP
0x34 (16-bit)	CCR1						CCR1
0x44	BDTR		BKBID	BKDSRM	BKF		MOE	AOE	BKP	BKE	OSSR	OSSI	LOCK		DTG
0x48 (16-bit)	DCR									DBL								DBA
0x4c (16-bit)	DMAR						DMAB
0x60	AF1												BKINP									BKINE
0x68	TISEL																		TI1SEL

Toggle registers

CR1

TIM17 control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: Unspecified

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				UIFREMAP rw		CKD rw		ARPE rw				OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware..

UDIS

Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..

URS

Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.

OPM

Bit 3: One pulse mode.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (TIx),.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

TIM17 control register 2

Offset: 0x4, size: 16, reset: 0x00000000, access: Unspecified

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						OIS1N rw	OIS1 rw					CCDS rw	CCUS rw		CCPC rw

Toggle fields

CCPC

Bit 0: Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output..

CCUS

Bit 2: Capture/compare control update selection Note: This bit acts only on channels that have a complementary output..

CCDS

Bit 3: Capture/compare DMA selection.

OIS1

Bit 8: Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..

OIS1N

Bit 9: Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..

DIER

TIM17 DMA/interrupt enable register

Offset: 0xc, size: 16, reset: 0x00000000, access: Unspecified

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC1DE rw	UDE rw	BIE rw		COMIE rw				CC1IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

SR

TIM17 status register

Offset: 0x10, size: 16, reset: 0x00000000, access: Unspecified

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC1OF rw		BIF rw		COMIF rw				CC1IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register..

CC1IF

Bit 1: Capture/Compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER)..

COMIF

Bit 5: COM interrupt flag.

BIF

Bit 7: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active..

CC1OF

Bit 9: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to 0..

EGR

TIM17 event generation register

Offset: 0x14, size: 16, reset: 0x00000000, access: Unspecified

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								BG w		COMG w				CC1G w	UG w

Toggle fields

UG

Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..

CC1G

Bit 1: Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high..

COMG

Bit 5: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output..

BG

Bit 7: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..

CCMR1_Input

TIM17 capture/compare mode register 1 [alternate]

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IC1F rw				IC1PSC rw		CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER)..

IC1PSC

Bits 2-3: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=0 (TIMx_CCER register)..

IC1F

Bits 4-7: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.

CCMR1_Output

TIM17 capture/compare mode register 1 [alternate]

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															OC1M_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OC1M rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER)..

OC1FE

Bit 2: Output Compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger..

OC1PE

Bit 3: Output Compare 1 preload enable Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in output). The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed..

OC1M

Bits 4-6: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. All other values: Reserved Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in output). In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from frozen mode to PWM mode. The OC1M[3] bit is not contiguous, located in bit 16..

OC1M_3

Bit 16: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. All other values: Reserved Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in output). In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from frozen mode to PWM mode. The OC1M[3] bit is not contiguous, located in bit 16..

CCER

TIM17 capture/compare enable register

Offset: 0x20, size: 16, reset: 0x00000000, access: Unspecified

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												CC1NP rw	CC1NE rw	CC1P rw	CC1E rw

Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to for details..

CC1P

Bit 1: Capture/Compare 1 output polarity When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: this configuration is reserved, it must not be used. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated..

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 complementary output polarity CC1 channel configured as output: CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to the description of CC1P. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in output). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a commutation event is generated..

CNT

TIM17 counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIFCPY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			BKBID rw		BKDSRM rw							BKF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MOE rw	AOE rw	BKP rw	BKE rw	OSSR rw	OSSI rw	LOCK rw		DTG rw

Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset..

OSSI

Bit 10: Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 1793). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..

OSSR

Bit 11: Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 1793). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..

BKE

Bit 12: Break enable 1; Break inputs (BRK and CCS clock failure event) enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

BKP

Bit 13: Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

AOE

Bit 14: Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

MOE

Bit 15: Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 1793)..

BKF

Bits 16-19: Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

BKDSRM

Bit 26: Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

BKBID

Bit 28: Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..

DCR

TIM17 DMA control register

Offset: 0x48, size: 16, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address..

DBL

Bits 8-12: DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ....

DMAR

TIM17 DMA address for full transfer

Offset: 0x4c, size: 16, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR)..

AF1

TIM17 alternate function register 1

Offset: 0x60, size: 32, reset: 0x00000001, access: Unspecified

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						BKINP rw									BKINE rw

Toggle fields

BKINE

Bit 0: BRK BKIN input enable This bit enables the BKIN alternate function input for the timers BRK input. BKIN input is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

BKINP

Bit 9: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..

TISEL

TIM17 input selection register

Offset: 0x68, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												TI1SEL rw

Toggle fields

TI1SEL

Bits 0-3: selects TI1[0] to TI1[15] input Others: Reserved.

TIM3

0x40000400: General-purpose timer

0/114 fields covered.

Toggle register map

Offset	Name	31	24	21	19	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0 (16-bit)	CR1											UIFREMAP		CKD		ARPE	CMS		DIR	OPM	URS	UDIS	CEN
0x4 (16-bit)	CR2															TI1S	MMS			CCDS
0x8	SMCR			TS2			SMS2	ETP	ECE	ETPS		ETF				MSM	TS1			OCCS	SMS1
0xc (16-bit)	DIER								TDE		CC4DE	CC3DE	CC2DE	CC1DE	UDE		TIE		CC4IE	CC3IE	CC2IE	CC1IE	UIE
0x10 (16-bit)	SR										CC4OF	CC3OF	CC2OF	CC1OF			TIF		CC4IF	CC3IF	CC2IF	CC1IF	UIF
0x14 (16-bit)	EGR																TG		CC4G	CC3G	CC2G	CC1G	UG
0x18	CCMR1_Input							IC2F				IC2PSC		CC2S		IC1F				IC1PSC		CC1S
0x18	CCMR1_Output		OC2M_3				OC1M_3	OC2CE	OC2M			OC2PE	OC2FE	CC2S		OC1CE	OC1M			OC1PE	OC1FE	CC1S
0x1c	CCMR2_Input							IC4F				IC4PSC		CC4S		IC3F				IC3PSC		CC3S
0x1c	CCMR2_Output		OC4M2				OC3M2	OC4CE	OC4M1			OC4PE	OC4FE	CC4S		OC3CE	OC3M1			OC3PE	OC3FE	CC3S
0x20 (16-bit)	CCER							CC4NP		CC4P	CC4E	CC3NP		CC3P	CC3E	CC2NP		CC2P	CC2E	CC1NP		CC1P	CC1E
0x24	CNT							CNT
0x24	CNT_remap	UIFCPY						CNT
0x28 (16-bit)	PSC							PSC
0x2c	ARR							ARR
0x34	CCR1							CCR1
0x38	CCR2							CCR2
0x3c	CCR3							CCR3
0x40	CCR4							CCR4
0x48 (16-bit)	DCR										DBL								DBA
0x4c (16-bit)	DMAR							DMAB
0x60	AF1					ETRSEL		ETRSEL
0x68	TISEL				TI3SEL							TI2SEL								TI1SEL

Toggle registers

CR1

TIM3 control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: Unspecified

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				UIFREMAP rw		CKD rw		ARPE rw	CMS rw		DIR rw	OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs..

UDIS

Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..

URS

Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode..

CMS

Bits 5-6: Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1).

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx),.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

TIM3 control register 2

Offset: 0x4, size: 16, reset: 0x00000000, access: Unspecified

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TI1S rw	MMS rw			CCDS rw

Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection These bits permit to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer..

TI1S

Bit 7: TI1 selection.

SMCR

TIM3 slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										TS2 rw					SMS2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETP rw	ECE rw	ETPS rw		ETF rw				MSM rw	TS1 rw			OCCS rw	SMS1 rw

Toggle fields

SMS1

Bits 0-2: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..

OCCS

Bit 3: OCREF clear selection This bit is used to select the OCREF clear source.

TS1

Bits 4-6: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.

ETPS

Bits 12-13: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks..

ECE

Bit 14: External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF..

ETP

Bit 15: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations.

SMS2

Bit 16: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..

TS2

Bits 20-21: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..

DIER

TIM3 DMA/Interrupt enable register

Offset: 0xc, size: 16, reset: 0x00000000, access: Unspecified

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDE rw		CC4DE rw	CC3DE rw	CC2DE rw	CC1DE rw	UDE rw		TIE rw		CC4IE rw	CC3IE rw	CC2IE rw	CC1IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

TIM3 status register

Offset: 0x10, size: 16, reset: 0x00000000, access: Unspecified

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CC4OF rw	CC3OF rw	CC2OF rw	CC1OF rw			TIF rw		CC4IF rw	CC3IF rw	CC2IF rw	CC1IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow and if UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register..

CC1IF

Bit 1: Capture/compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER)..

CC2IF

Bit 2: Capture/Compare 2 interrupt flag Refer to CC1IF description.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag Refer to CC1IF description.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag Refer to CC1IF description.

TIF

Bit 6: Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software..

CC1OF

Bit 9: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to 0..

CC2OF

Bit 10: Capture/compare 2 overcapture flag refer to CC1OF description.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag refer to CC1OF description.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag refer to CC1OF description.

EGR

TIM3 event generation register

Offset: 0x14, size: 16, reset: 0x00000000, access: Unspecified

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									TG w		CC4G w	CC3G w	CC2G w	CC1G w	UG w

Toggle fields

UG

Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..

CC1G

Bit 1: Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high..

CC2G

Bit 2: Capture/compare 2 generation Refer to CC1G description.

CC3G

Bit 3: Capture/compare 3 generation Refer to CC1G description.

CC4G

Bit 4: Capture/compare 4 generation Refer to CC1G description.

TG

Bit 6: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..

CCMR1_Input

TIM3 capture/compare mode register 1 [alternate]

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC2F rw				IC2PSC rw		CC2S rw		IC1F rw				IC1PSC rw		CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER)..

IC1PSC

Bits 2-3: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=0 (TIMx_CCER register)..

IC1F

Bits 4-7: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.

CC2S

Bits 8-9: Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER)..

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

TIM3 capture/compare mode register 1 [alternate]

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC2M_3 rw								OC1M_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC2CE rw	OC2M rw			OC2PE rw	OC2FE rw	CC2S rw		OC1CE rw	OC1M rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER)..

OC1FE

Bit 2: Output compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger..

OC1PE

Bit 3: Output compare 1 preload enable Note: The PWM mode can be used without validating the preload register only in one-pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed..

OC1M

Bits 4-6: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from frozen mode to PWM mode. Note: The OC1M[3] bit is not contiguous, located in bit 16..

OC1CE

Bit 7: Output compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER)..

OC2FE

Bit 10: Output compare 2 fast enable.

OC2PE

Bit 11: Output compare 2 preload enable.

OC2M

Bits 12-14: Output compare 2 mode refer to OC1M description on bits 6:4.

OC2CE

Bit 15: Output compare 2 clear enable.

OC1M_3

Bit 16: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from frozen mode to PWM mode. Note: The OC1M[3] bit is not contiguous, located in bit 16..

OC2M_3

Bit 24: Output compare 2 mode refer to OC1M description on bits 6:4.

CCMR2_Input

TIM3 capture/compare mode register 2 [alternate]

Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC4F rw				IC4PSC rw		CC4S rw		IC3F rw				IC3PSC rw		CC3S rw

Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER)..

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER)..

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCMR2_Output

TIM3 capture/compare mode register 2 [alternate]

Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC4M2 rw								OC3M2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC4CE rw	OC4M1 rw			OC4PE rw	OC4FE rw	CC4S rw		OC3CE rw	OC3M1 rw			OC3PE rw	OC3FE rw	CC3S rw

Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER)..

OC3FE

Bit 2: Output compare 3 fast enable.

OC3PE

Bit 3: Output compare 3 preload enable.

OC3M1

Bits 4-6: Output compare 3 mode Refer to OC1M description (bits 6:4 in TIMx_CCMR1 register).

OC3CE

Bit 7: Output compare 3 clear enable.

CC4S

Bits 8-9: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER)..

OC4FE

Bit 10: Output compare 4 fast enable.

OC4PE

Bit 11: Output compare 4 preload enable.

OC4M1

Bits 12-14: Output compare 4 mode Refer to OC1M description (bits 6:4 in TIMx_CCMR1 register).

OC4CE

Bit 15: Output compare 4 clear enable.

OC3M2

Bit 16: Output compare 3 mode Refer to OC1M description (bits 6:4 in TIMx_CCMR1 register).

OC4M2

Bit 24: Output compare 4 mode Refer to OC1M description (bits 6:4 in TIMx_CCMR1 register).

CCER

TIM3 capture/compare enable register

Offset: 0x20, size: 16, reset: 0x00000000, access: Unspecified

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CC4NP rw		CC4P rw	CC4E rw	CC3NP rw		CC3P rw	CC3E rw	CC2NP rw		CC2P rw	CC2E rw	CC1NP rw		CC1P rw	CC1E rw

Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable..

CC1P

Bit 1: Capture/Compare 1 output Polarity. When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges. The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: This configuration is reserved, it must not be used..

CC1NP

Bit 3: Capture/Compare 1 output Polarity. CC1 channel configured as output: CC1NP must be kept cleared in this case. CC1 channel configured as input: This bit is used in conjunction with CC1P to define TI1FP1/TI2FP1 polarity. refer to CC1P description..

CC2E

Bit 4: Capture/Compare 2 output enable. Refer to CC1E description.

CC2P

Bit 5: Capture/Compare 2 output Polarity. refer to CC1P description.

CC2NP

Bit 7: Capture/Compare 2 output Polarity. Refer to CC1NP description.

CC3E

Bit 8: Capture/Compare 3 output enable. Refer to CC1E description.

CC3P

Bit 9: Capture/Compare 3 output Polarity. Refer to CC1P description.

CC3NP

Bit 11: Capture/Compare 3 output Polarity. Refer to CC1NP description.

CC4E

Bit 12: Capture/Compare 4 output enable. refer to CC1E description.

CC4P

Bit 13: Capture/Compare 4 output Polarity. Refer to CC1P description.

CC4NP

Bit 15: Capture/Compare 4 output Polarity. Refer to CC1NP description.

CNT

TIM3 counter [alternate]

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle fields

CNT

Bits 0-15: counter value.

CNT_remap

TIM3 counter [alternate]

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIFCPY rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												TI3SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				TI2SEL rw								TI1SEL rw

Toggle fields

TI1SEL

Bits 0-3: TI1[0] to TI1[15] input selection These bits select the TI1[0] to TI1[15] input source. Others: Reserved.

TI2SEL

Bits 8-11: TI2[0] to TI2[15] input selection These bits select the TI2[0] to TI2[15] input source. Others: Reserved.

TI3SEL

Bits 16-19: TI3[0] to TI3[15] input selection These bits select the TI3[0] to TI3[15] input source. Others: Reserved.

USART1

0x40013800: USART register block

53/170 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1_disabled			FIFOEN	M1	EOBIE	RTOIE	DEAT					DEDT					OVER8	CMIE	MME	M0	WAKE	PCE	PS	PEIE	TXEIE	TCIE	RXNEIE	IDLEIE	TE	RE	UESM	UE
0x0	CR1_enabled	RXFFIE	TXFEIE	FIFOEN	M1	EOBIE	RTOIE	DEAT					DEDT					OVER8	CMIE	MME	M0	WAKE	PCE	PS	PEIE	TXFNFIE	TCIE	RXFNEIE	IDLEIE	TE	RE	UESM	UE
0x4	CR2	ADD								RTOEN	ABRMOD		ABREN	MSBFIRST	DATAINV	TXINV	RXINV	SWAP	LINEN	STOP		CLKEN	CPOL	CPHA	LBCL		LBDIE	LBDL	ADDM7	DIS_NSS			SLVEN
0x8	CR3	TXFTCFG			RXFTIE	RXFTCFG			TCBGTIE	TXFTIE	WUFIE	WUS		SCARCNT				DEP	DEM	DDRE	OVRDIS	ONEBIT	CTSIE	CTSE	RTSE	DMAT	DMAR	SCEN	NACK	HDSEL	IRLP	IREN	EIE
0xc	BRR																	BRR
0x10	GTPR																	GT								PSC
0x14	RTOR	BLEN								RTO								RTO
0x18	RQR																												TXFRQ	RXFRQ	MMRQ	SBKRQ	ABRRQ
0x1c	ISR_disabled							TCBGT			REACK	TEACK	WUF	RWU	SBKF	CMF	BUSY	ABRF	ABRE	UDR	EOBF	RTOF	CTS	CTSIF	LBDF	TXE	TC	RXNE	IDLE	ORE	NE	FE	PE
0x1c	ISR_enabled					TXFT	RXFT	TCBGT	RXFF	TXFE	REACK	TEACK	WUF	RWU	SBKF	CMF	BUSY	ABRF	ABRE	UDR	EOBF	RTOF	CTS	CTSIF	LBDF	TXFNF	TC	RXFNE	IDLE	ORE	NE	FE	PE
0x20	ICR												WUCF			CMCF				UDRCF	EOBCF	RTOCF		CTSCF	LBDCF	TCBGTCF	TCCF	TXFECF	IDLECF	ORECF	NECF	FECF	PECF
0x24	RDR																								RDR
0x28	TDR																								TDR
0x2c	PRESC																													PRESCALER

Toggle registers

CR1_disabled

USART control register 1 [alternate]

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

0/22 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		FIFOEN rw	M1 rw	EOBIE rw	RTOIE rw	DEAT rw					DEDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVER8 rw	CMIE rw	MME rw	M0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXEIE rw	TCIE rw	RXNEIE rw	IDLEIE rw	TE rw	RE rw	UESM rw	UE rw

Toggle fields

UE

Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the CK pin is always available when CLKEN = 1, regardless of the UE bit value..

UESM

Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 1985..

RE

Bit 2: Receiver enable This bit enables the receiver. It is set and cleared by software..

TE

Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit (0 followed by 1) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to 1. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..

IDLEIE

Bit 4: IDLE interrupt enable This bit is set and cleared by software..

RXNEIE

Bit 5: Receive data register not empty This bit is set and cleared by software..

TCIE

Bit 6: Transmission complete interrupt enable This bit is set and cleared by software..

TXEIE

Bit 7: Transmit data register empty This bit is set and cleared by software..

PEIE

Bit 8: PE interrupt enable This bit is set and cleared by software..

PS

Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UE = 0)..

PCE

Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UE = 0)..

WAKE

Bit 11: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..

M0

Bit 12: Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UE = 0)..

MME

Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..

CMIE

Bit 14: Character match interrupt enable This bit is set and cleared by software..

OVER8

Bit 15: Oversampling mode This bit can only be written when the USART is disabled (UE = 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared..

DEDT

Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

DEAT

Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOIE

Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ..

EOBIE

Bit 27: End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

M1

Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = 00: 1 start bit, 8 Data bits, n Stop bit M[1:0] = 01: 1 start bit, 9 Data bits, n Stop bit M[1:0] = 10: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..

FIFOEN

Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..

CR1_enabled

USART control register 1 [alternate]

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXFFIE rw	TXFEIE rw	FIFOEN rw	M1 rw	EOBIE rw	RTOIE rw	DEAT rw					DEDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVER8 rw	CMIE rw	MME rw	M0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXFNFIE rw	TCIE rw	RXFNEIE rw	IDLEIE rw	TE rw	RE rw	UESM rw	UE rw

Toggle fields

UE

Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the CK is always available when CLKEN = 1, regardless of the UE bit value..

UESM

Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 1985..

RE

Bit 2: Receiver enable This bit enables the receiver. It is set and cleared by software..

TE

Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit (0 followed by 1) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to 1. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..

IDLEIE

Bit 4: IDLE interrupt enable This bit is set and cleared by software..

RXFNEIE

Bit 5: RXFIFO not empty interrupt enable This bit is set and cleared by software..

TCIE

Bit 6: Transmission complete interrupt enable This bit is set and cleared by software..

TXFNFIE

Bit 7: TXFIFO not full interrupt enable This bit is set and cleared by software..

PEIE

Bit 8: PE interrupt enable This bit is set and cleared by software..

PS

Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UE = 0)..

PCE

Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UE = 0)..

WAKE

Bit 11: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..

M0

Bit 12: Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UE = 0)..

MME

Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..

CMIE

Bit 14: Character match interrupt enable This bit is set and cleared by software..

OVER8

Bit 15: Oversampling mode This bit can only be written when the USART is disabled (UE = 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared..

DEDT

Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

DEAT

Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOIE

Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ..

EOBIE

Bit 27: End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

M1

Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = 00: 1 start bit, 8 Data bits, n Stop bit M[1:0] = 01: 1 start bit, 9 Data bits, n Stop bit M[1:0] = 10: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..

FIFOEN

Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..

TXFEIE

Bit 30: TXFIFO empty interrupt enable This bit is set and cleared by software..

RXFFIE

Bit 31: RXFIFO Full interrupt enable This bit is set and cleared by software..

CR2

USART control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD rw								RTOEN rw	ABRMOD rw		ABREN rw	MSBFIRST rw	DATAINV rw	TXINV rw	RXINV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWAP rw	LINEN rw	STOP rw		CLKEN rw	CPOL rw	CPHA rw	LBCL rw		LBDIE rw	LBDL rw	ADDM7 rw	DIS_NSS rw			SLVEN rw

Toggle fields

SLVEN

Bit 0: Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

DIS_NSS

Bit 3: When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UE = 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively..

LBDL

Bit 5: LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UE = 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

LBDIE

Bit 6: LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

LBCL

Bit 8: Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the CK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CPHA

Bit 9: Clock phase This bit is used to select the phase of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see and ) This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CPOL

Bit 10: Clock polarity This bit enables the user to select the polarity of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CLKEN

Bit 11: Clock enable This bit enables the user to enable the CK pin. This bit can only be written when the USART is disabled (UE = 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to . In Smartcard mode, in order to provide correctly the CK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1.

STOP

Bits 12-13: stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UE = 0)..

LINEN

Bit 14: LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to ..

SWAP

Bit 15: Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..

RXINV

Bit 16: RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UE = 0)..

TXINV

Bit 17: TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UE = 0)..

DATAINV

Bit 18: Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..

MSBFIRST

Bit 19: Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..

ABREN

Bit 20: Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

ABRMOD

Bits 21-22: Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UE = 0). Note: If DATAINV = 1 and/or MSBFIRST = 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

RTOEN

Bit 23: Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to ..

ADD

Bits 24-31: Address of the USART node These bits give the address of the USART node in Mute mode or a character code to be recognized in low-power or Run mode: In Mute mode: they are used in multiprocessor communication to wakeup from Mute mode with 4-bit/7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. In 4-bit address mark detection, only ADD[3:0] bits are used. In low-power mode: they are used for wake up from low-power mode on character match. When WUS[1:0] is programmed to 0b00 (WUF active on address match), the wakeup from low-power mode is performed when the received character corresponds to the character programmed through ADD[6:0] or ADD[3:0] bitfield (depending on ADDM7 bit), and WUF interrupt is enabled by setting WUFIE bit. The MSB of the character sent by transmitter should be equal to 1. In Run mode with Mute mode inactive (for example, end-of-block detection in ModBus protocol): the whole received character (8 bits) is compared to ADD[7:0] value and CMF flag is set on match. An interrupt is generated if the CMIE bit is set. These bits can only be written when the reception is disabled (RE = 0) or when the USART is disabled (UE = 0)..

CR3

USART control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXFTCFG rw			RXFTIE rw	RXFTCFG rw			TCBGTIE rw	TXFTIE rw	WUFIE rw	WUS rw		SCARCNT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DEP rw	DEM rw	DDRE rw	OVRDIS rw	ONEBIT rw	CTSIE rw	CTSE rw	RTSE rw	DMAT rw	DMAR rw	SCEN rw	NACK rw	HDSEL rw	IRLP rw	IREN rw	EIE rw

Toggle fields

EIE

Bit 0: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE = 1 or ORE = 1 or NE = 1 or UDR = 1 in the USART_ISR register)..

IREN

Bit 1: IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

IRLP

Bit 2: IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

HDSEL

Bit 3: Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UE = 0)..

NACK

Bit 4: Smartcard NACK enable This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

SCEN

Bit 5: Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

DMAR

Bit 6: DMA enable receiver This bit is set/reset by software.

DMAT

Bit 7: DMA enable transmitter This bit is set/reset by software.

RTSE

Bit 8: RTS enable This bit can only be written when the USART is disabled (UE = 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CTSE

Bit 9: CTS enable This bit can only be written when the USART is disabled (UE = 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CTSIE

Bit 10: CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

ONEBIT

Bit 11: One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UE = 0)..

OVRDIS

Bit 12: Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UE = 0). Note: This control bit enables checking the communication flow w/o reading the data.

DDRE

Bit 13: DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error..

DEM

Bit 14: Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. ..

DEP

Bit 15: Driver enable polarity selection This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

SCARCNT

Bits 17-19: Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UE = 0). When the USART is enabled (UE = 1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

WUS

Bits 20-21: Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 1985..

WUFIE

Bit 22: Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 1985..

TXFTIE

Bit 23: TXFIFO threshold interrupt enable This bit is set and cleared by software..

TCBGTIE

Bit 24: Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration Remaining combinations: Reserved.

RXFTIE

Bit 28: RXFIFO threshold interrupt enable This bit is set and cleared by software..

TXFTCFG

Bits 29-31: TXFIFO threshold configuration Remaining combinations: Reserved.

BRR

USART baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRR rw

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BRR

Bits 0-15: USART baud rate BRR[15:4] BRR[15:4] = USARTDIV[15:4] BRR[3:0] When OVER8 = 0, BRR[3:0] = USARTDIV[3:0]. When OVER8 = 1: BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. BRR[3] must be kept cleared..

GTPR

USART guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
GT rw								PSC rw

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PSC

Bits 0-7: Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power baud rate PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0] = Prescaler value PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... ... This bitfield can only be written when the USART is disabled (UE = 0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to 0 when the Smartcard and IrDA modes are not supported. Refer to ..

GT

Bits 8-15: Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UE = 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOR

USART receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BLEN rw								RTO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RTO rw

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RTO

Bits 0-23: Receiver timeout value This bitfield gives the Receiver timeout value in terms of number of bits during which there is no activity on the RX line. In standard mode, the RTOF flag is set if, after the last received character, no new start bit is detected for more than the RTO value. In Smartcard mode, this value is used to implement the CWT and BWT. See Smartcard chapter for more details. In the standard, the CWT/BWT measurement is done starting from the start bit of the last received character. Note: This value must only be programmed once per received character..

BLEN

Bits 24-31: Block Length This bitfield gives the Block length in Smartcard T = 1 Reception. Its value equals the number of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. Examples: BLEN = 0: 0 information characters + LEC BLEN = 1: 0 information characters + CRC BLEN = 255: 254 information characters + CRC (total 256 characters)) In Smartcard mode, the Block length counter is reset when TXE = 0 (TXFE = 0 in case FIFO mode is enabled). This bitfield can be used also in other modes. In this case, the Block length counter is reset when RE = 0 (receiver disabled) and/or when the EOBCF bit is written to 1. Note: This value can be programmed after the start of the block reception (using the data from the LEN character in the Prologue Field). It must be programmed only once per received block..

RQR

USART request register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											TXFRQ w	RXFRQ w	MMRQ w	SBKRQ w	ABRRQ w

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ABRRQ

Bit 0: Auto baud rate request Writing 1 to this bit resets the ABRF and ABRE flags in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

SBKRQ

Bit 1: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit..

MMRQ

Bit 2: Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag..

RXFRQ

Bit 3: Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition..

TXFRQ

Bit 4: Transmit data flush request When FIFO mode is disabled, writing 1 to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register..

ISR_disabled

USART interrupt and status register [alternate]

Offset: 0x1c, size: 32, reset: 0x008000C0, access: Unspecified

24/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						TCBGT r			REACK r	TEACK r	WUF r	RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABRF r	ABRE r	UDR r	EOBF r	RTOF r	CTS r	CTSIF r	LBDF r	TXE r	TC r	RXNE r	IDLE r	ORE r	NE r	FE r	PE r

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PE

Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register..

FE

Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR1 register..

NE

Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 2012)..

ORE

Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXNE = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXNEIE = 1 or EIE = 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..

IDLE

Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MME = 1), IDLE is set if the USART is not mute (RWU = 0), whatever the Mute mode selected by the WAKE bit. If RWU = 1, IDLE is not set..

RXNE

Bit 5: Read data register not empty RXNE bit is set by hardware when the content of the USART_RDR shift register has been transferred to the USART_RDR register. It is cleared by reading from the USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXNEIE = 1 in the USART_CR1 register..

TC

Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXE is set. An interrupt is generated if TCIE = 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately..

TXE

Bit 7: Transmit data register empty TXE is set by hardware when the content of the USART_TDR register has been transferred into the shift register. It is cleared by writing to the USART_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T = 0 mode, in case of transmission failure). An interrupt is generated if the TXEIE bit = 1 in the USART_CR1 register..

LBDF

Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ..

CTSIF

Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE = 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

CTS

Bit 10: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

RTOF

Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE = 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..

EOBF

Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example T = 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ..

UDR

Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..

ABRE

Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

ABRF

Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXNE is also set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABRE = 1) (ABRE, RXNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

BUSY

Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..

CMF

Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE = 1in the USART_CR1 register..

SBKF

Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..

RWU

Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

WUF

Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIE = 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TEACK

Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE = 0, followed by TE = 1 in the USART_CR1 register, in order to respect the TE = 0 minimum period..

REACK

Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TCBGT

Bit 25: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is 1. Refer to on page 1985..

ISR_enabled

USART interrupt and status register [alternate]

Offset: 0x1c, size: 32, reset: 0x008000C0, access: Unspecified

28/28 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TXFT r	RXFT r	TCBGT r	RXFF r	TXFE r	REACK r	TEACK r	WUF r	RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABRF r	ABRE r	UDR r	EOBF r	RTOF r	CTS r	CTSIF r	LBDF r	TXFNF r	TC r	RXFNE r	IDLE r	ORE r	NE r	FE r	PE r

Toggle fields

PE

Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR..

FE

Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR..

NE

Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 2012). This error is associated with the character in the USART_RDR..

ORE

Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIE = 1 or EIE = 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..

IDLE

Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MME = 1), IDLE is set if the USART is not mute (RWU = 0), whatever the Mute mode selected by the WAKE bit. If RWU = 1, IDLE is not set..

RXFNE

Bit 5: RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIE = 1 in the USART_CR1 register..

TC

Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIE = 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set..

TXFNF

Bit 7: TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). This bit is used during single buffer transmission..

LBDF

Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ..

CTSIF

Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE = 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

CTS

Bit 10: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

RTOF

Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE = 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..

EOBF

Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example T = 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ..

UDR

Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..

ABRE

Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

ABRF

Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABRE = 1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

BUSY

Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..

CMF

Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE = 1in the USART_CR1 register..

SBKF

Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..

RWU

Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

WUF

Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIE = 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TEACK

Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE = 0, followed by TE = 1 in the USART_CR1 register, in order to respect the TE = 0 minimum period..

REACK

Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TXFE

Bit 23: TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit = 1 (bit 30) in the USART_CR1 register..

RXFF

Bit 24: RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit = 1 in the USART_CR1 register..

TCBGT

Bit 25: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is 1. Refer to on page 1985..

RXFT

Bit 26: RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit = 1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to 101, RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data..

TXFT

Bit 27: TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit = 1 (bit 31) in the USART_CR3 register..

ICR

USART interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											WUCF w			CMCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		UDRCF w	EOBCF w	RTOCF w		CTSCF w	LBDCF w	TCBGTCF w	TCCF w	TXFECF w	IDLECF w	ORECF w	NECF w	FECF w	PECF w

Toggle fields

PECF

Bit 0: Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register..

FECF

Bit 1: Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register..

NECF

Bit 2: Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register..

ORECF

Bit 3: Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register..

IDLECF

Bit 4: Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register..

TXFECF

Bit 5: TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register..

TCCF

Bit 6: Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register..

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register..

LBDCF

Bit 8: LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CTSCF

Bit 9: CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOCF

Bit 11: Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to page 1985..

EOBCF

Bit 12: End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

UDRCF

Bit 13: SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to.

CMCF

Bit 17: Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register..

WUCF

Bit 20: Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 1985..

RDR

USART receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							RDR r

Toggle fields

RDR

Bits 0-8: Receive data value Contains the received data character. The RDR register provides the parallel interface between the input shift register and the internal bus (see ). When receiving with the parity enabled, the value read in the MSB bit is the received parity bit..

TDR

USART transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							TDR rw

Toggle fields

TDR

Bits 0-8: Transmit data value Contains the data character to be transmitted. The USART_TDR register provides the parallel interface between the internal bus and the output shift register (see ). When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. Note: This register must be written only when TXE/TXFNF = 1..

PRESC

USART prescaler register

Offset: 0x2c, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PRESCALER rw

Toggle fields

PRESCALER

Bits 0-3: Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256..

USART2

0x40004400: USART register block

53/170 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1_disabled			FIFOEN	M1	EOBIE	RTOIE	DEAT					DEDT					OVER8	CMIE	MME	M0	WAKE	PCE	PS	PEIE	TXEIE	TCIE	RXNEIE	IDLEIE	TE	RE	UESM	UE
0x0	CR1_enabled	RXFFIE	TXFEIE	FIFOEN	M1	EOBIE	RTOIE	DEAT					DEDT					OVER8	CMIE	MME	M0	WAKE	PCE	PS	PEIE	TXFNFIE	TCIE	RXFNEIE	IDLEIE	TE	RE	UESM	UE
0x4	CR2	ADD								RTOEN	ABRMOD		ABREN	MSBFIRST	DATAINV	TXINV	RXINV	SWAP	LINEN	STOP		CLKEN	CPOL	CPHA	LBCL		LBDIE	LBDL	ADDM7	DIS_NSS			SLVEN
0x8	CR3	TXFTCFG			RXFTIE	RXFTCFG			TCBGTIE	TXFTIE	WUFIE	WUS		SCARCNT				DEP	DEM	DDRE	OVRDIS	ONEBIT	CTSIE	CTSE	RTSE	DMAT	DMAR	SCEN	NACK	HDSEL	IRLP	IREN	EIE
0xc	BRR																	BRR
0x10	GTPR																	GT								PSC
0x14	RTOR	BLEN								RTO								RTO
0x18	RQR																												TXFRQ	RXFRQ	MMRQ	SBKRQ	ABRRQ
0x1c	ISR_disabled							TCBGT			REACK	TEACK	WUF	RWU	SBKF	CMF	BUSY	ABRF	ABRE	UDR	EOBF	RTOF	CTS	CTSIF	LBDF	TXE	TC	RXNE	IDLE	ORE	NE	FE	PE
0x1c	ISR_enabled					TXFT	RXFT	TCBGT	RXFF	TXFE	REACK	TEACK	WUF	RWU	SBKF	CMF	BUSY	ABRF	ABRE	UDR	EOBF	RTOF	CTS	CTSIF	LBDF	TXFNF	TC	RXFNE	IDLE	ORE	NE	FE	PE
0x20	ICR												WUCF			CMCF				UDRCF	EOBCF	RTOCF		CTSCF	LBDCF	TCBGTCF	TCCF	TXFECF	IDLECF	ORECF	NECF	FECF	PECF
0x24	RDR																								RDR
0x28	TDR																								TDR
0x2c	PRESC																													PRESCALER

Toggle registers

CR1_disabled

USART control register 1 [alternate]

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

0/22 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		FIFOEN rw	M1 rw	EOBIE rw	RTOIE rw	DEAT rw					DEDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVER8 rw	CMIE rw	MME rw	M0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXEIE rw	TCIE rw	RXNEIE rw	IDLEIE rw	TE rw	RE rw	UESM rw	UE rw

Toggle fields

UE

Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the CK pin is always available when CLKEN = 1, regardless of the UE bit value..

UESM

Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 1985..

RE

Bit 2: Receiver enable This bit enables the receiver. It is set and cleared by software..

TE

Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit (0 followed by 1) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to 1. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..

IDLEIE

Bit 4: IDLE interrupt enable This bit is set and cleared by software..

RXNEIE

Bit 5: Receive data register not empty This bit is set and cleared by software..

TCIE

Bit 6: Transmission complete interrupt enable This bit is set and cleared by software..

TXEIE

Bit 7: Transmit data register empty This bit is set and cleared by software..

PEIE

Bit 8: PE interrupt enable This bit is set and cleared by software..

PS

Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UE = 0)..

PCE

Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UE = 0)..

WAKE

Bit 11: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..

M0

Bit 12: Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UE = 0)..

MME

Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..

CMIE

Bit 14: Character match interrupt enable This bit is set and cleared by software..

OVER8

Bit 15: Oversampling mode This bit can only be written when the USART is disabled (UE = 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared..

DEDT

Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

DEAT

Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOIE

Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ..

EOBIE

Bit 27: End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

M1

Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = 00: 1 start bit, 8 Data bits, n Stop bit M[1:0] = 01: 1 start bit, 9 Data bits, n Stop bit M[1:0] = 10: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..

FIFOEN

Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..

CR1_enabled

USART control register 1 [alternate]

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXFFIE rw	TXFEIE rw	FIFOEN rw	M1 rw	EOBIE rw	RTOIE rw	DEAT rw					DEDT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVER8 rw	CMIE rw	MME rw	M0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXFNFIE rw	TCIE rw	RXFNEIE rw	IDLEIE rw	TE rw	RE rw	UESM rw	UE rw

Toggle fields

UE

Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the CK is always available when CLKEN = 1, regardless of the UE bit value..

UESM

Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 1985..

RE

Bit 2: Receiver enable This bit enables the receiver. It is set and cleared by software..

TE

Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit (0 followed by 1) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to 1. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..

IDLEIE

Bit 4: IDLE interrupt enable This bit is set and cleared by software..

RXFNEIE

Bit 5: RXFIFO not empty interrupt enable This bit is set and cleared by software..

TCIE

Bit 6: Transmission complete interrupt enable This bit is set and cleared by software..

TXFNFIE

Bit 7: TXFIFO not full interrupt enable This bit is set and cleared by software..

PEIE

Bit 8: PE interrupt enable This bit is set and cleared by software..

PS

Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UE = 0)..

PCE

Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UE = 0)..

WAKE

Bit 11: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..

M0

Bit 12: Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UE = 0)..

MME

Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..

CMIE

Bit 14: Character match interrupt enable This bit is set and cleared by software..

OVER8

Bit 15: Oversampling mode This bit can only be written when the USART is disabled (UE = 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared..

DEDT

Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

DEAT

Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOIE

Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ..

EOBIE

Bit 27: End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

M1

Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = 00: 1 start bit, 8 Data bits, n Stop bit M[1:0] = 01: 1 start bit, 9 Data bits, n Stop bit M[1:0] = 10: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..

FIFOEN

Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..

TXFEIE

Bit 30: TXFIFO empty interrupt enable This bit is set and cleared by software..

RXFFIE

Bit 31: RXFIFO Full interrupt enable This bit is set and cleared by software..

CR2

USART control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD rw								RTOEN rw	ABRMOD rw		ABREN rw	MSBFIRST rw	DATAINV rw	TXINV rw	RXINV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWAP rw	LINEN rw	STOP rw		CLKEN rw	CPOL rw	CPHA rw	LBCL rw		LBDIE rw	LBDL rw	ADDM7 rw	DIS_NSS rw			SLVEN rw

Toggle fields

SLVEN

Bit 0: Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

DIS_NSS

Bit 3: When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UE = 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively..

LBDL

Bit 5: LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UE = 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

LBDIE

Bit 6: LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

LBCL

Bit 8: Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the CK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CPHA

Bit 9: Clock phase This bit is used to select the phase of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see and ) This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CPOL

Bit 10: Clock polarity This bit enables the user to select the polarity of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CLKEN

Bit 11: Clock enable This bit enables the user to enable the CK pin. This bit can only be written when the USART is disabled (UE = 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to . In Smartcard mode, in order to provide correctly the CK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1.

STOP

Bits 12-13: stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UE = 0)..

LINEN

Bit 14: LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to ..

SWAP

Bit 15: Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..

RXINV

Bit 16: RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UE = 0)..

TXINV

Bit 17: TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UE = 0)..

DATAINV

Bit 18: Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..

MSBFIRST

Bit 19: Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..

ABREN

Bit 20: Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

ABRMOD

Bits 21-22: Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UE = 0). Note: If DATAINV = 1 and/or MSBFIRST = 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

RTOEN

Bit 23: Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to ..

ADD

Bits 24-31: Address of the USART node These bits give the address of the USART node in Mute mode or a character code to be recognized in low-power or Run mode: In Mute mode: they are used in multiprocessor communication to wakeup from Mute mode with 4-bit/7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. In 4-bit address mark detection, only ADD[3:0] bits are used. In low-power mode: they are used for wake up from low-power mode on character match. When WUS[1:0] is programmed to 0b00 (WUF active on address match), the wakeup from low-power mode is performed when the received character corresponds to the character programmed through ADD[6:0] or ADD[3:0] bitfield (depending on ADDM7 bit), and WUF interrupt is enabled by setting WUFIE bit. The MSB of the character sent by transmitter should be equal to 1. In Run mode with Mute mode inactive (for example, end-of-block detection in ModBus protocol): the whole received character (8 bits) is compared to ADD[7:0] value and CMF flag is set on match. An interrupt is generated if the CMIE bit is set. These bits can only be written when the reception is disabled (RE = 0) or when the USART is disabled (UE = 0)..

CR3

USART control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXFTCFG rw			RXFTIE rw	RXFTCFG rw			TCBGTIE rw	TXFTIE rw	WUFIE rw	WUS rw		SCARCNT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DEP rw	DEM rw	DDRE rw	OVRDIS rw	ONEBIT rw	CTSIE rw	CTSE rw	RTSE rw	DMAT rw	DMAR rw	SCEN rw	NACK rw	HDSEL rw	IRLP rw	IREN rw	EIE rw

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EIE

Bit 0: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE = 1 or ORE = 1 or NE = 1 or UDR = 1 in the USART_ISR register)..

IREN

Bit 1: IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

IRLP

Bit 2: IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

HDSEL

Bit 3: Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UE = 0)..

NACK

Bit 4: Smartcard NACK enable This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

SCEN

Bit 5: Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

DMAR

Bit 6: DMA enable receiver This bit is set/reset by software.

DMAT

Bit 7: DMA enable transmitter This bit is set/reset by software.

RTSE

Bit 8: RTS enable This bit can only be written when the USART is disabled (UE = 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CTSE

Bit 9: CTS enable This bit can only be written when the USART is disabled (UE = 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CTSIE

Bit 10: CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

ONEBIT

Bit 11: One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UE = 0)..

OVRDIS

Bit 12: Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UE = 0). Note: This control bit enables checking the communication flow w/o reading the data.

DDRE

Bit 13: DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error..

DEM

Bit 14: Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. ..

DEP

Bit 15: Driver enable polarity selection This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

SCARCNT

Bits 17-19: Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UE = 0). When the USART is enabled (UE = 1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

WUS

Bits 20-21: Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 1985..

WUFIE

Bit 22: Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 1985..

TXFTIE

Bit 23: TXFIFO threshold interrupt enable This bit is set and cleared by software..

TCBGTIE

Bit 24: Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration Remaining combinations: Reserved.

RXFTIE

Bit 28: RXFIFO threshold interrupt enable This bit is set and cleared by software..

TXFTCFG

Bits 29-31: TXFIFO threshold configuration Remaining combinations: Reserved.

BRR

USART baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRR rw

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BRR

Bits 0-15: USART baud rate BRR[15:4] BRR[15:4] = USARTDIV[15:4] BRR[3:0] When OVER8 = 0, BRR[3:0] = USARTDIV[3:0]. When OVER8 = 1: BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. BRR[3] must be kept cleared..

GTPR

USART guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
GT rw								PSC rw

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PSC

Bits 0-7: Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power baud rate PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0] = Prescaler value PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... ... This bitfield can only be written when the USART is disabled (UE = 0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to 0 when the Smartcard and IrDA modes are not supported. Refer to ..

GT

Bits 8-15: Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UE = 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOR

USART receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BLEN rw								RTO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RTO rw

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RTO

Bits 0-23: Receiver timeout value This bitfield gives the Receiver timeout value in terms of number of bits during which there is no activity on the RX line. In standard mode, the RTOF flag is set if, after the last received character, no new start bit is detected for more than the RTO value. In Smartcard mode, this value is used to implement the CWT and BWT. See Smartcard chapter for more details. In the standard, the CWT/BWT measurement is done starting from the start bit of the last received character. Note: This value must only be programmed once per received character..

BLEN

Bits 24-31: Block Length This bitfield gives the Block length in Smartcard T = 1 Reception. Its value equals the number of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. Examples: BLEN = 0: 0 information characters + LEC BLEN = 1: 0 information characters + CRC BLEN = 255: 254 information characters + CRC (total 256 characters)) In Smartcard mode, the Block length counter is reset when TXE = 0 (TXFE = 0 in case FIFO mode is enabled). This bitfield can be used also in other modes. In this case, the Block length counter is reset when RE = 0 (receiver disabled) and/or when the EOBCF bit is written to 1. Note: This value can be programmed after the start of the block reception (using the data from the LEN character in the Prologue Field). It must be programmed only once per received block..

RQR

USART request register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											TXFRQ w	RXFRQ w	MMRQ w	SBKRQ w	ABRRQ w

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ABRRQ

Bit 0: Auto baud rate request Writing 1 to this bit resets the ABRF and ABRE flags in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..

SBKRQ

Bit 1: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit..

MMRQ

Bit 2: Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag..

RXFRQ

Bit 3: Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition..

TXFRQ

Bit 4: Transmit data flush request When FIFO mode is disabled, writing 1 to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register..

ISR_disabled

USART interrupt and status register [alternate]

Offset: 0x1c, size: 32, reset: 0x008000C0, access: Unspecified

24/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						TCBGT r			REACK r	TEACK r	WUF r	RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABRF r	ABRE r	UDR r	EOBF r	RTOF r	CTS r	CTSIF r	LBDF r	TXE r	TC r	RXNE r	IDLE r	ORE r	NE r	FE r	PE r

Toggle fields

PE

Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register..

FE

Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR1 register..

NE

Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 2012)..

ORE

Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXNE = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXNEIE = 1 or EIE = 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..

IDLE

Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MME = 1), IDLE is set if the USART is not mute (RWU = 0), whatever the Mute mode selected by the WAKE bit. If RWU = 1, IDLE is not set..

RXNE

Bit 5: Read data register not empty RXNE bit is set by hardware when the content of the USART_RDR shift register has been transferred to the USART_RDR register. It is cleared by reading from the USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXNEIE = 1 in the USART_CR1 register..

TC

Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXE is set. An interrupt is generated if TCIE = 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately..

TXE

Bit 7: Transmit data register empty TXE is set by hardware when the content of the USART_TDR register has been transferred into the shift register. It is cleared by writing to the USART_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T = 0 mode, in case of transmission failure). An interrupt is generated if the TXEIE bit = 1 in the USART_CR1 register..

LBDF

Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ..

CTSIF

Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE = 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

CTS

Bit 10: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

RTOF

Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE = 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..

EOBF

Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example T = 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ..

UDR

Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..

ABRE

Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

ABRF

Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXNE is also set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABRE = 1) (ABRE, RXNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

BUSY

Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..

CMF

Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE = 1in the USART_CR1 register..

SBKF

Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..

RWU

Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

WUF

Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIE = 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TEACK

Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE = 0, followed by TE = 1 in the USART_CR1 register, in order to respect the TE = 0 minimum period..

REACK

Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TCBGT

Bit 25: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is 1. Refer to on page 1985..

ISR_enabled

USART interrupt and status register [alternate]

Offset: 0x1c, size: 32, reset: 0x008000C0, access: Unspecified

28/28 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TXFT r	RXFT r	TCBGT r	RXFF r	TXFE r	REACK r	TEACK r	WUF r	RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABRF r	ABRE r	UDR r	EOBF r	RTOF r	CTS r	CTSIF r	LBDF r	TXFNF r	TC r	RXFNE r	IDLE r	ORE r	NE r	FE r	PE r

Toggle fields

PE

Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR..

FE

Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR..

NE

Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 2012). This error is associated with the character in the USART_RDR..

ORE

Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIE = 1 or EIE = 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..

IDLE

Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MME = 1), IDLE is set if the USART is not mute (RWU = 0), whatever the Mute mode selected by the WAKE bit. If RWU = 1, IDLE is not set..

RXFNE

Bit 5: RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIE = 1 in the USART_CR1 register..

TC

Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIE = 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set..

TXFNF

Bit 7: TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). This bit is used during single buffer transmission..

LBDF

Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ..

CTSIF

Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE = 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

CTS

Bit 10: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..

RTOF

Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE = 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..

EOBF

Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example T = 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ..

UDR

Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..

ABRE

Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

ABRF

Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABRE = 1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..

BUSY

Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..

CMF

Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE = 1in the USART_CR1 register..

SBKF

Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..

RWU

Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

WUF

Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIE = 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TEACK

Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE = 0, followed by TE = 1 in the USART_CR1 register, in order to respect the TE = 0 minimum period..

REACK

Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..

TXFE

Bit 23: TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit = 1 (bit 30) in the USART_CR1 register..

RXFF

Bit 24: RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit = 1 in the USART_CR1 register..

TCBGT

Bit 25: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is 1. Refer to on page 1985..

RXFT

Bit 26: RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit = 1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to 101, RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data..

TXFT

Bit 27: TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit = 1 (bit 31) in the USART_CR3 register..

ICR

USART interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											WUCF w			CMCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		UDRCF w	EOBCF w	RTOCF w		CTSCF w	LBDCF w	TCBGTCF w	TCCF w	TXFECF w	IDLECF w	ORECF w	NECF w	FECF w	PECF w

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PECF

Bit 0: Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register..

FECF

Bit 1: Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register..

NECF

Bit 2: Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register..

ORECF

Bit 3: Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register..

IDLECF

Bit 4: Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register..

TXFECF

Bit 5: TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register..

TCCF

Bit 6: Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register..

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register..

LBDCF

Bit 8: LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..

CTSCF

Bit 9: CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..

RTOCF

Bit 11: Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to page 1985..

EOBCF

Bit 12: End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..

UDRCF

Bit 13: SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to.

CMCF

Bit 17: Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register..

WUCF

Bit 20: Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 1985..

RDR

USART receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							RDR r

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RDR

Bits 0-8: Receive data value Contains the received data character. The RDR register provides the parallel interface between the input shift register and the internal bus (see ). When receiving with the parity enabled, the value read in the MSB bit is the received parity bit..

TDR

USART transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							TDR rw

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TDR

Bits 0-8: Transmit data value Contains the data character to be transmitted. The USART_TDR register provides the parallel interface between the internal bus and the output shift register (see ). When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. Note: This register must be written only when TXE/TXFNF = 1..

PRESC

USART prescaler register

Offset: 0x2c, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PRESCALER rw

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PRESCALER

Bits 0-3: Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256..

WWDG

0x40002c00: WWDG register block

0/6 fields covered.

Toggle register map

Offset	Name	13	9	7	6	0
0x0	CR			WDGA	T
0x4	CFR	WDGTB	EWI		W
0x8	SR					EWIF

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CR

WWDG control register

Offset: 0x0, size: 32, reset: 0x0000007F, access: Unspecified

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								WDGA rw	T rw

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T

Bits 0-6: 7-bit counter (MSB to LSB) These bits contain the value of the watchdog counter, decremented every (4096 x 2WDGTB[1:0]) PCLK cycles. A reset is produced when it is decremented from 0x40 to 0x3F (T6 becomes cleared)..

WDGA

Bit 7: Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset..

CFR

WWDG configuration register

Offset: 0x4, size: 32, reset: 0x0000007F, access: Unspecified

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		WDGTB rw				EWI rw			W rw

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W

Bits 0-6: 7-bit window value These bits contain the window value to be compared with the down-counter..

EWI

Bit 9: Early wakeup interrupt When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is only cleared by hardware after a reset..

WDGTB

Bits 11-13: Timer base The timebase of the prescaler can be modified as follows:.

SR

WWDG status register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EWIF rw

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EWIF

Bit 0: Early wakeup interrupt flag This bit is set by hardware when the counter has reached the value 0x40. It must be cleared by software by writing 0. Writing 1 has no effect. This bit is also set if the interrupt is not enabled..