ADRDY

Bit 0: ADC ready This bit is set by hardware after the ADC has been enabled (ADEN = 1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it..

Allowed values:
0: B_0x0: ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software)
1: B_0x1: ADC is ready to start conversion

EOSMP

Bit 1: End of sampling flag This bit is set by hardware during the conversion, at the end of the sampling phase.It is cleared by software by programming it to 1 ..

Allowed values:
0: B_0x0: Not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software)
1: B_0x1: End of sampling phase reached

EOC

Bit 2: End of conversion flag This bit is set by hardware at the end of each conversion of a channel when a new data result is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register..

Allowed values:
0: B_0x0: Channel conversion not complete (or the flag event was already acknowledged and cleared by software)
1: B_0x1: Channel conversion complete

EOS

Bit 3: End of sequence flag This bit is set by hardware at the end of the conversion of a sequence of channels selected by the CHSEL bits. It is cleared by software writing 1 to it..

Allowed values:
0: B_0x0: Conversion sequence not complete (or the flag event was already acknowledged and cleared by software)
1: B_0x1: Conversion sequence complete

OVR

Bit 4: ADC overrun This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete while the EOC flag was already set. It is cleared by software writing 1 to it..

Allowed values:
0: B_0x0: No overrun occurred (or the flag event was already acknowledged and cleared by software)
1: B_0x1: Overrun has occurred

AWD1

Bit 7: Analog watchdog 1 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_TR1 and ADC_HR1 registers. It is cleared by software by programming it to 1..

Allowed values:
0: B_0x0: No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software)
1: B_0x1: Analog watchdog event occurred

AWD2

Bit 8: Analog watchdog 2 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD2TR and ADC_AWD2TR registers. It is cleared by software programming it it..

Allowed values:
0: B_0x0: No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software)
1: B_0x1: Analog watchdog event occurred

AWD3

Bit 9: Analog watchdog 3 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD3TR and ADC_AWD3TR registers. It is cleared by software by programming it to 1..

Allowed values:
0: B_0x0: No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software)
1: B_0x1: Analog watchdog event occurred

EOCAL

Bit 11: End Of Calibration flag This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it..

Allowed values:
0: B_0x0: Calibration is not complete
1: B_0x1: Calibration is complete

CCRDY

Bit 13: Channel Configuration Ready flag This flag bit is set by hardware when the channel configuration is applied after programming to ADC_CHSELR register or changing CHSELRMOD or SCANDIR. It is cleared by software by programming it to it. Note: When the software configures the channels (by programming ADC_CHSELR or changing CHSELRMOD or SCANDIR), it must wait until the CCRDY flag rises before configuring again or starting conversions, otherwise the new configuration (or the START bit) is ignored. Once the flag is asserted, if the software needs to configure again the channels, it must clear the CCRDY flag before proceeding with a new configuration..

Allowed values:
0: B_0x0: Channel configuration update not applied.
1: B_0x1: Channel configuration update is applied.

ADRDYIE

Bit 0: ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADRDY interrupt disabled.
1: B_0x1: ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.

EOSMPIE

Bit 1: End of sampling flag interrupt enable This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: EOSMP interrupt disabled.
1: B_0x1: EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.

EOCIE

Bit 2: End of conversion interrupt enable This bit is set and cleared by software to enable/disable the end of conversion interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: EOC interrupt disabled
1: B_0x1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.

EOSIE

Bit 3: End of conversion sequence interrupt enable This bit is set and cleared by software to enable/disable the end of sequence of conversions interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: EOS interrupt disabled
1: B_0x1: EOS interrupt enabled. An interrupt is generated when the EOS bit is set.

OVRIE

Bit 4: Overrun interrupt enable This bit is set and cleared by software to enable/disable the overrun interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: Overrun interrupt disabled
1: B_0x1: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.

AWD1IE

Bit 7: Analog watchdog 1 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: Analog watchdog interrupt disabled
1: B_0x1: Analog watchdog interrupt enabled

AWD2IE

Bit 8: Analog watchdog 2 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: Analog watchdog interrupt disabled
1: B_0x1: Analog watchdog interrupt enabled

AWD3IE

Bit 9: Analog watchdog 3 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: Analog watchdog interrupt disabled
1: B_0x1: Analog watchdog interrupt enabled

EOCALIE

Bit 11: End of calibration interrupt enable This bit is set and cleared by software to enable/disable the end of calibration interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: End of calibration interrupt disabled
1: B_0x1: End of calibration interrupt enabled

CCRDYIE

Bit 13: Channel Configuration Ready Interrupt enable This bit is set and cleared by software to enable/disable the channel configuration ready interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: Channel configuration ready interrupt disabled
1: B_0x1: Channel configuration ready interrupt enabled

ADEN

Bit 0: ADC enable command This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the ADRDY flag has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL = 0, ADSTP = 0, ADSTART = 0, ADDIS = 0 and ADEN = 0).

Allowed values:
0: B_0x0: ADC is disabled (OFF state)
1: B_0x1: Write 1 to enable the ADC.

ADDIS

Bit 1: ADC disable command.

Allowed values:
0: B_0x0: No ADDIS command ongoing
1: B_0x1: Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress.

ADSTART

Bit 2: ADC start conversion command This bit is set by software to start ADC conversion. Depending on the EXTEN [1:0] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: In single conversion mode (CONT = 0, DISCEN = 0), when software trigger is selected (EXTEN = 00): at the assertion of the end of Conversion Sequence (EOS) flag. In discontinuous conversion mode(CONT = 0, DISCEN = 1), when the software trigger is selected (EXTEN = 00): at the assertion of the end of Conversion (EOC) flag. In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is cleared by hardware. Note: The software is allowed to set ADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC). Note: After writing to ADC_CHSELR register or changing CHSELRMOD or SCANDIRW, it is mandatory to wait until CCRDY flag is asserted before setting ADSTART, otherwise, the value written to ADSTART is ignored..

Allowed values:
0: B_0x0: No ADC conversion is ongoing.
1: B_0x1: Write 1 to start the ADC. Read 1 means that the ADC is operating and may be converting.

ADSTP

Bit 4: ADC stop conversion command.

Allowed values:
0: B_0x0: No ADC stop conversion command ongoing
1: B_0x1: Write 1 to stop the ADC. Read 1 means that an ADSTP command is in progress.

ADVREGEN

Bit 28: ADC Voltage Regulator Enable This bit is set by software, to enable the ADC internal voltage regulator. The voltage regulator output is available after t_{ADCVREG_STUP}. It is cleared by software to disable the voltage regulator. It can be cleared only if ADEN is et to 0. Note: The software is allowed to program this bit field only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)..

Allowed values:
0: B_0x0: ADC voltage regulator disabled
1: B_0x1: ADC voltage regulator enabled

ADCAL

Bit 31: ADC calibration This bit is set by software to start the calibration of the ADC. It is cleared by hardware after calibration is complete. Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0, AUTOFF = 0, and ADEN = 0). Note: The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN = 1 and ADSTART = 0 (ADC enabled and no conversion is ongoing)..

Allowed values:
0: B_0x0: Calibration complete
1: B_0x1: Write 1 to calibrate the ADC. Read at 1 means that a calibration is in progress.

DMAEN

Bit 0: Direct memory access enable This bit is set and cleared by software to enable the generation of DMA requests. This allows the DMA controller to be used to manage automatically the converted data. For more details, refer to Section 16.6.5: Managing converted data using the DMA on page 325..

Allowed values:
0: B_0x0: DMA disabled
1: B_0x1: DMA enabled

DMACFG

Bit 1: Direct memory access configuration This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN = 1. For more details, refer to Section 16.6.5: Managing converted data using the DMA on page 325..

Allowed values:
0: B_0x0: DMA one shot mode selected
1: B_0x1: DMA circular mode selected

SCANDIR

Bit 2: Scan sequence direction This bit is set and cleared by software to select the direction in which the channels is scanned in the sequence. It is effective only if CHSELMOD bit is cleared. Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0: B_0x0: Upward scan (from CHSEL0 to CHSEL22)
1: B_0x1: Backward scan (from CHSEL22 to CHSEL0)

RES

Bits 3-4: Data resolution These bits are written by software to select the resolution of the conversion..

Allowed values:
0: B_0x0: 12 bits
1: B_0x1: 10 bits
2: B_0x2: 8 bits
3: B_0x3: 6 bits

ALIGN

Bit 5: Data alignment This bit is set and cleared by software to select right or left alignment. Refer to Figure 43: Data alignment and resolution (oversampling disabled: OVSE = 0) on page 323.

Allowed values:
0: B_0x0: Right alignment
1: B_0x1: Left alignment

EXTSEL

Bits 6-8: External trigger selection These bits select the external event used to trigger the start of conversion (refer to Table 67: External triggers for details):.

Allowed values:
0: B_0x0: TRG0
1: B_0x1: TRG1
2: B_0x2: TRG2
3: B_0x3: TRG3
4: B_0x4: TRG4
5: B_0x5: TRG5
6: B_0x6: TRG6
7: B_0x7: TRG7

EXTEN

Bits 10-11: External trigger enable and polarity selection These bits are set and cleared by software to select the external trigger polarity and enable the trigger..

Allowed values:
0: B_0x0: Hardware trigger detection disabled (conversions can be started by software)
1: B_0x1: Hardware trigger detection on the rising edge
2: B_0x2: Hardware trigger detection on the falling edge
3: B_0x3: Hardware trigger detection on both the rising and falling edges

OVRMOD

Bit 12: Overrun management mode This bit is set and cleared by software and configure the way data overruns are managed..

Allowed values:
0: B_0x0: ADC_DR register is preserved with the old data when an overrun is detected.
1: B_0x1: ADC_DR register is overwritten with the last conversion result when an overrun is detected.

CONT

Bit 13: Single / continuous conversion mode This bit is set and cleared by software. If it is set, conversion takes place continuously until it is cleared. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1..

Allowed values:
0: B_0x0: Single conversion mode
1: B_0x1: Continuous conversion mode

WAIT

Bit 14: Wait conversion mode This bit is set and cleared by software to enable/disable wait conversion mode.^..

Allowed values:
0: B_0x0: Wait conversion mode off
1: B_0x1: Wait conversion mode on

AUTOFF

Bit 15: Auto-off mode This bit is set and cleared by software to enable/disable auto-off mode.^..

Allowed values:
0: B_0x0: Auto-off mode disabled
1: B_0x1: Auto-off mode enabled

DISCEN

Bit 16: Discontinuous mode This bit is set and cleared by software to enable/disable discontinuous mode. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1..

Allowed values:
0: B_0x0: Discontinuous mode disabled
1: B_0x1: Discontinuous mode enabled

CHSELRMOD

Bit 21: Mode selection of the ADC_CHSELR register This bit is set and cleared by software to control the ADC_CHSELR feature: Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0: B_0x0: Each bit of the ADC_CHSELR register enables an input
1: B_0x1: ADC_CHSELR register is able to sequence up to 8 channels

AWD1SGL

Bit 22: Enable the watchdog on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWDCH[4:0] bits or on all the channels.

Allowed values:
0: B_0x0: Analog watchdog 1 enabled on all channels
1: B_0x1: Analog watchdog 1 enabled on a single channel

AWD1EN

Bit 23: Analog watchdog enable This bit is set and cleared by software..

Allowed values:
0: B_0x0: Analog watchdog 1 disabled
1: B_0x1: Analog watchdog 1 enabled

AWD1CH

Bits 26-30: Analog watchdog channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. ..... Others: Reserved Note: The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR register..

Allowed values:
0: B_0x0: ADC analog input Channel 0 monitored by AWD
1: B_0x1: ADC analog input Channel 1 monitored by AWD
22: B_0x16: ADC analog input Channel 22 monitored by AWD

OVSE

Bit 0: Oversampler Enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADEN bit is cleared..

Allowed values:
0: B_0x0: Oversampler disabled
1: B_0x1: Oversampler enabled

OVSR

Bits 2-4: Oversampling ratio This bit filed defines the number of oversampling ratio. Note: The software is allowed to write this bit only when ADEN bit is cleared..

Allowed values:
0: B_0x0: 2x
1: B_0x1: 4x
2: B_0x2: 8x
3: B_0x3: 16x
4: B_0x4: 32x
5: B_0x5: 64x
6: B_0x6: 128x
7: B_0x7: 256x

OVSS

Bits 5-8: Oversampling shift This bit is set and cleared by software. Others: Reserved Note: The software is allowed to write this bit only when ADEN bit is cleared..

Allowed values:
0: B_0x0: No shift
1: B_0x1: Shift 1-bit
2: B_0x2: Shift 2-bits
3: B_0x3: Shift 3-bits
4: B_0x4: Shift 4-bits
5: B_0x5: Shift 5-bits
6: B_0x6: Shift 6-bits
7: B_0x7: Shift 7-bits
8: B_0x8: Shift 8-bits

TOVS

Bit 9: Triggered Oversampling This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADEN bit is cleared..

Allowed values:
0: B_0x0: All oversampled conversions for a channel are done consecutively after a trigger
1: B_0x1: Each oversampled conversion for a channel needs a trigger

LFTRIG

Bit 29: Low frequency trigger mode enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADEN bit is cleared..

Allowed values:
0: B_0x0: Low Frequency Trigger Mode disabled
1: B_0x1: Low Frequency Trigger Mode enabled

CKMODE

Bits 30-31: ADC clock mode These bits are set and cleared by software to define how the analog ADC is clocked: In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)..

Allowed values:
0: B_0x0: ADCCLK (Asynchronous clock mode), generated at product level (refer to RCC section)
1: B_0x1: PCLK/2 (Synchronous clock mode)
2: B_0x2: PCLK/4 (Synchronous clock mode)
3: B_0x3: PCLK (Synchronous clock mode). This configuration must be enabled only if PCLK has a 50% duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle)

SMP1

Bits 0-2: Sampling time selection 1 These bits are written by software to select the sampling time that applies to all channels. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: 1.5 ADC clock cycles
1: B_0x1: 3.5 ADC clock cycles
2: B_0x2: 7.5 ADC clock cycles
3: B_0x3: 12.5 ADC clock cycles
4: B_0x4: 19.5 ADC clock cycles
5: B_0x5: 39.5 ADC clock cycles
6: B_0x6: 79.5 ADC clock cycles
7: B_0x7: 160.5 ADC clock cycles

SMP2

Bits 4-6: Sampling time selection 2 These bits are written by software to select the sampling time that applies to all channels. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: 1.5 ADC clock cycles
1: B_0x1: 3.5 ADC clock cycles
2: B_0x2: 7.5 ADC clock cycles
3: B_0x3: 12.5 ADC clock cycles
4: B_0x4: 19.5 ADC clock cycles
5: B_0x5: 39.5 ADC clock cycles
6: B_0x6: 79.5 ADC clock cycles
7: B_0x7: 160.5 ADC clock cycles

SMPSEL0

Bit 8: Channel-x sampling time selection (x = 22 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: Refer to Section 16.3: ADC implementation for the maximum number of channels..

Allowed values:
0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL1

Bit 9: Channel-x sampling time selection (x = 22 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: Refer to Section 16.3: ADC implementation for the maximum number of channels..

Allowed values:
0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL2

Bit 10: Channel-x sampling time selection (x = 22 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: Refer to Section 16.3: ADC implementation for the maximum number of channels..

Allowed values:
0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL3

Bit 11: Channel-x sampling time selection (x = 22 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: Refer to Section 16.3: ADC implementation for the maximum number of channels..

Allowed values:
0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL4

Bit 12: Channel-x sampling time selection (x = 22 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: Refer to Section 16.3: ADC implementation for the maximum number of channels..

Allowed values:
0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL5

Bit 13: Channel-x sampling time selection (x = 22 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: Refer to Section 16.3: ADC implementation for the maximum number of channels..

Allowed values:
0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL6

Bit 14: Channel-x sampling time selection (x = 22 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: Refer to Section 16.3: ADC implementation for the maximum number of channels..

Allowed values:
0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL7

Bit 15: Channel-x sampling time selection (x = 22 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: Refer to Section 16.3: ADC implementation for the maximum number of channels..

Allowed values:
0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL8

Bit 16: Channel-x sampling time selection (x = 22 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: Refer to Section 16.3: ADC implementation for the maximum number of channels..

Allowed values:
0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL9

Bit 17: Channel-x sampling time selection (x = 22 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: Refer to Section 16.3: ADC implementation for the maximum number of channels..

Allowed values:
0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL10

Bit 18: Channel-x sampling time selection (x = 22 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: Refer to Section 16.3: ADC implementation for the maximum number of channels..

Allowed values:
0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL11

Bit 19: Channel-x sampling time selection (x = 22 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: Refer to Section 16.3: ADC implementation for the maximum number of channels..

Allowed values:
0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL12

Bit 20: Channel-x sampling time selection (x = 22 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: Refer to Section 16.3: ADC implementation for the maximum number of channels..

Allowed values:
0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL13

Bit 21: Channel-x sampling time selection (x = 22 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: Refer to Section 16.3: ADC implementation for the maximum number of channels..

Allowed values:
0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL14

Bit 22: Channel-x sampling time selection (x = 22 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: Refer to Section 16.3: ADC implementation for the maximum number of channels..

Allowed values:
0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL15

Bit 23: Channel-x sampling time selection (x = 22 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: Refer to Section 16.3: ADC implementation for the maximum number of channels..

Allowed values:
0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL16

Bit 24: Channel-x sampling time selection (x = 22 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: Refer to Section 16.3: ADC implementation for the maximum number of channels..

Allowed values:
0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL17

Bit 25: Channel-x sampling time selection (x = 22 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: Refer to Section 16.3: ADC implementation for the maximum number of channels..

Allowed values:
0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL18

Bit 26: Channel-x sampling time selection (x = 22 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: Refer to Section 16.3: ADC implementation for the maximum number of channels..

Allowed values:
0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL19

Bit 27: Channel-x sampling time selection (x = 22 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: Refer to Section 16.3: ADC implementation for the maximum number of channels..

Allowed values:
0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL20

Bit 28: Channel-x sampling time selection (x = 22 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: Refer to Section 16.3: ADC implementation for the maximum number of channels..

Allowed values:
0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL21

Bit 29: Channel-x sampling time selection (x = 22 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: Refer to Section 16.3: ADC implementation for the maximum number of channels..

Allowed values:
0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL22

Bit 30: Channel-x sampling time selection (x = 22 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: Refer to Section 16.3: ADC implementation for the maximum number of channels..

Allowed values:
0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

LT1

Bits 0-11: Analog watchdog 1 lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to Section 16.8: Analog window watchdogs on page 329..

HT1

Bits 16-27: Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to Section 16.8: Analog window watchdogs on page 329..

LT2

Bits 0-11: Analog watchdog 2 lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to Section 16.8: Analog window watchdogs on page 329..

HT2

Bits 16-27: Analog watchdog 2 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to Section 16.8: Analog window watchdogs on page 329..

CHSEL0

Bit 0: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0: B_0x0: Input Channel-x is not selected for conversion
1: B_0x1: Input Channel-x is selected for conversion

CHSEL1

Bit 1: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0: B_0x0: Input Channel-x is not selected for conversion
1: B_0x1: Input Channel-x is selected for conversion

CHSEL2

Bit 2: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0: B_0x0: Input Channel-x is not selected for conversion
1: B_0x1: Input Channel-x is selected for conversion

CHSEL3

Bit 3: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0: B_0x0: Input Channel-x is not selected for conversion
1: B_0x1: Input Channel-x is selected for conversion

CHSEL4

Bit 4: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0: B_0x0: Input Channel-x is not selected for conversion
1: B_0x1: Input Channel-x is selected for conversion

CHSEL5

Bit 5: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0: B_0x0: Input Channel-x is not selected for conversion
1: B_0x1: Input Channel-x is selected for conversion

CHSEL6

Bit 6: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0: B_0x0: Input Channel-x is not selected for conversion
1: B_0x1: Input Channel-x is selected for conversion

CHSEL7

Bit 7: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0: B_0x0: Input Channel-x is not selected for conversion
1: B_0x1: Input Channel-x is selected for conversion

CHSEL8

Bit 8: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0: B_0x0: Input Channel-x is not selected for conversion
1: B_0x1: Input Channel-x is selected for conversion

CHSEL9

Bit 9: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0: B_0x0: Input Channel-x is not selected for conversion
1: B_0x1: Input Channel-x is selected for conversion

CHSEL10

Bit 10: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0: B_0x0: Input Channel-x is not selected for conversion
1: B_0x1: Input Channel-x is selected for conversion

CHSEL11

Bit 11: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0: B_0x0: Input Channel-x is not selected for conversion
1: B_0x1: Input Channel-x is selected for conversion

CHSEL12

Bit 12: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0: B_0x0: Input Channel-x is not selected for conversion
1: B_0x1: Input Channel-x is selected for conversion

CHSEL13

Bit 13: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0: B_0x0: Input Channel-x is not selected for conversion
1: B_0x1: Input Channel-x is selected for conversion

CHSEL14

Bit 14: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0: B_0x0: Input Channel-x is not selected for conversion
1: B_0x1: Input Channel-x is selected for conversion

CHSEL15

Bit 15: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0: B_0x0: Input Channel-x is not selected for conversion
1: B_0x1: Input Channel-x is selected for conversion

CHSEL16

Bit 16: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0: B_0x0: Input Channel-x is not selected for conversion
1: B_0x1: Input Channel-x is selected for conversion

CHSEL17

Bit 17: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0: B_0x0: Input Channel-x is not selected for conversion
1: B_0x1: Input Channel-x is selected for conversion

CHSEL18

Bit 18: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0: B_0x0: Input Channel-x is not selected for conversion
1: B_0x1: Input Channel-x is selected for conversion

CHSEL19

Bit 19: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0: B_0x0: Input Channel-x is not selected for conversion
1: B_0x1: Input Channel-x is selected for conversion

CHSEL20

Bit 20: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0: B_0x0: Input Channel-x is not selected for conversion
1: B_0x1: Input Channel-x is selected for conversion

CHSEL21

Bit 21: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0: B_0x0: Input Channel-x is not selected for conversion
1: B_0x1: Input Channel-x is selected for conversion

CHSEL22

Bit 22: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 35: ADC connectivity for ADC inputs connected to external channels and internal sources. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0: B_0x0: Input Channel-x is not selected for conversion
1: B_0x1: Input Channel-x is selected for conversion

SQ1

Bits 0-3: 1st conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

SQ2

Bits 4-7: 2nd conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

SQ3

Bits 8-11: 3rd conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

SQ4

Bits 12-15: 4th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

SQ5

Bits 16-19: 5th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

SQ6

Bits 20-23: 6th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

SQ7

Bits 24-27: 7th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

SQ8

Bits 28-31: 8th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates the end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. ... Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: CH0
1: B_0x1: CH1
12: B_0xC: CH12
13: B_0xD: CH13
14: B_0xE: CH14
15: B_0xF: No channel selected (End of sequence)

LT3

Bits 0-11: Analog watchdog 3lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to Section 16.8: Analog window watchdogs on page 329..

HT3

Bits 16-27: Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to Section 16.8: Analog window watchdogs on page 329..

DATA

Bits 0-15: Converted data These bits are read-only. They contain the conversion result from the last converted channel. The data are left- or right-aligned as shown in Figure 43: Data alignment and resolution (oversampling disabled: OVSE = 0) on page 323. Just after a calibration is complete, DATA[6:0] contains the calibration factor..

AWD2CH0

Bit 0: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD2
1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH1

Bit 1: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD2
1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH2

Bit 2: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD2
1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH3

Bit 3: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD2
1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH4

Bit 4: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD2
1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH5

Bit 5: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD2
1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH6

Bit 6: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD2
1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH7

Bit 7: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD2
1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH8

Bit 8: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD2
1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH9

Bit 9: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD2
1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH10

Bit 10: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD2
1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH11

Bit 11: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD2
1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH12

Bit 12: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD2
1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH13

Bit 13: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD2
1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH14

Bit 14: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD2
1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH15

Bit 15: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD2
1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH16

Bit 16: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD2
1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH17

Bit 17: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD2
1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH18

Bit 18: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD2
1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH19

Bit 19: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD2
1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH20

Bit 20: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD2
1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH21

Bit 21: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD2
1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH22

Bit 22: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD2
1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD3CH0

Bit 0: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD3
1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH1

Bit 1: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD3
1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH2

Bit 2: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD3
1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH3

Bit 3: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD3
1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH4

Bit 4: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD3
1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH5

Bit 5: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD3
1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH6

Bit 6: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD3
1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH7

Bit 7: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD3
1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH8

Bit 8: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD3
1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH9

Bit 9: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD3
1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH10

Bit 10: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD3
1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH11

Bit 11: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD3
1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH12

Bit 12: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD3
1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH13

Bit 13: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD3
1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH14

Bit 14: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD3
1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH15

Bit 15: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD3
1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH16

Bit 16: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD3
1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH17

Bit 17: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD3
1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH18

Bit 18: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD3
1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH19

Bit 19: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD3
1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH20

Bit 20: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD3
1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH21

Bit 21: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD3
1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH22

Bit 22: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: ADC analog channel-x is not monitored by AWD3
1: B_0x1: ADC analog channel-x is monitored by AWD3

CALFACT

Bits 0-6: Calibration factor These bits are written by hardware or by software. Once a calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new conversion is launched. Just after a calibration is complete, DATA[6:0] contains the calibration factor. Note: Software can write these bits only when ADEN=1 (ADC is enabled and no calibration is ongoing and no conversion is ongoing)..

PRESC

Bits 18-21: ADC prescaler Set and cleared by software to select the frequency of the clock to the ADC. Other: Reserved Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)..

Allowed values:
0: B_0x0: input ADC clock not divided
1: B_0x1: input ADC clock divided by 2
2: B_0x2: input ADC clock divided by 4
3: B_0x3: input ADC clock divided by 6
4: B_0x4: input ADC clock divided by 8
5: B_0x5: input ADC clock divided by 10
6: B_0x6: input ADC clock divided by 12
7: B_0x7: input ADC clock divided by 16
8: B_0x8: input ADC clock divided by 32
9: B_0x9: input ADC clock divided by 64
10: B_0xA: input ADC clock divided by 128
11: B_0xB: input ADC clock divided by 256

VREFEN

Bit 22: V_REFINT enable This bit is set and cleared by software to enable/disable the V_REFINT. Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: V_REFINT disabled
1: B_0x1: V_REFINT enabled

TSEN

Bit 23: Temperature sensor enable This bit is set and cleared by software to enable/disable the temperature sensor. Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: B_0x0: Temperature sensor disabled
1: B_0x1: Temperature sensor enabled

DR

Bits 0-31: Data register bits This register is used to write new data to the CRC calculator. It holds the previous CRC calculation result when it is read. If the data size is less than 32 bits, the least significant bits are used to write/read the correct value..

IDR

Bits 0-31: General-purpose 32-bit data register bits These bits can be used as a temporary storage location for four bytes. This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register.

RESET

Bit 0: RESET bit This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware.

POLYSIZE

Bits 3-4: Polynomial size These bits control the size of the polynomial..

Allowed values:
0: B_0x0: 32 bit polynomial
1: B_0x1: 16 bit polynomial
2: B_0x2: 8 bit polynomial
3: B_0x3: 7 bit polynomial

REV_IN

Bits 5-6: Reverse input data This bitfield controls the reversal of the bit order of the input data.

Allowed values:
0: B_0x0: Bit order not affected
1: B_0x1: Bit reversal done by byte
2: B_0x2: Bit reversal done by half-word
3: B_0x3: Bit reversal done by word

REV_OUT

Bit 7: Reverse output data This bit controls the reversal of the bit order of the output data..

Allowed values:
0: B_0x0: Bit order not affected
1: B_0x1: Bit-reversed output format

CRC_INIT

Bits 0-31: Programmable initial CRC value This register is used to write the CRC initial value..

POL

Bits 0-31: Programmable polynomial This register is used to write the coefficients of the polynomial to be used for CRC calculation. If the polynomial size is less than 32 bits, the least significant bits have to be used to program the correct value..

DEV_ID

Bits 0-11: Device identifier This field indicates the device ID. Refer to Table 152..

REV_ID

Bits 16-31: Revision identifier This field indicates the revision of the device. Refer to Table 152..

DBG_STOP

Bit 1: Debug Stop mode Debug options in Stop mode. Upon Stop mode exit, the software must re-establish the desired clock configuration..

Allowed values:
0: B_0x0: All clocks disabled, including FCLK and HCLK. Upon Stop mode exit, the CPU is clocked by the HSI internal RC oscillator.
1: B_0x1: FCLK and HCLK running, derived from the internal RC oscillator remaining active. If Systick is enabled, it may generate periodic interrupt and wake up events.

DBG_STANDBY

Bit 2: Debug Standby and Shutdown modes Debug options in Standby or Shutdown mode..

Allowed values:
0: B_0x0: Digital part powered. From software point of view, exiting Standby and Shutdown modes is identical as fetching reset vector (except for status bits indicating that the MCU exits Standby)
1: B_0x1: Digital part powered and FCLK and HCLK running, derived from the internal RC oscillator remaining active. The MCU generates a system reset so that exiting Standby and Shutdown has the same effect as starting from reset.

DBG_TIM2_STOP

Bit 0: Clocking of TIM2 counter when the core is halted This bit enables/disables the clock to the counter of TIM2 when the core is halted: This bit is only available on STM32C071xx. On the other devices, it is reserved..

Allowed values:
0: B_0x0: Enable
1: B_0x1: Disable

DBG_TIM3_STOP

Bit 1: Clocking of TIM3 counter when the core is halted This bit enables/disables the clock to the counter of TIM3 when the core is halted:.

Allowed values:
0: B_0x0: Enable
1: B_0x1: Disable

DBG_RTC_STOP

Bit 10: Clocking of RTC counter when the core is halted This bit enables/disables the clock to the counter of RTC when the core is halted:.

Allowed values:
0: B_0x0: Enable
1: B_0x1: Disable

DBG_WWDG_STOP

Bit 11: Clocking of WWDG counter when the core is halted This bit enables/disables the clock to the counter of WWDG when the core is halted:.

Allowed values:
0: B_0x0: Enable
1: B_0x1: Disable

DBG_IWDG_STOP

Bit 12: Clocking of IWDG counter when the core is halted This bit enables/disables the clock to the counter of IWDG when the core is halted:.

Allowed values:
0: B_0x0: Enable
1: B_0x1: Disable

DBG_I2C1_SMBUS_TIMEOUT

Bit 21: SMBUS timeout when core is halted.

Allowed values:
0: B_0x0: Same behavior as in normal mode
1: B_0x1: The SMBUS timeout is frozen

DBG_TIM1_STOP

Bit 11: Clocking of TIM1 counter when the core is halted This bit enables/disables the clock to the counter of TIM1 when the core is halted:.

Allowed values:
0: B_0x0: Enable
1: B_0x1: Disable

DBG_TIM14_STOP

Bit 15: Clocking of TIM14 counter when the core is halted This bit enables/disables the clock to the counter of TIM14 when the core is halted:.

Allowed values:
0: B_0x0: Enable
1: B_0x1: Disable

DBG_TIM16_STOP

Bit 17: Clocking of TIM16 counter when the core is halted This bit enables/disables the clock to the counter of TIM16 when the core is halted:.

Allowed values:
0: B_0x0: Enable
1: B_0x1: Disable

DBG_TIM17_STOP

Bit 18: Clocking of TIM17 counter when the core is halted This bit enables/disables the clock to the counter of TIM17 when the core is halted:.

Allowed values:
0: B_0x0: Enable
1: B_0x1: Disable

GIF1

Bit 0: Global interrupt flag for channel 1.

Allowed values:
0: B_0x0: No TE, HT, or TC event
1: B_0x1: A TE, HT, or TC event occurred.

TCIF1

Bit 1: Transfer complete (TC) flag for channel 1.

Allowed values:
0: B_0x0: No TC event
1: B_0x1: A TC event occurred.

HTIF1

Bit 2: Half transfer (HT) flag for channel 1.

Allowed values:
0: B_0x0: No HT event
1: B_0x1: An HT event occurred.

TEIF1

Bit 3: Transfer error (TE) flag for channel 1.

Allowed values:
0: B_0x0: No TE event
1: B_0x1: A TE event occurred.

GIF2

Bit 4: Global interrupt flag for channel 2.

Allowed values:
0: B_0x0: No TE, HT, or TC event
1: B_0x1: A TE, HT, or TC event occurred.

TCIF2

Bit 5: Transfer complete (TC) flag for channel 2.

Allowed values:
0: B_0x0: No TC event
1: B_0x1: A TC event occurred.

HTIF2

Bit 6: Half transfer (HT) flag for channel 2.

Allowed values:
0: B_0x0: No HT event
1: B_0x1: An HT event occurred.

TEIF2

Bit 7: Transfer error (TE) flag for channel 2.

Allowed values:
0: B_0x0: No TE event
1: B_0x1: A TE event occurred.

GIF3

Bit 8: Global interrupt flag for channel 3.

Allowed values:
0: B_0x0: No TE, HT, or TC event
1: B_0x1: A TE, HT, or TC event occurred.

TCIF3

Bit 9: Transfer complete (TC) flag for channel 3.

Allowed values:
0: B_0x0: No TC event
1: B_0x1: A TC event occurred.

HTIF3

Bit 10: Half transfer (HT) flag for channel 3.

Allowed values:
0: B_0x0: No HT event
1: B_0x1: An HT event occurred.

TEIF3

Bit 11: Transfer error (TE) flag for channel 3.

Allowed values:
0: B_0x0: No TE event
1: B_0x1: A TE event occurred.

GIF4

Bit 12: global interrupt flag for channel 4.

Allowed values:
0: B_0x0: No TE, HT, or TC event
1: B_0x1: A TE, HT, or TC event occurred.

TCIF4

Bit 13: Transfer complete (TC) flag for channel 4.

Allowed values:
0: B_0x0: No TC event
1: B_0x1: A TC event occurred.

HTIF4

Bit 14: Half transfer (HT) flag for channel 4.

Allowed values:
0: B_0x0: No HT event
1: B_0x1: An HT event occurred.

TEIF4

Bit 15: Transfer error (TE) flag for channel 4.

Allowed values:
0: B_0x0: No TE event
1: B_0x1: A TE event occurred.

GIF5

Bit 16: global interrupt flag for channel 5.

Allowed values:
0: B_0x0: No TE, HT, or TC event
1: B_0x1: A TE, HT, or TC event occurred.

TCIF5

Bit 17: Transfer complete (TC) flag for channel 5.

Allowed values:
0: B_0x0: No TC event
1: B_0x1: A TC event occurred.

HTIF5

Bit 18: Half transfer (HT) flag for channel 5.

Allowed values:
0: B_0x0: No HT event
1: B_0x1: An HT event occurred.

TEIF5

Bit 19: Transfer error (TE) flag for channel 5.

Allowed values:
0: B_0x0: No TE event
1: B_0x1: A TE event occurred.

CGIF1

Bit 0: Global interrupt flag clear for channel 1.

CTCIF1

Bit 1: Transfer complete flag clear for channel 1.

CHTIF1

Bit 2: Half transfer flag clear for channel 1.

CTEIF1

Bit 3: Transfer error flag clear for channel 1.

CGIF2

Bit 4: Global interrupt flag clear for channel 2.

CTCIF2

Bit 5: Transfer complete flag clear for channel 2.

CHTIF2

Bit 6: Half transfer flag clear for channel 2.

CTEIF2

Bit 7: Transfer error flag clear for channel 2.

CGIF3

Bit 8: Global interrupt flag clear for channel 3.

CTCIF3

Bit 9: Transfer complete flag clear for channel 3.

CHTIF3

Bit 10: Half transfer flag clear for channel 3.

CTEIF3

Bit 11: Transfer error flag clear for channel 3.

CGIF4

Bit 12: Global interrupt flag clear for channel 4.

CTCIF4

Bit 13: Transfer complete flag clear for channel 4.

CHTIF4

Bit 14: Half transfer flag clear for channel 4.

CTEIF4

Bit 15: Transfer error flag clear for channel 4.

CGIF5

Bit 16: Global interrupt flag clear for channel 5.

CTCIF5

Bit 17: Transfer complete flag clear for channel 5.

CHTIF5

Bit 18: Half transfer flag clear for channel 5.

CTEIF5

Bit 19: Transfer error flag clear for channel 5.

EN

Bit 0: Channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: This bit is set and cleared by software..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

TCIE

Bit 1: Transfer complete interrupt enable Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

HTIE

Bit 2: Half transfer interrupt enable Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

TEIE

Bit 3: Transfer error interrupt enable Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

DIR

Bit 4: Data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Read from peripheral
1: B_0x1: Read from memory

CIRC

Bit 5: Circular mode Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

PINC

Bit 6: Peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this bit identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this bit identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

MINC

Bit 7: Memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this bit identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this bit identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

PSIZE

Bits 8-9: Peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: 8 bits
1: B_0x1: 16 bits
2: B_0x2: 32 bits

MSIZE

Bits 10-11: Memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: 8 bits
1: B_0x1: 16 bits
2: B_0x2: 32 bits

PL

Bits 12-13: Priority level Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Low
1: B_0x1: Medium
2: B_0x2: High
3: B_0x3: Very high

MEM2MEM

Bit 14: Memory-to-memory mode Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

NDT

Bits 0-15: Number of data to transfer (0 to 2¹⁶ - 1) This bitfield is updated by hardware when the channel is enabled: It is decremented after each single DMA read followed by write transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this bitfield is zero, no transfer can be served whatever the channel status (enabled or not). Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

PA

Bits 0-31: Peripheral address It contains the base address of the peripheral data register from/to which the data is read/written. When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE[1:0] = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this bitfield identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination address if DIR = 1 and the peripheral source address if DIR = 0. Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

MA

Bits 0-31: Peripheral address It contains the base address of the memory from/to which the data is read/written. When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE[1:0] = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this bitfield identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this bitfield identifies the peripheral source address if DIR = 1 and the peripheral destination address if DIR = 0. Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

EN

Bit 0: Channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: This bit is set and cleared by software..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

TCIE

Bit 1: Transfer complete interrupt enable Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

HTIE

Bit 2: Half transfer interrupt enable Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

TEIE

Bit 3: Transfer error interrupt enable Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

DIR

Bit 4: Data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Read from peripheral
1: B_0x1: Read from memory

CIRC

Bit 5: Circular mode Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

PINC

Bit 6: Peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this bit identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this bit identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

MINC

Bit 7: Memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this bit identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this bit identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

PSIZE

Bits 8-9: Peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: 8 bits
1: B_0x1: 16 bits
2: B_0x2: 32 bits

MSIZE

Bits 10-11: Memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: 8 bits
1: B_0x1: 16 bits
2: B_0x2: 32 bits

PL

Bits 12-13: Priority level Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Low
1: B_0x1: Medium
2: B_0x2: High
3: B_0x3: Very high

MEM2MEM

Bit 14: Memory-to-memory mode Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

NDT

Bits 0-15: Number of data to transfer (0 to 2¹⁶ - 1) This bitfield is updated by hardware when the channel is enabled: It is decremented after each single DMA read followed by write transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this bitfield is zero, no transfer can be served whatever the channel status (enabled or not). Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

PA

Bits 0-31: Peripheral address It contains the base address of the peripheral data register from/to which the data is read/written. When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE[1:0] = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this bitfield identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination address if DIR = 1 and the peripheral source address if DIR = 0. Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

MA

Bits 0-31: Peripheral address It contains the base address of the memory from/to which the data is read/written. When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE[1:0] = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this bitfield identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this bitfield identifies the peripheral source address if DIR = 1 and the peripheral destination address if DIR = 0. Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

EN

Bit 0: Channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: This bit is set and cleared by software..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

TCIE

Bit 1: Transfer complete interrupt enable Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

HTIE

Bit 2: Half transfer interrupt enable Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

TEIE

Bit 3: Transfer error interrupt enable Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

DIR

Bit 4: Data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Read from peripheral
1: B_0x1: Read from memory

CIRC

Bit 5: Circular mode Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

PINC

Bit 6: Peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this bit identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this bit identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

MINC

Bit 7: Memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this bit identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this bit identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

PSIZE

Bits 8-9: Peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: 8 bits
1: B_0x1: 16 bits
2: B_0x2: 32 bits

MSIZE

Bits 10-11: Memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: 8 bits
1: B_0x1: 16 bits
2: B_0x2: 32 bits

PL

Bits 12-13: Priority level Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Low
1: B_0x1: Medium
2: B_0x2: High
3: B_0x3: Very high

MEM2MEM

Bit 14: Memory-to-memory mode Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

NDT

Bits 0-15: Number of data to transfer (0 to 2¹⁶ - 1) This bitfield is updated by hardware when the channel is enabled: It is decremented after each single DMA read followed by write transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this bitfield is zero, no transfer can be served whatever the channel status (enabled or not). Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

PA

Bits 0-31: Peripheral address It contains the base address of the peripheral data register from/to which the data is read/written. When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE[1:0] = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this bitfield identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination address if DIR = 1 and the peripheral source address if DIR = 0. Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

MA

Bits 0-31: Peripheral address It contains the base address of the memory from/to which the data is read/written. When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE[1:0] = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this bitfield identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this bitfield identifies the peripheral source address if DIR = 1 and the peripheral destination address if DIR = 0. Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

EN

Bit 0: Channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: This bit is set and cleared by software..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

TCIE

Bit 1: Transfer complete interrupt enable Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

HTIE

Bit 2: Half transfer interrupt enable Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

TEIE

Bit 3: Transfer error interrupt enable Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

DIR

Bit 4: Data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Read from peripheral
1: B_0x1: Read from memory

CIRC

Bit 5: Circular mode Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

PINC

Bit 6: Peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this bit identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this bit identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

MINC

Bit 7: Memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this bit identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this bit identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

PSIZE

Bits 8-9: Peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: 8 bits
1: B_0x1: 16 bits
2: B_0x2: 32 bits

MSIZE

Bits 10-11: Memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: 8 bits
1: B_0x1: 16 bits
2: B_0x2: 32 bits

PL

Bits 12-13: Priority level Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Low
1: B_0x1: Medium
2: B_0x2: High
3: B_0x3: Very high

MEM2MEM

Bit 14: Memory-to-memory mode Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

NDT

Bits 0-15: Number of data to transfer (0 to 2¹⁶ - 1) This bitfield is updated by hardware when the channel is enabled: It is decremented after each single DMA read followed by write transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this bitfield is zero, no transfer can be served whatever the channel status (enabled or not). Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

PA

Bits 0-31: Peripheral address It contains the base address of the peripheral data register from/to which the data is read/written. When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE[1:0] = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this bitfield identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination address if DIR = 1 and the peripheral source address if DIR = 0. Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

MA

Bits 0-31: Peripheral address It contains the base address of the memory from/to which the data is read/written. When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE[1:0] = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this bitfield identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this bitfield identifies the peripheral source address if DIR = 1 and the peripheral destination address if DIR = 0. Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

EN

Bit 0: Channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: This bit is set and cleared by software..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

TCIE

Bit 1: Transfer complete interrupt enable Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

HTIE

Bit 2: Half transfer interrupt enable Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

TEIE

Bit 3: Transfer error interrupt enable Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

DIR

Bit 4: Data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Read from peripheral
1: B_0x1: Read from memory

CIRC

Bit 5: Circular mode Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

PINC

Bit 6: Peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this bit identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this bit identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

MINC

Bit 7: Memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this bit identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this bit identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

PSIZE

Bits 8-9: Peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: 8 bits
1: B_0x1: 16 bits
2: B_0x2: 32 bits

MSIZE

Bits 10-11: Memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: 8 bits
1: B_0x1: 16 bits
2: B_0x2: 32 bits

PL

Bits 12-13: Priority level Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Low
1: B_0x1: Medium
2: B_0x2: High
3: B_0x3: Very high

MEM2MEM

Bit 14: Memory-to-memory mode Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

Allowed values:
0: B_0x0: Disabled
1: B_0x1: Enabled

NDT

Bits 0-15: Number of data to transfer (0 to 2¹⁶ - 1) This bitfield is updated by hardware when the channel is enabled: It is decremented after each single DMA read followed by write transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this bitfield is zero, no transfer can be served whatever the channel status (enabled or not). Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

PA

Bits 0-31: Peripheral address It contains the base address of the peripheral data register from/to which the data is read/written. When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE[1:0] = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this bitfield identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination address if DIR = 1 and the peripheral source address if DIR = 0. Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

MA

Bits 0-31: Peripheral address It contains the base address of the memory from/to which the data is read/written. When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE[1:0] = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this bitfield identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this bitfield identifies the peripheral source address if DIR = 1 and the peripheral destination address if DIR = 0. Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..