STM32F100 Peripheral Coverage

ADC1

0x40012400: Analog to digital converter

77/81 fields covered.

Toggle register map

Offset	Name	29	26	24	23	22	21	20	19	17	15	14	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	SR																				STRT	JSTRT	JEOC	EOC	AWD
0x4	CR1				AWDEN	JAWDEN					DISCNUM		JDISCEN	DISCEN	JAUTO	AWDSGL	SCAN	JEOCIE	AWDIE	EOCIE	AWDCH
0x8	CR2				TSVREFE	SWSTART	JSWSTART	EXTTRIG	EXTSEL		JEXTTRIG	JEXTSEL		ALIGN			DMA					RSTCAL	CAL	CONT	ADON
0xc	SMPR1				SMP17			SMP16		SMP15	SMP15	SMP14		SMP13			SMP12			SMP11			SMP10
0x10	SMPR2	SMP9	SMP8		SMP7			SMP6		SMP5	SMP5	SMP4		SMP3			SMP2			SMP1			SMP0
0x14	JOFR1													JOFFSET1
0x18	JOFR2													JOFFSET2
0x1c	JOFR3													JOFFSET3
0x20	JOFR4													JOFFSET4
0x24	HTR													HT
0x28	LTR													LT
0x2c	SQR1				L				SQ16		SQ16	SQ15				SQ14					SQ13
0x30	SQR2	SQ12		SQ11					SQ10		SQ10	SQ9				SQ8					SQ7
0x34	SQR3	SQ6		SQ5					SQ4		SQ4	SQ3				SQ2					SQ1
0x38	JSQR						JL		JSQ4		JSQ4	JSQ3				JSQ2					JSQ1
0x3c	JDR1										JDATA
0x40	JDR2										JDATA
0x44	JDR3										JDATA
0x48	JDR4										JDATA
0x4c	DR										DATA

Toggle registers

SR

status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											STRT rw	JSTRT rw	JEOC rw	EOC rw	AWD rw

Toggle fields

AWD

Bit 0: Analog watchdog flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

EOC

Bit 1: Regular channel end of conversion.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

JEOC

Bit 2: Injected channel end of conversion.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

JSTRT

Bit 3: Injected channel start flag.

Allowed values:
0: NotStarted: No injected group conversion started
1: Started: Injected group conversion has started

STRT

Bit 4: Regular channel start flag.

Allowed values:
0: NotStarted: No regular channel conversion started
1: Started: Regular channel conversion has started

CR1

control register 1

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								AWDEN rw	JAWDEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DISCNUM rw			JDISCEN rw	DISCEN rw	JAUTO rw	AWDSGL rw	SCAN rw	JEOCIE rw	AWDIE rw	EOCIE rw	AWDCH rw

Toggle fields

AWDCH

Bits 0-4: Analog watchdog channel select bits.

Allowed values: 0x0-0x11

EOCIE

Bit 5: Interrupt enable for EOC.

Allowed values:
0: Disabled: EOC interrupt disabled
1: Enabled: EOC interrupt enabled. An interrupt is generated when the EOC bit is set

AWDIE

Bit 6: Analog watchdog interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

JEOCIE

Bit 7: Interrupt enable for injected channels.

Allowed values:
0: Disabled: JEOC interrupt disabled
1: Enabled: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set

SCAN

Bit 8: Scan mode.

Allowed values:
0: Disabled: Scan mode disabled
1: Enabled: Scan mode enabled

AWDSGL

Bit 9: Enable the watchdog on a single channel in scan mode.

Allowed values:
0: All: Analog watchdog enabled on all channels
1: Single: Analog watchdog enabled on a single channel

JAUTO

Bit 10: Automatic injected group conversion.

Allowed values:
0: Disabled: Automatic injected group conversion disabled
1: Enabled: Automatic injected group conversion enabled

DISCEN

Bit 11: Discontinuous mode on regular channels.

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

JDISCEN

Bit 12: Discontinuous mode on injected channels.

Allowed values:
0: Disabled: Discontinuous mode on injected channels disabled
1: Enabled: Discontinuous mode on injected channels enabled

DISCNUM

Bits 13-15: Discontinuous mode channel count.

Allowed values: 0x0-0x7

JAWDEN

Bit 22: Analog watchdog enable on injected channels.

Allowed values:
0: Disabled: Analog watchdog disabled on injected channels
1: Enabled: Analog watchdog enabled on injected channels

AWDEN

Bit 23: Analog watchdog enable on regular channels.

Allowed values:
0: Disabled: Analog watchdog disabled on regular channels
1: Enabled: Analog watchdog enabled on regular channels

CR2

control register 2

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

13/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								TSVREFE rw	SWSTART rw	JSWSTART rw	EXTTRIG rw	EXTSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JEXTTRIG rw	JEXTSEL rw			ALIGN rw			DMA rw					RSTCAL rw	CAL rw	CONT rw	ADON rw

Toggle fields

ADON

Bit 0: A/D converter ON / OFF.

Allowed values:
0: Disabled: Disable ADC conversion/calibration and go to power down mode
1: Enabled: Enable ADC and to start conversion

CONT

Bit 1: Continuous conversion.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

CAL

Bit 2: A/D calibration.

Allowed values:
0: Complete: Calibration completed
1: NotComplete: Calibrating

RSTCAL

Bit 3: Reset calibration.

Allowed values:
0: Initialized: Calibration register initialized
1: NotInitialized: Initializing calibration register

DMA

Bit 8: Direct memory access mode.

Allowed values:
0: Disabled: DMA mode disabled
1: Enabled: DMA mode enabled

ALIGN

Bit 11: Data alignment.

Allowed values:
0: Right: Right Alignment
1: Left: Left Alignment

JEXTSEL

Bits 12-14: External event select for injected group.

Allowed values:
0: Tim1Trgo: Timer 1 TRGO event
1: Tim1Cc4: Timer 1 CC4 event
2: Tim2Trgo: Timer 2 TRGO event
3: Tim2Cc1: Timer 2 CC1 event
4: Tim3Cc4: Timer 3 CC4 event
5: Tim4Trgo: Timer 4 TRGO event
6: Exti15: EXTI line15/TIM8_CC4 event (TIM8_CC4 is available only in high-density and XL-density devices)
7: Jswstart: JSWSTART

JEXTTRIG

Bit 15: External trigger conversion mode for injected channels.

Allowed values:
0: Disabled: Conversion on external event disabled
1: Enabled: Conversion on external event enabled

EXTSEL

Bits 17-19: External event select for regular group.

Allowed values:
0: Tim1Cc1: Timer 1 CC1 event
1: Tim1Cc2: Timer 1 CC2 event
2: Tim1Cc3: Timer 1 CC3 event
3: Tim2Cc2: Timer 2 CC2 event
4: Tim3Trgo: Timer 3 TRGO event
5: Tim4Cc4: Timer 4 CC4 event
6: Exti11: EXTI line 11/TIM8_TRGO event (TIM8_TRGO is available only in high-density and XL-density devices)
7: Swstart: SWSTART

EXTTRIG

Bit 20: External trigger conversion mode for regular channels.

Allowed values:
0: Disabled: Conversion on external event disabled
1: Enabled: Conversion on external event enabled

JSWSTART

Bit 21: Start conversion of injected channels.

Allowed values:
0: Started: Reset state
1: NotStarted: Starting conversion of injected channels

SWSTART

Bit 22: Start conversion of regular channels.

Allowed values:
0: Started: Reset state
1: NotStarted: Starting conversion of regular channels

TSVREFE

Bit 23: Temperature sensor and VREFINT enable.

Allowed values:
0: Disabled: Temperature sensor and V_REFINT channel disabled
1: Enabled: Temperature sensor and V_REFINT channel enabled

SMPR1

sample time register 1

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								SMP17 rw			SMP16 rw			SMP15 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SMP15 rw	SMP14 rw			SMP13 rw			SMP12 rw			SMP11 rw			SMP10 rw

Toggle fields

SMP10

Bits 0-2: Channel 10 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP11

Bits 3-5: Channel 11 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP12

Bits 6-8: Channel 12 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP13

Bits 9-11: Channel 13 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP14

Bits 12-14: Channel 14 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP15

Bits 15-17: Channel 15 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP16

Bits 18-20: Channel 16 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP17

Bits 21-23: Channel 17 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMPR2

sample time register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		SMP9 rw			SMP8 rw			SMP7 rw			SMP6 rw			SMP5 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SMP5 rw	SMP4 rw			SMP3 rw			SMP2 rw			SMP1 rw			SMP0 rw

Toggle fields

SMP0

Bits 0-2: Channel 0 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP1

Bits 3-5: Channel 1 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP2

Bits 6-8: Channel 2 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP3

Bits 9-11: Channel 3 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP4

Bits 12-14: Channel 4 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP5

Bits 15-17: Channel 5 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP6

Bits 18-20: Channel 6 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP7

Bits 21-23: Channel 7 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP8

Bits 24-26: Channel 8 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP9

Bits 27-29: Channel 9 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

JOFR1

injected channel data offset register x

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				JOFFSET1 rw

Toggle fields

JOFFSET1

Bits 0-11: Data offset for injected channel 1.

JOFR2

injected channel data offset register x

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				JOFFSET2 rw

Toggle fields

JOFFSET2

Bits 0-11: Data offset for injected channel 2.

JOFR3

injected channel data offset register x

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				JOFFSET3 rw

Toggle fields

JOFFSET3

Bits 0-11: Data offset for injected channel 3.

JOFR4

injected channel data offset register x

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				JOFFSET4 rw

Toggle fields

JOFFSET4

Bits 0-11: Data offset for injected channel 4.

HTR

watchdog higher threshold register

Offset: 0x24, size: 32, reset: 0x00000FFF, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				HT rw

Toggle fields

HT

Bits 0-11: Analog watchdog higher threshold.

Allowed values: 0x0-0xfff

LTR

watchdog lower threshold register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				LT rw

Toggle fields

LT

Bits 0-11: Analog watchdog lower threshold.

Allowed values: 0x0-0xfff

SQR1

regular sequence register 1

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								L rw				SQ16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SQ16 rw	SQ15 rw					SQ14 rw					SQ13 rw

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		SQ12 rw					SQ11 rw					SQ10 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SQ10 rw	SQ9 rw					SQ8 rw					SQ7 rw

Allowed values: 0x0-0x11

SQR3

regular sequence register 3

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		SQ6 rw					SQ5 rw					SQ4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SQ4 rw	SQ3 rw					SQ2 rw					SQ1 rw

Allowed values: 0x0-0x11

JSQR

injected sequence register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										JL rw		JSQ4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JSQ4 rw	JSQ3 rw					JSQ2 rw					JSQ1 rw

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JDATA r

Toggle fields

JDATA

Bits 0-15: Injected data.

JDR2

injected data register x

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JDATA r

Toggle fields

JDATA

Bits 0-15: Injected data.

JDR3

injected data register x

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JDATA r

Toggle fields

JDATA

Bits 0-15: Injected data.

JDR4

injected data register x

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JDATA r

Toggle fields

JDATA

Bits 0-15: Injected data.

DR

regular data register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATA r

Toggle fields

DATA

Bits 0-15: Regular data.

AFIO

0x40010000: Alternate function I/O

0/42 fields covered.

Toggle register map

Offset	Name	26	16	15	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	EVCR										EVOE	PORT			PIN
0x4	MAPR	SWJ_CFG	TIM5CH4_IREMAP	PD01_REMAP		TIM4_REMAP	TIM3_REMAP		TIM2_REMAP		TIM1_REMAP		USART3_REMAP		USART2_REMAP	USART1_REMAP	I2C1_REMAP	SPI1_REMAP
0x8	EXTICR1			EXTI3			EXTI2				EXTI1				EXTI0
0xc	EXTICR2			EXTI7			EXTI6				EXTI5				EXTI4
0x10	EXTICR3			EXTI11			EXTI10				EXTI9				EXTI8
0x14	EXTICR4			EXTI15			EXTI14				EXTI13				EXTI12
0x1c	MAPR2				MISC_REMAP	TIM12_REMAP	TIM67_DAC_DMA_REMAP	FSMC_NADV	TIM14_REMAP	TIM13_REMAP				TIM1_DMA_REMAP	CEC_REMAP	TIM17_REMAP	TIM16_REMAP	TIM15_REMAP

Toggle registers

EVCR

Event Control Register (AFIO_EVCR)

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								EVOE rw	PORT rw			PIN rw

Toggle fields

PIN

Bits 0-3: Pin selection.

PORT

Bits 4-6: Port selection.

EVOE

Bit 7: Event Output Enable.

MAPR

AF remap and debug I/O configuration register (AFIO_MAPR)

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					SWJ_CFG w										TIM5CH4_IREMAP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PD01_REMAP rw			TIM4_REMAP rw	TIM3_REMAP rw		TIM2_REMAP rw		TIM1_REMAP rw		USART3_REMAP rw		USART2_REMAP rw	USART1_REMAP rw	I2C1_REMAP rw	SPI1_REMAP rw

Toggle fields

SPI1_REMAP

Bit 0: SPI1 remapping.

I2C1_REMAP

Bit 1: I2C1 remapping.

USART1_REMAP

Bit 2: USART1 remapping.

USART2_REMAP

Bit 3: USART2 remapping.

USART3_REMAP

Bits 4-5: USART3 remapping.

TIM1_REMAP

Bits 6-7: TIM1 remapping.

TIM2_REMAP

0/11 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		MISC_REMAP rw	TIM12_REMAP rw	TIM67_DAC_DMA_REMAP rw	FSMC_NADV rw	TIM14_REMAP rw	TIM13_REMAP rw				TIM1_DMA_REMAP rw	CEC_REMAP rw	TIM17_REMAP rw	TIM16_REMAP rw	TIM15_REMAP rw

Toggle fields

TIM15_REMAP

Bit 0: TIM15 remapping.

TIM16_REMAP

Bit 1: TIM16 remapping.

TIM17_REMAP

Bit 2: TIM17 remapping.

CEC_REMAP

Bit 3: CEC remapping.

TIM1_DMA_REMAP

Bit 4: TIM1 DMA remapping.

TIM13_REMAP

Bit 8: TIM13 remapping.

TIM14_REMAP

Bit 9: TIM14 remapping.

FSMC_NADV

Bit 10: NADV connect/disconnect.

TIM67_DAC_DMA_REMAP

Bit 11: TIM67_DAC DMA remapping.

TIM12_REMAP

Bit 12: TIM12 remapping.

MISC_REMAP

Bit 13: Miscellaneous features remapping.

BKP

0x40006c04: Backup registers

52/53 fields covered.

Toggle register map

Offset	Name	15	9	8	7	6	2	1	0
0x0	DR[1]	D
0x4	DR[2]	D
0x8	DR[3]	D
0xc	DR[4]	D
0x10	DR[5]	D
0x14	DR[6]	D
0x18	DR[7]	D
0x1c	DR[8]	D
0x20	DR[9]	D
0x24	DR[10]	D
0x28	RTCCR		ASOS	ASOE	CCO	CAL
0x2c	CR							TPAL	TPE
0x30	CSR		TIF	TEF			TPIE	CTI	CTE
0x3c	BKP_DR[11]	D
0x40	BKP_DR[12]	D
0x44	BKP_DR[13]	D
0x48	BKP_DR[14]	D
0x4c	BKP_DR[15]	D
0x50	BKP_DR[16]	D
0x54	BKP_DR[17]	D
0x58	BKP_DR[18]	D
0x5c	BKP_DR[19]	D
0x60	BKP_DR[20]	D
0x64	BKP_DR[21]	D
0x68	BKP_DR[22]	D
0x6c	BKP_DR[23]	D
0x70	BKP_DR[24]	D
0x74	BKP_DR[25]	D
0x78	BKP_DR[26]	D
0x7c	BKP_DR[27]	D
0x80	BKP_DR[28]	D
0x84	BKP_DR[29]	D
0x88	BKP_DR[30]	D
0x8c	BKP_DR[31]	D
0x90	BKP_DR[32]	D
0x94	BKP_DR[33]	D
0x98	BKP_DR[34]	D
0x9c	BKP_DR[35]	D
0xa0	BKP_DR[36]	D
0xa4	BKP_DR[37]	D
0xa8	BKP_DR[38]	D
0xac	BKP_DR[39]	D
0xb0	BKP_DR[40]	D
0xb4	BKP_DR[41]	D
0xb8	BKP_DR[42]	D

Toggle registers

DR[1]

Backup data register (BKP_DR)

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

DR[2]

Backup data register (BKP_DR)

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

DR[3]

Backup data register (BKP_DR)

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

DR[4]

Backup data register (BKP_DR)

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

DR[5]

Backup data register (BKP_DR)

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

DR[6]

Backup data register (BKP_DR)

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

DR[7]

Backup data register (BKP_DR)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

DR[8]

Backup data register (BKP_DR)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

DR[9]

Backup data register (BKP_DR)

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

DR[10]

Backup data register (BKP_DR)

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

RTCCR

RTC clock calibration register (BKP_RTCCR)

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

3/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						ASOS rw	ASOE rw	CCO rw	CAL rw

Toggle fields

CAL

Bits 0-6: Calibration value.

Allowed values: 0x0-0x79

CCO

Bit 7: Calibration Clock Output.

ASOE

Bit 8: Alarm or second output enable.

Allowed values:
0: Disabled: Disabled
1: Enabled: Setting this bit outputs either the RTC Alarm pulse signal or the Second pulse signal on the TAMPER pin depending on the ASOS bit

ASOS

Bit 9: Alarm or second output selection.

Allowed values:
0: Alarm: RTC Alarm pulse output selected
1: Second: RTC Second pulse output selected

CR

Backup control register (BKP_CR)

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														TPAL rw	TPE rw

Toggle fields

TPE

Bit 0: Tamper pin enable.

Allowed values:
0: General: The TAMPER pin is free for general purpose I/O
1: Alternate: Tamper alternate I/O function is activated

TPAL

Bit 1: Tamper pin active level.

Allowed values:
0: High: A high level on the TAMPER pin resets all data backup registers (if TPE bit is set)
1: Low: A low level on the TAMPER pin resets all data backup registers (if TPE bit is set)

CSR

BKP_CSR control/status register (BKP_CSR)

Offset: 0x30, size: 32, reset: 0x00000000, access: Unspecified

5/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						TIF r	TEF r						TPIE rw	CTI w	CTE w

Toggle fields

CTE

Bit 0: Clear Tamper event.

Allowed values:
1: Reset: Reset the TEF Tamper event flag (and the Tamper detector)

CTI

Bit 1: Clear Tamper Interrupt.

Allowed values:
1: Clear: Clear the Tamper interrupt and the TIF Tamper interrupt flag

TPIE

Bit 2: Tamper Pin interrupt enable.

Allowed values:
0: Disabled: Tamper interrupt disabled
1: Enabled: Tamper interrupt enabled (the TPE bit must also be set in the BKP_CR register

TEF

Bit 8: Tamper Event Flag.

TIF

Bit 9: Tamper Interrupt Flag.

BKP_DR[11]

Backup data register (BKP_DR)

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[12]

Backup data register (BKP_DR)

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[13]

Backup data register (BKP_DR)

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[14]

Backup data register (BKP_DR)

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[15]

Backup data register (BKP_DR)

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[16]

Backup data register (BKP_DR)

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[17]

Backup data register (BKP_DR)

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[18]

Backup data register (BKP_DR)

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[19]

Backup data register (BKP_DR)

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[20]

Backup data register (BKP_DR)

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[21]

Backup data register (BKP_DR)

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[22]

Backup data register (BKP_DR)

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[23]

Backup data register (BKP_DR)

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[24]

Backup data register (BKP_DR)

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[25]

Backup data register (BKP_DR)

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[26]

Backup data register (BKP_DR)

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[27]

Backup data register (BKP_DR)

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[28]

Backup data register (BKP_DR)

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[29]

Backup data register (BKP_DR)

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[30]

Backup data register (BKP_DR)

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[31]

Backup data register (BKP_DR)

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[32]

Backup data register (BKP_DR)

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[33]

Backup data register (BKP_DR)

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[34]

Backup data register (BKP_DR)

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[35]

Backup data register (BKP_DR)

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[36]

Backup data register (BKP_DR)

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[37]

Backup data register (BKP_DR)

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[38]

Backup data register (BKP_DR)

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[39]

Backup data register (BKP_DR)

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[40]

Backup data register (BKP_DR)

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[41]

Backup data register (BKP_DR)

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[42]

Backup data register (BKP_DR)

Offset: 0xb8, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D rw

Toggle fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

CEC

0x40007800: HDMI-CEC controller

8/23 fields covered.

Toggle register map

Offset	Name	13	7	6	5	4	3	2	1	0
0x0	CFGR						BPEM	BTEM	IE	PE
0x4	OAR						OA
0x8	PRES	PRESC
0xc	ESR			TBTFE	LINE	ACKE	SBE	RBTFE	BPE	BTE
0x10	CSR		RBTF	RERR	REOM	RSOM	TBTRF	TERR	TEOM	TSOM
0x14	TXD		TXD
0x18	RXD		RXD

Toggle registers

CFGR

configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												BPEM rw	BTEM rw	IE rw	PE rw

Toggle fields

PE

Bit 0: Peripheral enable.

IE

Bit 1: Interrupt enable.

BTEM

Bit 2: Bit timing error mode.

BPEM

Bit 3: Bit period error mode.

OAR

CEC own address register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												OA rw

Toggle fields

OA

Bits 0-3: Own address.

PRES

Rx Data Register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		PRESC rw

Toggle fields

PRESC

Bits 0-13: CEC Rx Data Register.

ESR

CEC error status register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									TBTFE r	LINE r	ACKE r	SBE r	RBTFE r	BPE r	BTE r

Toggle fields

BTE

Bit 0: Bit timing error.

BPE

Bit 1: Bit period error.

RBTFE

Bit 2: Rx block transfer finished error.

SBE

Bit 3: Start bit error.

ACKE

Bit 4: Block acknowledge error.

LINE

Bit 5: Line error.

TBTFE

Bit 6: Tx block transfer finished error.

CSR

CEC control and status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RBTF rw	RERR rw	REOM rw	RSOM rw	TBTRF rw	TERR rw	TEOM rw	TSOM rw

Toggle fields

TSOM

Bit 0: Tx start of message.

TEOM

Bit 1: Tx end of message.

TERR

Bit 2: Tx error.

TBTRF

Bit 3: Tx byte transfer request or block transfer finished.

RSOM

Bit 4: Rx start of message.

REOM

Bit 5: Rx end of message.

RERR

Bit 6: Rx error.

RBTF

Bit 7: Rx byte/block transfer finished.

TXD

CEC Tx data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TXD rw

Toggle fields

TXD

Bits 0-7: Tx Data register.

RXD

CEC Rx data register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RXD r

Toggle fields

RXD

Bits 0-7: Rx data.

CRC

0x40023000: CRC calculation unit

3/3 fields covered.

Toggle register map

Offset	Name	31	15	7	0
0x0	DR	DR	DR
0x4	IDR			IDR
0x8	CR				RESET

Toggle registers

DR

Data register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR rw

Toggle fields

DR

Bits 0-31: Data Register.

Allowed values: 0x0-0xffffffff

IDR

Independent Data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IDR rw

Toggle fields

IDR

Bits 0-7: Independent Data register.

Allowed values: 0x0-0xff

CR

Control register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															RESET w

Toggle fields

RESET

Bit 0: Reset bit.

Allowed values:
1: Reset: Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF

DAC

0x40007400: Digital to analog converter

34/34 fields covered.

Toggle register map

Offset	Name	31	29	28	27	23	21	18	17	16	15	13	12	11	7	5	2	1	0
0x0	CR		DMAUDRIE2	DMAEN2	MAMP2	WAVE2	TSEL2	TEN2	BOFF2	EN2		DMAUDRIE1	DMAEN1	MAMP1	WAVE1	TSEL1	TEN1	BOFF1	EN1
0x4	SWTRIGR																	SWTRIG2	SWTRIG1
0x8	DHR12R1													DACC1DHR
0xc	DHR12L1										DACC1DHR
0x10	DHR8R1														DACC1DHR
0x14	DHR12R2													DACC2DHR
0x18	DHR12L2										DACC2DHR
0x1c	DHR8R2														DACC2DHR
0x20	DHR12RD				DACC2DHR									DACC1DHR
0x24	DHR12LD	DACC2DHR									DACC1DHR
0x28	DHR8RD										DACC2DHR				DACC1DHR
0x2c	DOR1													DACC1DOR
0x30	DOR2													DACC2DOR
0x34	SR		DMAUDR2									DMAUDR1

Toggle registers

CR

Control register (DAC_CR)

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		DMAUDRIE2 rw	DMAEN2 rw	MAMP2 rw				WAVE2 rw		TSEL2 rw			TEN2 rw	BOFF2 rw	EN2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		DMAUDRIE1 rw	DMAEN1 rw	MAMP1 rw				WAVE1 rw		TSEL1 rw			TEN1 rw	BOFF1 rw	EN1 rw

Toggle fields

EN1

Bit 0: DAC channel1 enable.

Allowed values:
0: Disabled: DAC channel X disabled
1: Enabled: DAC channel X enabled

BOFF1

Bit 1: DAC channel1 output buffer disable.

Allowed values:
0: Enabled: DAC channel X output buffer enabled
1: Disabled: DAC channel X output buffer disabled

TEN1

Bit 2: DAC channel1 trigger enable.

Allowed values:
0: Disabled: DAC channel X trigger disabled
1: Enabled: DAC channel X trigger enabled

TSEL1

Bits 3-5: DAC channel1 trigger selection.

Allowed values:
0: TIM6_TRGO: Timer 6 TRGO event
1: TIM3_TRGO: Timer 3 TRGO event
2: TIM7_TRGO: Timer 7 TRGO event
3: TIM15_TRGO: Timer 15 TRGO event
4: TIM2_TRGO: Timer 2 TRGO event
6: EXTI9: EXTI line9
7: SOFTWARE: Software trigger

WAVE1

Bits 6-7: DAC channel1 noise/triangle wave generation enable.

Allowed values:
0: Disabled: Wave generation disabled
1: Noise: Noise wave generation enabled
2: Triangle: Triangle wave generation enabled

MAMP1

Bits 8-11: DAC channel1 mask/amplitude selector.

Allowed values: 0x0-0xf

DMAEN1

Bit 12: DAC channel1 DMA enable.

Allowed values:
0: Disabled: DAC channel X DMA mode disabled
1: Enabled: DAC channel X DMA mode enabled

DMAUDRIE1

Bit 13: DAC channel1 DMA underrun interrupt enable.

Allowed values:
0: Disabled: DAC channel X DMA Underrun Interrupt disabled
1: Enabled: DAC channel X DMA Underrun Interrupt enabled

EN2

Bit 16: DAC channel2 enable.

Allowed values:
0: Disabled: DAC channel X disabled
1: Enabled: DAC channel X enabled

BOFF2

Bit 17: DAC channel2 output buffer disable.

Allowed values:
0: Enabled: DAC channel X output buffer enabled
1: Disabled: DAC channel X output buffer disabled

TEN2

Bit 18: DAC channel2 trigger enable.

Allowed values:
0: Disabled: DAC channel X trigger disabled
1: Enabled: DAC channel X trigger enabled

TSEL2

Bits 19-21: DAC channel2 trigger selection.

Allowed values:
0: TIM6_TRGO: Timer 6 TRGO event
1: TIM8_TRGO: Timer 8 TRGO event
2: TIM7_TRGO: Timer 7 TRGO event
3: TIM5_TRGO: Timer 5 TRGO event
4: TIM2_TRGO: Timer 2 TRGO event
5: TIM4_TRGO: Timer 4 TRGO event
6: EXTI9: EXTI line9
7: SOFTWARE: Software trigger

WAVE2

Bits 22-23: DAC channel2 noise/triangle wave generation enable.

Allowed values:
0: Disabled: Wave generation disabled
1: Noise: Noise wave generation enabled
2: Triangle: Triangle wave generation enabled

MAMP2

Bits 24-27: DAC channel2 mask/amplitude selector.

Allowed values: 0x0-0xf

DMAEN2

Bit 28: DAC channel2 DMA enable.

Allowed values:
0: Disabled: DAC channel X DMA mode disabled
1: Enabled: DAC channel X DMA mode enabled

DMAUDRIE2

Bit 29: DAC channel2 DMA underrun interrupt enable.

Allowed values:
0: Disabled: DAC channel X DMA Underrun Interrupt disabled
1: Enabled: DAC channel X DMA Underrun Interrupt enabled

SWTRIGR

DAC software trigger register (DAC_SWTRIGR)

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														SWTRIG2 w	SWTRIG1 w

Toggle fields

SWTRIG1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				DACC2DHR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				DACC1DHR rw

Toggle fields

DACC1DHR

Bits 0-11: DAC channel1 12-bit right-aligned data.

Allowed values: 0x0-0xfff

DACC2DHR

Bits 16-27: DAC channel2 12-bit right-aligned data.

Allowed values: 0x0-0xfff

DHR12LD

DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DACC2DHR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DACC1DHR rw

Toggle fields

DACC1DHR

Bits 4-15: DAC channel1 12-bit left-aligned data.

Allowed values: 0x0-0xfff

DACC2DHR

Bits 20-31: DAC channel2 12-bit right-aligned data.

Allowed values: 0x0-0xfff

DHR8RD

DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DACC2DHR rw								DACC1DHR rw

Toggle fields

DACC1DHR

Bits 0-7: DAC channel1 8-bit right-aligned data.

Allowed values: 0x0-0xff

DACC2DHR

Bits 8-15: DAC channel2 8-bit right-aligned data.

Allowed values: 0x0-0xff

DOR1

DAC channel1 data output register (DAC_DOR1)

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				DACC1DOR r

Toggle fields

DACC1DOR

Bits 0-11: DAC channel1 data output.

DOR2

DAC channel2 data output register (DAC_DOR2)

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				DACC2DOR r

Toggle fields

DACC2DOR

Bits 0-11: DAC channel2 data output.

SR

DAC status register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		DMAUDR2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		DMAUDR1 rw

Toggle fields

DMAUDR1

Bit 13: DAC channel1 DMA underrun flag.

Allowed values:
0: NoUnderrun: No DMA underrun error condition occurred for DAC channel X
1: Underrun: DMA underrun error condition occurred for DAC channel X

DMAUDR2

Bit 29: DAC channel2 DMA underrun flag.

Allowed values:
0: NoUnderrun: No DMA underrun error condition occurred for DAC channel X
1: Underrun: DMA underrun error condition occurred for DAC channel X

DBGMCU

0xe0042000: Debug support

2/24 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	IDCODE	REV_ID																				DEV_ID
0x4	CR					DBG_TIM14_STOP	DBG_TIM13_STOP	DBG_TIM12_STOP	DBG_TIM17_STOP	DBG_TIM16_STOP	DBG_TIM15_STOP		DBG_TIM7_STOP	DBG_TIM6_STOP	DBG_TIM5_STOP		DBG_I2C2_SMBUS_TIMEOUT	DBG_I2C1_SMBUS_TIMEOUT		DBG_TIM4_STOP	DBG_TIM3_STOP	DBG_TIM2_STOP	DBG_TIM1_STOP	DBG_WWDG_STOP	DBG_IWDG_STOP	TRACE_MODE		TRACE_IOEN			DBG_STANDBY	DBG_STOP	DBG_SLEEP

Toggle registers

IDCODE

DBGMCU_IDCODE

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
REV_ID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				DEV_ID r

Toggle fields

DEV_ID

Bits 0-11: DEV_ID.

REV_ID

Bits 16-31: REV_ID.

CR

DBGMCU_CR

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/22 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				DBG_TIM14_STOP rw	DBG_TIM13_STOP rw	DBG_TIM12_STOP rw	DBG_TIM17_STOP rw	DBG_TIM16_STOP rw	DBG_TIM15_STOP rw		DBG_TIM7_STOP rw	DBG_TIM6_STOP rw	DBG_TIM5_STOP rw		DBG_I2C2_SMBUS_TIMEOUT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DBG_I2C1_SMBUS_TIMEOUT rw		DBG_TIM4_STOP rw	DBG_TIM3_STOP rw	DBG_TIM2_STOP rw	DBG_TIM1_STOP rw	DBG_WWDG_STOP rw	DBG_IWDG_STOP rw	TRACE_MODE rw		TRACE_IOEN rw			DBG_STANDBY rw	DBG_STOP rw	DBG_SLEEP rw

Toggle fields

DBG_SLEEP

Bit 0: DBG_SLEEP.

DBG_STOP

Bit 1: DBG_STOP.

DBG_STANDBY

Bit 2: DBG_STANDBY.

TRACE_IOEN

Bit 5: TRACE_IOEN.

TRACE_MODE

Bits 6-7: TRACE_MODE.

DBG_IWDG_STOP

Bit 8: DBG_IWDG_STOP.

DBG_WWDG_STOP

Bit 9: DBG_WWDG_STOP.

DBG_TIM1_STOP

Bit 10: DBG_TIM1_STOP.

DBG_TIM2_STOP

Bit 11: DBG_TIM2_STOP.

DBG_TIM3_STOP

Bit 12: DBG_TIM3_STOP.

DBG_TIM4_STOP

Bit 13: DBG_TIM4_STOP.

DBG_I2C1_SMBUS_TIMEOUT

Bit 15: DBG_I2C1_SMBUS_TIMEOUT.

DBG_I2C2_SMBUS_TIMEOUT

Bit 16: DBG_I2C2_SMBUS_TIMEOUT.

DBG_TIM5_STOP

Bit 18: DBG_TIM5_STOP.

DBG_TIM6_STOP

Bit 19: DBG_TIM6_STOP.

DBG_TIM7_STOP

Bit 20: DBG_TIM7_STOP.

DBG_TIM15_STOP

Bit 22: DBG_TIM15_STOP.

DBG_TIM16_STOP

Bit 23: DBG_TIM16_STOP.

DBG_TIM17_STOP

Bit 24: DBG_TIM17_STOP.

DBG_TIM12_STOP

Bit 25: DBG_TIM12_STOP.

DBG_TIM13_STOP

Bit 26: DBG_TIM13_STOP.

DBG_TIM14_STOP

Bit 27: DBG_TIM14_STOP.

DMA1

0x40020000: DMA controller

147/161 fields covered.

Toggle register map

Offset	Name	31	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	ISR		TEIF[7]	HTIF[7]	TCIF[7]	GIF[7]	TEIF[6]	HTIF[6]	TCIF[6]	GIF[6]	TEIF[5]	HTIF[5]	TCIF[5]	GIF[5]	TEIF[4]	HTIF[4]	TCIF[4]	GIF[4]	TEIF[3]	HTIF[3]	TCIF[3]	GIF[3]	TEIF[2]	HTIF[2]	TCIF[2]	GIF[2]	TEIF[1]	HTIF[1]	TCIF[1]	GIF[1]
0x4	IFCR		CTEIF[7]	CHTIF[7]	CTCIF[7]	CGIF[7]	CTEIF[6]	CHTIF[6]	CTCIF[6]	CGIF[6]	CTEIF[5]	CHTIF[5]	CTCIF[5]	CGIF[5]	CTEIF[4]	CHTIF[4]	CTCIF[4]	CGIF[4]	CTEIF[3]	CHTIF[3]	CTCIF[3]	CGIF[3]	CTEIF[2]	CHTIF[2]	CTCIF[2]	CGIF[2]	CTEIF[1]	CHTIF[1]	CTCIF[1]	CGIF[1]
0x8	CR [1]															MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0xc	NDTR [1]														NDT
0x10	PAR [1]	PA													PA
0x14	MAR [1]	MA													MA
0x1c	CR [2]															MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x20	NDTR [2]														NDT
0x24	PAR [2]	PA													PA
0x28	MAR [2]	MA													MA
0x30	CR [3]															MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x34	NDTR [3]														NDT
0x38	PAR [3]	PA													PA
0x3c	MAR [3]	MA													MA
0x44	CR [4]															MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x48	NDTR [4]														NDT
0x4c	PAR [4]	PA													PA
0x50	MAR [4]	MA													MA
0x58	CR [5]															MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x5c	NDTR [5]														NDT
0x60	PAR [5]	PA													PA
0x64	MAR [5]	MA													MA
0x6c	CR [6]															MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x70	NDTR [6]														NDT
0x74	PAR [6]	PA													PA
0x78	MAR [6]	MA													MA
0x80	CR [7]															MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x84	NDTR [7]														NDT
0x88	PAR [7]	PA													PA
0x8c	MAR [7]	MA													MA

Toggle registers

ISR

DMA interrupt status register (DMA_ISR)

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

28/28 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TEIF[7] r	HTIF[7] r	TCIF[7] r	GIF[7] r	TEIF[6] r	HTIF[6] r	TCIF[6] r	GIF[6] r	TEIF[5] r	HTIF[5] r	TCIF[5] r	GIF[5] r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TEIF[4] r	HTIF[4] r	TCIF[4] r	GIF[4] r	TEIF[3] r	HTIF[3] r	TCIF[3] r	GIF[3] r	TEIF[2] r	HTIF[2] r	TCIF[2] r	GIF[2] r	TEIF[1] r	HTIF[1] r	TCIF[1] r	GIF[1] r

Toggle fields

GIF[1]

Bit 0: Channel 1 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[1]

Bit 1: Channel 1 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[1]

Bit 2: Channel 1 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[1]

Bit 3: Channel 1 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[2]

Bit 4: Channel 2 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[2]

Bit 5: Channel 2 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[2]

Bit 6: Channel 2 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[2]

Bit 7: Channel 2 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[3]

Bit 8: Channel 3 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[3]

Bit 9: Channel 3 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[3]

Bit 10: Channel 3 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[3]

Bit 11: Channel 3 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[4]

Bit 12: Channel 4 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[4]

Bit 13: Channel 4 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[4]

Bit 14: Channel 4 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[4]

Bit 15: Channel 4 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[5]

Bit 16: Channel 5 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[5]

Bit 17: Channel 5 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[5]

Bit 18: Channel 5 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[5]

Bit 19: Channel 5 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[6]

Bit 20: Channel 6 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[6]

Bit 21: Channel 6 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[6]

Bit 22: Channel 6 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[6]

Bit 23: Channel 6 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[7]

Bit 24: Channel 7 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[7]

Bit 25: Channel 7 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[7]

Bit 26: Channel 7 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[7]

Bit 27: Channel 7 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

IFCR

DMA interrupt flag clear register (DMA_IFCR)

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

28/28 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				CTEIF[7] w	CHTIF[7] w	CTCIF[7] w	CGIF[7] w	CTEIF[6] w	CHTIF[6] w	CTCIF[6] w	CGIF[6] w	CTEIF[5] w	CHTIF[5] w	CTCIF[5] w	CGIF[5] w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CTEIF[4] w	CHTIF[4] w	CTCIF[4] w	CGIF[4] w	CTEIF[3] w	CHTIF[3] w	CTCIF[3] w	CGIF[3] w	CTEIF[2] w	CHTIF[2] w	CTCIF[2] w	CGIF[2] w	CTEIF[1] w	CHTIF[1] w	CTCIF[1] w	CGIF[1] w

Toggle fields

CGIF[1]

Bit 0: Channel 1 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[1]

Bit 1: Channel 1 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[1]

Bit 2: Channel 1 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[1]

Bit 3: Channel 1 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[2]

Bit 4: Channel 2 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[2]

Bit 5: Channel 2 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[2]

Bit 6: Channel 2 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[2]

Bit 7: Channel 2 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[3]

Bit 8: Channel 3 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[3]

Bit 9: Channel 3 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[3]

Bit 10: Channel 3 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[3]

Bit 11: Channel 3 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[4]

Bit 12: Channel 4 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[4]

Bit 13: Channel 4 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[4]

Bit 14: Channel 4 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[4]

Bit 15: Channel 4 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[5]

Bit 16: Channel 5 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[5]

Bit 17: Channel 5 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[5]

Bit 18: Channel 5 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[5]

Bit 19: Channel 5 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[6]

Bit 20: Channel 6 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[6]

Bit 21: Channel 6 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[6]

Bit 22: Channel 6 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[6]

Bit 23: Channel 6 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[7]

Bit 24: Channel 7 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[7]

Bit 25: Channel 7 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[7]

Bit 26: Channel 7 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[7]

Bit 27: Channel 7 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CR [1]

DMA channel configuration register (DMA_CCR)

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half Transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [1]

DMA channel 1 number of data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [1]

DMA channel 1 peripheral address register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

MAR [1]

DMA channel 1 memory address register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: Memory address.

CR [2]

DMA channel configuration register (DMA_CCR)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half Transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [2]

DMA channel 1 number of data register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [2]

DMA channel 1 peripheral address register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

MAR [2]

DMA channel 1 memory address register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: Memory address.

CR [3]

DMA channel configuration register (DMA_CCR)

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half Transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [3]

DMA channel 1 number of data register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [3]

DMA channel 1 peripheral address register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

MAR [3]

DMA channel 1 memory address register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: Memory address.

CR [4]

DMA channel configuration register (DMA_CCR)

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half Transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [4]

DMA channel 1 number of data register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [4]

DMA channel 1 peripheral address register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

MAR [4]

DMA channel 1 memory address register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: Memory address.

CR [5]

DMA channel configuration register (DMA_CCR)

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half Transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [5]

DMA channel 1 number of data register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [5]

DMA channel 1 peripheral address register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

MAR [5]

DMA channel 1 memory address register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: Memory address.

CR [6]

DMA channel configuration register (DMA_CCR)

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half Transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [6]

DMA channel 1 number of data register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [6]

DMA channel 1 peripheral address register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

MAR [6]

DMA channel 1 memory address register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: Memory address.

CR [7]

DMA channel configuration register (DMA_CCR)

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half Transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [7]

DMA channel 1 number of data register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [7]

DMA channel 1 peripheral address register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

MAR [7]

DMA channel 1 memory address register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: Memory address.

DMA2

0x40020400: DMA controller

147/161 fields covered.

Toggle register map

Offset	Name	31	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	ISR		TEIF[7]	HTIF[7]	TCIF[7]	GIF[7]	TEIF[6]	HTIF[6]	TCIF[6]	GIF[6]	TEIF[5]	HTIF[5]	TCIF[5]	GIF[5]	TEIF[4]	HTIF[4]	TCIF[4]	GIF[4]	TEIF[3]	HTIF[3]	TCIF[3]	GIF[3]	TEIF[2]	HTIF[2]	TCIF[2]	GIF[2]	TEIF[1]	HTIF[1]	TCIF[1]	GIF[1]
0x4	IFCR		CTEIF[7]	CHTIF[7]	CTCIF[7]	CGIF[7]	CTEIF[6]	CHTIF[6]	CTCIF[6]	CGIF[6]	CTEIF[5]	CHTIF[5]	CTCIF[5]	CGIF[5]	CTEIF[4]	CHTIF[4]	CTCIF[4]	CGIF[4]	CTEIF[3]	CHTIF[3]	CTCIF[3]	CGIF[3]	CTEIF[2]	CHTIF[2]	CTCIF[2]	CGIF[2]	CTEIF[1]	CHTIF[1]	CTCIF[1]	CGIF[1]
0x8	CR [1]															MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0xc	NDTR [1]														NDT
0x10	PAR [1]	PA													PA
0x14	MAR [1]	MA													MA
0x1c	CR [2]															MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x20	NDTR [2]														NDT
0x24	PAR [2]	PA													PA
0x28	MAR [2]	MA													MA
0x30	CR [3]															MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x34	NDTR [3]														NDT
0x38	PAR [3]	PA													PA
0x3c	MAR [3]	MA													MA
0x44	CR [4]															MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x48	NDTR [4]														NDT
0x4c	PAR [4]	PA													PA
0x50	MAR [4]	MA													MA
0x58	CR [5]															MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x5c	NDTR [5]														NDT
0x60	PAR [5]	PA													PA
0x64	MAR [5]	MA													MA
0x6c	CR [6]															MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x70	NDTR [6]														NDT
0x74	PAR [6]	PA													PA
0x78	MAR [6]	MA													MA
0x80	CR [7]															MEM2MEM	PL		MSIZE		PSIZE		MINC	PINC	CIRC	DIR	TEIE	HTIE	TCIE	EN
0x84	NDTR [7]														NDT
0x88	PAR [7]	PA													PA
0x8c	MAR [7]	MA													MA

Toggle registers

ISR

DMA interrupt status register (DMA_ISR)

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

28/28 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TEIF[7] r	HTIF[7] r	TCIF[7] r	GIF[7] r	TEIF[6] r	HTIF[6] r	TCIF[6] r	GIF[6] r	TEIF[5] r	HTIF[5] r	TCIF[5] r	GIF[5] r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TEIF[4] r	HTIF[4] r	TCIF[4] r	GIF[4] r	TEIF[3] r	HTIF[3] r	TCIF[3] r	GIF[3] r	TEIF[2] r	HTIF[2] r	TCIF[2] r	GIF[2] r	TEIF[1] r	HTIF[1] r	TCIF[1] r	GIF[1] r

Toggle fields

GIF[1]

Bit 0: Channel 1 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[1]

Bit 1: Channel 1 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[1]

Bit 2: Channel 1 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[1]

Bit 3: Channel 1 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[2]

Bit 4: Channel 2 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[2]

Bit 5: Channel 2 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[2]

Bit 6: Channel 2 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[2]

Bit 7: Channel 2 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[3]

Bit 8: Channel 3 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[3]

Bit 9: Channel 3 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[3]

Bit 10: Channel 3 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[3]

Bit 11: Channel 3 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[4]

Bit 12: Channel 4 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[4]

Bit 13: Channel 4 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[4]

Bit 14: Channel 4 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[4]

Bit 15: Channel 4 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[5]

Bit 16: Channel 5 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[5]

Bit 17: Channel 5 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[5]

Bit 18: Channel 5 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[5]

Bit 19: Channel 5 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[6]

Bit 20: Channel 6 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[6]

Bit 21: Channel 6 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[6]

Bit 22: Channel 6 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[6]

Bit 23: Channel 6 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[7]

Bit 24: Channel 7 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[7]

Bit 25: Channel 7 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[7]

Bit 26: Channel 7 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[7]

Bit 27: Channel 7 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

IFCR

DMA interrupt flag clear register (DMA_IFCR)

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

28/28 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				CTEIF[7] w	CHTIF[7] w	CTCIF[7] w	CGIF[7] w	CTEIF[6] w	CHTIF[6] w	CTCIF[6] w	CGIF[6] w	CTEIF[5] w	CHTIF[5] w	CTCIF[5] w	CGIF[5] w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CTEIF[4] w	CHTIF[4] w	CTCIF[4] w	CGIF[4] w	CTEIF[3] w	CHTIF[3] w	CTCIF[3] w	CGIF[3] w	CTEIF[2] w	CHTIF[2] w	CTCIF[2] w	CGIF[2] w	CTEIF[1] w	CHTIF[1] w	CTCIF[1] w	CGIF[1] w

Toggle fields

CGIF[1]

Bit 0: Channel 1 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[1]

Bit 1: Channel 1 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[1]

Bit 2: Channel 1 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[1]

Bit 3: Channel 1 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[2]

Bit 4: Channel 2 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[2]

Bit 5: Channel 2 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[2]

Bit 6: Channel 2 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[2]

Bit 7: Channel 2 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[3]

Bit 8: Channel 3 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[3]

Bit 9: Channel 3 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[3]

Bit 10: Channel 3 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[3]

Bit 11: Channel 3 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[4]

Bit 12: Channel 4 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[4]

Bit 13: Channel 4 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[4]

Bit 14: Channel 4 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[4]

Bit 15: Channel 4 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[5]

Bit 16: Channel 5 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[5]

Bit 17: Channel 5 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[5]

Bit 18: Channel 5 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[5]

Bit 19: Channel 5 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[6]

Bit 20: Channel 6 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[6]

Bit 21: Channel 6 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[6]

Bit 22: Channel 6 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[6]

Bit 23: Channel 6 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[7]

Bit 24: Channel 7 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[7]

Bit 25: Channel 7 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[7]

Bit 26: Channel 7 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[7]

Bit 27: Channel 7 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CR [1]

DMA channel configuration register (DMA_CCR)

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half Transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [1]

DMA channel 1 number of data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [1]

DMA channel 1 peripheral address register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

MAR [1]

DMA channel 1 memory address register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: Memory address.

CR [2]

DMA channel configuration register (DMA_CCR)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half Transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [2]

DMA channel 1 number of data register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [2]

DMA channel 1 peripheral address register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

MAR [2]

DMA channel 1 memory address register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: Memory address.

CR [3]

DMA channel configuration register (DMA_CCR)

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half Transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [3]

DMA channel 1 number of data register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [3]

DMA channel 1 peripheral address register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

MAR [3]

DMA channel 1 memory address register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: Memory address.

CR [4]

DMA channel configuration register (DMA_CCR)

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half Transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [4]

DMA channel 1 number of data register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [4]

DMA channel 1 peripheral address register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

MAR [4]

DMA channel 1 memory address register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: Memory address.

CR [5]

DMA channel configuration register (DMA_CCR)

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half Transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [5]

DMA channel 1 number of data register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [5]

DMA channel 1 peripheral address register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

MAR [5]

DMA channel 1 memory address register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: Memory address.

CR [6]

DMA channel configuration register (DMA_CCR)

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half Transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [6]

DMA channel 1 number of data register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [6]

DMA channel 1 peripheral address register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

MAR [6]

DMA channel 1 memory address register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: Memory address.

CR [7]

DMA channel configuration register (DMA_CCR)

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half Transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [7]

DMA channel 1 number of data register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [7]

DMA channel 1 peripheral address register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

MAR [7]

DMA channel 1 memory address register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle fields

MA

Bits 0-31: Memory address.

EXTI

0x40010400: EXTI

108/108 fields covered.

Toggle register map

Offset	Name	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	IMR	MR17	MR16	MR15	MR14	MR13	MR12	MR11	MR10	MR9	MR8	MR7	MR6	MR5	MR4	MR3	MR2	MR1	MR0
0x4	EMR	MR17	MR16	MR15	MR14	MR13	MR12	MR11	MR10	MR9	MR8	MR7	MR6	MR5	MR4	MR3	MR2	MR1	MR0
0x8	RTSR	TR17	TR16	TR15	TR14	TR13	TR12	TR11	TR10	TR9	TR8	TR7	TR6	TR5	TR4	TR3	TR2	TR1	TR0
0xc	FTSR	TR17	TR16	TR15	TR14	TR13	TR12	TR11	TR10	TR9	TR8	TR7	TR6	TR5	TR4	TR3	TR2	TR1	TR0
0x10	SWIER	SWIER17	SWIER16	SWIER15	SWIER14	SWIER13	SWIER12	SWIER11	SWIER10	SWIER9	SWIER8	SWIER7	SWIER6	SWIER5	SWIER4	SWIER3	SWIER2	SWIER1	SWIER0
0x14	PR	PR17	PR16	PR15	PR14	PR13	PR12	PR11	PR10	PR9	PR8	PR7	PR6	PR5	PR4	PR3	PR2	PR1	PR0

Toggle registers

IMR

Interrupt mask register (EXTI_IMR)

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

18/18 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														MR17 rw	MR16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MR15 rw	MR14 rw	MR13 rw	MR12 rw	MR11 rw	MR10 rw	MR9 rw	MR8 rw	MR7 rw	MR6 rw	MR5 rw	MR4 rw	MR3 rw	MR2 rw	MR1 rw	MR0 rw

Toggle fields

MR0

Bit 0: Interrupt Mask on line 0.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR1

Bit 1: Interrupt Mask on line 1.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR2

Bit 2: Interrupt Mask on line 2.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR3

Bit 3: Interrupt Mask on line 3.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR4

Bit 4: Interrupt Mask on line 4.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR5

Bit 5: Interrupt Mask on line 5.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR6

Bit 6: Interrupt Mask on line 6.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR7

Bit 7: Interrupt Mask on line 7.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR8

Bit 8: Interrupt Mask on line 8.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR9

Bit 9: Interrupt Mask on line 9.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR10

Bit 10: Interrupt Mask on line 10.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR11

Bit 11: Interrupt Mask on line 11.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR12

Bit 12: Interrupt Mask on line 12.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR13

Bit 13: Interrupt Mask on line 13.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR14

Bit 14: Interrupt Mask on line 14.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR15

Bit 15: Interrupt Mask on line 15.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR16

Bit 16: Interrupt Mask on line 16.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR17

Bit 17: Interrupt Mask on line 17.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EMR

Event mask register (EXTI_EMR)

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

18/18 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														MR17 rw	MR16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MR15 rw	MR14 rw	MR13 rw	MR12 rw	MR11 rw	MR10 rw	MR9 rw	MR8 rw	MR7 rw	MR6 rw	MR5 rw	MR4 rw	MR3 rw	MR2 rw	MR1 rw	MR0 rw

Toggle fields

MR0

Bit 0: Event Mask on line 0.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR1

Bit 1: Event Mask on line 1.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR2

Bit 2: Event Mask on line 2.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR3

Bit 3: Event Mask on line 3.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR4

Bit 4: Event Mask on line 4.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR5

Bit 5: Event Mask on line 5.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR6

Bit 6: Event Mask on line 6.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR7

Bit 7: Event Mask on line 7.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR8

Bit 8: Event Mask on line 8.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR9

Bit 9: Event Mask on line 9.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR10

Bit 10: Event Mask on line 10.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR11

Bit 11: Event Mask on line 11.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR12

Bit 12: Event Mask on line 12.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR13

Bit 13: Event Mask on line 13.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR14

Bit 14: Event Mask on line 14.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR15

Bit 15: Event Mask on line 15.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR16

Bit 16: Event Mask on line 16.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR17

Bit 17: Event Mask on line 17.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

RTSR

Rising Trigger selection register (EXTI_RTSR)

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

18/18 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														TR17 rw	TR16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TR15 rw	TR14 rw	TR13 rw	TR12 rw	TR11 rw	TR10 rw	TR9 rw	TR8 rw	TR7 rw	TR6 rw	TR5 rw	TR4 rw	TR3 rw	TR2 rw	TR1 rw	TR0 rw

Toggle fields

TR0

Bit 0: Rising trigger event configuration of line 0.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR1

Bit 1: Rising trigger event configuration of line 1.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR2

Bit 2: Rising trigger event configuration of line 2.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR3

Bit 3: Rising trigger event configuration of line 3.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR4

Bit 4: Rising trigger event configuration of line 4.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR5

Bit 5: Rising trigger event configuration of line 5.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR6

Bit 6: Rising trigger event configuration of line 6.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR7

Bit 7: Rising trigger event configuration of line 7.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR8

Bit 8: Rising trigger event configuration of line 8.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR9

Bit 9: Rising trigger event configuration of line 9.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR10

Bit 10: Rising trigger event configuration of line 10.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR11

Bit 11: Rising trigger event configuration of line 11.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR12

Bit 12: Rising trigger event configuration of line 12.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR13

Bit 13: Rising trigger event configuration of line 13.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR14

Bit 14: Rising trigger event configuration of line 14.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR15

Bit 15: Rising trigger event configuration of line 15.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR16

Bit 16: Rising trigger event configuration of line 16.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR17

Bit 17: Rising trigger event configuration of line 17.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

FTSR

Falling Trigger selection register (EXTI_FTSR)

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

18/18 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														TR17 rw	TR16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TR15 rw	TR14 rw	TR13 rw	TR12 rw	TR11 rw	TR10 rw	TR9 rw	TR8 rw	TR7 rw	TR6 rw	TR5 rw	TR4 rw	TR3 rw	TR2 rw	TR1 rw	TR0 rw

Toggle fields

TR0

Bit 0: Falling trigger event configuration of line 0.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR1

Bit 1: Falling trigger event configuration of line 1.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR2

Bit 2: Falling trigger event configuration of line 2.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR3

Bit 3: Falling trigger event configuration of line 3.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR4

Bit 4: Falling trigger event configuration of line 4.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR5

Bit 5: Falling trigger event configuration of line 5.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR6

Bit 6: Falling trigger event configuration of line 6.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR7

Bit 7: Falling trigger event configuration of line 7.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR8

Bit 8: Falling trigger event configuration of line 8.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR9

Bit 9: Falling trigger event configuration of line 9.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR10

Bit 10: Falling trigger event configuration of line 10.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR11

Bit 11: Falling trigger event configuration of line 11.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR12

Bit 12: Falling trigger event configuration of line 12.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR13

Bit 13: Falling trigger event configuration of line 13.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR14

Bit 14: Falling trigger event configuration of line 14.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR15

Bit 15: Falling trigger event configuration of line 15.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR16

Bit 16: Falling trigger event configuration of line 16.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR17

Bit 17: Falling trigger event configuration of line 17.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

SWIER

Software interrupt event register (EXTI_SWIER)

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

18/18 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														SWIER17 rw	SWIER16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWIER15 rw	SWIER14 rw	SWIER13 rw	SWIER12 rw	SWIER11 rw	SWIER10 rw	SWIER9 rw	SWIER8 rw	SWIER7 rw	SWIER6 rw	SWIER5 rw	SWIER4 rw	SWIER3 rw	SWIER2 rw	SWIER1 rw	SWIER0 rw

Toggle fields

SWIER0

Bit 0: Software Interrupt on line 0.

Allowed values:
1: Pend: Generates an interrupt request

SWIER1

Bit 1: Software Interrupt on line 1.

Allowed values:
1: Pend: Generates an interrupt request

SWIER2

Bit 2: Software Interrupt on line 2.

Allowed values:
1: Pend: Generates an interrupt request

SWIER3

Bit 3: Software Interrupt on line 3.

Allowed values:
1: Pend: Generates an interrupt request

SWIER4

Bit 4: Software Interrupt on line 4.

Allowed values:
1: Pend: Generates an interrupt request

SWIER5

Bit 5: Software Interrupt on line 5.

Allowed values:
1: Pend: Generates an interrupt request

SWIER6

Bit 6: Software Interrupt on line 6.

Allowed values:
1: Pend: Generates an interrupt request

SWIER7

Bit 7: Software Interrupt on line 7.

Allowed values:
1: Pend: Generates an interrupt request

SWIER8

Bit 8: Software Interrupt on line 8.

Allowed values:
1: Pend: Generates an interrupt request

SWIER9

Bit 9: Software Interrupt on line 9.

Allowed values:
1: Pend: Generates an interrupt request

SWIER10

Bit 10: Software Interrupt on line 10.

Allowed values:
1: Pend: Generates an interrupt request

SWIER11

Bit 11: Software Interrupt on line 11.

Allowed values:
1: Pend: Generates an interrupt request

SWIER12

Bit 12: Software Interrupt on line 12.

Allowed values:
1: Pend: Generates an interrupt request

SWIER13

Bit 13: Software Interrupt on line 13.

Allowed values:
1: Pend: Generates an interrupt request

SWIER14

Bit 14: Software Interrupt on line 14.

Allowed values:
1: Pend: Generates an interrupt request

SWIER15

Bit 15: Software Interrupt on line 15.

Allowed values:
1: Pend: Generates an interrupt request

SWIER16

Bit 16: Software Interrupt on line 16.

Allowed values:
1: Pend: Generates an interrupt request

SWIER17

Bit 17: Software Interrupt on line 17.

Allowed values:
1: Pend: Generates an interrupt request

PR

Pending register (EXTI_PR)

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

18/18 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														PR17 rw	PR16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PR15 rw	PR14 rw	PR13 rw	PR12 rw	PR11 rw	PR10 rw	PR9 rw	PR8 rw	PR7 rw	PR6 rw	PR5 rw	PR4 rw	PR3 rw	PR2 rw	PR1 rw	PR0 rw

Toggle fields

PR0

Bit 0: Pending bit 0.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR1

Bit 1: Pending bit 1.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR2

Bit 2: Pending bit 2.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR3

Bit 3: Pending bit 3.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR4

Bit 4: Pending bit 4.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR5

Bit 5: Pending bit 5.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR6

Bit 6: Pending bit 6.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR7

Bit 7: Pending bit 7.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR8

Bit 8: Pending bit 8.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR9

Bit 9: Pending bit 9.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR10

Bit 10: Pending bit 10.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR11

Bit 11: Pending bit 11.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR12

Bit 12: Pending bit 12.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR13

Bit 13: Pending bit 13.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR14

Bit 14: Pending bit 14.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR15

Bit 15: Pending bit 15.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR16

Bit 16: Pending bit 16.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR17

Bit 17: Pending bit 17.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

FLASH

0x40022000: FLASH

9/26 fields covered.

Toggle register map

Offset	Name	31	25	17	15	12	10	9	7	6	5	4	3	2	1	0
0x0	ACR												HLFCYA
0x4	KEYR	KEY			KEY
0x8	OPTKEYR	OPTKEY			OPTKEY
0xc	SR										EOP	WRPRTERR		PGERR		BSY
0x10	CR					EOPIE	ERRIE	OPTWRE	LOCK	STRT	OPTER	OPTPG		MER	PER	PG
0x14	AR	FAR			FAR
0x1c	OBR		Data1	Data0	Data0							nRST_STDBY	nRST_STOP	WDG_SW	RDPRT	OPTERR
0x20	WRPR	WRP			WRP

Toggle registers

ACR

Flash access control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												HLFCYA rw

Toggle fields

HLFCYA

Bit 3: Flash half cycle access enable.

KEYR

Flash key register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
KEY w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY w

Toggle fields

KEY

Bits 0-31: FPEC key.

OPTKEYR

Flash option key register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OPTKEY w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OPTKEY w

Toggle fields

OPTKEY

Bits 0-31: Option byte key.

SR

Status register

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

1/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										EOP rw	WRPRTERR rw		PGERR rw		BSY r

Toggle fields

BSY

Bit 0: Busy.

PGERR

Bit 2: Programming error.

WRPRTERR

Bit 4: Write protection error.

EOP

Bit 5: End of operation.

CR

Control register

Offset: 0x10, size: 32, reset: 0x00000080, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			EOPIE rw		ERRIE rw	OPTWRE rw		LOCK rw	STRT rw	OPTER rw	OPTPG rw		MER rw	PER rw	PG rw

Toggle fields

PG

Bit 0: Programming.

PER

Bit 1: Page Erase.

MER

Bit 2: Mass Erase.

OPTPG

Bit 4: Option byte programming.

OPTER

Bit 5: Option byte erase.

STRT

Bit 6: Start.

LOCK

Bit 7: Lock.

OPTWRE

Bit 9: Option bytes write enable.

ERRIE

Bit 10: Error interrupt enable.

EOPIE

Bit 12: End of operation interrupt enable.

AR

Flash address register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
FAR w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FAR w

Toggle fields

FAR

Bits 0-31: Flash Address.

OBR

Option byte register

Offset: 0x1c, size: 32, reset: 0x03FFFFFC, access: read-only

7/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						Data1 r								Data0 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Data0 r											nRST_STDBY r	nRST_STOP r	WDG_SW r	RDPRT r	OPTERR r

Toggle fields

OPTERR

Bit 0: Option byte error.

RDPRT

Bit 1: Read protection.

WDG_SW

Bit 2: WDG_SW.

nRST_STOP

Bit 3: nRST_STOP.

nRST_STDBY

Bit 4: nRST_STDBY.

Data0

Bits 10-17: Data0.

Data1

Bits 18-25: Data1.

WRPR

Write protection register

Offset: 0x20, size: 32, reset: 0xFFFFFFFF, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
WRP r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WRP r

Toggle fields

WRP

Bits 0-31: Write protect.

FSMC

0xa0000000: Flexible static memory controller

104/116 fields covered.

Toggle register map

Offset	Name	29	27	23	19	18	15	14	13	12	11	10	9	8	7	6	5	3	1	0
0x0	BCR1				CBURSTRW	CPSIZE	ASYNCWAIT	EXTMOD	WAITEN	WREN	WAITCFG	WRAPMOD	WAITPOL	BURSTEN		FACCEN	MWID	MTYP	MUXEN	MBKEN
0x4	BTR[1]	ACCMOD	DATLAT	CLKDIV	BUSTURN		DATAST								ADDHLD			ADDSET
0x8	BCR[2]				CBURSTRW	CPSIZE	ASYNCWAIT	EXTMOD	WAITEN	WREN	WAITCFG	WRAPMOD	WAITPOL	BURSTEN		FACCEN	MWID	MTYP	MUXEN	MBKEN
0xc	BTR[2]	ACCMOD	DATLAT	CLKDIV	BUSTURN		DATAST								ADDHLD			ADDSET
0x10	BCR[3]				CBURSTRW	CPSIZE	ASYNCWAIT	EXTMOD	WAITEN	WREN	WAITCFG	WRAPMOD	WAITPOL	BURSTEN		FACCEN	MWID	MTYP	MUXEN	MBKEN
0x14	BTR[3]	ACCMOD	DATLAT	CLKDIV	BUSTURN		DATAST								ADDHLD			ADDSET
0x18	BCR[4]				CBURSTRW	CPSIZE	ASYNCWAIT	EXTMOD	WAITEN	WREN	WAITCFG	WRAPMOD	WAITPOL	BURSTEN		FACCEN	MWID	MTYP	MUXEN	MBKEN
0x1c	BTR[4]	ACCMOD	DATLAT	CLKDIV	BUSTURN		DATAST								ADDHLD			ADDSET
0x104	BWTR[1]	ACCMOD	DATLAT	CLKDIV	BUSTURN		DATAST								ADDHLD			ADDSET
0x10c	BWTR[2]	ACCMOD	DATLAT	CLKDIV	BUSTURN		DATAST								ADDHLD			ADDSET
0x114	BWTR[3]	ACCMOD	DATLAT	CLKDIV	BUSTURN		DATAST								ADDHLD			ADDSET
0x11c	BWTR[4]	ACCMOD	DATLAT	CLKDIV	BUSTURN		DATAST								ADDHLD			ADDSET

Toggle registers

BCR1

SRAM/NOR-Flash chip-select control register 1

Offset: 0x0, size: 32, reset: 0x000030D0, access: read-write

14/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												CBURSTRW rw	CPSIZE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ASYNCWAIT rw	EXTMOD rw	WAITEN rw	WREN rw	WAITCFG rw	WRAPMOD rw	WAITPOL rw	BURSTEN rw		FACCEN rw	MWID rw		MTYP rw		MUXEN rw	MBKEN rw

Toggle fields

MBKEN

Bit 0: MBKEN.

Allowed values:
0: Disabled: Corresponding memory bank is disabled
1: Enabled: Corresponding memory bank is enabled

MUXEN

Bit 1: MUXEN.

Allowed values:
0: Disabled: Address/Data non-multiplexed
1: Enabled: Address/Data multiplexed on databus

MTYP

Bits 2-3: MTYP.

Allowed values:
0: SRAM: SRAM memory type
1: PSRAM: PSRAM (CRAM) memory type
2: Flash: NOR Flash/OneNAND Flash

MWID

Bits 4-5: MWID.

Allowed values:
0: Bits8: Memory data bus width 8 bits
1: Bits16: Memory data bus width 16 bits
2: Bits32: Memory data bus width 32 bits

FACCEN

Bit 6: FACCEN.

Allowed values:
0: Disabled: Corresponding NOR Flash memory access is disabled
1: Enabled: Corresponding NOR Flash memory access is enabled

BURSTEN

Bit 8: BURSTEN.

Allowed values:
0: Disabled: Burst mode disabled
1: Enabled: Burst mode enabled

WAITPOL

Bit 9: WAITPOL.

Allowed values:
0: ActiveLow: NWAIT active low
1: ActiveHigh: NWAIT active high

WRAPMOD

Bit 10: WRAPMOD.

WAITCFG

Bit 11: WAITCFG.

Allowed values:
0: BeforeWaitState: NWAIT signal is active one data cycle before wait state
1: DuringWaitState: NWAIT signal is active during wait state

WREN

Bit 12: WREN.

Allowed values:
0: Disabled: Write operations disabled for the bank by the FMC
1: Enabled: Write operations enabled for the bank by the FMC

WAITEN

Bit 13: WAITEN.

Allowed values:
0: Disabled: Values inside the FMC_BWTR are taken into account
1: Enabled: NWAIT signal enabled

EXTMOD

Bit 14: EXTMOD.

Allowed values:
0: Disabled: Values inside the FMC_BWTR are not taken into account
1: Enabled: Values inside the FMC_BWTR are taken into account

ASYNCWAIT

Bit 15: ASYNCWAIT.

Allowed values:
0: Disabled: Wait signal not used in asynchronous mode
1: Enabled: Wait signal used even in asynchronous mode

CPSIZE

Bits 16-18: CRAM page size.

Allowed values:
0: NoBurstSplit: No burst split when crossing page boundary
1: Bytes128: 128 bytes CRAM page size
2: Bytes256: 256 bytes CRAM page size
3: Bytes512: 512 bytes CRAM page size
4: Bytes1024: 1024 bytes CRAM page size

CBURSTRW

Bit 19: CBURSTRW.

Allowed values:
0: Disabled: Write operations are always performed in asynchronous mode
1: Enabled: Write operations are performed in synchronous mode

BTR[1]

SRAM/NOR-Flash chip-select timing register 1

Offset: 0x4, size: 32, reset: 0xFFFFFFFF, access: read-write

7/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		ACCMOD rw		DATLAT rw				CLKDIV rw				BUSTURN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATAST rw								ADDHLD rw				ADDSET rw

Toggle fields

ADDSET

Bits 0-3: ADDSET.

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: ADDHLD.

Allowed values: 0x1-0xf

DATAST

Bits 8-15: DATAST.

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: BUSTURN.

Allowed values: 0x0-0xf

CLKDIV

Bits 20-23: CLKDIV.

Allowed values: 0x1-0xf

DATLAT

Bits 24-27: DATLAT.

Allowed values: 0x0-0xf

ACCMOD

Bits 28-29: ACCMOD.

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

BCR[2]

SRAM/NOR-Flash chip-select control register 2

Offset: 0x8, size: 32, reset: 0x000030D0, access: read-write

14/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												CBURSTRW rw	CPSIZE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ASYNCWAIT rw	EXTMOD rw	WAITEN rw	WREN rw	WAITCFG rw	WRAPMOD rw	WAITPOL rw	BURSTEN rw		FACCEN rw	MWID rw		MTYP rw		MUXEN rw	MBKEN rw

Toggle fields

MBKEN

Bit 0: MBKEN.

Allowed values:
0: Disabled: Corresponding memory bank is disabled
1: Enabled: Corresponding memory bank is enabled

MUXEN

Bit 1: MUXEN.

Allowed values:
0: Disabled: Address/Data non-multiplexed
1: Enabled: Address/Data multiplexed on databus

MTYP

Bits 2-3: MTYP.

Allowed values:
0: SRAM: SRAM memory type
1: PSRAM: PSRAM (CRAM) memory type
2: Flash: NOR Flash/OneNAND Flash

MWID

Bits 4-5: MWID.

Allowed values:
0: Bits8: Memory data bus width 8 bits
1: Bits16: Memory data bus width 16 bits
2: Bits32: Memory data bus width 32 bits

FACCEN

Bit 6: FACCEN.

Allowed values:
0: Disabled: Corresponding NOR Flash memory access is disabled
1: Enabled: Corresponding NOR Flash memory access is enabled

BURSTEN

Bit 8: BURSTEN.

Allowed values:
0: Disabled: Burst mode disabled
1: Enabled: Burst mode enabled

WAITPOL

Bit 9: WAITPOL.

Allowed values:
0: ActiveLow: NWAIT active low
1: ActiveHigh: NWAIT active high

WRAPMOD

Bit 10: WRAPMOD.

WAITCFG

Bit 11: WAITCFG.

Allowed values:
0: BeforeWaitState: NWAIT signal is active one data cycle before wait state
1: DuringWaitState: NWAIT signal is active during wait state

WREN

Bit 12: WREN.

Allowed values:
0: Disabled: Write operations disabled for the bank by the FMC
1: Enabled: Write operations enabled for the bank by the FMC

WAITEN

Bit 13: WAITEN.

Allowed values:
0: Disabled: Values inside the FMC_BWTR are taken into account
1: Enabled: NWAIT signal enabled

EXTMOD

Bit 14: EXTMOD.

Allowed values:
0: Disabled: Values inside the FMC_BWTR are not taken into account
1: Enabled: Values inside the FMC_BWTR are taken into account

ASYNCWAIT

Bit 15: ASYNCWAIT.

Allowed values:
0: Disabled: Wait signal not used in asynchronous mode
1: Enabled: Wait signal used even in asynchronous mode

CPSIZE

Bits 16-18: CRAM page size.

Allowed values:
0: NoBurstSplit: No burst split when crossing page boundary
1: Bytes128: 128 bytes CRAM page size
2: Bytes256: 256 bytes CRAM page size
3: Bytes512: 512 bytes CRAM page size
4: Bytes1024: 1024 bytes CRAM page size

CBURSTRW

Bit 19: CBURSTRW.

Allowed values:
0: Disabled: Write operations are always performed in asynchronous mode
1: Enabled: Write operations are performed in synchronous mode

BTR[2]

SRAM/NOR-Flash chip-select timing register 2

Offset: 0xc, size: 32, reset: 0xFFFFFFFF, access: read-write

7/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		ACCMOD rw		DATLAT rw				CLKDIV rw				BUSTURN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATAST rw								ADDHLD rw				ADDSET rw

Toggle fields

ADDSET

Bits 0-3: ADDSET.

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: ADDHLD.

Allowed values: 0x1-0xf

DATAST

Bits 8-15: DATAST.

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: BUSTURN.

Allowed values: 0x0-0xf

CLKDIV

Bits 20-23: CLKDIV.

Allowed values: 0x1-0xf

DATLAT

Bits 24-27: DATLAT.

Allowed values: 0x0-0xf

ACCMOD

Bits 28-29: ACCMOD.

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

BCR[3]

SRAM/NOR-Flash chip-select control register 3

Offset: 0x10, size: 32, reset: 0x000030D0, access: read-write

14/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												CBURSTRW rw	CPSIZE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ASYNCWAIT rw	EXTMOD rw	WAITEN rw	WREN rw	WAITCFG rw	WRAPMOD rw	WAITPOL rw	BURSTEN rw		FACCEN rw	MWID rw		MTYP rw		MUXEN rw	MBKEN rw

Toggle fields

MBKEN

Bit 0: MBKEN.

Allowed values:
0: Disabled: Corresponding memory bank is disabled
1: Enabled: Corresponding memory bank is enabled

MUXEN

Bit 1: MUXEN.

Allowed values:
0: Disabled: Address/Data non-multiplexed
1: Enabled: Address/Data multiplexed on databus

MTYP

Bits 2-3: MTYP.

Allowed values:
0: SRAM: SRAM memory type
1: PSRAM: PSRAM (CRAM) memory type
2: Flash: NOR Flash/OneNAND Flash

MWID

Bits 4-5: MWID.

Allowed values:
0: Bits8: Memory data bus width 8 bits
1: Bits16: Memory data bus width 16 bits
2: Bits32: Memory data bus width 32 bits

FACCEN

Bit 6: FACCEN.

Allowed values:
0: Disabled: Corresponding NOR Flash memory access is disabled
1: Enabled: Corresponding NOR Flash memory access is enabled

BURSTEN

Bit 8: BURSTEN.

Allowed values:
0: Disabled: Burst mode disabled
1: Enabled: Burst mode enabled

WAITPOL

Bit 9: WAITPOL.

Allowed values:
0: ActiveLow: NWAIT active low
1: ActiveHigh: NWAIT active high

WRAPMOD

Bit 10: WRAPMOD.

WAITCFG

Bit 11: WAITCFG.

Allowed values:
0: BeforeWaitState: NWAIT signal is active one data cycle before wait state
1: DuringWaitState: NWAIT signal is active during wait state

WREN

Bit 12: WREN.

Allowed values:
0: Disabled: Write operations disabled for the bank by the FMC
1: Enabled: Write operations enabled for the bank by the FMC

WAITEN

Bit 13: WAITEN.

Allowed values:
0: Disabled: Values inside the FMC_BWTR are taken into account
1: Enabled: NWAIT signal enabled

EXTMOD

Bit 14: EXTMOD.

Allowed values:
0: Disabled: Values inside the FMC_BWTR are not taken into account
1: Enabled: Values inside the FMC_BWTR are taken into account

ASYNCWAIT

Bit 15: ASYNCWAIT.

Allowed values:
0: Disabled: Wait signal not used in asynchronous mode
1: Enabled: Wait signal used even in asynchronous mode

CPSIZE

Bits 16-18: CRAM page size.

Allowed values:
0: NoBurstSplit: No burst split when crossing page boundary
1: Bytes128: 128 bytes CRAM page size
2: Bytes256: 256 bytes CRAM page size
3: Bytes512: 512 bytes CRAM page size
4: Bytes1024: 1024 bytes CRAM page size

CBURSTRW

Bit 19: CBURSTRW.

Allowed values:
0: Disabled: Write operations are always performed in asynchronous mode
1: Enabled: Write operations are performed in synchronous mode

BTR[3]

SRAM/NOR-Flash chip-select timing register 3

Offset: 0x14, size: 32, reset: 0xFFFFFFFF, access: read-write

7/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		ACCMOD rw		DATLAT rw				CLKDIV rw				BUSTURN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATAST rw								ADDHLD rw				ADDSET rw

Toggle fields

ADDSET

Bits 0-3: ADDSET.

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: ADDHLD.

Allowed values: 0x1-0xf

DATAST

Bits 8-15: DATAST.

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: BUSTURN.

Allowed values: 0x0-0xf

CLKDIV

Bits 20-23: CLKDIV.

Allowed values: 0x1-0xf

DATLAT

Bits 24-27: DATLAT.

Allowed values: 0x0-0xf

ACCMOD

Bits 28-29: ACCMOD.

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

BCR[4]

SRAM/NOR-Flash chip-select control register 4

Offset: 0x18, size: 32, reset: 0x000030D0, access: read-write

14/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												CBURSTRW rw	CPSIZE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ASYNCWAIT rw	EXTMOD rw	WAITEN rw	WREN rw	WAITCFG rw	WRAPMOD rw	WAITPOL rw	BURSTEN rw		FACCEN rw	MWID rw		MTYP rw		MUXEN rw	MBKEN rw

Toggle fields

MBKEN

Bit 0: MBKEN.

Allowed values:
0: Disabled: Corresponding memory bank is disabled
1: Enabled: Corresponding memory bank is enabled

MUXEN

Bit 1: MUXEN.

Allowed values:
0: Disabled: Address/Data non-multiplexed
1: Enabled: Address/Data multiplexed on databus

MTYP

Bits 2-3: MTYP.

Allowed values:
0: SRAM: SRAM memory type
1: PSRAM: PSRAM (CRAM) memory type
2: Flash: NOR Flash/OneNAND Flash

MWID

Bits 4-5: MWID.

Allowed values:
0: Bits8: Memory data bus width 8 bits
1: Bits16: Memory data bus width 16 bits
2: Bits32: Memory data bus width 32 bits

FACCEN

Bit 6: FACCEN.

Allowed values:
0: Disabled: Corresponding NOR Flash memory access is disabled
1: Enabled: Corresponding NOR Flash memory access is enabled

BURSTEN

Bit 8: BURSTEN.

Allowed values:
0: Disabled: Burst mode disabled
1: Enabled: Burst mode enabled

WAITPOL

Bit 9: WAITPOL.

Allowed values:
0: ActiveLow: NWAIT active low
1: ActiveHigh: NWAIT active high

WRAPMOD

Bit 10: WRAPMOD.

WAITCFG

Bit 11: WAITCFG.

Allowed values:
0: BeforeWaitState: NWAIT signal is active one data cycle before wait state
1: DuringWaitState: NWAIT signal is active during wait state

WREN

Bit 12: WREN.

Allowed values:
0: Disabled: Write operations disabled for the bank by the FMC
1: Enabled: Write operations enabled for the bank by the FMC

WAITEN

Bit 13: WAITEN.

Allowed values:
0: Disabled: Values inside the FMC_BWTR are taken into account
1: Enabled: NWAIT signal enabled

EXTMOD

Bit 14: EXTMOD.

Allowed values:
0: Disabled: Values inside the FMC_BWTR are not taken into account
1: Enabled: Values inside the FMC_BWTR are taken into account

ASYNCWAIT

Bit 15: ASYNCWAIT.

Allowed values:
0: Disabled: Wait signal not used in asynchronous mode
1: Enabled: Wait signal used even in asynchronous mode

CPSIZE

Bits 16-18: CRAM page size.

Allowed values:
0: NoBurstSplit: No burst split when crossing page boundary
1: Bytes128: 128 bytes CRAM page size
2: Bytes256: 256 bytes CRAM page size
3: Bytes512: 512 bytes CRAM page size
4: Bytes1024: 1024 bytes CRAM page size

CBURSTRW

Bit 19: CBURSTRW.

Allowed values:
0: Disabled: Write operations are always performed in asynchronous mode
1: Enabled: Write operations are performed in synchronous mode

BTR[4]

SRAM/NOR-Flash chip-select timing register 4

Offset: 0x1c, size: 32, reset: 0xFFFFFFFF, access: read-write

7/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		ACCMOD rw		DATLAT rw				CLKDIV rw				BUSTURN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATAST rw								ADDHLD rw				ADDSET rw

Toggle fields

ADDSET

Bits 0-3: ADDSET.

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: ADDHLD.

Allowed values: 0x1-0xf

DATAST

Bits 8-15: DATAST.

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: BUSTURN.

Allowed values: 0x0-0xf

CLKDIV

Bits 20-23: CLKDIV.

Allowed values: 0x1-0xf

DATLAT

Bits 24-27: DATLAT.

Allowed values: 0x0-0xf

ACCMOD

Bits 28-29: ACCMOD.

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

BWTR[1]

SRAM/NOR-Flash write timing registers 1

Offset: 0x104, size: 32, reset: 0x0FFFFFFF, access: read-write

5/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		ACCMOD rw		DATLAT rw				CLKDIV rw				BUSTURN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATAST rw								ADDHLD rw				ADDSET rw

Toggle fields

ADDSET

Bits 0-3: ADDSET.

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: ADDHLD.

Allowed values: 0x1-0xf

DATAST

Bits 8-15: DATAST.

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: Bus turnaround phase duration.

Allowed values: 0x0-0xf

CLKDIV

Bits 20-23: CLKDIV.

DATLAT

Bits 24-27: DATLAT.

ACCMOD

Bits 28-29: ACCMOD.

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

BWTR[2]

SRAM/NOR-Flash write timing registers 2

Offset: 0x10c, size: 32, reset: 0x0FFFFFFF, access: read-write

5/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		ACCMOD rw		DATLAT rw				CLKDIV rw				BUSTURN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATAST rw								ADDHLD rw				ADDSET rw

Toggle fields

ADDSET

Bits 0-3: ADDSET.

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: ADDHLD.

Allowed values: 0x1-0xf

DATAST

Bits 8-15: DATAST.

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: Bus turnaround phase duration.

Allowed values: 0x0-0xf

CLKDIV

Bits 20-23: CLKDIV.

DATLAT

Bits 24-27: DATLAT.

ACCMOD

Bits 28-29: ACCMOD.

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

BWTR[3]

SRAM/NOR-Flash write timing registers 3

Offset: 0x114, size: 32, reset: 0x0FFFFFFF, access: read-write

5/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		ACCMOD rw		DATLAT rw				CLKDIV rw				BUSTURN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATAST rw								ADDHLD rw				ADDSET rw

Toggle fields

ADDSET

Bits 0-3: ADDSET.

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: ADDHLD.

Allowed values: 0x1-0xf

DATAST

Bits 8-15: DATAST.

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: Bus turnaround phase duration.

Allowed values: 0x0-0xf

CLKDIV

Bits 20-23: CLKDIV.

DATLAT

Bits 24-27: DATLAT.

ACCMOD

Bits 28-29: ACCMOD.

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

BWTR[4]

SRAM/NOR-Flash write timing registers 4

Offset: 0x11c, size: 32, reset: 0x0FFFFFFF, access: read-write

5/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		ACCMOD rw		DATLAT rw				CLKDIV rw				BUSTURN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATAST rw								ADDHLD rw				ADDSET rw

Toggle fields

ADDSET

Bits 0-3: ADDSET.

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: ADDHLD.

Allowed values: 0x1-0xf

DATAST

Bits 8-15: DATAST.

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: Bus turnaround phase duration.

Allowed values: 0x0-0xf

CLKDIV

Bits 20-23: CLKDIV.

DATLAT

Bits 24-27: DATLAT.

ACCMOD

Bits 28-29: ACCMOD.

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

GPIOA

0x40010800: General purpose I/O

129/129 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CRL	CNF[7]		MODE[7]		CNF[6]		MODE[6]		CNF[5]		MODE[5]		CNF[4]		MODE[4]		CNF[3]		MODE[3]		CNF[2]		MODE[2]		CNF[1]		MODE[1]		CNF[0]		MODE[0]
0x4	CRH	CNF[15]		MODE[15]		CNF[14]		MODE[14]		CNF[13]		MODE[13]		CNF[12]		MODE[12]		CNF[11]		MODE[11]		CNF[10]		MODE[10]		CNF[9]		MODE[9]		CNF[8]		MODE[8]
0x8	IDR																	IDR[15]	IDR[14]	IDR[13]	IDR[12]	IDR[11]	IDR[10]	IDR[9]	IDR[8]	IDR[7]	IDR[6]	IDR[5]	IDR[4]	IDR[3]	IDR[2]	IDR[1]	IDR[0]
0xc	ODR																	ODR[15]	ODR[14]	ODR[13]	ODR[12]	ODR[11]	ODR[10]	ODR[9]	ODR[8]	ODR[7]	ODR[6]	ODR[5]	ODR[4]	ODR[3]	ODR[2]	ODR[1]	ODR[0]
0x10	BSRR	BR[15]	BR[14]	BR[13]	BR[12]	BR[11]	BR[10]	BR[9]	BR[8]	BR[7]	BR[6]	BR[5]	BR[4]	BR[3]	BR[2]	BR[1]	BR[0]	BS[15]	BS[14]	BS[13]	BS[12]	BS[11]	BS[10]	BS[9]	BS[8]	BS[7]	BS[6]	BS[5]	BS[4]	BS[3]	BS[2]	BS[1]	BS[0]
0x14	BRR																	BR[15]	BR[14]	BR[13]	BR[12]	BR[11]	BR[10]	BR[9]	BR[8]	BR[7]	BR[6]	BR[5]	BR[4]	BR[3]	BR[2]	BR[1]	BR[0]
0x18	LCKR																LCKK	LCK[15]	LCK[14]	LCK[13]	LCK[12]	LCK[11]	LCK[10]	LCK[9]	LCK[8]	LCK[7]	LCK[6]	LCK[5]	LCK[4]	LCK[3]	LCK[2]	LCK[1]	LCK[0]

Toggle registers

CRL

Port configuration register low (GPIOn_CRL)

Offset: 0x0, size: 32, reset: 0x44444444, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CNF[7] rw		MODE[7] rw		CNF[6] rw		MODE[6] rw		CNF[5] rw		MODE[5] rw		CNF[4] rw		MODE[4] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNF[3] rw		MODE[3] rw		CNF[2] rw		MODE[2] rw		CNF[1] rw		MODE[1] rw		CNF[0] rw		MODE[0] rw

Toggle fields

MODE[0]

Bits 0-1: Port n.0 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[0]

Bits 2-3: Port n.0 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[1]

Bits 4-5: Port n.1 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[1]

Bits 6-7: Port n.1 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[2]

Bits 8-9: Port n.2 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[2]

Bits 10-11: Port n.2 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[3]

Bits 12-13: Port n.3 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[3]

Bits 14-15: Port n.3 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[4]

Bits 16-17: Port n.4 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[4]

Bits 18-19: Port n.4 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[5]

Bits 20-21: Port n.5 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[5]

Bits 22-23: Port n.5 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[6]

Bits 24-25: Port n.6 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[6]

Bits 26-27: Port n.6 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[7]

Bits 28-29: Port n.7 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[7]

Bits 30-31: Port n.7 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

CRH

Port configuration register high (GPIOn_CRL)

Offset: 0x4, size: 32, reset: 0x44444444, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CNF[15] rw		MODE[15] rw		CNF[14] rw		MODE[14] rw		CNF[13] rw		MODE[13] rw		CNF[12] rw		MODE[12] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNF[11] rw		MODE[11] rw		CNF[10] rw		MODE[10] rw		CNF[9] rw		MODE[9] rw		CNF[8] rw		MODE[8] rw

Toggle fields

MODE[8]

Bits 0-1: Port n.8 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[8]

Bits 2-3: Port n.8 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[9]

Bits 4-5: Port n.9 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[9]

Bits 6-7: Port n.9 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[10]

Bits 8-9: Port n.10 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[10]

Bits 10-11: Port n.10 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[11]

Bits 12-13: Port n.11 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[11]

Bits 14-15: Port n.11 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[12]

Bits 16-17: Port n.12 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[12]

Bits 18-19: Port n.12 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[13]

Bits 20-21: Port n.13 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[13]

Bits 22-23: Port n.13 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[14]

Bits 24-25: Port n.14 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[14]

Bits 26-27: Port n.14 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[15]

Bits 28-29: Port n.15 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[15]

Bits 30-31: Port n.15 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

IDR

Port input data register (GPIOn_IDR)

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IDR[15] r	IDR[14] r	IDR[13] r	IDR[12] r	IDR[11] r	IDR[10] r	IDR[9] r	IDR[8] r	IDR[7] r	IDR[6] r	IDR[5] r	IDR[4] r	IDR[3] r	IDR[2] r	IDR[1] r	IDR[0] r

Toggle fields

IDR[0]

Bit 0: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

Port output data register (GPIOn_ODR)

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ODR[15] rw	ODR[14] rw	ODR[13] rw	ODR[12] rw	ODR[11] rw	ODR[10] rw	ODR[9] rw	ODR[8] rw	ODR[7] rw	ODR[6] rw	ODR[5] rw	ODR[4] rw	ODR[3] rw	ODR[2] rw	ODR[1] rw	ODR[0] rw

Toggle fields

ODR[0]

Bit 0: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

Port bit set/reset register (GPIOn_BSRR)

Offset: 0x10, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR[15] w	BR[14] w	BR[13] w	BR[12] w	BR[11] w	BR[10] w	BR[9] w	BR[8] w	BR[7] w	BR[6] w	BR[5] w	BR[4] w	BR[3] w	BR[2] w	BR[1] w	BR[0] w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS[15] w	BS[14] w	BS[13] w	BS[12] w	BS[11] w	BS[10] w	BS[9] w	BS[8] w	BS[7] w	BS[6] w	BS[5] w	BS[4] w	BS[3] w	BS[2] w	BS[1] w	BS[0] w

Toggle fields

BS[0]

Bit 0: Set bit 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Set bit 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Set bit 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Set bit 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Set bit 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Set bit 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Set bit 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Set bit 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Set bit 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Set bit 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Set bit 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Set bit 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Set bit 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Set bit 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Set bit 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Set bit 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Reset bit 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Reset bit 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Reset bit 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Reset bit 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Reset bit 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Reset bit 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Reset bit 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Reset bit 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Reset bit 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Reset bit 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Reset bit 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Reset bit 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Reset bit 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Reset bit 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Reset bit 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Reset bit 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BRR

Port bit reset register (GPIOn_BRR)

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR[15] w	BR[14] w	BR[13] w	BR[12] w	BR[11] w	BR[10] w	BR[9] w	BR[8] w	BR[7] w	BR[6] w	BR[5] w	BR[4] w	BR[3] w	BR[2] w	BR[1] w	BR[0] w

Toggle fields

BR[0]

Bit 0: Reset bit 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Reset bit 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Reset bit 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Reset bit 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Reset bit 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Reset bit 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Reset bit 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Reset bit 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Reset bit 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Reset bit 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Reset bit 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Reset bit 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Reset bit 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Reset bit 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Reset bit 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Reset bit 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

LCKR

Port configuration lock register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK[15] rw	LCK[14] rw	LCK[13] rw	LCK[12] rw	LCK[11] rw	LCK[10] rw	LCK[9] rw	LCK[8] rw	LCK[7] rw	LCK[6] rw	LCK[5] rw	LCK[4] rw	LCK[3] rw	LCK[2] rw	LCK[1] rw	LCK[0] rw

Toggle fields

LCK[0]

Bit 0: Port A Lock bit 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port A Lock bit 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port A Lock bit 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port A Lock bit 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port A Lock bit 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port A Lock bit 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port A Lock bit 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port A Lock bit 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port A Lock bit 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port A Lock bit 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port A Lock bit 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port A Lock bit 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port A Lock bit 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port A Lock bit 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port A Lock bit 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port A Lock bit 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Lock key.

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

GPIOB

0x40010c00: General purpose I/O

129/129 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CRL	CNF[7]		MODE[7]		CNF[6]		MODE[6]		CNF[5]		MODE[5]		CNF[4]		MODE[4]		CNF[3]		MODE[3]		CNF[2]		MODE[2]		CNF[1]		MODE[1]		CNF[0]		MODE[0]
0x4	CRH	CNF[15]		MODE[15]		CNF[14]		MODE[14]		CNF[13]		MODE[13]		CNF[12]		MODE[12]		CNF[11]		MODE[11]		CNF[10]		MODE[10]		CNF[9]		MODE[9]		CNF[8]		MODE[8]
0x8	IDR																	IDR[15]	IDR[14]	IDR[13]	IDR[12]	IDR[11]	IDR[10]	IDR[9]	IDR[8]	IDR[7]	IDR[6]	IDR[5]	IDR[4]	IDR[3]	IDR[2]	IDR[1]	IDR[0]
0xc	ODR																	ODR[15]	ODR[14]	ODR[13]	ODR[12]	ODR[11]	ODR[10]	ODR[9]	ODR[8]	ODR[7]	ODR[6]	ODR[5]	ODR[4]	ODR[3]	ODR[2]	ODR[1]	ODR[0]
0x10	BSRR	BR[15]	BR[14]	BR[13]	BR[12]	BR[11]	BR[10]	BR[9]	BR[8]	BR[7]	BR[6]	BR[5]	BR[4]	BR[3]	BR[2]	BR[1]	BR[0]	BS[15]	BS[14]	BS[13]	BS[12]	BS[11]	BS[10]	BS[9]	BS[8]	BS[7]	BS[6]	BS[5]	BS[4]	BS[3]	BS[2]	BS[1]	BS[0]
0x14	BRR																	BR[15]	BR[14]	BR[13]	BR[12]	BR[11]	BR[10]	BR[9]	BR[8]	BR[7]	BR[6]	BR[5]	BR[4]	BR[3]	BR[2]	BR[1]	BR[0]
0x18	LCKR																LCKK	LCK[15]	LCK[14]	LCK[13]	LCK[12]	LCK[11]	LCK[10]	LCK[9]	LCK[8]	LCK[7]	LCK[6]	LCK[5]	LCK[4]	LCK[3]	LCK[2]	LCK[1]	LCK[0]

Toggle registers

CRL

Port configuration register low (GPIOn_CRL)

Offset: 0x0, size: 32, reset: 0x44444444, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CNF[7] rw		MODE[7] rw		CNF[6] rw		MODE[6] rw		CNF[5] rw		MODE[5] rw		CNF[4] rw		MODE[4] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNF[3] rw		MODE[3] rw		CNF[2] rw		MODE[2] rw		CNF[1] rw		MODE[1] rw		CNF[0] rw		MODE[0] rw

Toggle fields

MODE[0]

Bits 0-1: Port n.0 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[0]

Bits 2-3: Port n.0 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[1]

Bits 4-5: Port n.1 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[1]

Bits 6-7: Port n.1 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[2]

Bits 8-9: Port n.2 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[2]

Bits 10-11: Port n.2 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[3]

Bits 12-13: Port n.3 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[3]

Bits 14-15: Port n.3 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[4]

Bits 16-17: Port n.4 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[4]

Bits 18-19: Port n.4 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[5]

Bits 20-21: Port n.5 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[5]

Bits 22-23: Port n.5 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[6]

Bits 24-25: Port n.6 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[6]

Bits 26-27: Port n.6 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[7]

Bits 28-29: Port n.7 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[7]

Bits 30-31: Port n.7 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

CRH

Port configuration register high (GPIOn_CRL)

Offset: 0x4, size: 32, reset: 0x44444444, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CNF[15] rw		MODE[15] rw		CNF[14] rw		MODE[14] rw		CNF[13] rw		MODE[13] rw		CNF[12] rw		MODE[12] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNF[11] rw		MODE[11] rw		CNF[10] rw		MODE[10] rw		CNF[9] rw		MODE[9] rw		CNF[8] rw		MODE[8] rw

Toggle fields

MODE[8]

Bits 0-1: Port n.8 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[8]

Bits 2-3: Port n.8 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[9]

Bits 4-5: Port n.9 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[9]

Bits 6-7: Port n.9 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[10]

Bits 8-9: Port n.10 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[10]

Bits 10-11: Port n.10 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[11]

Bits 12-13: Port n.11 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[11]

Bits 14-15: Port n.11 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[12]

Bits 16-17: Port n.12 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[12]

Bits 18-19: Port n.12 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[13]

Bits 20-21: Port n.13 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[13]

Bits 22-23: Port n.13 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[14]

Bits 24-25: Port n.14 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[14]

Bits 26-27: Port n.14 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[15]

Bits 28-29: Port n.15 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[15]

Bits 30-31: Port n.15 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

IDR

Port input data register (GPIOn_IDR)

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IDR[15] r	IDR[14] r	IDR[13] r	IDR[12] r	IDR[11] r	IDR[10] r	IDR[9] r	IDR[8] r	IDR[7] r	IDR[6] r	IDR[5] r	IDR[4] r	IDR[3] r	IDR[2] r	IDR[1] r	IDR[0] r

Toggle fields

IDR[0]

Bit 0: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

Port output data register (GPIOn_ODR)

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ODR[15] rw	ODR[14] rw	ODR[13] rw	ODR[12] rw	ODR[11] rw	ODR[10] rw	ODR[9] rw	ODR[8] rw	ODR[7] rw	ODR[6] rw	ODR[5] rw	ODR[4] rw	ODR[3] rw	ODR[2] rw	ODR[1] rw	ODR[0] rw

Toggle fields

ODR[0]

Bit 0: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

Port bit set/reset register (GPIOn_BSRR)

Offset: 0x10, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR[15] w	BR[14] w	BR[13] w	BR[12] w	BR[11] w	BR[10] w	BR[9] w	BR[8] w	BR[7] w	BR[6] w	BR[5] w	BR[4] w	BR[3] w	BR[2] w	BR[1] w	BR[0] w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS[15] w	BS[14] w	BS[13] w	BS[12] w	BS[11] w	BS[10] w	BS[9] w	BS[8] w	BS[7] w	BS[6] w	BS[5] w	BS[4] w	BS[3] w	BS[2] w	BS[1] w	BS[0] w

Toggle fields

BS[0]

Bit 0: Set bit 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Set bit 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Set bit 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Set bit 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Set bit 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Set bit 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Set bit 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Set bit 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Set bit 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Set bit 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Set bit 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Set bit 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Set bit 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Set bit 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Set bit 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Set bit 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Reset bit 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Reset bit 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Reset bit 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Reset bit 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Reset bit 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Reset bit 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Reset bit 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Reset bit 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Reset bit 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Reset bit 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Reset bit 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Reset bit 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Reset bit 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Reset bit 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Reset bit 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Reset bit 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BRR

Port bit reset register (GPIOn_BRR)

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR[15] w	BR[14] w	BR[13] w	BR[12] w	BR[11] w	BR[10] w	BR[9] w	BR[8] w	BR[7] w	BR[6] w	BR[5] w	BR[4] w	BR[3] w	BR[2] w	BR[1] w	BR[0] w

Toggle fields

BR[0]

Bit 0: Reset bit 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Reset bit 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Reset bit 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Reset bit 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Reset bit 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Reset bit 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Reset bit 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Reset bit 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Reset bit 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Reset bit 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Reset bit 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Reset bit 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Reset bit 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Reset bit 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Reset bit 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Reset bit 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

LCKR

Port configuration lock register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK[15] rw	LCK[14] rw	LCK[13] rw	LCK[12] rw	LCK[11] rw	LCK[10] rw	LCK[9] rw	LCK[8] rw	LCK[7] rw	LCK[6] rw	LCK[5] rw	LCK[4] rw	LCK[3] rw	LCK[2] rw	LCK[1] rw	LCK[0] rw

Toggle fields

LCK[0]

Bit 0: Port A Lock bit 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port A Lock bit 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port A Lock bit 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port A Lock bit 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port A Lock bit 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port A Lock bit 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port A Lock bit 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port A Lock bit 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port A Lock bit 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port A Lock bit 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port A Lock bit 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port A Lock bit 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port A Lock bit 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port A Lock bit 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port A Lock bit 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port A Lock bit 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Lock key.

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

GPIOC

0x40011000: General purpose I/O

129/129 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CRL	CNF[7]		MODE[7]		CNF[6]		MODE[6]		CNF[5]		MODE[5]		CNF[4]		MODE[4]		CNF[3]		MODE[3]		CNF[2]		MODE[2]		CNF[1]		MODE[1]		CNF[0]		MODE[0]
0x4	CRH	CNF[15]		MODE[15]		CNF[14]		MODE[14]		CNF[13]		MODE[13]		CNF[12]		MODE[12]		CNF[11]		MODE[11]		CNF[10]		MODE[10]		CNF[9]		MODE[9]		CNF[8]		MODE[8]
0x8	IDR																	IDR[15]	IDR[14]	IDR[13]	IDR[12]	IDR[11]	IDR[10]	IDR[9]	IDR[8]	IDR[7]	IDR[6]	IDR[5]	IDR[4]	IDR[3]	IDR[2]	IDR[1]	IDR[0]
0xc	ODR																	ODR[15]	ODR[14]	ODR[13]	ODR[12]	ODR[11]	ODR[10]	ODR[9]	ODR[8]	ODR[7]	ODR[6]	ODR[5]	ODR[4]	ODR[3]	ODR[2]	ODR[1]	ODR[0]
0x10	BSRR	BR[15]	BR[14]	BR[13]	BR[12]	BR[11]	BR[10]	BR[9]	BR[8]	BR[7]	BR[6]	BR[5]	BR[4]	BR[3]	BR[2]	BR[1]	BR[0]	BS[15]	BS[14]	BS[13]	BS[12]	BS[11]	BS[10]	BS[9]	BS[8]	BS[7]	BS[6]	BS[5]	BS[4]	BS[3]	BS[2]	BS[1]	BS[0]
0x14	BRR																	BR[15]	BR[14]	BR[13]	BR[12]	BR[11]	BR[10]	BR[9]	BR[8]	BR[7]	BR[6]	BR[5]	BR[4]	BR[3]	BR[2]	BR[1]	BR[0]
0x18	LCKR																LCKK	LCK[15]	LCK[14]	LCK[13]	LCK[12]	LCK[11]	LCK[10]	LCK[9]	LCK[8]	LCK[7]	LCK[6]	LCK[5]	LCK[4]	LCK[3]	LCK[2]	LCK[1]	LCK[0]

Toggle registers

CRL

Port configuration register low (GPIOn_CRL)

Offset: 0x0, size: 32, reset: 0x44444444, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CNF[7] rw		MODE[7] rw		CNF[6] rw		MODE[6] rw		CNF[5] rw		MODE[5] rw		CNF[4] rw		MODE[4] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNF[3] rw		MODE[3] rw		CNF[2] rw		MODE[2] rw		CNF[1] rw		MODE[1] rw		CNF[0] rw		MODE[0] rw

Toggle fields

MODE[0]

Bits 0-1: Port n.0 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[0]

Bits 2-3: Port n.0 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[1]

Bits 4-5: Port n.1 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[1]

Bits 6-7: Port n.1 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[2]

Bits 8-9: Port n.2 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[2]

Bits 10-11: Port n.2 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[3]

Bits 12-13: Port n.3 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[3]

Bits 14-15: Port n.3 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[4]

Bits 16-17: Port n.4 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[4]

Bits 18-19: Port n.4 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[5]

Bits 20-21: Port n.5 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[5]

Bits 22-23: Port n.5 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[6]

Bits 24-25: Port n.6 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[6]

Bits 26-27: Port n.6 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[7]

Bits 28-29: Port n.7 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[7]

Bits 30-31: Port n.7 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

CRH

Port configuration register high (GPIOn_CRL)

Offset: 0x4, size: 32, reset: 0x44444444, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CNF[15] rw		MODE[15] rw		CNF[14] rw		MODE[14] rw		CNF[13] rw		MODE[13] rw		CNF[12] rw		MODE[12] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNF[11] rw		MODE[11] rw		CNF[10] rw		MODE[10] rw		CNF[9] rw		MODE[9] rw		CNF[8] rw		MODE[8] rw

Toggle fields

MODE[8]

Bits 0-1: Port n.8 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[8]

Bits 2-3: Port n.8 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[9]

Bits 4-5: Port n.9 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[9]

Bits 6-7: Port n.9 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[10]

Bits 8-9: Port n.10 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[10]

Bits 10-11: Port n.10 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[11]

Bits 12-13: Port n.11 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[11]

Bits 14-15: Port n.11 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[12]

Bits 16-17: Port n.12 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[12]

Bits 18-19: Port n.12 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[13]

Bits 20-21: Port n.13 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[13]

Bits 22-23: Port n.13 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[14]

Bits 24-25: Port n.14 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[14]

Bits 26-27: Port n.14 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[15]

Bits 28-29: Port n.15 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[15]

Bits 30-31: Port n.15 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

IDR

Port input data register (GPIOn_IDR)

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IDR[15] r	IDR[14] r	IDR[13] r	IDR[12] r	IDR[11] r	IDR[10] r	IDR[9] r	IDR[8] r	IDR[7] r	IDR[6] r	IDR[5] r	IDR[4] r	IDR[3] r	IDR[2] r	IDR[1] r	IDR[0] r

Toggle fields

IDR[0]

Bit 0: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

Port output data register (GPIOn_ODR)

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ODR[15] rw	ODR[14] rw	ODR[13] rw	ODR[12] rw	ODR[11] rw	ODR[10] rw	ODR[9] rw	ODR[8] rw	ODR[7] rw	ODR[6] rw	ODR[5] rw	ODR[4] rw	ODR[3] rw	ODR[2] rw	ODR[1] rw	ODR[0] rw

Toggle fields

ODR[0]

Bit 0: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

Port bit set/reset register (GPIOn_BSRR)

Offset: 0x10, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR[15] w	BR[14] w	BR[13] w	BR[12] w	BR[11] w	BR[10] w	BR[9] w	BR[8] w	BR[7] w	BR[6] w	BR[5] w	BR[4] w	BR[3] w	BR[2] w	BR[1] w	BR[0] w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS[15] w	BS[14] w	BS[13] w	BS[12] w	BS[11] w	BS[10] w	BS[9] w	BS[8] w	BS[7] w	BS[6] w	BS[5] w	BS[4] w	BS[3] w	BS[2] w	BS[1] w	BS[0] w

Toggle fields

BS[0]

Bit 0: Set bit 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Set bit 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Set bit 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Set bit 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Set bit 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Set bit 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Set bit 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Set bit 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Set bit 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Set bit 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Set bit 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Set bit 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Set bit 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Set bit 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Set bit 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Set bit 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Reset bit 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Reset bit 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Reset bit 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Reset bit 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Reset bit 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Reset bit 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Reset bit 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Reset bit 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Reset bit 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Reset bit 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Reset bit 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Reset bit 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Reset bit 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Reset bit 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Reset bit 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Reset bit 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BRR

Port bit reset register (GPIOn_BRR)

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR[15] w	BR[14] w	BR[13] w	BR[12] w	BR[11] w	BR[10] w	BR[9] w	BR[8] w	BR[7] w	BR[6] w	BR[5] w	BR[4] w	BR[3] w	BR[2] w	BR[1] w	BR[0] w

Toggle fields

BR[0]

Bit 0: Reset bit 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Reset bit 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Reset bit 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Reset bit 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Reset bit 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Reset bit 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Reset bit 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Reset bit 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Reset bit 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Reset bit 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Reset bit 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Reset bit 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Reset bit 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Reset bit 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Reset bit 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Reset bit 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

LCKR

Port configuration lock register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK[15] rw	LCK[14] rw	LCK[13] rw	LCK[12] rw	LCK[11] rw	LCK[10] rw	LCK[9] rw	LCK[8] rw	LCK[7] rw	LCK[6] rw	LCK[5] rw	LCK[4] rw	LCK[3] rw	LCK[2] rw	LCK[1] rw	LCK[0] rw

Toggle fields

LCK[0]

Bit 0: Port A Lock bit 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port A Lock bit 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port A Lock bit 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port A Lock bit 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port A Lock bit 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port A Lock bit 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port A Lock bit 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port A Lock bit 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port A Lock bit 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port A Lock bit 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port A Lock bit 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port A Lock bit 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port A Lock bit 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port A Lock bit 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port A Lock bit 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port A Lock bit 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Lock key.

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

GPIOD

0x40011400: General purpose I/O

129/129 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CRL	CNF[7]		MODE[7]		CNF[6]		MODE[6]		CNF[5]		MODE[5]		CNF[4]		MODE[4]		CNF[3]		MODE[3]		CNF[2]		MODE[2]		CNF[1]		MODE[1]		CNF[0]		MODE[0]
0x4	CRH	CNF[15]		MODE[15]		CNF[14]		MODE[14]		CNF[13]		MODE[13]		CNF[12]		MODE[12]		CNF[11]		MODE[11]		CNF[10]		MODE[10]		CNF[9]		MODE[9]		CNF[8]		MODE[8]
0x8	IDR																	IDR[15]	IDR[14]	IDR[13]	IDR[12]	IDR[11]	IDR[10]	IDR[9]	IDR[8]	IDR[7]	IDR[6]	IDR[5]	IDR[4]	IDR[3]	IDR[2]	IDR[1]	IDR[0]
0xc	ODR																	ODR[15]	ODR[14]	ODR[13]	ODR[12]	ODR[11]	ODR[10]	ODR[9]	ODR[8]	ODR[7]	ODR[6]	ODR[5]	ODR[4]	ODR[3]	ODR[2]	ODR[1]	ODR[0]
0x10	BSRR	BR[15]	BR[14]	BR[13]	BR[12]	BR[11]	BR[10]	BR[9]	BR[8]	BR[7]	BR[6]	BR[5]	BR[4]	BR[3]	BR[2]	BR[1]	BR[0]	BS[15]	BS[14]	BS[13]	BS[12]	BS[11]	BS[10]	BS[9]	BS[8]	BS[7]	BS[6]	BS[5]	BS[4]	BS[3]	BS[2]	BS[1]	BS[0]
0x14	BRR																	BR[15]	BR[14]	BR[13]	BR[12]	BR[11]	BR[10]	BR[9]	BR[8]	BR[7]	BR[6]	BR[5]	BR[4]	BR[3]	BR[2]	BR[1]	BR[0]
0x18	LCKR																LCKK	LCK[15]	LCK[14]	LCK[13]	LCK[12]	LCK[11]	LCK[10]	LCK[9]	LCK[8]	LCK[7]	LCK[6]	LCK[5]	LCK[4]	LCK[3]	LCK[2]	LCK[1]	LCK[0]

Toggle registers

CRL

Port configuration register low (GPIOn_CRL)

Offset: 0x0, size: 32, reset: 0x44444444, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CNF[7] rw		MODE[7] rw		CNF[6] rw		MODE[6] rw		CNF[5] rw		MODE[5] rw		CNF[4] rw		MODE[4] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNF[3] rw		MODE[3] rw		CNF[2] rw		MODE[2] rw		CNF[1] rw		MODE[1] rw		CNF[0] rw		MODE[0] rw

Toggle fields

MODE[0]

Bits 0-1: Port n.0 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[0]

Bits 2-3: Port n.0 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[1]

Bits 4-5: Port n.1 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[1]

Bits 6-7: Port n.1 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[2]

Bits 8-9: Port n.2 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[2]

Bits 10-11: Port n.2 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[3]

Bits 12-13: Port n.3 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[3]

Bits 14-15: Port n.3 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[4]

Bits 16-17: Port n.4 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[4]

Bits 18-19: Port n.4 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[5]

Bits 20-21: Port n.5 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[5]

Bits 22-23: Port n.5 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[6]

Bits 24-25: Port n.6 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[6]

Bits 26-27: Port n.6 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[7]

Bits 28-29: Port n.7 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[7]

Bits 30-31: Port n.7 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

CRH

Port configuration register high (GPIOn_CRL)

Offset: 0x4, size: 32, reset: 0x44444444, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CNF[15] rw		MODE[15] rw		CNF[14] rw		MODE[14] rw		CNF[13] rw		MODE[13] rw		CNF[12] rw		MODE[12] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNF[11] rw		MODE[11] rw		CNF[10] rw		MODE[10] rw		CNF[9] rw		MODE[9] rw		CNF[8] rw		MODE[8] rw

Toggle fields

MODE[8]

Bits 0-1: Port n.8 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[8]

Bits 2-3: Port n.8 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[9]

Bits 4-5: Port n.9 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[9]

Bits 6-7: Port n.9 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[10]

Bits 8-9: Port n.10 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[10]

Bits 10-11: Port n.10 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[11]

Bits 12-13: Port n.11 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[11]

Bits 14-15: Port n.11 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[12]

Bits 16-17: Port n.12 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[12]

Bits 18-19: Port n.12 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[13]

Bits 20-21: Port n.13 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[13]

Bits 22-23: Port n.13 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[14]

Bits 24-25: Port n.14 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[14]

Bits 26-27: Port n.14 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[15]

Bits 28-29: Port n.15 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[15]

Bits 30-31: Port n.15 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

IDR

Port input data register (GPIOn_IDR)

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IDR[15] r	IDR[14] r	IDR[13] r	IDR[12] r	IDR[11] r	IDR[10] r	IDR[9] r	IDR[8] r	IDR[7] r	IDR[6] r	IDR[5] r	IDR[4] r	IDR[3] r	IDR[2] r	IDR[1] r	IDR[0] r

Toggle fields

IDR[0]

Bit 0: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

Port output data register (GPIOn_ODR)

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ODR[15] rw	ODR[14] rw	ODR[13] rw	ODR[12] rw	ODR[11] rw	ODR[10] rw	ODR[9] rw	ODR[8] rw	ODR[7] rw	ODR[6] rw	ODR[5] rw	ODR[4] rw	ODR[3] rw	ODR[2] rw	ODR[1] rw	ODR[0] rw

Toggle fields

ODR[0]

Bit 0: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

Port bit set/reset register (GPIOn_BSRR)

Offset: 0x10, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR[15] w	BR[14] w	BR[13] w	BR[12] w	BR[11] w	BR[10] w	BR[9] w	BR[8] w	BR[7] w	BR[6] w	BR[5] w	BR[4] w	BR[3] w	BR[2] w	BR[1] w	BR[0] w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS[15] w	BS[14] w	BS[13] w	BS[12] w	BS[11] w	BS[10] w	BS[9] w	BS[8] w	BS[7] w	BS[6] w	BS[5] w	BS[4] w	BS[3] w	BS[2] w	BS[1] w	BS[0] w

Toggle fields

BS[0]

Bit 0: Set bit 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Set bit 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Set bit 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Set bit 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Set bit 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Set bit 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Set bit 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Set bit 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Set bit 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Set bit 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Set bit 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Set bit 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Set bit 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Set bit 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Set bit 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Set bit 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Reset bit 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Reset bit 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Reset bit 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Reset bit 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Reset bit 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Reset bit 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Reset bit 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Reset bit 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Reset bit 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Reset bit 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Reset bit 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Reset bit 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Reset bit 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Reset bit 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Reset bit 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Reset bit 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BRR

Port bit reset register (GPIOn_BRR)

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR[15] w	BR[14] w	BR[13] w	BR[12] w	BR[11] w	BR[10] w	BR[9] w	BR[8] w	BR[7] w	BR[6] w	BR[5] w	BR[4] w	BR[3] w	BR[2] w	BR[1] w	BR[0] w

Toggle fields

BR[0]

Bit 0: Reset bit 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Reset bit 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Reset bit 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Reset bit 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Reset bit 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Reset bit 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Reset bit 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Reset bit 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Reset bit 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Reset bit 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Reset bit 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Reset bit 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Reset bit 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Reset bit 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Reset bit 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Reset bit 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

LCKR

Port configuration lock register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK[15] rw	LCK[14] rw	LCK[13] rw	LCK[12] rw	LCK[11] rw	LCK[10] rw	LCK[9] rw	LCK[8] rw	LCK[7] rw	LCK[6] rw	LCK[5] rw	LCK[4] rw	LCK[3] rw	LCK[2] rw	LCK[1] rw	LCK[0] rw

Toggle fields

LCK[0]

Bit 0: Port A Lock bit 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port A Lock bit 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port A Lock bit 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port A Lock bit 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port A Lock bit 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port A Lock bit 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port A Lock bit 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port A Lock bit 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port A Lock bit 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port A Lock bit 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port A Lock bit 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port A Lock bit 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port A Lock bit 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port A Lock bit 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port A Lock bit 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port A Lock bit 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Lock key.

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

GPIOE

0x40011800: General purpose I/O

129/129 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CRL	CNF[7]		MODE[7]		CNF[6]		MODE[6]		CNF[5]		MODE[5]		CNF[4]		MODE[4]		CNF[3]		MODE[3]		CNF[2]		MODE[2]		CNF[1]		MODE[1]		CNF[0]		MODE[0]
0x4	CRH	CNF[15]		MODE[15]		CNF[14]		MODE[14]		CNF[13]		MODE[13]		CNF[12]		MODE[12]		CNF[11]		MODE[11]		CNF[10]		MODE[10]		CNF[9]		MODE[9]		CNF[8]		MODE[8]
0x8	IDR																	IDR[15]	IDR[14]	IDR[13]	IDR[12]	IDR[11]	IDR[10]	IDR[9]	IDR[8]	IDR[7]	IDR[6]	IDR[5]	IDR[4]	IDR[3]	IDR[2]	IDR[1]	IDR[0]
0xc	ODR																	ODR[15]	ODR[14]	ODR[13]	ODR[12]	ODR[11]	ODR[10]	ODR[9]	ODR[8]	ODR[7]	ODR[6]	ODR[5]	ODR[4]	ODR[3]	ODR[2]	ODR[1]	ODR[0]
0x10	BSRR	BR[15]	BR[14]	BR[13]	BR[12]	BR[11]	BR[10]	BR[9]	BR[8]	BR[7]	BR[6]	BR[5]	BR[4]	BR[3]	BR[2]	BR[1]	BR[0]	BS[15]	BS[14]	BS[13]	BS[12]	BS[11]	BS[10]	BS[9]	BS[8]	BS[7]	BS[6]	BS[5]	BS[4]	BS[3]	BS[2]	BS[1]	BS[0]
0x14	BRR																	BR[15]	BR[14]	BR[13]	BR[12]	BR[11]	BR[10]	BR[9]	BR[8]	BR[7]	BR[6]	BR[5]	BR[4]	BR[3]	BR[2]	BR[1]	BR[0]
0x18	LCKR																LCKK	LCK[15]	LCK[14]	LCK[13]	LCK[12]	LCK[11]	LCK[10]	LCK[9]	LCK[8]	LCK[7]	LCK[6]	LCK[5]	LCK[4]	LCK[3]	LCK[2]	LCK[1]	LCK[0]

Toggle registers

CRL

Port configuration register low (GPIOn_CRL)

Offset: 0x0, size: 32, reset: 0x44444444, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CNF[7] rw		MODE[7] rw		CNF[6] rw		MODE[6] rw		CNF[5] rw		MODE[5] rw		CNF[4] rw		MODE[4] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNF[3] rw		MODE[3] rw		CNF[2] rw		MODE[2] rw		CNF[1] rw		MODE[1] rw		CNF[0] rw		MODE[0] rw

Toggle fields

MODE[0]

Bits 0-1: Port n.0 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[0]

Bits 2-3: Port n.0 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[1]

Bits 4-5: Port n.1 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[1]

Bits 6-7: Port n.1 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[2]

Bits 8-9: Port n.2 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[2]

Bits 10-11: Port n.2 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[3]

Bits 12-13: Port n.3 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[3]

Bits 14-15: Port n.3 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[4]

Bits 16-17: Port n.4 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[4]

Bits 18-19: Port n.4 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[5]

Bits 20-21: Port n.5 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[5]

Bits 22-23: Port n.5 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[6]

Bits 24-25: Port n.6 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[6]

Bits 26-27: Port n.6 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[7]

Bits 28-29: Port n.7 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[7]

Bits 30-31: Port n.7 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

CRH

Port configuration register high (GPIOn_CRL)

Offset: 0x4, size: 32, reset: 0x44444444, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CNF[15] rw		MODE[15] rw		CNF[14] rw		MODE[14] rw		CNF[13] rw		MODE[13] rw		CNF[12] rw		MODE[12] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNF[11] rw		MODE[11] rw		CNF[10] rw		MODE[10] rw		CNF[9] rw		MODE[9] rw		CNF[8] rw		MODE[8] rw

Toggle fields

MODE[8]

Bits 0-1: Port n.8 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[8]

Bits 2-3: Port n.8 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[9]

Bits 4-5: Port n.9 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[9]

Bits 6-7: Port n.9 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[10]

Bits 8-9: Port n.10 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[10]

Bits 10-11: Port n.10 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[11]

Bits 12-13: Port n.11 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[11]

Bits 14-15: Port n.11 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[12]

Bits 16-17: Port n.12 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[12]

Bits 18-19: Port n.12 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[13]

Bits 20-21: Port n.13 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[13]

Bits 22-23: Port n.13 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[14]

Bits 24-25: Port n.14 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[14]

Bits 26-27: Port n.14 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[15]

Bits 28-29: Port n.15 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[15]

Bits 30-31: Port n.15 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

IDR

Port input data register (GPIOn_IDR)

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IDR[15] r	IDR[14] r	IDR[13] r	IDR[12] r	IDR[11] r	IDR[10] r	IDR[9] r	IDR[8] r	IDR[7] r	IDR[6] r	IDR[5] r	IDR[4] r	IDR[3] r	IDR[2] r	IDR[1] r	IDR[0] r

Toggle fields

IDR[0]

Bit 0: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

Port output data register (GPIOn_ODR)

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ODR[15] rw	ODR[14] rw	ODR[13] rw	ODR[12] rw	ODR[11] rw	ODR[10] rw	ODR[9] rw	ODR[8] rw	ODR[7] rw	ODR[6] rw	ODR[5] rw	ODR[4] rw	ODR[3] rw	ODR[2] rw	ODR[1] rw	ODR[0] rw

Toggle fields

ODR[0]

Bit 0: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

Port bit set/reset register (GPIOn_BSRR)

Offset: 0x10, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR[15] w	BR[14] w	BR[13] w	BR[12] w	BR[11] w	BR[10] w	BR[9] w	BR[8] w	BR[7] w	BR[6] w	BR[5] w	BR[4] w	BR[3] w	BR[2] w	BR[1] w	BR[0] w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS[15] w	BS[14] w	BS[13] w	BS[12] w	BS[11] w	BS[10] w	BS[9] w	BS[8] w	BS[7] w	BS[6] w	BS[5] w	BS[4] w	BS[3] w	BS[2] w	BS[1] w	BS[0] w

Toggle fields

BS[0]

Bit 0: Set bit 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Set bit 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Set bit 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Set bit 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Set bit 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Set bit 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Set bit 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Set bit 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Set bit 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Set bit 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Set bit 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Set bit 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Set bit 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Set bit 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Set bit 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Set bit 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Reset bit 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Reset bit 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Reset bit 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Reset bit 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Reset bit 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Reset bit 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Reset bit 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Reset bit 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Reset bit 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Reset bit 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Reset bit 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Reset bit 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Reset bit 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Reset bit 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Reset bit 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Reset bit 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BRR

Port bit reset register (GPIOn_BRR)

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR[15] w	BR[14] w	BR[13] w	BR[12] w	BR[11] w	BR[10] w	BR[9] w	BR[8] w	BR[7] w	BR[6] w	BR[5] w	BR[4] w	BR[3] w	BR[2] w	BR[1] w	BR[0] w

Toggle fields

BR[0]

Bit 0: Reset bit 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Reset bit 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Reset bit 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Reset bit 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Reset bit 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Reset bit 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Reset bit 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Reset bit 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Reset bit 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Reset bit 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Reset bit 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Reset bit 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Reset bit 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Reset bit 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Reset bit 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Reset bit 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

LCKR

Port configuration lock register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK[15] rw	LCK[14] rw	LCK[13] rw	LCK[12] rw	LCK[11] rw	LCK[10] rw	LCK[9] rw	LCK[8] rw	LCK[7] rw	LCK[6] rw	LCK[5] rw	LCK[4] rw	LCK[3] rw	LCK[2] rw	LCK[1] rw	LCK[0] rw

Toggle fields

LCK[0]

Bit 0: Port A Lock bit 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port A Lock bit 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port A Lock bit 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port A Lock bit 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port A Lock bit 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port A Lock bit 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port A Lock bit 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port A Lock bit 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port A Lock bit 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port A Lock bit 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port A Lock bit 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port A Lock bit 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port A Lock bit 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port A Lock bit 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port A Lock bit 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port A Lock bit 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Lock key.

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

GPIOF

0x40011c00: General purpose I/O

129/129 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CRL	CNF[7]		MODE[7]		CNF[6]		MODE[6]		CNF[5]		MODE[5]		CNF[4]		MODE[4]		CNF[3]		MODE[3]		CNF[2]		MODE[2]		CNF[1]		MODE[1]		CNF[0]		MODE[0]
0x4	CRH	CNF[15]		MODE[15]		CNF[14]		MODE[14]		CNF[13]		MODE[13]		CNF[12]		MODE[12]		CNF[11]		MODE[11]		CNF[10]		MODE[10]		CNF[9]		MODE[9]		CNF[8]		MODE[8]
0x8	IDR																	IDR[15]	IDR[14]	IDR[13]	IDR[12]	IDR[11]	IDR[10]	IDR[9]	IDR[8]	IDR[7]	IDR[6]	IDR[5]	IDR[4]	IDR[3]	IDR[2]	IDR[1]	IDR[0]
0xc	ODR																	ODR[15]	ODR[14]	ODR[13]	ODR[12]	ODR[11]	ODR[10]	ODR[9]	ODR[8]	ODR[7]	ODR[6]	ODR[5]	ODR[4]	ODR[3]	ODR[2]	ODR[1]	ODR[0]
0x10	BSRR	BR[15]	BR[14]	BR[13]	BR[12]	BR[11]	BR[10]	BR[9]	BR[8]	BR[7]	BR[6]	BR[5]	BR[4]	BR[3]	BR[2]	BR[1]	BR[0]	BS[15]	BS[14]	BS[13]	BS[12]	BS[11]	BS[10]	BS[9]	BS[8]	BS[7]	BS[6]	BS[5]	BS[4]	BS[3]	BS[2]	BS[1]	BS[0]
0x14	BRR																	BR[15]	BR[14]	BR[13]	BR[12]	BR[11]	BR[10]	BR[9]	BR[8]	BR[7]	BR[6]	BR[5]	BR[4]	BR[3]	BR[2]	BR[1]	BR[0]
0x18	LCKR																LCKK	LCK[15]	LCK[14]	LCK[13]	LCK[12]	LCK[11]	LCK[10]	LCK[9]	LCK[8]	LCK[7]	LCK[6]	LCK[5]	LCK[4]	LCK[3]	LCK[2]	LCK[1]	LCK[0]

Toggle registers

CRL

Port configuration register low (GPIOn_CRL)

Offset: 0x0, size: 32, reset: 0x44444444, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CNF[7] rw		MODE[7] rw		CNF[6] rw		MODE[6] rw		CNF[5] rw		MODE[5] rw		CNF[4] rw		MODE[4] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNF[3] rw		MODE[3] rw		CNF[2] rw		MODE[2] rw		CNF[1] rw		MODE[1] rw		CNF[0] rw		MODE[0] rw

Toggle fields

MODE[0]

Bits 0-1: Port n.0 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[0]

Bits 2-3: Port n.0 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[1]

Bits 4-5: Port n.1 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[1]

Bits 6-7: Port n.1 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[2]

Bits 8-9: Port n.2 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[2]

Bits 10-11: Port n.2 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[3]

Bits 12-13: Port n.3 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[3]

Bits 14-15: Port n.3 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[4]

Bits 16-17: Port n.4 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[4]

Bits 18-19: Port n.4 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[5]

Bits 20-21: Port n.5 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[5]

Bits 22-23: Port n.5 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[6]

Bits 24-25: Port n.6 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[6]

Bits 26-27: Port n.6 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[7]

Bits 28-29: Port n.7 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[7]

Bits 30-31: Port n.7 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

CRH

Port configuration register high (GPIOn_CRL)

Offset: 0x4, size: 32, reset: 0x44444444, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CNF[15] rw		MODE[15] rw		CNF[14] rw		MODE[14] rw		CNF[13] rw		MODE[13] rw		CNF[12] rw		MODE[12] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNF[11] rw		MODE[11] rw		CNF[10] rw		MODE[10] rw		CNF[9] rw		MODE[9] rw		CNF[8] rw		MODE[8] rw

Toggle fields

MODE[8]

Bits 0-1: Port n.8 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[8]

Bits 2-3: Port n.8 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[9]

Bits 4-5: Port n.9 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[9]

Bits 6-7: Port n.9 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[10]

Bits 8-9: Port n.10 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[10]

Bits 10-11: Port n.10 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[11]

Bits 12-13: Port n.11 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[11]

Bits 14-15: Port n.11 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[12]

Bits 16-17: Port n.12 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[12]

Bits 18-19: Port n.12 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[13]

Bits 20-21: Port n.13 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[13]

Bits 22-23: Port n.13 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[14]

Bits 24-25: Port n.14 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[14]

Bits 26-27: Port n.14 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[15]

Bits 28-29: Port n.15 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[15]

Bits 30-31: Port n.15 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

IDR

Port input data register (GPIOn_IDR)

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IDR[15] r	IDR[14] r	IDR[13] r	IDR[12] r	IDR[11] r	IDR[10] r	IDR[9] r	IDR[8] r	IDR[7] r	IDR[6] r	IDR[5] r	IDR[4] r	IDR[3] r	IDR[2] r	IDR[1] r	IDR[0] r

Toggle fields

IDR[0]

Bit 0: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

Port output data register (GPIOn_ODR)

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ODR[15] rw	ODR[14] rw	ODR[13] rw	ODR[12] rw	ODR[11] rw	ODR[10] rw	ODR[9] rw	ODR[8] rw	ODR[7] rw	ODR[6] rw	ODR[5] rw	ODR[4] rw	ODR[3] rw	ODR[2] rw	ODR[1] rw	ODR[0] rw

Toggle fields

ODR[0]

Bit 0: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

Port bit set/reset register (GPIOn_BSRR)

Offset: 0x10, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR[15] w	BR[14] w	BR[13] w	BR[12] w	BR[11] w	BR[10] w	BR[9] w	BR[8] w	BR[7] w	BR[6] w	BR[5] w	BR[4] w	BR[3] w	BR[2] w	BR[1] w	BR[0] w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS[15] w	BS[14] w	BS[13] w	BS[12] w	BS[11] w	BS[10] w	BS[9] w	BS[8] w	BS[7] w	BS[6] w	BS[5] w	BS[4] w	BS[3] w	BS[2] w	BS[1] w	BS[0] w

Toggle fields

BS[0]

Bit 0: Set bit 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Set bit 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Set bit 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Set bit 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Set bit 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Set bit 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Set bit 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Set bit 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Set bit 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Set bit 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Set bit 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Set bit 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Set bit 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Set bit 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Set bit 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Set bit 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Reset bit 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Reset bit 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Reset bit 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Reset bit 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Reset bit 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Reset bit 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Reset bit 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Reset bit 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Reset bit 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Reset bit 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Reset bit 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Reset bit 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Reset bit 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Reset bit 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Reset bit 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Reset bit 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BRR

Port bit reset register (GPIOn_BRR)

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR[15] w	BR[14] w	BR[13] w	BR[12] w	BR[11] w	BR[10] w	BR[9] w	BR[8] w	BR[7] w	BR[6] w	BR[5] w	BR[4] w	BR[3] w	BR[2] w	BR[1] w	BR[0] w

Toggle fields

BR[0]

Bit 0: Reset bit 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Reset bit 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Reset bit 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Reset bit 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Reset bit 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Reset bit 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Reset bit 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Reset bit 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Reset bit 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Reset bit 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Reset bit 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Reset bit 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Reset bit 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Reset bit 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Reset bit 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Reset bit 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

LCKR

Port configuration lock register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK[15] rw	LCK[14] rw	LCK[13] rw	LCK[12] rw	LCK[11] rw	LCK[10] rw	LCK[9] rw	LCK[8] rw	LCK[7] rw	LCK[6] rw	LCK[5] rw	LCK[4] rw	LCK[3] rw	LCK[2] rw	LCK[1] rw	LCK[0] rw

Toggle fields

LCK[0]

Bit 0: Port A Lock bit 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port A Lock bit 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port A Lock bit 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port A Lock bit 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port A Lock bit 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port A Lock bit 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port A Lock bit 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port A Lock bit 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port A Lock bit 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port A Lock bit 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port A Lock bit 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port A Lock bit 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port A Lock bit 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port A Lock bit 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port A Lock bit 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port A Lock bit 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Lock key.

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

GPIOG

0x40012000: General purpose I/O

129/129 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CRL	CNF[7]		MODE[7]		CNF[6]		MODE[6]		CNF[5]		MODE[5]		CNF[4]		MODE[4]		CNF[3]		MODE[3]		CNF[2]		MODE[2]		CNF[1]		MODE[1]		CNF[0]		MODE[0]
0x4	CRH	CNF[15]		MODE[15]		CNF[14]		MODE[14]		CNF[13]		MODE[13]		CNF[12]		MODE[12]		CNF[11]		MODE[11]		CNF[10]		MODE[10]		CNF[9]		MODE[9]		CNF[8]		MODE[8]
0x8	IDR																	IDR[15]	IDR[14]	IDR[13]	IDR[12]	IDR[11]	IDR[10]	IDR[9]	IDR[8]	IDR[7]	IDR[6]	IDR[5]	IDR[4]	IDR[3]	IDR[2]	IDR[1]	IDR[0]
0xc	ODR																	ODR[15]	ODR[14]	ODR[13]	ODR[12]	ODR[11]	ODR[10]	ODR[9]	ODR[8]	ODR[7]	ODR[6]	ODR[5]	ODR[4]	ODR[3]	ODR[2]	ODR[1]	ODR[0]
0x10	BSRR	BR[15]	BR[14]	BR[13]	BR[12]	BR[11]	BR[10]	BR[9]	BR[8]	BR[7]	BR[6]	BR[5]	BR[4]	BR[3]	BR[2]	BR[1]	BR[0]	BS[15]	BS[14]	BS[13]	BS[12]	BS[11]	BS[10]	BS[9]	BS[8]	BS[7]	BS[6]	BS[5]	BS[4]	BS[3]	BS[2]	BS[1]	BS[0]
0x14	BRR																	BR[15]	BR[14]	BR[13]	BR[12]	BR[11]	BR[10]	BR[9]	BR[8]	BR[7]	BR[6]	BR[5]	BR[4]	BR[3]	BR[2]	BR[1]	BR[0]
0x18	LCKR																LCKK	LCK[15]	LCK[14]	LCK[13]	LCK[12]	LCK[11]	LCK[10]	LCK[9]	LCK[8]	LCK[7]	LCK[6]	LCK[5]	LCK[4]	LCK[3]	LCK[2]	LCK[1]	LCK[0]

Toggle registers

CRL

Port configuration register low (GPIOn_CRL)

Offset: 0x0, size: 32, reset: 0x44444444, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CNF[7] rw		MODE[7] rw		CNF[6] rw		MODE[6] rw		CNF[5] rw		MODE[5] rw		CNF[4] rw		MODE[4] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNF[3] rw		MODE[3] rw		CNF[2] rw		MODE[2] rw		CNF[1] rw		MODE[1] rw		CNF[0] rw		MODE[0] rw

Toggle fields

MODE[0]

Bits 0-1: Port n.0 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[0]

Bits 2-3: Port n.0 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[1]

Bits 4-5: Port n.1 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[1]

Bits 6-7: Port n.1 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[2]

Bits 8-9: Port n.2 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[2]

Bits 10-11: Port n.2 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[3]

Bits 12-13: Port n.3 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[3]

Bits 14-15: Port n.3 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[4]

Bits 16-17: Port n.4 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[4]

Bits 18-19: Port n.4 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[5]

Bits 20-21: Port n.5 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[5]

Bits 22-23: Port n.5 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[6]

Bits 24-25: Port n.6 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[6]

Bits 26-27: Port n.6 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[7]

Bits 28-29: Port n.7 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[7]

Bits 30-31: Port n.7 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

CRH

Port configuration register high (GPIOn_CRL)

Offset: 0x4, size: 32, reset: 0x44444444, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CNF[15] rw		MODE[15] rw		CNF[14] rw		MODE[14] rw		CNF[13] rw		MODE[13] rw		CNF[12] rw		MODE[12] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNF[11] rw		MODE[11] rw		CNF[10] rw		MODE[10] rw		CNF[9] rw		MODE[9] rw		CNF[8] rw		MODE[8] rw

Toggle fields

MODE[8]

Bits 0-1: Port n.8 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[8]

Bits 2-3: Port n.8 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[9]

Bits 4-5: Port n.9 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[9]

Bits 6-7: Port n.9 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[10]

Bits 8-9: Port n.10 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[10]

Bits 10-11: Port n.10 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[11]

Bits 12-13: Port n.11 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[11]

Bits 14-15: Port n.11 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[12]

Bits 16-17: Port n.12 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[12]

Bits 18-19: Port n.12 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[13]

Bits 20-21: Port n.13 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[13]

Bits 22-23: Port n.13 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[14]

Bits 24-25: Port n.14 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[14]

Bits 26-27: Port n.14 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

MODE[15]

Bits 28-29: Port n.15 mode bits.

Allowed values:
0: Input: Input mode (reset state)
1: Output: Output mode 10 MHz
2: Output2: Output mode 2 MHz
3: Output50: Output mode 50 MHz

CNF[15]

Bits 30-31: Port n.15 configuration bits.

Allowed values:
0: PushPull: Analog mode / Push-Pull mode
1: OpenDrain: Floating input (reset state) / Open Drain-Mode
2: AltPushPull: Input with pull-up/pull-down / Alternate Function Push-Pull Mode
3: AltOpenDrain: Alternate Function Open-Drain Mode

IDR

Port input data register (GPIOn_IDR)

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IDR[15] r	IDR[14] r	IDR[13] r	IDR[12] r	IDR[11] r	IDR[10] r	IDR[9] r	IDR[8] r	IDR[7] r	IDR[6] r	IDR[5] r	IDR[4] r	IDR[3] r	IDR[2] r	IDR[1] r	IDR[0] r

Toggle fields

IDR[0]

Bit 0: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

Port output data register (GPIOn_ODR)

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ODR[15] rw	ODR[14] rw	ODR[13] rw	ODR[12] rw	ODR[11] rw	ODR[10] rw	ODR[9] rw	ODR[8] rw	ODR[7] rw	ODR[6] rw	ODR[5] rw	ODR[4] rw	ODR[3] rw	ODR[2] rw	ODR[1] rw	ODR[0] rw

Toggle fields

ODR[0]

Bit 0: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

Port bit set/reset register (GPIOn_BSRR)

Offset: 0x10, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR[15] w	BR[14] w	BR[13] w	BR[12] w	BR[11] w	BR[10] w	BR[9] w	BR[8] w	BR[7] w	BR[6] w	BR[5] w	BR[4] w	BR[3] w	BR[2] w	BR[1] w	BR[0] w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS[15] w	BS[14] w	BS[13] w	BS[12] w	BS[11] w	BS[10] w	BS[9] w	BS[8] w	BS[7] w	BS[6] w	BS[5] w	BS[4] w	BS[3] w	BS[2] w	BS[1] w	BS[0] w

Toggle fields

BS[0]

Bit 0: Set bit 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Set bit 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Set bit 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Set bit 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Set bit 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Set bit 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Set bit 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Set bit 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Set bit 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Set bit 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Set bit 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Set bit 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Set bit 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Set bit 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Set bit 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Set bit 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Reset bit 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Reset bit 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Reset bit 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Reset bit 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Reset bit 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Reset bit 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Reset bit 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Reset bit 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Reset bit 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Reset bit 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Reset bit 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Reset bit 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Reset bit 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Reset bit 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Reset bit 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Reset bit 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BRR

Port bit reset register (GPIOn_BRR)

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR[15] w	BR[14] w	BR[13] w	BR[12] w	BR[11] w	BR[10] w	BR[9] w	BR[8] w	BR[7] w	BR[6] w	BR[5] w	BR[4] w	BR[3] w	BR[2] w	BR[1] w	BR[0] w

Toggle fields

BR[0]

Bit 0: Reset bit 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Reset bit 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Reset bit 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Reset bit 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Reset bit 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Reset bit 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Reset bit 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Reset bit 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Reset bit 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Reset bit 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Reset bit 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Reset bit 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Reset bit 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Reset bit 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Reset bit 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Reset bit 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

LCKR

Port configuration lock register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK[15] rw	LCK[14] rw	LCK[13] rw	LCK[12] rw	LCK[11] rw	LCK[10] rw	LCK[9] rw	LCK[8] rw	LCK[7] rw	LCK[6] rw	LCK[5] rw	LCK[4] rw	LCK[3] rw	LCK[2] rw	LCK[1] rw	LCK[0] rw

Toggle fields

LCK[0]

Bit 0: Port A Lock bit 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port A Lock bit 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port A Lock bit 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port A Lock bit 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port A Lock bit 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port A Lock bit 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port A Lock bit 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port A Lock bit 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port A Lock bit 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port A Lock bit 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port A Lock bit 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port A Lock bit 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port A Lock bit 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port A Lock bit 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port A Lock bit 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port A Lock bit 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Lock key.

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

I2C1

0x40005400: Inter integrated circuit

51/51 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1	SWRST		ALERT	PEC	POS	ACK	STOP	START	NOSTRETCH	ENGC	ENPEC	ENARP	SMBTYPE		SMBUS	PE
0x4	CR2				LAST	DMAEN	ITBUFEN	ITEVTEN	ITERREN			FREQ
0x8	OAR1	ADDMODE						ADD
0xc	OAR2									ADD2							ENDUAL
0x10	DR									DR
0x14	SR1	SMBALERT	TIMEOUT		PECERR	OVR	AF	ARLO	BERR	TxE	RxNE		STOPF	ADD10	BTF	ADDR	SB
0x18	SR2	PEC								DUALF	SMBHOST	SMBDEFAULT	GENCALL		TRA	BUSY	MSL
0x1c	CCR	F_S	DUTY			CCR
0x20	TRISE											TRISE

Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWRST rw		ALERT rw	PEC rw	POS rw	ACK rw	STOP rw	START rw	NOSTRETCH rw	ENGC rw	ENPEC rw	ENARP rw	SMBTYPE rw		SMBUS rw	PE rw

Toggle fields

PE

Bit 0: Peripheral enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

SMBUS

Bit 1: SMBus mode.

Allowed values:
0: I2C: I2C Mode
1: SMBus: SMBus

SMBTYPE

Bit 3: SMBus type.

Allowed values:
0: Device: SMBus Device
1: Host: SMBus Host

ENARP

Bit 4: ARP enable.

Allowed values:
0: Disabled: ARP disabled
1: Enabled: ARP enabled

ENPEC

Bit 5: PEC enable.

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

ENGC

Bit 6: General call enable.

Allowed values:
0: Disabled: General call disabled
1: Enabled: General call enabled

NOSTRETCH

Bit 7: Clock stretching disable (Slave mode).

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

START

Bit 8: Start generation.

Allowed values:
0: NoStart: No Start generation
1: Start: In master mode: repeated start generation, in slave mode: start generation when bus is free

STOP

Bit 9: Stop generation.

Allowed values:
0: NoStop: No Stop generation
1: Stop: In master mode: stop generation after current byte/start, in slave mode: release SCL and SDA after current byte

ACK

Bit 10: Acknowledge enable.

Allowed values:
0: NAK: No acknowledge returned
1: ACK: Acknowledge returned after a byte is received

POS

Bit 11: Acknowledge/PEC Position (for data reception).

Allowed values:
0: Current: ACK bit controls the (N)ACK of the current byte being received
1: Next: ACK bit controls the (N)ACK of the next byte to be received

PEC

Bit 12: Packet error checking.

Allowed values:
0: Disabled: No PEC transfer
1: Enabled: PEC transfer

ALERT

Bit 13: SMBus alert.

Allowed values:
0: Release: SMBA pin released high
1: Drive: SMBA pin driven low

SWRST

Bit 15: Software reset.

Allowed values:
0: NotReset: I2C peripheral not under reset
1: Reset: I2C peripheral under reset

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			LAST rw	DMAEN rw	ITBUFEN rw	ITEVTEN rw	ITERREN rw			FREQ rw

Toggle fields

FREQ

Bits 0-5: Peripheral clock frequency.

Allowed values: 0x2-0x32

ITERREN

Bit 8: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

ITEVTEN

Bit 9: Event interrupt enable.

Allowed values:
0: Disabled: Event interrupt disabled
1: Enabled: Event interrupt enabled

ITBUFEN

Bit 10: Buffer interrupt enable.

Allowed values:
0: Disabled: TxE=1 or RxNE=1 does not generate any interrupt
1: Enabled: TxE=1 or RxNE=1 generates Event interrupt

DMAEN

Bit 11: DMA requests enable.

Allowed values:
0: Disabled: DMA requests disabled
1: Enabled: DMA request enabled when TxE=1 or RxNE=1

LAST

Bit 12: DMA last transfer.

Allowed values:
0: NotLast: Next DMA EOT is not the last transfer
1: Last: Next DMA EOT is the last transfer

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDMODE rw						ADD rw

Toggle fields

ADD

Bits 0-9: Interface address.

Allowed values: 0x0-0x3ff

ADDMODE

Bit 15: Addressing mode (slave mode).

Allowed values:
0: ADD7: 7-bit slave address
1: ADD10: 10-bit slave address

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								ADD2 rw							ENDUAL rw

Toggle fields

ENDUAL

Bit 0: Dual addressing mode enable.

Allowed values:
0: Single: Single addressing mode
1: Dual: Dual addressing mode

ADD2

Bits 1-7: Interface address.

Allowed values: 0x0-0x7f

DR

Data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								DR rw

Toggle fields

DR

Bits 0-7: 8-bit data register.

Allowed values: 0x0-0xff

SR1

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

14/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SMBALERT rw	TIMEOUT rw		PECERR rw	OVR rw	AF rw	ARLO rw	BERR rw	TxE r	RxNE r		STOPF r	ADD10 r	BTF r	ADDR r	SB r

Toggle fields

SB

Bit 0: Start bit (Master mode).

Allowed values:
0: NoStart: No Start condition
1: Start: Start condition generated

ADDR

Bit 1: Address sent (master mode)/matched (slave mode).

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

BTF

Bit 2: Byte transfer finished.

Allowed values:
0: NotFinished: Data byte transfer not done
1: Finished: Data byte transfer successful

ADD10

Bit 3: 10-bit header sent (Master mode).

STOPF

Bit 4: Stop detection (slave mode).

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

RxNE

Bit 6: Data register not empty (receivers).

Allowed values:
0: Empty: Data register empty
1: NotEmpty: Data register not empty

TxE

Bit 7: Data register empty (transmitters).

Allowed values:
0: NotEmpty: Data register not empty
1: Empty: Data register empty

BERR

Bit 8: Bus error.

Allowed values:
0: NoError: No misplaced Start or Stop condition
1: Error: Misplaced Start or Stop condition

ARLO

Bit 9: Arbitration lost (master mode).

Allowed values:
0: NoLost: No Arbitration Lost detected
1: Lost: Arbitration Lost detected

AF

Bit 10: Acknowledge failure.

Allowed values:
0: NoFailure: No acknowledge failure
1: Failure: Acknowledge failure

OVR

Bit 11: Overrun/Underrun.

Allowed values:
0: NoOverrun: No overrun/underrun occured
1: Overrun: Overrun/underrun occured

PECERR

Bit 12: PEC Error in reception.

Allowed values:
0: NoError: no PEC error: receiver returns ACK after PEC reception (if ACK=1)
1: Error: PEC error: receiver returns NACK after PEC reception (whatever ACK)

TIMEOUT

Bit 14: Timeout or Tlow error.

Allowed values:
0: NoTimeout: No Timeout error
1: Timeout: SCL remained LOW for 25 ms

SMBALERT

Bit 15: SMBus alert.

Allowed values:
0: NoAlert: No SMBALERT occured
1: Alert: SMBALERT occurred

SR2

Status register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PEC r								DUALF r	SMBHOST r	SMBDEFAULT r	GENCALL r		TRA r	BUSY r	MSL r

Toggle fields

MSL

Bit 0: Master/slave.

BUSY

Bit 1: Bus busy.

TRA

Bit 2: Transmitter/receiver.

GENCALL

Bit 4: General call address (Slave mode).

SMBDEFAULT

Bit 5: SMBus device default address (Slave mode).

SMBHOST

Bit 6: SMBus host header (Slave mode).

DUALF

Bit 7: Dual flag (Slave mode).

PEC

Bits 8-15: acket error checking register.

CCR

Clock control register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
F_S rw	DUTY rw			CCR rw

Toggle fields

CCR

Bits 0-11: Clock control register in Fast/Standard mode (Master mode).

Allowed values: 0x1-0xfff

DUTY

Bit 14: Fast mode duty cycle.

Allowed values:
0: Duty2_1: Duty cycle t_low/t_high = 2/1
1: Duty16_9: Duty cycle t_low/t_high = 16/9

F_S

Bit 15: I2C master mode selection.

Allowed values:
0: Standard: Standard mode I2C
1: Fast: Fast mode I2C

TRISE

TRISE register

Offset: 0x20, size: 32, reset: 0x00000002, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										TRISE rw

Toggle fields

TRISE

Bits 0-5: Maximum rise time in Fast/Standard mode (Master mode).

Allowed values: 0x0-0x3f

I2C2

0x40005800: Inter integrated circuit

51/51 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1	SWRST		ALERT	PEC	POS	ACK	STOP	START	NOSTRETCH	ENGC	ENPEC	ENARP	SMBTYPE		SMBUS	PE
0x4	CR2				LAST	DMAEN	ITBUFEN	ITEVTEN	ITERREN			FREQ
0x8	OAR1	ADDMODE						ADD
0xc	OAR2									ADD2							ENDUAL
0x10	DR									DR
0x14	SR1	SMBALERT	TIMEOUT		PECERR	OVR	AF	ARLO	BERR	TxE	RxNE		STOPF	ADD10	BTF	ADDR	SB
0x18	SR2	PEC								DUALF	SMBHOST	SMBDEFAULT	GENCALL		TRA	BUSY	MSL
0x1c	CCR	F_S	DUTY			CCR
0x20	TRISE											TRISE

Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWRST rw		ALERT rw	PEC rw	POS rw	ACK rw	STOP rw	START rw	NOSTRETCH rw	ENGC rw	ENPEC rw	ENARP rw	SMBTYPE rw		SMBUS rw	PE rw

Toggle fields

PE

Bit 0: Peripheral enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

SMBUS

Bit 1: SMBus mode.

Allowed values:
0: I2C: I2C Mode
1: SMBus: SMBus

SMBTYPE

Bit 3: SMBus type.

Allowed values:
0: Device: SMBus Device
1: Host: SMBus Host

ENARP

Bit 4: ARP enable.

Allowed values:
0: Disabled: ARP disabled
1: Enabled: ARP enabled

ENPEC

Bit 5: PEC enable.

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

ENGC

Bit 6: General call enable.

Allowed values:
0: Disabled: General call disabled
1: Enabled: General call enabled

NOSTRETCH

Bit 7: Clock stretching disable (Slave mode).

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

START

Bit 8: Start generation.

Allowed values:
0: NoStart: No Start generation
1: Start: In master mode: repeated start generation, in slave mode: start generation when bus is free

STOP

Bit 9: Stop generation.

Allowed values:
0: NoStop: No Stop generation
1: Stop: In master mode: stop generation after current byte/start, in slave mode: release SCL and SDA after current byte

ACK

Bit 10: Acknowledge enable.

Allowed values:
0: NAK: No acknowledge returned
1: ACK: Acknowledge returned after a byte is received

POS

Bit 11: Acknowledge/PEC Position (for data reception).

Allowed values:
0: Current: ACK bit controls the (N)ACK of the current byte being received
1: Next: ACK bit controls the (N)ACK of the next byte to be received

PEC

Bit 12: Packet error checking.

Allowed values:
0: Disabled: No PEC transfer
1: Enabled: PEC transfer

ALERT

Bit 13: SMBus alert.

Allowed values:
0: Release: SMBA pin released high
1: Drive: SMBA pin driven low

SWRST

Bit 15: Software reset.

Allowed values:
0: NotReset: I2C peripheral not under reset
1: Reset: I2C peripheral under reset

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			LAST rw	DMAEN rw	ITBUFEN rw	ITEVTEN rw	ITERREN rw			FREQ rw

Toggle fields

FREQ

Bits 0-5: Peripheral clock frequency.

Allowed values: 0x2-0x32

ITERREN

Bit 8: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

ITEVTEN

Bit 9: Event interrupt enable.

Allowed values:
0: Disabled: Event interrupt disabled
1: Enabled: Event interrupt enabled

ITBUFEN

Bit 10: Buffer interrupt enable.

Allowed values:
0: Disabled: TxE=1 or RxNE=1 does not generate any interrupt
1: Enabled: TxE=1 or RxNE=1 generates Event interrupt

DMAEN

Bit 11: DMA requests enable.

Allowed values:
0: Disabled: DMA requests disabled
1: Enabled: DMA request enabled when TxE=1 or RxNE=1

LAST

Bit 12: DMA last transfer.

Allowed values:
0: NotLast: Next DMA EOT is not the last transfer
1: Last: Next DMA EOT is the last transfer

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDMODE rw						ADD rw

Toggle fields

ADD

Bits 0-9: Interface address.

Allowed values: 0x0-0x3ff

ADDMODE

Bit 15: Addressing mode (slave mode).

Allowed values:
0: ADD7: 7-bit slave address
1: ADD10: 10-bit slave address

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								ADD2 rw							ENDUAL rw

Toggle fields

ENDUAL

Bit 0: Dual addressing mode enable.

Allowed values:
0: Single: Single addressing mode
1: Dual: Dual addressing mode

ADD2

Bits 1-7: Interface address.

Allowed values: 0x0-0x7f

DR

Data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								DR rw

Toggle fields

DR

Bits 0-7: 8-bit data register.

Allowed values: 0x0-0xff

SR1

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

14/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SMBALERT rw	TIMEOUT rw		PECERR rw	OVR rw	AF rw	ARLO rw	BERR rw	TxE r	RxNE r		STOPF r	ADD10 r	BTF r	ADDR r	SB r

Toggle fields

SB

Bit 0: Start bit (Master mode).

Allowed values:
0: NoStart: No Start condition
1: Start: Start condition generated

ADDR

Bit 1: Address sent (master mode)/matched (slave mode).

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

BTF

Bit 2: Byte transfer finished.

Allowed values:
0: NotFinished: Data byte transfer not done
1: Finished: Data byte transfer successful

ADD10

Bit 3: 10-bit header sent (Master mode).

STOPF

Bit 4: Stop detection (slave mode).

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

RxNE

Bit 6: Data register not empty (receivers).

Allowed values:
0: Empty: Data register empty
1: NotEmpty: Data register not empty

TxE

Bit 7: Data register empty (transmitters).

Allowed values:
0: NotEmpty: Data register not empty
1: Empty: Data register empty

BERR

Bit 8: Bus error.

Allowed values:
0: NoError: No misplaced Start or Stop condition
1: Error: Misplaced Start or Stop condition

ARLO

Bit 9: Arbitration lost (master mode).

Allowed values:
0: NoLost: No Arbitration Lost detected
1: Lost: Arbitration Lost detected

AF

Bit 10: Acknowledge failure.

Allowed values:
0: NoFailure: No acknowledge failure
1: Failure: Acknowledge failure

OVR

Bit 11: Overrun/Underrun.

Allowed values:
0: NoOverrun: No overrun/underrun occured
1: Overrun: Overrun/underrun occured

PECERR

Bit 12: PEC Error in reception.

Allowed values:
0: NoError: no PEC error: receiver returns ACK after PEC reception (if ACK=1)
1: Error: PEC error: receiver returns NACK after PEC reception (whatever ACK)

TIMEOUT

Bit 14: Timeout or Tlow error.

Allowed values:
0: NoTimeout: No Timeout error
1: Timeout: SCL remained LOW for 25 ms

SMBALERT

Bit 15: SMBus alert.

Allowed values:
0: NoAlert: No SMBALERT occured
1: Alert: SMBALERT occurred

SR2

Status register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PEC r								DUALF r	SMBHOST r	SMBDEFAULT r	GENCALL r		TRA r	BUSY r	MSL r

Toggle fields

MSL

Bit 0: Master/slave.

BUSY

Bit 1: Bus busy.

TRA

Bit 2: Transmitter/receiver.

GENCALL

Bit 4: General call address (Slave mode).

SMBDEFAULT

Bit 5: SMBus device default address (Slave mode).

SMBHOST

Bit 6: SMBus host header (Slave mode).

DUALF

Bit 7: Dual flag (Slave mode).

PEC

Bits 8-15: acket error checking register.

CCR

Clock control register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
F_S rw	DUTY rw			CCR rw

Toggle fields

CCR

Bits 0-11: Clock control register in Fast/Standard mode (Master mode).

Allowed values: 0x1-0xfff

DUTY

Bit 14: Fast mode duty cycle.

Allowed values:
0: Duty2_1: Duty cycle t_low/t_high = 2/1
1: Duty16_9: Duty cycle t_low/t_high = 16/9

F_S

Bit 15: I2C master mode selection.

Allowed values:
0: Standard: Standard mode I2C
1: Fast: Fast mode I2C

TRISE

TRISE register

Offset: 0x20, size: 32, reset: 0x00000002, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										TRISE rw

Toggle fields

TRISE

Bits 0-5: Maximum rise time in Fast/Standard mode (Master mode).

Allowed values: 0x0-0x3f

IWDG

0x40003000: Independent watchdog

5/5 fields covered.

Toggle register map

Offset	Name	15	11	2	1	0
0x0	KR	KEY
0x4	PR			PR
0x8	RLR		RL
0xc	SR				RVU	PVU

Toggle registers

KR

Key register (IWDG_KR)

Offset: 0x0, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY w

Toggle fields

KEY

Bits 0-15: Key value.

Allowed values:
21845: Unlock: Enable access to PR, RLR and WINR registers
43690: Feed: Feed watchdog with RLR register value
52428: Start: Start the watchdog

PR

Prescaler register (IWDG_PR)

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													PR rw

Toggle fields

PR

Bits 0-2: Prescaler divider.

Allowed values:
0: DivideBy4: Divider /4
1: DivideBy8: Divider /8
2: DivideBy16: Divider /16
3: DivideBy32: Divider /32
4: DivideBy64: Divider /64
5: DivideBy128: Divider /128
6: DivideBy256: Divider /256

RLR

Reload register (IWDG_RLR)

Offset: 0x8, size: 32, reset: 0x00000FFF, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				RL rw

Toggle fields

RL

Bits 0-11: Watchdog counter reload value.

Allowed values: 0x0-0xfff

SR

Status register (IWDG_SR)

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														RVU r	PVU r

Toggle fields

PVU

Bit 0: Watchdog prescaler value update.

RVU

Bit 1: Watchdog counter reload value update.

MPU

0xe000ed90: Memory protection unit

6/19 fields covered.

Toggle register map

Offset	Name	31	28	26	23	21	18	17	16	15	7	5	4	3	2	1	0
0x0	TYPER				IREGION					DREGION							SEPARATE
0x4	CTRL														PRIVDEFENA	HFNMIENA	ENABLE
0x8	RNR										REGION
0xc	RBAR	ADDR								ADDR			VALID	REGION
0x10	RASR		XN	AP		TEX	S	C	B	SRD		SIZE					ENABLE

Toggle registers

TYPER

MPU type register

Offset: 0x0, size: 32, reset: 0x00000800, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								IREGION r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DREGION r															SEPARATE r

Toggle fields

SEPARATE

Bit 0: Separate flag.

DREGION

Bits 8-15: Number of MPU data regions.

IREGION

Bits 16-23: Number of MPU instruction regions.

CTRL

MPU control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													PRIVDEFENA r	HFNMIENA r	ENABLE r

Toggle fields

ENABLE

Bit 0: Enables the MPU.

HFNMIENA

Bit 1: Enables the operation of MPU during hard fault.

PRIVDEFENA

Bit 2: Enable priviliged software access to default memory map.

RNR

MPU region number register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REGION rw

Toggle fields

REGION

Bits 0-7: MPU region.

RBAR

MPU region base address register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADDR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDR rw											VALID rw	REGION rw

Toggle fields

REGION

Bits 0-3: MPU region field.

VALID

Bit 4: MPU region number valid.

ADDR

Bits 5-31: Region base address field.

RASR

MPU region attribute and size register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			XN rw		AP rw					TEX rw			S rw	C rw	B rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SRD rw										SIZE rw					ENABLE rw

Toggle fields

ENABLE

Bit 0: Region enable bit..

SIZE

Bits 1-5: Size of the MPU protection region.

SRD

Bits 8-15: Subregion disable bits.

B

Bit 16: memory attribute.

C

Bit 17: memory attribute.

S

Bit 18: Shareable memory attribute.

TEX

Bits 19-21: memory attribute.

AP

Bits 24-26: Access permission.

XN

Bit 28: Instruction access disable bit.

NVIC

0xe000e100: Nested Vectored Interrupt Controller

2/70 fields covered.

Toggle register map

Offset	Name	31	23	15	7
0x0	ISER0	SETENA		SETENA
0x4	ISER1	SETENA		SETENA
0x80	ICER0	CLRENA		CLRENA
0x84	ICER1	CLRENA		CLRENA
0x100	ISPR0	SETPEND		SETPEND
0x104	ISPR1	SETPEND		SETPEND
0x180	ICPR0	CLRPEND		CLRPEND
0x184	ICPR1	CLRPEND		CLRPEND
0x200	IABR0	ACTIVE		ACTIVE
0x204	IABR1	ACTIVE		ACTIVE
0x300	IPR0	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x304	IPR1	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x308	IPR2	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x30c	IPR3	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x310	IPR4	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x314	IPR5	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x318	IPR6	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x31c	IPR7	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x320	IPR8	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x324	IPR9	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x328	IPR10	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x32c	IPR11	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x330	IPR12	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x334	IPR13	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x338	IPR14	IPR_N3	IPR_N2	IPR_N1	IPR_N0

Toggle registers

ISER0

Interrupt Set-Enable Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SETENA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SETENA rw

Toggle fields

SETENA

Bits 0-31: SETENA.

ISER1

Interrupt Set-Enable Register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SETENA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SETENA rw

Toggle fields

SETENA

Bits 0-31: SETENA.

ICER0

Interrupt Clear-Enable Register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLRENA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLRENA rw

Toggle fields

CLRENA

Bits 0-31: CLRENA.

ICER1

Interrupt Clear-Enable Register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLRENA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLRENA rw

Toggle fields

CLRENA

Bits 0-31: CLRENA.

ISPR0

Interrupt Set-Pending Register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SETPEND rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SETPEND rw

Toggle fields

SETPEND

Bits 0-31: SETPEND.

ISPR1

Interrupt Set-Pending Register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SETPEND rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SETPEND rw

Toggle fields

SETPEND

Bits 0-31: SETPEND.

ICPR0

Interrupt Clear-Pending Register

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLRPEND rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLRPEND rw

Toggle fields

CLRPEND

Bits 0-31: CLRPEND.

ICPR1

Interrupt Clear-Pending Register

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLRPEND rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLRPEND rw

Toggle fields

CLRPEND

Bits 0-31: CLRPEND.

IABR0

Interrupt Active Bit Register

Offset: 0x200, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ACTIVE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ACTIVE r

Toggle fields

ACTIVE

Bits 0-31: ACTIVE.

IABR1

Interrupt Active Bit Register

Offset: 0x204, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ACTIVE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ACTIVE r

Toggle fields

ACTIVE

Bits 0-31: ACTIVE.

IPR0

Interrupt Priority Register

Offset: 0x300, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR1

Interrupt Priority Register

Offset: 0x304, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR2

Interrupt Priority Register

Offset: 0x308, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR3

Interrupt Priority Register

Offset: 0x30c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR4

Interrupt Priority Register

Offset: 0x310, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR5

Interrupt Priority Register

Offset: 0x314, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR6

Interrupt Priority Register

Offset: 0x318, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR7

Interrupt Priority Register

Offset: 0x31c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR8

Interrupt Priority Register

Offset: 0x320, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR9

Interrupt Priority Register

Offset: 0x324, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR10

Interrupt Priority Register

Offset: 0x328, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR11

Interrupt Priority Register

Offset: 0x32c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR12

Interrupt Priority Register

Offset: 0x330, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR13

Interrupt Priority Register

Offset: 0x334, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR14

Interrupt Priority Register

Offset: 0x338, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

NVIC_STIR

0xe000ef00: Nested vectored interrupt controller

0/1 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	STIR																								INTID

Toggle registers

STIR

Software trigger interrupt register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							INTID rw

Toggle fields

INTID

Bits 0-8: Software generated interrupt ID.

PWR

0x40007000: Power control

4/11 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR																								DBP	PLS			PVDE	CSBF	CWUF	PDDS	LPDS
0x4	CSR																								EWUP						PVDO	SBF	WUF

Toggle registers

CR

Power control register (PWR_CR)

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

1/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							DBP rw	PLS rw			PVDE rw	CSBF rw	CWUF rw	PDDS rw	LPDS rw

Toggle fields

LPDS

Bit 0: Low Power Deep Sleep.

PDDS

Bit 1: Power Down Deep Sleep.

Allowed values:
0: STOP_MODE: Enter Stop mode when the CPU enters deepsleep
1: STANDBY_MODE: Enter Standby mode when the CPU enters deepsleep

CWUF

Bit 2: Clear Wake-up Flag.

CSBF

Bit 3: Clear STANDBY Flag.

PVDE

Bit 4: Power Voltage Detector Enable.

PLS

Bits 5-7: PVD Level Selection.

DBP

Bit 8: Disable Backup Domain write protection.

CSR

Power control register (PWR_CR)

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

3/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							EWUP rw						PVDO r	SBF r	WUF r

Toggle fields

WUF

Bit 0: Wake-Up Flag.

SBF

Bit 1: STANDBY Flag.

PVDO

Bit 2: PVD Output.

EWUP

Bit 8: Enable WKUP pin.

RCC

0x40021000: Reset and clock control

133/133 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR							PLLRDY	PLLON					CSSON	HSEBYP	HSERDY	HSEON	HSICAL								HSITRIM						HSIRDY	HSION
0x4	CFGR						MCO					PLLMUL				PLLXTPRE	PLLSRC	ADCPRE		PPRE2			PPRE1			HPRE				SWS		SW
0x8	CIR									CSSC			PLLRDYC	HSERDYC	HSIRDYC	LSERDYC	LSIRDYC				PLLRDYIE	HSERDYIE	HSIRDYIE	LSERDYIE	LSIRDYIE	CSSF			PLLRDYF	HSERDYF	HSIRDYF	LSERDYF	LSIRDYF
0xc	APB2RSTR														TIM17RST	TIM16RST	TIM15RST		USART1RST		SPI1RST	TIM1RST		ADC1RST	IOPGRST	IOPFRST	IOPERST	IOPDRST	IOPCRST	IOPBRST	IOPARST		AFIORST
0x10	APB1RSTR		CECRST	DACRST	PWRRST	BKPRST					I2C2RST	I2C1RST	UART5RST	UART4RST	USART3RST	USART2RST		SPI3RST	SPI2RST			WWDGRST			TIM14RST	TIM13RST	TIM12RST	TIM7RST	TIM6RST	TIM5RST	TIM4RST	TIM3RST	TIM2RST
0x14	AHBENR																								FSMCEN		CRCEN		FLITFEN		SRAMEN	DMA2EN	DMA1EN
0x18	APB2ENR														TIM17EN	TIM16EN	TIM15EN		USART1EN		SPI1EN	TIM1EN		ADC1EN	IOPGEN	IOPFEN	IOPEEN	IOPDEN	IOPCEN	IOPBEN	IOPAEN		AFIOEN
0x1c	APB1ENR		CECEN	DACEN	PWREN	BKPEN					I2C2EN	I2C1EN	UART5EN	UART4EN	USART3EN	USART2EN		SPI3EN	SPI2EN			WWDGEN			TIM14EN	TIM13EN	TIM12EN	TIM7EN	TIM6EN	TIM5EN	TIM4EN	TIM3EN	TIM2EN
0x20	BDCR																BDRST	RTCEN						RTCSEL							LSEBYP	LSERDY	LSEON
0x24	CSR	LPWRRSTF	WWDGRSTF	IWDGRSTF	SFTRSTF	PORRSTF	PINRSTF		RMVF																							LSIRDY	LSION
0x2c	CFGR2																													PREDIV1

Toggle registers

CR

Clock control register

Offset: 0x0, size: 32, reset: 0x00000083, access: Unspecified

10/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						PLLRDY r	PLLON rw					CSSON rw	HSEBYP rw	HSERDY r	HSEON rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
HSICAL r								HSITRIM rw						HSIRDY r	HSION rw

Toggle fields

HSION

Bit 0: Internal High Speed clock enable.

Allowed values:
0: Off: Clock Off
1: On: Clock On

HSIRDY

Bit 1: Internal High Speed clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

HSITRIM

Bits 3-7: Internal High Speed clock trimming.

Allowed values: 0x0-0x1f

HSICAL

Bits 8-15: Internal High Speed clock Calibration.

Allowed values: 0x0-0xff

HSEON

Bit 16: External High Speed clock enable.

Allowed values:
0: Off: Clock Off
1: On: Clock On

HSERDY

Bit 17: External High Speed clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

HSEBYP

Bit 18: External High Speed clock Bypass.

Allowed values:
0: NotBypassed: HSE crystal oscillator not bypassed
1: Bypassed: HSE crystal oscillator bypassed with external clock

CSSON

Bit 19: Clock Security System enable.

Allowed values:
0: Off: Clock security system disabled (clock detector OFF)
1: On: Clock security system enable (clock detector ON if the HSE is ready, OFF if not)

PLLON

Bit 24: PLL enable.

Allowed values:
0: Off: Clock Off
1: On: Clock On

PLLRDY

Bit 25: PLL clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

CFGR

Clock configuration register (RCC_CFGR)

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

10/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					MCO rw					PLLMUL rw				PLLXTPRE rw	PLLSRC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADCPRE rw		PPRE2 rw			PPRE1 rw			HPRE rw				SWS r		SW rw

Toggle fields

SW

Bits 0-1: System clock Switch.

Allowed values:
0: HSI: HSI selected as system clock
1: HSE: HSE selected as system clock
2: PLL: PLL selected as system clock

SWS

Bits 2-3: System Clock Switch Status.

Allowed values:
0: HSI: HSI oscillator used as system clock
1: HSE: HSE oscillator used as system clock
2: PLL: PLL used as system clock

HPRE

Bits 4-7: AHB prescaler.

Allowed values:
8: Div2: SYSCLK divided by 2
9: Div4: SYSCLK divided by 4
10: Div8: SYSCLK divided by 8
11: Div16: SYSCLK divided by 16
12: Div64: SYSCLK divided by 64
13: Div128: SYSCLK divided by 128
14: Div256: SYSCLK divided by 256
15: Div512: SYSCLK divided by 512
0 (+): Div1: SYSCLK not divided

PPRE1

Bits 8-10: APB Low speed prescaler (APB1).

Allowed values:
4: Div2: HCLK divided by 2
5: Div4: HCLK divided by 4
6: Div8: HCLK divided by 8
7: Div16: HCLK divided by 16
0 (+): Div1: HCLK not divided

PPRE2

Bits 11-13: APB High speed prescaler (APB2).

Allowed values:
4: Div2: HCLK divided by 2
5: Div4: HCLK divided by 4
6: Div8: HCLK divided by 8
7: Div16: HCLK divided by 16
0 (+): Div1: HCLK not divided

ADCPRE

Bits 14-15: ADC prescaler.

Allowed values:
0: Div2: PCLK2 divided by 2
1: Div4: PCLK2 divided by 4
2: Div6: PCLK2 divided by 8
3: Div8: PCLK2 divided by 16

PLLSRC

Bit 16: PLL entry clock source.

Allowed values:
0: HSI_Div2: HSI divided by 2 selected as PLL input clock
1: HSE_Div_PREDIV: HSE divided by PREDIV selected as PLL input clock

PLLXTPRE

Bit 17: HSE divider for PLL entry.

Allowed values:
0: Div1: HSE clock not divided
1: Div2: HSE clock divided by 2

PLLMUL

Bits 18-21: PLL Multiplication Factor.

Allowed values:
0: Mul2: PLL input clock x2
1: Mul3: PLL input clock x3
2: Mul4: PLL input clock x4
3: Mul5: PLL input clock x5
4: Mul6: PLL input clock x6
5: Mul7: PLL input clock x7
6: Mul8: PLL input clock x8
7: Mul9: PLL input clock x9
8: Mul10: PLL input clock x10
9: Mul11: PLL input clock x11
10: Mul12: PLL input clock x12
11: Mul13: PLL input clock x13
12: Mul14: PLL input clock x14
13: Mul15: PLL input clock x15
14: Mul16: PLL input clock x16
15: Mul16x: PLL input clock x16

MCO

Bits 24-26: Microcontroller clock output.

Allowed values:
0: NoMCO: MCO output disabled, no clock on MCO
4: SYSCLK: System clock selected
5: HSI: HSI oscillator clock selected
6: HSE: HSE oscillator clock selected
7: PLL: PLL clock selected (divided by 1 or 2, depending en PLLNODIV)

CIR

Clock interrupt register (RCC_CIR)

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

17/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								CSSC w			PLLRDYC w	HSERDYC w	HSIRDYC w	LSERDYC w	LSIRDYC w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			PLLRDYIE rw	HSERDYIE rw	HSIRDYIE rw	LSERDYIE rw	LSIRDYIE rw	CSSF r			PLLRDYF r	HSERDYF r	HSIRDYF r	LSERDYF r	LSIRDYF r

Toggle fields

LSIRDYF

Bit 0: LSI Ready Interrupt flag.

Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt

LSERDYF

Bit 1: LSE Ready Interrupt flag.

Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt

HSIRDYF

Bit 2: HSI Ready Interrupt flag.

Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt

HSERDYF

Bit 3: HSE Ready Interrupt flag.

Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt

PLLRDYF

Bit 4: PLL Ready Interrupt flag.

Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt

CSSF

Bit 7: Clock Security System Interrupt flag.

Allowed values:
0: NotInterrupted: No clock security interrupt caused by HSE clock failure
1: Interrupted: Clock security interrupt caused by HSE clock failure

LSIRDYIE

Bit 8: LSI Ready Interrupt Enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

LSERDYIE

Bit 9: LSE Ready Interrupt Enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

HSIRDYIE

Bit 10: HSI Ready Interrupt Enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

HSERDYIE

Bit 11: HSE Ready Interrupt Enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

PLLRDYIE

Bit 12: PLL Ready Interrupt Enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

LSIRDYC

Bit 16: LSI Ready Interrupt Clear.

Allowed values:
1: Clear: Clear interrupt flag

LSERDYC

Bit 17: LSE Ready Interrupt Clear.

Allowed values:
1: Clear: Clear interrupt flag

HSIRDYC

Bit 18: HSI Ready Interrupt Clear.

Allowed values:
1: Clear: Clear interrupt flag

HSERDYC

Bit 19: HSE Ready Interrupt Clear.

Allowed values:
1: Clear: Clear interrupt flag

PLLRDYC

Bit 20: PLL Ready Interrupt Clear.

Allowed values:
1: Clear: Clear interrupt flag

CSSC

Bit 23: Clock security system interrupt clear.

Allowed values:
1: Clear: Clear CSSF flag

APB2RSTR

APB2 peripheral reset register (RCC_APB2RSTR)

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													TIM17RST rw	TIM16RST rw	TIM15RST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	USART1RST rw		SPI1RST rw	TIM1RST rw		ADC1RST rw	IOPGRST rw	IOPFRST rw	IOPERST rw	IOPDRST rw	IOPCRST rw	IOPBRST rw	IOPARST rw		AFIORST rw

Toggle fields

AFIORST

Bit 0: Alternate function I/O reset.

Allowed values:
1: Reset: Reset the selected module

IOPARST

Bit 2: IO port A reset.

Allowed values:
1: Reset: Reset the selected module

IOPBRST

Bit 3: IO port B reset.

Allowed values:
1: Reset: Reset the selected module

IOPCRST

Bit 4: IO port C reset.

Allowed values:
1: Reset: Reset the selected module

IOPDRST

Bit 5: IO port D reset.

Allowed values:
1: Reset: Reset the selected module

IOPERST

Bit 6: IO port E reset.

Allowed values:
1: Reset: Reset the selected module

IOPFRST

Bit 7: IO port F reset.

Allowed values:
1: Reset: Reset the selected module

IOPGRST

Bit 8: IO port G reset.

Allowed values:
1: Reset: Reset the selected module

ADC1RST

Bit 9: ADC 1 interface reset.

Allowed values:
1: Reset: Reset the selected module

TIM1RST

Bit 11: TIM1 timer reset.

Allowed values:
1: Reset: Reset the selected module

SPI1RST

Bit 12: SPI 1 reset.

Allowed values:
1: Reset: Reset the selected module

USART1RST

Bit 14: USART1 reset.

Allowed values:
1: Reset: Reset the selected module

TIM15RST

Bit 16: TIM15 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIM16RST

Bit 17: TIM16 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIM17RST

Bit 18: TIM17 timer reset.

Allowed values:
1: Reset: Reset the selected module

APB1RSTR

APB1 peripheral reset register (RCC_APB1RSTR)

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

22/22 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	CECRST rw	DACRST rw	PWRRST rw	BKPRST rw					I2C2RST rw	I2C1RST rw	UART5RST rw	UART4RST rw	USART3RST rw	USART2RST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SPI3RST rw	SPI2RST rw			WWDGRST rw			TIM14RST rw	TIM13RST rw	TIM12RST rw	TIM7RST rw	TIM6RST rw	TIM5RST rw	TIM4RST rw	TIM3RST rw	TIM2RST rw

Toggle fields

TIM2RST

Bit 0: Timer 2 reset.

Allowed values:
1: Reset: Reset the selected module

TIM3RST

Bit 1: Timer 3 reset.

Allowed values:
1: Reset: Reset the selected module

TIM4RST

Bit 2: Timer 4 reset.

Allowed values:
1: Reset: Reset the selected module

TIM5RST

Bit 3: Timer 5 reset.

Allowed values:
1: Reset: Reset the selected module

TIM6RST

Bit 4: Timer 6 reset.

Allowed values:
1: Reset: Reset the selected module

TIM7RST

Bit 5: Timer 7 reset.

Allowed values:
1: Reset: Reset the selected module

TIM12RST

Bit 6: Timer 12 reset.

Allowed values:
1: Reset: Reset the selected module

TIM13RST

Bit 7: Timer 13 reset.

Allowed values:
1: Reset: Reset the selected module

TIM14RST

Bit 8: Timer 14 reset.

Allowed values:
1: Reset: Reset the selected module

WWDGRST

Bit 11: Window watchdog reset.

Allowed values:
1: Reset: Reset the selected module

SPI2RST

Bit 14: SPI2 reset.

Allowed values:
1: Reset: Reset the selected module

SPI3RST

Bit 15: SPI3 reset.

Allowed values:
1: Reset: Reset the selected module

USART2RST

Bit 17: USART 2 reset.

Allowed values:
1: Reset: Reset the selected module

USART3RST

Bit 18: USART 3 reset.

Allowed values:
1: Reset: Reset the selected module

UART4RST

Bit 19: USART 4 reset.

Allowed values:
1: Reset: Reset the selected module

UART5RST

Bit 20: USART 5 reset.

Allowed values:
1: Reset: Reset the selected module

I2C1RST

Bit 21: I2C1 reset.

Allowed values:
1: Reset: Reset the selected module

I2C2RST

Bit 22: I2C2 reset.

Allowed values:
1: Reset: Reset the selected module

BKPRST

Bit 27: Backup interface reset.

Allowed values:
1: Reset: Reset the selected module

PWRRST

Bit 28: Power interface reset.

Allowed values:
1: Reset: Reset the selected module

DACRST

Bit 29: DAC interface reset.

Allowed values:
1: Reset: Reset the selected module

CECRST

Bit 30: CEC reset.

Allowed values:
1: Reset: Reset the selected module

AHBENR

AHB Peripheral Clock enable register (RCC_AHBENR)

Offset: 0x14, size: 32, reset: 0x00000014, access: read-write

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							FSMCEN rw		CRCEN rw		FLITFEN rw		SRAMEN rw	DMA2EN rw	DMA1EN rw

Toggle fields

DMA1EN

Bit 0: DMA1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

DMA2EN

Bit 1: DMA2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SRAMEN

Bit 2: SRAM interface clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

FLITFEN

Bit 4: FLITF clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

CRCEN

Bit 6: CRC clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

FSMCEN

Bit 8: FSMC clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

APB2ENR

APB2 peripheral clock enable register (RCC_APB2ENR)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													TIM17EN rw	TIM16EN rw	TIM15EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	USART1EN rw		SPI1EN rw	TIM1EN rw		ADC1EN rw	IOPGEN rw	IOPFEN rw	IOPEEN rw	IOPDEN rw	IOPCEN rw	IOPBEN rw	IOPAEN rw		AFIOEN rw

Toggle fields

AFIOEN

Bit 0: Alternate function I/O clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

IOPAEN

Bit 2: I/O port A clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

IOPBEN

Bit 3: I/O port B clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

IOPCEN

Bit 4: I/O port C clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

IOPDEN

Bit 5: I/O port D clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

IOPEEN

Bit 6: I/O port E clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

IOPFEN

Bit 7: I/O port F clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

IOPGEN

Bit 8: I/O port G clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

ADC1EN

Bit 9: ADC 1 interface clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM1EN

Bit 11: TIM1 Timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SPI1EN

Bit 12: SPI 1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USART1EN

Bit 14: USART1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM15EN

Bit 16: TIM15 Timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM16EN

Bit 17: TIM16 Timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM17EN

Bit 18: TIM17 Timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

APB1ENR

APB1 peripheral clock enable register (RCC_APB1ENR)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

22/22 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	CECEN rw	DACEN rw	PWREN rw	BKPEN rw					I2C2EN rw	I2C1EN rw	UART5EN rw	UART4EN rw	USART3EN rw	USART2EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SPI3EN rw	SPI2EN rw			WWDGEN rw			TIM14EN rw	TIM13EN rw	TIM12EN rw	TIM7EN rw	TIM6EN rw	TIM5EN rw	TIM4EN rw	TIM3EN rw	TIM2EN rw

Toggle fields

TIM2EN

Bit 0: Timer 2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM3EN

Bit 1: Timer 3 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM4EN

Bit 2: Timer 4 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM5EN

Bit 3: Timer 5 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM6EN

Bit 4: Timer 6 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM7EN

Bit 5: Timer 7 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM12EN

Bit 6: Timer 12 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM13EN

Bit 7: Timer 13 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM14EN

Bit 8: Timer 14 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

WWDGEN

Bit 11: Window watchdog clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SPI2EN

Bit 14: SPI 2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SPI3EN

Bit 15: SPI 3 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USART2EN

Bit 17: USART 2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USART3EN

Bit 18: USART 3 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

UART4EN

Bit 19: UART 4 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

UART5EN

Bit 20: UART 5 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

I2C1EN

Bit 21: I2C 1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

I2C2EN

Bit 22: I2C 2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

BKPEN

Bit 27: Backup interface clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

PWREN

Bit 28: Power interface clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

DACEN

Bit 29: DAC interface clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

CECEN

Bit 30: CEC clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

BDCR

Backup domain control register (RCC_BDCR)

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

6/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															BDRST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RTCEN rw						RTCSEL rw							LSEBYP rw	LSERDY r	LSEON rw

Toggle fields

LSEON

Bit 0: External Low Speed oscillator enable.

Allowed values:
0: Off: LSE oscillator Off
1: On: LSE oscillator On

LSERDY

Bit 1: External Low Speed oscillator ready.

Allowed values:
0: NotReady: LSE oscillator not ready
1: Ready: LSE oscillator ready

LSEBYP

Bit 2: External Low Speed oscillator bypass.

Allowed values:
0: NotBypassed: LSE crystal oscillator not bypassed
1: Bypassed: LSE crystal oscillator bypassed with external clock

RTCSEL

Bits 8-9: RTC clock source selection.

Allowed values:
0: NoClock: No clock
1: LSE: LSE oscillator clock used as RTC clock
2: LSI: LSI oscillator clock used as RTC clock
3: HSE: HSE oscillator clock divided by a prescaler used as RTC clock

RTCEN

Bit 15: RTC clock enable.

Allowed values:
0: Disabled: RTC clock disabled
1: Enabled: RTC clock enabled

BDRST

Bit 16: Backup domain software reset.

Allowed values:
0: Disabled: Reset not activated
1: Enabled: Reset the entire RTC domain

CSR

Control/status register (RCC_CSR)

Offset: 0x24, size: 32, reset: 0x0C000000, access: Unspecified

9/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LPWRRSTF rw	WWDGRSTF rw	IWDGRSTF rw	SFTRSTF rw	PORRSTF rw	PINRSTF rw		RMVF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														LSIRDY r	LSION rw

Toggle fields

LSION

Bit 0: Internal low speed oscillator enable.

Allowed values:
0: Off: LSI oscillator Off
1: On: LSI oscillator On

LSIRDY

Bit 1: Internal low speed oscillator ready.

Allowed values:
0: NotReady: LSI oscillator not ready
1: Ready: LSI oscillator ready

RMVF

Bit 24: Remove reset flag.

Allowed values:
1: Clear: Clears the reset flag

PINRSTF

Bit 26: PIN reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

PORRSTF

Bit 27: POR/PDR reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

SFTRSTF

Bit 28: Software reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

IWDGRSTF

Bit 29: Independent watchdog reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

WWDGRSTF

Bit 30: Window watchdog reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

LPWRRSTF

Bit 31: Low-power reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

CFGR2

Clock configuration register 2

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PREDIV1 rw

Toggle fields

PREDIV1

Bits 0-3: PREDIV1 division factor.

Allowed values:
0: Div1: PREDIV input clock not divided
1: Div2: PREDIV input clock divided by 2
2: Div3: PREDIV input clock divided by 3
3: Div4: PREDIV input clock divided by 4
4: Div5: PREDIV input clock divided by 5
5: Div6: PREDIV input clock divided by 6
6: Div7: PREDIV input clock divided by 7
7: Div8: PREDIV input clock divided by 8
8: Div9: PREDIV input clock divided by 9
9: Div10: PREDIV input clock divided by 10
10: Div11: PREDIV input clock divided by 11
11: Div12: PREDIV input clock divided by 12
12: Div13: PREDIV input clock divided by 13
13: Div14: PREDIV input clock divided by 14
14: Div15: PREDIV input clock divided by 15
15: Div16: PREDIV input clock divided by 16

RTC

0x40002800: Real time clock

3/17 fields covered.

Toggle register map

Offset	Name	15	5	4	3	2	1	0
0x0	CRH					OWIE	ALRIE	SECIE
0x4	CRL		RTOFF	CNF	RSF	OWF	ALRF	SECF
0x8	PRLH				PRLH
0xc	PRLL	PRLL
0x10	DIVH				DIVH
0x14	DIVL	DIVL
0x18	CNTH	CNTH
0x1c	CNTL	CNTL
0x20	ALRH	ALRH
0x24	ALRL	ALRL

Toggle registers

CRH

RTC Control Register High

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													OWIE rw	ALRIE rw	SECIE rw

Toggle fields

SECIE

Bit 0: Second interrupt Enable.

ALRIE

Bit 1: Alarm interrupt Enable.

OWIE

Bit 2: Overflow interrupt Enable.

CRL

RTC Control Register Low

Offset: 0x4, size: 32, reset: 0x00000020, access: Unspecified

1/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										RTOFF r	CNF rw	RSF rw	OWF rw	ALRF rw	SECF rw

Toggle fields

SECF

Bit 0: Second Flag.

ALRF

Bit 1: Alarm Flag.

OWF

Bit 2: Overflow Flag.

RSF

Bit 3: Registers Synchronized Flag.

CNF

Bit 4: Configuration Flag.

RTOFF

Bit 5: RTC operation OFF.

PRLH

RTC Prescaler Load Register High

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PRLH w

Toggle fields

PRLH

Bits 0-3: RTC Prescaler Load Register High.

PRLL

RTC Prescaler Load Register Low

Offset: 0xc, size: 32, reset: 0x00008000, access: write-only

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRLL w

Toggle fields

PRLL

Bits 0-15: RTC Prescaler Divider Register Low.

DIVH

RTC Prescaler Divider Register High

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												DIVH r

Toggle fields

DIVH

Bits 0-3: RTC prescaler divider register high.

DIVL

RTC Prescaler Divider Register Low

Offset: 0x14, size: 32, reset: 0x00008000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DIVL r

Toggle fields

DIVL

Bits 0-15: RTC prescaler divider register Low.

CNTH

RTC Counter Register High

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNTH rw

Toggle fields

CNTH

Bits 0-15: RTC counter register high.

CNTL

RTC Counter Register Low

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNTL rw

Toggle fields

CNTL

Bits 0-15: RTC counter register Low.

ALRH

RTC Alarm Register High

Offset: 0x20, size: 32, reset: 0x0000FFFF, access: write-only

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ALRH w

Toggle fields

ALRH

Bits 0-15: RTC alarm register high.

ALRL

RTC Alarm Register Low

Offset: 0x24, size: 32, reset: 0x0000FFFF, access: write-only

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ALRL w

Toggle fields

ALRL

Bits 0-15: RTC alarm register low.

SCB

0xe000ed00: System control block

5/74 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	19	18	17	16	15	14	13	12	11	10	9	8	7	5	4	3	2	1	0
0x0	CPUID	Implementer								Variant		Constant				PartNo											Revision
0x4	ICSR	NMIPENDSET			PENDSVSET	PENDSVCLR	PENDSTSET	PENDSTCLR			ISRPENDING		VECTPENDING			VECTPENDING				RETTOBASE			VECTACTIVE
0x8	VTOR			TBLOFF												TBLOFF
0xc	AIRCR	VECTKEYSTAT														ENDIANESS					PRIGROUP							SYSRESETREQ	VECTCLRACTIVE	VECTRESET
0x10	SCR																									SEVEONPEND		SLEEPDEEP	SLEEPONEXIT
0x14	CCR																					STKALIGN	BFHFNMIGN			DIV_0_TRP	UNALIGN__TRP		USERSETMPEND	NONBASETHRDENA
0x18	SHPR1									PRI_6						PRI_5								PRI_4
0x1c	SHPR2	PRI_11
0x20	SHPR3	PRI_15								PRI_14
0x24	SHCRS												USGFAULTENA	BUSFAULTENA	MEMFAULTENA	SVCALLPENDED	BUSFAULTPENDED	MEMFAULTPENDED	USGFAULTPENDED	SYSTICKACT	PENDSVACT		MONITORACT	SVCALLACT			USGFAULTACT		BUSFAULTACT	MEMFAULTACT
0x28	CFSR_UFSR_BFSR_MMFSR							DIVBYZERO	UNALIGNED			NOCP	INVPC	INVSTATE	UNDEFINSTR	BFARVALID		LSPERR	STKERR	UNSTKERR	IMPRECISERR	PRECISERR	IBUSERR	MMARVALID	MLSPERR	MSTKERR	MUNSTKERR		DACCVIOL	IACCVIOL
0x2c	HFSR	DEBUG_VT	FORCED																										VECTTBL
0x34	MMFAR	MMFAR														MMFAR
0x38	BFAR	BFAR														BFAR

Toggle registers

CPUID

CPUID base register

Offset: 0x0, size: 32, reset: 0x410FC241, access: read-only

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Implementer r								Variant r				Constant r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PartNo r												Revision r

Toggle fields

Revision

Bits 0-3: Revision number.

PartNo

Bits 4-15: Part number of the processor.

Constant

Bits 16-19: Reads as 0xF.

Variant

Bits 20-23: Variant number.

Implementer

Bits 24-31: Implementer code.

ICSR

Interrupt control and state register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
NMIPENDSET rw			PENDSVSET rw	PENDSVCLR rw	PENDSTSET rw	PENDSTCLR rw			ISRPENDING rw				VECTPENDING rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VECTPENDING rw				RETTOBASE rw			VECTACTIVE rw

Toggle fields

VECTACTIVE

Bits 0-8: Active vector.

RETTOBASE

Bit 11: Return to base level.

VECTPENDING

Bits 12-18: Pending vector.

ISRPENDING

Bit 22: Interrupt pending flag.

PENDSTCLR

Bit 25: SysTick exception clear-pending bit.

PENDSTSET

Bit 26: SysTick exception set-pending bit.

PENDSVCLR

Bit 27: PendSV clear-pending bit.

PENDSVSET

Bit 28: PendSV set-pending bit.

NMIPENDSET

Bit 31: NMI set-pending bit..

VTOR

Vector table offset register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		TBLOFF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TBLOFF rw

Toggle fields

TBLOFF

Bits 9-29: Vector table base offset field.

AIRCR

Application interrupt and reset control register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
VECTKEYSTAT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ENDIANESS rw					PRIGROUP rw								SYSRESETREQ rw	VECTCLRACTIVE rw	VECTRESET rw

Toggle fields

VECTRESET

Bit 0: VECTRESET.

VECTCLRACTIVE

Bit 1: VECTCLRACTIVE.

SYSRESETREQ

Bit 2: SYSRESETREQ.

PRIGROUP

Bits 8-10: PRIGROUP.

ENDIANESS

Bit 15: ENDIANESS.

VECTKEYSTAT

Bits 16-31: Register key.

SCR

System control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											SEVEONPEND rw		SLEEPDEEP rw	SLEEPONEXIT rw

Toggle fields

SLEEPONEXIT

Bit 1: SLEEPONEXIT.

SLEEPDEEP

Bit 2: SLEEPDEEP.

SEVEONPEND

Bit 4: Send Event on Pending bit.

CCR

Configuration and control register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						STKALIGN rw	BFHFNMIGN rw				DIV_0_TRP rw	UNALIGN__TRP rw		USERSETMPEND rw	NONBASETHRDENA rw

Toggle fields

NONBASETHRDENA

Bit 0: Configures how the processor enters Thread mode.

USERSETMPEND

Bit 1: USERSETMPEND.

UNALIGN__TRP

Bit 3: UNALIGN_ TRP.

DIV_0_TRP

Bit 4: DIV_0_TRP.

BFHFNMIGN

Bit 8: BFHFNMIGN.

STKALIGN

Bit 9: STKALIGN.

SHPR1

System handler priority registers

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRI_6 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRI_5 rw								PRI_4 rw

Toggle fields

PRI_4

Bits 0-7: Priority of system handler 4.

PRI_5

Bits 8-15: Priority of system handler 5.

PRI_6

Bits 16-23: Priority of system handler 6.

SHPR2

System handler priority registers

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRI_11 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

PRI_11

Bits 24-31: Priority of system handler 11.

SHPR3

System handler priority registers

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRI_15 rw								PRI_14 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

PRI_14

Bits 16-23: Priority of system handler 14.

PRI_15

Bits 24-31: Priority of system handler 15.

SHCRS

System handler control and state register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													USGFAULTENA rw	BUSFAULTENA rw	MEMFAULTENA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SVCALLPENDED rw	BUSFAULTPENDED rw	MEMFAULTPENDED rw	USGFAULTPENDED rw	SYSTICKACT rw	PENDSVACT rw		MONITORACT rw	SVCALLACT rw				USGFAULTACT rw		BUSFAULTACT rw	MEMFAULTACT rw

Toggle fields

MEMFAULTACT

Bit 0: Memory management fault exception active bit.

BUSFAULTACT

Bit 1: Bus fault exception active bit.

USGFAULTACT

Bit 3: Usage fault exception active bit.

SVCALLACT

Bit 7: SVC call active bit.

MONITORACT

Bit 8: Debug monitor active bit.

PENDSVACT

Bit 10: PendSV exception active bit.

SYSTICKACT

Bit 11: SysTick exception active bit.

USGFAULTPENDED

Bit 12: Usage fault exception pending bit.

MEMFAULTPENDED

Bit 13: Memory management fault exception pending bit.

BUSFAULTPENDED

Bit 14: Bus fault exception pending bit.

SVCALLPENDED

Bit 15: SVC call pending bit.

MEMFAULTENA

Bit 16: Memory management fault enable bit.

BUSFAULTENA

Bit 17: Bus fault enable bit.

USGFAULTENA

Bit 18: Usage fault enable bit.

CFSR_UFSR_BFSR_MMFSR

Configurable fault status register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						DIVBYZERO rw	UNALIGNED rw					NOCP rw	INVPC rw	INVSTATE rw	UNDEFINSTR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BFARVALID rw		LSPERR rw	STKERR rw	UNSTKERR rw	IMPRECISERR rw	PRECISERR rw	IBUSERR rw	MMARVALID rw		MLSPERR rw	MSTKERR rw	MUNSTKERR rw		DACCVIOL rw	IACCVIOL rw

Toggle fields

IACCVIOL

Bit 0: IACCVIOL.

DACCVIOL

Bit 1: DACCVIOL.

MUNSTKERR

Bit 3: MUNSTKERR.

MSTKERR

Bit 4: MSTKERR.

MLSPERR

Bit 5: MLSPERR.

MMARVALID

Bit 7: MMARVALID.

IBUSERR

Bit 8: Instruction bus error.

PRECISERR

Bit 9: Precise data bus error.

IMPRECISERR

Bit 10: Imprecise data bus error.

UNSTKERR

Bit 11: Bus fault on unstacking for a return from exception.

STKERR

Bit 12: Bus fault on stacking for exception entry.

LSPERR

Bit 13: Bus fault on floating-point lazy state preservation.

BFARVALID

Bit 15: Bus Fault Address Register (BFAR) valid flag.

UNDEFINSTR

Bit 16: Undefined instruction usage fault.

INVSTATE

Bit 17: Invalid state usage fault.

INVPC

Bit 18: Invalid PC load usage fault.

NOCP

Bit 19: No coprocessor usage fault..

UNALIGNED

Bit 24: Unaligned access usage fault.

DIVBYZERO

Bit 25: Divide by zero usage fault.

HFSR

Hard fault status register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DEBUG_VT rw	FORCED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														VECTTBL rw

Toggle fields

VECTTBL

Bit 1: Vector table hard fault.

FORCED

Bit 30: Forced hard fault.

DEBUG_VT

Bit 31: Reserved for Debug use.

MMFAR

Memory management fault address register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MMFAR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MMFAR rw

Toggle fields

MMFAR

Bits 0-31: Memory management fault address.

BFAR

Bus fault address register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BFAR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BFAR rw

Toggle fields

BFAR

Bits 0-31: Bus fault address.

SCB_ACTRL

0xe000e008: System control block ACTLR

0/4 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	ACTRL																				DISITMATBFLUSH	DISRAMODE	FPEXCODIS								DISFOLD

Toggle registers

ACTRL

Auxiliary control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DISITMATBFLUSH rw	DISRAMODE rw	FPEXCODIS rw								DISFOLD rw

Toggle fields

DISFOLD

Bit 2: DISFOLD.

FPEXCODIS

Bit 10: FPEXCODIS.

DISRAMODE

Bit 11: DISRAMODE.

DISITMATBFLUSH

Bit 12: DISITMATBFLUSH.

SPI1

0x40013000: Serial peripheral interface

31/31 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	2	1	0
0x0 (16-bit)	CR1	BIDIMODE	BIDIOE	CRCEN	CRCNEXT	DFF	RXONLY	SSM	SSI	LSBFIRST	SPE	BR		MSTR	CPOL	CPHA
0x4 (16-bit)	CR2									TXEIE	RXNEIE	ERRIE		SSOE	TXDMAEN	RXDMAEN
0x8 (16-bit)	SR									BSY	OVR	MODF	CRCERR		TXE	RXNE
0xc (16-bit)	DR	DR
0xc (8-bit)	DR8									DR
0x10 (16-bit)	CRCPR	CRCPOLY
0x14 (16-bit)	RXCRCR	RxCRC
0x18 (16-bit)	TXCRCR	TxCRC

Toggle registers

CR1

control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

14/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIDIMODE rw	BIDIOE rw	CRCEN rw	CRCNEXT rw	DFF rw	RXONLY rw	SSM rw	SSI rw	LSBFIRST rw	SPE rw	BR rw			MSTR rw	CPOL rw	CPHA rw

Toggle fields

CPHA

Bit 0: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 1: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

MSTR

Bit 2: Master selection.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

BR

Bits 3-5: Baud rate control.

Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256

SPE

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LSBFIRST

Bit 7: Frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SSI

Bit 8: Internal slave select.

Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored

SSM

Bit 9: Software slave management.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

RXONLY

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)

DFF

Bit 11: Data frame format.

Allowed values:
0: EightBit: 8-bit data frame format is selected for transmission/reception
1: SixteenBit: 16-bit data frame format is selected for transmission/reception

CRCNEXT

Bit 12: CRC transfer next.

Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register

CRCEN

Bit 13: Hardware CRC calculation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BIDIOE

Bit 14: Output enable in bidirectional mode.

Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)

BIDIMODE

Bit 15: Bidirectional data mode enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CR2

control register 2

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TXEIE rw	RXNEIE rw	ERRIE rw			SSOE rw	TXDMAEN rw	RXDMAEN rw

Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 1: Tx buffer DMA enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

SSOE

Bit 2: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked

TXEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked

SR

status register

Offset: 0x8, size: 16, reset: 0x00000002, access: Unspecified

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								BSY r	OVR r	MODF r	CRCERR rw			TXE r	RXNE r

Toggle fields

RXNE

Bit 0: Receive buffer not empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXE

Bit 1: Transmit buffer empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

CRCERR

Bit 4: CRC error flag.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

MODF

Bit 5: Mode fault.

Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred

OVR

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	2	1	0
0x0 (16-bit)	CR1	BIDIMODE	BIDIOE	CRCEN	CRCNEXT	DFF	RXONLY	SSM	SSI	LSBFIRST	SPE	BR		MSTR	CPOL	CPHA
0x4 (16-bit)	CR2									TXEIE	RXNEIE	ERRIE		SSOE	TXDMAEN	RXDMAEN
0x8 (16-bit)	SR									BSY	OVR	MODF	CRCERR		TXE	RXNE
0xc (16-bit)	DR	DR
0xc (8-bit)	DR8									DR
0x10 (16-bit)	CRCPR	CRCPOLY
0x14 (16-bit)	RXCRCR	RxCRC
0x18 (16-bit)	TXCRCR	TxCRC

Toggle registers

CR1

control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

14/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIDIMODE rw	BIDIOE rw	CRCEN rw	CRCNEXT rw	DFF rw	RXONLY rw	SSM rw	SSI rw	LSBFIRST rw	SPE rw	BR rw			MSTR rw	CPOL rw	CPHA rw

Toggle fields

CPHA

Bit 0: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 1: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

MSTR

Bit 2: Master selection.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

BR

Bits 3-5: Baud rate control.

Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256

SPE

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LSBFIRST

Bit 7: Frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SSI

Bit 8: Internal slave select.

Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored

SSM

Bit 9: Software slave management.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

RXONLY

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)

DFF

Bit 11: Data frame format.

Allowed values:
0: EightBit: 8-bit data frame format is selected for transmission/reception
1: SixteenBit: 16-bit data frame format is selected for transmission/reception

CRCNEXT

Bit 12: CRC transfer next.

Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register

CRCEN

Bit 13: Hardware CRC calculation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BIDIOE

Bit 14: Output enable in bidirectional mode.

Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)

BIDIMODE

Bit 15: Bidirectional data mode enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CR2

control register 2

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TXEIE rw	RXNEIE rw	ERRIE rw			SSOE rw	TXDMAEN rw	RXDMAEN rw

Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 1: Tx buffer DMA enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

SSOE

Bit 2: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked

TXEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked

SR

status register

Offset: 0x8, size: 16, reset: 0x00000002, access: Unspecified

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								BSY r	OVR r	MODF r	CRCERR rw			TXE r	RXNE r

Toggle fields

RXNE

Bit 0: Receive buffer not empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXE

Bit 1: Transmit buffer empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

CRCERR

Bit 4: CRC error flag.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

MODF

Bit 5: Mode fault.

Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred

OVR

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	2	1	0
0x0 (16-bit)	CR1	BIDIMODE	BIDIOE	CRCEN	CRCNEXT	DFF	RXONLY	SSM	SSI	LSBFIRST	SPE	BR		MSTR	CPOL	CPHA
0x4 (16-bit)	CR2									TXEIE	RXNEIE	ERRIE		SSOE	TXDMAEN	RXDMAEN
0x8 (16-bit)	SR									BSY	OVR	MODF	CRCERR		TXE	RXNE
0xc (16-bit)	DR	DR
0xc (8-bit)	DR8									DR
0x10 (16-bit)	CRCPR	CRCPOLY
0x14 (16-bit)	RXCRCR	RxCRC
0x18 (16-bit)	TXCRCR	TxCRC

Toggle registers

CR1

control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

14/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIDIMODE rw	BIDIOE rw	CRCEN rw	CRCNEXT rw	DFF rw	RXONLY rw	SSM rw	SSI rw	LSBFIRST rw	SPE rw	BR rw			MSTR rw	CPOL rw	CPHA rw

Toggle fields

CPHA

Bit 0: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 1: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

MSTR

Bit 2: Master selection.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

BR

Bits 3-5: Baud rate control.

Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256

SPE

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LSBFIRST

Bit 7: Frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SSI

Bit 8: Internal slave select.

Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored

SSM

Bit 9: Software slave management.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

RXONLY

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)

DFF

Bit 11: Data frame format.

Allowed values:
0: EightBit: 8-bit data frame format is selected for transmission/reception
1: SixteenBit: 16-bit data frame format is selected for transmission/reception

CRCNEXT

Bit 12: CRC transfer next.

Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register

CRCEN

Bit 13: Hardware CRC calculation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BIDIOE

Bit 14: Output enable in bidirectional mode.

Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)

BIDIMODE

Bit 15: Bidirectional data mode enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CR2

control register 2

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TXEIE rw	RXNEIE rw	ERRIE rw			SSOE rw	TXDMAEN rw	RXDMAEN rw

Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 1: Tx buffer DMA enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

SSOE

Bit 2: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked

TXEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked

SR

status register

Offset: 0x8, size: 16, reset: 0x00000002, access: Unspecified

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								BSY r	OVR r	MODF r	CRCERR rw			TXE r	RXNE r

Toggle fields

RXNE

Bit 0: Receive buffer not empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXE

Bit 1: Transmit buffer empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

CRCERR

Bit 4: CRC error flag.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

MODF

Bit 5: Mode fault.

Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred

OVR

Offset	Name	23	16	15	2	1	0
0x0	CTRL		COUNTFLAG		CLKSOURCE	TICKINT	ENABLE
0x4	LOAD_	RELOAD		RELOAD
0x8	VAL	CURRENT		CURRENT
0xc	CALIB	TENMS		TENMS

Toggle registers

CTRL

SysTick control and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															COUNTFLAG rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													CLKSOURCE rw	TICKINT rw	ENABLE rw

Toggle fields

ENABLE

Bit 0: Counter enable.

TICKINT

Bit 1: SysTick exception request enable.

CLKSOURCE

Bit 2: Clock source selection.

COUNTFLAG

Bit 16: COUNTFLAG.

LOAD_

SysTick reload value register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								RELOAD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RELOAD rw

Toggle fields

RELOAD

Bits 0-23: RELOAD value.

VAL

SysTick current value register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								CURRENT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CURRENT rw

Toggle fields

CURRENT

Bits 0-23: Current counter value.

CALIB

SysTick calibration value register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								TENMS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TENMS rw

Toggle fields

TENMS

Bits 0-23: Calibration value.

TIM1

0x40012c00: Advanced timer

92/127 fields covered.

Toggle register map

Offset	Name	18	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1								CKD		ARPE	CMS		DIR	OPM	URS	UDIS	CEN
0x4	CR2			OIS[4]	OIS[3]N	OIS[3]	OIS[2]N	OIS[2]	OIS[1]N	OIS[1]	TI1S	MMS			CCDS	CCUS		CCPC
0x8	SMCR		ETP	ECE	ETPS		ETF				MSM	TS				SMS
0xc	DIER			TDE	COMDE	CC[4]DE	CC[3]DE	CC[2]DE	CC[1]DE	UDE	BIE	TIE	COMIE	CC[4]IE	CC[3]IE	CC[2]IE	CC[1]IE	UIE
0x10	SR					CC[4]OF	CC[3]OF	CC[2]OF	CC[1]OF		BIF	TIF	COMIF	CC[4]IF	CC[3]IF	CC[2]IF	CC[1]IF	UIF
0x14	EGR										BG	TG	COMG	CC[4]G	CC[3]G	CC[2]G	CC[1]G	UG
0x18	CCMR1_Input	IC[2]F	IC[2]F				IC[2]PSC		CC[2]S		IC[1]F				IC[1]PSC		CC[1]S
0x18	CCMR1_Output		OC[2]CE	OC[2]M			OC[2]PE	OC[2]FE	CC[2]S		OC[1]CE	OC[1]M			OC[1]PE	OC[1]FE	CC[1]S
0x1c	CCMR2_Input	IC[4]F	IC[4]F				IC[4]PSC		CC[4]S		IC[3]F				IC[3]PSC		CC[3]S
0x1c	CCMR2_Output		OC[4]CE	OC[4]M			OC[4]PE	OC[4]FE	CC[4]S		OC[3]CE	OC[3]M			OC[3]PE	OC[3]FE	CC[3]S
0x20	CCER				CC[4]P	CC[4]E	CC[3]NP	CC[3]NE	CC[3]P	CC[3]E	CC[2]NP	CC[2]NE	CC[2]P	CC[2]E	CC[1]NP	CC[1]NE	CC[1]P	CC[1]E
0x24	CNT		CNT
0x28	PSC		PSC
0x2c	ARR		ARR
0x30	RCR										REP
0x34	CCR[1]		CCR
0x38	CCR[2]		CCR
0x3c	CCR[3]		CCR
0x40	CCR[4]		CCR
0x44	BDTR		MOE	AOE	BKP	BKE	OSSR	OSSI	LOCK		DTG
0x48	DCR					DBL								DBA
0x4c	DMAR		DMAB

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CKD rw		ARPE rw	CMS rw		DIR rw	OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

10/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	OIS[4] rw	OIS[3]N rw	OIS[3] rw	OIS[2]N rw	OIS[2] rw	OIS[1]N rw	OIS[1] rw	TI1S rw	MMS rw			CCDS rw	CCUS rw		CCPC rw

Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

OIS[1]

Bit 8: Output Idle state (OC1 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[1]N

Bit 9: Output Idle state (OC1N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[2]

Bit 10: Output Idle state (OC2 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[2]N

Bit 11: Output Idle state (OC2N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[3]

Bit 12: Output Idle state (OC3 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[3]N

Bit 13: Output Idle state (OC3N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[4]

Bit 14: Output Idle state (OC4 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETP rw	ECE rw	ETPS rw		ETF rw				MSM rw	TS rw				SMS rw

Toggle fields

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

12/15 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDE rw	COMDE rw	CC[4]DE rw	CC[3]DE rw	CC[2]DE rw	CC[1]DE rw	UDE rw	BIE rw	TIE rw	COMIE rw	CC[4]IE rw	CC[3]IE rw	CC[2]IE rw	CC[1]IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

COMIE

Bit 5: COM interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CC[4]OF rw	CC[3]OF rw	CC[2]OF rw	CC[1]OF rw		BIF rw	TIF rw	COMIF rw	CC[4]IF rw	CC[3]IF rw	CC[2]IF rw	CC[1]IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

BIF

Bit 7: Break interrupt flag.

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

6/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								BG w	TG w	COMG w	CC[4]G w	CC[3]G w	CC[2]G w	CC[1]G w	UG w

Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													IC[2]F rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC[2]F rw				IC[2]PSC rw		CC[2]S rw		IC[1]F rw				IC[1]PSC rw		CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

IC[2]F

Bits 15-18: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC[2]CE rw	OC[2]M rw			OC[2]PE rw	OC[2]FE rw	CC[2]S rw		OC[1]CE rw	OC[1]M rw			OC[1]PE rw	OC[1]FE rw	CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													IC[4]F rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC[4]F rw				IC[4]PSC rw		CC[4]S rw		IC[3]F rw				IC[3]PSC rw		CC[3]S rw

Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0x0-0x3

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values: 0x0-0xf

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0x0-0x3

IC[4]F

Bits 15-18: Input capture 4 filter.

Allowed values: 0x0-0xf

CCMR2_Output

capture/compare mode register (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC[4]CE rw	OC[4]M rw			OC[4]PE rw	OC[4]FE rw	CC[4]S rw		OC[3]CE rw	OC[3]M rw			OC[3]PE rw	OC[3]FE rw	CC[3]S rw

Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CC[4]P rw	CC[4]E rw	CC[3]NP rw	CC[3]NE rw	CC[3]P rw	CC[3]E rw	CC[2]NP rw	CC[2]NE rw	CC[2]P rw	CC[2]E rw	CC[1]NP rw	CC[1]NE rw	CC[1]P rw	CC[1]E rw

Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[1]NE

Bit 2: Capture/Compare 1 complementary output enable.

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

CC[2]NE

Bit 6: Capture/Compare 2 complementary output enable.

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CC[3]E

Bit 8: Capture/Compare 3 output enable.

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

CC[3]NE

Bit 10: Capture/Compare 3 complementary output enable.

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

CC[4]E

Bit 12: Capture/Compare 4 output enable.

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle fields

CNT

Bits 0-15: counter value.

Allowed values: 0x0-0xffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REP rw

Toggle fields

REP

Bits 0-7: Repetition counter value.

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MOE rw	AOE rw	BKP rw	BKE rw	OSSR rw	OSSI rw	LOCK rw		DTG rw

Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

Allowed values: 0x0-0xff

LOCK

Bits 8-9: Lock configuration.

Allowed values:
0: Off: No bit is write protected
1: Level1: Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
2: Level2: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
3: Level3: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written

OSSI

Bit 10: Off-state selection for Idle mode.

Allowed values:
0: Disabled: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are forced to idle level

OSSR

Bit 11: Off-state selection for Run mode.

Allowed values:
0: Disabled: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are enabled with their inactive level

BKE

Bit 12: Break enable.

Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x disabled

BKP

Bit 13: Break polarity.

Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high

AOE

Bit 14: Automatic output enable.

Allowed values:
0: Manual: MOE can be set only by software
1: Automatic: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)

MOE

Bit 15: Main output enable.

Allowed values:
0: DisabledIdle: OC/OCN are disabled or forced idle depending on OSSI
1: Enabled: OC/OCN are enabled if CCxE/CCxNE are set

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

TIM12

0x40001800: General purpose timer

12/49 fields covered.

Toggle register map

Offset	Name	15	14	11	10	9	7	6	5	4	3	2	1	0
0x0	CR1					CKD	ARPE				OPM	URS	UDIS	CEN
0x4	CR2							MMS
0x8	SMCR						MSM	TS				SMS
0xc	DIER							TIE				CC[2]IE	CC[1]IE	UIE
0x10	SR				CC[2]OF	CC[1]OF		TIF				CC[2]IF	CC[1]IF	UIF
0x14	EGR							TG				CC[2]G	CC[1]G	UG
0x18	CCMR1_Input	IC[2]F		IC[2]PSC		CC[2]S	IC[1]F				IC[1]PSC		CC[1]S
0x18	CCMR1_Output		OC[2]M	OC[2]PE	OC[2]FE	CC[2]S		OC[1]M			OC[1]PE	OC[1]FE	CC[1]S
0x20	CCER						CC[2]NP		CC[2]P	CC[2]E	CC[1]NP		CC[1]P	CC[1]E
0x24	CNT	CNT
0x28	PSC	PSC
0x2c	ARR	ARR
0x34	CCR[1]	CCR
0x38	CCR[2]	CCR

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CKD rw		ARPE rw				OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									MMS rw

Toggle fields

MMS

Bits 4-6: Master mode selection.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								MSM rw	TS rw				SMS rw

Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									TIE rw				CC[2]IE rw	CC[1]IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					CC[2]OF rw	CC[1]OF rw			TIF rw				CC[2]IF rw	CC[1]IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

1/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									TG w				CC[2]G w	CC[1]G w	UG w

Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

CC[2]G

Bit 2: Capture/compare 2 generation.

TG

Bit 6: Trigger generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC[2]F rw				IC[2]PSC rw		CC[2]S rw		IC[1]F rw				IC[1]PSC rw		CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

IC[2]F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

2/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	OC[2]M rw			OC[2]PE rw	OC[2]FE rw	CC[2]S rw			OC[1]M rw			OC[1]PE rw	OC[1]FE rw	CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

OC[2]FE

Bit 10: Output compare 2 fast enable.

OC[2]PE

Bit 11: Output compare 2 preload enable.

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								CC[2]NP rw		CC[2]P rw	CC[2]E rw	CC[1]NP rw		CC[1]P rw	CC[1]E rw

Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle fields

CNT

Bits 0-15: counter value.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-15: Auto-reload value.

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

TIM13

0x40001c00: General purpose timer

11/27 fields covered.

Toggle register map

Offset	Name	15	9	7	6	3	2	1	0
0x0	CR1		CKD	ARPE		OPM	URS	UDIS	CEN
0xc	DIER							CC[1]IE	UIE
0x10	SR		CC[1]OF					CC[1]IF	UIF
0x14	EGR							CC[1]G	UG
0x18	CCMR1_Input			IC[1]F		IC[1]PSC		CC[1]S
0x18	CCMR1_Output				OC[1]M	OC[1]PE	OC[1]FE	CC[1]S
0x20	CCER					CC[1]NP		CC[1]P	CC[1]E
0x24	CNT	CNT
0x28	PSC	PSC
0x2c	ARR	ARR
0x34	CCR[1]	CCR

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CKD rw		ARPE rw				OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CC[1]IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC[1]OF rw								CC[1]IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

1/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CC[1]G w	UG w

Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

CCMR1_Input

capture/compare mode register (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IC[1]F rw				IC[1]PSC rw		CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OC[1]M rw			OC[1]PE rw	OC[1]FE rw	CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												CC[1]NP rw		CC[1]P rw	CC[1]E rw

Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle fields

CNT

Bits 0-15: counter value.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-15: Auto-reload value.

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

TIM14

0x40002000: General purpose timer

11/27 fields covered.

Toggle register map

Offset	Name	15	9	7	6	3	2	1	0
0x0	CR1		CKD	ARPE		OPM	URS	UDIS	CEN
0xc	DIER							CC[1]IE	UIE
0x10	SR		CC[1]OF					CC[1]IF	UIF
0x14	EGR							CC[1]G	UG
0x18	CCMR1_Input			IC[1]F		IC[1]PSC		CC[1]S
0x18	CCMR1_Output				OC[1]M	OC[1]PE	OC[1]FE	CC[1]S
0x20	CCER					CC[1]NP		CC[1]P	CC[1]E
0x24	CNT	CNT
0x28	PSC	PSC
0x2c	ARR	ARR
0x34	CCR[1]	CCR

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CKD rw		ARPE rw				OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CC[1]IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC[1]OF rw								CC[1]IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

1/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CC[1]G w	UG w

Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

CCMR1_Input

capture/compare mode register (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IC[1]F rw				IC[1]PSC rw		CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OC[1]M rw			OC[1]PE rw	OC[1]FE rw	CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												CC[1]NP rw		CC[1]P rw	CC[1]E rw

Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle fields

CNT

Bits 0-15: counter value.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-15: Auto-reload value.

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

TIM15

0x40014000: General purpose timers

12/78 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1							CKD		ARPE				OPM	URS	UDIS	CEN
0x4	CR2						OIS2	OIS1N	OIS1		MMS			CCDS	CCUS		CCPC
0x8	SMCR									MSM	TS				SMS
0xc	DIER		TDE				CC[2]DE	CC[1]DE	UDE	BIE	TIE	COMIE			CC[2]IE	CC[1]IE	UIE
0x10	SR						CC[2]OF	CC[1]OF		BIF	TIF	COMIF			CC[2]IF	CC[1]IF	UIF
0x14	EGR									BG	TG	COMG			CC[2]G	CC[1]G	UG
0x18	CCMR1_Input	IC[2]F				IC[2]PSC		CC[2]S		IC[1]F				IC[1]PSC		CC[1]S
0x18	CCMR1_Output		OC[2]M			OC[2]PE	OC[2]FE	CC[2]S			OC[1]M			OC[1]PE	OC[1]FE	CC[1]S
0x20	CCER									CC[2]NP		CC[2]P	CC[2]E	CC[1]NP	CC[1]NE	CC[1]P	CC[1]E
0x24	CNT	CNT
0x28	PSC	PSC
0x2c	ARR	ARR
0x30	RCR									REP
0x34	CCR[1]	CCR
0x38	CCR[2]	CCR
0x44	BDTR	MOE	AOE	BKP	BKE	OSSR	OSSI	LOCK		DTG
0x48	DCR				DBL								DBA
0x4c	DMAR	DMAB

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CKD rw		ARPE rw				OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					OIS2 rw	OIS1N rw	OIS1 rw		MMS rw			CCDS rw	CCUS rw		CCPC rw

Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection.

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

OIS2

Bit 10: Output Idle state 2.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								MSM rw	TS rw				SMS rw

Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDE rw				CC[2]DE rw	CC[1]DE rw	UDE rw	BIE rw	TIE rw	COMIE rw			CC[2]IE rw	CC[1]IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					CC[2]OF rw	CC[1]OF rw		BIF rw	TIF rw	COMIF rw			CC[2]IF rw	CC[1]IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

BIF

Bit 7: Break interrupt flag.

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

1/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								BG w	TG w	COMG w			CC[2]G w	CC[1]G w	UG w

Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

CC[2]G

Bit 2: Capture/compare 2 generation.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC[2]F rw				IC[2]PSC rw		CC[2]S rw		IC[1]F rw				IC[1]PSC rw		CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

IC[2]F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

2/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	OC[2]M rw			OC[2]PE rw	OC[2]FE rw	CC[2]S rw			OC[1]M rw			OC[1]PE rw	OC[1]FE rw	CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

OC[2]FE

Bit 10: Output compare 2 fast enable.

OC[2]PE

Bit 11: Output compare 2 preload enable.

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								CC[2]NP rw		CC[2]P rw	CC[2]E rw	CC[1]NP rw	CC[1]NE rw	CC[1]P rw	CC[1]E rw

Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[1]NE

Bit 2: Capture/Compare 1 complementary output enable.

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle fields

CNT

Bits 0-15: counter value.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REP rw

Toggle fields

REP

Bits 0-7: Repetition counter value.

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MOE rw	AOE rw	BKP rw	BKE rw	OSSR rw	OSSI rw	LOCK rw		DTG rw

Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

TIM16

0x40014400: General-purpose-timers

20/57 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1							CKD		ARPE				OPM	URS	UDIS	CEN
0x4	CR2							OIS1N	OIS1					CCDS	CCUS		CCPC
0xc	DIER		TDE					CC[1]DE	UDE	BIE	TIE	COMIE				CC[1]IE	UIE
0x10	SR							CC[1]OF		BIF	TIF	COMIF				CC[1]IF	UIF
0x14	EGR									BG	TG	COMG				CC[1]G	UG
0x18	CCMR1_Input									IC[1]F				IC[1]PSC		CC[1]S
0x18	CCMR1_Output										OC[1]M			OC[1]PE	OC[1]FE	CC[1]S
0x20	CCER													CC[1]NP	CC[1]NE	CC[1]P	CC[1]E
0x24	CNT	CNT
0x28	PSC	PSC
0x2c	ARR	ARR
0x30	RCR									REP
0x34	CCR[1]	CCR
0x44	BDTR	MOE	AOE	BKP	BKE	OSSR	OSSI	LOCK		DTG
0x48	DCR				DBL								DBA
0x4c	DMAR	DMAB

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CKD rw		ARPE rw				OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						OIS1N rw	OIS1 rw					CCDS rw	CCUS rw		CCPC rw

Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

Allowed values:
0: NotPreloaded: CCxE, CCxNE and OCxM bits are not preloaded
1: Preloaded: CCxE, CCxNE and OCxM bits are preloaded

CCUS

Bit 2: Capture/compare control update selection.

Allowed values:
0: Default: Capture/compare are updated only by setting the COMG bit
1: WithRisingEdge: Capture/compare are updated by setting the COMG bit or when an rising edge occurs on TRGI

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

OIS1

Bit 8: Output Idle state 1.

Allowed values:
0: Reset: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
1: Set: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0

OIS1N

Bit 9: Output Idle state 1.

Allowed values:
0: Reset: OC1N=0 after a dead-time when MOE=0
1: Set: OC1N=1 after a dead-time when MOE=0

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

5/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDE rw					CC[1]DE rw	UDE rw	BIE rw	TIE rw	COMIE rw				CC[1]IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CC1 interrupt disabled
1: Enabled: CC1 interrupt enabled

COMIE

Bit 5: COM interrupt enable.

Allowed values:
0: Disabled: COM interrupt disabled
1: Enabled: COM interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

BIE

Bit 7: Break interrupt enable.

Allowed values:
0: Disabled: Break interrupt disabled
1: Enabled: Break interrupt enabled

UDE

Bit 8: Update DMA request enable.

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CC1 DMA request disabled
1: Enabled: CC1 DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC[1]OF rw		BIF rw	TIF rw	COMIF rw				CC[1]IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

BIF

Bit 7: Break interrupt flag.

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

1/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								BG w	TG w	COMG w				CC[1]G w	UG w

Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IC[1]F rw				IC[1]PSC rw		CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OC[1]M rw			OC[1]PE rw	OC[1]FE rw	CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												CC[1]NP rw	CC[1]NE rw	CC[1]P rw	CC[1]E rw

Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[1]NE

Bit 2: Capture/Compare 1 complementary output enable.

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle fields

CNT

Bits 0-15: counter value.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REP rw

Toggle fields

REP

Bits 0-7: Repetition counter value.

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MOE rw	AOE rw	BKP rw	BKE rw	OSSR rw	OSSI rw	LOCK rw		DTG rw

Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

TIM17

0x40014800: General-purpose-timers

20/57 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1							CKD		ARPE				OPM	URS	UDIS	CEN
0x4	CR2							OIS1N	OIS1					CCDS	CCUS		CCPC
0xc	DIER		TDE					CC[1]DE	UDE	BIE	TIE	COMIE				CC[1]IE	UIE
0x10	SR							CC[1]OF		BIF	TIF	COMIF				CC[1]IF	UIF
0x14	EGR									BG	TG	COMG				CC[1]G	UG
0x18	CCMR1_Input									IC[1]F				IC[1]PSC		CC[1]S
0x18	CCMR1_Output										OC[1]M			OC[1]PE	OC[1]FE	CC[1]S
0x20	CCER													CC[1]NP	CC[1]NE	CC[1]P	CC[1]E
0x24	CNT	CNT
0x28	PSC	PSC
0x2c	ARR	ARR
0x30	RCR									REP
0x34	CCR[1]	CCR
0x44	BDTR	MOE	AOE	BKP	BKE	OSSR	OSSI	LOCK		DTG
0x48	DCR				DBL								DBA
0x4c	DMAR	DMAB

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CKD rw		ARPE rw				OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						OIS1N rw	OIS1 rw					CCDS rw	CCUS rw		CCPC rw

Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

Allowed values:
0: NotPreloaded: CCxE, CCxNE and OCxM bits are not preloaded
1: Preloaded: CCxE, CCxNE and OCxM bits are preloaded

CCUS

Bit 2: Capture/compare control update selection.

Allowed values:
0: Default: Capture/compare are updated only by setting the COMG bit
1: WithRisingEdge: Capture/compare are updated by setting the COMG bit or when an rising edge occurs on TRGI

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

OIS1

Bit 8: Output Idle state 1.

Allowed values:
0: Reset: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
1: Set: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0

OIS1N

Bit 9: Output Idle state 1.

Allowed values:
0: Reset: OC1N=0 after a dead-time when MOE=0
1: Set: OC1N=1 after a dead-time when MOE=0

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

5/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDE rw					CC[1]DE rw	UDE rw	BIE rw	TIE rw	COMIE rw				CC[1]IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CC1 interrupt disabled
1: Enabled: CC1 interrupt enabled

COMIE

Bit 5: COM interrupt enable.

Allowed values:
0: Disabled: COM interrupt disabled
1: Enabled: COM interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

BIE

Bit 7: Break interrupt enable.

Allowed values:
0: Disabled: Break interrupt disabled
1: Enabled: Break interrupt enabled

UDE

Bit 8: Update DMA request enable.

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CC1 DMA request disabled
1: Enabled: CC1 DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC[1]OF rw		BIF rw	TIF rw	COMIF rw				CC[1]IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

BIF

Bit 7: Break interrupt flag.

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

1/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								BG w	TG w	COMG w				CC[1]G w	UG w

Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IC[1]F rw				IC[1]PSC rw		CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OC[1]M rw			OC[1]PE rw	OC[1]FE rw	CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												CC[1]NP rw	CC[1]NE rw	CC[1]P rw	CC[1]E rw

Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[1]NE

Bit 2: Capture/Compare 1 complementary output enable.

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle fields

CNT

Bits 0-15: counter value.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REP rw

Toggle fields

REP

Bits 0-7: Repetition counter value.

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MOE rw	AOE rw	BKP rw	BKE rw	OSSR rw	OSSI rw	LOCK rw		DTG rw

Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

TIM2

0x40000000: General purpose timer

77/97 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1							CKD		ARPE	CMS		DIR	OPM	URS	UDIS	CEN
0x4	CR2									TI1S	MMS			CCDS
0x8	SMCR	ETP	ECE	ETPS		ETF				MSM	TS			OCCS	SMS
0xc	DIER		TDE		CC[4]DE	CC[3]DE	CC[2]DE	CC[1]DE	UDE		TIE		CC[4]IE	CC[3]IE	CC[2]IE	CC[1]IE	UIE
0x10	SR				CC[4]OF	CC[3]OF	CC[2]OF	CC[1]OF			TIF		CC[4]IF	CC[3]IF	CC[2]IF	CC[1]IF	UIF
0x14	EGR										TG		CC[4]G	CC[3]G	CC[2]G	CC[1]G	UG
0x18	CCMR1_Input	IC[2]F				IC[2]PSC		CC[2]S		IC[1]F				IC[1]PSC		CC[1]S
0x18	CCMR1_Output	OC[2]CE	OC[2]M			OC[2]PE	OC[2]FE	CC[2]S		OC[1]CE	OC[1]M			OC[1]PE	OC[1]FE	CC[1]S
0x1c	CCMR2_Input	IC[4]F				IC[4]PSC		CC[4]S		IC[3]F				IC[3]PSC		CC[3]S
0x1c	CCMR2_Output	OC[4]CE	OC[4]M			OC[4]PE	OC[4]FE	CC[4]S		OC[3]CE	OC[3]M			OC[3]PE	OC[3]FE	CC[3]S
0x20	CCER			CC[4]P	CC[4]E			CC[3]P	CC[3]E			CC[2]P	CC[2]E			CC[1]P	CC[1]E
0x24	CNT	CNT
0x28	PSC	PSC
0x2c	ARR	ARR
0x34	CCR[1]	CCR
0x38	CCR[2]	CCR
0x3c	CCR[3]	CCR
0x40	CCR[4]	CCR
0x48	DCR				DBL								DBA
0x4c	DMAR	DMAB

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CKD rw		ARPE rw	CMS rw		DIR rw	OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TI1S rw	MMS rw			CCDS rw

Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

7/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETP rw	ECE rw	ETPS rw		ETF rw				MSM rw	TS rw			OCCS rw	SMS rw

Toggle fields

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

OCCS

Bit 3: OCREF clear selection.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDE rw		CC[4]DE rw	CC[3]DE rw	CC[2]DE rw	CC[1]DE rw	UDE rw		TIE rw		CC[4]IE rw	CC[3]IE rw	CC[2]IE rw	CC[1]IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CC[4]OF rw	CC[3]OF rw	CC[2]OF rw	CC[1]OF rw			TIF rw		CC[4]IF rw	CC[3]IF rw	CC[2]IF rw	CC[1]IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									TG w		CC[4]G w	CC[3]G w	CC[2]G w	CC[1]G w	UG w

Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC[2]F rw				IC[2]PSC rw		CC[2]S rw		IC[1]F rw				IC[1]PSC rw		CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC[2]CE rw	OC[2]M rw			OC[2]PE rw	OC[2]FE rw	CC[2]S rw		OC[1]CE rw	OC[1]M rw			OC[1]PE rw	OC[1]FE rw	CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC[4]F rw				IC[4]PSC rw		CC[4]S rw		IC[3]F rw				IC[3]PSC rw		CC[3]S rw

Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0x0-0x3

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values: 0x0-0xf

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0x0-0x3

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values: 0x0-0xf

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC[4]CE rw	OC[4]M rw			OC[4]PE rw	OC[4]FE rw	CC[4]S rw		OC[3]CE rw	OC[3]M rw			OC[3]PE rw	OC[3]FE rw	CC[3]S rw

Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CC[4]P rw	CC[4]E rw			CC[3]P rw	CC[3]E rw			CC[2]P rw	CC[2]E rw			CC[1]P rw	CC[1]E rw

Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

CC[3]E

Bit 8: Capture/Compare 3 output enable.

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

CC[4]E

Bit 12: Capture/Compare 4 output enable.

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle fields

CNT

Bits 0-15: counter value.

Allowed values: 0x0-0xffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

TIM3

0x40000400: General purpose timer

77/97 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1							CKD		ARPE	CMS		DIR	OPM	URS	UDIS	CEN
0x4	CR2									TI1S	MMS			CCDS
0x8	SMCR	ETP	ECE	ETPS		ETF				MSM	TS			OCCS	SMS
0xc	DIER		TDE		CC[4]DE	CC[3]DE	CC[2]DE	CC[1]DE	UDE		TIE		CC[4]IE	CC[3]IE	CC[2]IE	CC[1]IE	UIE
0x10	SR				CC[4]OF	CC[3]OF	CC[2]OF	CC[1]OF			TIF		CC[4]IF	CC[3]IF	CC[2]IF	CC[1]IF	UIF
0x14	EGR										TG		CC[4]G	CC[3]G	CC[2]G	CC[1]G	UG
0x18	CCMR1_Input	IC[2]F				IC[2]PSC		CC[2]S		IC[1]F				IC[1]PSC		CC[1]S
0x18	CCMR1_Output	OC[2]CE	OC[2]M			OC[2]PE	OC[2]FE	CC[2]S		OC[1]CE	OC[1]M			OC[1]PE	OC[1]FE	CC[1]S
0x1c	CCMR2_Input	IC[4]F				IC[4]PSC		CC[4]S		IC[3]F				IC[3]PSC		CC[3]S
0x1c	CCMR2_Output	OC[4]CE	OC[4]M			OC[4]PE	OC[4]FE	CC[4]S		OC[3]CE	OC[3]M			OC[3]PE	OC[3]FE	CC[3]S
0x20	CCER			CC[4]P	CC[4]E			CC[3]P	CC[3]E			CC[2]P	CC[2]E			CC[1]P	CC[1]E
0x24	CNT	CNT
0x28	PSC	PSC
0x2c	ARR	ARR
0x34	CCR[1]	CCR
0x38	CCR[2]	CCR
0x3c	CCR[3]	CCR
0x40	CCR[4]	CCR
0x48	DCR				DBL								DBA
0x4c	DMAR	DMAB

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CKD rw		ARPE rw	CMS rw		DIR rw	OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TI1S rw	MMS rw			CCDS rw

Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

7/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETP rw	ECE rw	ETPS rw		ETF rw				MSM rw	TS rw			OCCS rw	SMS rw

Toggle fields

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

OCCS

Bit 3: OCREF clear selection.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDE rw		CC[4]DE rw	CC[3]DE rw	CC[2]DE rw	CC[1]DE rw	UDE rw		TIE rw		CC[4]IE rw	CC[3]IE rw	CC[2]IE rw	CC[1]IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CC[4]OF rw	CC[3]OF rw	CC[2]OF rw	CC[1]OF rw			TIF rw		CC[4]IF rw	CC[3]IF rw	CC[2]IF rw	CC[1]IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									TG w		CC[4]G w	CC[3]G w	CC[2]G w	CC[1]G w	UG w

Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC[2]F rw				IC[2]PSC rw		CC[2]S rw		IC[1]F rw				IC[1]PSC rw		CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC[2]CE rw	OC[2]M rw			OC[2]PE rw	OC[2]FE rw	CC[2]S rw		OC[1]CE rw	OC[1]M rw			OC[1]PE rw	OC[1]FE rw	CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC[4]F rw				IC[4]PSC rw		CC[4]S rw		IC[3]F rw				IC[3]PSC rw		CC[3]S rw

Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0x0-0x3

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values: 0x0-0xf

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0x0-0x3

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values: 0x0-0xf

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC[4]CE rw	OC[4]M rw			OC[4]PE rw	OC[4]FE rw	CC[4]S rw		OC[3]CE rw	OC[3]M rw			OC[3]PE rw	OC[3]FE rw	CC[3]S rw

Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CC[4]P rw	CC[4]E rw			CC[3]P rw	CC[3]E rw			CC[2]P rw	CC[2]E rw			CC[1]P rw	CC[1]E rw

Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

CC[3]E

Bit 8: Capture/Compare 3 output enable.

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

CC[4]E

Bit 12: Capture/Compare 4 output enable.

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle fields

CNT

Bits 0-15: counter value.

Allowed values: 0x0-0xffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

TIM4

0x40000800: General purpose timer

77/97 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1							CKD		ARPE	CMS		DIR	OPM	URS	UDIS	CEN
0x4	CR2									TI1S	MMS			CCDS
0x8	SMCR	ETP	ECE	ETPS		ETF				MSM	TS			OCCS	SMS
0xc	DIER		TDE		CC[4]DE	CC[3]DE	CC[2]DE	CC[1]DE	UDE		TIE		CC[4]IE	CC[3]IE	CC[2]IE	CC[1]IE	UIE
0x10	SR				CC[4]OF	CC[3]OF	CC[2]OF	CC[1]OF			TIF		CC[4]IF	CC[3]IF	CC[2]IF	CC[1]IF	UIF
0x14	EGR										TG		CC[4]G	CC[3]G	CC[2]G	CC[1]G	UG
0x18	CCMR1_Input	IC[2]F				IC[2]PSC		CC[2]S		IC[1]F				IC[1]PSC		CC[1]S
0x18	CCMR1_Output	OC[2]CE	OC[2]M			OC[2]PE	OC[2]FE	CC[2]S		OC[1]CE	OC[1]M			OC[1]PE	OC[1]FE	CC[1]S
0x1c	CCMR2_Input	IC[4]F				IC[4]PSC		CC[4]S		IC[3]F				IC[3]PSC		CC[3]S
0x1c	CCMR2_Output	OC[4]CE	OC[4]M			OC[4]PE	OC[4]FE	CC[4]S		OC[3]CE	OC[3]M			OC[3]PE	OC[3]FE	CC[3]S
0x20	CCER			CC[4]P	CC[4]E			CC[3]P	CC[3]E			CC[2]P	CC[2]E			CC[1]P	CC[1]E
0x24	CNT	CNT
0x28	PSC	PSC
0x2c	ARR	ARR
0x34	CCR[1]	CCR
0x38	CCR[2]	CCR
0x3c	CCR[3]	CCR
0x40	CCR[4]	CCR
0x48	DCR				DBL								DBA
0x4c	DMAR	DMAB

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CKD rw		ARPE rw	CMS rw		DIR rw	OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TI1S rw	MMS rw			CCDS rw

Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

7/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETP rw	ECE rw	ETPS rw		ETF rw				MSM rw	TS rw			OCCS rw	SMS rw

Toggle fields

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

OCCS

Bit 3: OCREF clear selection.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDE rw		CC[4]DE rw	CC[3]DE rw	CC[2]DE rw	CC[1]DE rw	UDE rw		TIE rw		CC[4]IE rw	CC[3]IE rw	CC[2]IE rw	CC[1]IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CC[4]OF rw	CC[3]OF rw	CC[2]OF rw	CC[1]OF rw			TIF rw		CC[4]IF rw	CC[3]IF rw	CC[2]IF rw	CC[1]IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									TG w		CC[4]G w	CC[3]G w	CC[2]G w	CC[1]G w	UG w

Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC[2]F rw				IC[2]PSC rw		CC[2]S rw		IC[1]F rw				IC[1]PSC rw		CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC[2]CE rw	OC[2]M rw			OC[2]PE rw	OC[2]FE rw	CC[2]S rw		OC[1]CE rw	OC[1]M rw			OC[1]PE rw	OC[1]FE rw	CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC[4]F rw				IC[4]PSC rw		CC[4]S rw		IC[3]F rw				IC[3]PSC rw		CC[3]S rw

Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0x0-0x3

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values: 0x0-0xf

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0x0-0x3

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values: 0x0-0xf

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC[4]CE rw	OC[4]M rw			OC[4]PE rw	OC[4]FE rw	CC[4]S rw		OC[3]CE rw	OC[3]M rw			OC[3]PE rw	OC[3]FE rw	CC[3]S rw

Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CC[4]P rw	CC[4]E rw			CC[3]P rw	CC[3]E rw			CC[2]P rw	CC[2]E rw			CC[1]P rw	CC[1]E rw

Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

CC[3]E

Bit 8: Capture/Compare 3 output enable.

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

CC[4]E

Bit 12: Capture/Compare 4 output enable.

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle fields

CNT

Bits 0-15: counter value.

Allowed values: 0x0-0xffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

TIM5

0x40000c00: General purpose timer

77/97 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1							CKD		ARPE	CMS		DIR	OPM	URS	UDIS	CEN
0x4	CR2									TI1S	MMS			CCDS
0x8	SMCR	ETP	ECE	ETPS		ETF				MSM	TS			OCCS	SMS
0xc	DIER		TDE		CC[4]DE	CC[3]DE	CC[2]DE	CC[1]DE	UDE		TIE		CC[4]IE	CC[3]IE	CC[2]IE	CC[1]IE	UIE
0x10	SR				CC[4]OF	CC[3]OF	CC[2]OF	CC[1]OF			TIF		CC[4]IF	CC[3]IF	CC[2]IF	CC[1]IF	UIF
0x14	EGR										TG		CC[4]G	CC[3]G	CC[2]G	CC[1]G	UG
0x18	CCMR1_Input	IC[2]F				IC[2]PSC		CC[2]S		IC[1]F				IC[1]PSC		CC[1]S
0x18	CCMR1_Output	OC[2]CE	OC[2]M			OC[2]PE	OC[2]FE	CC[2]S		OC[1]CE	OC[1]M			OC[1]PE	OC[1]FE	CC[1]S
0x1c	CCMR2_Input	IC[4]F				IC[4]PSC		CC[4]S		IC[3]F				IC[3]PSC		CC[3]S
0x1c	CCMR2_Output	OC[4]CE	OC[4]M			OC[4]PE	OC[4]FE	CC[4]S		OC[3]CE	OC[3]M			OC[3]PE	OC[3]FE	CC[3]S
0x20	CCER			CC[4]P	CC[4]E			CC[3]P	CC[3]E			CC[2]P	CC[2]E			CC[1]P	CC[1]E
0x24	CNT	CNT
0x28	PSC	PSC
0x2c	ARR	ARR
0x34	CCR[1]	CCR
0x38	CCR[2]	CCR
0x3c	CCR[3]	CCR
0x40	CCR[4]	CCR
0x48	DCR				DBL								DBA
0x4c	DMAR	DMAB

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CKD rw		ARPE rw	CMS rw		DIR rw	OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TI1S rw	MMS rw			CCDS rw

Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

7/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETP rw	ECE rw	ETPS rw		ETF rw				MSM rw	TS rw			OCCS rw	SMS rw

Toggle fields

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

OCCS

Bit 3: OCREF clear selection.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDE rw		CC[4]DE rw	CC[3]DE rw	CC[2]DE rw	CC[1]DE rw	UDE rw		TIE rw		CC[4]IE rw	CC[3]IE rw	CC[2]IE rw	CC[1]IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CC[4]OF rw	CC[3]OF rw	CC[2]OF rw	CC[1]OF rw			TIF rw		CC[4]IF rw	CC[3]IF rw	CC[2]IF rw	CC[1]IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									TG w		CC[4]G w	CC[3]G w	CC[2]G w	CC[1]G w	UG w

Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC[2]F rw				IC[2]PSC rw		CC[2]S rw		IC[1]F rw				IC[1]PSC rw		CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC[2]CE rw	OC[2]M rw			OC[2]PE rw	OC[2]FE rw	CC[2]S rw		OC[1]CE rw	OC[1]M rw			OC[1]PE rw	OC[1]FE rw	CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC[4]F rw				IC[4]PSC rw		CC[4]S rw		IC[3]F rw				IC[3]PSC rw		CC[3]S rw

Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0x0-0x3

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values: 0x0-0xf

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0x0-0x3

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values: 0x0-0xf

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC[4]CE rw	OC[4]M rw			OC[4]PE rw	OC[4]FE rw	CC[4]S rw		OC[3]CE rw	OC[3]M rw			OC[3]PE rw	OC[3]FE rw	CC[3]S rw

Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CC[4]P rw	CC[4]E rw			CC[3]P rw	CC[3]E rw			CC[2]P rw	CC[2]E rw			CC[1]P rw	CC[1]E rw

Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

CC[3]E

Bit 8: Capture/Compare 3 output enable.

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

CC[4]E

Bit 12: Capture/Compare 4 output enable.

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle fields

CNT

Bits 0-15: counter value.

Allowed values: 0x0-0xffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

TIM6

0x40001000: Basic timer

13/13 fields covered.

Toggle register map

Offset	Name	15	8	7	6	3	2	1	0
0x0	CR1			ARPE		OPM	URS	UDIS	CEN
0x4	CR2				MMS
0xc	DIER		UDE						UIE
0x10	SR								UIF
0x14	EGR								UG
0x24	CNT	CNT
0x28	PSC	PSC
0x2c	ARR	ARR

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								ARPE rw				OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									MMS rw

Toggle fields

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: Use UG bit from TIMx_EGR register
1: Enable: Use CNT bit from TIMx_CEN register
2: Update: Use the update event

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							UDE rw								UIE rw

Toggle fields

UIE

Offset	Name	15	8	7	6	3	2	1	0
0x0	CR1			ARPE		OPM	URS	UDIS	CEN
0x4	CR2				MMS
0xc	DIER		UDE						UIE
0x10	SR								UIF
0x14	EGR								UG
0x24	CNT	CNT
0x28	PSC	PSC
0x2c	ARR	ARR

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								ARPE rw				OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									MMS rw

Toggle fields

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: Use UG bit from TIMx_EGR register
1: Enable: Use CNT bit from TIMx_CEN register
2: Update: Use the update event

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							UDE rw								UIE rw

Toggle fields

UIE

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	SR								LBD	TXE	TC	RXNE	IDLE	ORE	NE	FE	PE
0x4	DR								DR
0x8	BRR	DIV_Mantissa												DIV_Fraction
0xc	CR1			UE	M	WAKE	PCE	PS	PEIE	TXEIE	TCIE	RXNEIE	IDLEIE	TE	RE	RWU	SBK
0x10	CR2		LINEN	STOP							LBDIE	LBDL		ADD
0x14	CR3									DMAT	DMAR			HDSEL	IRLP	IREN	EIE

Toggle registers

SR

Status register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

6/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							LBD rw	TXE r	TC rw	RXNE rw	IDLE r	ORE r	NE r	FE r	PE r

Toggle fields

PE

Bit 0: Parity error.

FE

Bit 1: Framing error.

NE

Bit 2: Noise error flag.

ORE

Bit 3: Overrun error.

IDLE

Bit 4: IDLE line detected.

RXNE

Bit 5: Read data register not empty.

TC

Bit 6: Transmission complete.

TXE

Bit 7: Transmit data register empty.

LBD

Bit 8: LIN break detection flag.

DR

Data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							DR rw

Toggle fields

DR

Bits 0-8: DR.

Allowed values: 0x0-0x1ff

BRR

Baud rate register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DIV_Mantissa rw												DIV_Fraction rw

Toggle fields

DIV_Fraction

Bits 0-3: DIV_Fraction.

Allowed values: 0x0-0xf

DIV_Mantissa

Bits 4-15: DIV_Mantissa.

Allowed values: 0x0-0xfff

CR1

Control register 1

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		UE rw	M rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXEIE rw	TCIE rw	RXNEIE rw	IDLEIE rw	TE rw	RE rw	RWU rw	SBK rw

Toggle fields

SBK

Bit 0: Send break.

Allowed values:
0: NoBreak: No break character is transmitted
1: Break: Break character transmitted

RWU

Bit 1: Receiver wakeup.

Allowed values:
0: Active: Receiver in active mode
1: Mute: Receiver in mute mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver disabled
1: Enabled: Receiver enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter disabled
1: Enabled: Transmitter enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: IDLE interrupt disabled
1: Enabled: IDLE interrupt enabled

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: RXNE interrupt disabled
1: Enabled: RXNE interrupt enabled

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

TXEIE

Bit 7: TXE interrupt enable.

Allowed values:
0: Disabled: TXE interrupt disabled
1: Enabled: TXE interrupt enabled

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: PE interrupt disabled
1: Enabled: PE interrupt enabled

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Wakeup method.

Allowed values:
0: IdleLine: USART wakeup on idle line
1: AddressMark: USART wakeup on address mark

M

Bit 12: Word length.

Allowed values:
0: M8: 8 data bits
1: M9: 9 data bits

UE

Bit 13: USART enable.

Allowed values:
0: Disabled: USART prescaler and outputs disabled
1: Enabled: USART enabled

CR2

Control register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	LINEN rw	STOP rw							LBDIE rw	LBDL rw		ADD rw

Toggle fields

ADD

Bits 0-3: Address of the USART node.

Allowed values: 0x0-0xf

LBDL

Bit 5: lin break detection length.

Allowed values:
0: LBDL10: 10-bit break detection
1: LBDL11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: LIN break detection interrupt disabled
1: Enabled: LIN break detection interrupt enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
2: Stop2: 2 stop bits

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

CR3

Control register 3

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								DMAT rw	DMAR rw			HDSEL rw	IRLP rw	IREN rw	EIE rw

Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

IREN

Bit 1: IrDA mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: IrDA low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: FullDuplex: Half duplex mode is not selected
1: HalfDuplex: Half duplex mode is selected

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

UART5

0x40005000: Universal asynchronous receiver transmitter

34/37 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	SR								LBD	TXE	TC	RXNE	IDLE	ORE	NE	FE	PE
0x4	DR								DR
0x8	BRR	DIV_Mantissa												DIV_Fraction
0xc	CR1			UE	M	WAKE	PCE	PS	PEIE	TXEIE	TCIE	RXNEIE	IDLEIE	TE	RE	RWU	SBK
0x10	CR2		LINEN	STOP							LBDIE	LBDL		ADD
0x14	CR3									DMAT	DMAR			HDSEL	IRLP	IREN	EIE

Toggle registers

SR

Status register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

6/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							LBD rw	TXE r	TC rw	RXNE rw	IDLE r	ORE r	NE r	FE r	PE r

Toggle fields

PE

Bit 0: Parity error.

FE

Bit 1: Framing error.

NE

Bit 2: Noise error flag.

ORE

Bit 3: Overrun error.

IDLE

Bit 4: IDLE line detected.

RXNE

Bit 5: Read data register not empty.

TC

Bit 6: Transmission complete.

TXE

Bit 7: Transmit data register empty.

LBD

Bit 8: LIN break detection flag.

DR

Data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							DR rw

Toggle fields

DR

Bits 0-8: DR.

Allowed values: 0x0-0x1ff

BRR

Baud rate register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DIV_Mantissa rw												DIV_Fraction rw

Toggle fields

DIV_Fraction

Bits 0-3: DIV_Fraction.

Allowed values: 0x0-0xf

DIV_Mantissa

Bits 4-15: DIV_Mantissa.

Allowed values: 0x0-0xfff

CR1

Control register 1

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		UE rw	M rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXEIE rw	TCIE rw	RXNEIE rw	IDLEIE rw	TE rw	RE rw	RWU rw	SBK rw

Toggle fields

SBK

Bit 0: Send break.

Allowed values:
0: NoBreak: No break character is transmitted
1: Break: Break character transmitted

RWU

Bit 1: Receiver wakeup.

Allowed values:
0: Active: Receiver in active mode
1: Mute: Receiver in mute mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver disabled
1: Enabled: Receiver enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter disabled
1: Enabled: Transmitter enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: IDLE interrupt disabled
1: Enabled: IDLE interrupt enabled

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: RXNE interrupt disabled
1: Enabled: RXNE interrupt enabled

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

TXEIE

Bit 7: TXE interrupt enable.

Allowed values:
0: Disabled: TXE interrupt disabled
1: Enabled: TXE interrupt enabled

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: PE interrupt disabled
1: Enabled: PE interrupt enabled

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Wakeup method.

Allowed values:
0: IdleLine: USART wakeup on idle line
1: AddressMark: USART wakeup on address mark

M

Bit 12: Word length.

Allowed values:
0: M8: 8 data bits
1: M9: 9 data bits

UE

Bit 13: USART enable.

Allowed values:
0: Disabled: USART prescaler and outputs disabled
1: Enabled: USART enabled

CR2

Control register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	LINEN rw	STOP rw							LBDIE rw	LBDL rw		ADD rw

Toggle fields

ADD

Bits 0-3: Address of the USART node.

Allowed values: 0x0-0xf

LBDL

Bit 5: lin break detection length.

Allowed values:
0: LBDL10: 10-bit break detection
1: LBDL11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: LIN break detection interrupt disabled
1: Enabled: LIN break detection interrupt enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
2: Stop2: 2 stop bits

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

CR3

Control register 3

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								DMAT rw	DMAR rw			HDSEL rw	IRLP rw	IREN rw	EIE rw

Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

IREN

Bit 1: IrDA mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: IrDA low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: FullDuplex: Half duplex mode is not selected
1: HalfDuplex: Half duplex mode is selected

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

USART1

0x40013800: Universal synchronous asynchronous receiver transmitter

42/49 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	SR							CTS	LBD	TXE	TC	RXNE	IDLE	ORE	NE	FE	PE
0x4	DR								DR
0x8	BRR	DIV_Mantissa												DIV_Fraction
0xc	CR1			UE	M	WAKE	PCE	PS	PEIE	TXEIE	TCIE	RXNEIE	IDLEIE	TE	RE	RWU	SBK
0x10	CR2		LINEN	STOP		CLKEN	CPOL	CPHA	LBCL		LBDIE	LBDL		ADD
0x14	CR3						CTSIE	CTSE	RTSE	DMAT	DMAR	SCEN	NACK	HDSEL	IRLP	IREN	EIE
0x18	GTPR	GT								PSC

Toggle registers

SR

Status register

Offset: 0x0, size: 32, reset: 0x000000C0, access: Unspecified

6/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CTS rw	LBD rw	TXE r	TC rw	RXNE rw	IDLE r	ORE r	NE r	FE r	PE r

Toggle fields

PE

Bit 0: Parity error.

FE

Bit 1: Framing error.

NE

Bit 2: Noise error flag.

ORE

Bit 3: Overrun error.

IDLE

Bit 4: IDLE line detected.

RXNE

Bit 5: Read data register not empty.

TC

Bit 6: Transmission complete.

TXE

Bit 7: Transmit data register empty.

LBD

Bit 8: LIN break detection flag.

CTS

Bit 9: CTS flag.

DR

Data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							DR rw

Toggle fields

DR

Bits 0-8: Data value.

Allowed values: 0x0-0x1ff

BRR

Baud rate register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DIV_Mantissa rw												DIV_Fraction rw

Toggle fields

DIV_Fraction

Bits 0-3: fraction of USARTDIV.

Allowed values: 0x0-0xf

DIV_Mantissa

Bits 4-15: mantissa of USARTDIV.

Allowed values: 0x0-0xfff

CR1

Control register 1

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		UE rw	M rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXEIE rw	TCIE rw	RXNEIE rw	IDLEIE rw	TE rw	RE rw	RWU rw	SBK rw

Toggle fields

SBK

Bit 0: Send break.

Allowed values:
0: NoBreak: No break character is transmitted
1: Break: Break character transmitted

RWU

Bit 1: Receiver wakeup.

Allowed values:
0: Active: Receiver in active mode
1: Mute: Receiver in mute mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver disabled
1: Enabled: Receiver enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter disabled
1: Enabled: Transmitter enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: IDLE interrupt disabled
1: Enabled: IDLE interrupt enabled

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: RXNE interrupt disabled
1: Enabled: RXNE interrupt enabled

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

TXEIE

Bit 7: TXE interrupt enable.

Allowed values:
0: Disabled: TXE interrupt disabled
1: Enabled: TXE interrupt enabled

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: PE interrupt disabled
1: Enabled: PE interrupt enabled

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Wakeup method.

Allowed values:
0: IdleLine: USART wakeup on idle line
1: AddressMark: USART wakeup on address mark

M

Bit 12: Word length.

Allowed values:
0: M8: 8 data bits
1: M9: 9 data bits

UE

Bit 13: USART enable.

Allowed values:
0: Disabled: USART prescaler and outputs disabled
1: Enabled: USART enabled

CR2

Control register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

8/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	LINEN rw	STOP rw		CLKEN rw	CPOL rw	CPHA rw	LBCL rw		LBDIE rw	LBDL rw		ADD rw

Toggle fields

ADD

Bits 0-3: Address of the USART node.

Allowed values: 0x0-0xf

LBDL

Bit 5: lin break detection length.

Allowed values:
0: LBDL10: 10-bit break detection
1: LBDL11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: LIN break detection interrupt disabled
1: Enabled: LIN break detection interrupt enabled

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bits
2: Stop2: 2 stop bits
3: Stop1p5: 1.5 stop bits

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

CR3

Control register 3

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					CTSIE rw	CTSE rw	RTSE rw	DMAT rw	DMAR rw	SCEN rw	NACK rw	HDSEL rw	IRLP rw	IREN rw	EIE rw

Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

IREN

Bit 1: IrDA mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: IrDA low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: FullDuplex: Half duplex mode is not selected
1: HalfDuplex: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard mode disabled
1: Enabled: Smartcard mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS hardware flow control enabled

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS hardware flow control enabled

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: CTS interrupt disabled
1: Enabled: CTS interrupt enabled

GTPR

Guard time and prescaler register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
GT rw								PSC rw

Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

USART2

0x40004400: Universal synchronous asynchronous receiver transmitter

42/49 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	SR							CTS	LBD	TXE	TC	RXNE	IDLE	ORE	NE	FE	PE
0x4	DR								DR
0x8	BRR	DIV_Mantissa												DIV_Fraction
0xc	CR1			UE	M	WAKE	PCE	PS	PEIE	TXEIE	TCIE	RXNEIE	IDLEIE	TE	RE	RWU	SBK
0x10	CR2		LINEN	STOP		CLKEN	CPOL	CPHA	LBCL		LBDIE	LBDL		ADD
0x14	CR3						CTSIE	CTSE	RTSE	DMAT	DMAR	SCEN	NACK	HDSEL	IRLP	IREN	EIE
0x18	GTPR	GT								PSC

Toggle registers

SR

Status register

Offset: 0x0, size: 32, reset: 0x000000C0, access: Unspecified

6/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CTS rw	LBD rw	TXE r	TC rw	RXNE rw	IDLE r	ORE r	NE r	FE r	PE r

Toggle fields

PE

Bit 0: Parity error.

FE

Bit 1: Framing error.

NE

Bit 2: Noise error flag.

ORE

Bit 3: Overrun error.

IDLE

Bit 4: IDLE line detected.

RXNE

Bit 5: Read data register not empty.

TC

Bit 6: Transmission complete.

TXE

Bit 7: Transmit data register empty.

LBD

Bit 8: LIN break detection flag.

CTS

Bit 9: CTS flag.

DR

Data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							DR rw

Toggle fields

DR

Bits 0-8: Data value.

Allowed values: 0x0-0x1ff

BRR

Baud rate register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DIV_Mantissa rw												DIV_Fraction rw

Toggle fields

DIV_Fraction

Bits 0-3: fraction of USARTDIV.

Allowed values: 0x0-0xf

DIV_Mantissa

Bits 4-15: mantissa of USARTDIV.

Allowed values: 0x0-0xfff

CR1

Control register 1

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		UE rw	M rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXEIE rw	TCIE rw	RXNEIE rw	IDLEIE rw	TE rw	RE rw	RWU rw	SBK rw

Toggle fields

SBK

Bit 0: Send break.

Allowed values:
0: NoBreak: No break character is transmitted
1: Break: Break character transmitted

RWU

Bit 1: Receiver wakeup.

Allowed values:
0: Active: Receiver in active mode
1: Mute: Receiver in mute mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver disabled
1: Enabled: Receiver enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter disabled
1: Enabled: Transmitter enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: IDLE interrupt disabled
1: Enabled: IDLE interrupt enabled

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: RXNE interrupt disabled
1: Enabled: RXNE interrupt enabled

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

TXEIE

Bit 7: TXE interrupt enable.

Allowed values:
0: Disabled: TXE interrupt disabled
1: Enabled: TXE interrupt enabled

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: PE interrupt disabled
1: Enabled: PE interrupt enabled

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Wakeup method.

Allowed values:
0: IdleLine: USART wakeup on idle line
1: AddressMark: USART wakeup on address mark

M

Bit 12: Word length.

Allowed values:
0: M8: 8 data bits
1: M9: 9 data bits

UE

Bit 13: USART enable.

Allowed values:
0: Disabled: USART prescaler and outputs disabled
1: Enabled: USART enabled

CR2

Control register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

8/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	LINEN rw	STOP rw		CLKEN rw	CPOL rw	CPHA rw	LBCL rw		LBDIE rw	LBDL rw		ADD rw

Toggle fields

ADD

Bits 0-3: Address of the USART node.

Allowed values: 0x0-0xf

LBDL

Bit 5: lin break detection length.

Allowed values:
0: LBDL10: 10-bit break detection
1: LBDL11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: LIN break detection interrupt disabled
1: Enabled: LIN break detection interrupt enabled

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bits
2: Stop2: 2 stop bits
3: Stop1p5: 1.5 stop bits

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

CR3

Control register 3

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					CTSIE rw	CTSE rw	RTSE rw	DMAT rw	DMAR rw	SCEN rw	NACK rw	HDSEL rw	IRLP rw	IREN rw	EIE rw

Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

IREN

Bit 1: IrDA mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: IrDA low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: FullDuplex: Half duplex mode is not selected
1: HalfDuplex: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard mode disabled
1: Enabled: Smartcard mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS hardware flow control enabled

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS hardware flow control enabled

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: CTS interrupt disabled
1: Enabled: CTS interrupt enabled

GTPR

Guard time and prescaler register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
GT rw								PSC rw

Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

USART3

0x40004800: Universal synchronous asynchronous receiver transmitter

42/49 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	SR							CTS	LBD	TXE	TC	RXNE	IDLE	ORE	NE	FE	PE
0x4	DR								DR
0x8	BRR	DIV_Mantissa												DIV_Fraction
0xc	CR1			UE	M	WAKE	PCE	PS	PEIE	TXEIE	TCIE	RXNEIE	IDLEIE	TE	RE	RWU	SBK
0x10	CR2		LINEN	STOP		CLKEN	CPOL	CPHA	LBCL		LBDIE	LBDL		ADD
0x14	CR3						CTSIE	CTSE	RTSE	DMAT	DMAR	SCEN	NACK	HDSEL	IRLP	IREN	EIE
0x18	GTPR	GT								PSC

Toggle registers

SR

Status register

Offset: 0x0, size: 32, reset: 0x000000C0, access: Unspecified

6/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CTS rw	LBD rw	TXE r	TC rw	RXNE rw	IDLE r	ORE r	NE r	FE r	PE r

Toggle fields

PE

Bit 0: Parity error.

FE

Bit 1: Framing error.

NE

Bit 2: Noise error flag.

ORE

Bit 3: Overrun error.

IDLE

Bit 4: IDLE line detected.

RXNE

Bit 5: Read data register not empty.

TC

Bit 6: Transmission complete.

TXE

Bit 7: Transmit data register empty.

LBD

Bit 8: LIN break detection flag.

CTS

Bit 9: CTS flag.

DR

Data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							DR rw

Toggle fields

DR

Bits 0-8: Data value.

Allowed values: 0x0-0x1ff

BRR

Baud rate register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DIV_Mantissa rw												DIV_Fraction rw

Toggle fields

DIV_Fraction

Bits 0-3: fraction of USARTDIV.

Allowed values: 0x0-0xf

DIV_Mantissa

Bits 4-15: mantissa of USARTDIV.

Allowed values: 0x0-0xfff

CR1

Control register 1

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		UE rw	M rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXEIE rw	TCIE rw	RXNEIE rw	IDLEIE rw	TE rw	RE rw	RWU rw	SBK rw

Toggle fields

SBK

Bit 0: Send break.

Allowed values:
0: NoBreak: No break character is transmitted
1: Break: Break character transmitted

RWU

Bit 1: Receiver wakeup.

Allowed values:
0: Active: Receiver in active mode
1: Mute: Receiver in mute mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver disabled
1: Enabled: Receiver enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter disabled
1: Enabled: Transmitter enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: IDLE interrupt disabled
1: Enabled: IDLE interrupt enabled

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: RXNE interrupt disabled
1: Enabled: RXNE interrupt enabled

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

TXEIE

Bit 7: TXE interrupt enable.

Allowed values:
0: Disabled: TXE interrupt disabled
1: Enabled: TXE interrupt enabled

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: PE interrupt disabled
1: Enabled: PE interrupt enabled

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Wakeup method.

Allowed values:
0: IdleLine: USART wakeup on idle line
1: AddressMark: USART wakeup on address mark

M

Bit 12: Word length.

Allowed values:
0: M8: 8 data bits
1: M9: 9 data bits

UE

Bit 13: USART enable.

Allowed values:
0: Disabled: USART prescaler and outputs disabled
1: Enabled: USART enabled

CR2

Control register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

8/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	LINEN rw	STOP rw		CLKEN rw	CPOL rw	CPHA rw	LBCL rw		LBDIE rw	LBDL rw		ADD rw

Toggle fields

ADD

Bits 0-3: Address of the USART node.

Allowed values: 0x0-0xf

LBDL

Bit 5: lin break detection length.

Allowed values:
0: LBDL10: 10-bit break detection
1: LBDL11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: LIN break detection interrupt disabled
1: Enabled: LIN break detection interrupt enabled

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bits
2: Stop2: 2 stop bits
3: Stop1p5: 1.5 stop bits

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

CR3

Control register 3

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					CTSIE rw	CTSE rw	RTSE rw	DMAT rw	DMAR rw	SCEN rw	NACK rw	HDSEL rw	IRLP rw	IREN rw	EIE rw

Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

IREN

Bit 1: IrDA mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: IrDA low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: FullDuplex: Half duplex mode is not selected
1: HalfDuplex: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard mode disabled
1: Enabled: Smartcard mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS hardware flow control enabled

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS hardware flow control enabled

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: CTS interrupt disabled
1: Enabled: CTS interrupt enabled

GTPR

Guard time and prescaler register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
GT rw								PSC rw

Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

WWDG

0x40002c00: Window watchdog

6/6 fields covered.

Toggle register map

Offset	Name	9	8	7	6	0
0x0	CR			WDGA	T
0x4	CFR	EWI	WDGTB		W
0x8	SR					EWIF

Toggle registers

CR

Control register (WWDG_CR)

Offset: 0x0, size: 32, reset: 0x0000007F, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								WDGA rw	T rw

Toggle fields

T

Bits 0-6: 7-bit counter (MSB to LSB).

Allowed values: 0x0-0x7f

WDGA

Bit 7: Activation bit.

Allowed values:
0: Disabled: Watchdog disabled
1: Enabled: Watchdog enabled

CFR

Configuration register (WWDG_CFR)

Offset: 0x4, size: 32, reset: 0x0000007F, access: read-write

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EWI rw	WDGTB rw		W rw

Toggle fields

W

Bits 0-6: 7-bit window value.

Allowed values: 0x0-0x7f

WDGTB

Bits 7-8: Timer Base.

Allowed values:
0: Div1: Counter clock (PCLK1 div 4096) div 1
1: Div2: Counter clock (PCLK1 div 4096) div 2
2: Div4: Counter clock (PCLK1 div 4096) div 4
3: Div8: Counter clock (PCLK1 div 4096) div 8

EWI

Bit 9: Early Wakeup Interrupt.

Allowed values:
1: Enable: interrupt occurs whenever the counter reaches the value 0x40

SR

Status register (WWDG_SR)

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EWIF rw

Toggle fields

EWIF

Bit 0: Early Wakeup Interrupt.

Allowed values:
0: Finished: The EWI Interrupt Service Routine has been serviced
1: Pending: The EWI Interrupt Service Routine has been triggered