Overall: 3298/5101 fields covered

ADC1

0x40012400: Analog to digital converter

83/83 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 SR
0x4 CR1
0x8 CR2
0xc SMPR1
0x10 SMPR2
0x14 JOFR[1]
0x18 JOFR[2]
0x1c JOFR[3]
0x20 JOFR[4]
0x24 HTR
0x28 LTR
0x2c SQR1
0x30 SQR2
0x34 SQR3
0x38 JSQR
0x3c JDR[1]
0x40 JDR[2]
0x44 JDR[3]
0x48 JDR[4]
0x4c DR

SR

status register

Offset: 0x0, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STRT
rw 		JSTRT
rw 		JEOC
rw 		EOC
rw 		AWD
rw
Toggle Fields

AWD

Bit 0: Analog watchdog flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

EOC

Bit 1: Regular channel end of conversion.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

JEOC

Bit 2: Injected channel end of conversion.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

JSTRT

Bit 3: Injected channel start flag.

Allowed values:
0: NotStarted: No injected group conversion started
1: Started: Injected group conversion has started

STRT

Bit 4: Regular channel start flag.

Allowed values:
0: NotStarted: No regular channel conversion started
1: Started: Regular channel conversion has started

CR1

control register 1

Offset: 0x4, reset: 0x00000000, access: read-write

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDEN
rw 		JAWDEN
rw 		DUALMOD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISCNUM
rw 		JDISCEN
rw 		DISCEN
rw 		JAUTO
rw 		AWDSGL
rw 		SCAN
rw 		JEOCIE
rw 		AWDIE
rw 		EOCIE
rw 		AWDCH
rw
Toggle Fields

AWDCH

Bits 0-4: Analog watchdog channel select bits.

Allowed values: 0x0-0x11

EOCIE

Bit 5: Interrupt enable for EOC.

Allowed values:
0: Disabled: EOC interrupt disabled
1: Enabled: EOC interrupt enabled. An interrupt is generated when the EOC bit is set

AWDIE

Bit 6: Analog watchdog interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

JEOCIE

Bit 7: Interrupt enable for injected channels.

Allowed values:
0: Disabled: JEOC interrupt disabled
1: Enabled: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set

SCAN

Bit 8: Scan mode.

Allowed values:
0: Disabled: Scan mode disabled
1: Enabled: Scan mode enabled

AWDSGL

Bit 9: Enable the watchdog on a single channel in scan mode.

Allowed values:
0: All: Analog watchdog enabled on all channels
1: Single: Analog watchdog enabled on a single channel

JAUTO

Bit 10: Automatic injected group conversion.

Allowed values:
0: Disabled: Automatic injected group conversion disabled
1: Enabled: Automatic injected group conversion enabled

DISCEN

Bit 11: Discontinuous mode on regular channels.

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

JDISCEN

Bit 12: Discontinuous mode on injected channels.

Allowed values:
0: Disabled: Discontinuous mode on injected channels disabled
1: Enabled: Discontinuous mode on injected channels enabled

DISCNUM

Bits 13-15: Discontinuous mode channel count.

Allowed values: 0x0-0x7

DUALMOD

Bits 16-19: Dual mode selection.

Allowed values:
0: Independent: Independent mode
1: RegularInjected: Combined regular simultaneous + injected simultaneous mode
2: RegularAlternateTrigger: Combined regular simultaneous + alternate trigger mode
3: InjectedFastInterleaved: Combined injected simultaneous + fast interleaved mode
4: InjectedSlowInterleaved: Combined injected simultaneous + slow interleaved mode
5: Injected: Injected simultaneous mode only
6: Regular: Regular simultaneous mode only
7: FastInterleaved: Fast interleaved mode only
8: SlowInterleaved: Slow interleaved mode only
9: AlternateTrigger: Alternate trigger mode only

JAWDEN

Bit 22: Analog watchdog enable on injected channels.

Allowed values:
0: Disabled: Analog watchdog disabled on injected channels
1: Enabled: Analog watchdog enabled on injected channels

AWDEN

Bit 23: Analog watchdog enable on regular channels.

Allowed values:
0: Disabled: Analog watchdog disabled on regular channels
1: Enabled: Analog watchdog enabled on regular channels

CR2

control register 2

Offset: 0x8, reset: 0x00000000, access: read-write

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSVREFE
rw 		SWSTART
rw 		JSWSTART
rw 		EXTTRIG
rw 		EXTSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTTRIG
rw 		JEXTSEL
rw 		ALIGN
rw 		DMA
rw 		RSTCAL
rw 		CAL
rw 		CONT
rw 		ADON
rw
Toggle Fields

ADON

Bit 0: A/D converter ON / OFF.

Allowed values:
0: Disabled: Disable ADC conversion/calibration and go to power down mode
1: Enabled: Enable ADC and to start conversion

CONT

Bit 1: Continuous conversion.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

CAL

Bit 2: A/D calibration.

Allowed values:
0: Complete: Calibration completed
1: NotComplete: Calibrating

RSTCAL

Bit 3: Reset calibration.

Allowed values:
0: Initialized: Calibration register initialized
1: NotInitialized: Initializing calibration register

DMA

Bit 8: Direct memory access mode.

Allowed values:
0: Disabled: DMA mode disabled
1: Enabled: DMA mode enabled

ALIGN

Bit 11: Data alignment.

Allowed values:
0: Right: Right Alignment
1: Left: Left Alignment

JEXTSEL

Bits 12-14: External event select for injected group.

Allowed values:
0: Tim1Trgo: Timer 1 TRGO event
1: Tim1Cc4: Timer 1 CC4 event
2: Tim2Trgo: Timer 2 TRGO event
3: Tim2Cc1: Timer 2 CC1 event
4: Tim3Cc4: Timer 3 CC4 event
5: Tim4Trgo: Timer 4 TRGO event
6: Exti15: EXTI line15/TIM8_CC4 event (TIM8_CC4 is available only in high-density and XL-density devices)
7: Jswstart: JSWSTART

JEXTTRIG

Bit 15: External trigger conversion mode for injected channels.

Allowed values:
0: Disabled: Conversion on external event disabled
1: Enabled: Conversion on external event enabled

EXTSEL

Bits 17-19: External event select for regular group.

Allowed values:
0: Tim1Cc1: Timer 1 CC1 event
1: Tim1Cc2: Timer 1 CC2 event
2: Tim1Cc3: Timer 1 CC3 event
3: Tim2Cc2: Timer 2 CC2 event
4: Tim3Trgo: Timer 3 TRGO event
5: Tim4Cc4: Timer 4 CC4 event
6: Exti11: EXTI line 11/TIM8_TRGO event (TIM8_TRGO is available only in high-density and XL-density devices)
7: Swstart: SWSTART

EXTTRIG

Bit 20: External trigger conversion mode for regular channels.

Allowed values:
0: Disabled: Conversion on external event disabled
1: Enabled: Conversion on external event enabled

JSWSTART

Bit 21: Start conversion of injected channels.

Allowed values:
0: Started: Reset state
1: NotStarted: Starting conversion of injected channels

SWSTART

Bit 22: Start conversion of regular channels.

Allowed values:
0: Started: Reset state
1: NotStarted: Starting conversion of regular channels

TSVREFE

Bit 23: Temperature sensor and VREFINT enable.

Allowed values:
0: Disabled: Temperature sensor and V_REFINT channel disabled
1: Enabled: Temperature sensor and V_REFINT channel enabled

SMPR1

sample time register 1

Offset: 0xc, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP17
rw 		SMP16
rw 		SMP15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP15
rw 		SMP14
rw 		SMP13
rw 		SMP12
rw 		SMP11
rw 		SMP10
rw
Toggle Fields

SMP10

Bits 0-2: Channel 10 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP11

Bits 3-5: Channel 11 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP12

Bits 6-8: Channel 12 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP13

Bits 9-11: Channel 13 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP14

Bits 12-14: Channel 14 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP15

Bits 15-17: Channel 15 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP16

Bits 18-20: Channel 16 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP17

Bits 21-23: Channel 17 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMPR2

sample time register 2

Offset: 0x10, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP9
rw 		SMP8
rw 		SMP7
rw 		SMP6
rw 		SMP5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP5
rw 		SMP4
rw 		SMP3
rw 		SMP2
rw 		SMP1
rw 		SMP0
rw
Toggle Fields

SMP0

Bits 0-2: Channel 0 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP1

Bits 3-5: Channel 1 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP2

Bits 6-8: Channel 2 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP3

Bits 9-11: Channel 3 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP4

Bits 12-14: Channel 4 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP5

Bits 15-17: Channel 5 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP6

Bits 18-20: Channel 6 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP7

Bits 21-23: Channel 7 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP8

Bits 24-26: Channel 8 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP9

Bits 27-29: Channel 9 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

JOFR[1]

injected channel data offset register x

Offset: 0x14, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JOFFSET
rw
Toggle Fields

JOFFSET

Bits 0-11: Data offset for injected channel x.

Allowed values: 0x0-0xfff

JOFR[2]

injected channel data offset register x

Offset: 0x18, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JOFFSET
rw
Toggle Fields

JOFFSET

Bits 0-11: Data offset for injected channel x.

Allowed values: 0x0-0xfff

JOFR[3]

injected channel data offset register x

Offset: 0x1c, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JOFFSET
rw
Toggle Fields

JOFFSET

Bits 0-11: Data offset for injected channel x.

Allowed values: 0x0-0xfff

JOFR[4]

injected channel data offset register x

Offset: 0x20, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JOFFSET
rw
Toggle Fields

JOFFSET

Bits 0-11: Data offset for injected channel x.

Allowed values: 0x0-0xfff

HTR

watchdog higher threshold register

Offset: 0x24, reset: 0x00000FFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HT
rw
Toggle Fields

HT

Bits 0-11: Analog watchdog higher threshold.

Allowed values: 0x0-0xfff

LTR

watchdog lower threshold register

Offset: 0x28, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT
rw
Toggle Fields

LT

Bits 0-11: Analog watchdog lower threshold.

Allowed values: 0x0-0xfff

SQR1

regular sequence register 1

Offset: 0x2c, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
L
rw 		SQ16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ16
rw 		SQ15
rw 		SQ14
rw 		SQ13
rw
Toggle Fields

SQ13

Bits 0-4: 13th conversion in regular sequence.

Allowed values: 0x0-0x11

SQ14

Bits 5-9: 14th conversion in regular sequence.

Allowed values: 0x0-0x11

SQ15

Bits 10-14: 15th conversion in regular sequence.

Allowed values: 0x0-0x11

SQ16

Bits 15-19: 16th conversion in regular sequence.

Allowed values: 0x0-0x11

L

Bits 20-23: Regular channel sequence length.

Allowed values: 0x0-0xf

SQR2

regular sequence register 2

Offset: 0x30, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ12
rw 		SQ11
rw 		SQ10
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ10
rw 		SQ9
rw 		SQ8
rw 		SQ7
rw
Toggle Fields

SQ7

Bits 0-4: 7th conversion in regular sequence.

Allowed values: 0x0-0x11

SQ8

Bits 5-9: 8th conversion in regular sequence.

Allowed values: 0x0-0x11

SQ9

Bits 10-14: 9th conversion in regular sequence.

Allowed values: 0x0-0x11

SQ10

Bits 15-19: 10th conversion in regular sequence.

Allowed values: 0x0-0x11

SQ11

Bits 20-24: 11th conversion in regular sequence.

Allowed values: 0x0-0x11

SQ12

Bits 25-29: 12th conversion in regular sequence.

Allowed values: 0x0-0x11

SQR3

regular sequence register 3

Offset: 0x34, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ6
rw 		SQ5
rw 		SQ4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ4
rw 		SQ3
rw 		SQ2
rw 		SQ1
rw
Toggle Fields

SQ1

Bits 0-4: 1st conversion in regular sequence.

Allowed values: 0x0-0x11

SQ2

Bits 5-9: 2nd conversion in regular sequence.

Allowed values: 0x0-0x11

SQ3

Bits 10-14: 3rd conversion in regular sequence.

Allowed values: 0x0-0x11

SQ4

Bits 15-19: 4th conversion in regular sequence.

Allowed values: 0x0-0x11

SQ5

Bits 20-24: 5th conversion in regular sequence.

Allowed values: 0x0-0x11

SQ6

Bits 25-29: 6th conversion in regular sequence.

Allowed values: 0x0-0x11

JSQR

injected sequence register

Offset: 0x38, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JL
rw 		JSQ4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JSQ4
rw 		JSQ3
rw 		JSQ2
rw 		JSQ1
rw
Toggle Fields

JSQ1

Bits 0-4: 1st conversion in injected sequence.

Allowed values: 0x0-0x11

JSQ2

Bits 5-9: 2nd conversion in injected sequence.

Allowed values: 0x0-0x11

JSQ3

Bits 10-14: 3rd conversion in injected sequence.

Allowed values: 0x0-0x11

JSQ4

Bits 15-19: 4th conversion in injected sequence.

Allowed values: 0x0-0x11

JL

Bits 20-21: Injected sequence length.

Allowed values: 0x0-0x3

JDR[1]

injected data register x

Offset: 0x3c, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle Fields

JDATA

Bits 0-15: Injected data.

JDR[2]

injected data register x

Offset: 0x40, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle Fields

JDATA

Bits 0-15: Injected data.

JDR[3]

injected data register x

Offset: 0x44, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle Fields

JDATA

Bits 0-15: Injected data.

JDR[4]

injected data register x

Offset: 0x48, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle Fields

JDATA

Bits 0-15: Injected data.

DR

regular data register

Offset: 0x4c, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADC2DATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
r
Toggle Fields

DATA

Bits 0-15: Regular data.

ADC2DATA

Bits 16-31: ADC2 data.

ADC2

0x40012800: Analog to digital converter

80/81 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 SR
0x4 CR1
0x8 CR2
0xc SMPR1
0x10 SMPR2
0x14 JOFR[1]
0x18 JOFR[2]
0x1c JOFR[3]
0x20 JOFR[4]
0x24 HTR
0x28 LTR
0x2c SQR1
0x30 SQR2
0x34 SQR3
0x38 JSQR
0x3c JDR[1]
0x40 JDR[2]
0x44 JDR[3]
0x48 JDR[4]
0x4c DR

SR

status register

Offset: 0x0, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STRT
rw 		JSTRT
rw 		JEOC
rw 		EOC
rw 		AWD
rw
Toggle Fields

AWD

Bit 0: Analog watchdog flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

EOC

Bit 1: Regular channel end of conversion.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

JEOC

Bit 2: Injected channel end of conversion.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

JSTRT

Bit 3: Injected channel start flag.

Allowed values:
0: NotStarted: No injected group conversion started
1: Started: Injected group conversion has started

STRT

Bit 4: Regular channel start flag.

Allowed values:
0: NotStarted: No regular channel conversion started
1: Started: Regular channel conversion has started

CR1

control register 1

Offset: 0x4, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDEN
rw 		JAWDEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISCNUM
rw 		JDISCEN
rw 		DISCEN
rw 		JAUTO
rw 		AWDSGL
rw 		SCAN
rw 		JEOCIE
rw 		AWDIE
rw 		EOCIE
rw 		AWDCH
rw
Toggle Fields

AWDCH

Bits 0-4: Analog watchdog channel select bits.

Allowed values: 0x0-0x11

EOCIE

Bit 5: Interrupt enable for EOC.

Allowed values:
0: Disabled: EOC interrupt disabled
1: Enabled: EOC interrupt enabled. An interrupt is generated when the EOC bit is set

AWDIE

Bit 6: Analog watchdog interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

JEOCIE

Bit 7: Interrupt enable for injected channels.

Allowed values:
0: Disabled: JEOC interrupt disabled
1: Enabled: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set

SCAN

Bit 8: Scan mode.

Allowed values:
0: Disabled: Scan mode disabled
1: Enabled: Scan mode enabled

AWDSGL

Bit 9: Enable the watchdog on a single channel in scan mode.

Allowed values:
0: All: Analog watchdog enabled on all channels
1: Single: Analog watchdog enabled on a single channel

JAUTO

Bit 10: Automatic injected group conversion.

Allowed values:
0: Disabled: Automatic injected group conversion disabled
1: Enabled: Automatic injected group conversion enabled

DISCEN

Bit 11: Discontinuous mode on regular channels.

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

JDISCEN

Bit 12: Discontinuous mode on injected channels.

Allowed values:
0: Disabled: Discontinuous mode on injected channels disabled
1: Enabled: Discontinuous mode on injected channels enabled

DISCNUM

Bits 13-15: Discontinuous mode channel count.

Allowed values: 0x0-0x7

JAWDEN

Bit 22: Analog watchdog enable on injected channels.

Allowed values:
0: Disabled: Analog watchdog disabled on injected channels
1: Enabled: Analog watchdog enabled on injected channels

AWDEN

Bit 23: Analog watchdog enable on regular channels.

Allowed values:
0: Disabled: Analog watchdog disabled on regular channels
1: Enabled: Analog watchdog enabled on regular channels

CR2

control register 2

Offset: 0x8, reset: 0x00000000, access: read-write

12/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSVREFE
rw 		SWSTART
rw 		JSWSTART
rw 		EXTTRIG
rw 		EXTSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTTRIG
rw 		JEXTSEL
rw 		ALIGN
rw 		DMA
rw 		RSTCAL
rw 		CAL
rw 		CONT
rw 		ADON
rw
Toggle Fields

ADON

Bit 0: A/D converter ON / OFF.

Allowed values:
0: Disabled: Disable ADC conversion/calibration and go to power down mode
1: Enabled: Enable ADC and to start conversion

CONT

Bit 1: Continuous conversion.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

CAL

Bit 2: A/D calibration.

Allowed values:
0: Complete: Calibration completed
1: NotComplete: Calibrating

RSTCAL

Bit 3: Reset calibration.

Allowed values:
0: Initialized: Calibration register initialized
1: NotInitialized: Initializing calibration register

DMA

Bit 8: Direct memory access mode.

ALIGN

Bit 11: Data alignment.

Allowed values:
0: Right: Right Alignment
1: Left: Left Alignment

JEXTSEL

Bits 12-14: External event select for injected group.

Allowed values:
0: Tim1Trgo: Timer 1 TRGO event
1: Tim1Cc4: Timer 1 CC4 event
2: Tim2Trgo: Timer 2 TRGO event
3: Tim2Cc1: Timer 2 CC1 event
4: Tim3Cc4: Timer 3 CC4 event
5: Tim4Trgo: Timer 4 TRGO event
6: Exti15: EXTI line15/TIM8_CC4 event (TIM8_CC4 is available only in high-density and XL-density devices)
7: Jswstart: JSWSTART

JEXTTRIG

Bit 15: External trigger conversion mode for injected channels.

Allowed values:
0: Disabled: Conversion on external event disabled
1: Enabled: Conversion on external event enabled

EXTSEL

Bits 17-19: External event select for regular group.

Allowed values:
0: Tim1Cc1: Timer 1 CC1 event
1: Tim1Cc2: Timer 1 CC2 event
2: Tim1Cc3: Timer 1 CC3 event
3: Tim2Cc2: Timer 2 CC2 event
4: Tim3Trgo: Timer 3 TRGO event
5: Tim4Cc4: Timer 4 CC4 event
6: Exti11: EXTI line 11/TIM8_TRGO event (TIM8_TRGO is available only in high-density and XL-density devices)
7: Swstart: SWSTART

EXTTRIG

Bit 20: External trigger conversion mode for regular channels.

Allowed values:
0: Disabled: Conversion on external event disabled
1: Enabled: Conversion on external event enabled

JSWSTART

Bit 21: Start conversion of injected channels.

Allowed values:
0: Started: Reset state
1: NotStarted: Starting conversion of injected channels

SWSTART

Bit 22: Start conversion of regular channels.

Allowed values:
0: Started: Reset state
1: NotStarted: Starting conversion of regular channels

TSVREFE

Bit 23: Temperature sensor and VREFINT enable.

Allowed values:
0: Disabled: Temperature sensor and V_REFINT channel disabled
1: Enabled: Temperature sensor and V_REFINT channel enabled

SMPR1

sample time register 1

Offset: 0xc, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP17
rw 		SMP16
rw 		SMP15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP15
rw 		SMP14
rw 		SMP13
rw 		SMP12
rw 		SMP11
rw 		SMP10
rw
Toggle Fields

SMP10

Bits 0-2: Channel 10 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP11

Bits 3-5: Channel 11 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP12

Bits 6-8: Channel 12 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP13

Bits 9-11: Channel 13 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP14

Bits 12-14: Channel 14 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP15

Bits 15-17: Channel 15 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP16

Bits 18-20: Channel 16 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP17

Bits 21-23: Channel 17 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMPR2

sample time register 2

Offset: 0x10, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP9
rw 		SMP8
rw 		SMP7
rw 		SMP6
rw 		SMP5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP5
rw 		SMP4
rw 		SMP3
rw 		SMP2
rw 		SMP1
rw 		SMP0
rw
Toggle Fields

SMP0

Bits 0-2: Channel 0 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP1

Bits 3-5: Channel 1 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP2

Bits 6-8: Channel 2 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP3

Bits 9-11: Channel 3 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP4

Bits 12-14: Channel 4 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP5

Bits 15-17: Channel 5 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP6

Bits 18-20: Channel 6 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP7

Bits 21-23: Channel 7 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP8

Bits 24-26: Channel 8 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP9

Bits 27-29: Channel 9 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

JOFR[1]

injected channel data offset register x

Offset: 0x14, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JOFFSET
rw
Toggle Fields

JOFFSET

Bits 0-11: Data offset for injected channel x.

Allowed values: 0x0-0xfff

JOFR[2]

injected channel data offset register x

Offset: 0x18, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JOFFSET
rw
Toggle Fields

JOFFSET

Bits 0-11: Data offset for injected channel x.

Allowed values: 0x0-0xfff

JOFR[3]

injected channel data offset register x

Offset: 0x1c, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JOFFSET
rw
Toggle Fields

JOFFSET

Bits 0-11: Data offset for injected channel x.

Allowed values: 0x0-0xfff

JOFR[4]

injected channel data offset register x

Offset: 0x20, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JOFFSET
rw
Toggle Fields

JOFFSET

Bits 0-11: Data offset for injected channel x.

Allowed values: 0x0-0xfff

HTR

watchdog higher threshold register

Offset: 0x24, reset: 0x00000FFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HT
rw
Toggle Fields

HT

Bits 0-11: Analog watchdog higher threshold.

Allowed values: 0x0-0xfff

LTR

watchdog lower threshold register

Offset: 0x28, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT
rw
Toggle Fields

LT

Bits 0-11: Analog watchdog lower threshold.

Allowed values: 0x0-0xfff

SQR1

regular sequence register 1

Offset: 0x2c, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
L
rw 		SQ16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ16
rw 		SQ15
rw 		SQ14
rw 		SQ13
rw
Toggle Fields

SQ13

Bits 0-4: 13th conversion in regular sequence.

Allowed values: 0x0-0x11

SQ14

Bits 5-9: 14th conversion in regular sequence.

Allowed values: 0x0-0x11

SQ15

Bits 10-14: 15th conversion in regular sequence.

Allowed values: 0x0-0x11

SQ16

Bits 15-19: 16th conversion in regular sequence.

Allowed values: 0x0-0x11

L

Bits 20-23: Regular channel sequence length.

Allowed values: 0x0-0xf

SQR2

regular sequence register 2

Offset: 0x30, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ12
rw 		SQ11
rw 		SQ10
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ10
rw 		SQ9
rw 		SQ8
rw 		SQ7
rw
Toggle Fields

SQ7

Bits 0-4: 7th conversion in regular sequence.

Allowed values: 0x0-0x11

SQ8

Bits 5-9: 8th conversion in regular sequence.

Allowed values: 0x0-0x11

SQ9

Bits 10-14: 9th conversion in regular sequence.

Allowed values: 0x0-0x11

SQ10

Bits 15-19: 10th conversion in regular sequence.

Allowed values: 0x0-0x11

SQ11

Bits 20-24: 11th conversion in regular sequence.

Allowed values: 0x0-0x11

SQ12

Bits 25-29: 12th conversion in regular sequence.

Allowed values: 0x0-0x11

SQR3

regular sequence register 3

Offset: 0x34, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ6
rw 		SQ5
rw 		SQ4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ4
rw 		SQ3
rw 		SQ2
rw 		SQ1
rw
Toggle Fields

SQ1

Bits 0-4: 1st conversion in regular sequence.

Allowed values: 0x0-0x11

SQ2

Bits 5-9: 2nd conversion in regular sequence.

Allowed values: 0x0-0x11

SQ3

Bits 10-14: 3rd conversion in regular sequence.

Allowed values: 0x0-0x11

SQ4

Bits 15-19: 4th conversion in regular sequence.

Allowed values: 0x0-0x11

SQ5

Bits 20-24: 5th conversion in regular sequence.

Allowed values: 0x0-0x11

SQ6

Bits 25-29: 6th conversion in regular sequence.

Allowed values: 0x0-0x11

JSQR

injected sequence register

Offset: 0x38, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JL
rw 		JSQ4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JSQ4
rw 		JSQ3
rw 		JSQ2
rw 		JSQ1
rw
Toggle Fields

JSQ1

Bits 0-4: 1st conversion in injected sequence.

Allowed values: 0x0-0x11

JSQ2

Bits 5-9: 2nd conversion in injected sequence.

Allowed values: 0x0-0x11

JSQ3

Bits 10-14: 3rd conversion in injected sequence.

Allowed values: 0x0-0x11

JSQ4

Bits 15-19: 4th conversion in injected sequence.

Allowed values: 0x0-0x11

JL

Bits 20-21: Injected sequence length.

Allowed values: 0x0-0x3

JDR[1]

injected data register x

Offset: 0x3c, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle Fields

JDATA

Bits 0-15: Injected data.

JDR[2]

injected data register x

Offset: 0x40, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle Fields

JDATA

Bits 0-15: Injected data.

JDR[3]

injected data register x

Offset: 0x44, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle Fields

JDATA

Bits 0-15: Injected data.

JDR[4]

injected data register x

Offset: 0x48, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle Fields

JDATA

Bits 0-15: Injected data.

DR

regular data register

Offset: 0x4c, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
r
Toggle Fields

DATA

Bits 0-15: Regular data.

ADC3

0x40013c00: Analog to digital converter

81/81 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 SR
0x4 CR1
0x8 CR2
0xc SMPR1
0x10 SMPR2
0x14 JOFR[1]
0x18 JOFR[2]
0x1c JOFR[3]
0x20 JOFR[4]
0x24 HTR
0x28 LTR
0x2c SQR1
0x30 SQR2
0x34 SQR3
0x38 JSQR
0x3c JDR[1]
0x40 JDR[2]
0x44 JDR[3]
0x48 JDR[4]
0x4c DR

SR

status register

Offset: 0x0, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STRT
rw 		JSTRT
rw 		JEOC
rw 		EOC
rw 		AWD
rw
Toggle Fields

AWD

Bit 0: Analog watchdog flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

EOC

Bit 1: Regular channel end of conversion.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

JEOC

Bit 2: Injected channel end of conversion.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

JSTRT

Bit 3: Injected channel start flag.

Allowed values:
0: NotStarted: No injected group conversion started
1: Started: Injected group conversion has started

STRT

Bit 4: Regular channel start flag.

Allowed values:
0: NotStarted: No regular channel conversion started
1: Started: Regular channel conversion has started

CR1

control register 1

Offset: 0x4, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDEN
rw 		JAWDEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISCNUM
rw 		JDISCEN
rw 		DISCEN
rw 		JAUTO
rw 		AWDSGL
rw 		SCAN
rw 		JEOCIE
rw 		AWDIE
rw 		EOCIE
rw 		AWDCH
rw
Toggle Fields

AWDCH

Bits 0-4: Analog watchdog channel select bits.

Allowed values: 0x0-0x11

EOCIE

Bit 5: Interrupt enable for EOC.

Allowed values:
0: Disabled: EOC interrupt disabled
1: Enabled: EOC interrupt enabled. An interrupt is generated when the EOC bit is set

AWDIE

Bit 6: Analog watchdog interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

JEOCIE

Bit 7: Interrupt enable for injected channels.

Allowed values:
0: Disabled: JEOC interrupt disabled
1: Enabled: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set

SCAN

Bit 8: Scan mode.

Allowed values:
0: Disabled: Scan mode disabled
1: Enabled: Scan mode enabled

AWDSGL

Bit 9: Enable the watchdog on a single channel in scan mode.

Allowed values:
0: All: Analog watchdog enabled on all channels
1: Single: Analog watchdog enabled on a single channel

JAUTO

Bit 10: Automatic injected group conversion.

Allowed values:
0: Disabled: Automatic injected group conversion disabled
1: Enabled: Automatic injected group conversion enabled

DISCEN

Bit 11: Discontinuous mode on regular channels.

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

JDISCEN

Bit 12: Discontinuous mode on injected channels.

Allowed values:
0: Disabled: Discontinuous mode on injected channels disabled
1: Enabled: Discontinuous mode on injected channels enabled

DISCNUM

Bits 13-15: Discontinuous mode channel count.

Allowed values: 0x0-0x7

JAWDEN

Bit 22: Analog watchdog enable on injected channels.

Allowed values:
0: Disabled: Analog watchdog disabled on injected channels
1: Enabled: Analog watchdog enabled on injected channels

AWDEN

Bit 23: Analog watchdog enable on regular channels.

Allowed values:
0: Disabled: Analog watchdog disabled on regular channels
1: Enabled: Analog watchdog enabled on regular channels

CR2

control register 2

Offset: 0x8, reset: 0x00000000, access: read-write

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSVREFE
rw 		SWSTART
rw 		JSWSTART
rw 		EXTTRIG
rw 		EXTSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTTRIG
rw 		JEXTSEL
rw 		ALIGN
rw 		DMA
rw 		RSTCAL
rw 		CAL
rw 		CONT
rw 		ADON
rw
Toggle Fields

ADON

Bit 0: A/D converter ON / OFF.

Allowed values:
0: Disabled: Disable ADC conversion/calibration and go to power down mode
1: Enabled: Enable ADC and to start conversion

CONT

Bit 1: Continuous conversion.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

CAL

Bit 2: A/D calibration.

Allowed values:
0: Complete: Calibration completed
1: NotComplete: Calibrating

RSTCAL

Bit 3: Reset calibration.

Allowed values:
0: Initialized: Calibration register initialized
1: NotInitialized: Initializing calibration register

DMA

Bit 8: Direct memory access mode.

Allowed values:
0: Disabled: DMA mode disabled
1: Enabled: DMA mode enabled

ALIGN

Bit 11: Data alignment.

Allowed values:
0: Right: Right Alignment
1: Left: Left Alignment

JEXTSEL

Bits 12-14: External event select for injected group.

Allowed values:
0: Tim1Trgo: Timer 1 TRGO event
1: Tim1Cc4: Timer 1 CC4 event
2: Tim4Cc3: Timer 4 CC3 event
3: Tim8Cc2: Timer 8 CC2 event
4: Tim8Cc4: Timer 8 CC4 event
5: Tim5Trgo: Timer 5 TRGO event
6: Tim5Cc4: Timer 5 CC4 event
7: Jswstart: JSWSTART

JEXTTRIG

Bit 15: External trigger conversion mode for injected channels.

Allowed values:
0: Disabled: Conversion on external event disabled
1: Enabled: Conversion on external event enabled

EXTSEL

Bits 17-19: External event select for regular group.

Allowed values:
0: Tim3Cc1: Timer 3 CC1 event
1: Tim2Cc3: Timer 2 CC3 event
2: Tim1Cc3: Timer 1 CC3 event
3: Tim8Cc1: Timer 8 CC1 event
4: Tim8Trgo: Timer 8 TRGO event
5: Tim5Cc1: Timer 5 CC1 event
6: Tim5Cc3: Timer 5 CC3 event
7: Swstart: SWSTART

EXTTRIG

Bit 20: External trigger conversion mode for regular channels.

Allowed values:
0: Disabled: Conversion on external event disabled
1: Enabled: Conversion on external event enabled

JSWSTART

Bit 21: Start conversion of injected channels.

Allowed values:
0: Started: Reset state
1: NotStarted: Starting conversion of injected channels

SWSTART

Bit 22: Start conversion of regular channels.

Allowed values:
0: Started: Reset state
1: NotStarted: Starting conversion of regular channels

TSVREFE

Bit 23: Temperature sensor and VREFINT enable.

Allowed values:
0: Disabled: Temperature sensor and V_REFINT channel disabled
1: Enabled: Temperature sensor and V_REFINT channel enabled

SMPR1

sample time register 1

Offset: 0xc, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP17
rw 		SMP16
rw 		SMP15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP15
rw 		SMP14
rw 		SMP13
rw 		SMP12
rw 		SMP11
rw 		SMP10
rw
Toggle Fields

SMP10

Bits 0-2: Channel 10 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP11

Bits 3-5: Channel 11 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP12

Bits 6-8: Channel 12 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP13

Bits 9-11: Channel 13 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP14

Bits 12-14: Channel 14 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP15

Bits 15-17: Channel 15 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP16

Bits 18-20: Channel 16 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP17

Bits 21-23: Channel 17 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMPR2

sample time register 2

Offset: 0x10, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP9
rw 		SMP8
rw 		SMP7
rw 		SMP6
rw 		SMP5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP5
rw 		SMP4
rw 		SMP3
rw 		SMP2
rw 		SMP1
rw 		SMP0
rw
Toggle Fields

SMP0

Bits 0-2: Channel 0 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP1

Bits 3-5: Channel 1 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP2

Bits 6-8: Channel 2 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP3

Bits 9-11: Channel 3 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP4

Bits 12-14: Channel 4 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP5

Bits 15-17: Channel 5 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP6

Bits 18-20: Channel 6 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP7

Bits 21-23: Channel 7 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP8

Bits 24-26: Channel 8 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SMP9

Bits 27-29: Channel 9 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

JOFR[1]

injected channel data offset register x

Offset: 0x14, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JOFFSET
rw
Toggle Fields

JOFFSET

Bits 0-11: Data offset for injected channel x.

Allowed values: 0x0-0xfff

JOFR[2]

injected channel data offset register x

Offset: 0x18, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JOFFSET
rw
Toggle Fields

JOFFSET

Bits 0-11: Data offset for injected channel x.

Allowed values: 0x0-0xfff

JOFR[3]

injected channel data offset register x

Offset: 0x1c, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JOFFSET
rw
Toggle Fields

JOFFSET

Bits 0-11: Data offset for injected channel x.

Allowed values: 0x0-0xfff

JOFR[4]

injected channel data offset register x

Offset: 0x20, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JOFFSET
rw
Toggle Fields

JOFFSET

Bits 0-11: Data offset for injected channel x.

Allowed values: 0x0-0xfff

HTR

watchdog higher threshold register

Offset: 0x24, reset: 0x00000FFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HT
rw
Toggle Fields

HT

Bits 0-11: Analog watchdog higher threshold.

Allowed values: 0x0-0xfff

LTR

watchdog lower threshold register

Offset: 0x28, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT
rw
Toggle Fields

LT

Bits 0-11: Analog watchdog lower threshold.

Allowed values: 0x0-0xfff

SQR1

regular sequence register 1

Offset: 0x2c, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
L
rw 		SQ16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ16
rw 		SQ15
rw 		SQ14
rw 		SQ13
rw
Toggle Fields

SQ13

Bits 0-4: 13th conversion in regular sequence.

Allowed values: 0x0-0x11

SQ14

Bits 5-9: 14th conversion in regular sequence.

Allowed values: 0x0-0x11

SQ15

Bits 10-14: 15th conversion in regular sequence.

Allowed values: 0x0-0x11

SQ16

Bits 15-19: 16th conversion in regular sequence.

Allowed values: 0x0-0x11

L

Bits 20-23: Regular channel sequence length.

Allowed values: 0x0-0xf

SQR2

regular sequence register 2

Offset: 0x30, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ12
rw 		SQ11
rw 		SQ10
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ10
rw 		SQ9
rw 		SQ8
rw 		SQ7
rw
Toggle Fields

SQ7

Bits 0-4: 7th conversion in regular sequence.

Allowed values: 0x0-0x11

SQ8

Bits 5-9: 8th conversion in regular sequence.

Allowed values: 0x0-0x11

SQ9

Bits 10-14: 9th conversion in regular sequence.

Allowed values: 0x0-0x11

SQ10

Bits 15-19: 10th conversion in regular sequence.

Allowed values: 0x0-0x11

SQ11

Bits 20-24: 11th conversion in regular sequence.

Allowed values: 0x0-0x11

SQ12

Bits 25-29: 12th conversion in regular sequence.

Allowed values: 0x0-0x11

SQR3

regular sequence register 3

Offset: 0x34, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ6
rw 		SQ5
rw 		SQ4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ4
rw 		SQ3
rw 		SQ2
rw 		SQ1
rw
Toggle Fields

SQ1

Bits 0-4: 1st conversion in regular sequence.

Allowed values: 0x0-0x11

SQ2

Bits 5-9: 2nd conversion in regular sequence.

Allowed values: 0x0-0x11

SQ3

Bits 10-14: 3rd conversion in regular sequence.

Allowed values: 0x0-0x11

SQ4

Bits 15-19: 4th conversion in regular sequence.

Allowed values: 0x0-0x11

SQ5

Bits 20-24: 5th conversion in regular sequence.

Allowed values: 0x0-0x11

SQ6

Bits 25-29: 6th conversion in regular sequence.

Allowed values: 0x0-0x11

JSQR

injected sequence register

Offset: 0x38, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JL
rw 		JSQ4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JSQ4
rw 		JSQ3
rw 		JSQ2
rw 		JSQ1
rw
Toggle Fields

JSQ1

Bits 0-4: 1st conversion in injected sequence.

Allowed values: 0x0-0x11

JSQ2

Bits 5-9: 2nd conversion in injected sequence.

Allowed values: 0x0-0x11

JSQ3

Bits 10-14: 3rd conversion in injected sequence.

Allowed values: 0x0-0x11

JSQ4

Bits 15-19: 4th conversion in injected sequence.

Allowed values: 0x0-0x11

JL

Bits 20-21: Injected sequence length.

Allowed values: 0x0-0x3

JDR[1]

injected data register x

Offset: 0x3c, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle Fields

JDATA

Bits 0-15: Injected data.

JDR[2]

injected data register x

Offset: 0x40, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle Fields

JDATA

Bits 0-15: Injected data.

JDR[3]

injected data register x

Offset: 0x44, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle Fields

JDATA

Bits 0-15: Injected data.

JDR[4]

injected data register x

Offset: 0x48, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle Fields

JDATA

Bits 0-15: Injected data.

DR

regular data register

Offset: 0x4c, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
r
Toggle Fields

DATA

Bits 0-15: Regular data.

AFIO

0x40010000: Alternate function I/O

0/42 fields covered. Toggle Registers

Show register map

EVCR

Event Control Register (AFIO_EVCR)

Offset: 0x0, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EVOE
rw 		PORT
rw 		PIN
rw
Toggle Fields

PIN

Bits 0-3: Pin selection.

PORT

Bits 4-6: Port selection.

EVOE

Bit 7: Event Output Enable.

MAPR

AF remap and debug I/O configuration register (AFIO_MAPR)

Offset: 0x4, reset: 0x00000000, access: Unspecified

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWJ_CFG
w 		ADC2_ETRGREG_REMAP
rw 		ADC2_ETRGINJ_REMAP
rw 		ADC1_ETRGREG_REMAP
rw 		ADC1_ETRGINJ_REMAP
rw 		TIM5CH4_IREMAP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD01_REMAP
rw 		CAN_REMAP
rw 		TIM4_REMAP
rw 		TIM3_REMAP
rw 		TIM2_REMAP
rw 		TIM1_REMAP
rw 		USART3_REMAP
rw 		USART2_REMAP
rw 		USART1_REMAP
rw 		I2C1_REMAP
rw 		SPI1_REMAP
rw
Toggle Fields

SPI1_REMAP

Bit 0: SPI1 remapping.

I2C1_REMAP

Bit 1: I2C1 remapping.

USART1_REMAP

Bit 2: USART1 remapping.

USART2_REMAP

Bit 3: USART2 remapping.

USART3_REMAP

Bits 4-5: USART3 remapping.

TIM1_REMAP

Bits 6-7: TIM1 remapping.

TIM2_REMAP

Bits 8-9: TIM2 remapping.

TIM3_REMAP

Bits 10-11: TIM3 remapping.

TIM4_REMAP

Bit 12: TIM4 remapping.

CAN_REMAP

Bits 13-14: CAN1 remapping.

PD01_REMAP

Bit 15: Port D0/Port D1 mapping on OSCIN/OSCOUT.

TIM5CH4_IREMAP

Bit 16: Set and cleared by software.

ADC1_ETRGINJ_REMAP

Bit 17: ADC 1 External trigger injected conversion remapping.

ADC1_ETRGREG_REMAP

Bit 18: ADC 1 external trigger regular conversion remapping.

ADC2_ETRGINJ_REMAP

Bit 19: ADC 2 external trigger injected conversion remapping.

ADC2_ETRGREG_REMAP

Bit 20: ADC 2 external trigger regular conversion remapping.

SWJ_CFG

Bits 24-26: Serial wire JTAG configuration.

EXTICR1

External interrupt configuration register 1 (AFIO_EXTICR1)

Offset: 0x8, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI3
rw 		EXTI2
rw 		EXTI1
rw 		EXTI0
rw
Toggle Fields

EXTI0

Bits 0-3: EXTI0 configuration.

EXTI1

Bits 4-7: EXTI1 configuration.

EXTI2

Bits 8-11: EXTI2 configuration.

EXTI3

Bits 12-15: EXTI3 configuration.

EXTICR2

External interrupt configuration register 2 (AFIO_EXTICR2)

Offset: 0xc, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI7
rw 		EXTI6
rw 		EXTI5
rw 		EXTI4
rw
Toggle Fields

EXTI4

Bits 0-3: EXTI4 configuration.

EXTI5

Bits 4-7: EXTI5 configuration.

EXTI6

Bits 8-11: EXTI6 configuration.

EXTI7

Bits 12-15: EXTI7 configuration.

EXTICR3

External interrupt configuration register 3 (AFIO_EXTICR3)

Offset: 0x10, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI11
rw 		EXTI10
rw 		EXTI9
rw 		EXTI8
rw
Toggle Fields

EXTI8

Bits 0-3: EXTI8 configuration.

EXTI9

Bits 4-7: EXTI9 configuration.

EXTI10

Bits 8-11: EXTI10 configuration.

EXTI11

Bits 12-15: EXTI11 configuration.

EXTICR4

External interrupt configuration register 4 (AFIO_EXTICR4)

Offset: 0x14, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI15
rw 		EXTI14
rw 		EXTI13
rw 		EXTI12
rw
Toggle Fields

EXTI12

Bits 0-3: EXTI12 configuration.

EXTI13

Bits 4-7: EXTI13 configuration.

EXTI14

Bits 8-11: EXTI14 configuration.

EXTI15

Bits 12-15: EXTI15 configuration.

MAPR2

AF remap and debug I/O configuration register

Offset: 0x1c, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSMC_NADV
rw 		TIM14_REMAP
rw 		TIM13_REMAP
rw 		TIM11_REMAP
rw 		TIM10_REMAP
rw 		TIM9_REMAP
rw
Toggle Fields

TIM9_REMAP

Bit 5: TIM9 remapping.

TIM10_REMAP

Bit 6: TIM10 remapping.

TIM11_REMAP

Bit 7: TIM11 remapping.

TIM13_REMAP

Bit 8: TIM13 remapping.

TIM14_REMAP

Bit 9: TIM14 remapping.

FSMC_NADV

Bit 10: NADV connect/disconnect.

BKP

0x40006c04: Backup registers

52/53 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 DR[1]
0x4 DR[2]
0x8 DR[3]
0xc DR[4]
0x10 DR[5]
0x14 DR[6]
0x18 DR[7]
0x1c DR[8]
0x20 DR[9]
0x24 DR[10]
0x28 RTCCR
0x2c CR
0x30 CSR
0x3c BKP_DR[11]
0x40 BKP_DR[12]
0x44 BKP_DR[13]
0x48 BKP_DR[14]
0x4c BKP_DR[15]
0x50 BKP_DR[16]
0x54 BKP_DR[17]
0x58 BKP_DR[18]
0x5c BKP_DR[19]
0x60 BKP_DR[20]
0x64 BKP_DR[21]
0x68 BKP_DR[22]
0x6c BKP_DR[23]
0x70 BKP_DR[24]
0x74 BKP_DR[25]
0x78 BKP_DR[26]
0x7c BKP_DR[27]
0x80 BKP_DR[28]
0x84 BKP_DR[29]
0x88 BKP_DR[30]
0x8c BKP_DR[31]
0x90 BKP_DR[32]
0x94 BKP_DR[33]
0x98 BKP_DR[34]
0x9c BKP_DR[35]
0xa0 BKP_DR[36]
0xa4 BKP_DR[37]
0xa8 BKP_DR[38]
0xac BKP_DR[39]
0xb0 BKP_DR[40]
0xb4 BKP_DR[41]
0xb8 BKP_DR[42]

DR[1]

Backup data register (BKP_DR)

Offset: 0x0, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

DR[2]

Backup data register (BKP_DR)

Offset: 0x4, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

DR[3]

Backup data register (BKP_DR)

Offset: 0x8, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

DR[4]

Backup data register (BKP_DR)

Offset: 0xc, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

DR[5]

Backup data register (BKP_DR)

Offset: 0x10, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

DR[6]

Backup data register (BKP_DR)

Offset: 0x14, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

DR[7]

Backup data register (BKP_DR)

Offset: 0x18, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

DR[8]

Backup data register (BKP_DR)

Offset: 0x1c, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

DR[9]

Backup data register (BKP_DR)

Offset: 0x20, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

DR[10]

Backup data register (BKP_DR)

Offset: 0x24, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

RTCCR

RTC clock calibration register (BKP_RTCCR)

Offset: 0x28, reset: 0x00000000, access: read-write

3/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASOS
rw 		ASOE
rw 		CCO
rw 		CAL
rw
Toggle Fields

CAL

Bits 0-6: Calibration value.

Allowed values: 0x0-0x79

CCO

Bit 7: Calibration Clock Output.

ASOE

Bit 8: Alarm or second output enable.

Allowed values:
0: Disabled: Disabled
1: Enabled: Setting this bit outputs either the RTC Alarm pulse signal or the Second pulse signal on the TAMPER pin depending on the ASOS bit

ASOS

Bit 9: Alarm or second output selection.

Allowed values:
0: Alarm: RTC Alarm pulse output selected
1: Second: RTC Second pulse output selected

CR

Backup control register (BKP_CR)

Offset: 0x2c, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TPAL
rw 		TPE
rw
Toggle Fields

TPE

Bit 0: Tamper pin enable.

Allowed values:
0: General: The TAMPER pin is free for general purpose I/O
1: Alternate: Tamper alternate I/O function is activated

TPAL

Bit 1: Tamper pin active level.

Allowed values:
0: High: A high level on the TAMPER pin resets all data backup registers (if TPE bit is set)
1: Low: A low level on the TAMPER pin resets all data backup registers (if TPE bit is set)

CSR

BKP_CSR control/status register (BKP_CSR)

Offset: 0x30, reset: 0x00000000, access: Unspecified

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIF
r 		TEF
r 		TPIE
rw 		CTI
w 		CTE
w
Toggle Fields

CTE

Bit 0: Clear Tamper event.

Allowed values:
1: Reset: Reset the TEF Tamper event flag (and the Tamper detector)

CTI

Bit 1: Clear Tamper Interrupt.

Allowed values:
1: Clear: Clear the Tamper interrupt and the TIF Tamper interrupt flag

TPIE

Bit 2: Tamper Pin interrupt enable.

Allowed values:
0: Disabled: Tamper interrupt disabled
1: Enabled: Tamper interrupt enabled (the TPE bit must also be set in the BKP_CR register

TEF

Bit 8: Tamper Event Flag.

TIF

Bit 9: Tamper Interrupt Flag.

BKP_DR[11]

Backup data register (BKP_DR)

Offset: 0x3c, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[12]

Backup data register (BKP_DR)

Offset: 0x40, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[13]

Backup data register (BKP_DR)

Offset: 0x44, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[14]

Backup data register (BKP_DR)

Offset: 0x48, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[15]

Backup data register (BKP_DR)

Offset: 0x4c, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[16]

Backup data register (BKP_DR)

Offset: 0x50, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[17]

Backup data register (BKP_DR)

Offset: 0x54, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[18]

Backup data register (BKP_DR)

Offset: 0x58, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[19]

Backup data register (BKP_DR)

Offset: 0x5c, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[20]

Backup data register (BKP_DR)

Offset: 0x60, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[21]

Backup data register (BKP_DR)

Offset: 0x64, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[22]

Backup data register (BKP_DR)

Offset: 0x68, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[23]

Backup data register (BKP_DR)

Offset: 0x6c, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[24]

Backup data register (BKP_DR)

Offset: 0x70, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[25]

Backup data register (BKP_DR)

Offset: 0x74, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[26]

Backup data register (BKP_DR)

Offset: 0x78, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[27]

Backup data register (BKP_DR)

Offset: 0x7c, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[28]

Backup data register (BKP_DR)

Offset: 0x80, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[29]

Backup data register (BKP_DR)

Offset: 0x84, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[30]

Backup data register (BKP_DR)

Offset: 0x88, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[31]

Backup data register (BKP_DR)

Offset: 0x8c, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[32]

Backup data register (BKP_DR)

Offset: 0x90, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[33]

Backup data register (BKP_DR)

Offset: 0x94, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[34]

Backup data register (BKP_DR)

Offset: 0x98, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[35]

Backup data register (BKP_DR)

Offset: 0x9c, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[36]

Backup data register (BKP_DR)

Offset: 0xa0, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[37]

Backup data register (BKP_DR)

Offset: 0xa4, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[38]

Backup data register (BKP_DR)

Offset: 0xa8, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[39]

Backup data register (BKP_DR)

Offset: 0xac, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[40]

Backup data register (BKP_DR)

Offset: 0xb0, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[41]

Backup data register (BKP_DR)

Offset: 0xb4, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

BKP_DR[42]

Backup data register (BKP_DR)

Offset: 0xb8, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D
rw
Toggle Fields

D

Bits 0-15: Backup data.

Allowed values: 0x0-0xffff

CAN1

0x40006400: Controller area network

82/238 fields covered. Toggle Registers

Show register map

Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MCR
0x4 MSR
0x8 TSR
0xc RF[0]R
0x10<