0x40012400: Analog to digital converter
81/81 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | SR | ||||||||||||||||||||||||||||||||
| 0x4 | CR1 | ||||||||||||||||||||||||||||||||
| 0x8 | CR2 | ||||||||||||||||||||||||||||||||
| 0xc | SMPR1 | ||||||||||||||||||||||||||||||||
| 0x10 | SMPR2 | ||||||||||||||||||||||||||||||||
| 0x14 | JOFR[1] | ||||||||||||||||||||||||||||||||
| 0x18 | JOFR[2] | ||||||||||||||||||||||||||||||||
| 0x1c | JOFR[3] | ||||||||||||||||||||||||||||||||
| 0x20 | JOFR[4] | ||||||||||||||||||||||||||||||||
| 0x24 | HTR | ||||||||||||||||||||||||||||||||
| 0x28 | LTR | ||||||||||||||||||||||||||||||||
| 0x2c | SQR1 | ||||||||||||||||||||||||||||||||
| 0x30 | SQR2 | ||||||||||||||||||||||||||||||||
| 0x34 | SQR3 | ||||||||||||||||||||||||||||||||
| 0x38 | JSQR | ||||||||||||||||||||||||||||||||
| 0x3c | JDR[1] | ||||||||||||||||||||||||||||||||
| 0x40 | JDR[2] | ||||||||||||||||||||||||||||||||
| 0x44 | JDR[3] | ||||||||||||||||||||||||||||||||
| 0x48 | JDR[4] | ||||||||||||||||||||||||||||||||
| 0x4c | DR | ||||||||||||||||||||||||||||||||
status register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
5/5 fields covered.
Bit 0: Analog watchdog flag.
Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred
Bit 1: Regular channel end of conversion.
Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete
Bit 2: Injected channel end of conversion.
Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete
Bit 3: Injected channel start flag.
Allowed values:
0: NotStarted: No injected group conversion started
1: Started: Injected group conversion has started
Bit 4: Regular channel start flag.
Allowed values:
0: NotStarted: No regular channel conversion started
1: Started: Regular channel conversion has started
control register 1
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
12/12 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
AWDEN
rw |
JAWDEN
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DISCNUM
rw |
JDISCEN
rw |
DISCEN
rw |
JAUTO
rw |
AWDSGL
rw |
SCAN
rw |
JEOCIE
rw |
AWDIE
rw |
EOCIE
rw |
AWDCH
rw |
||||||
Bits 0-4: Analog watchdog channel select bits.
Allowed values: 0x0-0x11
Bit 5: Interrupt enable for EOC.
Allowed values:
0: Disabled: EOC interrupt disabled
1: Enabled: EOC interrupt enabled. An interrupt is generated when the EOC bit is set
Bit 6: Analog watchdog interrupt enable.
Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled
Bit 7: Interrupt enable for injected channels.
Allowed values:
0: Disabled: JEOC interrupt disabled
1: Enabled: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set
Bit 8: Scan mode.
Allowed values:
0: Disabled: Scan mode disabled
1: Enabled: Scan mode enabled
Bit 9: Enable the watchdog on a single channel in scan mode.
Allowed values:
0: All: Analog watchdog enabled on all channels
1: Single: Analog watchdog enabled on a single channel
Bit 10: Automatic injected group conversion.
Allowed values:
0: Disabled: Automatic injected group conversion disabled
1: Enabled: Automatic injected group conversion enabled
Bit 11: Discontinuous mode on regular channels.
Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled
Bit 12: Discontinuous mode on injected channels.
Allowed values:
0: Disabled: Discontinuous mode on injected channels disabled
1: Enabled: Discontinuous mode on injected channels enabled
Bits 13-15: Discontinuous mode channel count.
Allowed values: 0x0-0x7
Bit 22: Analog watchdog enable on injected channels.
Allowed values:
0: Disabled: Analog watchdog disabled on injected channels
1: Enabled: Analog watchdog enabled on injected channels
Bit 23: Analog watchdog enable on regular channels.
Allowed values:
0: Disabled: Analog watchdog disabled on regular channels
1: Enabled: Analog watchdog enabled on regular channels
control register 2
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
13/13 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TSVREFE
rw |
SWSTART
rw |
JSWSTART
rw |
EXTTRIG
rw |
EXTSEL
rw |
|||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
JEXTTRIG
rw |
JEXTSEL
rw |
ALIGN
rw |
DMA
rw |
RSTCAL
rw |
CAL
rw |
CONT
rw |
ADON
rw |
||||||||
Bit 0: A/D converter ON / OFF.
Allowed values:
0: Disabled: Disable ADC conversion/calibration and go to power down mode
1: Enabled: Enable ADC and to start conversion
Bit 1: Continuous conversion.
Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode
Bit 2: A/D calibration.
Allowed values:
0: Complete: Calibration completed
1: NotComplete: Calibrating
Bit 3: Reset calibration.
Allowed values:
0: Initialized: Calibration register initialized
1: NotInitialized: Initializing calibration register
Bit 8: Direct memory access mode.
Allowed values:
0: Disabled: DMA mode disabled
1: Enabled: DMA mode enabled
Bit 11: Data alignment.
Allowed values:
0: Right: Right Alignment
1: Left: Left Alignment
Bits 12-14: External event select for injected group.
Allowed values:
0: Tim19Cc1: Timer 19 CC1 event
1: Tim19Cc2: Timer 19 CC2 event
2: Tim2Trgo: Timer 2 TRGO event
3: Tim2Cc1: Timer 2 CC1 event
4: Tim3Cc4: Timer 3 CC4 event
5: Tim4Trgo: Timer 4 TRGO event
6: Exti15: EXTI line15
7: Jswstart: JSWSTART
Bit 15: External trigger conversion mode for injected channels.
Allowed values:
0: Disabled: Conversion on external event disabled
1: Enabled: Conversion on external event enabled
Bits 17-19: External event select for regular group.
Allowed values:
0: Tim19Trgo: Timer 19 TRGO event
1: Tim19Cc3: Timer 19 CC3 event
2: Tim19Cc4: Timer 19 CC4 event
3: Tim2Cc2: Timer 2 CC2 event
4: Tim3Trgo: Timer 3 TRGO event
5: Tim4Cc4: Timer 4 CC4 event
6: Exti11: EXTI line 11
7: Swstart: SWSTART
Bit 20: External trigger conversion mode for regular channels.
Allowed values:
0: Disabled: Conversion on external event disabled
1: Enabled: Conversion on external event enabled
Bit 21: Start conversion of injected channels.
Allowed values:
0: Started: Reset state
1: NotStarted: Starting conversion of injected channels
Bit 22: Start conversion of regular channels.
Allowed values:
0: Started: Reset state
1: NotStarted: Starting conversion of regular channels
Bit 23: Temperature sensor and VREFINT enable.
Allowed values:
0: Disabled: Temperature sensor and V_REFINT channel disabled
1: Enabled: Temperature sensor and V_REFINT channel enabled
sample time register 1
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SMP17
rw |
SMP16
rw |
SMP15
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SMP15
rw |
SMP14
rw |
SMP13
rw |
SMP12
rw |
SMP11
rw |
SMP10
rw |
||||||||||
Bits 0-2: Channel 10 sampling time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 3-5: Channel 11 sampling time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 6-8: Channel 12 sampling time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 9-11: Channel 13 sampling time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 12-14: Channel 14 sampling time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 15-17: Channel 15 sampling time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 18-20: Channel 16 sampling time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 21-23: Channel 17 sampling time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
sample time register 2
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
10/10 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SMP9
rw |
SMP8
rw |
SMP7
rw |
SMP6
rw |
SMP5
rw |
|||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SMP5
rw |
SMP4
rw |
SMP3
rw |
SMP2
rw |
SMP1
rw |
SMP0
rw |
||||||||||
Bits 0-2: Channel 0 sampling time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 3-5: Channel 1 sampling time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 6-8: Channel 2 sampling time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 9-11: Channel 3 sampling time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 12-14: Channel 4 sampling time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 15-17: Channel 5 sampling time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 18-20: Channel 6 sampling time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 21-23: Channel 7 sampling time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 24-26: Channel 8 sampling time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 27-29: Channel 9 sampling time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
injected channel data offset register x
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
JOFFSET
rw |
|||||||||||||||
injected channel data offset register x
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
JOFFSET
rw |
|||||||||||||||
injected channel data offset register x
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
JOFFSET
rw |
|||||||||||||||
injected channel data offset register x
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
JOFFSET
rw |
|||||||||||||||
watchdog higher threshold register
Offset: 0x24, size: 32, reset: 0x00000FFF, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
HT
rw |
|||||||||||||||
watchdog lower threshold register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
LT
rw |
|||||||||||||||
regular sequence register 1
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
5/5 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
L
rw |
SQ16
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SQ16
rw |
SQ15
rw |
SQ14
rw |
SQ13
rw |
||||||||||||
Bits 0-4: 13th conversion in regular sequence.
Allowed values: 0x0-0x11
Bits 5-9: 14th conversion in regular sequence.
Allowed values: 0x0-0x11
Bits 10-14: 15th conversion in regular sequence.
Allowed values: 0x0-0x11
Bits 15-19: 16th conversion in regular sequence.
Allowed values: 0x0-0x11
Bits 20-23: Regular channel sequence length.
Allowed values: 0x0-0xf
regular sequence register 2
Offset: 0x30, size: 32, reset: 0x00000000, access: read-write
6/6 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SQ12
rw |
SQ11
rw |
SQ10
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SQ10
rw |
SQ9
rw |
SQ8
rw |
SQ7
rw |
||||||||||||
Bits 0-4: 7th conversion in regular sequence.
Allowed values: 0x0-0x11
Bits 5-9: 8th conversion in regular sequence.
Allowed values: 0x0-0x11
Bits 10-14: 9th conversion in regular sequence.
Allowed values: 0x0-0x11
Bits 15-19: 10th conversion in regular sequence.
Allowed values: 0x0-0x11
Bits 20-24: 11th conversion in regular sequence.
Allowed values: 0x0-0x11
Bits 25-29: 12th conversion in regular sequence.
Allowed values: 0x0-0x11
regular sequence register 3
Offset: 0x34, size: 32, reset: 0x00000000, access: read-write
6/6 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SQ6
rw |
SQ5
rw |
SQ4
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SQ4
rw |
SQ3
rw |
SQ2
rw |
SQ1
rw |
||||||||||||
Bits 0-4: 1st conversion in regular sequence.
Allowed values: 0x0-0x11
Bits 5-9: 2nd conversion in regular sequence.
Allowed values: 0x0-0x11
Bits 10-14: 3rd conversion in regular sequence.
Allowed values: 0x0-0x11
Bits 15-19: 4th conversion in regular sequence.
Allowed values: 0x0-0x11
Bits 20-24: 5th conversion in regular sequence.
Allowed values: 0x0-0x11
Bits 25-29: 6th conversion in regular sequence.
Allowed values: 0x0-0x11
injected sequence register
Offset: 0x38, size: 32, reset: 0x00000000, access: read-write
5/5 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
JL
rw |
JSQ4
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
JSQ4
rw |
JSQ3
rw |
JSQ2
rw |
JSQ1
rw |
||||||||||||
Bits 0-4: 1st conversion in injected sequence.
Allowed values: 0x0-0x11
Bits 5-9: 2nd conversion in injected sequence.
Allowed values: 0x0-0x11
Bits 10-14: 3rd conversion in injected sequence.
Allowed values: 0x0-0x11
Bits 15-19: 4th conversion in injected sequence.
Allowed values: 0x0-0x11
Bits 20-21: Injected sequence length.
Allowed values: 0x0-0x3
injected data register x
Offset: 0x3c, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
JDATA
r |
|||||||||||||||
injected data register x
Offset: 0x40, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
JDATA
r |
|||||||||||||||
injected data register x
Offset: 0x44, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
JDATA
r |
|||||||||||||||
injected data register x
Offset: 0x48, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
JDATA
r |
|||||||||||||||
regular data register
Offset: 0x4c, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DATA
r |
|||||||||||||||
0x40006400: Controller area network
82/323 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | MCR | ||||||||||||||||||||||||||||||||
| 0x4 | MSR | ||||||||||||||||||||||||||||||||
| 0x8 | TSR | ||||||||||||||||||||||||||||||||
| 0xc | RF[0]R | ||||||||||||||||||||||||||||||||
| 0x10 | RF[1]R | ||||||||||||||||||||||||||||||||
| 0x14 | IER | ||||||||||||||||||||||||||||||||
| 0x18 | ESR | ||||||||||||||||||||||||||||||||
| 0x1c | BTR | ||||||||||||||||||||||||||||||||
| 0x180 | TIR [0] | ||||||||||||||||||||||||||||||||
| 0x184 | TDTR [0] | ||||||||||||||||||||||||||||||||
| 0x188 | TDLR [0] | ||||||||||||||||||||||||||||||||
| 0x18c | TDHR [0] | ||||||||||||||||||||||||||||||||
| 0x190 | TIR [1] | ||||||||||||||||||||||||||||||||
| 0x194 | TDTR [1] | ||||||||||||||||||||||||||||||||
| 0x198 | TDLR [1] | ||||||||||||||||||||||||||||||||
| 0x19c | TDHR [1] | ||||||||||||||||||||||||||||||||
| 0x1a0 | TIR [2] | ||||||||||||||||||||||||||||||||
| 0x1a4 | TDTR [2] | ||||||||||||||||||||||||||||||||
| 0x1a8 | TDLR [2] | ||||||||||||||||||||||||||||||||
| 0x1ac | TDHR [2] | ||||||||||||||||||||||||||||||||
| 0x1b0 | RIR [0] | ||||||||||||||||||||||||||||||||
| 0x1b4 | RDTR [0] | ||||||||||||||||||||||||||||||||
| 0x1b8 | RDLR [0] | ||||||||||||||||||||||||||||||||
| 0x1bc | RDHR [0] | ||||||||||||||||||||||||||||||||
| 0x1c0 | RIR [1] | ||||||||||||||||||||||||||||||||
| 0x1c4 | RDTR [1] | ||||||||||||||||||||||||||||||||
| 0x1c8 | RDLR [1] | ||||||||||||||||||||||||||||||||
| 0x1cc | RDHR [1] | ||||||||||||||||||||||||||||||||
| 0x200 | FMR | ||||||||||||||||||||||||||||||||
| 0x204 | FM1R | ||||||||||||||||||||||||||||||||
| 0x20c | FS1R | ||||||||||||||||||||||||||||||||
| 0x214 | FFA1R | ||||||||||||||||||||||||||||||||
| 0x21c | FA1R | ||||||||||||||||||||||||||||||||
| 0x240 | FR1 [0] | ||||||||||||||||||||||||||||||||
| 0x244 | FR2 [0] | ||||||||||||||||||||||||||||||||
| 0x248 | FR1 [1] | ||||||||||||||||||||||||||||||||
| 0x24c | FR2 [1] | ||||||||||||||||||||||||||||||||
| 0x250 | FR1 [2] | ||||||||||||||||||||||||||||||||
| 0x254 | FR2 [2] | ||||||||||||||||||||||||||||||||
| 0x258 | FR1 [3] | ||||||||||||||||||||||||||||||||
| 0x25c | FR2 [3] | ||||||||||||||||||||||||||||||||
| 0x260 | FR1 [4] | ||||||||||||||||||||||||||||||||
| 0x264 | FR2 [4] | ||||||||||||||||||||||||||||||||
| 0x268 | FR1 [5] | ||||||||||||||||||||||||||||||||
| 0x26c | FR2 [5] | ||||||||||||||||||||||||||||||||
| 0x270 | FR1 [6] | ||||||||||||||||||||||||||||||||
| 0x274 | FR2 [6] | ||||||||||||||||||||||||||||||||
| 0x278 | FR1 [7] | ||||||||||||||||||||||||||||||||
| 0x27c | FR2 [7] | ||||||||||||||||||||||||||||||||
| 0x280 | FR1 [8] | ||||||||||||||||||||||||||||||||
| 0x284 | FR2 [8] | ||||||||||||||||||||||||||||||||
| 0x288 | FR1 [9] | ||||||||||||||||||||||||||||||||
| 0x28c | FR2 [9] | ||||||||||||||||||||||||||||||||
| 0x290 | FR1 [10] | ||||||||||||||||||||||||||||||||
| 0x294 | FR2 [10] | ||||||||||||||||||||||||||||||||
| 0x298 | FR1 [11] | ||||||||||||||||||||||||||||||||
| 0x29c | FR2 [11] | ||||||||||||||||||||||||||||||||
| 0x2a0 | FR1 [12] | ||||||||||||||||||||||||||||||||
| 0x2a4 | FR2 [12] | ||||||||||||||||||||||||||||||||
| 0x2a8 | FR1 [13] | ||||||||||||||||||||||||||||||||
| 0x2ac | FR2 [13] | ||||||||||||||||||||||||||||||||
| 0x2b0 | FR1 [14] | ||||||||||||||||||||||||||||||||
| 0x2b4 | FR2 [14] | ||||||||||||||||||||||||||||||||
| 0x2b8 | FR1 [15] | ||||||||||||||||||||||||||||||||
| 0x2bc | FR2 [15] | ||||||||||||||||||||||||||||||||
| 0x2c0 | FR1 [16] | ||||||||||||||||||||||||||||||||
| 0x2c4 | FR2 [16] | ||||||||||||||||||||||||||||||||
| 0x2c8 | FR1 [17] | ||||||||||||||||||||||||||||||||
| 0x2cc | FR2 [17] | ||||||||||||||||||||||||||||||||
| 0x2d0 | FR1 [18] | ||||||||||||||||||||||||||||||||
| 0x2d4 | FR2 [18] | ||||||||||||||||||||||||||||||||
| 0x2d8 | FR1 [19] | ||||||||||||||||||||||||||||||||
| 0x2dc | FR2 [19] | ||||||||||||||||||||||||||||||||
| 0x2e0 | FR1 [20] | ||||||||||||||||||||||||||||||||
| 0x2e4 | FR2 [20] | ||||||||||||||||||||||||||||||||
| 0x2e8 | FR1 [21] | ||||||||||||||||||||||||||||||||
| 0x2ec | FR2 [21] | ||||||||||||||||||||||||||||||||
| 0x2f0 | FR1 [22] | ||||||||||||||||||||||||||||||||
| 0x2f4 | FR2 [22] | ||||||||||||||||||||||||||||||||
| 0x2f8 | FR1 [23] | ||||||||||||||||||||||||||||||||
| 0x2fc | FR2 [23] | ||||||||||||||||||||||||||||||||
| 0x300 | FR1 [24] | ||||||||||||||||||||||||||||||||
| 0x304 | FR2 [24] | ||||||||||||||||||||||||||||||||
| 0x308 | FR1 [25] | ||||||||||||||||||||||||||||||||
| 0x30c | FR2 [25] | ||||||||||||||||||||||||||||||||
| 0x310 | FR1 [26] | ||||||||||||||||||||||||||||||||
| 0x314 | FR2 [26] | ||||||||||||||||||||||||||||||||
| 0x318 | FR1 [27] | ||||||||||||||||||||||||||||||||
| 0x31c | FR2 [27] | ||||||||||||||||||||||||||||||||
master control register
Offset: 0x0, size: 32, reset: 0x00010002, access: read-write
0/10 fields covered.
master status register
Offset: 0x4, size: 32, reset: 0x00000C02, access: Unspecified
6/9 fields covered.
transmit status register
Offset: 0x8, size: 32, reset: 0x1C000000, access: Unspecified
7/22 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
LOW[2]
r |
LOW[1]
r |
LOW[0]
r |
TME[2]
r |
TME[1]
r |
TME[0]
r |
CODE
r |
ABRQ2
rw |
TERR2
rw |
ALST2
rw |
TXOK2
rw |
RQCP2
rw |
||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ABRQ1
rw |
TERR1
rw |
ALST1
rw |
TXOK1
rw |
RQCP1
rw |
ABRQ0
rw |
TERR0
rw |
ALST0
rw |
TXOK0
rw |
RQCP0
rw |
||||||
Bit 0: RQCP0.
Bit 1: TXOK0.
Bit 2: ALST0.
Bit 3: TERR0.
Bit 7: ABRQ0.
Bit 8: RQCP1.
Bit 9: TXOK1.
Bit 10: ALST1.
Bit 11: TERR1.
Bit 15: ABRQ1.
Bit 16: RQCP2.
Bit 17: TXOK2.
Bit 18: ALST2.
Bit 19: TERR2.
Bit 23: ABRQ2.
Bits 24-25: CODE.
Bit 26: Lowest priority flag for mailbox 0.
Bit 27: Lowest priority flag for mailbox 1.
Bit 28: Lowest priority flag for mailbox 2.
Bit 29: Lowest priority flag for mailbox 0.
Bit 30: Lowest priority flag for mailbox 1.
Bit 31: Lowest priority flag for mailbox 2.
receive FIFO 0 register
Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified
4/4 fields covered.
Bits 0-1: FMP0.
Bit 3: FULL0.
Allowed values:
0: NotFull: FIFO x is not full
1: Full: FIFO x is full
Bit 4: FOVR0.
Allowed values:
0: NoOverrun: No FIFO x overrun
1: Overrun: FIFO x overrun
Bit 5: RFOM0.
Allowed values:
1: Release: Set by software to release the output mailbox of the FIFO
receive FIFO 1 register
Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified
4/4 fields covered.
Bits 0-1: FMP0.
Bit 3: FULL0.
Allowed values:
0: NotFull: FIFO x is not full
1: Full: FIFO x is full
Bit 4: FOVR0.
Allowed values:
0: NoOverrun: No FIFO x overrun
1: Overrun: FIFO x overrun
Bit 5: RFOM0.
Allowed values:
1: Release: Set by software to release the output mailbox of the FIFO
interrupt enable register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
14/14 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SLKIE
rw |
WKUIE
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ERRIE
rw |
LECIE
rw |
BOFIE
rw |
EPVIE
rw |
EWGIE
rw |
FOVIE1
rw |
FFIE1
rw |
FMPIE1
rw |
FOVIE0
rw |
FFIE0
rw |
FMPIE0
rw |
TMEIE
rw |
||||
Bit 0: TMEIE.
Allowed values:
0: Disabled: No interrupt when RQCPx bit is set
1: Enabled: Interrupt generated when RQCPx bit is set
Bit 1: FMPIE0.
Allowed values:
0: Disabled: No interrupt generated when state of FMP[1:0] bits are not 00
1: Enabled: Interrupt generated when state of FMP[1:0] bits are not 00b
Bit 2: FFIE0.
Allowed values:
0: Disabled: No interrupt when FULL bit is set
1: Enabled: Interrupt generated when FULL bit is set
Bit 3: FOVIE0.
Allowed values:
0: Disabled: No interrupt when FOVR bit is set
1: Enabled: Interrupt generated when FOVR bit is set
Bit 4: FMPIE1.
Allowed values:
0: Disabled: No interrupt generated when state of FMP[1:0] bits are not 00b
1: Enabled: Interrupt generated when state of FMP[1:0] bits are not 00b
Bit 5: FFIE1.
Allowed values:
0: Disabled: No interrupt when FULL bit is set
1: Enabled: Interrupt generated when FULL bit is set
Bit 6: FOVIE1.
Allowed values:
0: Disabled: No interrupt when FOVR is set
1: Enabled: Interrupt generation when FOVR is set
Bit 8: EWGIE.
Allowed values:
0: Disabled: ERRI bit will not be set when EWGF is set
1: Enabled: ERRI bit will be set when EWGF is set
Bit 9: EPVIE.
Allowed values:
0: Disabled: ERRI bit will not be set when EPVF is set
1: Enabled: ERRI bit will be set when EPVF is set
Bit 10: BOFIE.
Allowed values:
0: Disabled: ERRI bit will not be set when BOFF is set
1: Enabled: ERRI bit will be set when BOFF is set
Bit 11: LECIE.
Allowed values:
0: Disabled: ERRI bit will not be set when the error code in LEC[2:0] is set by hardware on error detection
1: Enabled: ERRI bit will be set when the error code in LEC[2:0] is set by hardware on error detection
Bit 15: ERRIE.
Allowed values:
0: Disabled: No interrupt will be generated when an error condition is pending in the CAN_ESR
1: Enabled: An interrupt will be generation when an error condition is pending in the CAN_ESR
Bit 16: WKUIE.
Allowed values:
0: Disabled: No interrupt when WKUI is set
1: Enabled: Interrupt generated when WKUI bit is set
Bit 17: SLKIE.
Allowed values:
0: Disabled: No interrupt when SLAKI bit is set
1: Enabled: Interrupt generated when SLAKI bit is set
error status register
Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified
6/6 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
REC
r |
TEC
r |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
LEC
rw |
BOFF
r |
EPVF
r |
EWGF
r |
||||||||||||
Bit 0: EWGF.
Bit 1: EPVF.
Bit 2: BOFF.
Bits 4-6: LEC.
Allowed values:
0: NoError: No Error
1: Stuff: Stuff Error
2: Form: Form Error
3: Ack: Acknowledgment Error
4: BitRecessive: Bit recessive Error
5: BitDominant: Bit dominant Error
6: Crc: CRC Error
7: Custom: Set by software
Bits 16-23: TEC.
Bits 24-31: REC.
bit timing register
Offset: 0x1c, size: 32, reset: 0x01230000, access: read-write
2/6 fields covered.
TX mailbox identifier register
Offset: 0x180, size: 32, reset: 0x00000000, access: read-write
2/5 fields covered.
mailbox data length control and time stamp register
Offset: 0x184, size: 32, reset: 0x00000000, access: read-write
1/3 fields covered.
mailbox data low register
Offset: 0x188, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
mailbox data high register
Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
TX mailbox identifier register
Offset: 0x190, size: 32, reset: 0x00000000, access: read-write
2/5 fields covered.
mailbox data length control and time stamp register
Offset: 0x194, size: 32, reset: 0x00000000, access: read-write
1/3 fields covered.
mailbox data low register
Offset: 0x198, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
mailbox data high register
Offset: 0x19c, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
TX mailbox identifier register
Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write
2/5 fields covered.
mailbox data length control and time stamp register
Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-write
1/3 fields covered.
mailbox data low register
Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
mailbox data high register
Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
receive FIFO mailbox identifier register
Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-only
4/4 fields covered.
receive FIFO mailbox data length control and time stamp register
Offset: 0x1b4, size: 32, reset: 0x00000000, access: read-only
3/3 fields covered.
receive FIFO mailbox data low register
Offset: 0x1b8, size: 32, reset: 0x00000000, access: read-only
4/4 fields covered.
receive FIFO mailbox data high register
Offset: 0x1bc, size: 32, reset: 0x00000000, access: read-only
4/4 fields covered.
receive FIFO mailbox identifier register
Offset: 0x1c0, size: 32, reset: 0x00000000, access: read-only
4/4 fields covered.
receive FIFO mailbox data length control and time stamp register
Offset: 0x1c4, size: 32, reset: 0x00000000, access: read-only
3/3 fields covered.
receive FIFO mailbox data low register
Offset: 0x1c8, size: 32, reset: 0x00000000, access: read-only
4/4 fields covered.
receive FIFO mailbox data high register
Offset: 0x1cc, size: 32, reset: 0x00000000, access: read-only
4/4 fields covered.
filter master register
Offset: 0x200, size: 32, reset: 0x2A1C0E01, access: read-write
0/2 fields covered.
filter mode register
Offset: 0x204, size: 32, reset: 0x00000000, access: read-write
0/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
FBM[27]
rw |
FBM[26]
rw |
FBM[25]
rw |
FBM[24]
rw |
FBM[23]
rw |
FBM[22]
rw |
FBM[21]
rw |
FBM[20]
rw |
FBM[19]
rw |
FBM[18]
rw |
FBM[17]
rw |
FBM[16]
rw |
||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FBM[15]
rw |
FBM[14]
rw |
FBM[13]
rw |
FBM[12]
rw |
FBM[11]
rw |
FBM[10]
rw |
FBM[9]
rw |
FBM[8]
rw |
FBM[7]
rw |
FBM[6]
rw |
FBM[5]
rw |
FBM[4]
rw |
FBM[3]
rw |
FBM[2]
rw |
FBM[1]
rw |
FBM[0]
rw |
Bit 0: Filter mode.
Bit 1: Filter mode.
Bit 2: Filter mode.
Bit 3: Filter mode.
Bit 4: Filter mode.
Bit 5: Filter mode.
Bit 6: Filter mode.
Bit 7: Filter mode.
Bit 8: Filter mode.
Bit 9: Filter mode.
Bit 10: Filter mode.
Bit 11: Filter mode.
Bit 12: Filter mode.
Bit 13: Filter mode.
Bit 14: Filter mode.
Bit 15: Filter mode.
Bit 16: Filter mode.
Bit 17: Filter mode.
Bit 18: Filter mode.
Bit 19: Filter mode.
Bit 20: Filter mode.
Bit 21: Filter mode.
Bit 22: Filter mode.
Bit 23: Filter mode.
Bit 24: Filter mode.
Bit 25: Filter mode.
Bit 26: Filter mode.
Bit 27: Filter mode.
filter scale register
Offset: 0x20c, size: 32, reset: 0x00000000, access: read-write
0/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
FSC[27]
rw |
FSC[26]
rw |
FSC[25]
rw |
FSC[24]
rw |
FSC[23]
rw |
FSC[22]
rw |
FSC[21]
rw |
FSC[20]
rw |
FSC[19]
rw |
FSC[18]
rw |
FSC[17]
rw |
FSC[16]
rw |
||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FSC[15]
rw |
FSC[14]
rw |
FSC[13]
rw |
FSC[12]
rw |
FSC[11]
rw |
FSC[10]
rw |
FSC[9]
rw |
FSC[8]
rw |
FSC[7]
rw |
FSC[6]
rw |
FSC[5]
rw |
FSC[4]
rw |
FSC[3]
rw |
FSC[2]
rw |
FSC[1]
rw |
FSC[0]
rw |
Bit 0: Filter scale configuration.
Bit 1: Filter scale configuration.
Bit 2: Filter scale configuration.
Bit 3: Filter scale configuration.
Bit 4: Filter scale configuration.
Bit 5: Filter scale configuration.
Bit 6: Filter scale configuration.
Bit 7: Filter scale configuration.
Bit 8: Filter scale configuration.
Bit 9: Filter scale configuration.
Bit 10: Filter scale configuration.
Bit 11: Filter scale configuration.
Bit 12: Filter scale configuration.
Bit 13: Filter scale configuration.
Bit 14: Filter scale configuration.
Bit 15: Filter scale configuration.
Bit 16: Filter scale configuration.
Bit 17: Filter scale configuration.
Bit 18: Filter scale configuration.
Bit 19: Filter scale configuration.
Bit 20: Filter scale configuration.
Bit 21: Filter scale configuration.
Bit 22: Filter scale configuration.
Bit 23: Filter scale configuration.
Bit 24: Filter scale configuration.
Bit 25: Filter scale configuration.
Bit 26: Filter scale configuration.
Bit 27: Filter scale configuration.
filter FIFO assignment register
Offset: 0x214, size: 32, reset: 0x00000000, access: read-write
0/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
FFA[27]
rw |
FFA[26]
rw |
FFA[25]
rw |
FFA[24]
rw |
FFA[23]
rw |
FFA[22]
rw |
FFA[21]
rw |
FFA[20]
rw |
FFA[19]
rw |
FFA[18]
rw |
FFA[17]
rw |
FFA[16]
rw |
||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FFA[15]
rw |
FFA[14]
rw |
FFA[13]
rw |
FFA[12]
rw |
FFA[11]
rw |
FFA[10]
rw |
FFA[9]
rw |
FFA[8]
rw |
FFA[7]
rw |
FFA[6]
rw |
FFA[5]
rw |
FFA[4]
rw |
FFA[3]
rw |
FFA[2]
rw |
FFA[1]
rw |
FFA[0]
rw |
Bit 0: Filter FIFO assignment for filter 0.
Bit 1: Filter FIFO assignment for filter 1.
Bit 2: Filter FIFO assignment for filter 2.
Bit 3: Filter FIFO assignment for filter 3.
Bit 4: Filter FIFO assignment for filter 4.
Bit 5: Filter FIFO assignment for filter 5.
Bit 6: Filter FIFO assignment for filter 6.
Bit 7: Filter FIFO assignment for filter 7.
Bit 8: Filter FIFO assignment for filter 8.
Bit 9: Filter FIFO assignment for filter 9.
Bit 10: Filter FIFO assignment for filter 10.
Bit 11: Filter FIFO assignment for filter 11.
Bit 12: Filter FIFO assignment for filter 12.
Bit 13: Filter FIFO assignment for filter 13.
Bit 14: Filter FIFO assignment for filter 14.
Bit 15: Filter FIFO assignment for filter 15.
Bit 16: Filter FIFO assignment for filter 16.
Bit 17: Filter FIFO assignment for filter 17.
Bit 18: Filter FIFO assignment for filter 18.
Bit 19: Filter FIFO assignment for filter 19.
Bit 20: Filter FIFO assignment for filter 20.
Bit 21: Filter FIFO assignment for filter 21.
Bit 22: Filter FIFO assignment for filter 22.
Bit 23: Filter FIFO assignment for filter 23.
Bit 24: Filter FIFO assignment for filter 24.
Bit 25: Filter FIFO assignment for filter 25.
Bit 26: Filter FIFO assignment for filter 26.
Bit 27: Filter FIFO assignment for filter 27.
CAN filter activation register
Offset: 0x21c, size: 32, reset: 0x00000000, access: read-write
0/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
FACT[27]
rw |
FACT[26]
rw |
FACT[25]
rw |
FACT[24]
rw |
FACT[23]
rw |
FACT[22]
rw |
FACT[21]
rw |
FACT[20]
rw |
FACT[19]
rw |
FACT[18]
rw |
FACT[17]
rw |
FACT[16]
rw |
||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FACT[15]
rw |
FACT[14]
rw |
FACT[13]
rw |
FACT[12]
rw |
FACT[11]
rw |
FACT[10]
rw |
FACT[9]
rw |
FACT[8]
rw |
FACT[7]
rw |
FACT[6]
rw |
FACT[5]
rw |
FACT[4]
rw |
FACT[3]
rw |
FACT[2]
rw |
FACT[1]
rw |
FACT[0]
rw |
Bit 0: Filter active.
Bit 1: Filter active.
Bit 2: Filter active.
Bit 3: Filter active.
Bit 4: Filter active.
Bit 5: Filter active.
Bit 6: Filter active.
Bit 7: Filter active.
Bit 8: Filter active.
Bit 9: Filter active.
Bit 10: Filter active.
Bit 11: Filter active.
Bit 12: Filter active.
Bit 13: Filter active.
Bit 14: Filter active.
Bit 15: Filter active.
Bit 16: Filter active.
Bit 17: Filter active.
Bit 18: Filter active.
Bit 19: Filter active.
Bit 20: Filter active.
Bit 21: Filter active.
Bit 22: Filter active.
Bit 23: Filter active.
Bit 24: Filter active.
Bit 25: Filter active.
Bit 26: Filter active.
Bit 27: Filter active.
Filter bank x register 1
Offset: 0x240, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x244, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x248, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x24c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x250, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x254, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x258, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x25c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x260, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x264, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x268, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x26c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x270, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x274, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x278, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x27c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x280, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x284, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x288, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x28c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x290, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x294, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x298, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x29c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x2a0, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x2a4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x2a8, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x2ac, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x2b0, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x2b4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x2b8, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x2bc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x2c0, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x2c4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x2c8, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x2cc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x2d0, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x2d4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x2d8, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x2dc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x2e0, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x2e4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x2e8, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x2ec, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x2f0, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x2f4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x2f8, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x2fc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x300, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x304, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x308, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x30c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x310, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x314, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
0x40007800: HDMI-CEC controller
4/40 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR | ||||||||||||||||||||||||||||||||
| 0x4 | CFGR | ||||||||||||||||||||||||||||||||
| 0x8 | TXDR | ||||||||||||||||||||||||||||||||
| 0xc | RXDR | ||||||||||||||||||||||||||||||||
| 0x10 | ISR | ||||||||||||||||||||||||||||||||
| 0x14 | IER | ||||||||||||||||||||||||||||||||
control register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
configuration register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
2/9 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
LSTN
rw |
OAR
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SFTOP
rw |
BRDNOGEN
rw |
LBPEGEN
rw |
BREGEN
rw |
BRESTP
rw |
RXTOL
rw |
SFT
rw |
|||||||||
Bits 0-2: Signal Free Time.
Allowed values: 0x0-0x7
Bit 3: Rx-Tolerance.
Bit 4: Rx-stop on bit rising error.
Bit 5: Generate error-bit on bit rising error.
Bit 6: Generate Error-Bit on Long Bit Period Error.
Bit 7: Avoid Error-Bit Generation in Broadcast.
Bit 8: SFT Option Bit.
Bits 16-30: Own Address.
Allowed values: 0x0-0x7fff
Bit 31: Listen mode.
Tx data register
Offset: 0x8, size: 32, reset: 0x00000000, access: write-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TXD
w |
|||||||||||||||
Rx Data Register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
RXDR
r |
|||||||||||||||
Interrupt and Status Register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
0/13 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TXACKE
rw |
TXERR
rw |
TXUDR
rw |
TXEND
rw |
TXBR
rw |
ARBLST
rw |
RXACKE
rw |
LBPE
rw |
SBPE
rw |
BRE
rw |
RXOVR
rw |
RXEND
rw |
RXBR
rw |
|||
Bit 0: Rx-Byte Received.
Bit 1: End Of Reception.
Bit 2: Rx-Overrun.
Bit 3: Rx-Bit rising error.
Bit 4: Rx-Short Bit period error.
Bit 5: Rx-Long Bit Period Error.
Bit 6: Rx-Missing Acknowledge.
Bit 7: Arbitration Lost.
Bit 8: Tx-Byte Request.
Bit 9: End of Transmission.
Bit 10: Tx-Buffer Underrun.
Bit 11: Tx-Error.
Bit 12: Tx-Missing acknowledge error.
interrupt enable register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
0/13 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TXACKIE
rw |
TXERRIE
rw |
TXUDRIE
rw |
TXENDIE
rw |
TXBRIE
rw |
ARBLSTIE
rw |
RXACKIE
rw |
LBPEIE
rw |
SBPEIE
rw |
BREIE
rw |
RXOVRIE
rw |
RXENDIE
rw |
RXBRIE
rw |
|||
Bit 0: Rx-Byte Received Interrupt Enable.
Bit 1: End Of Reception Interrupt Enable.
Bit 2: Rx-Buffer Overrun Interrupt Enable.
Bit 3: Bit Rising Error Interrupt Enable.
Bit 4: Short Bit Period Error Interrupt Enable.
Bit 5: Long Bit Period Error Interrupt Enable.
Bit 6: Rx-Missing Acknowledge Error Interrupt Enable.
Bit 7: Arbitration Lost Interrupt Enable.
Bit 8: Tx-Byte Request Interrupt Enable.
Bit 9: Tx-End of message interrupt enable.
Bit 10: Tx-Underrun interrupt enable.
Bit 11: Tx-Error Interrupt Enable.
Bit 12: Tx-Missing Acknowledge Error Interrupt Enable.
0x40010000: General purpose comparators
2/18 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x1c | CSR | ||||||||||||||||||||||||||||||||
control and status register
Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified
2/18 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
COMP2LOCK
rw |
COMP2OUT
r |
COMP2HYST
rw |
COMP2POL
rw |
COMP2OUTSEL
rw |
WNDWEN
rw |
COMP2INSEL
rw |
COMP2MODE
rw |
COMP2EN
rw |
|||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
COMP1LOCK
rw |
COMP1OUT
r |
COMP1HYST
rw |
COMP1POL
rw |
COMP1OUTSEL
rw |
COMP1INSEL
rw |
COMP1MODE
rw |
COMP1_INP_DAC
rw |
COMP1EN
rw |
|||||||
Bit 0: Comparator 1 enable.
Bit 1: Comparator 1 non inverting input connection to DAC output.
Bits 2-3: Comparator 1 mode.
Bits 4-6: Comparator 1 inverting input selection.
Bits 8-10: Comparator 1 output selection.
Bit 11: Comparator 1 output polarity.
Bits 12-13: Comparator 1 hysteresis.
Bit 14: Comparator 1 output.
Bit 15: Comparator 1 lock.
Bit 16: Comparator 2 enable.
Bits 18-19: Comparator 2 mode.
Bits 20-22: Comparator 2 inverting input selection.
Bit 23: Window mode enable.
Bits 24-26: Comparator 2 output selection.
Bit 27: Comparator 2 output polarity.
Bits 28-29: Comparator 2 hysteresis.
Bit 30: Comparator 2 output.
Bit 31: Comparator 2 lock.
0x40023000: cyclic redundancy check calculation unit
10/10 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | DR | ||||||||||||||||||||||||||||||||
| 0x0 (16-bit) | DR16 | ||||||||||||||||||||||||||||||||
| 0x0 (8-bit) | DR8 | ||||||||||||||||||||||||||||||||
| 0x4 | IDR | ||||||||||||||||||||||||||||||||
| 0x8 | CR | ||||||||||||||||||||||||||||||||
| 0x10 | INIT | ||||||||||||||||||||||||||||||||
| 0x14 | POL | ||||||||||||||||||||||||||||||||
Data register - half-word sized
Offset: 0x0, size: 16, reset: 0x0000FFFF, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DR16
rw |
|||||||||||||||
Data register - byte sized
Offset: 0x0, size: 8, reset: 0x000000FF, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DR8
rw |
|||||||||||||||
Independent data register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IDR
rw |
|||||||||||||||
Control register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
4/4 fields covered.
Bit 0: reset bit.
Allowed values:
1: Reset: Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF
Bits 3-4: Polynomial size.
Allowed values:
0: Polysize32: 32-bit polynomial
1: Polysize16: 16-bit polynomial
2: Polysize8: 8-bit polynomial
3: Polysize7: 7-bit polynomial
Bits 5-6: Reverse input data.
Allowed values:
0: Normal: Bit order not affected
1: Byte: Bit reversal done by byte
2: HalfWord: Bit reversal done by half-word
3: Word: Bit reversal done by word
Bit 7: Reverse output data.
Allowed values:
0: Normal: Bit order not affected
1: Reversed: Bit reversed output
0x40007400: Digital-to-analog converter
2/34 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR | ||||||||||||||||||||||||||||||||
| 0x4 | SWTRIGR | ||||||||||||||||||||||||||||||||
| 0x8 | DHR12R1 | ||||||||||||||||||||||||||||||||
| 0xc | DHR12L1 | ||||||||||||||||||||||||||||||||
| 0x10 | DHR8R1 | ||||||||||||||||||||||||||||||||
| 0x14 | DHR12R2 | ||||||||||||||||||||||||||||||||
| 0x18 | DHR12L2 | ||||||||||||||||||||||||||||||||
| 0x1c | DHR8R2 | ||||||||||||||||||||||||||||||||
| 0x20 | DHR12RD | ||||||||||||||||||||||||||||||||
| 0x24 | DHR12LD | ||||||||||||||||||||||||||||||||
| 0x28 | DHR8RD | ||||||||||||||||||||||||||||||||
| 0x2c | DOR1 | ||||||||||||||||||||||||||||||||
| 0x30 | DOR2 | ||||||||||||||||||||||||||||||||
| 0x34 | SR | ||||||||||||||||||||||||||||||||
control register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
0/16 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DMAUDRIE2
rw |
DMAEN2
rw |
MAMP2
rw |
WAVE2
rw |
TSEL2
rw |
TEN2
rw |
BOFF2
rw |
EN2
rw |
||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAUDRIE1
rw |
DMAEN1
rw |
MAMP1
rw |
WAVE1
rw |
TSEL1
rw |
TEN1
rw |
BOFF1
rw |
EN1
rw |
||||||||
Bit 0: DAC channel1 enable.
Bit 1: DAC channel1 output buffer disable.
Bit 2: DAC channel1 trigger enable.
Bits 3-5: DAC channel1 trigger selection.
Bits 6-7: DAC channel1 noise/triangle wave generation enable.
Bits 8-11: DAC channel1 mask/amplitude selector.
Bit 12: DAC channel1 DMA enable.
Bit 13: DAC channel1 DMA Underrun Interrupt enable.
Bit 16: DAC channel2 enable.
Bit 17: DAC channel2 output buffer disable.
Bit 18: DAC channel2 trigger enable.
Bits 19-21: DAC channel2 trigger selection.
Bits 22-23: DAC channel2 noise/triangle wave generation enable.
Bits 24-27: DAC channel2 mask/amplitude selector.
Bit 28: DAC channel2 DMA enable.
Bit 29: DAC channel2 DMA underrun interrupt enable.
software trigger register
Offset: 0x4, size: 32, reset: 0x00000000, access: write-only
0/2 fields covered.
channel1 12-bit right-aligned data holding register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DACC1DHR
rw |
|||||||||||||||
channel1 12-bit left aligned data holding register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DACC1DHR
rw |
|||||||||||||||
channel1 8-bit right aligned data holding register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DACC1DHR
rw |
|||||||||||||||
channel2 12-bit right aligned data holding register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DACC2DHR
rw |
|||||||||||||||
channel2 12-bit left aligned data holding register
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DACC2DHR
rw |
|||||||||||||||
channel2 8-bit right-aligned data holding register
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DACC2DHR
rw |
|||||||||||||||
Dual DAC 12-bit right-aligned data holding register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
DUAL DAC 12-bit left aligned data holding register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
DUAL DAC 8-bit right aligned data holding register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
channel1 data output register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DACC1DOR
r |
|||||||||||||||
channel2 data output register
Offset: 0x30, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DACC2DOR
r |
|||||||||||||||
0x40009800: Digital-to-analog converter
1/18 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR | ||||||||||||||||||||||||||||||||
| 0x4 | SWTRIGR | ||||||||||||||||||||||||||||||||
| 0x8 | DHR12R1 | ||||||||||||||||||||||||||||||||
| 0xc | DHR12L1 | ||||||||||||||||||||||||||||||||
| 0x10 | DHR8R1 | ||||||||||||||||||||||||||||||||
| 0x2c | DOR1 | ||||||||||||||||||||||||||||||||
| 0x34 | SR | ||||||||||||||||||||||||||||||||
control register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
0/12 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DMAUDRIE1
rw |
DMAEN1
rw |
MAMP13
rw |
MAMP12
rw |
MAMP11
rw |
MAMP10
rw |
WAVE1
rw |
WAVE2
rw |
TSEL1
rw |
TEN1
rw |
BOFF1
rw |
EN1
rw |
||||
Bit 0: DAC channel1 enable.
Bit 1: DAC channel1 output buffer disable.
Bit 2: DAC channel1 trigger enable.
Bits 3-5: DAC channel1 trigger selection.
Bit 6: WAVE2.
Bit 7: DAC channel1 noise/triangle wave generation enable.
Bit 8: MAMP10.
Bit 9: MAMP11.
Bit 10: MAMP12.
Bit 11: DAC channel1 mask/amplitude selector.
Bit 12: DAC channel1 DMA enable.
Bit 13: DAC channel1 DMA Underrun Interrupt enable.
software trigger register
Offset: 0x4, size: 32, reset: 0x00000000, access: write-only
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SWTRIG1
w |
|||||||||||||||
channel1 12-bit right-aligned data holding register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DACC1DHR
rw |
|||||||||||||||
DAC channel1 12-bit left aligned data holding register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DACC1DHR
rw |
|||||||||||||||
DAC channel1 8-bit right aligned data holding register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DACC1DHR
rw |
|||||||||||||||
DAC channel1 data output register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DACC1DOR
r |
|||||||||||||||
DAC status register
Offset: 0x34, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DMAUDR1
rw |
|||||||||||||||
0xe0042000: Debug support
2/27 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | IDCODE | ||||||||||||||||||||||||||||||||
| 0x4 | CR | ||||||||||||||||||||||||||||||||
| 0x8 | APB1_FZ | ||||||||||||||||||||||||||||||||
| 0xc | APB2_FZ | ||||||||||||||||||||||||||||||||
MCU Device ID Code Register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-only
2/2 fields covered.
Debug MCU Configuration Register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
0/5 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TRACE_MODE
rw |
TRACE_IOEN
rw |
DBG_STANDBY
rw |
DBG_STOP
rw |
DBG_SLEEP
rw |
|||||||||||
APB Low Freeze Register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
0/16 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DBG_CAN_STOP
rw |
I2C2_SMBUS_TIMEOUT
rw |
I2C1_SMBUS_TIMEOUT
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DBG_IWDG_STOP
rw |
DBG_WWDG_STOP
rw |
DBG_RTC_STOP
rw |
DBG_TIM18_STOP
rw |
DBG_TIMER14_STOP
rw |
DBG_TIM13_STOP
rw |
DBG_TIM12_STOP
rw |
DBG_TIM7_STOP
rw |
DBG_TIM6_STOP
rw |
DBG_TIM5_STOP
rw |
DBG_TIM4_STOP
rw |
DBG_TIM3_STOP
rw |
DBG_TIM2_STOP
rw |
|||
Bit 0: Debug Timer 2 stopped when Core is halted.
Bit 1: Debug Timer 3 stopped when Core is halted.
Bit 2: Debug Timer 4 stopped when Core is halted.
Bit 3: Debug Timer 5 stopped when Core is halted.
Bit 4: Debug Timer 6 stopped when Core is halted.
Bit 5: Debug Timer 7 stopped when Core is halted.
Bit 6: Debug Timer 12 stopped when Core is halted.
Bit 7: Debug Timer 13 stopped when Core is halted.
Bit 8: Debug Timer 14 stopped when Core is halted.
Bit 9: Debug Timer 18 stopped when Core is halted.
Bit 10: Debug RTC stopped when Core is halted.
Bit 11: Debug Window Wachdog stopped when Core is halted.
Bit 12: Debug Independent Wachdog stopped when Core is halted.
Bit 21: SMBUS timeout mode stopped when Core is halted.
Bit 22: SMBUS timeout mode stopped when Core is halted.
Bit 25: Debug CAN stopped when core is halted.
APB High Freeze Register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DBG_TIM19_STOP
rw |
DBG_TIM17_STO
rw |
DBG_TIM16_STOP
rw |
DBG_TIM15_STOP
rw |
||||||||||||
0x40020000: DMA controller 1
147/161 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | ISR | ||||||||||||||||||||||||||||||||
| 0x4 | IFCR | ||||||||||||||||||||||||||||||||
| 0x8 | CR [1] | ||||||||||||||||||||||||||||||||
| 0xc | NDTR [1] | ||||||||||||||||||||||||||||||||
| 0x10 | PAR [1] | ||||||||||||||||||||||||||||||||
| 0x14 | MAR [1] | ||||||||||||||||||||||||||||||||
| 0x1c | CR [2] | ||||||||||||||||||||||||||||||||
| 0x20 | NDTR [2] | ||||||||||||||||||||||||||||||||
| 0x24 | PAR [2] | ||||||||||||||||||||||||||||||||
| 0x28 | MAR [2] | ||||||||||||||||||||||||||||||||
| 0x30 | CR [3] | ||||||||||||||||||||||||||||||||
| 0x34 | NDTR [3] | ||||||||||||||||||||||||||||||||
| 0x38 | PAR [3] | ||||||||||||||||||||||||||||||||
| 0x3c | MAR [3] | ||||||||||||||||||||||||||||||||
| 0x44 | CR [4] | ||||||||||||||||||||||||||||||||
| 0x48 | NDTR [4] | ||||||||||||||||||||||||||||||||
| 0x4c | PAR [4] | ||||||||||||||||||||||||||||||||
| 0x50 | MAR [4] | ||||||||||||||||||||||||||||||||
| 0x58 | CR [5] | ||||||||||||||||||||||||||||||||
| 0x5c | NDTR [5] | ||||||||||||||||||||||||||||||||
| 0x60 | PAR [5] | ||||||||||||||||||||||||||||||||
| 0x64 | MAR [5] | ||||||||||||||||||||||||||||||||
| 0x6c | CR [6] | ||||||||||||||||||||||||||||||||
| 0x70 | NDTR [6] | ||||||||||||||||||||||||||||||||
| 0x74 | PAR [6] | ||||||||||||||||||||||||||||||||
| 0x78 | MAR [6] | ||||||||||||||||||||||||||||||||
| 0x80 | CR [7] | ||||||||||||||||||||||||||||||||
| 0x84 | NDTR [7] | ||||||||||||||||||||||||||||||||
| 0x88 | PAR [7] | ||||||||||||||||||||||||||||||||
| 0x8c | MAR [7] | ||||||||||||||||||||||||||||||||
DMA interrupt status register (DMA_ISR)
Offset: 0x0, size: 32, reset: 0x00000000, access: read-only
28/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TEIF[7]
r |
HTIF[7]
r |
TCIF[7]
r |
GIF[7]
r |
TEIF[6]
r |
HTIF[6]
r |
TCIF[6]
r |
GIF[6]
r |
TEIF[5]
r |
HTIF[5]
r |
TCIF[5]
r |
GIF[5]
r |
||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TEIF[4]
r |
HTIF[4]
r |
TCIF[4]
r |
GIF[4]
r |
TEIF[3]
r |
HTIF[3]
r |
TCIF[3]
r |
GIF[3]
r |
TEIF[2]
r |
HTIF[2]
r |
TCIF[2]
r |
GIF[2]
r |
TEIF[1]
r |
HTIF[1]
r |
TCIF[1]
r |
GIF[1]
r |
Bit 0: Channel 1 Global interrupt flag.
Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured
Bit 1: Channel 1 Transfer Complete flag.
Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured
Bit 2: Channel 1 Half Transfer Complete flag.
Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured
Bit 3: Channel 1 Transfer Error flag.
Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured
Bit 4: Channel 2 Global interrupt flag.
Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured
Bit 5: Channel 2 Transfer Complete flag.
Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured
Bit 6: Channel 2 Half Transfer Complete flag.
Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured
Bit 7: Channel 2 Transfer Error flag.
Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured
Bit 8: Channel 3 Global interrupt flag.
Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured
Bit 9: Channel 3 Transfer Complete flag.
Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured
Bit 10: Channel 3 Half Transfer Complete flag.
Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured
Bit 11: Channel 3 Transfer Error flag.
Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured
Bit 12: Channel 4 Global interrupt flag.
Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured
Bit 13: Channel 4 Transfer Complete flag.
Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured
Bit 14: Channel 4 Half Transfer Complete flag.
Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured
Bit 15: Channel 4 Transfer Error flag.
Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured
Bit 16: Channel 5 Global interrupt flag.
Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured
Bit 17: Channel 5 Transfer Complete flag.
Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured
Bit 18: Channel 5 Half Transfer Complete flag.
Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured
Bit 19: Channel 5 Transfer Error flag.
Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured
Bit 20: Channel 6 Global interrupt flag.
Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured
Bit 21: Channel 6 Transfer Complete flag.
Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured
Bit 22: Channel 6 Half Transfer Complete flag.
Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured
Bit 23: Channel 6 Transfer Error flag.
Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured
Bit 24: Channel 7 Global interrupt flag.
Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured
Bit 25: Channel 7 Transfer Complete flag.
Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured
Bit 26: Channel 7 Half Transfer Complete flag.
Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured
Bit 27: Channel 7 Transfer Error flag.
Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured
DMA interrupt flag clear register (DMA_IFCR)
Offset: 0x4, size: 32, reset: 0x00000000, access: write-only
28/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CTEIF[7]
w |
CHTIF[7]
w |
CTCIF[7]
w |
CGIF[7]
w |
CTEIF[6]
w |
CHTIF[6]
w |
CTCIF[6]
w |
CGIF[6]
w |
CTEIF[5]
w |
CHTIF[5]
w |
CTCIF[5]
w |
CGIF[5]
w |
||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CTEIF[4]
w |
CHTIF[4]
w |
CTCIF[4]
w |
CGIF[4]
w |
CTEIF[3]
w |
CHTIF[3]
w |
CTCIF[3]
w |
CGIF[3]
w |
CTEIF[2]
w |
CHTIF[2]
w |
CTCIF[2]
w |
CGIF[2]
w |
CTEIF[1]
w |
CHTIF[1]
w |
CTCIF[1]
w |
CGIF[1]
w |
Bit 0: Channel 1 Global interrupt clear.
Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
Bit 1: Channel 1 Transfer Complete clear.
Allowed values:
1: Clear: Clears the TCIF flag in the ISR register
Bit 2: Channel 1 Half Transfer clear.
Allowed values:
1: Clear: Clears the HTIF flag in the ISR register
Bit 3: Channel 1 Transfer Error clear.
Allowed values:
1: Clear: Clears the TEIF flag in the ISR register
Bit 4: Channel 2 Global interrupt clear.
Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
Bit 5: Channel 2 Transfer Complete clear.
Allowed values:
1: Clear: Clears the TCIF flag in the ISR register
Bit 6: Channel 2 Half Transfer clear.
Allowed values:
1: Clear: Clears the HTIF flag in the ISR register
Bit 7: Channel 2 Transfer Error clear.
Allowed values:
1: Clear: Clears the TEIF flag in the ISR register
Bit 8: Channel 3 Global interrupt clear.
Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
Bit 9: Channel 3 Transfer Complete clear.
Allowed values:
1: Clear: Clears the TCIF flag in the ISR register
Bit 10: Channel 3 Half Transfer clear.
Allowed values:
1: Clear: Clears the HTIF flag in the ISR register
Bit 11: Channel 3 Transfer Error clear.
Allowed values:
1: Clear: Clears the TEIF flag in the ISR register
Bit 12: Channel 4 Global interrupt clear.
Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
Bit 13: Channel 4 Transfer Complete clear.
Allowed values:
1: Clear: Clears the TCIF flag in the ISR register
Bit 14: Channel 4 Half Transfer clear.
Allowed values:
1: Clear: Clears the HTIF flag in the ISR register
Bit 15: Channel 4 Transfer Error clear.
Allowed values:
1: Clear: Clears the TEIF flag in the ISR register
Bit 16: Channel 5 Global interrupt clear.
Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
Bit 17: Channel 5 Transfer Complete clear.
Allowed values:
1: Clear: Clears the TCIF flag in the ISR register
Bit 18: Channel 5 Half Transfer clear.
Allowed values:
1: Clear: Clears the HTIF flag in the ISR register
Bit 19: Channel 5 Transfer Error clear.
Allowed values:
1: Clear: Clears the TEIF flag in the ISR register
Bit 20: Channel 6 Global interrupt clear.
Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
Bit 21: Channel 6 Transfer Complete clear.
Allowed values:
1: Clear: Clears the TCIF flag in the ISR register
Bit 22: Channel 6 Half Transfer clear.
Allowed values:
1: Clear: Clears the HTIF flag in the ISR register
Bit 23: Channel 6 Transfer Error clear.
Allowed values:
1: Clear: Clears the TEIF flag in the ISR register
Bit 24: Channel 7 Global interrupt clear.
Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
Bit 25: Channel 7 Transfer Complete clear.
Allowed values:
1: Clear: Clears the TCIF flag in the ISR register
Bit 26: Channel 7 Half Transfer clear.
Allowed values:
1: Clear: Clears the HTIF flag in the ISR register
Bit 27: Channel 7 Transfer Error clear.
Allowed values:
1: Clear: Clears the TEIF flag in the ISR register
DMA channel configuration register (DMA_CCR)
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
12/12 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MEM2MEM
rw |
PL
rw |
MSIZE
rw |
PSIZE
rw |
MINC
rw |
PINC
rw |
CIRC
rw |
DIR
rw |
TEIE
rw |
HTIE
rw |
TCIE
rw |
EN
rw |
||||
Bit 0: Channel enable.
Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled
Bit 1: Transfer complete interrupt enable.
Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled
Bit 2: Half Transfer interrupt enable.
Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled
Bit 3: Transfer error interrupt enable.
Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled
Bit 4: Data transfer direction.
Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory
Bit 5: Circular mode.
Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled
Bit 6: Peripheral increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bit 7: Memory increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bits 8-9: Peripheral size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 10-11: Memory size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 12-13: Channel Priority level.
Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority
Bit 14: Memory to memory mode.
Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled
DMA channel 1 number of data register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
NDT
rw |
|||||||||||||||
DMA channel 1 peripheral address register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
DMA channel 1 memory address register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
DMA channel configuration register (DMA_CCR)
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
12/12 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MEM2MEM
rw |
PL
rw |
MSIZE
rw |
PSIZE
rw |
MINC
rw |
PINC
rw |
CIRC
rw |
DIR
rw |
TEIE
rw |
HTIE
rw |
TCIE
rw |
EN
rw |
||||
Bit 0: Channel enable.
Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled
Bit 1: Transfer complete interrupt enable.
Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled
Bit 2: Half Transfer interrupt enable.
Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled
Bit 3: Transfer error interrupt enable.
Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled
Bit 4: Data transfer direction.
Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory
Bit 5: Circular mode.
Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled
Bit 6: Peripheral increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bit 7: Memory increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bits 8-9: Peripheral size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 10-11: Memory size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 12-13: Channel Priority level.
Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority
Bit 14: Memory to memory mode.
Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled
DMA channel 1 number of data register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
NDT
rw |
|||||||||||||||
DMA channel 1 peripheral address register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
DMA channel 1 memory address register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
DMA channel configuration register (DMA_CCR)
Offset: 0x30, size: 32, reset: 0x00000000, access: read-write
12/12 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MEM2MEM
rw |
PL
rw |
MSIZE
rw |
PSIZE
rw |
MINC
rw |
PINC
rw |
CIRC
rw |
DIR
rw |
TEIE
rw |
HTIE
rw |
TCIE
rw |
EN
rw |
||||
Bit 0: Channel enable.
Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled
Bit 1: Transfer complete interrupt enable.
Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled
Bit 2: Half Transfer interrupt enable.
Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled
Bit 3: Transfer error interrupt enable.
Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled
Bit 4: Data transfer direction.
Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory
Bit 5: Circular mode.
Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled
Bit 6: Peripheral increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bit 7: Memory increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bits 8-9: Peripheral size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 10-11: Memory size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 12-13: Channel Priority level.
Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority
Bit 14: Memory to memory mode.
Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled
DMA channel 1 number of data register
Offset: 0x34, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
NDT
rw |
|||||||||||||||
DMA channel 1 peripheral address register
Offset: 0x38, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
DMA channel 1 memory address register
Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
DMA channel configuration register (DMA_CCR)
Offset: 0x44, size: 32, reset: 0x00000000, access: read-write
12/12 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MEM2MEM
rw |
PL
rw |
MSIZE
rw |
PSIZE
rw |
MINC
rw |
PINC
rw |
CIRC
rw |
DIR
rw |
TEIE
rw |
HTIE
rw |
TCIE
rw |
EN
rw |
||||
Bit 0: Channel enable.
Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled
Bit 1: Transfer complete interrupt enable.
Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled
Bit 2: Half Transfer interrupt enable.
Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled
Bit 3: Transfer error interrupt enable.
Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled
Bit 4: Data transfer direction.
Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory
Bit 5: Circular mode.
Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled
Bit 6: Peripheral increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bit 7: Memory increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bits 8-9: Peripheral size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 10-11: Memory size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 12-13: Channel Priority level.
Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority
Bit 14: Memory to memory mode.
Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled
DMA channel 1 number of data register
Offset: 0x48, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
NDT
rw |
|||||||||||||||
DMA channel 1 peripheral address register
Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
DMA channel 1 memory address register
Offset: 0x50, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
DMA channel configuration register (DMA_CCR)
Offset: 0x58, size: 32, reset: 0x00000000, access: read-write
12/12 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MEM2MEM
rw |
PL
rw |
MSIZE
rw |
PSIZE
rw |
MINC
rw |
PINC
rw |
CIRC
rw |
DIR
rw |
TEIE
rw |
HTIE
rw |
TCIE
rw |
EN
rw |
||||
Bit 0: Channel enable.
Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled
Bit 1: Transfer complete interrupt enable.
Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled
Bit 2: Half Transfer interrupt enable.
Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled
Bit 3: Transfer error interrupt enable.
Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled
Bit 4: Data transfer direction.
Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory
Bit 5: Circular mode.
Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled
Bit 6: Peripheral increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bit 7: Memory increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bits 8-9: Peripheral size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 10-11: Memory size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 12-13: Channel Priority level.
Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority
Bit 14: Memory to memory mode.
Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled
DMA channel 1 number of data register
Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
NDT
rw |
|||||||||||||||
DMA channel 1 peripheral address register
Offset: 0x60, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
DMA channel 1 memory address register
Offset: 0x64, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
DMA channel configuration register (DMA_CCR)
Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write
12/12 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MEM2MEM
rw |
PL
rw |
MSIZE
rw |
PSIZE
rw |
MINC
rw |
PINC
rw |
CIRC
rw |
DIR
rw |
TEIE
rw |
HTIE
rw |
TCIE
rw |
EN
rw |
||||
Bit 0: Channel enable.
Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled
Bit 1: Transfer complete interrupt enable.
Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled
Bit 2: Half Transfer interrupt enable.
Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled
Bit 3: Transfer error interrupt enable.
Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled
Bit 4: Data transfer direction.
Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory
Bit 5: Circular mode.
Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled
Bit 6: Peripheral increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bit 7: Memory increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bits 8-9: Peripheral size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 10-11: Memory size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 12-13: Channel Priority level.
Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority
Bit 14: Memory to memory mode.
Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled
DMA channel 1 number of data register
Offset: 0x70, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
NDT
rw |
|||||||||||||||
DMA channel 1 peripheral address register
Offset: 0x74, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
DMA channel 1 memory address register
Offset: 0x78, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
DMA channel configuration register (DMA_CCR)
Offset: 0x80, size: 32, reset: 0x00000000, access: read-write
12/12 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MEM2MEM
rw |
PL
rw |
MSIZE
rw |
PSIZE
rw |
MINC
rw |
PINC
rw |
CIRC
rw |
DIR
rw |
TEIE
rw |
HTIE
rw |
TCIE
rw |
EN
rw |
||||
Bit 0: Channel enable.
Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled
Bit 1: Transfer complete interrupt enable.
Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled
Bit 2: Half Transfer interrupt enable.
Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled
Bit 3: Transfer error interrupt enable.
Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled
Bit 4: Data transfer direction.
Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory
Bit 5: Circular mode.
Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled
Bit 6: Peripheral increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bit 7: Memory increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bits 8-9: Peripheral size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 10-11: Memory size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 12-13: Channel Priority level.
Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority
Bit 14: Memory to memory mode.
Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled
DMA channel 1 number of data register
Offset: 0x84, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
NDT
rw |
|||||||||||||||
0x40020400: DMA controller 1
147/161 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | ISR | ||||||||||||||||||||||||||||||||
| 0x4 | IFCR | ||||||||||||||||||||||||||||||||
| 0x8 | CR [1] | ||||||||||||||||||||||||||||||||
| 0xc | NDTR [1] | ||||||||||||||||||||||||||||||||
| 0x10 | PAR [1] | ||||||||||||||||||||||||||||||||
| 0x14 | MAR [1] | ||||||||||||||||||||||||||||||||
| 0x1c | CR [2] | ||||||||||||||||||||||||||||||||
| 0x20 | NDTR [2] | ||||||||||||||||||||||||||||||||
| 0x24 | PAR [2] | ||||||||||||||||||||||||||||||||
| 0x28 | MAR [2] | ||||||||||||||||||||||||||||||||
| 0x30 | CR [3] | ||||||||||||||||||||||||||||||||
| 0x34 | NDTR [3] | ||||||||||||||||||||||||||||||||
| 0x38 | PAR [3] | ||||||||||||||||||||||||||||||||
| 0x3c | MAR [3] | ||||||||||||||||||||||||||||||||
| 0x44 | CR [4] | ||||||||||||||||||||||||||||||||
| 0x48 | NDTR [4] | ||||||||||||||||||||||||||||||||
| 0x4c | PAR [4] | ||||||||||||||||||||||||||||||||
| 0x50 | MAR [4] | ||||||||||||||||||||||||||||||||
| 0x58 | CR [5] | ||||||||||||||||||||||||||||||||
| 0x5c | NDTR [5] | ||||||||||||||||||||||||||||||||
| 0x60 | PAR [5] | ||||||||||||||||||||||||||||||||
| 0x64 | MAR [5] | ||||||||||||||||||||||||||||||||
| 0x6c | CR [6] | ||||||||||||||||||||||||||||||||
| 0x70 | NDTR [6] | ||||||||||||||||||||||||||||||||
| 0x74 | PAR [6] | ||||||||||||||||||||||||||||||||
| 0x78 | MAR [6] | ||||||||||||||||||||||||||||||||
| 0x80 | CR [7] | ||||||||||||||||||||||||||||||||
| 0x84 | NDTR [7] | ||||||||||||||||||||||||||||||||
| 0x88 | PAR [7] | ||||||||||||||||||||||||||||||||
| 0x8c | MAR [7] | ||||||||||||||||||||||||||||||||
DMA interrupt status register (DMA_ISR)
Offset: 0x0, size: 32, reset: 0x00000000, access: read-only
28/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TEIF[7]
r |
HTIF[7]
r |
TCIF[7]
r |
GIF[7]
r |
TEIF[6]
r |
HTIF[6]
r |
TCIF[6]
r |
GIF[6]
r |
TEIF[5]
r |
HTIF[5]
r |
TCIF[5]
r |
GIF[5]
r |
||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TEIF[4]
r |
HTIF[4]
r |
TCIF[4]
r |
GIF[4]
r |
TEIF[3]
r |
HTIF[3]
r |
TCIF[3]
r |
GIF[3]
r |
TEIF[2]
r |
HTIF[2]
r |
TCIF[2]
r |
GIF[2]
r |
TEIF[1]
r |
HTIF[1]
r |
TCIF[1]
r |
GIF[1]
r |
Bit 0: Channel 1 Global interrupt flag.
Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured
Bit 1: Channel 1 Transfer Complete flag.
Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured
Bit 2: Channel 1 Half Transfer Complete flag.
Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured
Bit 3: Channel 1 Transfer Error flag.
Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured
Bit 4: Channel 2 Global interrupt flag.
Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured
Bit 5: Channel 2 Transfer Complete flag.
Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured
Bit 6: Channel 2 Half Transfer Complete flag.
Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured
Bit 7: Channel 2 Transfer Error flag.
Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured
Bit 8: Channel 3 Global interrupt flag.
Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured
Bit 9: Channel 3 Transfer Complete flag.
Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured
Bit 10: Channel 3 Half Transfer Complete flag.
Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured
Bit 11: Channel 3 Transfer Error flag.
Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured
Bit 12: Channel 4 Global interrupt flag.
Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured
Bit 13: Channel 4 Transfer Complete flag.
Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured
Bit 14: Channel 4 Half Transfer Complete flag.
Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured
Bit 15: Channel 4 Transfer Error flag.
Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured
Bit 16: Channel 5 Global interrupt flag.
Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured
Bit 17: Channel 5 Transfer Complete flag.
Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured
Bit 18: Channel 5 Half Transfer Complete flag.
Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured
Bit 19: Channel 5 Transfer Error flag.
Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured
Bit 20: Channel 6 Global interrupt flag.
Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured
Bit 21: Channel 6 Transfer Complete flag.
Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured
Bit 22: Channel 6 Half Transfer Complete flag.
Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured
Bit 23: Channel 6 Transfer Error flag.
Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured
Bit 24: Channel 7 Global interrupt flag.
Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured
Bit 25: Channel 7 Transfer Complete flag.
Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured
Bit 26: Channel 7 Half Transfer Complete flag.
Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured
Bit 27: Channel 7 Transfer Error flag.
Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured
DMA interrupt flag clear register (DMA_IFCR)
Offset: 0x4, size: 32, reset: 0x00000000, access: write-only
28/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CTEIF[7]
w |
CHTIF[7]
w |
CTCIF[7]
w |
CGIF[7]
w |
CTEIF[6]
w |
CHTIF[6]
w |
CTCIF[6]
w |
CGIF[6]
w |
CTEIF[5]
w |
CHTIF[5]
w |
CTCIF[5]
w |
CGIF[5]
w |
||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CTEIF[4]
w |
CHTIF[4]
w |
CTCIF[4]
w |
CGIF[4]
w |
CTEIF[3]
w |
CHTIF[3]
w |
CTCIF[3]
w |
CGIF[3]
w |
CTEIF[2]
w |
CHTIF[2]
w |
CTCIF[2]
w |
CGIF[2]
w |
CTEIF[1]
w |
CHTIF[1]
w |
CTCIF[1]
w |
CGIF[1]
w |
Bit 0: Channel 1 Global interrupt clear.
Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
Bit 1: Channel 1 Transfer Complete clear.
Allowed values:
1: Clear: Clears the TCIF flag in the ISR register
Bit 2: Channel 1 Half Transfer clear.
Allowed values:
1: Clear: Clears the HTIF flag in the ISR register
Bit 3: Channel 1 Transfer Error clear.
Allowed values:
1: Clear: Clears the TEIF flag in the ISR register
Bit 4: Channel 2 Global interrupt clear.
Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
Bit 5: Channel 2 Transfer Complete clear.
Allowed values:
1: Clear: Clears the TCIF flag in the ISR register
Bit 6: Channel 2 Half Transfer clear.
Allowed values:
1: Clear: Clears the HTIF flag in the ISR register
Bit 7: Channel 2 Transfer Error clear.
Allowed values:
1: Clear: Clears the TEIF flag in the ISR register
Bit 8: Channel 3 Global interrupt clear.
Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
Bit 9: Channel 3 Transfer Complete clear.
Allowed values:
1: Clear: Clears the TCIF flag in the ISR register
Bit 10: Channel 3 Half Transfer clear.
Allowed values:
1: Clear: Clears the HTIF flag in the ISR register
Bit 11: Channel 3 Transfer Error clear.
Allowed values:
1: Clear: Clears the TEIF flag in the ISR register
Bit 12: Channel 4 Global interrupt clear.
Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
Bit 13: Channel 4 Transfer Complete clear.
Allowed values:
1: Clear: Clears the TCIF flag in the ISR register
Bit 14: Channel 4 Half Transfer clear.
Allowed values:
1: Clear: Clears the HTIF flag in the ISR register
Bit 15: Channel 4 Transfer Error clear.
Allowed values:
1: Clear: Clears the TEIF flag in the ISR register
Bit 16: Channel 5 Global interrupt clear.
Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
Bit 17: Channel 5 Transfer Complete clear.
Allowed values:
1: Clear: Clears the TCIF flag in the ISR register
Bit 18: Channel 5 Half Transfer clear.
Allowed values:
1: Clear: Clears the HTIF flag in the ISR register
Bit 19: Channel 5 Transfer Error clear.
Allowed values:
1: Clear: Clears the TEIF flag in the ISR register
Bit 20: Channel 6 Global interrupt clear.
Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
Bit 21: Channel 6 Transfer Complete clear.
Allowed values:
1: Clear: Clears the TCIF flag in the ISR register
Bit 22: Channel 6 Half Transfer clear.
Allowed values:
1: Clear: Clears the HTIF flag in the ISR register
Bit 23: Channel 6 Transfer Error clear.
Allowed values:
1: Clear: Clears the TEIF flag in the ISR register
Bit 24: Channel 7 Global interrupt clear.
Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
Bit 25: Channel 7 Transfer Complete clear.
Allowed values:
1: Clear: Clears the TCIF flag in the ISR register
Bit 26: Channel 7 Half Transfer clear.
Allowed values:
1: Clear: Clears the HTIF flag in the ISR register
Bit 27: Channel 7 Transfer Error clear.
Allowed values:
1: Clear: Clears the TEIF flag in the ISR register
DMA channel configuration register (DMA_CCR)
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
12/12 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MEM2MEM
rw |
PL
rw |
MSIZE
rw |
PSIZE
rw |
MINC
rw |
PINC
rw |
CIRC
rw |
DIR
rw |
TEIE
rw |
HTIE
rw |
TCIE
rw |
EN
rw |
||||
Bit 0: Channel enable.
Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled
Bit 1: Transfer complete interrupt enable.
Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled
Bit 2: Half Transfer interrupt enable.
Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled
Bit 3: Transfer error interrupt enable.
Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled
Bit 4: Data transfer direction.
Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory
Bit 5: Circular mode.
Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled
Bit 6: Peripheral increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bit 7: Memory increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bits 8-9: Peripheral size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 10-11: Memory size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 12-13: Channel Priority level.
Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority
Bit 14: Memory to memory mode.
Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled
DMA channel 1 number of data register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
NDT
rw |
|||||||||||||||
DMA channel 1 peripheral address register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
DMA channel 1 memory address register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
DMA channel configuration register (DMA_CCR)
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
12/12 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MEM2MEM
rw |
PL
rw |
MSIZE
rw |
PSIZE
rw |
MINC
rw |
PINC
rw |
CIRC
rw |
DIR
rw |
TEIE
rw |
HTIE
rw |
TCIE
rw |
EN
rw |
||||
Bit 0: Channel enable.
Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled
Bit 1: Transfer complete interrupt enable.
Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled
Bit 2: Half Transfer interrupt enable.
Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled
Bit 3: Transfer error interrupt enable.
Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled
Bit 4: Data transfer direction.
Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory
Bit 5: Circular mode.
Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled
Bit 6: Peripheral increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bit 7: Memory increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bits 8-9: Peripheral size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 10-11: Memory size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 12-13: Channel Priority level.
Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority
Bit 14: Memory to memory mode.
Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled
DMA channel 1 number of data register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
NDT
rw |
|||||||||||||||
DMA channel 1 peripheral address register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
DMA channel 1 memory address register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
DMA channel configuration register (DMA_CCR)
Offset: 0x30, size: 32, reset: 0x00000000, access: read-write
12/12 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MEM2MEM
rw |
PL
rw |
MSIZE
rw |
PSIZE
rw |
MINC
rw |
PINC
rw |
CIRC
rw |
DIR
rw |
TEIE
rw |
HTIE
rw |
TCIE
rw |
EN
rw |
||||
Bit 0: Channel enable.
Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled
Bit 1: Transfer complete interrupt enable.
Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled
Bit 2: Half Transfer interrupt enable.
Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled
Bit 3: Transfer error interrupt enable.
Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled
Bit 4: Data transfer direction.
Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory
Bit 5: Circular mode.
Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled
Bit 6: Peripheral increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bit 7: Memory increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bits 8-9: Peripheral size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 10-11: Memory size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 12-13: Channel Priority level.
Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority
Bit 14: Memory to memory mode.
Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled
DMA channel 1 number of data register
Offset: 0x34, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
NDT
rw |
|||||||||||||||
DMA channel 1 peripheral address register
Offset: 0x38, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
DMA channel 1 memory address register
Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
DMA channel configuration register (DMA_CCR)
Offset: 0x44, size: 32, reset: 0x00000000, access: read-write
12/12 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MEM2MEM
rw |
PL
rw |
MSIZE
rw |
PSIZE
rw |
MINC
rw |
PINC
rw |
CIRC
rw |
DIR
rw |
TEIE
rw |
HTIE
rw |
TCIE
rw |
EN
rw |
||||
Bit 0: Channel enable.
Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled
Bit 1: Transfer complete interrupt enable.
Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled
Bit 2: Half Transfer interrupt enable.
Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled
Bit 3: Transfer error interrupt enable.
Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled
Bit 4: Data transfer direction.
Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory
Bit 5: Circular mode.
Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled
Bit 6: Peripheral increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bit 7: Memory increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bits 8-9: Peripheral size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 10-11: Memory size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 12-13: Channel Priority level.
Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority
Bit 14: Memory to memory mode.
Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled
DMA channel 1 number of data register
Offset: 0x48, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
NDT
rw |
|||||||||||||||
DMA channel 1 peripheral address register
Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
DMA channel 1 memory address register
Offset: 0x50, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
DMA channel configuration register (DMA_CCR)
Offset: 0x58, size: 32, reset: 0x00000000, access: read-write
12/12 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MEM2MEM
rw |
PL
rw |
MSIZE
rw |
PSIZE
rw |
MINC
rw |
PINC
rw |
CIRC
rw |
DIR
rw |
TEIE
rw |
HTIE
rw |
TCIE
rw |
EN
rw |
||||
Bit 0: Channel enable.
Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled
Bit 1: Transfer complete interrupt enable.
Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled
Bit 2: Half Transfer interrupt enable.
Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled
Bit 3: Transfer error interrupt enable.
Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled
Bit 4: Data transfer direction.
Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory
Bit 5: Circular mode.
Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled
Bit 6: Peripheral increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bit 7: Memory increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bits 8-9: Peripheral size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 10-11: Memory size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 12-13: Channel Priority level.
Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority
Bit 14: Memory to memory mode.
Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled
DMA channel 1 number of data register
Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
NDT
rw |
|||||||||||||||
DMA channel 1 peripheral address register
Offset: 0x60, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
DMA channel 1 memory address register
Offset: 0x64, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
DMA channel configuration register (DMA_CCR)
Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write
12/12 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MEM2MEM
rw |
PL
rw |
MSIZE
rw |
PSIZE
rw |
MINC
rw |
PINC
rw |
CIRC
rw |
DIR
rw |
TEIE
rw |
HTIE
rw |
TCIE
rw |
EN
rw |
||||
Bit 0: Channel enable.
Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled
Bit 1: Transfer complete interrupt enable.
Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled
Bit 2: Half Transfer interrupt enable.
Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled
Bit 3: Transfer error interrupt enable.
Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled
Bit 4: Data transfer direction.
Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory
Bit 5: Circular mode.
Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled
Bit 6: Peripheral increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bit 7: Memory increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bits 8-9: Peripheral size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 10-11: Memory size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 12-13: Channel Priority level.
Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority
Bit 14: Memory to memory mode.
Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled
DMA channel 1 number of data register
Offset: 0x70, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
NDT
rw |
|||||||||||||||
DMA channel 1 peripheral address register
Offset: 0x74, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
DMA channel 1 memory address register
Offset: 0x78, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
DMA channel configuration register (DMA_CCR)
Offset: 0x80, size: 32, reset: 0x00000000, access: read-write
12/12 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MEM2MEM
rw |
PL
rw |
MSIZE
rw |
PSIZE
rw |
MINC
rw |
PINC
rw |
CIRC
rw |
DIR
rw |
TEIE
rw |
HTIE
rw |
TCIE
rw |
EN
rw |
||||
Bit 0: Channel enable.
Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled
Bit 1: Transfer complete interrupt enable.
Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled
Bit 2: Half Transfer interrupt enable.
Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled
Bit 3: Transfer error interrupt enable.
Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled
Bit 4: Data transfer direction.
Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory
Bit 5: Circular mode.
Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled
Bit 6: Peripheral increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bit 7: Memory increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bits 8-9: Peripheral size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 10-11: Memory size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 12-13: Channel Priority level.
Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority
Bit 14: Memory to memory mode.
Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled
DMA channel 1 number of data register
Offset: 0x84, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
NDT
rw |
|||||||||||||||
0x40010400: External interrupt/event controller
150/150 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | IMR | ||||||||||||||||||||||||||||||||
| 0x4 | EMR | ||||||||||||||||||||||||||||||||
| 0x8 | RTSR | ||||||||||||||||||||||||||||||||
| 0xc | FTSR | ||||||||||||||||||||||||||||||||
| 0x10 | SWIER | ||||||||||||||||||||||||||||||||
| 0x14 | PR |
Interrupt mask register (EXTI_IMR)
Offset: 0x0, size: 32, reset: 0x1F800000, access: read-write
29/29 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MR28
rw |
MR27
rw |
MR26
rw |
MR25
rw |
MR24
rw |
MR23
rw |
MR22
rw |
MR21
rw |
MR20
rw |
MR19
rw |
MR18
rw |
MR17
rw |
MR16
rw |
|||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MR15
rw |
MR14
rw |
MR13
rw |
MR12
rw |
MR11
rw |
MR10
rw |
MR9
rw |
MR8
rw |
MR7
rw |
MR6
rw |
MR5
rw |
MR4
rw |
MR3
rw |
MR2
rw |
MR1
rw |
MR0
rw |
Bit 0: Interrupt Mask on line 0.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 1: Interrupt Mask on line 1.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 2: Interrupt Mask on line 2.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 3: Interrupt Mask on line 3.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 4: Interrupt Mask on line 4.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 5: Interrupt Mask on line 5.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 6: Interrupt Mask on line 6.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 7: Interrupt Mask on line 7.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 8: Interrupt Mask on line 8.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 9: Interrupt Mask on line 9.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 10: Interrupt Mask on line 10.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 11: Interrupt Mask on line 11.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 12: Interrupt Mask on line 12.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 13: Interrupt Mask on line 13.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 14: Interrupt Mask on line 14.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 15: Interrupt Mask on line 15.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 16: Interrupt Mask on line 16.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 17: Interrupt Mask on line 17.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 18: Interrupt Mask on line 18.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 19: Interrupt Mask on line 19.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 20: Interrupt Mask on line 20.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 21: Interrupt Mask on line 21.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 22: Interrupt Mask on line 22.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 23: Interrupt Mask on line 23.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 24: Interrupt Mask on line 24.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 25: Interrupt Mask on line 25.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 26: Interrupt Mask on line 26.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 27: Interrupt Mask on line 27.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 28: Interrupt Mask on line 28.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Event mask register (EXTI_EMR)
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
29/29 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MR28
rw |
MR27
rw |
MR26
rw |
MR25
rw |
MR24
rw |
MR23
rw |
MR22
rw |
MR21
rw |
MR20
rw |
MR19
rw |
MR18
rw |
MR17
rw |
MR16
rw |
|||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MR15
rw |
MR14
rw |
MR13
rw |
MR12
rw |
MR11
rw |
MR10
rw |
MR9
rw |
MR8
rw |
MR7
rw |
MR6
rw |
MR5
rw |
MR4
rw |
MR3
rw |
MR2
rw |
MR1
rw |
MR0
rw |
Bit 0: Event Mask on line 0.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 1: Event Mask on line 1.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 2: Event Mask on line 2.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 3: Event Mask on line 3.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 4: Event Mask on line 4.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 5: Event Mask on line 5.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 6: Event Mask on line 6.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 7: Event Mask on line 7.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 8: Event Mask on line 8.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 9: Event Mask on line 9.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 10: Event Mask on line 10.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 11: Event Mask on line 11.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 12: Event Mask on line 12.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 13: Event Mask on line 13.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 14: Event Mask on line 14.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 15: Event Mask on line 15.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 16: Event Mask on line 16.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 17: Event Mask on line 17.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 18: Event Mask on line 18.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 19: Event Mask on line 19.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 20: Event Mask on line 20.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 21: Event Mask on line 21.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 22: Event Mask on line 22.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 23: Event Mask on line 23.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 24: Event Mask on line 24.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 25: Event Mask on line 25.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 26: Event Mask on line 26.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 27: Event Mask on line 27.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 28: Event Mask on line 28.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Rising Trigger selection register (EXTI_RTSR)
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
23/23 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TR22
rw |
TR21
rw |
TR20
rw |
TR19
rw |
TR18
rw |
TR17
rw |
TR16
rw |
|||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TR15
rw |
TR14
rw |
TR13
rw |
TR12
rw |
TR11
rw |
TR10
rw |
TR9
rw |
TR8
rw |
TR7
rw |
TR6
rw |
TR5
rw |
TR4
rw |
TR3
rw |
TR2
rw |
TR1
rw |
TR0
rw |
Bit 0: Rising trigger event configuration of line 0.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 1: Rising trigger event configuration of line 1.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 2: Rising trigger event configuration of line 2.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 3: Rising trigger event configuration of line 3.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 4: Rising trigger event configuration of line 4.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 5: Rising trigger event configuration of line 5.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 6: Rising trigger event configuration of line 6.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 7: Rising trigger event configuration of line 7.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 8: Rising trigger event configuration of line 8.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 9: Rising trigger event configuration of line 9.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 10: Rising trigger event configuration of line 10.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 11: Rising trigger event configuration of line 11.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 12: Rising trigger event configuration of line 12.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 13: Rising trigger event configuration of line 13.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 14: Rising trigger event configuration of line 14.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 15: Rising trigger event configuration of line 15.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 16: Rising trigger event configuration of line 16.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 17: Rising trigger event configuration of line 17.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 18: Rising trigger event configuration of line 18.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 19: Rising trigger event configuration of line 19.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 20: Rising trigger event configuration of line 20.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 21: Rising trigger event configuration of line 21.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 22: Rising trigger event configuration of line 22.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Falling Trigger selection register (EXTI_FTSR)
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
23/23 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TR22
rw |
TR21
rw |
TR20
rw |
TR19
rw |
TR18
rw |
TR17
rw |
TR16
rw |
|||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TR15
rw |
TR14
rw |
TR13
rw |
TR12
rw |
TR11
rw |
TR10
rw |
TR9
rw |
TR8
rw |
TR7
rw |
TR6
rw |
TR5
rw |
TR4
rw |
TR3
rw |
TR2
rw |
TR1
rw |
TR0
rw |
Bit 0: Falling trigger event configuration of line 0.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 1: Falling trigger event configuration of line 1.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 2: Falling trigger event configuration of line 2.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 3: Falling trigger event configuration of line 3.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 4: Falling trigger event configuration of line 4.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 5: Falling trigger event configuration of line 5.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 6: Falling trigger event configuration of line 6.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 7: Falling trigger event configuration of line 7.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 8: Falling trigger event configuration of line 8.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 9: Falling trigger event configuration of line 9.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 10: Falling trigger event configuration of line 10.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 11: Falling trigger event configuration of line 11.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 12: Falling trigger event configuration of line 12.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 13: Falling trigger event configuration of line 13.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 14: Falling trigger event configuration of line 14.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 15: Falling trigger event configuration of line 15.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 16: Falling trigger event configuration of line 16.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 17: Falling trigger event configuration of line 17.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 18: Rising trigger event configuration of line 18.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 19: Rising trigger event configuration of line 19.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 20: Rising trigger event configuration of line 20.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 21: Rising trigger event configuration of line 21.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 22: Rising trigger event configuration of line 22.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Software interrupt event register (EXTI_SWIER)
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
23/23 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SWIER22
rw |
SWIER21
rw |
SWIER20
rw |
SWIER19
rw |
SWIER18
rw |
SWIER17
rw |
SWIER16
rw |
|||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SWIER15
rw |
SWIER14
rw |
SWIER13
rw |
SWIER12
rw |
SWIER11
rw |
SWIER10
rw |
SWIER9
rw |
SWIER8
rw |
SWIER7
rw |
SWIER6
rw |
SWIER5
rw |
SWIER4
rw |
SWIER3
rw |
SWIER2
rw |
SWIER1
rw |
SWIER0
rw |
Bit 0: Software Interrupt on line 0.
Allowed values:
1: Pend: Generates an interrupt request
Bit 1: Software Interrupt on line 1.
Allowed values:
1: Pend: Generates an interrupt request
Bit 2: Software Interrupt on line 2.
Allowed values:
1: Pend: Generates an interrupt request
Bit 3: Software Interrupt on line 3.
Allowed values:
1: Pend: Generates an interrupt request
Bit 4: Software Interrupt on line 4.
Allowed values:
1: Pend: Generates an interrupt request
Bit 5: Software Interrupt on line 5.
Allowed values:
1: Pend: Generates an interrupt request
Bit 6: Software Interrupt on line 6.
Allowed values:
1: Pend: Generates an interrupt request
Bit 7: Software Interrupt on line 7.
Allowed values:
1: Pend: Generates an interrupt request
Bit 8: Software Interrupt on line 8.
Allowed values:
1: Pend: Generates an interrupt request
Bit 9: Software Interrupt on line 9.
Allowed values:
1: Pend: Generates an interrupt request
Bit 10: Software Interrupt on line 10.
Allowed values:
1: Pend: Generates an interrupt request
Bit 11: Software Interrupt on line 11.
Allowed values:
1: Pend: Generates an interrupt request
Bit 12: Software Interrupt on line 12.
Allowed values:
1: Pend: Generates an interrupt request
Bit 13: Software Interrupt on line 13.
Allowed values:
1: Pend: Generates an interrupt request
Bit 14: Software Interrupt on line 14.
Allowed values:
1: Pend: Generates an interrupt request
Bit 15: Software Interrupt on line 15.
Allowed values:
1: Pend: Generates an interrupt request
Bit 16: Software Interrupt on line 16.
Allowed values:
1: Pend: Generates an interrupt request
Bit 17: Software Interrupt on line 17.
Allowed values:
1: Pend: Generates an interrupt request
Bit 18: Software Interrupt on line 18.
Allowed values:
1: Pend: Generates an interrupt request
Bit 19: Software Interrupt on line 19.
Allowed values:
1: Pend: Generates an interrupt request
Bit 20: Software Interrupt on line 20.
Allowed values:
1: Pend: Generates an interrupt request
Bit 21: Software Interrupt on line 21.
Allowed values:
1: Pend: Generates an interrupt request
Bit 22: Software Interrupt on line 22.
Allowed values:
1: Pend: Generates an interrupt request
Pending register (EXTI_PR)
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
23/23 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PR22
rw |
PR21
rw |
PR20
rw |
PR19
rw |
PR18
rw |
PR17
rw |
PR16
rw |
|||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PR15
rw |
PR14
rw |
PR13
rw |
PR12
rw |
PR11
rw |
PR10
rw |
PR9
rw |
PR8
rw |
PR7
rw |
PR6
rw |
PR5
rw |
PR4
rw |
PR3
rw |
PR2
rw |
PR1
rw |
PR0
rw |
Bit 0: Pending bit 0.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 1: Pending bit 1.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 2: Pending bit 2.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 3: Pending bit 3.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 4: Pending bit 4.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 5: Pending bit 5.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 6: Pending bit 6.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 7: Pending bit 7.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 8: Pending bit 8.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 9: Pending bit 9.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 10: Pending bit 10.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 11: Pending bit 11.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 12: Pending bit 12.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 13: Pending bit 13.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 14: Pending bit 14.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 15: Pending bit 15.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 16: Pending bit 16.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 17: Pending bit 17.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 18: Pending bit 18.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 19: Pending bit 19.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 20: Pending bit 20.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 21: Pending bit 21.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 22: Pending bit 22.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
0x40022000: Flash
33/33 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | ACR | ||||||||||||||||||||||||||||||||
| 0x4 | KEYR | ||||||||||||||||||||||||||||||||
| 0x8 | OPTKEYR | ||||||||||||||||||||||||||||||||
| 0xc | SR | ||||||||||||||||||||||||||||||||
| 0x10 | CR | ||||||||||||||||||||||||||||||||
| 0x14 | AR | ||||||||||||||||||||||||||||||||
| 0x1c | OBR | ||||||||||||||||||||||||||||||||
| 0x20 | WRPR | ||||||||||||||||||||||||||||||||
Flash access control register
Offset: 0x0, size: 32, reset: 0x00000030, access: Unspecified
3/3 fields covered.
Bits 0-2: LATENCY.
Allowed values:
0: WS0: 0 wait states, if 0 < HCLK <= 24 MHz
1: WS1: 1 wait state, if 24 < HCLK <= 48 MHz
2: WS2: 2 wait states, if 48 < HCLK <= 72 MHz
Bit 4: PRFTBE.
Allowed values:
0: Disabled: Prefetch is disabled
1: Enabled: Prefetch is enabled
Bit 5: PRFTBS.
Allowed values:
0: Disabled: Prefetch buffer is disabled
1: Enabled: Prefetch buffer is enabled
Flash key register
Offset: 0x4, size: 32, reset: 0x00000000, access: write-only
1/1 fields covered.
Flash option key register
Offset: 0x8, size: 32, reset: 0x00000000, access: write-only
1/1 fields covered.
Flash status register
Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified
4/4 fields covered.
Bit 0: Busy.
Allowed values:
0: Inactive: No write/erase operation is in progress
1: Active: No write/erase operation is in progress
Bit 2: Programming error.
Allowed values:
0: NoError: No programming error occurred
1: Error: A programming error occurred
Bit 4: Write protection error.
Allowed values:
0: NoError: No write protection error occurred
1: Error: A write protection error occurred
Bit 5: End of operation.
Allowed values:
0: NoEvent: No EOP event occurred
1: Event: An EOP event occurred
Flash control register
Offset: 0x10, size: 32, reset: 0x00000080, access: read-write
11/11 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OBL_LAUNCH
rw |
EOPIE
rw |
ERRIE
rw |
OPTWRE
rw |
LOCK
rw |
STRT
rw |
OPTER
rw |
OPTPG
rw |
MER
rw |
PER
rw |
PG
rw |
|||||
Bit 0: Programming.
Allowed values:
1: Program: Flash programming activated
Bit 1: Page erase.
Allowed values:
1: PageErase: Erase activated for selected page
Bit 2: Mass erase.
Allowed values:
1: MassErase: Erase activated for all user sectors
Bit 4: Option byte programming.
Allowed values:
1: OptionByteProgramming: Program option byte activated
Bit 5: Option byte erase.
Allowed values:
1: OptionByteErase: Erase option byte activated
Bit 6: Start.
Allowed values:
1: Start: Trigger an erase operation
Bit 7: Lock.
Allowed values:
0: Unlocked: FLASH_CR register is unlocked
1: Locked: FLASH_CR register is locked
Bit 9: Option bytes write enable.
Allowed values:
0: Disabled: Option byte write enabled
1: Enabled: Option byte write disabled
Bit 10: Error interrupt enable.
Allowed values:
0: Disabled: Error interrupt generation disabled
1: Enabled: Error interrupt generation enabled
Bit 12: End of operation interrupt enable.
Allowed values:
0: Disabled: End of operation interrupt disabled
1: Enabled: End of operation interrupt enabled
Bit 13: Force option byte loading.
Allowed values:
0: Inactive: Force option byte loading inactive
1: Active: Force option byte loading active
Flash address register
Offset: 0x14, size: 32, reset: 0x00000000, access: write-only
1/1 fields covered.
Option byte register
Offset: 0x1c, size: 32, reset: 0xFFFFFF0F, access: read-only
11/11 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
Data1
r |
Data0
r |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SDADC12_VDD_MONITOR
r |
SRAM_PARITY_CHECK
r |
VDDA_MONITOR
r |
nBOOT1
r |
nRST_STDBY
r |
nRST_STOP
r |
WDG_SW
r |
RDPRT
r |
OPTERR
r |
|||||||
Bit 0: Option byte error.
Allowed values:
1: OptionByteError: The loaded option byte and its complement do not match
Bits 1-2: Read protection Level status.
Allowed values:
0: Level0: Level 0
1: Level1: Level 1
3: Level2: Level 2
Bit 8: WDG_SW.
Allowed values:
0: Hardware: Hardware watchdog
1: Software: Software watchdog
Bit 9: nRST_STOP.
Allowed values:
0: Reset: Reset generated when entering Stop mode
1: NoReset: No reset generated
Bit 10: nRST_STDBY.
Allowed values:
0: Reset: Reset generated when entering Standby mode
1: NoReset: No reset generated
Bit 12: BOOT1.
Allowed values:
0: Disabled: Together with BOOT0, select the device boot mode
1: Enabled: Together with BOOT0, select the device boot mode
Bit 13: VDDA_MONITOR.
Allowed values:
0: Disabled: VDDA power supply supervisor disabled
1: Enabled: VDDA power supply supervisor enabled
Bit 14: SRAM_PARITY_CHECK.
Allowed values:
0: Disabled: RAM parity check disabled
1: Enabled: RAM parity check enabled
Bit 15: SDADC12_VDD_MONITOR.
Allowed values:
0: Disabled: VDDSD12 monitoring disabled
1: Enabled: VDDSD12 monitoring enabled
Bits 16-23: Data0.
Allowed values: 0x0-0xff
Bits 24-31: Data1.
Allowed values: 0x0-0xff
0xe000ef34: Floting point unit
0/24 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | FPCCR | ||||||||||||||||||||||||||||||||
| 0x4 | FPCAR | ||||||||||||||||||||||||||||||||
| 0x8 | FPSCR | ||||||||||||||||||||||||||||||||
Floating-point context control register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
0/9 fields covered.
Floating-point context address register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Floating-point status control register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
0/14 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
N
rw |
Z
rw |
C
rw |
V
rw |
AHP
rw |
DN
rw |
FZ
rw |
RMode
rw |
||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IDC
rw |
IXC
rw |
UFC
rw |
OFC
rw |
DZC
rw |
IOC
rw |
||||||||||
Bit 0: Invalid operation cumulative exception bit.
Bit 1: Division by zero cumulative exception bit..
Bit 2: Overflow cumulative exception bit.
Bit 3: Underflow cumulative exception bit.
Bit 4: Inexact cumulative exception bit.
Bit 7: Input denormal cumulative exception bit..
Bits 22-23: Rounding Mode control field.
Bit 24: Flush-to-zero mode control bit:.
Bit 25: Default NaN mode control bit.
Bit 26: Alternative half-precision control bit.
Bit 28: Overflow condition code flag.
Bit 29: Carry condition code flag.
Bit 30: Zero condition code flag.
Bit 31: Negative condition code flag.
0xe000ed88: Floating point unit CPACR
0/1 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CPACR | ||||||||||||||||||||||||||||||||
Coprocessor access control register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0x48000000: General-purpose I/Os
177/177 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | MODER | ||||||||||||||||||||||||||||||||
| 0x4 | OTYPER | ||||||||||||||||||||||||||||||||
| 0x8 | OSPEEDR | ||||||||||||||||||||||||||||||||
| 0xc | PUPDR | ||||||||||||||||||||||||||||||||
| 0x10 | IDR | ||||||||||||||||||||||||||||||||
| 0x14 | ODR | ||||||||||||||||||||||||||||||||
| 0x18 | BSRR | ||||||||||||||||||||||||||||||||
| 0x1c | LCKR | ||||||||||||||||||||||||||||||||
| 0x20 | AFRL | ||||||||||||||||||||||||||||||||
| 0x24 | AFRH | ||||||||||||||||||||||||||||||||
| 0x28 | BRR | ||||||||||||||||||||||||||||||||
GPIO port mode register
Offset: 0x0, size: 32, reset: 0xA8000000, access: read-write
16/16 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MODER[15]
rw |
MODER[14]
rw |
MODER[13]
rw |
MODER[12]
rw |
MODER[11]
rw |
MODER[10]
rw |
MODER[9]
rw |
MODER[8]
rw |
||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MODER[7]
rw |
MODER[6]
rw |
MODER[5]
rw |
MODER[4]
rw |
MODER[3]
rw |
MODER[2]
rw |
MODER[1]
rw |
MODER[0]
rw |
||||||||
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
GPIO port output type register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OT[15]
rw |
OT[14]
rw |
OT[13]
rw |
OT[12]
rw |
OT[11]
rw |
OT[10]
rw |
OT[9]
rw |
OT[8]
rw |
OT[7]
rw |
OT[6]
rw |
OT[5]
rw |
OT[4]
rw |
OT[3]
rw |
OT[2]
rw |
OT[1]
rw |
OT[0]
rw |
Bit 0: Port x configuration pin 0.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 1: Port x configuration pin 1.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 2: Port x configuration pin 2.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 3: Port x configuration pin 3.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 4: Port x configuration pin 4.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 5: Port x configuration pin 5.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 6: Port x configuration pin 6.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 7: Port x configuration pin 7.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 8: Port x configuration pin 8.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 9: Port x configuration pin 9.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 10: Port x configuration pin 10.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 11: Port x configuration pin 11.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 12: Port x configuration pin 12.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 13: Port x configuration pin 13.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 14: Port x configuration pin 14.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 15: Port x configuration pin 15.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
GPIO port output speed register
Offset: 0x8, size: 32, reset: 0x0C000000, access: read-write
16/16 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OSPEEDR[15]
rw |
OSPEEDR[14]
rw |
OSPEEDR[13]
rw |
OSPEEDR[12]
rw |
OSPEEDR[11]
rw |
OSPEEDR[10]
rw |
OSPEEDR[9]
rw |
OSPEEDR[8]
rw |
||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OSPEEDR[7]
rw |
OSPEEDR[6]
rw |
OSPEEDR[5]
rw |
OSPEEDR[4]
rw |
OSPEEDR[3]
rw |
OSPEEDR[2]
rw |
OSPEEDR[1]
rw |
OSPEEDR[0]
rw |
||||||||
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
GPIO port pull-up/pull-down register
Offset: 0xc, size: 32, reset: 0x64000000, access: read-write
16/16 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PUPDR[15]
rw |
PUPDR[14]
rw |
PUPDR[13]
rw |
PUPDR[12]
rw |
PUPDR[11]
rw |
PUPDR[10]
rw |
PUPDR[9]
rw |
PUPDR[8]
rw |
||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PUPDR[7]
rw |
PUPDR[6]
rw |
PUPDR[5]
rw |
PUPDR[4]
rw |
PUPDR[3]
rw |
PUPDR[2]
rw |
PUPDR[1]
rw |
PUPDR[0]
rw |
||||||||
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
GPIO port input data register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-only
16/16 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IDR[15]
r |
IDR[14]
r |
IDR[13]
r |
IDR[12]
r |
IDR[11]
r |
IDR[10]
r |
IDR[9]
r |
IDR[8]
r |
IDR[7]
r |
IDR[6]
r |
IDR[5]
r |
IDR[4]
r |
IDR[3]
r |
IDR[2]
r |
IDR[1]
r |
IDR[0]
r |
Bit 0: Port input data pin 0.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 1: Port input data pin 1.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 2: Port input data pin 2.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 3: Port input data pin 3.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 4: Port input data pin 4.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 5: Port input data pin 5.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 6: Port input data pin 6.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 7: Port input data pin 7.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 8: Port input data pin 8.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 9: Port input data pin 9.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 10: Port input data pin 10.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 11: Port input data pin 11.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 12: Port input data pin 12.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 13: Port input data pin 13.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 14: Port input data pin 14.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 15: Port input data pin 15.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
GPIO port output data register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ODR[15]
rw |
ODR[14]
rw |
ODR[13]
rw |
ODR[12]
rw |
ODR[11]
rw |
ODR[10]
rw |
ODR[9]
rw |
ODR[8]
rw |
ODR[7]
rw |
ODR[6]
rw |
ODR[5]
rw |
ODR[4]
rw |
ODR[3]
rw |
ODR[2]
rw |
ODR[1]
rw |
ODR[0]
rw |
Bit 0: Port output data pin 0.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 1: Port output data pin 1.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 2: Port output data pin 2.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 3: Port output data pin 3.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 4: Port output data pin 4.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 5: Port output data pin 5.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 6: Port output data pin 6.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 7: Port output data pin 7.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 8: Port output data pin 8.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 9: Port output data pin 9.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 10: Port output data pin 10.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 11: Port output data pin 11.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 12: Port output data pin 12.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 13: Port output data pin 13.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 14: Port output data pin 14.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 15: Port output data pin 15.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
GPIO port bit set/reset register
Offset: 0x18, size: 32, reset: 0x00000000, access: write-only
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BS[15]
w |
BS[14]
w |
BS[13]
w |
BS[12]
w |
BS[11]
w |
BS[10]
w |
BS[9]
w |
BS[8]
w |
BS[7]
w |
BS[6]
w |
BS[5]
w |
BS[4]
w |
BS[3]
w |
BS[2]
w |
BS[1]
w |
BS[0]
w |
Bit 0: Port x set pin 0.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 1: Port x set pin 1.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 2: Port x set pin 2.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 3: Port x set pin 3.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 4: Port x set pin 4.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 5: Port x set pin 5.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 6: Port x set pin 6.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 7: Port x set pin 7.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 8: Port x set pin 8.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 9: Port x set pin 9.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 10: Port x set pin 10.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 11: Port x set pin 11.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 12: Port x set pin 12.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 13: Port x set pin 13.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 14: Port x set pin 14.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 15: Port x set pin 15.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 16: Port x reset pin 0.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 17: Port x reset pin 1.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 18: Port x reset pin 2.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 19: Port x reset pin 3.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 20: Port x reset pin 4.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 21: Port x reset pin 5.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 22: Port x reset pin 6.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 23: Port x reset pin 7.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 24: Port x reset pin 8.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 25: Port x reset pin 9.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 26: Port x reset pin 10.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 27: Port x reset pin 11.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 28: Port x reset pin 12.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 29: Port x reset pin 13.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 30: Port x reset pin 14.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 31: Port x reset pin 15.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
GPIO port configuration lock register
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
17/17 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
LCKK
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
LCK[15]
rw |
LCK[14]
rw |
LCK[13]
rw |
LCK[12]
rw |
LCK[11]
rw |
LCK[10]
rw |
LCK[9]
rw |
LCK[8]
rw |
LCK[7]
rw |
LCK[6]
rw |
LCK[5]
rw |
LCK[4]
rw |
LCK[3]
rw |
LCK[2]
rw |
LCK[1]
rw |
LCK[0]
rw |
Bit 0: Port x lock pin 0.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 1: Port x lock pin 1.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 2: Port x lock pin 2.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 3: Port x lock pin 3.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 4: Port x lock pin 4.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 5: Port x lock pin 5.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 6: Port x lock pin 6.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 7: Port x lock pin 7.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 8: Port x lock pin 8.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 9: Port x lock pin 9.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 10: Port x lock pin 10.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 11: Port x lock pin 11.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 12: Port x lock pin 12.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 13: Port x lock pin 13.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 14: Port x lock pin 14.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 15: Port x lock pin 15.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 16: Lok Key.
Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active
GPIO alternate function low register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
AFR[L7]
rw |
AFR[L6]
rw |
AFR[L5]
rw |
AFR[L4]
rw |
||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
AFR[L3]
rw |
AFR[L2]
rw |
AFR[L1]
rw |
AFR[L0]
rw |
||||||||||||
Bits 0-3: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 4-7: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 8-11: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 12-15: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 16-19: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 20-23: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 24-27: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 28-31: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
GPIO alternate function high register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
AFR[H15]
rw |
AFR[H14]
rw |
AFR[H13]
rw |
AFR[H12]
rw |
||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
AFR[H11]
rw |
AFR[H10]
rw |
AFR[H9]
rw |
AFR[H8]
rw |
||||||||||||
Bits 0-3: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 4-7: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 8-11: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 12-15: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 16-19: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 20-23: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 24-27: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 28-31: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Port bit reset register
Offset: 0x28, size: 32, reset: 0x00000000, access: write-only
16/16 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
Bit 0: Port x reset pin 0.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 1: Port x reset pin 1.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 2: Port x reset pin 2.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 3: Port x reset pin 3.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 4: Port x reset pin 4.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 5: Port x reset pin 5.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 6: Port x reset pin 6.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 7: Port x reset pin 7.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 8: Port x reset pin 8.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 9: Port x reset pin 9.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 10: Port x reset pin 10.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 11: Port x reset pin 11.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 12: Port x reset pin 12.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 13: Port x reset pin 13.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 14: Port x reset pin 14.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 15: Port x reset pin 15.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
0x48000400: General-purpose I/Os
177/177 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | MODER | ||||||||||||||||||||||||||||||||
| 0x4 | OTYPER | ||||||||||||||||||||||||||||||||
| 0x8 | OSPEEDR | ||||||||||||||||||||||||||||||||
| 0xc | PUPDR | ||||||||||||||||||||||||||||||||
| 0x10 | IDR | ||||||||||||||||||||||||||||||||
| 0x14 | ODR | ||||||||||||||||||||||||||||||||
| 0x18 | BSRR | ||||||||||||||||||||||||||||||||
| 0x1c | LCKR | ||||||||||||||||||||||||||||||||
| 0x20 | AFRL | ||||||||||||||||||||||||||||||||
| 0x24 | AFRH | ||||||||||||||||||||||||||||||||
| 0x28 | BRR | ||||||||||||||||||||||||||||||||
GPIO port mode register
Offset: 0x0, size: 32, reset: 0x00000280, access: read-write
16/16 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MODER[15]
rw |
MODER[14]
rw |
MODER[13]
rw |
MODER[12]
rw |
MODER[11]
rw |
MODER[10]
rw |
MODER[9]
rw |
MODER[8]
rw |
||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MODER[7]
rw |
MODER[6]
rw |
MODER[5]
rw |
MODER[4]
rw |
MODER[3]
rw |
MODER[2]
rw |
MODER[1]
rw |
MODER[0]
rw |
||||||||
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
GPIO port output type register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OT[15]
rw |
OT[14]
rw |
OT[13]
rw |
OT[12]
rw |
OT[11]
rw |
OT[10]
rw |
OT[9]
rw |
OT[8]
rw |
OT[7]
rw |
OT[6]
rw |
OT[5]
rw |
OT[4]
rw |
OT[3]
rw |
OT[2]
rw |
OT[1]
rw |
OT[0]
rw |
Bit 0: Port x configuration pin 0.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 1: Port x configuration pin 1.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 2: Port x configuration pin 2.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 3: Port x configuration pin 3.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 4: Port x configuration pin 4.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 5: Port x configuration pin 5.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 6: Port x configuration pin 6.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 7: Port x configuration pin 7.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 8: Port x configuration pin 8.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 9: Port x configuration pin 9.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 10: Port x configuration pin 10.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 11: Port x configuration pin 11.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 12: Port x configuration pin 12.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 13: Port x configuration pin 13.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 14: Port x configuration pin 14.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 15: Port x configuration pin 15.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
GPIO port output speed register
Offset: 0x8, size: 32, reset: 0x000000C0, access: read-write
16/16 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OSPEEDR[15]
rw |
OSPEEDR[14]
rw |
OSPEEDR[13]
rw |
OSPEEDR[12]
rw |
OSPEEDR[11]
rw |
OSPEEDR[10]
rw |
OSPEEDR[9]
rw |
OSPEEDR[8]
rw |
||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OSPEEDR[7]
rw |
OSPEEDR[6]
rw |
OSPEEDR[5]
rw |
OSPEEDR[4]
rw |
OSPEEDR[3]
rw |
OSPEEDR[2]
rw |
OSPEEDR[1]
rw |
OSPEEDR[0]
rw |
||||||||
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
GPIO port pull-up/pull-down register
Offset: 0xc, size: 32, reset: 0x00000100, access: read-write
16/16 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PUPDR[15]
rw |
PUPDR[14]
rw |
PUPDR[13]
rw |
PUPDR[12]
rw |
PUPDR[11]
rw |
PUPDR[10]
rw |
PUPDR[9]
rw |
PUPDR[8]
rw |
||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PUPDR[7]
rw |
PUPDR[6]
rw |
PUPDR[5]
rw |
PUPDR[4]
rw |
PUPDR[3]
rw |
PUPDR[2]
rw |
PUPDR[1]
rw |
PUPDR[0]
rw |
||||||||
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
GPIO port input data register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-only
16/16 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IDR[15]
r |
IDR[14]
r |
IDR[13]
r |
IDR[12]
r |
IDR[11]
r |
IDR[10]
r |
IDR[9]
r |
IDR[8]
r |
IDR[7]
r |
IDR[6]
r |
IDR[5]
r |
IDR[4]
r |
IDR[3]
r |
IDR[2]
r |
IDR[1]
r |
IDR[0]
r |
Bit 0: Port input data pin 0.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 1: Port input data pin 1.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 2: Port input data pin 2.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 3: Port input data pin 3.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 4: Port input data pin 4.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 5: Port input data pin 5.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 6: Port input data pin 6.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 7: Port input data pin 7.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 8: Port input data pin 8.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 9: Port input data pin 9.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 10: Port input data pin 10.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 11: Port input data pin 11.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 12: Port input data pin 12.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 13: Port input data pin 13.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 14: Port input data pin 14.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 15: Port input data pin 15.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
GPIO port output data register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ODR[15]
rw |
ODR[14]
rw |
ODR[13]
rw |
ODR[12]
rw |
ODR[11]
rw |
ODR[10]
rw |
ODR[9]
rw |
ODR[8]
rw |
ODR[7]
rw |
ODR[6]
rw |
ODR[5]
rw |
ODR[4]
rw |
ODR[3]
rw |
ODR[2]
rw |
ODR[1]
rw |
ODR[0]
rw |
Bit 0: Port output data pin 0.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 1: Port output data pin 1.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 2: Port output data pin 2.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 3: Port output data pin 3.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 4: Port output data pin 4.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 5: Port output data pin 5.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 6: Port output data pin 6.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 7: Port output data pin 7.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 8: Port output data pin 8.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 9: Port output data pin 9.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 10: Port output data pin 10.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 11: Port output data pin 11.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 12: Port output data pin 12.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 13: Port output data pin 13.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 14: Port output data pin 14.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 15: Port output data pin 15.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
GPIO port bit set/reset register
Offset: 0x18, size: 32, reset: 0x00000000, access: write-only
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BS[15]
w |
BS[14]
w |
BS[13]
w |
BS[12]
w |
BS[11]
w |
BS[10]
w |
BS[9]
w |
BS[8]
w |
BS[7]
w |
BS[6]
w |
BS[5]
w |
BS[4]
w |
BS[3]
w |
BS[2]
w |
BS[1]
w |
BS[0]
w |
Bit 0: Port x set pin 0.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 1: Port x set pin 1.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 2: Port x set pin 2.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 3: Port x set pin 3.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 4: Port x set pin 4.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 5: Port x set pin 5.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 6: Port x set pin 6.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 7: Port x set pin 7.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 8: Port x set pin 8.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 9: Port x set pin 9.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 10: Port x set pin 10.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 11: Port x set pin 11.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 12: Port x set pin 12.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 13: Port x set pin 13.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 14: Port x set pin 14.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 15: Port x set pin 15.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 16: Port x reset pin 0.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 17: Port x reset pin 1.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 18: Port x reset pin 2.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 19: Port x reset pin 3.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 20: Port x reset pin 4.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 21: Port x reset pin 5.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 22: Port x reset pin 6.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 23: Port x reset pin 7.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 24: Port x reset pin 8.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 25: Port x reset pin 9.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 26: Port x reset pin 10.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 27: Port x reset pin 11.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 28: Port x reset pin 12.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 29: Port x reset pin 13.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 30: Port x reset pin 14.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 31: Port x reset pin 15.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
GPIO port configuration lock register
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
17/17 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
LCKK
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
LCK[15]
rw |
LCK[14]
rw |
LCK[13]
rw |
LCK[12]
rw |
LCK[11]
rw |
LCK[10]
rw |
LCK[9]
rw |
LCK[8]
rw |
LCK[7]
rw |
LCK[6]
rw |
LCK[5]
rw |
LCK[4]
rw |
LCK[3]
rw |
LCK[2]
rw |
LCK[1]
rw |
LCK[0]
rw |
Bit 0: Port x lock pin 0.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 1: Port x lock pin 1.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 2: Port x lock pin 2.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 3: Port x lock pin 3.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 4: Port x lock pin 4.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 5: Port x lock pin 5.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 6: Port x lock pin 6.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 7: Port x lock pin 7.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 8: Port x lock pin 8.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 9: Port x lock pin 9.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 10: Port x lock pin 10.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 11: Port x lock pin 11.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 12: Port x lock pin 12.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 13: Port x lock pin 13.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 14: Port x lock pin 14.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 15: Port x lock pin 15.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 16: Lok Key.
Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active
GPIO alternate function low register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
AFR[L7]
rw |
AFR[L6]
rw |
AFR[L5]
rw |
AFR[L4]
rw |
||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
AFR[L3]
rw |
AFR[L2]
rw |
AFR[L1]
rw |
AFR[L0]
rw |
||||||||||||
Bits 0-3: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 4-7: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 8-11: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 12-15: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 16-19: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 20-23: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 24-27: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 28-31: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
GPIO alternate function high register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
AFR[H15]
rw |
AFR[H14]
rw |
AFR[H13]
rw |
AFR[H12]
rw |
||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
AFR[H11]
rw |
AFR[H10]
rw |
AFR[H9]
rw |
AFR[H8]
rw |
||||||||||||
Bits 0-3: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 4-7: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 8-11: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 12-15: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 16-19: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 20-23: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 24-27: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 28-31: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Port bit reset register
Offset: 0x28, size: 32, reset: 0x00000000, access: write-only
16/16 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
Bit 0: Port x reset pin 0.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 1: Port x reset pin 1.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 2: Port x reset pin 2.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 3: Port x reset pin 3.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 4: Port x reset pin 4.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 5: Port x reset pin 5.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 6: Port x reset pin 6.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 7: Port x reset pin 7.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 8: Port x reset pin 8.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 9: Port x reset pin 9.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 10: Port x reset pin 10.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 11: Port x reset pin 11.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 12: Port x reset pin 12.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 13: Port x reset pin 13.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 14: Port x reset pin 14.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 15: Port x reset pin 15.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
0x48000800: General-purpose I/Os
160/160 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | MODER | ||||||||||||||||||||||||||||||||
| 0x4 | OTYPER | ||||||||||||||||||||||||||||||||
| 0x8 | OSPEEDR | ||||||||||||||||||||||||||||||||
| 0xc | PUPDR | ||||||||||||||||||||||||||||||||
| 0x10 | IDR | ||||||||||||||||||||||||||||||||
| 0x14 | ODR | ||||||||||||||||||||||||||||||||
| 0x18 | BSRR | ||||||||||||||||||||||||||||||||
| 0x20 | AFRL | ||||||||||||||||||||||||||||||||
| 0x24 | AFRH | ||||||||||||||||||||||||||||||||
| 0x28 | BRR | ||||||||||||||||||||||||||||||||
GPIO port mode register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MODER[15]
rw |
MODER[14]
rw |
MODER[13]
rw |
MODER[12]
rw |
MODER[11]
rw |
MODER[10]
rw |
MODER[9]
rw |
MODER[8]
rw |
||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MODER[7]
rw |
MODER[6]
rw |
MODER[5]
rw |
MODER[4]
rw |
MODER[3]
rw |
MODER[2]
rw |
MODER[1]
rw |
MODER[0]
rw |
||||||||
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
GPIO port output type register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OT[15]
rw |
OT[14]
rw |
OT[13]
rw |
OT[12]
rw |
OT[11]
rw |
OT[10]
rw |
OT[9]
rw |
OT[8]
rw |
OT[7]
rw |
OT[6]
rw |
OT[5]
rw |
OT[4]
rw |
OT[3]
rw |
OT[2]
rw |
OT[1]
rw |
OT[0]
rw |
Bit 0: Port x configuration pin 0.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 1: Port x configuration pin 1.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 2: Port x configuration pin 2.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 3: Port x configuration pin 3.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 4: Port x configuration pin 4.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 5: Port x configuration pin 5.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 6: Port x configuration pin 6.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 7: Port x configuration pin 7.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 8: Port x configuration pin 8.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 9: Port x configuration pin 9.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 10: Port x configuration pin 10.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 11: Port x configuration pin 11.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 12: Port x configuration pin 12.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 13: Port x configuration pin 13.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 14: Port x configuration pin 14.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 15: Port x configuration pin 15.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
GPIO port output speed register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OSPEEDR[15]
rw |
OSPEEDR[14]
rw |
OSPEEDR[13]
rw |
OSPEEDR[12]
rw |
OSPEEDR[11]
rw |
OSPEEDR[10]
rw |
OSPEEDR[9]
rw |
OSPEEDR[8]
rw |
||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OSPEEDR[7]
rw |
OSPEEDR[6]
rw |
OSPEEDR[5]
rw |
OSPEEDR[4]
rw |
OSPEEDR[3]
rw |
OSPEEDR[2]
rw |
OSPEEDR[1]
rw |
OSPEEDR[0]
rw |
||||||||
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
GPIO port pull-up/pull-down register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PUPDR[15]
rw |
PUPDR[14]
rw |
PUPDR[13]
rw |
PUPDR[12]
rw |
PUPDR[11]
rw |
PUPDR[10]
rw |
PUPDR[9]
rw |
PUPDR[8]
rw |
||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PUPDR[7]
rw |
PUPDR[6]
rw |
PUPDR[5]
rw |
PUPDR[4]
rw |
PUPDR[3]
rw |
PUPDR[2]
rw |
PUPDR[1]
rw |
PUPDR[0]
rw |
||||||||
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
GPIO port input data register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-only
16/16 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IDR[15]
r |
IDR[14]
r |
IDR[13]
r |
IDR[12]
r |
IDR[11]
r |
IDR[10]
r |
IDR[9]
r |
IDR[8]
r |
IDR[7]
r |
IDR[6]
r |
IDR[5]
r |
IDR[4]
r |
IDR[3]
r |
IDR[2]
r |
IDR[1]
r |
IDR[0]
r |
Bit 0: Port input data pin 0.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 1: Port input data pin 1.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 2: Port input data pin 2.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 3: Port input data pin 3.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 4: Port input data pin 4.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 5: Port input data pin 5.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 6: Port input data pin 6.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 7: Port input data pin 7.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 8: Port input data pin 8.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 9: Port input data pin 9.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 10: Port input data pin 10.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 11: Port input data pin 11.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 12: Port input data pin 12.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 13: Port input data pin 13.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 14: Port input data pin 14.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 15: Port input data pin 15.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
GPIO port output data register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ODR[15]
rw |
ODR[14]
rw |
ODR[13]
rw |
ODR[12]
rw |
ODR[11]
rw |
ODR[10]
rw |
ODR[9]
rw |
ODR[8]
rw |
ODR[7]
rw |
ODR[6]
rw |
ODR[5]
rw |
ODR[4]
rw |
ODR[3]
rw |
ODR[2]
rw |
ODR[1]
rw |
ODR[0]
rw |
Bit 0: Port output data pin 0.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 1: Port output data pin 1.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 2: Port output data pin 2.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 3: Port output data pin 3.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 4: Port output data pin 4.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 5: Port output data pin 5.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 6: Port output data pin 6.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 7: Port output data pin 7.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 8: Port output data pin 8.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 9: Port output data pin 9.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 10: Port output data pin 10.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 11: Port output data pin 11.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 12: Port output data pin 12.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 13: Port output data pin 13.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 14: Port output data pin 14.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 15: Port output data pin 15.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
GPIO port bit set/reset register
Offset: 0x18, size: 32, reset: 0x00000000, access: write-only
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BS[15]
w |
BS[14]
w |
BS[13]
w |
BS[12]
w |
BS[11]
w |
BS[10]
w |
BS[9]
w |
BS[8]
w |
BS[7]
w |
BS[6]
w |
BS[5]
w |
BS[4]
w |
BS[3]
w |
BS[2]
w |
BS[1]
w |
BS[0]
w |
Bit 0: Port x set pin 0.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 1: Port x set pin 1.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 2: Port x set pin 2.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 3: Port x set pin 3.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 4: Port x set pin 4.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 5: Port x set pin 5.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 6: Port x set pin 6.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 7: Port x set pin 7.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 8: Port x set pin 8.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 9: Port x set pin 9.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 10: Port x set pin 10.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 11: Port x set pin 11.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 12: Port x set pin 12.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 13: Port x set pin 13.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 14: Port x set pin 14.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 15: Port x set pin 15.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 16: Port x reset pin 0.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 17: Port x reset pin 1.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 18: Port x reset pin 2.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 19: Port x reset pin 3.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 20: Port x reset pin 4.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 21: Port x reset pin 5.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 22: Port x reset pin 6.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 23: Port x reset pin 7.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 24: Port x reset pin 8.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 25: Port x reset pin 9.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 26: Port x reset pin 10.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 27: Port x reset pin 11.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 28: Port x reset pin 12.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 29: Port x reset pin 13.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 30: Port x reset pin 14.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 31: Port x reset pin 15.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
GPIO alternate function low register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
AFR[L7]
rw |
AFR[L6]
rw |
AFR[L5]
rw |
AFR[L4]
rw |
||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
AFR[L3]
rw |
AFR[L2]
rw |
AFR[L1]
rw |
AFR[L0]
rw |
||||||||||||
Bits 0-3: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 4-7: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 8-11: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 12-15: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 16-19: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 20-23: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 24-27: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 28-31: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
GPIO alternate function high register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
AFR[H15]
rw |
AFR[H14]
rw |
AFR[H13]
rw |
AFR[H12]
rw |
||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
AFR[H11]
rw |
AFR[H10]
rw |
AFR[H9]
rw |
AFR[H8]
rw |
||||||||||||
Bits 0-3: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 4-7: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 8-11: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 12-15: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 16-19: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 20-23: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 24-27: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 28-31: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Port bit reset register
Offset: 0x28, size: 32, reset: 0x00000000, access: write-only
16/16 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
Bit 0: Port x reset pin 0.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 1: Port x reset pin 1.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 2: Port x reset pin 2.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 3: Port x reset pin 3.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 4: Port x reset pin 4.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 5: Port x reset pin 5.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 6: Port x reset pin 6.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 7: Port x reset pin 7.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 8: Port x reset pin 8.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 9: Port x reset pin 9.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 10: Port x reset pin 10.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 11: Port x reset pin 11.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 12: Port x reset pin 12.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 13: Port x reset pin 13.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 14: Port x reset pin 14.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 15: Port x reset pin 15.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
0x48000c00: General-purpose I/Os
177/177 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | MODER | ||||||||||||||||||||||||||||||||
| 0x4 | OTYPER | ||||||||||||||||||||||||||||||||
| 0x8 | OSPEEDR | ||||||||||||||||||||||||||||||||
| 0xc | PUPDR | ||||||||||||||||||||||||||||||||
| 0x10 | IDR | ||||||||||||||||||||||||||||||||
| 0x14 | ODR | ||||||||||||||||||||||||||||||||
| 0x18 | BSRR | ||||||||||||||||||||||||||||||||
| 0x1c | LCKR | ||||||||||||||||||||||||||||||||
| 0x20 | AFRL | ||||||||||||||||||||||||||||||||
| 0x24 | AFRH | ||||||||||||||||||||||||||||||||
| 0x28 | BRR | ||||||||||||||||||||||||||||||||
GPIO port mode register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MODER[15]
rw |
MODER[14]
rw |
MODER[13]
rw |
MODER[12]
rw |
MODER[11]
rw |
MODER[10]
rw |
MODER[9]
rw |
MODER[8]
rw |
||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MODER[7]
rw |
MODER[6]
rw |
MODER[5]
rw |
MODER[4]
rw |
MODER[3]
rw |
MODER[2]
rw |
MODER[1]
rw |
MODER[0]
rw |
||||||||
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
GPIO port output type register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OT[15]
rw |
OT[14]
rw |
OT[13]
rw |
OT[12]
rw |
OT[11]
rw |
OT[10]
rw |
OT[9]
rw |
OT[8]
rw |
OT[7]
rw |
OT[6]
rw |
OT[5]
rw |
OT[4]
rw |
OT[3]
rw |
OT[2]
rw |
OT[1]
rw |
OT[0]
rw |
Bit 0: Port x configuration pin 0.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 1: Port x configuration pin 1.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 2: Port x configuration pin 2.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 3: Port x configuration pin 3.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 4: Port x configuration pin 4.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 5: Port x configuration pin 5.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 6: Port x configuration pin 6.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 7: Port x configuration pin 7.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 8: Port x configuration pin 8.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 9: Port x configuration pin 9.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 10: Port x configuration pin 10.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 11: Port x configuration pin 11.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 12: Port x configuration pin 12.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 13: Port x configuration pin 13.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 14: Port x configuration pin 14.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 15: Port x configuration pin 15.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
GPIO port output speed register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OSPEEDR[15]
rw |
OSPEEDR[14]
rw |
OSPEEDR[13]
rw |
OSPEEDR[12]
rw |
OSPEEDR[11]
rw |
OSPEEDR[10]
rw |
OSPEEDR[9]
rw |
OSPEEDR[8]
rw |
||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OSPEEDR[7]
rw |
OSPEEDR[6]
rw |
OSPEEDR[5]
rw |
OSPEEDR[4]
rw |
OSPEEDR[3]
rw |
OSPEEDR[2]
rw |
OSPEEDR[1]
rw |
OSPEEDR[0]
rw |
||||||||
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
GPIO port pull-up/pull-down register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PUPDR[15]
rw |
PUPDR[14]
rw |
PUPDR[13]
rw |
PUPDR[12]
rw |
PUPDR[11]
rw |
PUPDR[10]
rw |
PUPDR[9]
rw |
PUPDR[8]
rw |
||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PUPDR[7]
rw |
PUPDR[6]
rw |
PUPDR[5]
rw |
PUPDR[4]
rw |
PUPDR[3]
rw |
PUPDR[2]
rw |
PUPDR[1]
rw |
PUPDR[0]
rw |
||||||||
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
GPIO port input data register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-only
16/16 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IDR[15]
r |
IDR[14]
r |
IDR[13]
r |
IDR[12]
r |
IDR[11]
r |
IDR[10]
r |
IDR[9]
r |
IDR[8]
r |
IDR[7]
r |
IDR[6]
r |
IDR[5]
r |
IDR[4]
r |
IDR[3]
r |
IDR[2]
r |
IDR[1]
r |
IDR[0]
r |
Bit 0: Port input data pin 0.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 1: Port input data pin 1.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 2: Port input data pin 2.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 3: Port input data pin 3.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 4: Port input data pin 4.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 5: Port input data pin 5.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 6: Port input data pin 6.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 7: Port input data pin 7.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 8: Port input data pin 8.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 9: Port input data pin 9.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 10: Port input data pin 10.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 11: Port input data pin 11.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 12: Port input data pin 12.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 13: Port input data pin 13.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 14: Port input data pin 14.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 15: Port input data pin 15.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
GPIO port output data register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ODR[15]
rw |
ODR[14]
rw |
ODR[13]
rw |
ODR[12]
rw |
ODR[11]
rw |
ODR[10]
rw |
ODR[9]
rw |
ODR[8]
rw |
ODR[7]
rw |
ODR[6]
rw |
ODR[5]
rw |
ODR[4]
rw |
ODR[3]
rw |
ODR[2]
rw |
ODR[1]
rw |
ODR[0]
rw |
Bit 0: Port output data pin 0.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 1: Port output data pin 1.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 2: Port output data pin 2.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 3: Port output data pin 3.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 4: Port output data pin 4.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 5: Port output data pin 5.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 6: Port output data pin 6.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 7: Port output data pin 7.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 8: Port output data pin 8.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 9: Port output data pin 9.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 10: Port output data pin 10.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 11: Port output data pin 11.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 12: Port output data pin 12.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 13: Port output data pin 13.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 14: Port output data pin 14.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 15: Port output data pin 15.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
GPIO port bit set/reset register
Offset: 0x18, size: 32, reset: 0x00000000, access: write-only
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BS[15]
w |
BS[14]
w |
BS[13]
w |
BS[12]
w |
BS[11]
w |
BS[10]
w |
BS[9]
w |
BS[8]
w |
BS[7]
w |
BS[6]
w |
BS[5]
w |
BS[4]
w |
BS[3]
w |
BS[2]
w |
BS[1]
w |
BS[0]
w |
Bit 0: Port x set pin 0.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 1: Port x set pin 1.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 2: Port x set pin 2.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 3: Port x set pin 3.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 4: Port x set pin 4.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 5: Port x set pin 5.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 6: Port x set pin 6.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 7: Port x set pin 7.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 8: Port x set pin 8.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 9: Port x set pin 9.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 10: Port x set pin 10.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 11: Port x set pin 11.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 12: Port x set pin 12.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 13: Port x set pin 13.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 14: Port x set pin 14.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 15: Port x set pin 15.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 16: Port x reset pin 0.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 17: Port x reset pin 1.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 18: Port x reset pin 2.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 19: Port x reset pin 3.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 20: Port x reset pin 4.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 21: Port x reset pin 5.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 22: Port x reset pin 6.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 23: Port x reset pin 7.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 24: Port x reset pin 8.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 25: Port x reset pin 9.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 26: Port x reset pin 10.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 27: Port x reset pin 11.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 28: Port x reset pin 12.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 29: Port x reset pin 13.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 30: Port x reset pin 14.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 31: Port x reset pin 15.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
GPIO port configuration lock register
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
17/17 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
LCKK
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
LCK[15]
rw |
LCK[14]
rw |
LCK[13]
rw |
LCK[12]
rw |
LCK[11]
rw |
LCK[10]
rw |
LCK[9]
rw |
LCK[8]
rw |
LCK[7]
rw |
LCK[6]
rw |
LCK[5]
rw |
LCK[4]
rw |
LCK[3]
rw |
LCK[2]
rw |
LCK[1]
rw |
LCK[0]
rw |
Bit 0: Port x lock pin 0.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 1: Port x lock pin 1.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 2: Port x lock pin 2.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 3: Port x lock pin 3.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 4: Port x lock pin 4.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 5: Port x lock pin 5.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 6: Port x lock pin 6.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 7: Port x lock pin 7.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 8: Port x lock pin 8.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 9: Port x lock pin 9.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 10: Port x lock pin 10.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 11: Port x lock pin 11.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 12: Port x lock pin 12.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 13: Port x lock pin 13.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 14: Port x lock pin 14.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 15: Port x lock pin 15.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 16: Lok Key.
Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active
GPIO alternate function low register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
AFR[L7]
rw |
AFR[L6]
rw |
AFR[L5]
rw |
AFR[L4]
rw |
||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
AFR[L3]
rw |
AFR[L2]
rw |
AFR[L1]
rw |
AFR[L0]
rw |
||||||||||||
Bits 0-3: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 4-7: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 8-11: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 12-15: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 16-19: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 20-23: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 24-27: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 28-31: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
GPIO alternate function high register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
AFR[H15]
rw |
AFR[H14]
rw |
AFR[H13]
rw |
AFR[H12]
rw |
||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
AFR[H11]
rw |
AFR[H10]
rw |
AFR[H9]
rw |
AFR[H8]
rw |
||||||||||||
Bits 0-3: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 4-7: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 8-11: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 12-15: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 16-19: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 20-23: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 24-27: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 28-31: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Port bit reset register
Offset: 0x28, size: 32, reset: 0x00000000, access: write-only
16/16 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
Bit 0: Port x reset pin 0.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 1: Port x reset pin 1.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 2: Port x reset pin 2.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 3: Port x reset pin 3.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 4: Port x reset pin 4.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 5: Port x reset pin 5.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 6: Port x reset pin 6.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 7: Port x reset pin 7.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 8: Port x reset pin 8.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 9: Port x reset pin 9.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 10: Port x reset pin 10.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 11: Port x reset pin 11.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 12: Port x reset pin 12.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 13: Port x reset pin 13.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 14: Port x reset pin 14.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 15: Port x reset pin 15.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
0x48001000: General-purpose I/Os
160/160 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | MODER | ||||||||||||||||||||||||||||||||
| 0x4 | OTYPER | ||||||||||||||||||||||||||||||||
| 0x8 | OSPEEDR | ||||||||||||||||||||||||||||||||
| 0xc | PUPDR | ||||||||||||||||||||||||||||||||
| 0x10 | IDR | ||||||||||||||||||||||||||||||||
| 0x14 | ODR | ||||||||||||||||||||||||||||||||
| 0x18 | BSRR | ||||||||||||||||||||||||||||||||
| 0x20 | AFRL | ||||||||||||||||||||||||||||||||
| 0x24 | AFRH | ||||||||||||||||||||||||||||||||
| 0x28 | BRR | ||||||||||||||||||||||||||||||||
GPIO port mode register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MODER[15]
rw |
MODER[14]
rw |
MODER[13]
rw |
MODER[12]
rw |
MODER[11]
rw |
MODER[10]
rw |
MODER[9]
rw |
MODER[8]
rw |
||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MODER[7]
rw |
MODER[6]
rw |
MODER[5]
rw |
MODER[4]
rw |
MODER[3]
rw |
MODER[2]
rw |
MODER[1]
rw |
MODER[0]
rw |
||||||||
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
GPIO port output type register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OT[15]
rw |
OT[14]
rw |
OT[13]
rw |
OT[12]
rw |
OT[11]
rw |
OT[10]
rw |
OT[9]
rw |
OT[8]
rw |
OT[7]
rw |
OT[6]
rw |
OT[5]
rw |
OT[4]
rw |
OT[3]
rw |
OT[2]
rw |
OT[1]
rw |
OT[0]
rw |
Bit 0: Port x configuration pin 0.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 1: Port x configuration pin 1.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 2: Port x configuration pin 2.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 3: Port x configuration pin 3.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 4: Port x configuration pin 4.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 5: Port x configuration pin 5.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 6: Port x configuration pin 6.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 7: Port x configuration pin 7.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 8: Port x configuration pin 8.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 9: Port x configuration pin 9.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 10: Port x configuration pin 10.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 11: Port x configuration pin 11.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 12: Port x configuration pin 12.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 13: Port x configuration pin 13.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 14: Port x configuration pin 14.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 15: Port x configuration pin 15.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
GPIO port output speed register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OSPEEDR[15]
rw |
OSPEEDR[14]
rw |
OSPEEDR[13]
rw |
OSPEEDR[12]
rw |
OSPEEDR[11]
rw |
OSPEEDR[10]
rw |
OSPEEDR[9]
rw |
OSPEEDR[8]
rw |
||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OSPEEDR[7]
rw |
OSPEEDR[6]
rw |
OSPEEDR[5]
rw |
OSPEEDR[4]
rw |
OSPEEDR[3]
rw |
OSPEEDR[2]
rw |
OSPEEDR[1]
rw |
OSPEEDR[0]
rw |
||||||||
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
GPIO port pull-up/pull-down register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PUPDR[15]
rw |
PUPDR[14]
rw |
PUPDR[13]
rw |
PUPDR[12]
rw |
PUPDR[11]
rw |
PUPDR[10]
rw |
PUPDR[9]
rw |
PUPDR[8]
rw |
||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PUPDR[7]
rw |
PUPDR[6]
rw |
PUPDR[5]
rw |
PUPDR[4]
rw |
PUPDR[3]
rw |
PUPDR[2]
rw |
PUPDR[1]
rw |
PUPDR[0]
rw |
||||||||
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
GPIO port input data register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-only
16/16 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IDR[15]
r |
IDR[14]
r |
IDR[13]
r |
IDR[12]
r |
IDR[11]
r |
IDR[10]
r |
IDR[9]
r |
IDR[8]
r |
IDR[7]
r |
IDR[6]
r |
IDR[5]
r |
IDR[4]
r |
IDR[3]
r |
IDR[2]
r |
IDR[1]
r |
IDR[0]
r |
Bit 0: Port input data pin 0.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 1: Port input data pin 1.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 2: Port input data pin 2.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 3: Port input data pin 3.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 4: Port input data pin 4.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 5: Port input data pin 5.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 6: Port input data pin 6.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 7: Port input data pin 7.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 8: Port input data pin 8.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 9: Port input data pin 9.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 10: Port input data pin 10.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 11: Port input data pin 11.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 12: Port input data pin 12.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 13: Port input data pin 13.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 14: Port input data pin 14.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 15: Port input data pin 15.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
GPIO port output data register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ODR[15]
rw |
ODR[14]
rw |
ODR[13]
rw |
ODR[12]
rw |
ODR[11]
rw |
ODR[10]
rw |
ODR[9]
rw |
ODR[8]
rw |
ODR[7]
rw |
ODR[6]
rw |
ODR[5]
rw |
ODR[4]
rw |
ODR[3]
rw |
ODR[2]
rw |
ODR[1]
rw |
ODR[0]
rw |
Bit 0: Port output data pin 0.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 1: Port output data pin 1.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 2: Port output data pin 2.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 3: Port output data pin 3.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 4: Port output data pin 4.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 5: Port output data pin 5.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 6: Port output data pin 6.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 7: Port output data pin 7.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 8: Port output data pin 8.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 9: Port output data pin 9.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 10: Port output data pin 10.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 11: Port output data pin 11.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 12: Port output data pin 12.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 13: Port output data pin 13.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 14: Port output data pin 14.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 15: Port output data pin 15.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
GPIO port bit set/reset register
Offset: 0x18, size: 32, reset: 0x00000000, access: write-only
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BS[15]
w |
BS[14]
w |
BS[13]
w |
BS[12]
w |
BS[11]
w |
BS[10]
w |
BS[9]
w |
BS[8]
w |
BS[7]
w |
BS[6]
w |
BS[5]
w |
BS[4]
w |
BS[3]
w |
BS[2]
w |
BS[1]
w |
BS[0]
w |
Bit 0: Port x set pin 0.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 1: Port x set pin 1.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 2: Port x set pin 2.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 3: Port x set pin 3.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 4: Port x set pin 4.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 5: Port x set pin 5.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 6: Port x set pin 6.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 7: Port x set pin 7.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 8: Port x set pin 8.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 9: Port x set pin 9.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 10: Port x set pin 10.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 11: Port x set pin 11.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 12: Port x set pin 12.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 13: Port x set pin 13.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 14: Port x set pin 14.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 15: Port x set pin 15.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 16: Port x reset pin 0.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 17: Port x reset pin 1.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 18: Port x reset pin 2.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 19: Port x reset pin 3.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 20: Port x reset pin 4.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 21: Port x reset pin 5.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 22: Port x reset pin 6.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 23: Port x reset pin 7.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 24: Port x reset pin 8.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 25: Port x reset pin 9.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 26: Port x reset pin 10.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 27: Port x reset pin 11.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 28: Port x reset pin 12.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 29: Port x reset pin 13.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 30: Port x reset pin 14.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 31: Port x reset pin 15.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
GPIO alternate function low register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
AFR[L7]
rw |
AFR[L6]
rw |
AFR[L5]
rw |
AFR[L4]
rw |
||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
AFR[L3]
rw |
AFR[L2]
rw |
AFR[L1]
rw |
AFR[L0]
rw |
||||||||||||
Bits 0-3: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 4-7: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 8-11: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 12-15: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 16-19: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 20-23: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 24-27: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 28-31: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
GPIO alternate function high register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
AFR[H15]
rw |
AFR[H14]
rw |
AFR[H13]
rw |
AFR[H12]
rw |
||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
AFR[H11]
rw |
AFR[H10]
rw |
AFR[H9]
rw |
AFR[H8]
rw |
||||||||||||
Bits 0-3: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 4-7: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 8-11: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 12-15: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 16-19: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 20-23: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 24-27: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 28-31: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Port bit reset register
Offset: 0x28, size: 32, reset: 0x00000000, access: write-only
16/16 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
Bit 0: Port x reset pin 0.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 1: Port x reset pin 1.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 2: Port x reset pin 2.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 3: Port x reset pin 3.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 4: Port x reset pin 4.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 5: Port x reset pin 5.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 6: Port x reset pin 6.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 7: Port x reset pin 7.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 8: Port x reset pin 8.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 9: Port x reset pin 9.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 10: Port x reset pin 10.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 11: Port x reset pin 11.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 12: Port x reset pin 12.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 13: Port x reset pin 13.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 14: Port x reset pin 14.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 15: Port x reset pin 15.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
0x48001400: General-purpose I/Os
160/160 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | MODER | ||||||||||||||||||||||||||||||||
| 0x4 | OTYPER | ||||||||||||||||||||||||||||||||
| 0x8 | OSPEEDR | ||||||||||||||||||||||||||||||||
| 0xc | PUPDR | ||||||||||||||||||||||||||||||||
| 0x10 | IDR | ||||||||||||||||||||||||||||||||
| 0x14 | ODR | ||||||||||||||||||||||||||||||||
| 0x18 | BSRR | ||||||||||||||||||||||||||||||||
| 0x20 | AFRL | ||||||||||||||||||||||||||||||||
| 0x24 | AFRH | ||||||||||||||||||||||||||||||||
| 0x28 | BRR | ||||||||||||||||||||||||||||||||
GPIO port mode register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MODER[15]
rw |
MODER[14]
rw |
MODER[13]
rw |
MODER[12]
rw |
MODER[11]
rw |
MODER[10]
rw |
MODER[9]
rw |
MODER[8]
rw |
||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MODER[7]
rw |
MODER[6]
rw |
MODER[5]
rw |
MODER[4]
rw |
MODER[3]
rw |
MODER[2]
rw |
MODER[1]
rw |
MODER[0]
rw |
||||||||
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
GPIO port output type register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OT[15]
rw |
OT[14]
rw |
OT[13]
rw |
OT[12]
rw |
OT[11]
rw |
OT[10]
rw |
OT[9]
rw |
OT[8]
rw |
OT[7]
rw |
OT[6]
rw |
OT[5]
rw |
OT[4]
rw |
OT[3]
rw |
OT[2]
rw |
OT[1]
rw |
OT[0]
rw |
Bit 0: Port x configuration pin 0.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 1: Port x configuration pin 1.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 2: Port x configuration pin 2.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 3: Port x configuration pin 3.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 4: Port x configuration pin 4.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 5: Port x configuration pin 5.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 6: Port x configuration pin 6.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 7: Port x configuration pin 7.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 8: Port x configuration pin 8.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 9: Port x configuration pin 9.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 10: Port x configuration pin 10.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 11: Port x configuration pin 11.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 12: Port x configuration pin 12.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 13: Port x configuration pin 13.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 14: Port x configuration pin 14.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 15: Port x configuration pin 15.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
GPIO port output speed register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OSPEEDR[15]
rw |
OSPEEDR[14]
rw |
OSPEEDR[13]
rw |
OSPEEDR[12]
rw |
OSPEEDR[11]
rw |
OSPEEDR[10]
rw |
OSPEEDR[9]
rw |
OSPEEDR[8]
rw |
||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OSPEEDR[7]
rw |
OSPEEDR[6]
rw |
OSPEEDR[5]
rw |
OSPEEDR[4]
rw |
OSPEEDR[3]
rw |
OSPEEDR[2]
rw |
OSPEEDR[1]
rw |
OSPEEDR[0]
rw |
||||||||
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed
GPIO port pull-up/pull-down register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PUPDR[15]
rw |
PUPDR[14]
rw |
PUPDR[13]
rw |
PUPDR[12]
rw |
PUPDR[11]
rw |
PUPDR[10]
rw |
PUPDR[9]
rw |
PUPDR[8]
rw |
||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PUPDR[7]
rw |
PUPDR[6]
rw |
PUPDR[5]
rw |
PUPDR[4]
rw |
PUPDR[3]
rw |
PUPDR[2]
rw |
PUPDR[1]
rw |
PUPDR[0]
rw |
||||||||
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
GPIO port input data register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-only
16/16 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IDR[15]
r |
IDR[14]
r |
IDR[13]
r |
IDR[12]
r |
IDR[11]
r |
IDR[10]
r |
IDR[9]
r |
IDR[8]
r |
IDR[7]
r |
IDR[6]
r |
IDR[5]
r |
IDR[4]
r |
IDR[3]
r |
IDR[2]
r |
IDR[1]
r |
IDR[0]
r |
Bit 0: Port input data pin 0.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 1: Port input data pin 1.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 2: Port input data pin 2.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 3: Port input data pin 3.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 4: Port input data pin 4.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 5: Port input data pin 5.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 6: Port input data pin 6.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 7: Port input data pin 7.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 8: Port input data pin 8.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 9: Port input data pin 9.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 10: Port input data pin 10.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 11: Port input data pin 11.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 12: Port input data pin 12.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 13: Port input data pin 13.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 14: Port input data pin 14.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 15: Port input data pin 15.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
GPIO port output data register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ODR[15]
rw |
ODR[14]
rw |
ODR[13]
rw |
ODR[12]
rw |
ODR[11]
rw |
ODR[10]
rw |
ODR[9]
rw |
ODR[8]
rw |
ODR[7]
rw |
ODR[6]
rw |
ODR[5]
rw |
ODR[4]
rw |
ODR[3]
rw |
ODR[2]
rw |
ODR[1]
rw |
ODR[0]
rw |
Bit 0: Port output data pin 0.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 1: Port output data pin 1.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 2: Port output data pin 2.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 3: Port output data pin 3.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 4: Port output data pin 4.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 5: Port output data pin 5.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 6: Port output data pin 6.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 7: Port output data pin 7.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 8: Port output data pin 8.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 9: Port output data pin 9.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 10: Port output data pin 10.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 11: Port output data pin 11.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 12: Port output data pin 12.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 13: Port output data pin 13.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 14: Port output data pin 14.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 15: Port output data pin 15.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
GPIO port bit set/reset register
Offset: 0x18, size: 32, reset: 0x00000000, access: write-only
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BS[15]
w |
BS[14]
w |
BS[13]
w |
BS[12]
w |
BS[11]
w |
BS[10]
w |
BS[9]
w |
BS[8]
w |
BS[7]
w |
BS[6]
w |
BS[5]
w |
BS[4]
w |
BS[3]
w |
BS[2]
w |
BS[1]
w |
BS[0]
w |
Bit 0: Port x set pin 0.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 1: Port x set pin 1.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 2: Port x set pin 2.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 3: Port x set pin 3.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 4: Port x set pin 4.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 5: Port x set pin 5.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 6: Port x set pin 6.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 7: Port x set pin 7.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 8: Port x set pin 8.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 9: Port x set pin 9.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 10: Port x set pin 10.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 11: Port x set pin 11.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 12: Port x set pin 12.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 13: Port x set pin 13.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 14: Port x set pin 14.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 15: Port x set pin 15.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 16: Port x reset pin 0.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 17: Port x reset pin 1.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 18: Port x reset pin 2.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 19: Port x reset pin 3.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 20: Port x reset pin 4.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 21: Port x reset pin 5.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 22: Port x reset pin 6.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 23: Port x reset pin 7.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 24: Port x reset pin 8.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 25: Port x reset pin 9.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 26: Port x reset pin 10.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 27: Port x reset pin 11.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 28: Port x reset pin 12.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 29: Port x reset pin 13.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 30: Port x reset pin 14.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 31: Port x reset pin 15.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
GPIO alternate function low register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
AFR[L7]
rw |
AFR[L6]
rw |
AFR[L5]
rw |
AFR[L4]
rw |
||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
AFR[L3]
rw |
AFR[L2]
rw |
AFR[L1]
rw |
AFR[L0]
rw |
||||||||||||
Bits 0-3: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 4-7: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 8-11: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 12-15: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 16-19: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 20-23: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 24-27: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 28-31: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
GPIO alternate function high register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
AFR[H15]
rw |
AFR[H14]
rw |
AFR[H13]
rw |
AFR[H12]
rw |
||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
AFR[H11]
rw |
AFR[H10]
rw |
AFR[H9]
rw |
AFR[H8]
rw |
||||||||||||
Bits 0-3: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 4-7: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 8-11: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 12-15: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 16-19: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 20-23: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 24-27: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 28-31: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Port bit reset register
Offset: 0x28, size: 32, reset: 0x00000000, access: write-only
16/16 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
Bit 0: Port x reset pin 0.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 1: Port x reset pin 1.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 2: Port x reset pin 2.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 3: Port x reset pin 3.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 4: Port x reset pin 4.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 5: Port x reset pin 5.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 6: Port x reset pin 6.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 7: Port x reset pin 7.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 8: Port x reset pin 8.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 9: Port x reset pin 9.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 10: Port x reset pin 10.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 11: Port x reset pin 11.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 12: Port x reset pin 12.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 13: Port x reset pin 13.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 14: Port x reset pin 14.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 15: Port x reset pin 15.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
0x40005400: Inter-integrated circuit
76/77 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | OAR1 | ||||||||||||||||||||||||||||||||
| 0xc | OAR2 | ||||||||||||||||||||||||||||||||
| 0x10 | TIMINGR | ||||||||||||||||||||||||||||||||
| 0x14 | TIMEOUTR | ||||||||||||||||||||||||||||||||
| 0x18 | ISR | ||||||||||||||||||||||||||||||||
| 0x1c | ICR | ||||||||||||||||||||||||||||||||
| 0x20 | PECR | ||||||||||||||||||||||||||||||||
| 0x24 | RXDR | ||||||||||||||||||||||||||||||||
| 0x28 | TXDR | ||||||||||||||||||||||||||||||||
Control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified
20/21 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PECEN
rw |
ALERTEN
rw |
SMBDEN
rw |
SMBHEN
rw |
GCEN
rw |
WUPEN
rw |
NOSTRETCH
rw |
SBC
rw |
||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RXDMAEN
rw |
TXDMAEN
rw |
SWRST
w |
ANFOFF
rw |
DNF
rw |
ERRIE
rw |
TCIE
rw |
STOPIE
rw |
NACKIE
rw |
ADDRIE
rw |
RXIE
rw |
TXIE
rw |
PE
rw |
|||
Bit 0: Peripheral enable.
Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled
Bit 1: TX Interrupt enable.
Allowed values:
0: Disabled: Transmit (TXIS) interrupt disabled
1: Enabled: Transmit (TXIS) interrupt enabled
Bit 2: RX Interrupt enable.
Allowed values:
0: Disabled: Receive (RXNE) interrupt disabled
1: Enabled: Receive (RXNE) interrupt enabled
Bit 3: Address match interrupt enable (slave only).
Allowed values:
0: Disabled: Address match (ADDR) interrupts disabled
1: Enabled: Address match (ADDR) interrupts enabled
Bit 4: Not acknowledge received interrupt enable.
Allowed values:
0: Disabled: Not acknowledge (NACKF) received interrupts disabled
1: Enabled: Not acknowledge (NACKF) received interrupts enabled
Bit 5: STOP detection Interrupt enable.
Allowed values:
0: Disabled: Stop detection (STOPF) interrupt disabled
1: Enabled: Stop detection (STOPF) interrupt enabled
Bit 6: Transfer Complete interrupt enable.
Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled
Bit 7: Error interrupts enable.
Allowed values:
0: Disabled: Error detection interrupts disabled
1: Enabled: Error detection interrupts enabled
Bits 8-11: Digital noise filter.
Allowed values:
0: NoFilter: Digital filter disabled
1: Filter1: Digital filter enabled and filtering capability up to 1 tI2CCLK
2: Filter2: Digital filter enabled and filtering capability up to 2 tI2CCLK
3: Filter3: Digital filter enabled and filtering capability up to 3 tI2CCLK
4: Filter4: Digital filter enabled and filtering capability up to 4 tI2CCLK
5: Filter5: Digital filter enabled and filtering capability up to 5 tI2CCLK
6: Filter6: Digital filter enabled and filtering capability up to 6 tI2CCLK
7: Filter7: Digital filter enabled and filtering capability up to 7 tI2CCLK
8: Filter8: Digital filter enabled and filtering capability up to 8 tI2CCLK
9: Filter9: Digital filter enabled and filtering capability up to 9 tI2CCLK
10: Filter10: Digital filter enabled and filtering capability up to 10 tI2CCLK
11: Filter11: Digital filter enabled and filtering capability up to 11 tI2CCLK
12: Filter12: Digital filter enabled and filtering capability up to 12 tI2CCLK
13: Filter13: Digital filter enabled and filtering capability up to 13 tI2CCLK
14: Filter14: Digital filter enabled and filtering capability up to 14 tI2CCLK
15: Filter15: Digital filter enabled and filtering capability up to 15 tI2CCLK
Bit 12: Analog noise filter OFF.
Allowed values:
0: Enabled: Analog noise filter enabled
1: Disabled: Analog noise filter disabled
Bit 13: Software reset.
Bit 14: DMA transmission requests enable.
Allowed values:
0: Disabled: DMA mode disabled for transmission
1: Enabled: DMA mode enabled for transmission
Bit 15: DMA reception requests enable.
Allowed values:
0: Disabled: DMA mode disabled for reception
1: Enabled: DMA mode enabled for reception
Bit 16: Slave byte control.
Allowed values:
0: Disabled: Slave byte control disabled
1: Enabled: Slave byte control enabled
Bit 17: Clock stretching disable.
Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled
Bit 18: Wakeup from STOP enable.
Allowed values:
0: Disabled: Wakeup from Stop mode disabled
1: Enabled: Wakeup from Stop mode enabled
Bit 19: General call enable.
Allowed values:
0: Disabled: General call disabled. Address 0b00000000 is NACKed
1: Enabled: General call enabled. Address 0b00000000 is ACKed
Bit 20: SMBus Host address enable.
Allowed values:
0: Disabled: Host address disabled. Address 0b0001000x is NACKed
1: Enabled: Host address enabled. Address 0b0001000x is ACKed
Bit 21: SMBus Device Default address enable.
Allowed values:
0: Disabled: Device default address disabled. Address 0b1100001x is NACKed
1: Enabled: Device default address enabled. Address 0b1100001x is ACKed
Bit 22: SMBUS alert enable.
Allowed values:
0: Disabled: In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
1: Enabled: In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported
Bit 23: PEC enable.
Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled
Control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
11/11 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PECBYTE
rw |
AUTOEND
rw |
RELOAD
rw |
NBYTES
rw |
||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
NACK
rw |
STOP
rw |
START
rw |
HEAD10R
rw |
ADD10
rw |
RD_WRN
rw |
SADD
rw |
|||||||||
Bits 0-9: Slave address bit 9:8 (master mode).
Allowed values: 0x0-0x3ff
Bit 10: Transfer direction (master mode).
Allowed values:
0: Write: Master requests a write transfer
1: Read: Master requests a read transfer
Bit 11: 10-bit addressing mode (master mode).
Allowed values:
0: Bit7: The master operates in 7-bit addressing mode
1: Bit10: The master operates in 10-bit addressing mode
Bit 12: 10-bit address header only read direction (master receiver mode).
Allowed values:
0: Complete: The master sends the complete 10 bit slave address read sequence
1: Partial: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction
Bit 13: Start generation.
Allowed values:
0: NoStart: No Start generation
1: Start: Restart/Start generation
Bit 14: Stop generation (master mode).
Allowed values:
0: NoStop: No Stop generation
1: Stop: Stop generation after current byte transfer
Bit 15: NACK generation (slave mode).
Allowed values:
0: Ack: an ACK is sent after current received byte
1: Nack: a NACK is sent after current received byte
Bits 16-23: Number of bytes.
Allowed values: 0x0-0xff
Bit 24: NBYTES reload mode.
Allowed values:
0: Completed: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)
1: NotCompleted: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)
Bit 25: Automatic end mode (master mode).
Allowed values:
0: Software: Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low
1: Automatic: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred
Bit 26: Packet error checking byte.
Allowed values:
0: NoPec: No PEC transfer
1: Pec: PEC transmission/reception is requested
Own address register 1
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
3/3 fields covered.
Bits 0-9: Interface address.
Allowed values: 0x0-0x3ff
Bit 10: Own Address 1 10-bit mode.
Allowed values:
0: Bit7: Own address 1 is a 7-bit address
1: Bit10: Own address 1 is a 10-bit address
Bit 15: Own Address 1 enable.
Allowed values:
0: Disabled: Own address 1 disabled. The received slave address OA1 is NACKed
1: Enabled: Own address 1 enabled. The received slave address OA1 is ACKed
Own address register 2
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
3/3 fields covered.
Bits 1-7: Interface address.
Allowed values: 0x0-0x7f
Bits 8-10: Own Address 2 masks.
Allowed values:
0: NoMask: No mask
1: Mask1: OA2[1] is masked and don’t care. Only OA2[7:2] are compared
2: Mask2: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
3: Mask3: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
4: Mask4: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
5: Mask5: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
6: Mask6: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
7: Mask7: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged
Bit 15: Own Address 2 enable.
Allowed values:
0: Disabled: Own address 2 disabled. The received slave address OA2 is NACKed
1: Enabled: Own address 2 enabled. The received slave address OA2 is ACKed
Timing register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
5/5 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PRESC
rw |
SCLDEL
rw |
SDADEL
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SCLH
rw |
SCLL
rw |
||||||||||||||
Bits 0-7: SCL low period (master mode).
Allowed values: 0x0-0xff
Bits 8-15: SCL high period (master mode).
Allowed values: 0x0-0xff
Bits 16-19: Data hold time.
Allowed values: 0x0-0xf
Bits 20-23: Data setup time.
Allowed values: 0x0-0xf
Bits 28-31: Timing prescaler.
Allowed values: 0x0-0xf
Status register 1
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
5/5 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TEXTEN
rw |
TIMEOUTB
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TIMOUTEN
rw |
TIDLE
rw |
TIMEOUTA
rw |
|||||||||||||
Bits 0-11: Bus timeout A.
Allowed values: 0x0-0xfff
Bit 12: Idle clock timeout detection.
Allowed values:
0: Disabled: TIMEOUTA is used to detect SCL low timeout
1: Enabled: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)
Bit 15: Clock timeout enable.
Allowed values:
0: Disabled: SCL timeout detection is disabled
1: Enabled: SCL timeout detection is enabled
Bits 16-27: Bus timeout B.
Allowed values: 0x0-0xfff
Bit 31: Extended clock timeout enable.
Allowed values:
0: Disabled: Extended clock timeout detection is disabled
1: Enabled: Extended clock timeout detection is enabled
Interrupt and Status register
Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified
17/17 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ADDCODE
r |
DIR
r |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BUSY
r |
ALERT
r |
TIMEOUT
r |
PECERR
r |
OVR
r |
ARLO
r |
BERR
r |
TCR
r |
TC
r |
STOPF
r |
NACKF
r |
ADDR
r |
RXNE
r |
TXIS
rw |
TXE
rw |
|
Bit 0: Transmit data register empty (transmitters).
Allowed values:
0: NotEmpty: TXDR register not empty
1: Empty: TXDR register empty
Bit 1: Transmit interrupt status (transmitters).
Allowed values:
0: NotEmpty: The TXDR register is not empty
1: Empty: The TXDR register is empty and the data to be transmitted must be written in the TXDR register
Bit 2: Receive data register not empty (receivers).
Allowed values:
0: Empty: The RXDR register is empty
1: NotEmpty: Received data is copied into the RXDR register, and is ready to be read
Bit 3: Address matched (slave mode).
Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses
Bit 4: Not acknowledge received flag.
Allowed values:
0: NoNack: No NACK has been received
1: Nack: NACK has been received
Bit 5: Stop detection flag.
Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected
Bit 6: Transfer Complete (master mode).
Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered
Bit 7: Transfer Complete Reload.
Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered
Bit 8: Bus error.
Allowed values:
0: NoError: No bus error
1: Error: Misplaced Start and Stop condition is detected
Bit 9: Arbitration lost.
Allowed values:
0: NotLost: No arbitration lost
1: Lost: Arbitration lost
Bit 10: Overrun/Underrun (slave mode).
Allowed values:
0: NoOverrun: No overrun/underrun error occurs
1: Overrun: slave mode with NOSTRETCH=1, when an overrun/underrun error occurs
Bit 11: PEC Error in reception.
Allowed values:
0: Match: Received PEC does match with PEC register
1: NoMatch: Received PEC does not match with PEC register
Bit 12: Timeout or t_low detection flag.
Allowed values:
0: NoTimeout: No timeout occured
1: Timeout: Timeout occured
Bit 13: SMBus alert.
Allowed values:
0: NoAlert: SMBA alert is not detected
1: Alert: SMBA alert event is detected on SMBA pin
Bit 15: Bus busy.
Allowed values:
0: NotBusy: No communication is in progress on the bus
1: Busy: A communication is in progress on the bus
Bit 16: Transfer direction (Slave mode).
Allowed values:
0: Write: Write transfer, slave enters receiver mode
1: Read: Read transfer, slave enters transmitter mode
Bits 17-23: Address match code (Slave mode).
Allowed values: 0x0-0x7f
Interrupt clear register
Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only
9/9 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ALERTCF
w |
TIMOUTCF
w |
PECCF
w |
OVRCF
w |
ARLOCF
w |
BERRCF
w |
STOPCF
w |
NACKCF
w |
ADDRCF
w |
|||||||
Bit 3: Address Matched flag clear.
Allowed values:
1: Clear: Clears the ADDR flag in ISR register
Bit 4: Not Acknowledge flag clear.
Allowed values:
1: Clear: Clears the NACK flag in ISR register
Bit 5: Stop detection flag clear.
Allowed values:
1: Clear: Clears the STOP flag in ISR register
Bit 8: Bus error flag clear.
Allowed values:
1: Clear: Clears the BERR flag in ISR register
Bit 9: Arbitration lost flag clear.
Allowed values:
1: Clear: Clears the ARLO flag in ISR register
Bit 10: Overrun/Underrun flag clear.
Allowed values:
1: Clear: Clears the OVR flag in ISR register
Bit 11: PEC Error flag clear.
Allowed values:
1: Clear: Clears the PEC flag in ISR register
Bit 12: Timeout detection flag clear.
Allowed values:
1: Clear: Clears the TIMOUT flag in ISR register
Bit 13: Alert flag clear.
Allowed values:
1: Clear: Clears the ALERT flag in ISR register
PEC register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PEC
r |
|||||||||||||||
Receive data register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
RXDATA
r |
|||||||||||||||
Transmit data register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TXDATA
rw |
|||||||||||||||
0x40005800: Inter-integrated circuit
76/77 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | OAR1 | ||||||||||||||||||||||||||||||||
| 0xc | OAR2 | ||||||||||||||||||||||||||||||||
| 0x10 | TIMINGR | ||||||||||||||||||||||||||||||||
| 0x14 | TIMEOUTR | ||||||||||||||||||||||||||||||||
| 0x18 | ISR | ||||||||||||||||||||||||||||||||
| 0x1c | ICR | ||||||||||||||||||||||||||||||||
| 0x20 | PECR | ||||||||||||||||||||||||||||||||
| 0x24 | RXDR | ||||||||||||||||||||||||||||||||
| 0x28 | TXDR | ||||||||||||||||||||||||||||||||
Control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified
20/21 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PECEN
rw |
ALERTEN
rw |
SMBDEN
rw |
SMBHEN
rw |
GCEN
rw |
WUPEN
rw |
NOSTRETCH
rw |
SBC
rw |
||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RXDMAEN
rw |
TXDMAEN
rw |
SWRST
w |
ANFOFF
rw |
DNF
rw |
ERRIE
rw |
TCIE
rw |
STOPIE
rw |
NACKIE
rw |
ADDRIE
rw |
RXIE
rw |
TXIE
rw |
PE
rw |
|||
Bit 0: Peripheral enable.
Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled
Bit 1: TX Interrupt enable.
Allowed values:
0: Disabled: Transmit (TXIS) interrupt disabled
1: Enabled: Transmit (TXIS) interrupt enabled
Bit 2: RX Interrupt enable.
Allowed values:
0: Disabled: Receive (RXNE) interrupt disabled
1: Enabled: Receive (RXNE) interrupt enabled
Bit 3: Address match interrupt enable (slave only).
Allowed values:
0: Disabled: Address match (ADDR) interrupts disabled
1: Enabled: Address match (ADDR) interrupts enabled
Bit 4: Not acknowledge received interrupt enable.
Allowed values:
0: Disabled: Not acknowledge (NACKF) received interrupts disabled
1: Enabled: Not acknowledge (NACKF) received interrupts enabled
Bit 5: STOP detection Interrupt enable.
Allowed values:
0: Disabled: Stop detection (STOPF) interrupt disabled
1: Enabled: Stop detection (STOPF) interrupt enabled
Bit 6: Transfer Complete interrupt enable.
Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled
Bit 7: Error interrupts enable.
Allowed values:
0: Disabled: Error detection interrupts disabled
1: Enabled: Error detection interrupts enabled
Bits 8-11: Digital noise filter.
Allowed values:
0: NoFilter: Digital filter disabled
1: Filter1: Digital filter enabled and filtering capability up to 1 tI2CCLK
2: Filter2: Digital filter enabled and filtering capability up to 2 tI2CCLK
3: Filter3: Digital filter enabled and filtering capability up to 3 tI2CCLK
4: Filter4: Digital filter enabled and filtering capability up to 4 tI2CCLK
5: Filter5: Digital filter enabled and filtering capability up to 5 tI2CCLK
6: Filter6: Digital filter enabled and filtering capability up to 6 tI2CCLK
7: Filter7: Digital filter enabled and filtering capability up to 7 tI2CCLK
8: Filter8: Digital filter enabled and filtering capability up to 8 tI2CCLK
9: Filter9: Digital filter enabled and filtering capability up to 9 tI2CCLK
10: Filter10: Digital filter enabled and filtering capability up to 10 tI2CCLK
11: Filter11: Digital filter enabled and filtering capability up to 11 tI2CCLK
12: Filter12: Digital filter enabled and filtering capability up to 12 tI2CCLK
13: Filter13: Digital filter enabled and filtering capability up to 13 tI2CCLK
14: Filter14: Digital filter enabled and filtering capability up to 14 tI2CCLK
15: Filter15: Digital filter enabled and filtering capability up to 15 tI2CCLK
Bit 12: Analog noise filter OFF.
Allowed values:
0: Enabled: Analog noise filter enabled
1: Disabled: Analog noise filter disabled
Bit 13: Software reset.
Bit 14: DMA transmission requests enable.
Allowed values:
0: Disabled: DMA mode disabled for transmission
1: Enabled: DMA mode enabled for transmission
Bit 15: DMA reception requests enable.
Allowed values:
0: Disabled: DMA mode disabled for reception
1: Enabled: DMA mode enabled for reception
Bit 16: Slave byte control.
Allowed values:
0: Disabled: Slave byte control disabled
1: Enabled: Slave byte control enabled
Bit 17: Clock stretching disable.
Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled
Bit 18: Wakeup from STOP enable.
Allowed values:
0: Disabled: Wakeup from Stop mode disabled
1: Enabled: Wakeup from Stop mode enabled
Bit 19: General call enable.
Allowed values:
0: Disabled: General call disabled. Address 0b00000000 is NACKed
1: Enabled: General call enabled. Address 0b00000000 is ACKed
Bit 20: SMBus Host address enable.
Allowed values:
0: Disabled: Host address disabled. Address 0b0001000x is NACKed
1: Enabled: Host address enabled. Address 0b0001000x is ACKed
Bit 21: SMBus Device Default address enable.
Allowed values:
0: Disabled: Device default address disabled. Address 0b1100001x is NACKed
1: Enabled: Device default address enabled. Address 0b1100001x is ACKed
Bit 22: SMBUS alert enable.
Allowed values:
0: Disabled: In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
1: Enabled: In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported
Bit 23: PEC enable.
Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled
Control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
11/11 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PECBYTE
rw |
AUTOEND
rw |
RELOAD
rw |
NBYTES
rw |
||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
NACK
rw |
STOP
rw |
START
rw |
HEAD10R
rw |
ADD10
rw |
RD_WRN
rw |
SADD
rw |
|||||||||
Bits 0-9: Slave address bit 9:8 (master mode).
Allowed values: 0x0-0x3ff
Bit 10: Transfer direction (master mode).
Allowed values:
0: Write: Master requests a write transfer
1: Read: Master requests a read transfer
Bit 11: 10-bit addressing mode (master mode).
Allowed values:
0: Bit7: The master operates in 7-bit addressing mode
1: Bit10: The master operates in 10-bit addressing mode
Bit 12: 10-bit address header only read direction (master receiver mode).
Allowed values:
0: Complete: The master sends the complete 10 bit slave address read sequence
1: Partial: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction
Bit 13: Start generation.
Allowed values:
0: NoStart: No Start generation
1: Start: Restart/Start generation
Bit 14: Stop generation (master mode).
Allowed values:
0: NoStop: No Stop generation
1: Stop: Stop generation after current byte transfer
Bit 15: NACK generation (slave mode).
Allowed values:
0: Ack: an ACK is sent after current received byte
1: Nack: a NACK is sent after current received byte
Bits 16-23: Number of bytes.
Allowed values: 0x0-0xff
Bit 24: NBYTES reload mode.
Allowed values:
0: Completed: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)
1: NotCompleted: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)
Bit 25: Automatic end mode (master mode).
Allowed values:
0: Software: Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low
1: Automatic: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred
Bit 26: Packet error checking byte.
Allowed values:
0: NoPec: No PEC transfer
1: Pec: PEC transmission/reception is requested
Own address register 1
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
3/3 fields covered.
Bits 0-9: Interface address.
Allowed values: 0x0-0x3ff
Bit 10: Own Address 1 10-bit mode.
Allowed values:
0: Bit7: Own address 1 is a 7-bit address
1: Bit10: Own address 1 is a 10-bit address
Bit 15: Own Address 1 enable.
Allowed values:
0: Disabled: Own address 1 disabled. The received slave address OA1 is NACKed
1: Enabled: Own address 1 enabled. The received slave address OA1 is ACKed
Own address register 2
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
3/3 fields covered.
Bits 1-7: Interface address.
Allowed values: 0x0-0x7f
Bits 8-10: Own Address 2 masks.
Allowed values:
0: NoMask: No mask
1: Mask1: OA2[1] is masked and don’t care. Only OA2[7:2] are compared
2: Mask2: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
3: Mask3: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
4: Mask4: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
5: Mask5: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
6: Mask6: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
7: Mask7: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged
Bit 15: Own Address 2 enable.
Allowed values:
0: Disabled: Own address 2 disabled. The received slave address OA2 is NACKed
1: Enabled: Own address 2 enabled. The received slave address OA2 is ACKed
Timing register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
5/5 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PRESC
rw |
SCLDEL
rw |
SDADEL
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SCLH
rw |
SCLL
rw |
||||||||||||||
Bits 0-7: SCL low period (master mode).
Allowed values: 0x0-0xff
Bits 8-15: SCL high period (master mode).
Allowed values: 0x0-0xff
Bits 16-19: Data hold time.
Allowed values: 0x0-0xf
Bits 20-23: Data setup time.
Allowed values: 0x0-0xf
Bits 28-31: Timing prescaler.
Allowed values: 0x0-0xf
Status register 1
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
5/5 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TEXTEN
rw |
TIMEOUTB
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TIMOUTEN
rw |
TIDLE
rw |
TIMEOUTA
rw |
|||||||||||||
Bits 0-11: Bus timeout A.
Allowed values: 0x0-0xfff
Bit 12: Idle clock timeout detection.
Allowed values:
0: Disabled: TIMEOUTA is used to detect SCL low timeout
1: Enabled: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)
Bit 15: Clock timeout enable.
Allowed values:
0: Disabled: SCL timeout detection is disabled
1: Enabled: SCL timeout detection is enabled
Bits 16-27: Bus timeout B.
Allowed values: 0x0-0xfff
Bit 31: Extended clock timeout enable.
Allowed values:
0: Disabled: Extended clock timeout detection is disabled
1: Enabled: Extended clock timeout detection is enabled
Interrupt and Status register
Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified
17/17 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ADDCODE
r |
DIR
r |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BUSY
r |
ALERT
r |
TIMEOUT
r |
PECERR
r |
OVR
r |
ARLO
r |
BERR
r |
TCR
r |
TC
r |
STOPF
r |
NACKF
r |
ADDR
r |
RXNE
r |
TXIS
rw |
TXE
rw |
|
Bit 0: Transmit data register empty (transmitters).
Allowed values:
0: NotEmpty: TXDR register not empty
1: Empty: TXDR register empty
Bit 1: Transmit interrupt status (transmitters).
Allowed values:
0: NotEmpty: The TXDR register is not empty
1: Empty: The TXDR register is empty and the data to be transmitted must be written in the TXDR register
Bit 2: Receive data register not empty (receivers).
Allowed values:
0: Empty: The RXDR register is empty
1: NotEmpty: Received data is copied into the RXDR register, and is ready to be read
Bit 3: Address matched (slave mode).
Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses
Bit 4: Not acknowledge received flag.
Allowed values:
0: NoNack: No NACK has been received
1: Nack: NACK has been received
Bit 5: Stop detection flag.
Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected
Bit 6: Transfer Complete (master mode).
Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered
Bit 7: Transfer Complete Reload.
Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered
Bit 8: Bus error.
Allowed values:
0: NoError: No bus error
1: Error: Misplaced Start and Stop condition is detected
Bit 9: Arbitration lost.
Allowed values:
0: NotLost: No arbitration lost
1: Lost: Arbitration lost
Bit 10: Overrun/Underrun (slave mode).
Allowed values:
0: NoOverrun: No overrun/underrun error occurs
1: Overrun: slave mode with NOSTRETCH=1, when an overrun/underrun error occurs
Bit 11: PEC Error in reception.
Allowed values:
0: Match: Received PEC does match with PEC register
1: NoMatch: Received PEC does not match with PEC register
Bit 12: Timeout or t_low detection flag.
Allowed values:
0: NoTimeout: No timeout occured
1: Timeout: Timeout occured
Bit 13: SMBus alert.
Allowed values:
0: NoAlert: SMBA alert is not detected
1: Alert: SMBA alert event is detected on SMBA pin
Bit 15: Bus busy.
Allowed values:
0: NotBusy: No communication is in progress on the bus
1: Busy: A communication is in progress on the bus
Bit 16: Transfer direction (Slave mode).
Allowed values:
0: Write: Write transfer, slave enters receiver mode
1: Read: Read transfer, slave enters transmitter mode
Bits 17-23: Address match code (Slave mode).
Allowed values: 0x0-0x7f
Interrupt clear register
Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only
9/9 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ALERTCF
w |
TIMOUTCF
w |
PECCF
w |
OVRCF
w |
ARLOCF
w |
BERRCF
w |
STOPCF
w |
NACKCF
w |
ADDRCF
w |
|||||||
Bit 3: Address Matched flag clear.
Allowed values:
1: Clear: Clears the ADDR flag in ISR register
Bit 4: Not Acknowledge flag clear.
Allowed values:
1: Clear: Clears the NACK flag in ISR register
Bit 5: Stop detection flag clear.
Allowed values:
1: Clear: Clears the STOP flag in ISR register
Bit 8: Bus error flag clear.
Allowed values:
1: Clear: Clears the BERR flag in ISR register
Bit 9: Arbitration lost flag clear.
Allowed values:
1: Clear: Clears the ARLO flag in ISR register
Bit 10: Overrun/Underrun flag clear.
Allowed values:
1: Clear: Clears the OVR flag in ISR register
Bit 11: PEC Error flag clear.
Allowed values:
1: Clear: Clears the PEC flag in ISR register
Bit 12: Timeout detection flag clear.
Allowed values:
1: Clear: Clears the TIMOUT flag in ISR register
Bit 13: Alert flag clear.
Allowed values:
1: Clear: Clears the ALERT flag in ISR register
PEC register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PEC
r |
|||||||||||||||
Receive data register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
RXDATA
r |
|||||||||||||||
Transmit data register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TXDATA
rw |
|||||||||||||||
0x40003400: Serial peripheral interface/Inter-IC sound
53/53 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 (16-bit) | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 (16-bit) | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 (16-bit) | SR | ||||||||||||||||||||||||||||||||
| 0xc (16-bit) | DR | ||||||||||||||||||||||||||||||||
| 0xc (8-bit) | DR8 | ||||||||||||||||||||||||||||||||
| 0x10 (16-bit) | CRCPR | ||||||||||||||||||||||||||||||||
| 0x14 (16-bit) | RXCRCR | ||||||||||||||||||||||||||||||||
| 0x18 (16-bit) | TXCRCR | ||||||||||||||||||||||||||||||||
| 0x1c (16-bit) | I2SCFGR | ||||||||||||||||||||||||||||||||
| 0x20 (16-bit) | I2SPR | ||||||||||||||||||||||||||||||||
control register 1
Offset: 0x0, size: 16, reset: 0x00000000, access: read-write
14/14 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BIDIMODE
rw |
BIDIOE
rw |
CRCEN
rw |
CRCNEXT
rw |
CRCL
rw |
RXONLY
rw |
SSM
rw |
SSI
rw |
LSBFIRST
rw |
SPE
rw |
BR
rw |
MSTR
rw |
CPOL
rw |
CPHA
rw |
||
Bit 0: Clock phase.
Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge
Bit 1: Clock polarity.
Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle
Bit 2: Master selection.
Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration
Bits 3-5: Baud rate control.
Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256
Bit 6: SPI enable.
Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled
Bit 7: Frame format.
Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first
Bit 8: Internal slave select.
Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
Bit 9: Software slave management.
Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled
Bit 10: Receive only.
Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)
Bit 11: CRC length.
Allowed values:
0: EightBit: 8-bit CRC length
1: SixteenBit: 16-bit CRC length
Bit 12: CRC transfer next.
Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register
Bit 13: Hardware CRC calculation enable.
Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled
Bit 14: Output enable in bidirectional mode.
Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)
Bit 15: Bidirectional data mode enable.
Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected
control register 2
Offset: 0x4, size: 16, reset: 0x00000000, access: read-write
12/12 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
LDMA_TX
rw |
LDMA_RX
rw |
FRXTH
rw |
DS
rw |
TXEIE
rw |
RXNEIE
rw |
ERRIE
rw |
FRF
rw |
NSSP
rw |
SSOE
rw |
TXDMAEN
rw |
RXDMAEN
rw |
||||
Bit 0: Rx buffer DMA enable.
Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled
Bit 1: Tx buffer DMA enable.
Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled
Bit 2: SS output enable.
Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode
Bit 3: NSS pulse management.
Allowed values:
0: NoPulse: No NSS pulse
1: PulseGenerated: NSS pulse generated
Bit 4: Frame format.
Allowed values:
0: Motorola: SPI Motorola mode
1: TI: SPI TI mode
Bit 5: Error interrupt enable.
Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked
Bit 6: RX buffer not empty interrupt enable.
Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked
Bit 7: Tx buffer empty interrupt enable.
Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked
Bits 8-11: Data size.
Allowed values:
3: FourBit: 4-bit
4: FiveBit: 5-bit
5: SixBit: 6-bit
6: SevenBit: 7-bit
7: EightBit: 8-bit
8: NineBit: 9-bit
9: TenBit: 10-bit
10: ElevenBit: 11-bit
11: TwelveBit: 12-bit
12: ThirteenBit: 13-bit
13: FourteenBit: 14-bit
14: FifteenBit: 15-bit
15: SixteenBit: 16-bit
Bit 12: FIFO reception threshold.
Allowed values:
0: Half: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)
1: Quarter: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)
Bit 13: Last DMA transfer for reception.
Allowed values:
0: Even: Number of data to transfer for receive is even
1: Odd: Number of data to transfer for receive is odd
Bit 14: Last DMA transfer for transmission.
Allowed values:
0: Even: Number of data to transfer for transmit is even
1: Odd: Number of data to transfer for transmit is odd
status register
Offset: 0x8, size: 16, reset: 0x00000002, access: Unspecified
11/11 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
FTLVL
r |
FRLVL
r |
TIFRFE
r |
BSY
r |
OVR
r |
MODF
r |
CRCERR
rw |
UDR
r |
CHSIDE
r |
TXE
r |
RXNE
r |
|||||
Bit 0: Receive buffer not empty.
Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty
Bit 1: Transmit buffer empty.
Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty
Bit 2: Channel side.
Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received
Bit 3: Underrun flag.
Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred
Bit 4: CRC error flag.
Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value
Bit 5: Mode fault.
Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred
Bit 6: Overrun flag.
Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred
Bit 7: Busy flag.
Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy
Bit 8: TI frame format error.
Allowed values:
0: NoError: No frame format error
1: Error: A frame format error occurred
Bits 9-10: FIFO reception level.
Allowed values:
0: Empty: Rx FIFO Empty
1: Quarter: Rx 1/4 FIFO
2: Half: Rx 1/2 FIFO
3: Full: Rx FIFO full
Bits 11-12: FIFO transmission level.
Allowed values:
0: Empty: Tx FIFO Empty
1: Quarter: Tx 1/4 FIFO
2: Half: Tx 1/2 FIFO
3: Full: Tx FIFO full
data register
Offset: 0xc, size: 16, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DR
rw |
|||||||||||||||
Direct 8-bit access to data register
Offset: 0xc, size: 8, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DR
rw |
|||||||||||||||
CRC polynomial register
Offset: 0x10, size: 16, reset: 0x00000007, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CRCPOLY
rw |
|||||||||||||||
RX CRC register
Offset: 0x14, size: 16, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
RxCRC
r |
|||||||||||||||
TX CRC register
Offset: 0x18, size: 16, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TxCRC
r |
|||||||||||||||
I2S configuration register
Offset: 0x1c, size: 16, reset: 0x00000000, access: read-write
8/8 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
I2SMOD
rw |
I2SE
rw |
I2SCFG
rw |
PCMSYNC
rw |
I2SSTD
rw |
CKPOL
rw |
DATLEN
rw |
CHLEN
rw |
||||||||
Bit 0: Channel length (number of bits per audio channel).
Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide
Bits 1-2: Data length to be transferred.
Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length
Bit 3: Steady state clock polarity.
Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level
Bits 4-5: I2S standard selection.
Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard
Bit 7: PCM frame synchronization.
Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation
Bits 8-9: I2S configuration mode.
Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive
Bit 10: I2S Enable.
Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled
Bit 11: I2S mode selection.
Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected
I2S prescaler register
Offset: 0x20, size: 16, reset: 0x00000010, access: read-write
3/3 fields covered.
Bits 0-7: I2S Linear prescaler.
Allowed values: 0x2-0xff
Bit 8: Odd factor for the prescaler.
Allowed values:
0: Even: Real divider value is I2SDIV * 2
1: Odd: Real divider value is (I2SDIV * 2) + 1
Bit 9: Master clock output enable.
Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled
0x40004000: Serial peripheral interface/Inter-IC sound
53/53 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 (16-bit) | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 (16-bit) | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 (16-bit) | SR | ||||||||||||||||||||||||||||||||
| 0xc (16-bit) | DR | ||||||||||||||||||||||||||||||||
| 0xc (8-bit) | DR8 | ||||||||||||||||||||||||||||||||
| 0x10 (16-bit) | CRCPR | ||||||||||||||||||||||||||||||||
| 0x14 (16-bit) | RXCRCR | ||||||||||||||||||||||||||||||||
| 0x18 (16-bit) | TXCRCR | ||||||||||||||||||||||||||||||||
| 0x1c (16-bit) | I2SCFGR | ||||||||||||||||||||||||||||||||
| 0x20 (16-bit) | I2SPR | ||||||||||||||||||||||||||||||||
control register 1
Offset: 0x0, size: 16, reset: 0x00000000, access: read-write
14/14 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BIDIMODE
rw |
BIDIOE
rw |
CRCEN
rw |
CRCNEXT
rw |
CRCL
rw |
RXONLY
rw |
SSM
rw |
SSI
rw |
LSBFIRST
rw |
SPE
rw |
BR
rw |
MSTR
rw |
CPOL
rw |
CPHA
rw |
||
Bit 0: Clock phase.
Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge
Bit 1: Clock polarity.
Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle
Bit 2: Master selection.
Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration
Bits 3-5: Baud rate control.
Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256
Bit 6: SPI enable.
Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled
Bit 7: Frame format.
Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first
Bit 8: Internal slave select.
Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
Bit 9: Software slave management.
Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled
Bit 10: Receive only.
Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)
Bit 11: CRC length.
Allowed values:
0: EightBit: 8-bit CRC length
1: SixteenBit: 16-bit CRC length
Bit 12: CRC transfer next.
Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register
Bit 13: Hardware CRC calculation enable.
Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled
Bit 14: Output enable in bidirectional mode.
Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)
Bit 15: Bidirectional data mode enable.
Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected
control register 2
Offset: 0x4, size: 16, reset: 0x00000000, access: read-write
12/12 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
LDMA_TX
rw |
LDMA_RX
rw |
FRXTH
rw |
DS
rw |
TXEIE
rw |
RXNEIE
rw |
ERRIE
rw |
FRF
rw |
NSSP
rw |
SSOE
rw |
TXDMAEN
rw |
RXDMAEN
rw |
||||
Bit 0: Rx buffer DMA enable.
Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled
Bit 1: Tx buffer DMA enable.
Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled
Bit 2: SS output enable.
Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode
Bit 3: NSS pulse management.
Allowed values:
0: NoPulse: No NSS pulse
1: PulseGenerated: NSS pulse generated
Bit 4: Frame format.
Allowed values:
0: Motorola: SPI Motorola mode
1: TI: SPI TI mode
Bit 5: Error interrupt enable.
Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked
Bit 6: RX buffer not empty interrupt enable.
Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked
Bit 7: Tx buffer empty interrupt enable.
Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked
Bits 8-11: Data size.
Allowed values:
3: FourBit: 4-bit
4: FiveBit: 5-bit
5: SixBit: 6-bit
6: SevenBit: 7-bit
7: EightBit: 8-bit
8: NineBit: 9-bit
9: TenBit: 10-bit
10: ElevenBit: 11-bit
11: TwelveBit: 12-bit
12: ThirteenBit: 13-bit
13: FourteenBit: 14-bit
14: FifteenBit: 15-bit
15: SixteenBit: 16-bit
Bit 12: FIFO reception threshold.
Allowed values:
0: Half: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)
1: Quarter: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)
Bit 13: Last DMA transfer for reception.
Allowed values:
0: Even: Number of data to transfer for receive is even
1: Odd: Number of data to transfer for receive is odd
Bit 14: Last DMA transfer for transmission.
Allowed values:
0: Even: Number of data to transfer for transmit is even
1: Odd: Number of data to transfer for transmit is odd
status register
Offset: 0x8, size: 16, reset: 0x00000002, access: Unspecified
11/11 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
FTLVL
r |
FRLVL
r |
TIFRFE
r |
BSY
r |
OVR
r |
MODF
r |
CRCERR
rw |
UDR
r |
CHSIDE
r |
TXE
r |
RXNE
r |
|||||
Bit 0: Receive buffer not empty.
Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty
Bit 1: Transmit buffer empty.
Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty
Bit 2: Channel side.
Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received
Bit 3: Underrun flag.
Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred
Bit 4: CRC error flag.
Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value
Bit 5: Mode fault.
Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred
Bit 6: Overrun flag.
Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred
Bit 7: Busy flag.
Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy
Bit 8: TI frame format error.
Allowed values:
0: NoError: No frame format error
1: Error: A frame format error occurred
Bits 9-10: FIFO reception level.
Allowed values:
0: Empty: Rx FIFO Empty
1: Quarter: Rx 1/4 FIFO
2: Half: Rx 1/2 FIFO
3: Full: Rx FIFO full
Bits 11-12: FIFO transmission level.
Allowed values:
0: Empty: Tx FIFO Empty
1: Quarter: Tx 1/4 FIFO
2: Half: Tx 1/2 FIFO
3: Full: Tx FIFO full
data register
Offset: 0xc, size: 16, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DR
rw |
|||||||||||||||
Direct 8-bit access to data register
Offset: 0xc, size: 8, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DR
rw |
|||||||||||||||
CRC polynomial register
Offset: 0x10, size: 16, reset: 0x00000007, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CRCPOLY
rw |
|||||||||||||||
RX CRC register
Offset: 0x14, size: 16, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
RxCRC
r |
|||||||||||||||
TX CRC register
Offset: 0x18, size: 16, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TxCRC
r |
|||||||||||||||
I2S configuration register
Offset: 0x1c, size: 16, reset: 0x00000000, access: read-write
8/8 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
I2SMOD
rw |
I2SE
rw |
I2SCFG
rw |
PCMSYNC
rw |
I2SSTD
rw |
CKPOL
rw |
DATLEN
rw |
CHLEN
rw |
||||||||
Bit 0: Channel length (number of bits per audio channel).
Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide
Bits 1-2: Data length to be transferred.
Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length
Bit 3: Steady state clock polarity.
Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level
Bits 4-5: I2S standard selection.
Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard
Bit 7: PCM frame synchronization.
Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation
Bits 8-9: I2S configuration mode.
Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive
Bit 10: I2S Enable.
Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled
Bit 11: I2S mode selection.
Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected
I2S prescaler register
Offset: 0x20, size: 16, reset: 0x00000010, access: read-write
3/3 fields covered.
Bits 0-7: I2S Linear prescaler.
Allowed values: 0x2-0xff
Bit 8: Odd factor for the prescaler.
Allowed values:
0: Even: Real divider value is I2SDIV * 2
1: Odd: Real divider value is (I2SDIV * 2) + 1
Bit 9: Master clock output enable.
Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled
0x40003000: Independent watchdog
7/7 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | KR | ||||||||||||||||||||||||||||||||
| 0x4 | PR | ||||||||||||||||||||||||||||||||
| 0x8 | RLR | ||||||||||||||||||||||||||||||||
| 0xc | SR | ||||||||||||||||||||||||||||||||
| 0x10 | WINR | ||||||||||||||||||||||||||||||||
Key register
Offset: 0x0, size: 32, reset: 0x00000000, access: write-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
KEY
w |
|||||||||||||||
Prescaler register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PR
rw |
|||||||||||||||
Reload register
Offset: 0x8, size: 32, reset: 0x00000FFF, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
RL
rw |
|||||||||||||||
Window register
Offset: 0x10, size: 32, reset: 0x00000FFF, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
WIN
rw |
|||||||||||||||
0xe000ed90: Memory protection unit
6/19 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | TYPER | ||||||||||||||||||||||||||||||||
| 0x4 | CTRL | ||||||||||||||||||||||||||||||||
| 0x8 | RNR | ||||||||||||||||||||||||||||||||
| 0xc | RBAR | ||||||||||||||||||||||||||||||||
| 0x10 | RASR | ||||||||||||||||||||||||||||||||
MPU type register
Offset: 0x0, size: 32, reset: 0x00000800, access: read-only
3/3 fields covered.
MPU control register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-only
3/3 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PRIVDEFENA
r |
HFNMIENA
r |
ENABLE
r |
|||||||||||||
MPU region number register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
REGION
rw |
|||||||||||||||
MPU region base address register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
MPU region attribute and size register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
0/9 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
XN
rw |
AP
rw |
TEX
rw |
S
rw |
C
rw |
B
rw |
||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SRD
rw |
SIZE
rw |
ENABLE
rw |
|||||||||||||
Bit 0: Region enable bit..
Bits 1-5: Size of the MPU protection region.
Bits 8-15: Subregion disable bits.
Bit 16: memory attribute.
Bit 17: memory attribute.
Bit 18: Shareable memory attribute.
Bits 19-21: memory attribute.
Bits 24-26: Access permission.
Bit 28: Instruction access disable bit.
0xe000e100: Nested Vectored Interrupt Controller
3/99 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | ISER0 | ||||||||||||||||||||||||||||||||
| 0x4 | ISER1 | ||||||||||||||||||||||||||||||||
| 0x8 | ISER2 | ||||||||||||||||||||||||||||||||
| 0x80 | ICER0 | ||||||||||||||||||||||||||||||||
| 0x84 | ICER1 | ||||||||||||||||||||||||||||||||
| 0x88 | ICER2 | ||||||||||||||||||||||||||||||||
| 0x100 | ISPR0 | ||||||||||||||||||||||||||||||||
| 0x104 | ISPR1 | ||||||||||||||||||||||||||||||||
| 0x108 | ISPR2 | ||||||||||||||||||||||||||||||||
| 0x180 | ICPR0 | ||||||||||||||||||||||||||||||||
| 0x184 | ICPR1 | ||||||||||||||||||||||||||||||||
| 0x188 | ICPR2 | ||||||||||||||||||||||||||||||||
| 0x200 | IABR0 | ||||||||||||||||||||||||||||||||
| 0x204 | IABR1 | ||||||||||||||||||||||||||||||||
| 0x208 | IABR2 | ||||||||||||||||||||||||||||||||
| 0x300 | IPR0 | ||||||||||||||||||||||||||||||||
| 0x304 | IPR1 | ||||||||||||||||||||||||||||||||
| 0x308 | IPR2 | ||||||||||||||||||||||||||||||||
| 0x30c | IPR3 | ||||||||||||||||||||||||||||||||
| 0x310 | IPR4 | ||||||||||||||||||||||||||||||||
| 0x314 | IPR5 | ||||||||||||||||||||||||||||||||
| 0x318 | IPR6 | ||||||||||||||||||||||||||||||||
| 0x31c | IPR7 | ||||||||||||||||||||||||||||||||
| 0x320 | IPR8 | ||||||||||||||||||||||||||||||||
| 0x324 | IPR9 | ||||||||||||||||||||||||||||||||
| 0x328 | IPR10 | ||||||||||||||||||||||||||||||||
| 0x32c | IPR11 | ||||||||||||||||||||||||||||||||
| 0x330 | IPR12 | ||||||||||||||||||||||||||||||||
| 0x334 | IPR13 | ||||||||||||||||||||||||||||||||
| 0x338 | IPR14 | ||||||||||||||||||||||||||||||||
| 0x33c | IPR15 | ||||||||||||||||||||||||||||||||
| 0x340 | IPR16 | ||||||||||||||||||||||||||||||||
| 0x344 | IPR17 | ||||||||||||||||||||||||||||||||
| 0x348 | IPR18 | ||||||||||||||||||||||||||||||||
| 0x34c | IPR19 | ||||||||||||||||||||||||||||||||
| 0x350 | IPR20 | ||||||||||||||||||||||||||||||||
Interrupt Set-Enable Register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Interrupt Set-Enable Register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Interrupt Set-Enable Register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Interrupt Clear-Enable Register
Offset: 0x80, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Interrupt Clear-Enable Register
Offset: 0x84, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Interrupt Clear-Enable Register
Offset: 0x88, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Interrupt Set-Pending Register
Offset: 0x100, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Interrupt Set-Pending Register
Offset: 0x104, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Interrupt Set-Pending Register
Offset: 0x108, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Interrupt Clear-Pending Register
Offset: 0x180, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Interrupt Clear-Pending Register
Offset: 0x184, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Interrupt Clear-Pending Register
Offset: 0x188, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Interrupt Active Bit Register
Offset: 0x200, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
Interrupt Active Bit Register
Offset: 0x204, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
Interrupt Active Bit Register
Offset: 0x208, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
Interrupt Priority Register
Offset: 0x300, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
Interrupt Priority Register
Offset: 0x304, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
Interrupt Priority Register
Offset: 0x308, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
Interrupt Priority Register
Offset: 0x30c, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
Interrupt Priority Register
Offset: 0x310, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
Interrupt Priority Register
Offset: 0x314, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
Interrupt Priority Register
Offset: 0x318, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
Interrupt Priority Register
Offset: 0x31c, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
Interrupt Priority Register
Offset: 0x320, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
Interrupt Priority Register
Offset: 0x324, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
Interrupt Priority Register
Offset: 0x328, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
Interrupt Priority Register
Offset: 0x32c, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
Interrupt Priority Register
Offset: 0x330, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
Interrupt Priority Register
Offset: 0x334, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
Interrupt Priority Register
Offset: 0x338, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
Interrupt Priority Register
Offset: 0x33c, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
Interrupt Priority Register
Offset: 0x340, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
Interrupt Priority Register
Offset: 0x344, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
Interrupt Priority Register
Offset: 0x348, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
Interrupt Priority Register
Offset: 0x34c, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
0xe000ef00: Nested vectored interrupt controller
0/1 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | STIR | ||||||||||||||||||||||||||||||||
Software trigger interrupt register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
INTID
rw |
|||||||||||||||
0x40007000: Power control
3/16 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR | ||||||||||||||||||||||||||||||||
| 0x4 | CSR | ||||||||||||||||||||||||||||||||
power control register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
0/10 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ENSD3
rw |
ENSD2
rw |
ENSD1
rw |
DBP
rw |
PLS
rw |
PVDE
rw |
CSBF
rw |
CWUF
rw |
PDDS
rw |
LPDS
rw |
||||||
Bit 0: Low-power deep sleep.
Bit 1: Power down deepsleep.
Bit 2: Clear wakeup flag.
Bit 3: Clear standby flag.
Bit 4: Power voltage detector enable.
Bits 5-7: PVD level selection.
Bit 8: Disable backup domain write protection.
Bit 9: ENable SD1 ADC.
Bit 10: ENable SD2 ADC.
Bit 11: ENable SD3 ADC.
0x40021000: Reset and clock control
152/152 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR | ||||||||||||||||||||||||||||||||
| 0x4 | CFGR | ||||||||||||||||||||||||||||||||
| 0x8 | CIR | ||||||||||||||||||||||||||||||||
| 0xc | APB2RSTR | ||||||||||||||||||||||||||||||||
| 0x10 | APB1RSTR | ||||||||||||||||||||||||||||||||
| 0x14 | AHBENR | ||||||||||||||||||||||||||||||||
| 0x18 | APB2ENR | ||||||||||||||||||||||||||||||||
| 0x1c | APB1ENR | ||||||||||||||||||||||||||||||||
| 0x20 | BDCR | ||||||||||||||||||||||||||||||||
| 0x24 | CSR | ||||||||||||||||||||||||||||||||
| 0x28 | AHBRSTR | ||||||||||||||||||||||||||||||||
| 0x2c | CFGR2 | ||||||||||||||||||||||||||||||||
| 0x30 | CFGR3 | ||||||||||||||||||||||||||||||||
Clock control register
Offset: 0x0, size: 32, reset: 0x00000083, access: Unspecified
10/10 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PLLRDY
r |
PLLON
rw |
CSSON
rw |
HSEBYP
rw |
HSERDY
r |
HSEON
rw |
||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
HSICAL
r |
HSITRIM
rw |
HSIRDY
r |
HSION
rw |
||||||||||||
Bit 0: Internal High Speed clock enable.
Allowed values:
0: Off: Clock Off
1: On: Clock On
Bit 1: Internal High Speed clock ready flag.
Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready
Bits 3-7: Internal High Speed clock trimming.
Allowed values: 0x0-0x1f
Bits 8-15: Internal High Speed clock Calibration.
Allowed values: 0x0-0xff
Bit 16: External High Speed clock enable.
Allowed values:
0: Off: Clock Off
1: On: Clock On
Bit 17: External High Speed clock ready flag.
Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready
Bit 18: External High Speed clock Bypass.
Allowed values:
0: NotBypassed: HSE crystal oscillator not bypassed
1: Bypassed: HSE crystal oscillator bypassed with external clock
Bit 19: Clock Security System enable.
Allowed values:
0: Off: Clock security system disabled (clock detector OFF)
1: On: Clock security system enable (clock detector ON if the HSE is ready, OFF if not)
Bit 24: PLL enable.
Allowed values:
0: Off: Clock Off
1: On: Clock On
Bit 25: PLL clock ready flag.
Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready
Clock configuration register (RCC_CFGR)
Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified
12/12 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SDPRE
rw |
MCO
rw |
USBPRE
rw |
PLLMUL
rw |
PLLXTPRE
rw |
PLLSRC
rw |
||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ADCPRE
rw |
PPRE2
rw |
PPRE1
rw |
HPRE
rw |
SWS
r |
SW
rw |
||||||||||
Bits 0-1: System clock Switch.
Allowed values:
0: HSI: HSI selected as system clock
1: HSE: HSE selected as system clock
2: PLL: PLL selected as system clock
Bits 2-3: System Clock Switch Status.
Allowed values:
0: HSI: HSI oscillator used as system clock
1: HSE: HSE oscillator used as system clock
2: PLL: PLL used as system clock
Bits 4-7: AHB prescaler.
Allowed values:
8: Div2: SYSCLK divided by 2
9: Div4: SYSCLK divided by 4
10: Div8: SYSCLK divided by 8
11: Div16: SYSCLK divided by 16
12: Div64: SYSCLK divided by 64
13: Div128: SYSCLK divided by 128
14: Div256: SYSCLK divided by 256
15: Div512: SYSCLK divided by 512
0 (+): Div1: SYSCLK not divided
Bits 8-10: APB Low speed prescaler (APB1).
Allowed values:
4: Div2: HCLK divided by 2
5: Div4: HCLK divided by 4
6: Div8: HCLK divided by 8
7: Div16: HCLK divided by 16
0 (+): Div1: HCLK not divided
Bits 11-13: APB high speed prescaler (APB2).
Allowed values:
4: Div2: HCLK divided by 2
5: Div4: HCLK divided by 4
6: Div8: HCLK divided by 8
7: Div16: HCLK divided by 16
0 (+): Div1: HCLK not divided
Bits 14-15: ADC prescaler.
Allowed values:
0: Div2: PCLK divided by 2
1: Div4: PCLK divided by 4
2: Div6: PCLK divided by 6
3: Div8: PCLK divided by 8
Bit 16: PLL entry clock source.
Allowed values:
0: HSI_Div2: HSI divided by 2 selected as PLL input clock
1: HSE_Div_PREDIV: HSE divided by PREDIV selected as PLL input clock
Bit 17: HSE divider for PLL entry.
Allowed values:
0: Div1: HSE clock not divided
1: Div2: HSE clock divided by 2
Bits 18-21: PLL Multiplication Factor.
Allowed values:
0: Mul2: PLL input clock x2
1: Mul3: PLL input clock x3
2: Mul4: PLL input clock x4
3: Mul5: PLL input clock x5
4: Mul6: PLL input clock x6
5: Mul7: PLL input clock x7
6: Mul8: PLL input clock x8
7: Mul9: PLL input clock x9
8: Mul10: PLL input clock x10
9: Mul11: PLL input clock x11
10: Mul12: PLL input clock x12
11: Mul13: PLL input clock x13
12: Mul14: PLL input clock x14
13: Mul15: PLL input clock x15
14: Mul16: PLL input clock x16
15: Mul16x: PLL input clock x16
Bit 22: USB prescaler.
Allowed values:
0: DIV1_5: PLL clock is divided by 1.5
1: DIV1: PLL clock is not divided
Bits 24-26: Microcontroller clock output.
Allowed values:
0: NoMCO: MCO output disabled, no clock on MCO
2: LSI: Internal low speed (LSI) oscillator clock selected
3: LSE: External low speed (LSE) oscillator clock selected
4: SYSCLK: System clock selected
5: HSI: Internal RC 8 MHz (HSI) oscillator clock selected
6: HSE: External 4-32 MHz (HSE) oscillator clock selected
7: PLL: PLL clock selected (divided by 1 or 2, depending en PLLNODIV)
Bits 27-31: SDADC prescaler.
Allowed values:
17: Div4: SYSCLK divided by 4
18: Div6: SYSCLK divided by 6
19: Div8: SYSCLK divided by 8
20: Div10: SYSCLK divided by 10
21: Div12: SYSCLK divided by 12
22: Div14: SYSCLK divided by 14
23: Div16: SYSCLK divided by 16
24: Div20: SYSCLK divided by 20
25: Div24: SYSCLK divided by 24
26: Div28: SYSCLK divided by 28
27: Div32: SYSCLK divided by 32
28: Div36: SYSCLK divided by 36
29: Div40: SYSCLK divided by 40
30: Div44: SYSCLK divided by 44
31: Div48: SYSCLK divided by 48
0 (+): Div2: SYSCLK divided by 2
Clock interrupt register (RCC_CIR)
Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified
17/17 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CSSC
w |
PLLRDYC
w |
HSERDYC
w |
HSIRDYC
w |
LSERDYC
w |
LSIRDYC
w |
||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PLLRDYIE
rw |
HSERDYIE
rw |
HSIRDYIE
rw |
LSERDYIE
rw |
LSIRDYIE
rw |
CSSF
r |
PLLRDYF
r |
HSERDYF
r |
HSIRDYF
r |
LSERDYF
r |
LSIRDYF
r |
|||||
Bit 0: LSI Ready Interrupt flag.
Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt
Bit 1: LSE Ready Interrupt flag.
Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt
Bit 2: HSI Ready Interrupt flag.
Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt
Bit 3: HSE Ready Interrupt flag.
Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt
Bit 4: PLL Ready Interrupt flag.
Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt
Bit 7: Clock Security System Interrupt flag.
Allowed values:
0: NotInterrupted: No clock security interrupt caused by HSE clock failure
1: Interrupted: Clock security interrupt caused by HSE clock failure
Bit 8: LSI Ready Interrupt Enable.
Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled
Bit 9: LSE Ready Interrupt Enable.
Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled
Bit 10: HSI Ready Interrupt Enable.
Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled
Bit 11: HSE Ready Interrupt Enable.
Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled
Bit 12: PLL Ready Interrupt Enable.
Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled
Bit 16: LSI Ready Interrupt Clear.
Allowed values:
1: Clear: Clear interrupt flag
Bit 17: LSE Ready Interrupt Clear.
Allowed values:
1: Clear: Clear interrupt flag
Bit 18: HSI Ready Interrupt Clear.
Allowed values:
1: Clear: Clear interrupt flag
Bit 19: HSE Ready Interrupt Clear.
Allowed values:
1: Clear: Clear interrupt flag
Bit 20: PLL Ready Interrupt Clear.
Allowed values:
1: Clear: Clear interrupt flag
Bit 23: Clock security system interrupt clear.
Allowed values:
1: Clear: Clear CSSF flag
APB2 peripheral reset register (RCC_APB2RSTR)
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
11/11 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SDADC3RST
rw |
SDADC2RST
rw |
SDADC1RST
rw |
TIM19RST
rw |
TIM17RST
rw |
TIM16RST
rw |
TIM15RST
rw |
|||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
USART1RST
rw |
SPI1RST
rw |
ADCRST
rw |
SYSCFGRST
rw |
||||||||||||
Bit 0: SYSCFG and COMP reset.
Allowed values:
1: Reset: Reset the selected module
Bit 9: ADC interface reset.
Allowed values:
1: Reset: Reset the selected module
Bit 12: SPI 1 reset.
Allowed values:
1: Reset: Reset the selected module
Bit 14: USART1 reset.
Allowed values:
1: Reset: Reset the selected module
Bit 16: TIM15 timer reset.
Allowed values:
1: Reset: Reset the selected module
Bit 17: TIM16 timer reset.
Allowed values:
1: Reset: Reset the selected module
Bit 18: TIM17 timer reset.
Allowed values:
1: Reset: Reset the selected module
Bit 19: TIM19 timer reset.
Allowed values:
1: Reset: Reset the selected module
Bit 24: SDADC1 (Sigma delta ADC 1) reset.
Allowed values:
1: Reset: Reset the selected module
Bit 25: SDADC2 (Sigma delta ADC 2) reset.
Allowed values:
1: Reset: Reset the selected module
Bit 26: SDADC3 (Sigma delta ADC 3) reset.
Allowed values:
1: Reset: Reset the selected module
APB1 peripheral reset register (RCC_APB1RSTR)
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
23/23 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CECRST
rw |
DAC1RST
rw |
PWRRST
rw |
DAC2RST
rw |
CANRST
rw |
USBRST
rw |
I2C2RST
rw |
I2C1RST
rw |
USART3RST
rw |
USART2RST
rw |
||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SPI3RST
rw |
SPI2RST
rw |
WWDGRST
rw |
TIM18RST
rw |
TIM14RST
rw |
TIM13RST
rw |
TIM12RST
rw |
TIM7RST
rw |
TIM6RST
rw |
TIM5RST
rw |
TIM4RST
rw |
TIM3RST
rw |
TIM2RST
rw |
|||
Bit 0: Timer 2 reset.
Allowed values:
1: Reset: Reset the selected module
Bit 1: Timer 3 reset.
Allowed values:
1: Reset: Reset the selected module
Bit 2: Timer 14 reset.
Allowed values:
1: Reset: Reset the selected module
Bit 3: Timer 5 reset.
Allowed values:
1: Reset: Reset the selected module
Bit 4: Timer 6 reset.
Allowed values:
1: Reset: Reset the selected module
Bit 5: Timer 7 reset.
Allowed values:
1: Reset: Reset the selected module
Bit 6: Timer 12 reset.
Allowed values:
1: Reset: Reset the selected module
Bit 7: Timer 13 reset.
Allowed values:
1: Reset: Reset the selected module
Bit 8: Timer 14 reset.
Allowed values:
1: Reset: Reset the selected module
Bit 9: Timer 18 reset.
Allowed values:
1: Reset: Reset the selected module
Bit 11: Window watchdog reset.
Allowed values:
1: Reset: Reset the selected module
Bit 14: SPI2 reset.
Allowed values:
1: Reset: Reset the selected module
Bit 15: SPI3 reset.
Allowed values:
1: Reset: Reset the selected module
Bit 17: USART 2 reset.
Allowed values:
1: Reset: Reset the selected module
Bit 18: USART3 reset.
Allowed values:
1: Reset: Reset the selected module
Bit 21: I2C1 reset.
Allowed values:
1: Reset: Reset the selected module
Bit 22: I2C2 reset.
Allowed values:
1: Reset: Reset the selected module
Bit 23: USB reset.
Allowed values:
1: Reset: Reset the selected module
Bit 25: CAN reset.
Allowed values:
1: Reset: Reset the selected module
Bit 26: DAC3 reset.
Allowed values:
1: Reset: Reset the selected module
Bit 28: Power interface reset.
Allowed values:
1: Reset: Reset the selected module
Bit 29: DAC interface reset.
Allowed values:
1: Reset: Reset the selected module
Bit 30: HDMI CEC reset.
Allowed values:
1: Reset: Reset the selected module
AHB Peripheral Clock enable register (RCC_AHBENR)
Offset: 0x14, size: 32, reset: 0x00000014, access: read-write
12/12 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TSCEN
rw |
IOPFEN
rw |
IOPEEN
rw |
IOPDEN
rw |
IOPCEN
rw |
IOPBEN
rw |
IOPAEN
rw |
|||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CRCEN
rw |
FLITFEN
rw |
SRAMEN
rw |
DMA2EN
rw |
DMA1EN
rw |
|||||||||||
Bit 0: DMA1 clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 1: DMA2 clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 2: SRAM interface clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 4: FLITF clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 6: CRC clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 17: I/O port A clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 18: I/O port B clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 19: I/O port C clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 20: I/O port D clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 21: I/O port E clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 22: I/O port F clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 24: Touch sensing controller clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
APB2 peripheral clock enable register (RCC_APB2ENR)
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
12/12 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SDADC3EN
rw |
SDADC2EN
rw |
SDADC1EN
rw |
DBGMCUEN
rw |
TIM19EN
rw |
TIM17EN
rw |
TIM16EN
rw |
TIM15EN
rw |
||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
USART1EN
rw |
SPI1EN
rw |
ADCEN
rw |
SYSCFGEN
rw |
||||||||||||
Bit 0: SYSCFG clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 9: ADC 1 interface clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 12: SPI 1 clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 14: USART1 clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 16: TIM15 timer clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 17: TIM16 timer clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 18: TIM17 timer clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 19: TIM19 timer clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 22: MCU debug module clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 24: SDADC1 (Sigma Delta ADC 1) clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 25: SDADC2 (Sigma Delta ADC 2) clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 26: SDADC3 (Sigma Delta ADC 3) clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
APB1 peripheral clock enable register (RCC_APB1ENR)
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
23/23 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CECEN
rw |
DAC1EN
rw |
PWREN
rw |
DAC2EN
rw |
CANEN
rw |
USBEN
rw |
I2C2EN
rw |
I2C1EN
rw |
USART3EN
rw |
USART2EN
rw |
||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SPI3EN
rw |
SPI2EN
rw |
WWDGEN
rw |
TIM18EN
rw |
TIM14EN
rw |
TIM13EN
rw |
TIM12EN
rw |
TIM7EN
rw |
TIM6EN
rw |
TIM5EN
rw |
TIM4EN
rw |
TIM3EN
rw |
TIM2EN
rw |
|||
Bit 0: Timer 2 clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 1: Timer 3 clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 2: Timer 4 clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 3: Timer 5 clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 4: Timer 6 clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 5: Timer 7 clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 6: Timer 12 clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 7: Timer 13 clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 8: Timer 14 clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 9: Timer 18 clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 11: Window watchdog clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 14: SPI 2 clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 15: SPI 3 clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 17: USART 2 clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 18: USART 3 clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 21: I2C 1 clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 22: I2C 2 clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 23: USB clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 25: CAN clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 26: DAC3 interface clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 28: Power interface clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 29: DAC interface clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Bit 30: HDMI CEC interface clock enable.
Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled
Backup domain control register (RCC_BDCR)
Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified
7/7 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BDRST
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RTCEN
rw |
RTCSEL
rw |
LSEDRV
rw |
LSEBYP
rw |
LSERDY
r |
LSEON
rw |
||||||||||
Bit 0: External Low Speed oscillator enable.
Allowed values:
0: Off: LSE oscillator Off
1: On: LSE oscillator On
Bit 1: External Low Speed oscillator ready.
Allowed values:
0: NotReady: LSE oscillator not ready
1: Ready: LSE oscillator ready
Bit 2: External Low Speed oscillator bypass.
Allowed values:
0: NotBypassed: LSE crystal oscillator not bypassed
1: Bypassed: LSE crystal oscillator bypassed with external clock
Bits 3-4: LSE oscillator drive capability.
Allowed values:
0: Low: Low drive capacity
1: MediumHigh: Medium-high drive capacity
2: MediumLow: Medium-low drive capacity
3: High: High drive capacity
Bits 8-9: RTC clock source selection.
Allowed values:
0: NoClock: No clock
1: LSE: LSE oscillator clock used as RTC clock
2: LSI: LSI oscillator clock used as RTC clock
3: HSE: HSE oscillator clock divided by a prescaler used as RTC clock
Bit 15: RTC clock enable.
Allowed values:
0: Disabled: RTC clock disabled
1: Enabled: RTC clock enabled
Bit 16: Backup domain software reset.
Allowed values:
0: Disabled: Reset not activated
1: Enabled: Reset the entire RTC domain
Control/status register (RCC_CSR)
Offset: 0x24, size: 32, reset: 0x0C000000, access: Unspecified
11/11 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
LPWRRSTF
rw |
WWDGRSTF
rw |
IWDGRSTF
rw |
SFTRSTF
rw |
PORRSTF
rw |
PINRSTF
rw |
OBLRSTF
rw |
RMVF
rw |
V18PWRRSTF
N/A |
|||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
LSIRDY
r |
LSION
rw |
||||||||||||||
Bit 0: Internal low speed oscillator enable.
Allowed values:
0: Off: LSI oscillator Off
1: On: LSI oscillator On
Bit 1: Internal low speed oscillator ready.
Allowed values:
0: NotReady: LSI oscillator not ready
1: Ready: LSI oscillator ready
Bit 23: Reset flag of the 1.8 V domain.
Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured
Bit 24: Remove reset flag.
Allowed values:
1: Clear: Clears the reset flag
Bit 25: Option byte loader reset flag.
Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured
Bit 26: PIN reset flag.
Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured
Bit 27: POR/PDR reset flag.
Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured
Bit 28: Software reset flag.
Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured
Bit 29: Independent watchdog reset flag.
Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured
Bit 30: Window watchdog reset flag.
Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured
Bit 31: Low-power reset flag.
Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured
AHB peripheral reset register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
7/7 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TSCRST
rw |
IOPFRST
rw |
IOPERST
rw |
IOPDRST
rw |
IOPCRST
rw |
IOPBRST
rw |
IOPARST
rw |
|||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bit 17: I/O port A reset.
Allowed values:
1: Reset: Reset the selected module
Bit 18: I/O port B reset.
Allowed values:
1: Reset: Reset the selected module
Bit 19: I/O port C reset.
Allowed values:
1: Reset: Reset the selected module
Bit 20: I/O port D reset.
Allowed values:
1: Reset: Reset the selected module
Bit 21: I/O port E reset.
Allowed values:
1: Reset: Reset the selected module
Bit 22: I/O port F reset.
Allowed values:
1: Reset: Reset the selected module
Bit 24: Touch sensing controller reset.
Allowed values:
1: Reset: Reset the selected module
Clock configuration register 2
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PREDIV
rw |
|||||||||||||||
Bits 0-3: PREDIV division factor.
Allowed values:
0: Div1: PREDIV input clock not divided
1: Div2: PREDIV input clock divided by 2
2: Div3: PREDIV input clock divided by 3
3: Div4: PREDIV input clock divided by 4
4: Div5: PREDIV input clock divided by 5
5: Div6: PREDIV input clock divided by 6
6: Div7: PREDIV input clock divided by 7
7: Div8: PREDIV input clock divided by 8
8: Div9: PREDIV input clock divided by 9
9: Div10: PREDIV input clock divided by 10
10: Div11: PREDIV input clock divided by 11
11: Div12: PREDIV input clock divided by 12
12: Div13: PREDIV input clock divided by 13
13: Div14: PREDIV input clock divided by 14
14: Div15: PREDIV input clock divided by 15
15: Div16: PREDIV input clock divided by 16
Clock configuration register 3
Offset: 0x30, size: 32, reset: 0x00000000, access: read-write
6/6 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
USART3SW
rw |
USART2SW
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CECSW
rw |
I2C2SW
rw |
I2C1SW
rw |
USART1SW
rw |
||||||||||||
Bits 0-1: USART1 clock source selection.
Allowed values:
0: PCLK: PCLK selected as USART clock source
1: SYSCLK: SYSCLK selected as USART clock source
2: LSE: LSE selected as USART clock source
3: HSI: HSI selected as USART clock source
Bit 4: I2C1 clock source selection.
Allowed values:
0: HSI: HSI clock selected as I2C clock source
1: SYSCLK: SYSCLK clock selected as I2C clock source
Bit 5: I2C2 clock source selection.
Allowed values:
0: HSI: HSI clock selected as I2C clock source
1: SYSCLK: SYSCLK clock selected as I2C clock source
Bit 6: HDMI CEC clock source selection.
Allowed values:
0: HSI_Div244: HSI clock divided by 244 selected as CEC clock source
1: LSE: LSE clock selected as CEC clock source
Bits 16-17: USART2 clock source selection.
Allowed values:
0: PCLK: PCLK selected as USART clock source
1: SYSCLK: SYSCLK selected as USART clock source
2: LSE: LSE selected as USART clock source
3: HSI: HSI selected as USART clock source
Bits 18-19: USART3 clock source selection.
Allowed values:
0: PCLK: PCLK selected as USART clock source
1: SYSCLK: SYSCLK selected as USART clock source
2: LSE: LSE selected as USART clock source
3: HSI: HSI selected as USART clock source
0x40002800: Real-time clock
157/157 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | TR | ||||||||||||||||||||||||||||||||
| 0x4 | DR | ||||||||||||||||||||||||||||||||
| 0x8 | CR | ||||||||||||||||||||||||||||||||
| 0xc | ISR | ||||||||||||||||||||||||||||||||
| 0x10 | PRER | ||||||||||||||||||||||||||||||||
| 0x14 | WUTR | ||||||||||||||||||||||||||||||||
| 0x1c | ALRM[A]R | ||||||||||||||||||||||||||||||||
| 0x20 | ALRM[B]R | ||||||||||||||||||||||||||||||||
| 0x24 | WPR | ||||||||||||||||||||||||||||||||
| 0x28 | SSR | ||||||||||||||||||||||||||||||||
| 0x2c | SHIFTR | ||||||||||||||||||||||||||||||||
| 0x30 | TSTR | ||||||||||||||||||||||||||||||||
| 0x34 | TSDR | ||||||||||||||||||||||||||||||||
| 0x38 | TSSSR | ||||||||||||||||||||||||||||||||
| 0x3c | CALR | ||||||||||||||||||||||||||||||||
| 0x40 | TAFCR | ||||||||||||||||||||||||||||||||
| 0x44 | ALRM[A]SSR | ||||||||||||||||||||||||||||||||
| 0x48 | ALRM[B]SSR | ||||||||||||||||||||||||||||||||
| 0x50 | BKP[0]R | ||||||||||||||||||||||||||||||||
| 0x54 | BKP[1]R | ||||||||||||||||||||||||||||||||
| 0x58 | BKP[2]R | ||||||||||||||||||||||||||||||||
| 0x5c | BKP[3]R | ||||||||||||||||||||||||||||||||
| 0x60 | BKP[4]R | ||||||||||||||||||||||||||||||||
| 0x64 | BKP[5]R | ||||||||||||||||||||||||||||||||
| 0x68 | BKP[6]R | ||||||||||||||||||||||||||||||||
| 0x6c | BKP[7]R | ||||||||||||||||||||||||||||||||
| 0x70 | BKP[8]R | ||||||||||||||||||||||||||||||||
| 0x74 | BKP[9]R | ||||||||||||||||||||||||||||||||
| 0x78 | BKP[10]R | ||||||||||||||||||||||||||||||||
| 0x7c | BKP[11]R | ||||||||||||||||||||||||||||||||
| 0x80 | BKP[12]R | ||||||||||||||||||||||||||||||||
| 0x84 | BKP[13]R | ||||||||||||||||||||||||||||||||
| 0x88 | BKP[14]R | ||||||||||||||||||||||||||||||||
| 0x8c | BKP[15]R | ||||||||||||||||||||||||||||||||
| 0x90 | BKP[16]R | ||||||||||||||||||||||||||||||||
| 0x94 | BKP[17]R | ||||||||||||||||||||||||||||||||
| 0x98 | BKP[18]R | ||||||||||||||||||||||||||||||||
| 0x9c | BKP[19]R | ||||||||||||||||||||||||||||||||
| 0xa0 | BKP[20]R | ||||||||||||||||||||||||||||||||
| 0xa4 | BKP[21]R | ||||||||||||||||||||||||||||||||
| 0xa8 | BKP[22]R | ||||||||||||||||||||||||||||||||
| 0xac | BKP[23]R | ||||||||||||||||||||||||||||||||
| 0xb0 | BKP[24]R | ||||||||||||||||||||||||||||||||
| 0xb4 | BKP[25]R | ||||||||||||||||||||||||||||||||
| 0xb8 | BKP[26]R | ||||||||||||||||||||||||||||||||
| 0xbc | BKP[27]R | ||||||||||||||||||||||||||||||||
| 0xc0 | BKP[28]R | ||||||||||||||||||||||||||||||||
| 0xc4 | BKP[29]R | ||||||||||||||||||||||||||||||||
| 0xc8 | BKP[30]R | ||||||||||||||||||||||||||||||||
| 0xcc | BKP[31]R | ||||||||||||||||||||||||||||||||
time register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
7/7 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PM
rw |
HT
rw |
HU
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MNT
rw |
MNU
rw |
ST
rw |
SU
rw |
||||||||||||
Bits 0-3: Second units in BCD format.
Allowed values: 0x0-0xf
Bits 4-6: Second tens in BCD format.
Allowed values: 0x0-0x7
Bits 8-11: Minute units in BCD format.
Allowed values: 0x0-0xf
Bits 12-14: Minute tens in BCD format.
Allowed values: 0x0-0x7
Bits 16-19: Hour units in BCD format.
Allowed values: 0x0-0xf
Bits 20-21: Hour tens in BCD format.
Allowed values: 0x0-0x3
Bit 22: AM/PM notation.
Allowed values:
0: AM: AM or 24-hour format
1: PM: PM
date register
Offset: 0x4, size: 32, reset: 0x00002101, access: read-write
7/7 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
YT
rw |
YU
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
WDU
rw |
MT
rw |
MU
rw |
DT
rw |
DU
rw |
|||||||||||
Bits 0-3: Date units in BCD format.
Allowed values: 0x0-0xf
Bits 4-5: Date tens in BCD format.
Allowed values: 0x0-0x3
Bits 8-11: Month units in BCD format.
Allowed values: 0x0-0xf
Bit 12: Month tens in BCD format.
Allowed values:
0: Zero: Month tens is 0
1: One: Month tens is 1
Bits 13-15: Week day units.
Allowed values: 0x1-0x7
Bits 16-19: Year units in BCD format.
Allowed values: 0x0-0xf
Bits 20-23: Year tens in BCD format.
Allowed values: 0x0-0xf
control register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
20/20 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
COE
rw |
OSEL
rw |
POL
rw |
COSEL
rw |
BKP
rw |
SUB1H
rw |
ADD1H
rw |
|||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TSIE
rw |
WUTIE
rw |
ALRBIE
rw |
ALRAIE
rw |
TSE
rw |
WUTE
rw |
ALRBE
rw |
ALRAE
rw |
FMT
rw |
BYPSHAD
rw |
REFCKON
rw |
TSEDGE
rw |
WUCKSEL
rw |
|||
Bits 0-2: Wakeup clock selection.
Allowed values:
0: Div16: RTC/16 clock is selected
1: Div8: RTC/8 clock is selected
2: Div4: RTC/4 clock is selected
3: Div2: RTC/2 clock is selected
4: ClockSpare: ck_spre (usually 1 Hz) clock is selected
6: ClockSpareWithOffset: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value
Bit 3: Time-stamp event active edge.
Allowed values:
0: RisingEdge: RTC_TS input rising edge generates a time-stamp event
1: FallingEdge: RTC_TS input falling edge generates a time-stamp event
Bit 4: Reference clock detection enable (50 or 60 Hz).
Allowed values:
0: Disabled: RTC_REFIN detection disabled
1: Enabled: RTC_REFIN detection enabled
Bit 5: Bypass the shadow registers.
Allowed values:
0: ShadowReg: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles
1: BypassShadowReg: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters
Bit 6: Hour format.
Allowed values:
0: Twenty_Four_Hour: 24 hour/day format
1: AM_PM: AM/PM hour format
Bit 8: Alarm A enable.
Allowed values:
0: Disabled: Alarm A disabled
1: Enabled: Alarm A enabled
Bit 9: Alarm B enable.
Allowed values:
0: Disabled: Alarm B disabled
1: Enabled: Alarm B enabled
Bit 10: Wakeup timer enable.
Allowed values:
0: Disabled: Wakeup timer disabled
1: Enabled: Wakeup timer enabled
Bit 11: Time stamp enable.
Allowed values:
0: Disabled: Timestamp disabled
1: Enabled: Timestamp enabled
Bit 12: Alarm A interrupt enable.
Allowed values:
0: Disabled: Alarm A interrupt disabled
1: Enabled: Alarm A interrupt enabled
Bit 13: Alarm B interrupt enable.
Allowed values:
0: Disabled: Alarm B Interrupt disabled
1: Enabled: Alarm B Interrupt enabled
Bit 14: Wakeup timer interrupt enable.
Allowed values:
0: Disabled: Wakeup timer interrupt disabled
1: Enabled: Wakeup timer interrupt enabled
Bit 15: Time-stamp interrupt enable.
Allowed values:
0: Disabled: Time-stamp Interrupt disabled
1: Enabled: Time-stamp Interrupt enabled
Bit 16: Add 1 hour (summer time change).
Allowed values:
1: Add1: Adds 1 hour to the current time. This can be used for summer time change outside initialization mode
Bit 17: Subtract 1 hour (winter time change).
Allowed values:
1: Sub1: Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode
Bit 18: Backup.
Allowed values:
0: DST_Not_Changed: Daylight Saving Time change has not been performed
1: DST_Changed: Daylight Saving Time change has been performed
Bit 19: Calibration output selection.
Allowed values:
0: CalFreq_512Hz: Calibration output is 512 Hz (with default prescaler setting)
1: CalFreq_1Hz: Calibration output is 1 Hz (with default prescaler setting)
Bit 20: Output polarity.
Allowed values:
0: High: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])
1: Low: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])
Bits 21-22: Output selection.
Allowed values:
0: Disabled: Output disabled
1: AlarmA: Alarm A output enabled
2: AlarmB: Alarm B output enabled
3: Wakeup: Wakeup output enabled
Bit 23: Calibration output enable.
Allowed values:
0: Disabled: Calibration output disabled
1: Enabled: Calibration output enabled
initialization and status register
Offset: 0xc, size: 32, reset: 0x00000007, access: Unspecified
17/17 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
RECALPF
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TAMP3F
rw |
TAMP2F
rw |
TAMP1F
rw |
TSOVF
rw |
TSF
rw |
WUTF
rw |
ALRBF
rw |
ALRAF
rw |
INIT
rw |
INITF
r |
RSF
rw |
INITS
r |
SHPF
rw |
WUTWF
r |
ALRBWF
r |
ALRAWF
r |
Bit 0: Alarm A write flag.
Allowed values:
0: UpdateNotAllowed: Alarm update not allowed
1: UpdateAllowed: Alarm update allowed
Bit 1: Alarm B write flag.
Allowed values:
0: UpdateNotAllowed: Alarm update not allowed
1: UpdateAllowed: Alarm update allowed
Bit 2: Wakeup timer write flag.
Allowed values:
0: UpdateNotAllowed: Wakeup timer configuration update not allowed
1: UpdateAllowed: Wakeup timer configuration update allowed
Bit 3: Shift operation pending.
Allowed values:
0: NoShiftPending: No shift operation is pending
1: ShiftPending: A shift operation is pending
Bit 4: Initialization status flag.
Allowed values:
0: NotInitalized: Calendar has not been initialized
1: Initalized: Calendar has been initialized
Bit 5: Registers synchronization flag.
Allowed values:
0: NotSynced: Calendar shadow registers not yet synchronized
1: Synced: Calendar shadow registers synchronized
Bit 6: Initialization flag.
Allowed values:
0: NotAllowed: Calendar registers update is not allowed
1: Allowed: Calendar registers update is allowed
Bit 7: Initialization mode.
Allowed values:
0: FreeRunningMode: Free running mode
1: InitMode: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.
Bit 8: Alarm A flag.
Allowed values:
1: Match: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR)
Bit 9: Alarm B flag.
Allowed values:
1: Match: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR)
Bit 10: Wakeup timer flag.
Allowed values:
1: Zero: This flag is set by hardware when the wakeup auto-reload counter reaches 0
Bit 11: Time-stamp flag.
Allowed values:
1: TimestampEvent: This flag is set by hardware when a time-stamp event occurs
Bit 12: Time-stamp overflow flag.
Allowed values:
1: Overflow: This flag is set by hardware when a time-stamp event occurs while TSF is already set
Bit 13: Tamper detection flag.
Allowed values:
1: Tampered: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input
Bit 14: RTC_TAMP2 detection flag.
Allowed values:
1: Tampered: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input
Bit 15: RTC_TAMP3 detection flag.
Allowed values:
1: Tampered: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input
Bit 16: Recalibration pending Flag.
Allowed values:
1: Pending: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0
prescaler register
Offset: 0x10, size: 32, reset: 0x007F00FF, access: read-write
2/2 fields covered.
wakeup timer register
Offset: 0x14, size: 32, reset: 0x0000FFFF, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
WUT
rw |
|||||||||||||||
Alarm A register
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
14/14 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MSK4
rw |
WDSEL
rw |
DT
rw |
DU
rw |
MSK3
rw |
PM
rw |
HT
rw |
HU
rw |
||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MSK2
rw |
MNT
rw |
MNU
rw |
MSK1
rw |
ST
rw |
SU
rw |
||||||||||
Bits 0-3: Second units in BCD format.
Allowed values: 0x0-0xf
Bits 4-6: Second tens in BCD format.
Allowed values: 0x0-0x7
Bit 7: Alarm seconds mask.
Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison
Bits 8-11: Minute units in BCD format.
Allowed values: 0x0-0xf
Bits 12-14: Minute tens in BCD format.
Allowed values: 0x0-0x7
Bit 15: Alarm minutes mask.
Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison
Bits 16-19: Hour units in BCD format.
Allowed values: 0x0-0xf
Bits 20-21: Hour tens in BCD format.
Allowed values: 0x0-0x3
Bit 22: AM/PM notation.
Allowed values:
0: AM: AM or 24-hour format
1: PM: PM
Bit 23: Alarm hours mask.
Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison
Bits 24-27: Date units or day in BCD format.
Allowed values: 0x0-0xf
Bits 28-29: Date tens in BCD format.
Allowed values: 0x0-0x3
Bit 30: Week day selection.
Allowed values:
0: DateUnits: DU[3:0] represents the date units
1: WeekDay: DU[3:0] represents the week day. DT[1:0] is don’t care.
Bit 31: Alarm date mask.
Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison
Alarm B register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
14/14 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MSK4
rw |
WDSEL
rw |
DT
rw |
DU
rw |
MSK3
rw |
PM
rw |
HT
rw |
HU
rw |
||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MSK2
rw |
MNT
rw |
MNU
rw |
MSK1
rw |
ST
rw |
SU
rw |
||||||||||
Bits 0-3: Second units in BCD format.
Allowed values: 0x0-0xf
Bits 4-6: Second tens in BCD format.
Allowed values: 0x0-0x7
Bit 7: Alarm seconds mask.
Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison
Bits 8-11: Minute units in BCD format.
Allowed values: 0x0-0xf
Bits 12-14: Minute tens in BCD format.
Allowed values: 0x0-0x7
Bit 15: Alarm minutes mask.
Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison
Bits 16-19: Hour units in BCD format.
Allowed values: 0x0-0xf
Bits 20-21: Hour tens in BCD format.
Allowed values: 0x0-0x3
Bit 22: AM/PM notation.
Allowed values:
0: AM: AM or 24-hour format
1: PM: PM
Bit 23: Alarm hours mask.
Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison
Bits 24-27: Date units or day in BCD format.
Allowed values: 0x0-0xf
Bits 28-29: Date tens in BCD format.
Allowed values: 0x0-0x3
Bit 30: Week day selection.
Allowed values:
0: DateUnits: DU[3:0] represents the date units
1: WeekDay: DU[3:0] represents the week day. DT[1:0] is don’t care.
Bit 31: Alarm date mask.
Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison
write protection register
Offset: 0x24, size: 32, reset: 0x00000000, access: write-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
KEY
w |
|||||||||||||||
sub second register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SS
r |
|||||||||||||||
shift control register
Offset: 0x2c, size: 32, reset: 0x00000000, access: write-only
2/2 fields covered.
time stamp time register
Offset: 0x30, size: 32, reset: 0x00000000, access: read-write
7/7 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PM
rw |
HT
rw |
HU
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MNT
rw |
MNU
rw |
ST
rw |
SU
rw |
||||||||||||
Bits 0-3: Second units in BCD format.
Allowed values: 0x0-0xf
Bits 4-6: Second tens in BCD format.
Allowed values: 0x0-0x7
Bits 8-11: Minute units in BCD format.
Allowed values: 0x0-0xf
Bits 12-14: Minute tens in BCD format.
Allowed values: 0x0-0x7
Bits 16-19: Hour units in BCD format.
Allowed values: 0x0-0xf
Bits 20-21: Hour tens in BCD format.
Allowed values: 0x0-0x3
Bit 22: AM/PM notation.
Allowed values:
0: AM: AM or 24-hour format
1: PM: PM
time stamp date register
Offset: 0x34, size: 32, reset: 0x00002101, access: read-write
7/7 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
YT
rw |
YU
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
WDU
rw |
MT
rw |
MU
rw |
DT
rw |
DU
rw |
|||||||||||
Bits 0-3: Date units in BCD format.
Allowed values: 0x0-0xf
Bits 4-5: Date tens in BCD format.
Allowed values: 0x0-0x3
Bits 8-11: Month units in BCD format.
Allowed values: 0x0-0xf
Bit 12: Month tens in BCD format.
Allowed values:
0: Zero: Month tens is 0
1: One: Month tens is 1
Bits 13-15: Week day units.
Allowed values: 0x1-0x7
Bits 16-19: Year units in BCD format.
Allowed values: 0x0-0xf
Bits 20-23: Year tens in BCD format.
Allowed values: 0x0-0xf
timestamp sub second register
Offset: 0x38, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SS
r |
|||||||||||||||
calibration register
Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write
4/4 fields covered.
Bits 0-8: Calibration minus.
Allowed values: 0x0-0x1ff
Bit 13: Use a 16-second calibration cycle period.
Allowed values:
1: Sixteen_Second: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1
Bit 14: Use an 8-second calibration cycle period.
Allowed values:
1: Eight_Second: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected
Bit 15: Increase frequency of RTC by 488.5 ppm.
Allowed values:
0: NoChange: No RTCCLK pulses are added
1: IncreaseFreq: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm)
tamper and alternate function configuration register
Offset: 0x40, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PC15MODE
rw |
PC15VALUE
rw |
PC14MODE
rw |
PC14VALUE
rw |
PC13MODE
rw |
PC13VALUE
rw |
||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TAMPPUDIS
rw |
TAMPPRCH
rw |
TAMPFLT
rw |
TAMPFREQ
rw |
TAMPTS
rw |
TAMP2TRG
rw |
TAMP2E
rw |
TAMPIE
rw |
TAMP1TRG
rw |
TAMP1E
rw |
||||||
Bit 0: Tamper 1 detection enable.
Allowed values:
0: Disabled: RTC_TAMPx input detection disabled
1: Enabled: RTC_TAMPx input detection enabled
Bit 1: Active level for tamper 1.
Allowed values:
0: RisingEdge: If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event.
1: FallingEdge: If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event
Bit 2: Tamper interrupt enable.
Allowed values:
0: Disabled: Tamper interrupt disabled
1: Enabled: Tamper interrupt enabled
Bit 3: Tamper 2 detection enable.
Allowed values:
0: Disabled: RTC_TAMPx input detection disabled
1: Enabled: RTC_TAMPx input detection enabled
Bit 4: Active level for tamper 2.
Allowed values:
0: RisingEdge: If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event.
1: FallingEdge: If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event
Bit 7: Activate timestamp on tamper detection event.
Allowed values:
0: NoSave: Tamper detection event does not cause a timestamp to be saved
1: Save: Save timestamp on tamper detection event
Bits 8-10: Tamper sampling frequency.
Allowed values:
0: Div32768: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz)
1: Div16384: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz)
2: Div8192: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz)
3: Div4096: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz)
4: Div2048: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz)
5: Div1024: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz)
6: Div512: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz)
7: Div256: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)
Bits 11-12: Tamper filter count.
Allowed values:
0: Immediate: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input)
1: Samples2: Tamper event is activated after 2 consecutive samples at the active level
2: Samples4: Tamper event is activated after 4 consecutive samples at the active level
3: Samples8: Tamper event is activated after 8 consecutive samples at the active level
Bits 13-14: Tamper precharge duration.
Allowed values:
0: Cycles1: 1 RTCCLK cycle
1: Cycles2: 2 RTCCLK cycles
2: Cycles4: 4 RTCCLK cycles
3: Cycles8: 8 RTCCLK cycles
Bit 15: TAMPER pull-up disable.
Allowed values:
0: Enabled: Precharge RTC_TAMPx pins before sampling (enable internal pull-up)
1: Disabled: Disable precharge of RTC_TAMPx pins
Bit 18: PC13 value.
Allowed values:
0: Low: If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic low
1: High: If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic high
Bit 19: PC13 mode.
Allowed values:
0: Floating: PCx is controlled by the GPIO configuration Register. Consequently PC15 is floating in Standby mode
1: PushPull: PCx is forced to push-pull output if LSE is disabled
Bit 20: PC14 value.
Allowed values:
0: Low: If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic low
1: High: If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic high
Bit 21: PC 14 mode.
Allowed values:
0: Floating: PCx is controlled by the GPIO configuration Register. Consequently PC15 is floating in Standby mode
1: PushPull: PCx is forced to push-pull output if LSE is disabled
Bit 22: PC15 value.
Allowed values:
0: Low: If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic low
1: High: If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic high
Bit 23: PC15 mode.
Allowed values:
0: Floating: PCx is controlled by the GPIO configuration Register. Consequently PC15 is floating in Standby mode
1: PushPull: PCx is forced to push-pull output if LSE is disabled
Alarm A sub-second register
Offset: 0x44, size: 32, reset: 0x00000000, access: read-write
2/2 fields covered.
Alarm B sub-second register
Offset: 0x48, size: 32, reset: 0x00000000, access: read-write
2/2 fields covered.
backup register
Offset: 0x50, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0x54, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0x58, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0x60, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0x64, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0x68, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0x70, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0x74, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0x78, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0x80, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0x84, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0x88, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0x90, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0x94, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0x98, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0xac, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0xb8, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0xbc, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
0xe000ed00: System control block
5/74 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CPUID | ||||||||||||||||||||||||||||||||
| 0x4 | ICSR | ||||||||||||||||||||||||||||||||
| 0x8 | VTOR | ||||||||||||||||||||||||||||||||
| 0xc | AIRCR | ||||||||||||||||||||||||||||||||
| 0x10 | SCR | ||||||||||||||||||||||||||||||||
| 0x14 | CCR | ||||||||||||||||||||||||||||||||
| 0x18 | SHPR1 | ||||||||||||||||||||||||||||||||
| 0x1c | SHPR2 | ||||||||||||||||||||||||||||||||
| 0x20 | SHPR3 | ||||||||||||||||||||||||||||||||
| 0x24 | SHCRS | ||||||||||||||||||||||||||||||||
| 0x28 | CFSR_UFSR_BFSR_MMFSR | ||||||||||||||||||||||||||||||||
| 0x2c | HFSR | ||||||||||||||||||||||||||||||||
| 0x34 | MMFAR | ||||||||||||||||||||||||||||||||
| 0x38 | BFAR | ||||||||||||||||||||||||||||||||
| 0x3c | AFSR | ||||||||||||||||||||||||||||||||
CPUID base register
Offset: 0x0, size: 32, reset: 0x410FC241, access: read-only
5/5 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
Implementer
r |
Variant
r |
Constant
r |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PartNo
r |
Revision
r |
||||||||||||||
Interrupt control and state register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
0/9 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
NMIPENDSET
rw |
PENDSVSET
rw |
PENDSVCLR
rw |
PENDSTSET
rw |
PENDSTCLR
rw |
ISRPENDING
rw |
VECTPENDING
rw |
|||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
VECTPENDING
rw |
RETTOBASE
rw |
VECTACTIVE
rw |
|||||||||||||
Bits 0-8: Active vector.
Bit 11: Return to base level.
Bits 12-18: Pending vector.
Bit 22: Interrupt pending flag.
Bit 25: SysTick exception clear-pending bit.
Bit 26: SysTick exception set-pending bit.
Bit 27: PendSV clear-pending bit.
Bit 28: PendSV set-pending bit.
Bit 31: NMI set-pending bit..
Vector table offset register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Application interrupt and reset control register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
0/6 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
VECTKEYSTAT
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ENDIANESS
rw |
PRIGROUP
rw |
SYSRESETREQ
rw |
VECTCLRACTIVE
rw |
VECTRESET
rw |
|||||||||||
System control register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SEVEONPEND
rw |
SLEEPDEEP
rw |
SLEEPONEXIT
rw |
|||||||||||||
Configuration and control register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
0/6 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
STKALIGN
rw |
BFHFNMIGN
rw |
DIV_0_TRP
rw |
UNALIGN__TRP
rw |
USERSETMPEND
rw |
NONBASETHRDENA
rw |
||||||||||
System handler priority registers
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
System handler priority registers
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PRI_11
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
System handler priority registers
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
System handler control and state register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
0/14 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
USGFAULTENA
rw |
BUSFAULTENA
rw |
MEMFAULTENA
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SVCALLPENDED
rw |
BUSFAULTPENDED
rw |
MEMFAULTPENDED
rw |
USGFAULTPENDED
rw |
SYSTICKACT
rw |
PENDSVACT
rw |
MONITORACT
rw |
SVCALLACT
rw |
USGFAULTACT
rw |
BUSFAULTACT
rw |
MEMFAULTACT
rw |
|||||
Bit 0: Memory management fault exception active bit.
Bit 1: Bus fault exception active bit.
Bit 3: Usage fault exception active bit.
Bit 7: SVC call active bit.
Bit 8: Debug monitor active bit.
Bit 10: PendSV exception active bit.
Bit 11: SysTick exception active bit.
Bit 12: Usage fault exception pending bit.
Bit 13: Memory management fault exception pending bit.
Bit 14: Bus fault exception pending bit.
Bit 15: SVC call pending bit.
Bit 16: Memory management fault enable bit.
Bit 17: Bus fault enable bit.
Bit 18: Usage fault enable bit.
Configurable fault status register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
0/18 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DIVBYZERO
rw |
UNALIGNED
rw |
NOCP
rw |
INVPC
rw |
INVSTATE
rw |
UNDEFINSTR
rw |
||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BFARVALID
rw |
LSPERR
rw |
STKERR
rw |
UNSTKERR
rw |
IMPRECISERR
rw |
PRECISERR
rw |
IBUSERR
rw |
MMARVALID
rw |
MLSPERR
rw |
MSTKERR
rw |
MUNSTKERR
rw |
IACCVIOL
rw |
||||
Bit 1: Instruction access violation flag.
Bit 3: Memory manager fault on unstacking for a return from exception.
Bit 4: Memory manager fault on stacking for exception entry..
Bit 5: MLSPERR.
Bit 7: Memory Management Fault Address Register (MMAR) valid flag.
Bit 8: Instruction bus error.
Bit 9: Precise data bus error.
Bit 10: Imprecise data bus error.
Bit 11: Bus fault on unstacking for a return from exception.
Bit 12: Bus fault on stacking for exception entry.
Bit 13: Bus fault on floating-point lazy state preservation.
Bit 15: Bus Fault Address Register (BFAR) valid flag.
Bit 16: Undefined instruction usage fault.
Bit 17: Invalid state usage fault.
Bit 18: Invalid PC load usage fault.
Bit 19: No coprocessor usage fault..
Bit 24: Unaligned access usage fault.
Bit 25: Divide by zero usage fault.
Hard fault status register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Memory management fault address register
Offset: 0x34, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
0xe000e008: System control block ACTLR
0/5 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | ACTRL |
Auxiliary control register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
0/5 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DISOOFP
rw |
DISFPCA
rw |
DISFOLD
rw |
DISDEFWBUF
rw |
DISMCYCINT
rw |
|||||||||||
0x40016000: Sigma-delta analog-to-digital converter
21/72 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | ISR | ||||||||||||||||||||||||||||||||
| 0xc | CLRISR | ||||||||||||||||||||||||||||||||
| 0x14 | JCHGR | ||||||||||||||||||||||||||||||||
| 0x20 | CONF0R | ||||||||||||||||||||||||||||||||
| 0x24 | CONF1R | ||||||||||||||||||||||||||||||||
| 0x28 | CONF2R | ||||||||||||||||||||||||||||||||
| 0x40 | CONFCHR1 | ||||||||||||||||||||||||||||||||
| 0x44 | CONFCHR2 | ||||||||||||||||||||||||||||||||
| 0x60 | JDATAR | ||||||||||||||||||||||||||||||||
| 0x64 | RDATAR | ||||||||||||||||||||||||||||||||
| 0x70 | JDATA12R | ||||||||||||||||||||||||||||||||
| 0x74 | RDATA12R | ||||||||||||||||||||||||||||||||
| 0x78 | JDATA13R | ||||||||||||||||||||||||||||||||
| 0x7c | RDATA13R | ||||||||||||||||||||||||||||||||
control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
0/14 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
INIT
rw |
RDMAEN
rw |
JDMAEN
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RSYNC
rw |
JSYNC
rw |
PDI
rw |
SBI
rw |
SLOWCK
rw |
REFV
rw |
ROVRIE
rw |
REOCIE
rw |
JOVRIE
rw |
JEOCIE
rw |
EOCALIE
rw |
|||||
Bit 0: End of calibration interrupt enable.
Bit 1: Injected end of conversion interrupt enable.
Bit 2: Injected data overrun interrupt enable.
Bit 3: Regular end of conversion interrupt enable.
Bit 4: Regular data overrun interrupt enable.
Bits 8-9: Reference voltage selection.
Bit 10: Slow clock mode enable.
Bit 11: Enter Standby mode when idle.
Bit 12: Enter power down mode when idle.
Bit 14: Launch a injected conversion synchronously with SDADC1.
Bit 15: Launch regular conversion synchronously with SDADC1.
Bit 16: DMA channel enabled to read data for the injected channel group.
Bit 17: DMA channel enabled to read data for the regular channel.
Bit 31: Initialization mode request.
control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
0/12 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
FAST
rw |
RSWSTART
rw |
RCONT
rw |
RCH
rw |
||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
JSWSTART
rw |
JEXTEN
rw |
JEXTSEL
rw |
JDS
rw |
JCONT
rw |
STARTCALIB
rw |
CALIBCNT
rw |
ADON
rw |
||||||||
Bit 0: SDADC enable.
Bits 1-2: Number of calibration sequences to be performed (number of valid configurations).
Bit 4: Start calibration.
Bit 5: Continuous mode selection for injected conversions.
Bit 6: Delay start of injected conversions..
Bits 8-11: Trigger signal selection for launching injected conversions.
Bits 13-14: Trigger enable and trigger edge selection for injected conversions.
Bit 15: Start a conversion of the injected group of channels.
Bits 16-19: Regular channel selection.
Bit 22: Continuous mode selection for regular conversions.
Bit 23: Software start of a conversion on the regular channel.
Bit 24: Fast conversion mode selection.
interrupt and status register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-only
10/10 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
INITRDY
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
STABIP
r |
RCIP
r |
JCIP
r |
CALIBIP
r |
ROVRF
r |
REOCF
r |
JOVRF
r |
JEOCF
r |
EOCALF
r |
|||||||
Bit 0: End of calibration flag.
Bit 1: End of injected conversion flag.
Bit 2: Injected conversion overrun flag.
Bit 3: End of regular conversion flag.
Bit 4: Regular conversion overrun flag.
Bit 12: Calibration in progress status.
Bit 13: Injected conversion in progress status.
Bit 14: Regular conversion in progress status.
Bit 15: Stabilization in progress status.
Bit 31: Initialization mode is ready.
interrupt and status clear register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
injected channel group selection register
Offset: 0x14, size: 32, reset: 0x00000001, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
JCHG
rw |
|||||||||||||||
configuration 0 register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
configuration 1 register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
configuration 2 register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
channel configuration register 1
Offset: 0x40, size: 32, reset: 0x00000000, access: read-write
0/8 fields covered.
channel configuration register 2
Offset: 0x44, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CONFCH8
rw |
|||||||||||||||
data register for injected group
Offset: 0x60, size: 32, reset: 0x00000000, access: read-only
2/2 fields covered.
data register for the regular channel
Offset: 0x64, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
RDATA
r |
|||||||||||||||
SDADC1 and SDADC2 injected data register
Offset: 0x70, size: 32, reset: 0x00000000, access: read-only
2/2 fields covered.
SDADC1 and SDADC2 regular data register
Offset: 0x74, size: 32, reset: 0x00000000, access: read-only
2/2 fields covered.
SDADC1 and SDADC3 injected data register
Offset: 0x78, size: 32, reset: 0x00000000, access: read-only
2/2 fields covered.
0x40016400: Sigma-delta analog-to-digital converter
21/72 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | ISR | ||||||||||||||||||||||||||||||||
| 0xc | CLRISR | ||||||||||||||||||||||||||||||||
| 0x14 | JCHGR | ||||||||||||||||||||||||||||||||
| 0x20 | CONF0R | ||||||||||||||||||||||||||||||||
| 0x24 | CONF1R | ||||||||||||||||||||||||||||||||
| 0x28 | CONF2R | ||||||||||||||||||||||||||||||||
| 0x40 | CONFCHR1 | ||||||||||||||||||||||||||||||||
| 0x44 | CONFCHR2 | ||||||||||||||||||||||||||||||||
| 0x60 | JDATAR | ||||||||||||||||||||||||||||||||
| 0x64 | RDATAR | ||||||||||||||||||||||||||||||||
| 0x70 | JDATA12R | ||||||||||||||||||||||||||||||||
| 0x74 | RDATA12R | ||||||||||||||||||||||||||||||||
| 0x78 | JDATA13R | ||||||||||||||||||||||||||||||||
| 0x7c | RDATA13R | ||||||||||||||||||||||||||||||||
control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
0/14 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
INIT
rw |
RDMAEN
rw |
JDMAEN
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RSYNC
rw |
JSYNC
rw |
PDI
rw |
SBI
rw |
SLOWCK
rw |
REFV
rw |
ROVRIE
rw |
REOCIE
rw |
JOVRIE
rw |
JEOCIE
rw |
EOCALIE
rw |
|||||
Bit 0: End of calibration interrupt enable.
Bit 1: Injected end of conversion interrupt enable.
Bit 2: Injected data overrun interrupt enable.
Bit 3: Regular end of conversion interrupt enable.
Bit 4: Regular data overrun interrupt enable.
Bits 8-9: Reference voltage selection.
Bit 10: Slow clock mode enable.
Bit 11: Enter Standby mode when idle.
Bit 12: Enter power down mode when idle.
Bit 14: Launch a injected conversion synchronously with SDADC1.
Bit 15: Launch regular conversion synchronously with SDADC1.
Bit 16: DMA channel enabled to read data for the injected channel group.
Bit 17: DMA channel enabled to read data for the regular channel.
Bit 31: Initialization mode request.
control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
0/12 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
FAST
rw |
RSWSTART
rw |
RCONT
rw |
RCH
rw |
||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
JSWSTART
rw |
JEXTEN
rw |
JEXTSEL
rw |
JDS
rw |
JCONT
rw |
STARTCALIB
rw |
CALIBCNT
rw |
ADON
rw |
||||||||
Bit 0: SDADC enable.
Bits 1-2: Number of calibration sequences to be performed (number of valid configurations).
Bit 4: Start calibration.
Bit 5: Continuous mode selection for injected conversions.
Bit 6: Delay start of injected conversions..
Bits 8-11: Trigger signal selection for launching injected conversions.
Bits 13-14: Trigger enable and trigger edge selection for injected conversions.
Bit 15: Start a conversion of the injected group of channels.
Bits 16-19: Regular channel selection.
Bit 22: Continuous mode selection for regular conversions.
Bit 23: Software start of a conversion on the regular channel.
Bit 24: Fast conversion mode selection.
interrupt and status register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-only
10/10 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
INITRDY
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
STABIP
r |
RCIP
r |
JCIP
r |
CALIBIP
r |
ROVRF
r |
REOCF
r |
JOVRF
r |
JEOCF
r |
EOCALF
r |
|||||||
Bit 0: End of calibration flag.
Bit 1: End of injected conversion flag.
Bit 2: Injected conversion overrun flag.
Bit 3: End of regular conversion flag.
Bit 4: Regular conversion overrun flag.
Bit 12: Calibration in progress status.
Bit 13: Injected conversion in progress status.
Bit 14: Regular conversion in progress status.
Bit 15: Stabilization in progress status.
Bit 31: Initialization mode is ready.
interrupt and status clear register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
injected channel group selection register
Offset: 0x14, size: 32, reset: 0x00000001, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
JCHG
rw |
|||||||||||||||
configuration 0 register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
configuration 1 register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
configuration 2 register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
channel configuration register 1
Offset: 0x40, size: 32, reset: 0x00000000, access: read-write
0/8 fields covered.
channel configuration register 2
Offset: 0x44, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CONFCH8
rw |
|||||||||||||||
data register for injected group
Offset: 0x60, size: 32, reset: 0x00000000, access: read-only
2/2 fields covered.
data register for the regular channel
Offset: 0x64, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
RDATA
r |
|||||||||||||||
SDADC1 and SDADC2 injected data register
Offset: 0x70, size: 32, reset: 0x00000000, access: read-only
2/2 fields covered.
SDADC1 and SDADC2 regular data register
Offset: 0x74, size: 32, reset: 0x00000000, access: read-only
2/2 fields covered.
SDADC1 and SDADC3 injected data register
Offset: 0x78, size: 32, reset: 0x00000000, access: read-only
2/2 fields covered.
0x40016800: Sigma-delta analog-to-digital converter
21/72 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | ISR | ||||||||||||||||||||||||||||||||
| 0xc | CLRISR | ||||||||||||||||||||||||||||||||
| 0x14 | JCHGR | ||||||||||||||||||||||||||||||||
| 0x20 | CONF0R | ||||||||||||||||||||||||||||||||
| 0x24 | CONF1R | ||||||||||||||||||||||||||||||||
| 0x28 | CONF2R | ||||||||||||||||||||||||||||||||
| 0x40 | CONFCHR1 | ||||||||||||||||||||||||||||||||
| 0x44 | CONFCHR2 | ||||||||||||||||||||||||||||||||
| 0x60 | JDATAR | ||||||||||||||||||||||||||||||||
| 0x64 | RDATAR | ||||||||||||||||||||||||||||||||
| 0x70 | JDATA12R | ||||||||||||||||||||||||||||||||
| 0x74 | RDATA12R | ||||||||||||||||||||||||||||||||
| 0x78 | JDATA13R | ||||||||||||||||||||||||||||||||
| 0x7c | RDATA13R | ||||||||||||||||||||||||||||||||
control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
0/14 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
INIT
rw |
RDMAEN
rw |
JDMAEN
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RSYNC
rw |
JSYNC
rw |
PDI
rw |
SBI
rw |
SLOWCK
rw |
REFV
rw |
ROVRIE
rw |
REOCIE
rw |
JOVRIE
rw |
JEOCIE
rw |
EOCALIE
rw |
|||||
Bit 0: End of calibration interrupt enable.
Bit 1: Injected end of conversion interrupt enable.
Bit 2: Injected data overrun interrupt enable.
Bit 3: Regular end of conversion interrupt enable.
Bit 4: Regular data overrun interrupt enable.
Bits 8-9: Reference voltage selection.
Bit 10: Slow clock mode enable.
Bit 11: Enter Standby mode when idle.
Bit 12: Enter power down mode when idle.
Bit 14: Launch a injected conversion synchronously with SDADC1.
Bit 15: Launch regular conversion synchronously with SDADC1.
Bit 16: DMA channel enabled to read data for the injected channel group.
Bit 17: DMA channel enabled to read data for the regular channel.
Bit 31: Initialization mode request.
control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
0/12 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
FAST
rw |
RSWSTART
rw |
RCONT
rw |
RCH
rw |
||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
JSWSTART
rw |
JEXTEN
rw |
JEXTSEL
rw |
JDS
rw |
JCONT
rw |
STARTCALIB
rw |
CALIBCNT
rw |
ADON
rw |
||||||||
Bit 0: SDADC enable.
Bits 1-2: Number of calibration sequences to be performed (number of valid configurations).
Bit 4: Start calibration.
Bit 5: Continuous mode selection for injected conversions.
Bit 6: Delay start of injected conversions..
Bits 8-11: Trigger signal selection for launching injected conversions.
Bits 13-14: Trigger enable and trigger edge selection for injected conversions.
Bit 15: Start a conversion of the injected group of channels.
Bits 16-19: Regular channel selection.
Bit 22: Continuous mode selection for regular conversions.
Bit 23: Software start of a conversion on the regular channel.
Bit 24: Fast conversion mode selection.
interrupt and status register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-only
10/10 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
INITRDY
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
STABIP
r |
RCIP
r |
JCIP
r |
CALIBIP
r |
ROVRF
r |
REOCF
r |
JOVRF
r |
JEOCF
r |
EOCALF
r |
|||||||
Bit 0: End of calibration flag.
Bit 1: End of injected conversion flag.
Bit 2: Injected conversion overrun flag.
Bit 3: End of regular conversion flag.
Bit 4: Regular conversion overrun flag.
Bit 12: Calibration in progress status.
Bit 13: Injected conversion in progress status.
Bit 14: Regular conversion in progress status.
Bit 15: Stabilization in progress status.
Bit 31: Initialization mode is ready.
interrupt and status clear register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
injected channel group selection register
Offset: 0x14, size: 32, reset: 0x00000001, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
JCHG
rw |
|||||||||||||||
configuration 0 register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
configuration 1 register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
configuration 2 register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
channel configuration register 1
Offset: 0x40, size: 32, reset: 0x00000000, access: read-write
0/8 fields covered.
channel configuration register 2
Offset: 0x44, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CONFCH8
rw |
|||||||||||||||
data register for injected group
Offset: 0x60, size: 32, reset: 0x00000000, access: read-only
2/2 fields covered.
data register for the regular channel
Offset: 0x64, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
RDATA
r |
|||||||||||||||
SDADC1 and SDADC2 injected data register
Offset: 0x70, size: 32, reset: 0x00000000, access: read-only
2/2 fields covered.
SDADC1 and SDADC2 regular data register
Offset: 0x74, size: 32, reset: 0x00000000, access: read-only
2/2 fields covered.
SDADC1 and SDADC3 injected data register
Offset: 0x78, size: 32, reset: 0x00000000, access: read-only
2/2 fields covered.
0x40013000: Serial peripheral interface/Inter-IC sound
53/53 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 (16-bit) | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 (16-bit) | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 (16-bit) | SR | ||||||||||||||||||||||||||||||||
| 0xc (16-bit) | DR | ||||||||||||||||||||||||||||||||
| 0xc (8-bit) | DR8 | ||||||||||||||||||||||||||||||||
| 0x10 (16-bit) | CRCPR | ||||||||||||||||||||||||||||||||
| 0x14 (16-bit) | RXCRCR | ||||||||||||||||||||||||||||||||
| 0x18 (16-bit) | TXCRCR | ||||||||||||||||||||||||||||||||
| 0x1c (16-bit) | I2SCFGR | ||||||||||||||||||||||||||||||||
| 0x20 (16-bit) | I2SPR | ||||||||||||||||||||||||||||||||
control register 1
Offset: 0x0, size: 16, reset: 0x00000000, access: read-write
14/14 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BIDIMODE
rw |
BIDIOE
rw |
CRCEN
rw |
CRCNEXT
rw |
CRCL
rw |
RXONLY
rw |
SSM
rw |
SSI
rw |
LSBFIRST
rw |
SPE
rw |
BR
rw |
MSTR
rw |
CPOL
rw |
CPHA
rw |
||
Bit 0: Clock phase.
Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge
Bit 1: Clock polarity.
Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle
Bit 2: Master selection.
Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration
Bits 3-5: Baud rate control.
Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256
Bit 6: SPI enable.
Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled
Bit 7: Frame format.
Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first
Bit 8: Internal slave select.
Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
Bit 9: Software slave management.
Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled
Bit 10: Receive only.
Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)
Bit 11: CRC length.
Allowed values:
0: EightBit: 8-bit CRC length
1: SixteenBit: 16-bit CRC length
Bit 12: CRC transfer next.
Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register
Bit 13: Hardware CRC calculation enable.
Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled
Bit 14: Output enable in bidirectional mode.
Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)
Bit 15: Bidirectional data mode enable.
Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected
control register 2
Offset: 0x4, size: 16, reset: 0x00000000, access: read-write
12/12 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
LDMA_TX
rw |
LDMA_RX
rw |
FRXTH
rw |
DS
rw |
TXEIE
rw |
RXNEIE
rw |
ERRIE
rw |
FRF
rw |
NSSP
rw |
SSOE
rw |
TXDMAEN
rw |
RXDMAEN
rw |
||||
Bit 0: Rx buffer DMA enable.
Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled
Bit 1: Tx buffer DMA enable.
Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled
Bit 2: SS output enable.
Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode
Bit 3: NSS pulse management.
Allowed values:
0: NoPulse: No NSS pulse
1: PulseGenerated: NSS pulse generated
Bit 4: Frame format.
Allowed values:
0: Motorola: SPI Motorola mode
1: TI: SPI TI mode
Bit 5: Error interrupt enable.
Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked
Bit 6: RX buffer not empty interrupt enable.
Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked
Bit 7: Tx buffer empty interrupt enable.
Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked
Bits 8-11: Data size.
Allowed values:
3: FourBit: 4-bit
4: FiveBit: 5-bit
5: SixBit: 6-bit
6: SevenBit: 7-bit
7: EightBit: 8-bit
8: NineBit: 9-bit
9: TenBit: 10-bit
10: ElevenBit: 11-bit
11: TwelveBit: 12-bit
12: ThirteenBit: 13-bit
13: FourteenBit: 14-bit
14: FifteenBit: 15-bit
15: SixteenBit: 16-bit
Bit 12: FIFO reception threshold.
Allowed values:
0: Half: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)
1: Quarter: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)
Bit 13: Last DMA transfer for reception.
Allowed values:
0: Even: Number of data to transfer for receive is even
1: Odd: Number of data to transfer for receive is odd
Bit 14: Last DMA transfer for transmission.
Allowed values:
0: Even: Number of data to transfer for transmit is even
1: Odd: Number of data to transfer for transmit is odd
status register
Offset: 0x8, size: 16, reset: 0x00000002, access: Unspecified
11/11 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
FTLVL
r |
FRLVL
r |
TIFRFE
r |
BSY
r |
OVR
r |
MODF
r |
CRCERR
rw |
UDR
r |
CHSIDE
r |
TXE
r |
RXNE
r |
|||||
Bit 0: Receive buffer not empty.
Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty
Bit 1: Transmit buffer empty.
Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty
Bit 2: Channel side.
Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received
Bit 3: Underrun flag.
Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred
Bit 4: CRC error flag.
Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value
Bit 5: Mode fault.
Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred
Bit 6: Overrun flag.
Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred
Bit 7: Busy flag.
Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy
Bit 8: TI frame format error.
Allowed values:
0: NoError: No frame format error
1: Error: A frame format error occurred
Bits 9-10: FIFO reception level.
Allowed values:
0: Empty: Rx FIFO Empty
1: Quarter: Rx 1/4 FIFO
2: Half: Rx 1/2 FIFO
3: Full: Rx FIFO full
Bits 11-12: FIFO transmission level.
Allowed values:
0: Empty: Tx FIFO Empty
1: Quarter: Tx 1/4 FIFO
2: Half: Tx 1/2 FIFO
3: Full: Tx FIFO full
data register
Offset: 0xc, size: 16, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DR
rw |
|||||||||||||||
Direct 8-bit access to data register
Offset: 0xc, size: 8, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DR
rw |
|||||||||||||||
CRC polynomial register
Offset: 0x10, size: 16, reset: 0x00000007, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CRCPOLY
rw |
|||||||||||||||
RX CRC register
Offset: 0x14, size: 16, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
RxCRC
r |
|||||||||||||||
TX CRC register
Offset: 0x18, size: 16, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TxCRC
r |
|||||||||||||||
I2S configuration register
Offset: 0x1c, size: 16, reset: 0x00000000, access: read-write
8/8 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
I2SMOD
rw |
I2SE
rw |
I2SCFG
rw |
PCMSYNC
rw |
I2SSTD
rw |
CKPOL
rw |
DATLEN
rw |
CHLEN
rw |
||||||||
Bit 0: Channel length (number of bits per audio channel).
Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide
Bits 1-2: Data length to be transferred.
Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length
Bit 3: Steady state clock polarity.
Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level
Bits 4-5: I2S standard selection.
Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard
Bit 7: PCM frame synchronization.
Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation
Bits 8-9: I2S configuration mode.
Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive
Bit 10: I2S Enable.
Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled
Bit 11: I2S mode selection.
Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected
I2S prescaler register
Offset: 0x20, size: 16, reset: 0x00000010, access: read-write
3/3 fields covered.
Bits 0-7: I2S Linear prescaler.
Allowed values: 0x2-0xff
Bit 8: Odd factor for the prescaler.
Allowed values:
0: Even: Real divider value is I2SDIV * 2
1: Odd: Real divider value is (I2SDIV * 2) + 1
Bit 9: Master clock output enable.
Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled
0x40003800: Serial peripheral interface/Inter-IC sound
53/53 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 (16-bit) | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 (16-bit) | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 (16-bit) | SR | ||||||||||||||||||||||||||||||||
| 0xc (16-bit) | DR | ||||||||||||||||||||||||||||||||
| 0xc (8-bit) | DR8 | ||||||||||||||||||||||||||||||||
| 0x10 (16-bit) | CRCPR | ||||||||||||||||||||||||||||||||
| 0x14 (16-bit) | RXCRCR | ||||||||||||||||||||||||||||||||
| 0x18 (16-bit) | TXCRCR | ||||||||||||||||||||||||||||||||
| 0x1c (16-bit) | I2SCFGR | ||||||||||||||||||||||||||||||||
| 0x20 (16-bit) | I2SPR | ||||||||||||||||||||||||||||||||
control register 1
Offset: 0x0, size: 16, reset: 0x00000000, access: read-write
14/14 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BIDIMODE
rw |
BIDIOE
rw |
CRCEN
rw |
CRCNEXT
rw |
CRCL
rw |
RXONLY
rw |
SSM
rw |
SSI
rw |
LSBFIRST
rw |
SPE
rw |
BR
rw |
MSTR
rw |
CPOL
rw |
CPHA
rw |
||
Bit 0: Clock phase.
Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge
Bit 1: Clock polarity.
Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle
Bit 2: Master selection.
Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration
Bits 3-5: Baud rate control.
Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256
Bit 6: SPI enable.
Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled
Bit 7: Frame format.
Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first
Bit 8: Internal slave select.
Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
Bit 9: Software slave management.
Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled
Bit 10: Receive only.
Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)
Bit 11: CRC length.
Allowed values:
0: EightBit: 8-bit CRC length
1: SixteenBit: 16-bit CRC length
Bit 12: CRC transfer next.
Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register
Bit 13: Hardware CRC calculation enable.
Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled
Bit 14: Output enable in bidirectional mode.
Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)
Bit 15: Bidirectional data mode enable.
Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected
control register 2
Offset: 0x4, size: 16, reset: 0x00000000, access: read-write
12/12 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
LDMA_TX
rw |
LDMA_RX
rw |
FRXTH
rw |
DS
rw |
TXEIE
rw |
RXNEIE
rw |
ERRIE
rw |
FRF
rw |
NSSP
rw |
SSOE
rw |
TXDMAEN
rw |
RXDMAEN
rw |
||||
Bit 0: Rx buffer DMA enable.
Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled
Bit 1: Tx buffer DMA enable.
Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled
Bit 2: SS output enable.
Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode
Bit 3: NSS pulse management.
Allowed values:
0: NoPulse: No NSS pulse
1: PulseGenerated: NSS pulse generated
Bit 4: Frame format.
Allowed values:
0: Motorola: SPI Motorola mode
1: TI: SPI TI mode
Bit 5: Error interrupt enable.
Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked
Bit 6: RX buffer not empty interrupt enable.
Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked
Bit 7: Tx buffer empty interrupt enable.
Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked
Bits 8-11: Data size.
Allowed values:
3: FourBit: 4-bit
4: FiveBit: 5-bit
5: SixBit: 6-bit
6: SevenBit: 7-bit
7: EightBit: 8-bit
8: NineBit: 9-bit
9: TenBit: 10-bit
10: ElevenBit: 11-bit
11: TwelveBit: 12-bit
12: ThirteenBit: 13-bit
13: FourteenBit: 14-bit
14: FifteenBit: 15-bit
15: SixteenBit: 16-bit
Bit 12: FIFO reception threshold.
Allowed values:
0: Half: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)
1: Quarter: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)
Bit 13: Last DMA transfer for reception.
Allowed values:
0: Even: Number of data to transfer for receive is even
1: Odd: Number of data to transfer for receive is odd
Bit 14: Last DMA transfer for transmission.
Allowed values:
0: Even: Number of data to transfer for transmit is even
1: Odd: Number of data to transfer for transmit is odd
status register
Offset: 0x8, size: 16, reset: 0x00000002, access: Unspecified
11/11 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
FTLVL
r |
FRLVL
r |
TIFRFE
r |
BSY
r |
OVR
r |
MODF
r |
CRCERR
rw |
UDR
r |
CHSIDE
r |
TXE
r |
RXNE
r |
|||||
Bit 0: Receive buffer not empty.
Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty
Bit 1: Transmit buffer empty.
Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty
Bit 2: Channel side.
Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received
Bit 3: Underrun flag.
Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred
Bit 4: CRC error flag.
Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value
Bit 5: Mode fault.
Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred
Bit 6: Overrun flag.
Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred
Bit 7: Busy flag.
Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy
Bit 8: TI frame format error.
Allowed values:
0: NoError: No frame format error
1: Error: A frame format error occurred
Bits 9-10: FIFO reception level.
Allowed values:
0: Empty: Rx FIFO Empty
1: Quarter: Rx 1/4 FIFO
2: Half: Rx 1/2 FIFO
3: Full: Rx FIFO full
Bits 11-12: FIFO transmission level.
Allowed values:
0: Empty: Tx FIFO Empty
1: Quarter: Tx 1/4 FIFO
2: Half: Tx 1/2 FIFO
3: Full: Tx FIFO full
data register
Offset: 0xc, size: 16, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DR
rw |
|||||||||||||||
Direct 8-bit access to data register
Offset: 0xc, size: 8, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DR
rw |
|||||||||||||||
CRC polynomial register
Offset: 0x10, size: 16, reset: 0x00000007, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CRCPOLY
rw |
|||||||||||||||
RX CRC register
Offset: 0x14, size: 16, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
RxCRC
r |
|||||||||||||||
TX CRC register
Offset: 0x18, size: 16, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TxCRC
r |
|||||||||||||||
I2S configuration register
Offset: 0x1c, size: 16, reset: 0x00000000, access: read-write
8/8 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
I2SMOD
rw |
I2SE
rw |
I2SCFG
rw |
PCMSYNC
rw |
I2SSTD
rw |
CKPOL
rw |
DATLEN
rw |
CHLEN
rw |
||||||||
Bit 0: Channel length (number of bits per audio channel).
Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide
Bits 1-2: Data length to be transferred.
Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length
Bit 3: Steady state clock polarity.
Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level
Bits 4-5: I2S standard selection.
Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard
Bit 7: PCM frame synchronization.
Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation
Bits 8-9: I2S configuration mode.
Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive
Bit 10: I2S Enable.
Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled
Bit 11: I2S mode selection.
Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected
I2S prescaler register
Offset: 0x20, size: 16, reset: 0x00000010, access: read-write
3/3 fields covered.
Bits 0-7: I2S Linear prescaler.
Allowed values: 0x2-0xff
Bit 8: Odd factor for the prescaler.
Allowed values:
0: Even: Real divider value is I2SDIV * 2
1: Odd: Real divider value is (I2SDIV * 2) + 1
Bit 9: Master clock output enable.
Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled
0x40003c00: Serial peripheral interface/Inter-IC sound
53/53 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 (16-bit) | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 (16-bit) | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 (16-bit) | SR | ||||||||||||||||||||||||||||||||
| 0xc (16-bit) | DR | ||||||||||||||||||||||||||||||||
| 0xc (8-bit) | DR8 | ||||||||||||||||||||||||||||||||
| 0x10 (16-bit) | CRCPR | ||||||||||||||||||||||||||||||||
| 0x14 (16-bit) | RXCRCR | ||||||||||||||||||||||||||||||||
| 0x18 (16-bit) | TXCRCR | ||||||||||||||||||||||||||||||||
| 0x1c (16-bit) | I2SCFGR | ||||||||||||||||||||||||||||||||
| 0x20 (16-bit) | I2SPR | ||||||||||||||||||||||||||||||||
control register 1
Offset: 0x0, size: 16, reset: 0x00000000, access: read-write
14/14 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BIDIMODE
rw |
BIDIOE
rw |
CRCEN
rw |
CRCNEXT
rw |
CRCL
rw |
RXONLY
rw |
SSM
rw |
SSI
rw |
LSBFIRST
rw |
SPE
rw |
BR
rw |
MSTR
rw |
CPOL
rw |
CPHA
rw |
||
Bit 0: Clock phase.
Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge
Bit 1: Clock polarity.
Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle
Bit 2: Master selection.
Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration
Bits 3-5: Baud rate control.
Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256
Bit 6: SPI enable.
Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled
Bit 7: Frame format.
Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first
Bit 8: Internal slave select.
Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
Bit 9: Software slave management.
Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled
Bit 10: Receive only.
Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)
Bit 11: CRC length.
Allowed values:
0: EightBit: 8-bit CRC length
1: SixteenBit: 16-bit CRC length
Bit 12: CRC transfer next.
Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register
Bit 13: Hardware CRC calculation enable.
Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled
Bit 14: Output enable in bidirectional mode.
Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)
Bit 15: Bidirectional data mode enable.
Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected
control register 2
Offset: 0x4, size: 16, reset: 0x00000000, access: read-write
12/12 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
LDMA_TX
rw |
LDMA_RX
rw |
FRXTH
rw |
DS
rw |
TXEIE
rw |
RXNEIE
rw |
ERRIE
rw |
FRF
rw |
NSSP
rw |
SSOE
rw |
TXDMAEN
rw |
RXDMAEN
rw |
||||
Bit 0: Rx buffer DMA enable.
Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled
Bit 1: Tx buffer DMA enable.
Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled
Bit 2: SS output enable.
Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode
Bit 3: NSS pulse management.
Allowed values:
0: NoPulse: No NSS pulse
1: PulseGenerated: NSS pulse generated
Bit 4: Frame format.
Allowed values:
0: Motorola: SPI Motorola mode
1: TI: SPI TI mode
Bit 5: Error interrupt enable.
Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked
Bit 6: RX buffer not empty interrupt enable.
Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked
Bit 7: Tx buffer empty interrupt enable.
Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked
Bits 8-11: Data size.
Allowed values:
3: FourBit: 4-bit
4: FiveBit: 5-bit
5: SixBit: 6-bit
6: SevenBit: 7-bit
7: EightBit: 8-bit
8: NineBit: 9-bit
9: TenBit: 10-bit
10: ElevenBit: 11-bit
11: TwelveBit: 12-bit
12: ThirteenBit: 13-bit
13: FourteenBit: 14-bit
14: FifteenBit: 15-bit
15: SixteenBit: 16-bit
Bit 12: FIFO reception threshold.
Allowed values:
0: Half: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)
1: Quarter: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)
Bit 13: Last DMA transfer for reception.
Allowed values:
0: Even: Number of data to transfer for receive is even
1: Odd: Number of data to transfer for receive is odd
Bit 14: Last DMA transfer for transmission.
Allowed values:
0: Even: Number of data to transfer for transmit is even
1: Odd: Number of data to transfer for transmit is odd
status register
Offset: 0x8, size: 16, reset: 0x00000002, access: Unspecified
11/11 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
FTLVL
r |
FRLVL
r |
TIFRFE
r |
BSY
r |
OVR
r |
MODF
r |
CRCERR
rw |
UDR
r |
CHSIDE
r |
TXE
r |
RXNE
r |
|||||
Bit 0: Receive buffer not empty.
Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty
Bit 1: Transmit buffer empty.
Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty
Bit 2: Channel side.
Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received
Bit 3: Underrun flag.
Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred
Bit 4: CRC error flag.
Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value
Bit 5: Mode fault.
Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred
Bit 6: Overrun flag.
Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred
Bit 7: Busy flag.
Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy
Bit 8: TI frame format error.
Allowed values:
0: NoError: No frame format error
1: Error: A frame format error occurred
Bits 9-10: FIFO reception level.
Allowed values:
0: Empty: Rx FIFO Empty
1: Quarter: Rx 1/4 FIFO
2: Half: Rx 1/2 FIFO
3: Full: Rx FIFO full
Bits 11-12: FIFO transmission level.
Allowed values:
0: Empty: Tx FIFO Empty
1: Quarter: Tx 1/4 FIFO
2: Half: Tx 1/2 FIFO
3: Full: Tx FIFO full
data register
Offset: 0xc, size: 16, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DR
rw |
|||||||||||||||
Direct 8-bit access to data register
Offset: 0xc, size: 8, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DR
rw |
|||||||||||||||
CRC polynomial register
Offset: 0x10, size: 16, reset: 0x00000007, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CRCPOLY
rw |
|||||||||||||||
RX CRC register
Offset: 0x14, size: 16, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
RxCRC
r |
|||||||||||||||
TX CRC register
Offset: 0x18, size: 16, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TxCRC
r |
|||||||||||||||
I2S configuration register
Offset: 0x1c, size: 16, reset: 0x00000000, access: read-write
8/8 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
I2SMOD
rw |
I2SE
rw |
I2SCFG
rw |
PCMSYNC
rw |
I2SSTD
rw |
CKPOL
rw |
DATLEN
rw |
CHLEN
rw |
||||||||
Bit 0: Channel length (number of bits per audio channel).
Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide
Bits 1-2: Data length to be transferred.
Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length
Bit 3: Steady state clock polarity.
Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level
Bits 4-5: I2S standard selection.
Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard
Bit 7: PCM frame synchronization.
Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation
Bits 8-9: I2S configuration mode.
Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive
Bit 10: I2S Enable.
Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled
Bit 11: I2S mode selection.
Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected
I2S prescaler register
Offset: 0x20, size: 16, reset: 0x00000010, access: read-write
3/3 fields covered.
Bits 0-7: I2S Linear prescaler.
Allowed values: 0x2-0xff
Bit 8: Odd factor for the prescaler.
Allowed values:
0: Even: Real divider value is I2SDIV * 2
1: Odd: Real divider value is (I2SDIV * 2) + 1
Bit 9: Master clock output enable.
Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled
0xe000e010: SysTick timer
0/9 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CTRL | ||||||||||||||||||||||||||||||||
| 0x4 | LOAD | ||||||||||||||||||||||||||||||||
| 0x8 | VAL | ||||||||||||||||||||||||||||||||
| 0xc | CALIB | ||||||||||||||||||||||||||||||||
SysTick control and status register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
SysTick reload value register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
SysTick current value register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
0x40010000: System configuration controller
39/39 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CFGR1 | ||||||||||||||||||||||||||||||||
| 0x8 | EXTICR1 | ||||||||||||||||||||||||||||||||
| 0xc | EXTICR2 | ||||||||||||||||||||||||||||||||
| 0x10 | EXTICR3 | ||||||||||||||||||||||||||||||||
| 0x14 | EXTICR4 | ||||||||||||||||||||||||||||||||
| 0x18 | CFGR2 | ||||||||||||||||||||||||||||||||
configuration register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
19/19 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
FPU_IE5
rw |
FPU_IE4
rw |
FPU_IE3
rw |
FPU_IE2
rw |
FPU_IE1
rw |
FPU_IE0
rw |
VBAT_MON
rw |
I2C2_FMP
rw |
I2C1_FMP
rw |
I2C_PB9_FMP
rw |
I2C_PB8_FMP
rw |
I2C_PB7_FMP
rw |
I2C_PB6_FMP
rw |
|||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TIM18_DAC2_OUT1_DMA_RMP
rw |
TIM7_DAC1_OUT2_DMA_RMP
rw |
TIM6_DAC1_OUT1_DMA_RMP
rw |
TIM17_DMA_RMP
rw |
TIM16_DMA_RMP
rw |
MEM_MODE
rw |
||||||||||
Bits 0-1: Memory mapping selection bits.
Allowed values:
0: MainFlash: Main Flash memory mapped at 0x0000_0000
1: SystemFlash: System Flash memory mapped at 0x0000_0000
2: MainFlash2: Main Flash memory mapped at 0x0000_0000
3: SRAM: Embedded SRAM mapped at 0x0000_0000
Bit 11: TIM16 DMA request remapping bit.
Allowed values:
0: NotRemapped: TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3
1: Remapped: TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4
Bit 12: TIM17 DMA request remapping bit.
Allowed values:
0: NotRemapped: TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1
1: Remapped: TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2
Bit 13: TIM6 and DAC1 DMA request remapping bit.
Allowed values:
0: NotRemapped: TIM7 and DAC1_OUT1 DMA requests mapped on DMA2 channel 3
1: Remapped: TIM7 and DAC1_OUT1 DMA requests mapped on DMA1 channel 3
Bit 14: TIM7 and DAC2 DMA request remapping bit.
Allowed values:
0: NotRemapped: TIM7 and DAC1_OUT2 DMA requests mapped on DMA2 channel 4
1: Remapped: TIM7 and DAC1_OUT2 DMA requests mapped on DMA1 channel 4
Bit 15: TIM18 and DAC2_OUT1 DMA request remapping bit.
Allowed values:
0: NotRemapped: TIM18 and DAC2_OUT1 DMA requests mapped on DMA2 channel 5
1: Remapped: TIM18 and DAC2_OUT1 DMA requests mapped on DMA1 channel 5
Bit 16: Fast Mode Plus (FM+) driving capability activation bits..
Allowed values:
0: Standard: PB6 pin operate in standard mode
1: FMP: I2C FM+ mode enabled on PB6 and the Speed control is bypassed
Bit 17: Fast Mode Plus (FM+) driving capability activation bits..
Allowed values:
0: Standard: PB7 pin operate in standard mode
1: FMP: I2C FM+ mode enabled on PB7 and the Speed control is bypassed
Bit 18: Fast Mode Plus (FM+) driving capability activation bits..
Allowed values:
0: Standard: PB8 pin operate in standard mode
1: FMP: I2C FM+ mode enabled on PB8 and the Speed control is bypassed
Bit 19: Fast Mode Plus (FM+) driving capability activation bits..
Allowed values:
0: Standard: PB9 pin operate in standard mode
1: FMP: I2C FM+ mode enabled on PB9 and the Speed control is bypassed
Bit 20: I2C1 Fast Mode Plus.
Allowed values:
0: Standard: FM+ mode is controlled by I2C_Pxx_FMP bits only
1: FMP: FM+ mode is enabled on all I2C1 pins selected through selection through IOPORT control registers AF selection bits
Bit 21: I2C2 Fast Mode Plus.
Allowed values:
0: Standard: FM+ mode is controlled by I2C_Pxx_FMP bits only
1: FMP: FM+ mode is enabled on all I2C2 pins selected through selection through IOPORT control registers AF selection bits
Bit 24: VBAT monitoring enable.
Allowed values:
0: Disable: Disable the power switch to not deliver VBAT voltage on ADC channel 18 input
1: Enable: Enable the power switch to deliver VBAT voltage on ADC channel 18 input
Bit 26: Invalid operation interrupt enable.
Allowed values:
0: Disabled: Invalid operation interrupt disable
1: Enabled: Invalid operation interrupt enable
Bit 27: Devide-by-zero interrupt enable.
Allowed values:
0: Disabled: Devide-by-zero interrupt disable
1: Enabled: Devide-by-zero interrupt enable
Bit 28: Underflow interrupt enable.
Allowed values:
0: Disabled: Underflow interrupt disable
1: Enabled: Underflow interrupt enable
Bit 29: Overflow interrupt enable.
Allowed values:
0: Disabled: Overflow interrupt disable
1: Enabled: Overflow interrupt enable
Bit 30: Input denormal interrupt enable.
Allowed values:
0: Disabled: Input denormal interrupt disable
1: Enabled: Input denormal interrupt enable
Bit 31: Inexact interrupt enable.
Allowed values:
0: Disabled: Inexact interrupt disable
1: Enabled: Inexact interrupt enable
external interrupt configuration register 1
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
4/4 fields covered.
Bits 0-3: EXTI 0 configuration bits.
Allowed values:
0: PA0: Select PA0 as the source input for the EXTI0 external interrupt
1: PB0: Select PB0 as the source input for the EXTI0 external interrupt
2: PC0: Select PC0 as the source input for the EXTI0 external interrupt
3: PD0: Select PD0 as the source input for the EXTI0 external interrupt
4: PE0: Select PE0 as the source input for the EXTI0 external interrupt
5: PF0: Select PF0 as the source input for the EXTI0 external interrupt
Bits 4-7: EXTI 1 configuration bits.
Allowed values:
0: PA1: Select PA1 as the source input for the EXTI1 external interrupt
1: PB1: Select PB1 as the source input for the EXTI1 external interrupt
2: PC1: Select PC1 as the source input for the EXTI1 external interrupt
3: PD1: Select PD1 as the source input for the EXTI1 external interrupt
4: PE1: Select PE1 as the source input for the EXTI1 external interrupt
5: PF1: Select PF1 as the source input for the EXTI1 external interrupt
Bits 8-11: EXTI 2 configuration bits.
Allowed values:
0: PA2: Select PA2 as the source input for the EXTI2 external interrupt
1: PB2: Select PB2 as the source input for the EXTI2 external interrupt
2: PC2: Select PC2 as the source input for the EXTI2 external interrupt
3: PD2: Select PD2 as the source input for the EXTI2 external interrupt
4: PE2: Select PE2 as the source input for the EXTI2 external interrupt
5: PF2: Select PF2 as the source input for the EXTI2 external interrupt
Bits 12-15: EXTI 3 configuration bits.
Allowed values:
0: PA3: Select PA3 as the source input for the EXTI3 external interrupt
1: PB3: Select PB3 as the source input for the EXTI3 external interrupt
2: PC3: Select PC3 as the source input for the EXTI3 external interrupt
3: PD3: Select PD3 as the source input for the EXTI3 external interrupt
4: PE3: Select PE3 as the source input for the EXTI3 external interrupt
external interrupt configuration register 2
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
4/4 fields covered.
Bits 0-3: EXTI 4 configuration bits.
Allowed values:
0: PA4: Select PA4 as the source input for the EXTI4 external interrupt
1: PB4: Select PB4 as the source input for the EXTI4 external interrupt
2: PC4: Select PC4 as the source input for the EXTI4 external interrupt
3: PD4: Select PD4 as the source input for the EXTI4 external interrupt
4: PE4: Select PE4 as the source input for the EXTI4 external interrupt
5: PF4: Select PF4 as the source input for the EXTI4 external interrupt
Bits 4-7: EXTI 5 configuration bits.
Allowed values:
0: PA5: Select PA5 as the source input for the EXTI5 external interrupt
1: PB5: Select PB5 as the source input for the EXTI5 external interrupt
2: PC5: Select PC5 as the source input for the EXTI5 external interrupt
3: PD5: Select PD5 as the source input for the EXTI5 external interrupt
4: PE5: Select PE5 as the source input for the EXTI5 external interrupt
Bits 8-11: EXTI 6 configuration bits.
Allowed values:
0: PA6: Select PA6 as the source input for the EXTI6 external interrupt
1: PB6: Select PB6 as the source input for the EXTI6 external interrupt
2: PC6: Select PC6 as the source input for the EXTI6 external interrupt
3: PD6: Select PD6 as the source input for the EXTI6 external interrupt
4: PE6: Select PE6 as the source input for the EXTI6 external interrupt
5: PF6: Select PF6 as the source input for the EXTI6 external interrupt
Bits 12-15: EXTI 7 configuration bits.
Allowed values:
0: PA7: Select PA7 as the source input for the EXTI7 external interrupt
1: PB7: Select PB7 as the source input for the EXTI7 external interrupt
2: PC7: Select PC7 as the source input for the EXTI7 external interrupt
3: PD7: Select PD7 as the source input for the EXTI7 external interrupt
4: PE7: Select PE7 as the source input for the EXTI7 external interrupt
5: PF7: Select PF7 as the source input for the EXTI7 external interrupt
external interrupt configuration register 3
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
4/4 fields covered.
Bits 0-3: EXTI 8 configuration bits.
Allowed values:
0: PA8: Select PA8 as the source input for the EXTI8 external interrupt
1: PB8: Select PB8 as the source input for the EXTI8 external interrupt
2: PC8: Select PC8 as the source input for the EXTI8 external interrupt
3: PD8: Select PD8 as the source input for the EXTI8 external interrupt
4: PE8: Select PE8 as the source input for the EXTI8 external interrupt
Bits 4-7: EXTI 9 configuration bits.
Allowed values:
0: PA9: Select PA9 as the source input for the EXTI9 external interrupt
1: PB9: Select PB9 as the source input for the EXTI9 external interrupt
2: PC9: Select PC9 as the source input for the EXTI9 external interrupt
3: PD9: Select PD9 as the source input for the EXTI9 external interrupt
4: PE9: Select PE9 as the source input for the EXTI9 external interrupt
5: PF9: Select PF9 as the source input for the EXTI9 external interrupt
Bits 8-11: EXTI 10 configuration bits.
Allowed values:
0: PA10: Select PA10 as the source input for the EXTI10 external interrupt
1: PB10: Select PB10 as the source input for the EXTI10 external interrupt
2: PC10: Select PC10 as the source input for the EXTI10 external interrupt
3: PD10: Select PD10 as the source input for the EXTI10 external interrupt
4: PE10: Select PE10 as the source input for the EXTI10 external interrupt
5: PF10: Select PF10 as the source input for the EXTI10 external interrupt
Bits 12-15: EXTI 11 configuration bits.
Allowed values:
0: PA11: Select PA11 as the source input for the EXTI11 external interrupt
2: PC11: Select PC11 as the source input for the EXTI11 external interrupt
3: PD11: Select PD11 as the source input for the EXTI11 external interrupt
4: PE11: Select PE11 as the source input for the EXTI11 external interrupt
external interrupt configuration register 4
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
4/4 fields covered.
Bits 0-3: EXTI 12 configuration bits.
Allowed values:
0: PA12: Select PA12 as the source input for the EXTI12 external interrupt
2: PC12: Select PC12 as the source input for the EXTI12 external interrupt
3: PD12: Select PD12 as the source input for the EXTI12 external interrupt
4: PE12: Select PE12 as the source input for the EXTI12 external interrupt
Bits 4-7: EXTI 13 configuration bits.
Allowed values:
0: PA13: Select PA13 as the source input for the EXTI13 external interrupt
2: PC13: Select PC13 as the source input for the EXTI13 external interrupt
3: PD13: Select PD13 as the source input for the EXTI13 external interrupt
4: PE13: Select PE13 as the source input for the EXTI13 external interrupt
Bits 8-11: EXTI 14 configuration bits.
Allowed values:
0: PA14: Select PA14 as the source input for the EXTI14 external interrupt
1: PB14: Select PB14 as the source input for the EXTI14 external interrupt
2: PC14: Select PC14 as the source input for the EXTI14 external interrupt
3: PD14: Select PD14 as the source input for the EXTI14 external interrupt
4: PE14: Select PE14 as the source input for the EXTI14 external interrupt
Bits 12-15: EXTI 15 configuration bits.
Allowed values:
0: PA15: Select PA15 as the source input for the EXTI15 external interrupt
1: PB15: Select PB15 as the source input for the EXTI15 external interrupt
2: PC15: Select PC15 as the source input for the EXTI15 external interrupt
3: PD15: Select PD15 as the source input for the EXTI15 external interrupt
4: PE15: Select PE15 as the source input for the EXTI15 external interrupt
configuration register 2
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
4/4 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SRAM_PEF
rw |
PVD_LOCK
rw |
SRAM_PARITY_LOCK
rw |
LOCKUP_LOCK
rw |
||||||||||||
Bit 0: Cortex-M0 LOCKUP bit enable bit.
Allowed values:
0: Disconnected: Cortex-M4F LOCKUP output disconnected from TIM1/15/16/17 Break input
1: Connected: Cortex-M4F LOCKUP output connected to TIM1/15/16/17 Break input
Bit 1: SRAM parity lock bit.
Allowed values:
0: Disconnected: SRAM parity error disconnected from TIM1/15/16/17 Break input
1: Connected: SRAM parity error connected to TIM1/15/16/17 Break input
Bit 2: PVD lock enable bit.
Allowed values:
0: Disconnected: PVD interrupt disconnected from TIM15/16/17 Break input
1: Connected: PVD interrupt connected to TIM15/16/17 Break input
Bit 8: SRAM parity flag.
Allowed values:
0: NoParityError: No SRAM parity error detected
1: ParityErrorDetected: SRAM parity error detected
0x40001800: General purpose timers
12/48 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x8 | SMCR | ||||||||||||||||||||||||||||||||
| 0xc | DIER | ||||||||||||||||||||||||||||||||
| 0x10 | SR | ||||||||||||||||||||||||||||||||
| 0x14 | EGR | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
| 0x20 | CCER | ||||||||||||||||||||||||||||||||
| 0x24 | CNT | ||||||||||||||||||||||||||||||||
| 0x28 | PSC | ||||||||||||||||||||||||||||||||
| 0x2c | ARR | ||||||||||||||||||||||||||||||||
| 0x34 | CCR[1] | ||||||||||||||||||||||||||||||||
| 0x38 | CCR[2] | ||||||||||||||||||||||||||||||||
control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
6/6 fields covered.
Bit 0: Counter enable.
Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled
Bit 1: Update disable.
Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled
Bit 2: Update request source.
Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request
Bit 3: One-pulse mode.
Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)
Bit 7: Auto-reload preload enable.
Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered
Bits 8-9: Clock division.
Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT
slave mode control register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
DMA/Interrupt enable register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
1/4 fields covered.
status register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
1/6 fields covered.
Bit 0: Update interrupt flag.
Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending
Bit 1: Capture/compare 1 interrupt flag.
Bit 2: Capture/compare 2 interrupt flag.
Bit 6: Trigger interrupt flag.
Bit 9: Capture/Compare 1 overcapture flag.
Bit 10: Capture/Compare 2 overcapture flag.
event generation register
Offset: 0x14, size: 32, reset: 0x00000000, access: write-only
1/4 fields covered.
capture/compare mode register 1 (input mode)
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
0/6 fields covered.
capture/compare mode register (output mode)
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
2/8 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OC[2]M
rw |
OC[2]PE
rw |
OC[2]FE
rw |
CC[2]S
rw |
OC[1]M
rw |
OC[1]PE
rw |
OC[1]FE
rw |
CC[1]S
rw |
||||||||
Bits 0-1: Capture/Compare 1 selection.
Bit 2: Output compare 1 fast enable.
Bit 3: Output compare 1 preload enable.
Bits 4-6: Output compare 1 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1
Bits 8-9: Capture/Compare 2 selection.
Bit 10: Output compare 2 fast enable.
Bit 11: Output compare 2 preload enable.
Bits 12-14: Output compare 2 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1
capture/compare enable register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
0/6 fields covered.
Bit 0: Capture/Compare 1 output enable.
Bit 1: Capture/Compare 1 output Polarity.
Bit 3: Capture/Compare 1 output Polarity.
Bit 4: Capture/Compare 2 output enable.
Bit 5: Capture/Compare 2 output Polarity.
Bit 7: Capture/Compare 2 output Polarity.
counter
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ARR
rw |
|||||||||||||||
capture/compare register
Offset: 0x34, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CCR
rw |
|||||||||||||||
capture/compare register
Offset: 0x38, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CCR
rw |
|||||||||||||||
0x40001c00: General purpose timers
10/26 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0xc | DIER | ||||||||||||||||||||||||||||||||
| 0x10 | SR | ||||||||||||||||||||||||||||||||
| 0x14 | EGR | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
| 0x20 | CCER | ||||||||||||||||||||||||||||||||
| 0x24 | CNT | ||||||||||||||||||||||||||||||||
| 0x28 | PSC | ||||||||||||||||||||||||||||||||
| 0x2c | ARR | ||||||||||||||||||||||||||||||||
| 0x34 | CCR[1] | ||||||||||||||||||||||||||||||||
control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
5/5 fields covered.
Bit 0: Counter enable.
Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled
Bit 1: Update disable.
Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled
Bit 2: Update request source.
Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request
Bit 7: Auto-reload preload enable.
Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered
Bits 8-9: Clock division.
Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT
DMA/Interrupt enable register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
1/2 fields covered.
status register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
1/3 fields covered.
event generation register
Offset: 0x14, size: 32, reset: 0x00000000, access: write-only
1/2 fields covered.
capture/compare mode register (input mode)
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
capture/compare mode register (output mode)
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
1/4 fields covered.
Bits 0-1: Capture/Compare 1 selection.
Bit 2: Output compare 1 fast enable.
Bit 3: Output compare 1 preload enable.
Bits 4-6: Output compare 1 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1
capture/compare enable register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
counter
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ARR
rw |
|||||||||||||||
capture/compare register
Offset: 0x34, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CCR
rw |
|||||||||||||||
0x40002000: General purpose timers
10/26 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0xc | DIER | ||||||||||||||||||||||||||||||||
| 0x10 | SR | ||||||||||||||||||||||||||||||||
| 0x14 | EGR | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
| 0x20 | CCER | ||||||||||||||||||||||||||||||||
| 0x24 | CNT | ||||||||||||||||||||||||||||||||
| 0x28 | PSC | ||||||||||||||||||||||||||||||||
| 0x2c | ARR | ||||||||||||||||||||||||||||||||
| 0x34 | CCR[1] | ||||||||||||||||||||||||||||||||
control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
5/5 fields covered.
Bit 0: Counter enable.
Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled
Bit 1: Update disable.
Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled
Bit 2: Update request source.
Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request
Bit 7: Auto-reload preload enable.
Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered
Bits 8-9: Clock division.
Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT
DMA/Interrupt enable register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
1/2 fields covered.
status register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
1/3 fields covered.
event generation register
Offset: 0x14, size: 32, reset: 0x00000000, access: write-only
1/2 fields covered.
capture/compare mode register (input mode)
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
capture/compare mode register (output mode)
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
1/4 fields covered.
Bits 0-1: Capture/Compare 1 selection.
Bit 2: Output compare 1 fast enable.
Bit 3: Output compare 1 preload enable.
Bits 4-6: Output compare 1 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1
capture/compare enable register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
counter
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ARR
rw |
|||||||||||||||
capture/compare register
Offset: 0x34, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CCR
rw |
|||||||||||||||
0x40014000: General purpose timers
12/78 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | SMCR | ||||||||||||||||||||||||||||||||
| 0xc | DIER | ||||||||||||||||||||||||||||||||
| 0x10 | SR | ||||||||||||||||||||||||||||||||
| 0x14 | EGR | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
| 0x20 | CCER | ||||||||||||||||||||||||||||||||
| 0x24 | CNT | ||||||||||||||||||||||||||||||||
| 0x28 | PSC | ||||||||||||||||||||||||||||||||
| 0x2c | ARR | ||||||||||||||||||||||||||||||||
| 0x30 | RCR | ||||||||||||||||||||||||||||||||
| 0x34 | CCR[1] | ||||||||||||||||||||||||||||||||
| 0x38 | CCR[2] | ||||||||||||||||||||||||||||||||
| 0x44 | BDTR | ||||||||||||||||||||||||||||||||
| 0x48 | DCR | ||||||||||||||||||||||||||||||||
| 0x4c | DMAR | ||||||||||||||||||||||||||||||||
control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
6/6 fields covered.
Bit 0: Counter enable.
Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled
Bit 1: Update disable.
Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled
Bit 2: Update request source.
Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request
Bit 3: One-pulse mode.
Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)
Bit 7: Auto-reload preload enable.
Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered
Bits 8-9: Clock division.
Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT
control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
0/7 fields covered.
slave mode control register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
DMA/Interrupt enable register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
1/10 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TDE
rw |
CC[2]DE
rw |
CC[1]DE
rw |
UDE
rw |
BIE
rw |
TIE
rw |
COMIE
rw |
CC[2]IE
rw |
CC[1]IE
rw |
UIE
rw |
||||||
Bit 0: Update interrupt enable.
Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled
Bit 1: Capture/Compare 1 interrupt enable.
Bit 2: Capture/Compare 2 interrupt enable.
Bit 5: COM interrupt enable.
Bit 6: Trigger interrupt enable.
Bit 7: Break interrupt enable.
Bit 8: Update DMA request enable.
Bit 9: Capture/Compare 1 DMA request enable.
Bit 10: Capture/Compare 2 DMA request enable.
Bit 14: Trigger DMA request enable.
status register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
1/8 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CC[2]OF
rw |
CC[1]OF
rw |
BIF
rw |
TIF
rw |
COMIF
rw |
CC[2]IF
rw |
CC[1]IF
rw |
UIF
rw |
||||||||
Bit 0: Update interrupt flag.
Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending
Bit 1: Capture/compare 1 interrupt flag.
Bit 2: Capture/compare 2 interrupt flag.
Bit 5: COM interrupt flag.
Bit 6: Trigger interrupt flag.
Bit 7: Break interrupt flag.
Bit 9: Capture/Compare 1 overcapture flag.
Bit 10: Capture/Compare 2 overcapture flag.
event generation register
Offset: 0x14, size: 32, reset: 0x00000000, access: write-only
1/6 fields covered.
Bit 0: Update generation.
Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.
Bit 1: Capture/compare 1 generation.
Bit 2: Capture/compare 2 generation.
Bit 5: Capture/Compare control update generation.
Bit 6: Trigger generation.
Bit 7: Break generation.
capture/compare mode register 1 (input mode)
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
0/6 fields covered.
capture/compare mode register (output mode)
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
2/8 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OC[2]M
rw |
OC[2]PE
rw |
OC[2]FE
rw |
CC[2]S
rw |
OC[1]M
rw |
OC[1]PE
rw |
OC[1]FE
rw |
CC[1]S
rw |
||||||||
Bits 0-1: Capture/Compare 1 selection.
Bit 2: Output compare 1 fast enable.
Bit 3: Output compare 1 preload enable.
Bits 4-6: Output compare 1 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1
Bits 8-9: Capture/Compare 2 selection.
Bit 10: Output compare 2 fast enable.
Bit 11: Output compare 2 preload enable.
Bits 12-14: Output compare 2 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1
capture/compare enable register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
0/7 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CC[2]NP
rw |
CC[2]P
rw |
CC[2]E
rw |
CC[1]NP
rw |
CC[1]NE
rw |
CC[1]P
rw |
CC[1]E
rw |
|||||||||
Bit 0: Capture/Compare 1 output enable.
Bit 1: Capture/Compare 1 output Polarity.
Bit 2: Capture/Compare 1 complementary output enable.
Bit 3: Capture/Compare 1 output Polarity.
Bit 4: Capture/Compare 2 output enable.
Bit 5: Capture/Compare 2 output Polarity.
Bit 7: Capture/Compare 2 output Polarity.
counter
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ARR
rw |
|||||||||||||||
repetition counter register
Offset: 0x30, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
REP
rw |
|||||||||||||||
capture/compare register
Offset: 0x34, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CCR
rw |
|||||||||||||||
capture/compare register
Offset: 0x38, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CCR
rw |
|||||||||||||||
break and dead-time register
Offset: 0x44, size: 32, reset: 0x00000000, access: read-write
0/8 fields covered.
Bits 0-7: Dead-time generator setup.
Bits 8-9: Lock configuration.
Bit 10: Off-state selection for Idle mode.
Bit 11: Off-state selection for Run mode.
Bit 12: Break enable.
Bit 13: Break polarity.
Bit 14: Automatic output enable.
Bit 15: Main output enable.
DMA control register
Offset: 0x48, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
DMA address for full transfer
Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DMAB
rw |
|||||||||||||||
0x40014400: General-purpose-timers
20/57 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0xc | DIER | ||||||||||||||||||||||||||||||||
| 0x10 | SR | ||||||||||||||||||||||||||||||||
| 0x14 | EGR | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
| 0x20 | CCER | ||||||||||||||||||||||||||||||||
| 0x24 | CNT | ||||||||||||||||||||||||||||||||
| 0x28 | PSC | ||||||||||||||||||||||||||||||||
| 0x2c | ARR | ||||||||||||||||||||||||||||||||
| 0x30 | RCR | ||||||||||||||||||||||||||||||||
| 0x34 | CCR[1] | ||||||||||||||||||||||||||||||||
| 0x44 | BDTR | ||||||||||||||||||||||||||||||||
| 0x48 | DCR | ||||||||||||||||||||||||||||||||
| 0x4c | DMAR | ||||||||||||||||||||||||||||||||
control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
6/6 fields covered.
Bit 0: Counter enable.
Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled
Bit 1: Update disable.
Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled
Bit 2: Update request source.
Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request
Bit 3: One-pulse mode.
Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)
Bit 7: Auto-reload preload enable.
Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered
Bits 8-9: Clock division.
Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT
control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
5/5 fields covered.
Bit 0: Capture/compare preloaded control.
Allowed values:
0: NotPreloaded: CCxE, CCxNE and OCxM bits are not preloaded
1: Preloaded: CCxE, CCxNE and OCxM bits are preloaded
Bit 2: Capture/compare control update selection.
Allowed values:
0: Default: Capture/compare are updated only by setting the COMG bit
1: WithRisingEdge: Capture/compare are updated by setting the COMG bit or when an rising edge occurs on TRGI
Bit 3: Capture/compare DMA selection.
Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs
Bit 8: Output Idle state 1.
Allowed values:
0: Reset: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
1: Set: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
Bit 9: Output Idle state 1.
Allowed values:
0: Reset: OC1N=0 after a dead-time when MOE=0
1: Set: OC1N=1 after a dead-time when MOE=0
DMA/Interrupt enable register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
5/8 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TDE
rw |
CC[1]DE
rw |
UDE
rw |
BIE
rw |
TIE
rw |
COMIE
rw |
CC[1]IE
rw |
UIE
rw |
||||||||
Bit 0: Update interrupt enable.
Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled
Bit 1: Capture/Compare 1 interrupt enable.
Allowed values:
0: Disabled: CC1 interrupt disabled
1: Enabled: CC1 interrupt enabled
Bit 5: COM interrupt enable.
Allowed values:
0: Disabled: COM interrupt disabled
1: Enabled: COM interrupt enabled
Bit 6: Trigger interrupt enable.
Bit 7: Break interrupt enable.
Allowed values:
0: Disabled: Break interrupt disabled
1: Enabled: Break interrupt enabled
Bit 8: Update DMA request enable.
Bit 9: Capture/Compare 1 DMA request enable.
Allowed values:
0: Disabled: CC1 DMA request disabled
1: Enabled: CC1 DMA request enabled
Bit 14: Trigger DMA request enable.
status register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
1/6 fields covered.
Bit 0: Update interrupt flag.
Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending
Bit 1: Capture/compare 1 interrupt flag.
Bit 5: COM interrupt flag.
Bit 6: Trigger interrupt flag.
Bit 7: Break interrupt flag.
Bit 9: Capture/Compare 1 overcapture flag.
event generation register
Offset: 0x14, size: 32, reset: 0x00000000, access: write-only
1/5 fields covered.
Bit 0: Update generation.
Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.
Bit 1: Capture/compare 1 generation.
Bit 5: Capture/Compare control update generation.
Bit 6: Trigger generation.
Bit 7: Break generation.
capture/compare mode register 1 (input mode)
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
capture/compare mode register (output mode)
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
1/4 fields covered.
Bits 0-1: Capture/Compare 1 selection.
Bit 2: Output compare 1 fast enable.
Bit 3: Output compare 1 preload enable.
Bits 4-6: Output compare 1 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1
capture/compare enable register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
counter
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ARR
rw |
|||||||||||||||
repetition counter register
Offset: 0x30, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
REP
rw |
|||||||||||||||
capture/compare register
Offset: 0x34, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CCR
rw |
|||||||||||||||
break and dead-time register
Offset: 0x44, size: 32, reset: 0x00000000, access: read-write
0/8 fields covered.
Bits 0-7: Dead-time generator setup.
Bits 8-9: Lock configuration.
Bit 10: Off-state selection for Idle mode.
Bit 11: Off-state selection for Run mode.
Bit 12: Break enable.
Bit 13: Break polarity.
Bit 14: Automatic output enable.
Bit 15: Main output enable.
DMA control register
Offset: 0x48, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
DMA address for full transfer
Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DMAB
rw |
|||||||||||||||
0x40014800: General-purpose-timers
20/57 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0xc | DIER | ||||||||||||||||||||||||||||||||
| 0x10 | SR | ||||||||||||||||||||||||||||||||
| 0x14 | EGR | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
| 0x20 | CCER | ||||||||||||||||||||||||||||||||
| 0x24 | CNT | ||||||||||||||||||||||||||||||||
| 0x28 | PSC | ||||||||||||||||||||||||||||||||
| 0x2c | ARR | ||||||||||||||||||||||||||||||||
| 0x30 | RCR | ||||||||||||||||||||||||||||||||
| 0x34 | CCR[1] | ||||||||||||||||||||||||||||||||
| 0x44 | BDTR | ||||||||||||||||||||||||||||||||
| 0x48 | DCR | ||||||||||||||||||||||||||||||||
| 0x4c | DMAR | ||||||||||||||||||||||||||||||||
control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
6/6 fields covered.
Bit 0: Counter enable.
Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled
Bit 1: Update disable.
Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled
Bit 2: Update request source.
Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request
Bit 3: One-pulse mode.
Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)
Bit 7: Auto-reload preload enable.
Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered
Bits 8-9: Clock division.
Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT
control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
5/5 fields covered.
Bit 0: Capture/compare preloaded control.
Allowed values:
0: NotPreloaded: CCxE, CCxNE and OCxM bits are not preloaded
1: Preloaded: CCxE, CCxNE and OCxM bits are preloaded
Bit 2: Capture/compare control update selection.
Allowed values:
0: Default: Capture/compare are updated only by setting the COMG bit
1: WithRisingEdge: Capture/compare are updated by setting the COMG bit or when an rising edge occurs on TRGI
Bit 3: Capture/compare DMA selection.
Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs
Bit 8: Output Idle state 1.
Allowed values:
0: Reset: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
1: Set: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
Bit 9: Output Idle state 1.
Allowed values:
0: Reset: OC1N=0 after a dead-time when MOE=0
1: Set: OC1N=1 after a dead-time when MOE=0
DMA/Interrupt enable register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
5/8 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TDE
rw |
CC[1]DE
rw |
UDE
rw |
BIE
rw |
TIE
rw |
COMIE
rw |
CC[1]IE
rw |
UIE
rw |
||||||||
Bit 0: Update interrupt enable.
Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled
Bit 1: Capture/Compare 1 interrupt enable.
Allowed values:
0: Disabled: CC1 interrupt disabled
1: Enabled: CC1 interrupt enabled
Bit 5: COM interrupt enable.
Allowed values:
0: Disabled: COM interrupt disabled
1: Enabled: COM interrupt enabled
Bit 6: Trigger interrupt enable.
Bit 7: Break interrupt enable.
Allowed values:
0: Disabled: Break interrupt disabled
1: Enabled: Break interrupt enabled
Bit 8: Update DMA request enable.
Bit 9: Capture/Compare 1 DMA request enable.
Allowed values:
0: Disabled: CC1 DMA request disabled
1: Enabled: CC1 DMA request enabled
Bit 14: Trigger DMA request enable.
status register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
1/6 fields covered.
Bit 0: Update interrupt flag.
Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending
Bit 1: Capture/compare 1 interrupt flag.
Bit 5: COM interrupt flag.
Bit 6: Trigger interrupt flag.
Bit 7: Break interrupt flag.
Bit 9: Capture/Compare 1 overcapture flag.
event generation register
Offset: 0x14, size: 32, reset: 0x00000000, access: write-only
1/5 fields covered.
Bit 0: Update generation.
Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.
Bit 1: Capture/compare 1 generation.
Bit 5: Capture/Compare control update generation.
Bit 6: Trigger generation.
Bit 7: Break generation.
capture/compare mode register 1 (input mode)
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
capture/compare mode register (output mode)
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
1/4 fields covered.
Bits 0-1: Capture/Compare 1 selection.
Bit 2: Output compare 1 fast enable.
Bit 3: Output compare 1 preload enable.
Bits 4-6: Output compare 1 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1
capture/compare enable register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
counter
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ARR
rw |
|||||||||||||||
repetition counter register
Offset: 0x30, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
REP
rw |
|||||||||||||||
capture/compare register
Offset: 0x34, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CCR
rw |
|||||||||||||||
break and dead-time register
Offset: 0x44, size: 32, reset: 0x00000000, access: read-write
0/8 fields covered.
Bits 0-7: Dead-time generator setup.
Bits 8-9: Lock configuration.
Bit 10: Off-state selection for Idle mode.
Bit 11: Off-state selection for Run mode.
Bit 12: Break enable.
Bit 13: Break polarity.
Bit 14: Automatic output enable.
Bit 15: Main output enable.
DMA control register
Offset: 0x48, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
DMA address for full transfer
Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DMAB
rw |
|||||||||||||||
0x40009c00: Basic timers
13/13 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0xc | DIER | ||||||||||||||||||||||||||||||||
| 0x10 | SR | ||||||||||||||||||||||||||||||||
| 0x14 | EGR | ||||||||||||||||||||||||||||||||
| 0x24 | CNT | ||||||||||||||||||||||||||||||||
| 0x28 | PSC | ||||||||||||||||||||||||||||||||
| 0x2c | ARR | ||||||||||||||||||||||||||||||||
control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
5/5 fields covered.
Bit 0: Counter enable.
Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled
Bit 1: Update disable.
Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled
Bit 2: Update request source.
Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request
Bit 3: One-pulse mode.
Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)
Bit 7: Auto-reload preload enable.
Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered
control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MMS
rw |
|||||||||||||||
DMA/Interrupt enable register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
2/2 fields covered.
status register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UIF
rw |
|||||||||||||||
event generation register
Offset: 0x14, size: 32, reset: 0x00000000, access: write-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UG
w |
|||||||||||||||
counter
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ARR
rw |
|||||||||||||||
0x40015c00: General purpose timer
77/100 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | SMCR | ||||||||||||||||||||||||||||||||
| 0xc | DIER | ||||||||||||||||||||||||||||||||
| 0x10 | SR | ||||||||||||||||||||||||||||||||
| 0x14 | EGR | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
| 0x1c | CCMR2_Input | ||||||||||||||||||||||||||||||||
| 0x1c | CCMR2_Output | ||||||||||||||||||||||||||||||||
| 0x20 | CCER | ||||||||||||||||||||||||||||||||
| 0x24 | CNT | ||||||||||||||||||||||||||||||||
| 0x28 | PSC | ||||||||||||||||||||||||||||||||
| 0x2c | ARR | ||||||||||||||||||||||||||||||||
| 0x34 | CCR[1] | ||||||||||||||||||||||||||||||||
| 0x38 | CCR[2] | ||||||||||||||||||||||||||||||||
| 0x3c | CCR[3] | ||||||||||||||||||||||||||||||||
| 0x40 | CCR[4] | ||||||||||||||||||||||||||||||||
| 0x48 | DCR | ||||||||||||||||||||||||||||||||
| 0x4c | DMAR | ||||||||||||||||||||||||||||||||
control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
Bit 0: Counter enable.
Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled
Bit 1: Update disable.
Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled
Bit 2: Update request source.
Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request
Bit 3: One-pulse mode.
Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)
Bit 4: Direction.
Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter
Bits 5-6: Center-aligned mode selection.
Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
Bit 7: Auto-reload preload enable.
Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered
Bits 8-9: Clock division.
Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT
control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
3/3 fields covered.
Bit 3: Capture/compare DMA selection.
Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs
Bits 4-6: Master mode selection.
Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output
Bit 7: TI1 selection.
Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
slave mode control register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
7/7 fields covered.
Bits 0-2: Slave mode selection.
Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Bits 4-6: Trigger selection.
Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)
Bit 7: Master/Slave mode.
Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Bits 8-11: External trigger filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
Bits 12-13: External trigger prescaler.
Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8
Bit 14: External clock enable.
Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
Bit 15: External trigger polarity.
Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge
DMA/Interrupt enable register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
12/12 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TDE
rw |
CC[4]DE
rw |
CC[3]DE
rw |
CC[2]DE
rw |
CC[1]DE
rw |
UDE
rw |
TIE
rw |
CC[4]IE
rw |
CC[3]IE
rw |
CC[2]IE
rw |
CC[1]IE
rw |
UIE
rw |
Bit 0: Update interrupt enable.
Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled
Bit 1: Capture/Compare 1 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 2: Capture/Compare 2 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 3: Capture/Compare 3 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 4: Capture/Compare 4 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 6: Trigger interrupt enable.
Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled
Bit 8: Update DMA request enable.
Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled
Bit 9: Capture/Compare 1 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 10: Capture/Compare 2 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 11: Capture/Compare 3 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 12: Capture/Compare 4 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 14: Trigger DMA request enable.
Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled
status register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
10/10 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CC[4]OF
rw |
CC[3]OF
rw |
CC[2]OF
rw |
CC[1]OF
rw |
TIF
rw |
CC[4]IF
rw |
CC[3]IF
rw |
CC[2]IF
rw |
CC[1]IF
rw |
UIF
rw |
||||||
Bit 0: Update interrupt flag.
Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending
Bit 1: Capture/compare 1 interrupt flag.
Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 2: Capture/compare 2 interrupt flag.
Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 3: Capture/compare 3 interrupt flag.
Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 4: Capture/compare 4 interrupt flag.
Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 6: Trigger interrupt flag.
Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending
Bit 9: Capture/Compare 1 overcapture flag.
Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
Bit 10: Capture/Compare 2 overcapture flag.
Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
Bit 11: Capture/Compare 3 overcapture flag.
Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
Bit 12: Capture/Compare 4 overcapture flag.
Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
event generation register
Offset: 0x14, size: 32, reset: 0x00000000, access: write-only
6/6 fields covered.
Bit 0: Update generation.
Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.
Bit 1: Capture/compare 1 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 2: Capture/compare 2 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 3: Capture/compare 3 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 4: Capture/compare 4 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 6: Trigger generation.
Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
capture/compare mode register 1 (input mode)
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
4/6 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IC[2]F
rw |
IC[2]PSC
rw |
CC[2]S
rw |
IC[1]F
rw |
IC[1]PSC
rw |
CC[1]S
rw |
||||||||||
Bits 0-1: Capture/Compare 1 selection.
Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC
Bits 2-3: Input capture 1 prescaler.
Bits 4-7: Input capture 1 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
Bits 8-9: Capture/Compare 2 selection.
Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC
Bits 10-11: Input capture 2 prescaler.
Bits 12-15: Input capture 2 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
capture/compare mode register 1 (output mode)
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
6/10 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OC[2]CE
rw |
OC[2]M
rw |
OC[2]PE
rw |
OC[2]FE
rw |
CC[2]S
rw |
OC[1]CE
rw |
OC[1]M
rw |
OC[1]PE
rw |
OC[1]FE
rw |
CC[1]S
rw |
||||||
Bits 0-1: Capture/Compare 1 selection.
Allowed values:
0: Output: CC1 channel is configured as output
Bit 2: Output compare 1 fast enable.
Bit 3: Output compare 1 preload enable.
Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event
Bits 4-6: Output compare 1 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1
Bit 7: Output compare 1 clear enable.
Bits 8-9: Capture/Compare 2 selection.
Allowed values:
0: Output: CC1 channel is configured as output
Bit 10: Output compare 2 fast enable.
Bit 11: Output compare 2 preload enable.
Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event
Bits 12-14: Output compare 2 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1
Bit 15: Output compare 2 clear enable.
capture/compare mode register 2 (input mode)
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
6/6 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IC[4]F
rw |
IC[4]PSC
rw |
CC[4]S
rw |
IC[3]F
rw |
IC[3]PSC
rw |
CC[3]S
rw |
||||||||||
Bits 0-1: Capture/Compare 3 selection.
Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC
Bits 2-3: Input capture 3 prescaler.
Allowed values: 0x0-0x3
Bits 4-7: Input capture 3 filter.
Allowed values: 0x0-0xf
Bits 8-9: Capture/Compare 4 selection.
Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC
Bits 10-11: Input capture 4 prescaler.
Allowed values: 0x0-0x3
Bits 12-15: Input capture 4 filter.
Allowed values: 0x0-0xf
capture/compare mode register 2 (output mode)
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
6/10 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OC[4]CE
rw |
OC[4]M
rw |
OC[4]PE
rw |
OC[4]FE
rw |
CC[4]S
rw |
OC[3]CE
rw |
OC[3]M
rw |
OC[3]PE
rw |
OC[3]FE
rw |
CC[3]S
rw |
||||||
Bits 0-1: Capture/Compare 3 selection.
Allowed values:
0: Output: CC3 channel is configured as output
Bit 2: Output compare 3 fast enable.
Bit 3: Output compare 3 preload enable.
Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event
Bits 4-6: Output compare 3 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1
Bit 7: Output compare 3 clear enable.
Bits 8-9: Capture/Compare 4 selection.
Allowed values:
0: Output: CC3 channel is configured as output
Bit 10: Output compare 4 fast enable.
Bit 11: Output compare 4 preload enable.
Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event
Bits 12-14: Output compare 4 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1
Bit 15: Output compare 4 clear enable.
capture/compare enable register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
0/12 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CC[4]NP
rw |
CC[4]P
rw |
CC[4]E
rw |
CC[3]NP
rw |
CC[3]P
rw |
CC[3]E
rw |
CC[2]NP
rw |
CC[2]P
rw |
CC[2]E
rw |
CC[1]NP
rw |
CC[1]P
rw |
CC[1]E
rw |
Bit 0: Capture/Compare 1 output enable.
Bit 1: Capture/Compare 1 output Polarity.
Bit 3: Capture/Compare 1 output Polarity.
Bit 4: Capture/Compare 2 output enable.
Bit 5: Capture/Compare 2 output Polarity.
Bit 7: Capture/Compare 2 output Polarity.
Bit 8: Capture/Compare 3 output enable.
Bit 9: Capture/Compare 3 output Polarity.
Bit 11: Capture/Compare 3 output Polarity.
Bit 12: Capture/Compare 4 output enable.
Bit 13: Capture/Compare 4 output Polarity.
Bit 15: Capture/Compare 4 output Polarity.
counter
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ARR
rw |
|||||||||||||||
capture/compare register
Offset: 0x34, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CCR
rw |
|||||||||||||||
capture/compare register
Offset: 0x38, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CCR
rw |
|||||||||||||||
capture/compare register
Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CCR
rw |
|||||||||||||||
capture/compare register
Offset: 0x40, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CCR
rw |
|||||||||||||||
DMA control register
Offset: 0x48, size: 32, reset: 0x00000000, access: read-write
2/2 fields covered.
DMA address for full transfer
Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DMAB
rw |
|||||||||||||||
0x40000000: General purpose timer
77/101 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | SMCR | ||||||||||||||||||||||||||||||||
| 0xc | DIER | ||||||||||||||||||||||||||||||||
| 0x10 | SR | ||||||||||||||||||||||||||||||||
| 0x14 | EGR | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
| 0x1c | CCMR2_Input | ||||||||||||||||||||||||||||||||
| 0x1c | CCMR2_Output | ||||||||||||||||||||||||||||||||
| 0x20 | CCER | ||||||||||||||||||||||||||||||||
| 0x24 | CNT | ||||||||||||||||||||||||||||||||
| 0x28 | PSC | ||||||||||||||||||||||||||||||||
| 0x2c | ARR | ||||||||||||||||||||||||||||||||
| 0x34 | CCR[1] | ||||||||||||||||||||||||||||||||
| 0x38 | CCR[2] | ||||||||||||||||||||||||||||||||
| 0x3c | CCR[3] | ||||||||||||||||||||||||||||||||
| 0x40 | CCR[4] | ||||||||||||||||||||||||||||||||
| 0x48 | DCR | ||||||||||||||||||||||||||||||||
| 0x4c | DMAR | ||||||||||||||||||||||||||||||||
| 0x50 | OR | ||||||||||||||||||||||||||||||||
control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
Bit 0: Counter enable.
Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled
Bit 1: Update disable.
Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled
Bit 2: Update request source.
Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request
Bit 3: One-pulse mode.
Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)
Bit 4: Direction.
Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter
Bits 5-6: Center-aligned mode selection.
Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
Bit 7: Auto-reload preload enable.
Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered
Bits 8-9: Clock division.
Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT
control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
3/3 fields covered.
Bit 3: Capture/compare DMA selection.
Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs
Bits 4-6: Master mode selection.
Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output
Bit 7: TI1 selection.
Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
slave mode control register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
7/7 fields covered.
Bits 0-2: Slave mode selection.
Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Bits 4-6: Trigger selection.
Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)
Bit 7: Master/Slave mode.
Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Bits 8-11: External trigger filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
Bits 12-13: External trigger prescaler.
Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8
Bit 14: External clock enable.
Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
Bit 15: External trigger polarity.
Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge
DMA/Interrupt enable register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
12/12 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TDE
rw |
CC[4]DE
rw |
CC[3]DE
rw |
CC[2]DE
rw |
CC[1]DE
rw |
UDE
rw |
TIE
rw |
CC[4]IE
rw |
CC[3]IE
rw |
CC[2]IE
rw |
CC[1]IE
rw |
UIE
rw |
Bit 0: Update interrupt enable.
Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled
Bit 1: Capture/Compare 1 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 2: Capture/Compare 2 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 3: Capture/Compare 3 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 4: Capture/Compare 4 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 6: Trigger interrupt enable.
Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled
Bit 8: Update DMA request enable.
Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled
Bit 9: Capture/Compare 1 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 10: Capture/Compare 2 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 11: Capture/Compare 3 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 12: Capture/Compare 4 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 14: Trigger DMA request enable.
Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled
status register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
10/10 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CC[4]OF
rw |
CC[3]OF
rw |
CC[2]OF
rw |
CC[1]OF
rw |
TIF
rw |
CC[4]IF
rw |
CC[3]IF
rw |
CC[2]IF
rw |
CC[1]IF
rw |
UIF
rw |
||||||
Bit 0: Update interrupt flag.
Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending
Bit 1: Capture/compare 1 interrupt flag.
Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 2: Capture/compare 2 interrupt flag.
Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 3: Capture/compare 3 interrupt flag.
Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 4: Capture/compare 4 interrupt flag.
Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 6: Trigger interrupt flag.
Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending
Bit 9: Capture/Compare 1 overcapture flag.
Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
Bit 10: Capture/Compare 2 overcapture flag.
Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
Bit 11: Capture/Compare 3 overcapture flag.
Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
Bit 12: Capture/Compare 4 overcapture flag.
Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
event generation register
Offset: 0x14, size: 32, reset: 0x00000000, access: write-only
6/6 fields covered.
Bit 0: Update generation.
Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.
Bit 1: Capture/compare 1 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 2: Capture/compare 2 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 3: Capture/compare 3 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 4: Capture/compare 4 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 6: Trigger generation.
Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
capture/compare mode register 1 (input mode)
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
4/6 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IC[2]F
rw |
IC[2]PSC
rw |
CC[2]S
rw |
IC[1]F
rw |
IC[1]PSC
rw |
CC[1]S
rw |
||||||||||
Bits 0-1: Capture/Compare 1 selection.
Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC
Bits 2-3: Input capture 1 prescaler.
Bits 4-7: Input capture 1 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
Bits 8-9: Capture/Compare 2 selection.
Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC
Bits 10-11: Input capture 2 prescaler.
Bits 12-15: Input capture 2 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
capture/compare mode register 1 (output mode)
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
6/10 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OC[2]CE
rw |
OC[2]M
rw |
OC[2]PE
rw |
OC[2]FE
rw |
CC[2]S
rw |
OC[1]CE
rw |
OC[1]M
rw |
OC[1]PE
rw |
OC[1]FE
rw |
CC[1]S
rw |
||||||
Bits 0-1: Capture/Compare 1 selection.
Allowed values:
0: Output: CC1 channel is configured as output
Bit 2: Output compare 1 fast enable.
Bit 3: Output compare 1 preload enable.
Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event
Bits 4-6: Output compare 1 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1
Bit 7: Output compare 1 clear enable.
Bits 8-9: Capture/Compare 2 selection.
Allowed values:
0: Output: CC1 channel is configured as output
Bit 10: Output compare 2 fast enable.
Bit 11: Output compare 2 preload enable.
Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event
Bits 12-14: Output compare 2 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1
Bit 15: Output compare 2 clear enable.
capture/compare mode register 2 (input mode)
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
6/6 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IC[4]F
rw |
IC[4]PSC
rw |
CC[4]S
rw |
IC[3]F
rw |
IC[3]PSC
rw |
CC[3]S
rw |
||||||||||
Bits 0-1: Capture/Compare 3 selection.
Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC
Bits 2-3: Input capture 3 prescaler.
Allowed values: 0x0-0x3
Bits 4-7: Input capture 3 filter.
Allowed values: 0x0-0xf
Bits 8-9: Capture/Compare 4 selection.
Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC
Bits 10-11: Input capture 4 prescaler.
Allowed values: 0x0-0x3
Bits 12-15: Input capture 4 filter.
Allowed values: 0x0-0xf
capture/compare mode register 2 (output mode)
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
6/10 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OC[4]CE
rw |
OC[4]M
rw |
OC[4]PE
rw |
OC[4]FE
rw |
CC[4]S
rw |
OC[3]CE
rw |
OC[3]M
rw |
OC[3]PE
rw |
OC[3]FE
rw |
CC[3]S
rw |
||||||
Bits 0-1: Capture/Compare 3 selection.
Allowed values:
0: Output: CC3 channel is configured as output
Bit 2: Output compare 3 fast enable.
Bit 3: Output compare 3 preload enable.
Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event
Bits 4-6: Output compare 3 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1
Bit 7: Output compare 3 clear enable.
Bits 8-9: Capture/Compare 4 selection.
Allowed values:
0: Output: CC3 channel is configured as output
Bit 10: Output compare 4 fast enable.
Bit 11: Output compare 4 preload enable.
Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event
Bits 12-14: Output compare 4 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1
Bit 15: Output compare 4 clear enable.
capture/compare enable register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
0/12 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CC[4]NP
rw |
CC[4]P
rw |
CC[4]E
rw |
CC[3]NP
rw |
CC[3]P
rw |
CC[3]E
rw |
CC[2]NP
rw |
CC[2]P
rw |
CC[2]E
rw |
CC[1]NP
rw |
CC[1]P
rw |
CC[1]E
rw |
Bit 0: Capture/Compare 1 output enable.
Bit 1: Capture/Compare 1 output Polarity.
Bit 3: Capture/Compare 1 output Polarity.
Bit 4: Capture/Compare 2 output enable.
Bit 5: Capture/Compare 2 output Polarity.
Bit 7: Capture/Compare 2 output Polarity.
Bit 8: Capture/Compare 3 output enable.
Bit 9: Capture/Compare 3 output Polarity.
Bit 11: Capture/Compare 3 output Polarity.
Bit 12: Capture/Compare 4 output enable.
Bit 13: Capture/Compare 4 output Polarity.
Bit 15: Capture/Compare 4 output Polarity.
prescaler
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
capture/compare register
Offset: 0x34, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
capture/compare register
Offset: 0x38, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
capture/compare register
Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
capture/compare register
Offset: 0x40, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
DMA control register
Offset: 0x48, size: 32, reset: 0x00000000, access: read-write
2/2 fields covered.
DMA address for full transfer
Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DMAB
rw |
|||||||||||||||
option register
Offset: 0x50, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ITR1_RMP
rw |
|||||||||||||||
0x40000400: General purpose timer
77/100 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | SMCR | ||||||||||||||||||||||||||||||||
| 0xc | DIER | ||||||||||||||||||||||||||||||||
| 0x10 | SR | ||||||||||||||||||||||||||||||||
| 0x14 | EGR | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
| 0x1c | CCMR2_Input | ||||||||||||||||||||||||||||||||
| 0x1c | CCMR2_Output | ||||||||||||||||||||||||||||||||
| 0x20 | CCER | ||||||||||||||||||||||||||||||||
| 0x24 | CNT | ||||||||||||||||||||||||||||||||
| 0x28 | PSC | ||||||||||||||||||||||||||||||||
| 0x2c | ARR | ||||||||||||||||||||||||||||||||
| 0x34 | CCR[1] | ||||||||||||||||||||||||||||||||
| 0x38 | CCR[2] | ||||||||||||||||||||||||||||||||
| 0x3c | CCR[3] | ||||||||||||||||||||||||||||||||
| 0x40 | CCR[4] | ||||||||||||||||||||||||||||||||
| 0x48 | DCR | ||||||||||||||||||||||||||||||||
| 0x4c | DMAR | ||||||||||||||||||||||||||||||||
control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
Bit 0: Counter enable.
Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled
Bit 1: Update disable.
Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled
Bit 2: Update request source.
Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request
Bit 3: One-pulse mode.
Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)
Bit 4: Direction.
Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter
Bits 5-6: Center-aligned mode selection.
Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
Bit 7: Auto-reload preload enable.
Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered
Bits 8-9: Clock division.
Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT
control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
3/3 fields covered.
Bit 3: Capture/compare DMA selection.
Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs
Bits 4-6: Master mode selection.
Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output
Bit 7: TI1 selection.
Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
slave mode control register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
7/7 fields covered.
Bits 0-2: Slave mode selection.
Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Bits 4-6: Trigger selection.
Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)
Bit 7: Master/Slave mode.
Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Bits 8-11: External trigger filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
Bits 12-13: External trigger prescaler.
Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8
Bit 14: External clock enable.
Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
Bit 15: External trigger polarity.
Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge
DMA/Interrupt enable register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
12/12 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TDE
rw |
CC[4]DE
rw |
CC[3]DE
rw |
CC[2]DE
rw |
CC[1]DE
rw |
UDE
rw |
TIE
rw |
CC[4]IE
rw |
CC[3]IE
rw |
CC[2]IE
rw |
CC[1]IE
rw |
UIE
rw |
Bit 0: Update interrupt enable.
Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled
Bit 1: Capture/Compare 1 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 2: Capture/Compare 2 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 3: Capture/Compare 3 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 4: Capture/Compare 4 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 6: Trigger interrupt enable.
Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled
Bit 8: Update DMA request enable.
Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled
Bit 9: Capture/Compare 1 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 10: Capture/Compare 2 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 11: Capture/Compare 3 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 12: Capture/Compare 4 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 14: Trigger DMA request enable.
Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled
status register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
10/10 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CC[4]OF
rw |
CC[3]OF
rw |
CC[2]OF
rw |
CC[1]OF
rw |
TIF
rw |
CC[4]IF
rw |
CC[3]IF
rw |
CC[2]IF
rw |
CC[1]IF
rw |
UIF
rw |
||||||
Bit 0: Update interrupt flag.
Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending
Bit 1: Capture/compare 1 interrupt flag.
Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 2: Capture/compare 2 interrupt flag.
Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 3: Capture/compare 3 interrupt flag.
Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 4: Capture/compare 4 interrupt flag.
Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 6: Trigger interrupt flag.
Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending
Bit 9: Capture/Compare 1 overcapture flag.
Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
Bit 10: Capture/Compare 2 overcapture flag.
Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
Bit 11: Capture/Compare 3 overcapture flag.
Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
Bit 12: Capture/Compare 4 overcapture flag.
Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
event generation register
Offset: 0x14, size: 32, reset: 0x00000000, access: write-only
6/6 fields covered.
Bit 0: Update generation.
Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.
Bit 1: Capture/compare 1 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 2: Capture/compare 2 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 3: Capture/compare 3 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 4: Capture/compare 4 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 6: Trigger generation.
Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
capture/compare mode register 1 (input mode)
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
4/6 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IC[2]F
rw |
IC[2]PSC
rw |
CC[2]S
rw |
IC[1]F
rw |
IC[1]PSC
rw |
CC[1]S
rw |
||||||||||
Bits 0-1: Capture/Compare 1 selection.
Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC
Bits 2-3: Input capture 1 prescaler.
Bits 4-7: Input capture 1 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
Bits 8-9: Capture/Compare 2 selection.
Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC
Bits 10-11: Input capture 2 prescaler.
Bits 12-15: Input capture 2 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
capture/compare mode register 1 (output mode)
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
6/10 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OC[2]CE
rw |
OC[2]M
rw |
OC[2]PE
rw |
OC[2]FE
rw |
CC[2]S
rw |
OC[1]CE
rw |
OC[1]M
rw |
OC[1]PE
rw |
OC[1]FE
rw |
CC[1]S
rw |
||||||
Bits 0-1: Capture/Compare 1 selection.
Allowed values:
0: Output: CC1 channel is configured as output
Bit 2: Output compare 1 fast enable.
Bit 3: Output compare 1 preload enable.
Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event
Bits 4-6: Output compare 1 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1
Bit 7: Output compare 1 clear enable.
Bits 8-9: Capture/Compare 2 selection.
Allowed values:
0: Output: CC1 channel is configured as output
Bit 10: Output compare 2 fast enable.
Bit 11: Output compare 2 preload enable.
Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event
Bits 12-14: Output compare 2 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1
Bit 15: Output compare 2 clear enable.
capture/compare mode register 2 (input mode)
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
6/6 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IC[4]F
rw |
IC[4]PSC
rw |
CC[4]S
rw |
IC[3]F
rw |
IC[3]PSC
rw |
CC[3]S
rw |
||||||||||
Bits 0-1: Capture/Compare 3 selection.
Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC
Bits 2-3: Input capture 3 prescaler.
Allowed values: 0x0-0x3
Bits 4-7: Input capture 3 filter.
Allowed values: 0x0-0xf
Bits 8-9: Capture/Compare 4 selection.
Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC
Bits 10-11: Input capture 4 prescaler.
Allowed values: 0x0-0x3
Bits 12-15: Input capture 4 filter.
Allowed values: 0x0-0xf
capture/compare mode register 2 (output mode)
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
6/10 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OC[4]CE
rw |
OC[4]M
rw |
OC[4]PE
rw |
OC[4]FE
rw |
CC[4]S
rw |
OC[3]CE
rw |
OC[3]M
rw |
OC[3]PE
rw |
OC[3]FE
rw |
CC[3]S
rw |
||||||
Bits 0-1: Capture/Compare 3 selection.
Allowed values:
0: Output: CC3 channel is configured as output
Bit 2: Output compare 3 fast enable.
Bit 3: Output compare 3 preload enable.
Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event
Bits 4-6: Output compare 3 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1
Bit 7: Output compare 3 clear enable.
Bits 8-9: Capture/Compare 4 selection.
Allowed values:
0: Output: CC3 channel is configured as output
Bit 10: Output compare 4 fast enable.
Bit 11: Output compare 4 preload enable.
Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event
Bits 12-14: Output compare 4 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1
Bit 15: Output compare 4 clear enable.
capture/compare enable register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
0/12 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CC[4]NP
rw |
CC[4]P
rw |
CC[4]E
rw |
CC[3]NP
rw |
CC[3]P
rw |
CC[3]E
rw |
CC[2]NP
rw |
CC[2]P
rw |
CC[2]E
rw |
CC[1]NP
rw |
CC[1]P
rw |
CC[1]E
rw |
Bit 0: Capture/Compare 1 output enable.
Bit 1: Capture/Compare 1 output Polarity.
Bit 3: Capture/Compare 1 output Polarity.
Bit 4: Capture/Compare 2 output enable.
Bit 5: Capture/Compare 2 output Polarity.
Bit 7: Capture/Compare 2 output Polarity.
Bit 8: Capture/Compare 3 output enable.
Bit 9: Capture/Compare 3 output Polarity.
Bit 11: Capture/Compare 3 output Polarity.
Bit 12: Capture/Compare 4 output enable.
Bit 13: Capture/Compare 4 output Polarity.
Bit 15: Capture/Compare 4 output Polarity.
counter
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ARR
rw |
|||||||||||||||
capture/compare register
Offset: 0x34, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CCR
rw |
|||||||||||||||
capture/compare register
Offset: 0x38, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CCR
rw |
|||||||||||||||
capture/compare register
Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CCR
rw |
|||||||||||||||
capture/compare register
Offset: 0x40, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CCR
rw |
|||||||||||||||
DMA control register
Offset: 0x48, size: 32, reset: 0x00000000, access: read-write
2/2 fields covered.
DMA address for full transfer
Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DMAB
rw |
|||||||||||||||
0x40000800: General purpose timer
77/100 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | SMCR | ||||||||||||||||||||||||||||||||
| 0xc | DIER | ||||||||||||||||||||||||||||||||
| 0x10 | SR | ||||||||||||||||||||||||||||||||
| 0x14 | EGR | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
| 0x1c | CCMR2_Input | ||||||||||||||||||||||||||||||||
| 0x1c | CCMR2_Output | ||||||||||||||||||||||||||||||||
| 0x20 | CCER | ||||||||||||||||||||||||||||||||
| 0x24 | CNT | ||||||||||||||||||||||||||||||||
| 0x28 | PSC | ||||||||||||||||||||||||||||||||
| 0x2c | ARR | ||||||||||||||||||||||||||||||||
| 0x34 | CCR[1] | ||||||||||||||||||||||||||||||||
| 0x38 | CCR[2] | ||||||||||||||||||||||||||||||||
| 0x3c | CCR[3] | ||||||||||||||||||||||||||||||||
| 0x40 | CCR[4] | ||||||||||||||||||||||||||||||||
| 0x48 | DCR | ||||||||||||||||||||||||||||||||
| 0x4c | DMAR | ||||||||||||||||||||||||||||||||
control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
Bit 0: Counter enable.
Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled
Bit 1: Update disable.
Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled
Bit 2: Update request source.
Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request
Bit 3: One-pulse mode.
Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)
Bit 4: Direction.
Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter
Bits 5-6: Center-aligned mode selection.
Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
Bit 7: Auto-reload preload enable.
Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered
Bits 8-9: Clock division.
Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT
control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
3/3 fields covered.
Bit 3: Capture/compare DMA selection.
Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs
Bits 4-6: Master mode selection.
Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output
Bit 7: TI1 selection.
Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
slave mode control register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
7/7 fields covered.
Bits 0-2: Slave mode selection.
Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Bits 4-6: Trigger selection.
Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)
Bit 7: Master/Slave mode.
Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Bits 8-11: External trigger filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
Bits 12-13: External trigger prescaler.
Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8
Bit 14: External clock enable.
Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
Bit 15: External trigger polarity.
Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge
DMA/Interrupt enable register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
12/12 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TDE
rw |
CC[4]DE
rw |
CC[3]DE
rw |
CC[2]DE
rw |
CC[1]DE
rw |
UDE
rw |
TIE
rw |
CC[4]IE
rw |
CC[3]IE
rw |
CC[2]IE
rw |
CC[1]IE
rw |
UIE
rw |
Bit 0: Update interrupt enable.
Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled
Bit 1: Capture/Compare 1 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 2: Capture/Compare 2 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 3: Capture/Compare 3 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 4: Capture/Compare 4 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 6: Trigger interrupt enable.
Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled
Bit 8: Update DMA request enable.
Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled
Bit 9: Capture/Compare 1 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 10: Capture/Compare 2 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 11: Capture/Compare 3 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 12: Capture/Compare 4 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 14: Trigger DMA request enable.
Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled
status register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
10/10 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CC[4]OF
rw |
CC[3]OF
rw |
CC[2]OF
rw |
CC[1]OF
rw |
TIF
rw |
CC[4]IF
rw |
CC[3]IF
rw |
CC[2]IF
rw |
CC[1]IF
rw |
UIF
rw |
||||||
Bit 0: Update interrupt flag.
Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending
Bit 1: Capture/compare 1 interrupt flag.
Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 2: Capture/compare 2 interrupt flag.
Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 3: Capture/compare 3 interrupt flag.
Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 4: Capture/compare 4 interrupt flag.
Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 6: Trigger interrupt flag.
Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending
Bit 9: Capture/Compare 1 overcapture flag.
Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
Bit 10: Capture/Compare 2 overcapture flag.
Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
Bit 11: Capture/Compare 3 overcapture flag.
Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
Bit 12: Capture/Compare 4 overcapture flag.
Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
event generation register
Offset: 0x14, size: 32, reset: 0x00000000, access: write-only
6/6 fields covered.
Bit 0: Update generation.
Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.
Bit 1: Capture/compare 1 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 2: Capture/compare 2 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 3: Capture/compare 3 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 4: Capture/compare 4 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 6: Trigger generation.
Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
capture/compare mode register 1 (input mode)
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
4/6 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IC[2]F
rw |
IC[2]PSC
rw |
CC[2]S
rw |
IC[1]F
rw |
IC[1]PSC
rw |
CC[1]S
rw |
||||||||||
Bits 0-1: Capture/Compare 1 selection.
Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC
Bits 2-3: Input capture 1 prescaler.
Bits 4-7: Input capture 1 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
Bits 8-9: Capture/Compare 2 selection.
Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC
Bits 10-11: Input capture 2 prescaler.
Bits 12-15: Input capture 2 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
capture/compare mode register 1 (output mode)
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
6/10 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OC[2]CE
rw |
OC[2]M
rw |
OC[2]PE
rw |
OC[2]FE
rw |
CC[2]S
rw |
OC[1]CE
rw |
OC[1]M
rw |
OC[1]PE
rw |
OC[1]FE
rw |
CC[1]S
rw |
||||||
Bits 0-1: Capture/Compare 1 selection.
Allowed values:
0: Output: CC1 channel is configured as output
Bit 2: Output compare 1 fast enable.
Bit 3: Output compare 1 preload enable.
Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event
Bits 4-6: Output compare 1 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1
Bit 7: Output compare 1 clear enable.
Bits 8-9: Capture/Compare 2 selection.
Allowed values:
0: Output: CC1 channel is configured as output
Bit 10: Output compare 2 fast enable.
Bit 11: Output compare 2 preload enable.
Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event
Bits 12-14: Output compare 2 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1
Bit 15: Output compare 2 clear enable.
capture/compare mode register 2 (input mode)
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
6/6 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IC[4]F
rw |
IC[4]PSC
rw |
CC[4]S
rw |
IC[3]F
rw |
IC[3]PSC
rw |
CC[3]S
rw |
||||||||||
Bits 0-1: Capture/Compare 3 selection.
Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC
Bits 2-3: Input capture 3 prescaler.
Allowed values: 0x0-0x3
Bits 4-7: Input capture 3 filter.
Allowed values: 0x0-0xf
Bits 8-9: Capture/Compare 4 selection.
Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC
Bits 10-11: Input capture 4 prescaler.
Allowed values: 0x0-0x3
Bits 12-15: Input capture 4 filter.
Allowed values: 0x0-0xf
capture/compare mode register 2 (output mode)
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
6/10 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OC[4]CE
rw |
OC[4]M
rw |
OC[4]PE
rw |
OC[4]FE
rw |
CC[4]S
rw |
OC[3]CE
rw |
OC[3]M
rw |
OC[3]PE
rw |
OC[3]FE
rw |
CC[3]S
rw |
||||||
Bits 0-1: Capture/Compare 3 selection.
Allowed values:
0: Output: CC3 channel is configured as output
Bit 2: Output compare 3 fast enable.
Bit 3: Output compare 3 preload enable.
Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event
Bits 4-6: Output compare 3 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1
Bit 7: Output compare 3 clear enable.
Bits 8-9: Capture/Compare 4 selection.
Allowed values:
0: Output: CC3 channel is configured as output
Bit 10: Output compare 4 fast enable.
Bit 11: Output compare 4 preload enable.
Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event
Bits 12-14: Output compare 4 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1
Bit 15: Output compare 4 clear enable.
capture/compare enable register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
0/12 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CC[4]NP
rw |
CC[4]P
rw |
CC[4]E
rw |
CC[3]NP
rw |
CC[3]P
rw |
CC[3]E
rw |
CC[2]NP
rw |
CC[2]P
rw |
CC[2]E
rw |
CC[1]NP
rw |
CC[1]P
rw |
CC[1]E
rw |
Bit 0: Capture/Compare 1 output enable.
Bit 1: Capture/Compare 1 output Polarity.
Bit 3: Capture/Compare 1 output Polarity.
Bit 4: Capture/Compare 2 output enable.
Bit 5: Capture/Compare 2 output Polarity.
Bit 7: Capture/Compare 2 output Polarity.
Bit 8: Capture/Compare 3 output enable.
Bit 9: Capture/Compare 3 output Polarity.
Bit 11: Capture/Compare 3 output Polarity.
Bit 12: Capture/Compare 4 output enable.
Bit 13: Capture/Compare 4 output Polarity.
Bit 15: Capture/Compare 4 output Polarity.
counter
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ARR
rw |
|||||||||||||||
capture/compare register
Offset: 0x34, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CCR
rw |
|||||||||||||||
capture/compare register
Offset: 0x38, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CCR
rw |
|||||||||||||||
capture/compare register
Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CCR
rw |
|||||||||||||||
capture/compare register
Offset: 0x40, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CCR
rw |
|||||||||||||||
DMA control register
Offset: 0x48, size: 32, reset: 0x00000000, access: read-write
2/2 fields covered.
DMA address for full transfer
Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DMAB
rw |
|||||||||||||||
0x40000c00: General purpose timer
77/101 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | SMCR | ||||||||||||||||||||||||||||||||
| 0xc | DIER | ||||||||||||||||||||||||||||||||
| 0x10 | SR | ||||||||||||||||||||||||||||||||
| 0x14 | EGR | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
| 0x1c | CCMR2_Input | ||||||||||||||||||||||||||||||||
| 0x1c | CCMR2_Output | ||||||||||||||||||||||||||||||||
| 0x20 | CCER | ||||||||||||||||||||||||||||||||
| 0x24 | CNT | ||||||||||||||||||||||||||||||||
| 0x28 | PSC | ||||||||||||||||||||||||||||||||
| 0x2c | ARR | ||||||||||||||||||||||||||||||||
| 0x34 | CCR[1] | ||||||||||||||||||||||||||||||||
| 0x38 | CCR[2] | ||||||||||||||||||||||||||||||||
| 0x3c | CCR[3] | ||||||||||||||||||||||||||||||||
| 0x40 | CCR[4] | ||||||||||||||||||||||||||||||||
| 0x48 | DCR | ||||||||||||||||||||||||||||||||
| 0x4c | DMAR | ||||||||||||||||||||||||||||||||
| 0x50 | OR | ||||||||||||||||||||||||||||||||
control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
Bit 0: Counter enable.
Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled
Bit 1: Update disable.
Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled
Bit 2: Update request source.
Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request
Bit 3: One-pulse mode.
Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)
Bit 4: Direction.
Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter
Bits 5-6: Center-aligned mode selection.
Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
Bit 7: Auto-reload preload enable.
Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered
Bits 8-9: Clock division.
Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT
control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
3/3 fields covered.
Bit 3: Capture/compare DMA selection.
Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs
Bits 4-6: Master mode selection.
Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output
Bit 7: TI1 selection.
Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
slave mode control register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
7/7 fields covered.
Bits 0-2: Slave mode selection.
Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Bits 4-6: Trigger selection.
Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)
Bit 7: Master/Slave mode.
Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Bits 8-11: External trigger filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
Bits 12-13: External trigger prescaler.
Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8
Bit 14: External clock enable.
Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
Bit 15: External trigger polarity.
Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge
DMA/Interrupt enable register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
12/12 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TDE
rw |
CC[4]DE
rw |
CC[3]DE
rw |
CC[2]DE
rw |
CC[1]DE
rw |
UDE
rw |
TIE
rw |
CC[4]IE
rw |
CC[3]IE
rw |
CC[2]IE
rw |
CC[1]IE
rw |
UIE
rw |
Bit 0: Update interrupt enable.
Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled
Bit 1: Capture/Compare 1 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 2: Capture/Compare 2 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 3: Capture/Compare 3 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 4: Capture/Compare 4 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 6: Trigger interrupt enable.
Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled
Bit 8: Update DMA request enable.
Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled
Bit 9: Capture/Compare 1 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 10: Capture/Compare 2 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 11: Capture/Compare 3 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 12: Capture/Compare 4 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 14: Trigger DMA request enable.
Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled
status register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
10/10 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CC[4]OF
rw |
CC[3]OF
rw |
CC[2]OF
rw |
CC[1]OF
rw |
TIF
rw |
CC[4]IF
rw |
CC[3]IF
rw |
CC[2]IF
rw |
CC[1]IF
rw |
UIF
rw |
||||||
Bit 0: Update interrupt flag.
Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending
Bit 1: Capture/compare 1 interrupt flag.
Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 2: Capture/compare 2 interrupt flag.
Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 3: Capture/compare 3 interrupt flag.
Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 4: Capture/compare 4 interrupt flag.
Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 6: Trigger interrupt flag.
Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending
Bit 9: Capture/Compare 1 overcapture flag.
Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
Bit 10: Capture/Compare 2 overcapture flag.
Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
Bit 11: Capture/Compare 3 overcapture flag.
Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
Bit 12: Capture/Compare 4 overcapture flag.
Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
event generation register
Offset: 0x14, size: 32, reset: 0x00000000, access: write-only
6/6 fields covered.
Bit 0: Update generation.
Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.
Bit 1: Capture/compare 1 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 2: Capture/compare 2 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 3: Capture/compare 3 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 4: Capture/compare 4 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 6: Trigger generation.
Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
capture/compare mode register 1 (input mode)
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
4/6 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IC[2]F
rw |
IC[2]PSC
rw |
CC[2]S
rw |
IC[1]F
rw |
IC[1]PSC
rw |
CC[1]S
rw |
||||||||||
Bits 0-1: Capture/Compare 1 selection.
Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC
Bits 2-3: Input capture 1 prescaler.
Bits 4-7: Input capture 1 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
Bits 8-9: Capture/Compare 2 selection.
Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC
Bits 10-11: Input capture 2 prescaler.
Bits 12-15: Input capture 2 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
capture/compare mode register 1 (output mode)
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
6/10 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OC[2]CE
rw |
OC[2]M
rw |
OC[2]PE
rw |
OC[2]FE
rw |
CC[2]S
rw |
OC[1]CE
rw |
OC[1]M
rw |
OC[1]PE
rw |
OC[1]FE
rw |
CC[1]S
rw |
||||||
Bits 0-1: Capture/Compare 1 selection.
Allowed values:
0: Output: CC1 channel is configured as output
Bit 2: Output compare 1 fast enable.
Bit 3: Output compare 1 preload enable.
Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event
Bits 4-6: Output compare 1 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1
Bit 7: Output compare 1 clear enable.
Bits 8-9: Capture/Compare 2 selection.
Allowed values:
0: Output: CC1 channel is configured as output
Bit 10: Output compare 2 fast enable.
Bit 11: Output compare 2 preload enable.
Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event
Bits 12-14: Output compare 2 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1
Bit 15: Output compare 2 clear enable.
capture/compare mode register 2 (input mode)
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
6/6 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IC[4]F
rw |
IC[4]PSC
rw |
CC[4]S
rw |
IC[3]F
rw |
IC[3]PSC
rw |
CC[3]S
rw |
||||||||||
Bits 0-1: Capture/Compare 3 selection.
Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC
Bits 2-3: Input capture 3 prescaler.
Allowed values: 0x0-0x3
Bits 4-7: Input capture 3 filter.
Allowed values: 0x0-0xf
Bits 8-9: Capture/Compare 4 selection.
Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC
Bits 10-11: Input capture 4 prescaler.
Allowed values: 0x0-0x3
Bits 12-15: Input capture 4 filter.
Allowed values: 0x0-0xf
capture/compare mode register 2 (output mode)
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
6/10 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OC[4]CE
rw |
OC[4]M
rw |
OC[4]PE
rw |
OC[4]FE
rw |
CC[4]S
rw |
OC[3]CE
rw |
OC[3]M
rw |
OC[3]PE
rw |
OC[3]FE
rw |
CC[3]S
rw |
||||||
Bits 0-1: Capture/Compare 3 selection.
Allowed values:
0: Output: CC3 channel is configured as output
Bit 2: Output compare 3 fast enable.
Bit 3: Output compare 3 preload enable.
Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event
Bits 4-6: Output compare 3 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1
Bit 7: Output compare 3 clear enable.
Bits 8-9: Capture/Compare 4 selection.
Allowed values:
0: Output: CC3 channel is configured as output
Bit 10: Output compare 4 fast enable.
Bit 11: Output compare 4 preload enable.
Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event
Bits 12-14: Output compare 4 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1
Bit 15: Output compare 4 clear enable.
capture/compare enable register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
0/12 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CC[4]NP
rw |
CC[4]P
rw |
CC[4]E
rw |
CC[3]NP
rw |
CC[3]P
rw |
CC[3]E
rw |
CC[2]NP
rw |
CC[2]P
rw |
CC[2]E
rw |
CC[1]NP
rw |
CC[1]P
rw |
CC[1]E
rw |
Bit 0: Capture/Compare 1 output enable.
Bit 1: Capture/Compare 1 output Polarity.
Bit 3: Capture/Compare 1 output Polarity.
Bit 4: Capture/Compare 2 output enable.
Bit 5: Capture/Compare 2 output Polarity.
Bit 7: Capture/Compare 2 output Polarity.
Bit 8: Capture/Compare 3 output enable.
Bit 9: Capture/Compare 3 output Polarity.
Bit 11: Capture/Compare 3 output Polarity.
Bit 12: Capture/Compare 4 output enable.
Bit 13: Capture/Compare 4 output Polarity.
Bit 15: Capture/Compare 4 output Polarity.
prescaler
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
capture/compare register
Offset: 0x34, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
capture/compare register
Offset: 0x38, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
capture/compare register
Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
capture/compare register
Offset: 0x40, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
DMA control register
Offset: 0x48, size: 32, reset: 0x00000000, access: read-write
2/2 fields covered.
DMA address for full transfer
Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DMAB
rw |
|||||||||||||||
option register
Offset: 0x50, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IT4_RMP
rw |
|||||||||||||||
0x40001000: Basic timers
13/13 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0xc | DIER | ||||||||||||||||||||||||||||||||
| 0x10 | SR | ||||||||||||||||||||||||||||||||
| 0x14 | EGR | ||||||||||||||||||||||||||||||||
| 0x24 | CNT | ||||||||||||||||||||||||||||||||
| 0x28 | PSC | ||||||||||||||||||||||||||||||||
| 0x2c | ARR | ||||||||||||||||||||||||||||||||
control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
5/5 fields covered.
Bit 0: Counter enable.
Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled
Bit 1: Update disable.
Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled
Bit 2: Update request source.
Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request
Bit 3: One-pulse mode.
Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)
Bit 7: Auto-reload preload enable.
Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered
control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MMS
rw |
|||||||||||||||
DMA/Interrupt enable register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
2/2 fields covered.
status register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UIF
rw |
|||||||||||||||
event generation register
Offset: 0x14, size: 32, reset: 0x00000000, access: write-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UG
w |
|||||||||||||||
counter
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ARR
rw |
|||||||||||||||
0x40001400: Basic timers
13/13 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0xc | DIER | ||||||||||||||||||||||||||||||||
| 0x10 | SR | ||||||||||||||||||||||||||||||||
| 0x14 | EGR | ||||||||||||||||||||||||||||||||
| 0x24 | CNT | ||||||||||||||||||||||||||||||||
| 0x28 | PSC | ||||||||||||||||||||||||||||||||
| 0x2c | ARR | ||||||||||||||||||||||||||||||||
control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
5/5 fields covered.
Bit 0: Counter enable.
Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled
Bit 1: Update disable.
Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled
Bit 2: Update request source.
Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request
Bit 3: One-pulse mode.
Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)
Bit 7: Auto-reload preload enable.
Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered
control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MMS
rw |
|||||||||||||||
DMA/Interrupt enable register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
2/2 fields covered.
status register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UIF
rw |
|||||||||||||||
event generation register
Offset: 0x14, size: 32, reset: 0x00000000, access: write-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UG
w |
|||||||||||||||
counter
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ARR
rw |
|||||||||||||||
0x40024000: Touch sensing controller
14/170 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR | ||||||||||||||||||||||||||||||||
| 0x4 | IER | ||||||||||||||||||||||||||||||||
| 0x8 | ICR | ||||||||||||||||||||||||||||||||
| 0xc | ISR | ||||||||||||||||||||||||||||||||
| 0x10 | IOHCR | ||||||||||||||||||||||||||||||||
| 0x18 | IOASCR | ||||||||||||||||||||||||||||||||
| 0x20 | IOSCR | ||||||||||||||||||||||||||||||||
| 0x28 | IOCCR | ||||||||||||||||||||||||||||||||
| 0x30 | IOGCSR | ||||||||||||||||||||||||||||||||
| 0x34 | IOG[1]CR | ||||||||||||||||||||||||||||||||
| 0x38 | IOG[2]CR | ||||||||||||||||||||||||||||||||
| 0x3c | IOG[3]CR | ||||||||||||||||||||||||||||||||
| 0x40 | IOG[4]CR | ||||||||||||||||||||||||||||||||
| 0x44 | IOG[5]CR | ||||||||||||||||||||||||||||||||
| 0x48 | IOG[6]CR | ||||||||||||||||||||||||||||||||
| 0x4c | IOG[7]CR | ||||||||||||||||||||||||||||||||
| 0x50 | IOG[8]CR | ||||||||||||||||||||||||||||||||
control register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
0/12 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CTPH
rw |
CTPL
rw |
SSD
rw |
SSE
rw |
||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SSPSC
rw |
PGPSC
rw |
MCV
rw |
IODEF
rw |
SYNCPOL
rw |
AM
rw |
START
rw |
TSCE
rw |
||||||||
Bit 0: Touch sensing controller enable.
Bit 1: Start a new acquisition.
Bit 2: Acquisition mode.
Bit 3: Synchronization pin polarity.
Bit 4: I/O Default mode.
Bits 5-7: Max count value.
Bits 12-14: pulse generator prescaler.
Bit 15: Spread spectrum prescaler.
Bit 16: Spread spectrum enable.
Bits 17-23: Spread spectrum deviation.
Bits 24-27: Charge transfer pulse low.
Bits 28-31: Charge transfer pulse high.
interrupt enable register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
interrupt clear register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
interrupt status register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
I/O hysteresis control register
Offset: 0x10, size: 32, reset: 0xFFFFFFFF, access: read-write
0/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
G8_IO4
rw |
G8_IO3
rw |
G8_IO2
rw |
G8_IO1
rw |
G7_IO4
rw |
G7_IO3
rw |
G7_IO2
rw |
G7_IO1
rw |
G6_IO4
rw |
G6_IO3
rw |
G6_IO2
rw |
G6_IO1
rw |
G5_IO4
rw |
G5_IO3
rw |
G5_IO2
rw |
G5_IO1
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
G4_IO4
rw |
G4_IO3
rw |
G4_IO2
rw |
G4_IO1
rw |
G3_IO4
rw |
G3_IO3
rw |
G3_IO2
rw |
G3_IO1
rw |
G2_IO4
rw |
G2_IO3
rw |
G2_IO2
rw |
G2_IO1
rw |
G1_IO4
rw |
G1_IO3
rw |
G1_IO2
rw |
G1_IO1
rw |
Bit 0: G1_IO1 Schmitt trigger hysteresis mode.
Bit 1: G1_IO2 Schmitt trigger hysteresis mode.
Bit 2: G1_IO3 Schmitt trigger hysteresis mode.
Bit 3: G1_IO4 Schmitt trigger hysteresis mode.
Bit 4: G2_IO1 Schmitt trigger hysteresis mode.
Bit 5: G2_IO2 Schmitt trigger hysteresis mode.
Bit 6: G2_IO3 Schmitt trigger hysteresis mode.
Bit 7: G2_IO4 Schmitt trigger hysteresis mode.
Bit 8: G3_IO1 Schmitt trigger hysteresis mode.
Bit 9: G3_IO2 Schmitt trigger hysteresis mode.
Bit 10: G3_IO3 Schmitt trigger hysteresis mode.
Bit 11: G3_IO4 Schmitt trigger hysteresis mode.
Bit 12: G4_IO1 Schmitt trigger hysteresis mode.
Bit 13: G4_IO2 Schmitt trigger hysteresis mode.
Bit 14: G4_IO3 Schmitt trigger hysteresis mode.
Bit 15: G4_IO4 Schmitt trigger hysteresis mode.
Bit 16: G5_IO1 Schmitt trigger hysteresis mode.
Bit 17: G5_IO2 Schmitt trigger hysteresis mode.
Bit 18: G5_IO3 Schmitt trigger hysteresis mode.
Bit 19: G5_IO4 Schmitt trigger hysteresis mode.
Bit 20: G6_IO1 Schmitt trigger hysteresis mode.
Bit 21: G6_IO2 Schmitt trigger hysteresis mode.
Bit 22: G6_IO3 Schmitt trigger hysteresis mode.
Bit 23: G6_IO4 Schmitt trigger hysteresis mode.
Bit 24: G7_IO1 Schmitt trigger hysteresis mode.
Bit 25: G7_IO2 Schmitt trigger hysteresis mode.
Bit 26: G7_IO3 Schmitt trigger hysteresis mode.
Bit 27: G7_IO4 Schmitt trigger hysteresis mode.
Bit 28: G8_IO1 Schmitt trigger hysteresis mode.
Bit 29: G8_IO2 Schmitt trigger hysteresis mode.
Bit 30: G8_IO3 Schmitt trigger hysteresis mode.
Bit 31: G8_IO4 Schmitt trigger hysteresis mode.
I/O analog switch control register
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
0/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
G8_IO4
rw |
G8_IO3
rw |
G8_IO2
rw |
G8_IO1
rw |
G7_IO4
rw |
G7_IO3
rw |
G7_IO2
rw |
G7_IO1
rw |
G6_IO4
rw |
G6_IO3
rw |
G6_IO2
rw |
G6_IO1
rw |
G5_IO4
rw |
G5_IO3
rw |
G5_IO2
rw |
G5_IO1
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
G4_IO4
rw |
G4_IO3
rw |
G4_IO2
rw |
G4_IO1
rw |
G3_IO4
rw |
G3_IO3
rw |
G3_IO2
rw |
G3_IO1
rw |
G2_IO4
rw |
G2_IO3
rw |
G2_IO2
rw |
G2_IO1
rw |
G1_IO4
rw |
G1_IO3
rw |
G1_IO2
rw |
G1_IO1
rw |
Bit 0: G1_IO1 analog switch enable.
Bit 1: G1_IO2 analog switch enable.
Bit 2: G1_IO3 analog switch enable.
Bit 3: G1_IO4 analog switch enable.
Bit 4: G2_IO1 analog switch enable.
Bit 5: G2_IO2 analog switch enable.
Bit 6: G2_IO3 analog switch enable.
Bit 7: G2_IO4 analog switch enable.
Bit 8: G3_IO1 analog switch enable.
Bit 9: G3_IO2 analog switch enable.
Bit 10: G3_IO3 analog switch enable.
Bit 11: G3_IO4 analog switch enable.
Bit 12: G4_IO1 analog switch enable.
Bit 13: G4_IO2 analog switch enable.
Bit 14: G4_IO3 analog switch enable.
Bit 15: G4_IO4 analog switch enable.
Bit 16: G5_IO1 analog switch enable.
Bit 17: G5_IO2 analog switch enable.
Bit 18: G5_IO3 analog switch enable.
Bit 19: G5_IO4 analog switch enable.
Bit 20: G6_IO1 analog switch enable.
Bit 21: G6_IO2 analog switch enable.
Bit 22: G6_IO3 analog switch enable.
Bit 23: G6_IO4 analog switch enable.
Bit 24: G7_IO1 analog switch enable.
Bit 25: G7_IO2 analog switch enable.
Bit 26: G7_IO3 analog switch enable.
Bit 27: G7_IO4 analog switch enable.
Bit 28: G8_IO1 analog switch enable.
Bit 29: G8_IO2 analog switch enable.
Bit 30: G8_IO3 analog switch enable.
Bit 31: G8_IO4 analog switch enable.
I/O sampling control register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
0/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
G8_IO4
rw |
G8_IO3
rw |
G8_IO2
rw |
G8_IO1
rw |
G7_IO4
rw |
G7_IO3
rw |
G7_IO2
rw |
G7_IO1
rw |
G6_IO4
rw |
G6_IO3
rw |
G6_IO2
rw |
G6_IO1
rw |
G5_IO4
rw |
G5_IO3
rw |
G5_IO2
rw |
G5_IO1
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
G4_IO4
rw |
G4_IO3
rw |
G4_IO2
rw |
G4_IO1
rw |
G3_IO4
rw |
G3_IO3
rw |
G3_IO2
rw |
G3_IO1
rw |
G2_IO4
rw |
G2_IO3
rw |
G2_IO2
rw |
G2_IO1
rw |
G1_IO4
rw |
G1_IO3
rw |
G1_IO2
rw |
G1_IO1
rw |
Bit 0: G1_IO1 sampling mode.
Bit 1: G1_IO2 sampling mode.
Bit 2: G1_IO3 sampling mode.
Bit 3: G1_IO4 sampling mode.
Bit 4: G2_IO1 sampling mode.
Bit 5: G2_IO2 sampling mode.
Bit 6: G2_IO3 sampling mode.
Bit 7: G2_IO4 sampling mode.
Bit 8: G3_IO1 sampling mode.
Bit 9: G3_IO2 sampling mode.
Bit 10: G3_IO3 sampling mode.
Bit 11: G3_IO4 sampling mode.
Bit 12: G4_IO1 sampling mode.
Bit 13: G4_IO2 sampling mode.
Bit 14: G4_IO3 sampling mode.
Bit 15: G4_IO4 sampling mode.
Bit 16: G5_IO1 sampling mode.
Bit 17: G5_IO2 sampling mode.
Bit 18: G5_IO3 sampling mode.
Bit 19: G5_IO4 sampling mode.
Bit 20: G6_IO1 sampling mode.
Bit 21: G6_IO2 sampling mode.
Bit 22: G6_IO3 sampling mode.
Bit 23: G6_IO4 sampling mode.
Bit 24: G7_IO1 sampling mode.
Bit 25: G7_IO2 sampling mode.
Bit 26: G7_IO3 sampling mode.
Bit 27: G7_IO4 sampling mode.
Bit 28: G8_IO1 sampling mode.
Bit 29: G8_IO2 sampling mode.
Bit 30: G8_IO3 sampling mode.
Bit 31: G8_IO4 sampling mode.
I/O channel control register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
0/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
G8_IO4
rw |
G8_IO3
rw |
G8_IO2
rw |
G8_IO1
rw |
G7_IO4
rw |
G7_IO3
rw |
G7_IO2
rw |
G7_IO1
rw |
G6_IO4
rw |
G6_IO3
rw |
G6_IO2
rw |
G6_IO1
rw |
G5_IO4
rw |
G5_IO3
rw |
G5_IO2
rw |
G5_IO1
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
G4_IO4
rw |
G4_IO3
rw |
G4_IO2
rw |
G4_IO1
rw |
G3_IO4
rw |
G3_IO3
rw |
G3_IO2
rw |
G3_IO1
rw |
G2_IO4
rw |
G2_IO3
rw |
G2_IO2
rw |
G2_IO1
rw |
G1_IO4
rw |
G1_IO3
rw |
G1_IO2
rw |
G1_IO1
rw |
Bit 0: G1_IO1 channel mode.
Bit 1: G1_IO2 channel mode.
Bit 2: G1_IO3 channel mode.
Bit 3: G1_IO4 channel mode.
Bit 4: G2_IO1 channel mode.
Bit 5: G2_IO2 channel mode.
Bit 6: G2_IO3 channel mode.
Bit 7: G2_IO4 channel mode.
Bit 8: G3_IO1 channel mode.
Bit 9: G3_IO2 channel mode.
Bit 10: G3_IO3 channel mode.
Bit 11: G3_IO4 channel mode.
Bit 12: G4_IO1 channel mode.
Bit 13: G4_IO2 channel mode.
Bit 14: G4_IO3 channel mode.
Bit 15: G4_IO4 channel mode.
Bit 16: G5_IO1 channel mode.
Bit 17: G5_IO2 channel mode.
Bit 18: G5_IO3 channel mode.
Bit 19: G5_IO4 channel mode.
Bit 20: G6_IO1 channel mode.
Bit 21: G6_IO2 channel mode.
Bit 22: G6_IO3 channel mode.
Bit 23: G6_IO4 channel mode.
Bit 24: G7_IO1 channel mode.
Bit 25: G7_IO2 channel mode.
Bit 26: G7_IO3 channel mode.
Bit 27: G7_IO4 channel mode.
Bit 28: G8_IO1 channel mode.
Bit 29: G8_IO2 channel mode.
Bit 30: G8_IO3 channel mode.
Bit 31: G8_IO4 channel mode.
I/O group control status register
Offset: 0x30, size: 32, reset: 0x00000000, access: Unspecified
6/16 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
G8S
rw |
G7S
rw |
G6S
r |
G5S
r |
G4S
r |
G3S
r |
G2S
r |
G1S
r |
||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
G8E
rw |
G7E
rw |
G6E
rw |
G5E
rw |
G4E
rw |
G3E
rw |
G2E
rw |
G1E
rw |
||||||||
Bit 0: Analog I/O group x enable.
Bit 1: Analog I/O group x enable.
Bit 2: Analog I/O group x enable.
Bit 3: Analog I/O group x enable.
Bit 4: Analog I/O group x enable.
Bit 5: Analog I/O group x enable.
Bit 6: Analog I/O group x enable.
Bit 7: Analog I/O group x enable.
Bit 16: Analog I/O group x status.
Bit 17: Analog I/O group x status.
Bit 18: Analog I/O group x status.
Bit 19: Analog I/O group x status.
Bit 20: Analog I/O group x status.
Bit 21: Analog I/O group x status.
Bit 22: Analog I/O group x status.
Bit 23: Analog I/O group x status.
I/O group x counter register
Offset: 0x34, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CNT
r |
|||||||||||||||
I/O group x counter register
Offset: 0x38, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CNT
r |
|||||||||||||||
I/O group x counter register
Offset: 0x3c, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CNT
r |
|||||||||||||||
I/O group x counter register
Offset: 0x40, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CNT
r |
|||||||||||||||
I/O group x counter register
Offset: 0x44, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CNT
r |
|||||||||||||||
I/O group x counter register
Offset: 0x48, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CNT
r |
|||||||||||||||
I/O group x counter register
Offset: 0x4c, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CNT
r |
|||||||||||||||
I/O group x counter register
Offset: 0x50, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CNT
r |
|||||||||||||||
0x40013800: Universal synchronous asynchronous receiver transmitter
103/103 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | CR3 | ||||||||||||||||||||||||||||||||
| 0xc | BRR | ||||||||||||||||||||||||||||||||
| 0x10 | GTPR | ||||||||||||||||||||||||||||||||
| 0x14 | RTOR | ||||||||||||||||||||||||||||||||
| 0x18 | RQR | ||||||||||||||||||||||||||||||||
| 0x1c | ISR | ||||||||||||||||||||||||||||||||
| 0x20 | ICR | ||||||||||||||||||||||||||||||||
| 0x24 | RDR | ||||||||||||||||||||||||||||||||
| 0x28 | TDR | ||||||||||||||||||||||||||||||||
Control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
20/20 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
EOBIE
rw |
RTOIE
rw |
DEAT
rw |
DEDT
rw |
||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OVER8
rw |
CMIE
rw |
MME
rw |
M
rw |
WAKE
rw |
PCE
rw |
PS
rw |
PEIE
rw |
TXEIE
rw |
TCIE
rw |
RXNEIE
rw |
IDLEIE
rw |
TE
rw |
RE
rw |
UESM
rw |
UE
rw |
Bit 0: USART enable.
Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled
Bit 1: USART enable in Stop mode.
Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode
Bit 2: Receiver enable.
Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled
Bit 3: Transmitter enable.
Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled
Bit 4: IDLE interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register
Bit 5: RXNE interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register
Bit 6: Transmission complete interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register
Bit 7: interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register
Bit 8: PE interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register
Bit 9: Parity selection.
Allowed values:
0: Even: Even parity
1: Odd: Odd parity
Bit 10: Parity control enable.
Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled
Bit 11: Receiver wakeup method.
Allowed values:
0: Idle: Idle line
1: Address: Address mask
Bit 12: Word length.
Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits
Bit 13: Mute mode enable.
Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode
Bit 14: Character match interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register
Bit 15: Oversampling mode.
Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8
Bits 16-20: Driver Enable deassertion time.
Allowed values: 0x0-0x1f
Bits 21-25: Driver Enable assertion time.
Allowed values: 0x0-0x1f
Bit 26: Receiver timeout interrupt enable.
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register
Bit 27: End of Block interrupt enable.
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register
Control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
18/18 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ADD
rw |
RTOEN
rw |
ABRMOD
rw |
ABREN
rw |
MSBFIRST
rw |
DATAINV
rw |
TXINV
rw |
RXINV
rw |
||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SWAP
rw |
LINEN
rw |
STOP
rw |
CLKEN
rw |
CPOL
rw |
CPHA
rw |
LBCL
rw |
LBDIE
rw |
LBDL
rw |
ADDM7
rw |
||||||
Bit 4: 7-bit Address Detection/4-bit Address Detection.
Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection
Bit 5: LIN break detection length.
Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection
Bit 6: LIN break detection interrupt enable.
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register
Bit 8: Last bit clock pulse.
Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin
Bit 9: Clock phase.
Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge
Bit 10: Clock polarity.
Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window
Bit 11: Clock enable.
Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled
Bits 12-13: STOP bits.
Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit
Bit 14: LIN mode enable.
Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled
Bit 15: Swap TX/RX pins.
Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped
Bit 16: RX pin active level inversion.
Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted
Bit 17: TX pin active level inversion.
Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted
Bit 18: Binary data inversion.
Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic
Bit 19: Most significant bit first.
Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit
Bit 20: Auto baud rate enable.
Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled
Bits 21-22: Auto baud rate mode.
Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection
Bit 23: Receiver timeout enable.
Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled
Bits 24-31: Address of the USART node.
Allowed values: 0x0-0xff
Control register 3
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
19/19 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
WUFIE
rw |
WUS
rw |
SCARCNT
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DEP
rw |
DEM
rw |
DDRE
rw |
OVRDIS
rw |
ONEBIT
rw |
CTSIE
rw |
CTSE
rw |
RTSE
rw |
DMAT
rw |
DMAR
rw |
SCEN
rw |
NACK
rw |
HDSEL
rw |
IRLP
rw |
IREN
rw |
EIE
rw |
Bit 0: Error interrupt enable.
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register
Bit 1: IrDA mode enable.
Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled
Bit 2: IrDA low-power.
Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode
Bit 3: Half-duplex selection.
Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected
Bit 4: Smartcard NACK enable.
Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled
Bit 5: Smartcard mode enable.
Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled
Bit 6: DMA enable receiver.
Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception
Bit 7: DMA enable transmitter.
Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission
Bit 8: RTS enable.
Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer
Bit 9: CTS enable.
Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted
Bit 10: CTS interrupt enable.
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register
Bit 11: One sample bit method enable.
Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method
Bit 12: Overrun Disable.
Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register
Bit 13: DMA Disable on Reception Error.
Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error
Bit 14: Driver enable mode.
Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin
Bit 15: Driver enable polarity selection.
Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low
Bits 17-19: Smartcard auto-retry count.
Allowed values: 0x0-0x7
Bits 20-21: Wakeup from Stop mode interrupt flag selection.
Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE
Bit 22: Wakeup from Stop mode interrupt enable.
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register
Baud rate register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BRR
rw |
|||||||||||||||
Guard time and prescaler register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
2/2 fields covered.
Receiver timeout register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
2/2 fields covered.
Request register
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
5/5 fields covered.
Bit 0: Auto baud rate request.
Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame
Bit 1: Send break request.
Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available
Bit 2: Mute mode request.
Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag
Bit 3: Receive data flush request.
Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition
Bit 4: Transmit data flush request.
Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data
Interrupt & status register
Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only
22/22 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
REACK
r |
TEACK
r |
WUF
r |
RWU
r |
SBKF
r |
CMF
r |
BUSY
r |
|||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ABRF
r |
ABRE
r |
EOBF
r |
RTOF
r |
CTS
r |
CTSIF
r |
LBDF
r |
TXE
r |
TC
r |
RXNE
r |
IDLE
r |
ORE
r |
NF
r |
FE
r |
PE
r |
|
Bit 0: Parity error.
Bit 1: Framing error.
Bit 2: Noise detected flag.
Bit 3: Overrun error.
Bit 4: Idle line detected.
Bit 5: Read data register not empty.
Bit 6: Transmission complete.
Bit 7: Transmit data register empty.
Bit 8: LIN break detection flag.
Bit 9: CTS interrupt flag.
Bit 10: CTS flag.
Bit 11: Receiver timeout.
Bit 12: End of block flag.
Bit 14: Auto baud rate error.
Bit 15: Auto baud rate flag.
Bit 16: Busy flag.
Bit 17: character match flag.
Bit 18: Send break flag.
Bit 19: Receiver wakeup from Mute mode.
Bit 20: Wakeup from Stop mode flag.
Bit 21: Transmit enable acknowledge flag.
Bit 22: Receive enable acknowledge flag.
Interrupt flag clear register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
12/12 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
WUCF
rw |
CMCF
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EOBCF
rw |
RTOCF
rw |
CTSCF
rw |
LBDCF
rw |
TCCF
rw |
IDLECF
rw |
ORECF
rw |
NCF
rw |
FECF
rw |
PECF
rw |
||||||
Bit 0: Parity error clear flag.
Allowed values:
1: Clear: Clears the PE flag in the ISR register
Bit 1: Framing error clear flag.
Allowed values:
1: Clear: Clears the FE flag in the ISR register
Bit 2: Noise detected clear flag.
Allowed values:
1: Clear: Clears the NF flag in the ISR register
Bit 3: Overrun error clear flag.
Allowed values:
1: Clear: Clears the ORE flag in the ISR register
Bit 4: Idle line detected clear flag.
Allowed values:
1: Clear: Clears the IDLE flag in the ISR register
Bit 6: Transmission complete clear flag.
Allowed values:
1: Clear: Clears the TC flag in the ISR register
Bit 8: LIN break detection clear flag.
Allowed values:
1: Clear: Clears the LBDF flag in the ISR register
Bit 9: CTS clear flag.
Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register
Bit 11: Receiver timeout clear flag.
Allowed values:
1: Clear: Clears the RTOF flag in the ISR register
Bit 12: End of timeout clear flag.
Allowed values:
1: Clear: Clears the EOBF flag in the ISR register
Bit 17: Character match clear flag.
Allowed values:
1: Clear: Clears the CMF flag in the ISR register
Bit 20: Wakeup from Stop mode clear flag.
Allowed values:
1: Clear: Clears the WUF flag in the ISR register
Receive data register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
RDR
r |
|||||||||||||||
Transmit data register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TDR
rw |
|||||||||||||||
0x40004400: Universal synchronous asynchronous receiver transmitter
103/103 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | CR3 | ||||||||||||||||||||||||||||||||
| 0xc | BRR | ||||||||||||||||||||||||||||||||
| 0x10 | GTPR | ||||||||||||||||||||||||||||||||
| 0x14 | RTOR | ||||||||||||||||||||||||||||||||
| 0x18 | RQR | ||||||||||||||||||||||||||||||||
| 0x1c | ISR | ||||||||||||||||||||||||||||||||
| 0x20 | ICR | ||||||||||||||||||||||||||||||||
| 0x24 | RDR | ||||||||||||||||||||||||||||||||
| 0x28 | TDR | ||||||||||||||||||||||||||||||||
Control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
20/20 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
EOBIE
rw |
RTOIE
rw |
DEAT
rw |
DEDT
rw |
||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OVER8
rw |
CMIE
rw |
MME
rw |
M
rw |
WAKE
rw |
PCE
rw |
PS
rw |
PEIE
rw |
TXEIE
rw |
TCIE
rw |
RXNEIE
rw |
IDLEIE
rw |
TE
rw |
RE
rw |
UESM
rw |
UE
rw |
Bit 0: USART enable.
Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled
Bit 1: USART enable in Stop mode.
Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode
Bit 2: Receiver enable.
Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled
Bit 3: Transmitter enable.
Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled
Bit 4: IDLE interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register
Bit 5: RXNE interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register
Bit 6: Transmission complete interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register
Bit 7: interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register
Bit 8: PE interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register
Bit 9: Parity selection.
Allowed values:
0: Even: Even parity
1: Odd: Odd parity
Bit 10: Parity control enable.
Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled
Bit 11: Receiver wakeup method.
Allowed values:
0: Idle: Idle line
1: Address: Address mask
Bit 12: Word length.
Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits
Bit 13: Mute mode enable.
Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode
Bit 14: Character match interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register
Bit 15: Oversampling mode.
Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8
Bits 16-20: Driver Enable deassertion time.
Allowed values: 0x0-0x1f
Bits 21-25: Driver Enable assertion time.
Allowed values: 0x0-0x1f
Bit 26: Receiver timeout interrupt enable.
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register
Bit 27: End of Block interrupt enable.
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register
Control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
18/18 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ADD
rw |
RTOEN
rw |
ABRMOD
rw |
ABREN
rw |
MSBFIRST
rw |
DATAINV
rw |
TXINV
rw |
RXINV
rw |
||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SWAP
rw |
LINEN
rw |
STOP
rw |
CLKEN
rw |
CPOL
rw |
CPHA
rw |
LBCL
rw |
LBDIE
rw |
LBDL
rw |
ADDM7
rw |
||||||
Bit 4: 7-bit Address Detection/4-bit Address Detection.
Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection
Bit 5: LIN break detection length.
Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection
Bit 6: LIN break detection interrupt enable.
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register
Bit 8: Last bit clock pulse.
Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin
Bit 9: Clock phase.
Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge
Bit 10: Clock polarity.
Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window
Bit 11: Clock enable.
Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled
Bits 12-13: STOP bits.
Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit
Bit 14: LIN mode enable.
Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled
Bit 15: Swap TX/RX pins.
Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped
Bit 16: RX pin active level inversion.
Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted
Bit 17: TX pin active level inversion.
Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted
Bit 18: Binary data inversion.
Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic
Bit 19: Most significant bit first.
Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit
Bit 20: Auto baud rate enable.
Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled
Bits 21-22: Auto baud rate mode.
Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection
Bit 23: Receiver timeout enable.
Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled
Bits 24-31: Address of the USART node.
Allowed values: 0x0-0xff
Control register 3
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
19/19 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
WUFIE
rw |
WUS
rw |
SCARCNT
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DEP
rw |
DEM
rw |
DDRE
rw |
OVRDIS
rw |
ONEBIT
rw |
CTSIE
rw |
CTSE
rw |
RTSE
rw |
DMAT
rw |
DMAR
rw |
SCEN
rw |
NACK
rw |
HDSEL
rw |
IRLP
rw |
IREN
rw |
EIE
rw |
Bit 0: Error interrupt enable.
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register
Bit 1: IrDA mode enable.
Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled
Bit 2: IrDA low-power.
Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode
Bit 3: Half-duplex selection.
Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected
Bit 4: Smartcard NACK enable.
Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled
Bit 5: Smartcard mode enable.
Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled
Bit 6: DMA enable receiver.
Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception
Bit 7: DMA enable transmitter.
Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission
Bit 8: RTS enable.
Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer
Bit 9: CTS enable.
Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted
Bit 10: CTS interrupt enable.
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register
Bit 11: One sample bit method enable.
Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method
Bit 12: Overrun Disable.
Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register
Bit 13: DMA Disable on Reception Error.
Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error
Bit 14: Driver enable mode.
Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin
Bit 15: Driver enable polarity selection.
Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low
Bits 17-19: Smartcard auto-retry count.
Allowed values: 0x0-0x7
Bits 20-21: Wakeup from Stop mode interrupt flag selection.
Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE
Bit 22: Wakeup from Stop mode interrupt enable.
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register
Baud rate register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BRR
rw |
|||||||||||||||
Guard time and prescaler register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
2/2 fields covered.
Receiver timeout register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
2/2 fields covered.
Request register
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
5/5 fields covered.
Bit 0: Auto baud rate request.
Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame
Bit 1: Send break request.
Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available
Bit 2: Mute mode request.
Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag
Bit 3: Receive data flush request.
Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition
Bit 4: Transmit data flush request.
Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data
Interrupt & status register
Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only
22/22 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
REACK
r |
TEACK
r |
WUF
r |
RWU
r |
SBKF
r |
CMF
r |
BUSY
r |
|||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ABRF
r |
ABRE
r |
EOBF
r |
RTOF
r |
CTS
r |
CTSIF
r |
LBDF
r |
TXE
r |
TC
r |
RXNE
r |
IDLE
r |
ORE
r |
NF
r |
FE
r |
PE
r |
|
Bit 0: Parity error.
Bit 1: Framing error.
Bit 2: Noise detected flag.
Bit 3: Overrun error.
Bit 4: Idle line detected.
Bit 5: Read data register not empty.
Bit 6: Transmission complete.
Bit 7: Transmit data register empty.
Bit 8: LIN break detection flag.
Bit 9: CTS interrupt flag.
Bit 10: CTS flag.
Bit 11: Receiver timeout.
Bit 12: End of block flag.
Bit 14: Auto baud rate error.
Bit 15: Auto baud rate flag.
Bit 16: Busy flag.
Bit 17: character match flag.
Bit 18: Send break flag.
Bit 19: Receiver wakeup from Mute mode.
Bit 20: Wakeup from Stop mode flag.
Bit 21: Transmit enable acknowledge flag.
Bit 22: Receive enable acknowledge flag.
Interrupt flag clear register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
12/12 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
WUCF
rw |
CMCF
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EOBCF
rw |
RTOCF
rw |
CTSCF
rw |
LBDCF
rw |
TCCF
rw |
IDLECF
rw |
ORECF
rw |
NCF
rw |
FECF
rw |
PECF
rw |
||||||
Bit 0: Parity error clear flag.
Allowed values:
1: Clear: Clears the PE flag in the ISR register
Bit 1: Framing error clear flag.
Allowed values:
1: Clear: Clears the FE flag in the ISR register
Bit 2: Noise detected clear flag.
Allowed values:
1: Clear: Clears the NF flag in the ISR register
Bit 3: Overrun error clear flag.
Allowed values:
1: Clear: Clears the ORE flag in the ISR register
Bit 4: Idle line detected clear flag.
Allowed values:
1: Clear: Clears the IDLE flag in the ISR register
Bit 6: Transmission complete clear flag.
Allowed values:
1: Clear: Clears the TC flag in the ISR register
Bit 8: LIN break detection clear flag.
Allowed values:
1: Clear: Clears the LBDF flag in the ISR register
Bit 9: CTS clear flag.
Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register
Bit 11: Receiver timeout clear flag.
Allowed values:
1: Clear: Clears the RTOF flag in the ISR register
Bit 12: End of timeout clear flag.
Allowed values:
1: Clear: Clears the EOBF flag in the ISR register
Bit 17: Character match clear flag.
Allowed values:
1: Clear: Clears the CMF flag in the ISR register
Bit 20: Wakeup from Stop mode clear flag.
Allowed values:
1: Clear: Clears the WUF flag in the ISR register
Receive data register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
RDR
r |
|||||||||||||||
Transmit data register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TDR
rw |
|||||||||||||||
0x40004800: Universal synchronous asynchronous receiver transmitter
103/103 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | CR3 | ||||||||||||||||||||||||||||||||
| 0xc | BRR | ||||||||||||||||||||||||||||||||
| 0x10 | GTPR | ||||||||||||||||||||||||||||||||
| 0x14 | RTOR | ||||||||||||||||||||||||||||||||
| 0x18 | RQR | ||||||||||||||||||||||||||||||||
| 0x1c | ISR | ||||||||||||||||||||||||||||||||
| 0x20 | ICR | ||||||||||||||||||||||||||||||||
| 0x24 | RDR | ||||||||||||||||||||||||||||||||
| 0x28 | TDR | ||||||||||||||||||||||||||||||||
Control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
20/20 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
EOBIE
rw |
RTOIE
rw |
DEAT
rw |
DEDT
rw |
||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OVER8
rw |
CMIE
rw |
MME
rw |
M
rw |
WAKE
rw |
PCE
rw |
PS
rw |
PEIE
rw |
TXEIE
rw |
TCIE
rw |
RXNEIE
rw |
IDLEIE
rw |
TE
rw |
RE
rw |
UESM
rw |
UE
rw |
Bit 0: USART enable.
Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled
Bit 1: USART enable in Stop mode.
Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode
Bit 2: Receiver enable.
Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled
Bit 3: Transmitter enable.
Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled
Bit 4: IDLE interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register
Bit 5: RXNE interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register
Bit 6: Transmission complete interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register
Bit 7: interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register
Bit 8: PE interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register
Bit 9: Parity selection.
Allowed values:
0: Even: Even parity
1: Odd: Odd parity
Bit 10: Parity control enable.
Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled
Bit 11: Receiver wakeup method.
Allowed values:
0: Idle: Idle line
1: Address: Address mask
Bit 12: Word length.
Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits
Bit 13: Mute mode enable.
Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode
Bit 14: Character match interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register
Bit 15: Oversampling mode.
Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8
Bits 16-20: Driver Enable deassertion time.
Allowed values: 0x0-0x1f
Bits 21-25: Driver Enable assertion time.
Allowed values: 0x0-0x1f
Bit 26: Receiver timeout interrupt enable.
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register
Bit 27: End of Block interrupt enable.
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register
Control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
18/18 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ADD
rw |
RTOEN
rw |
ABRMOD
rw |
ABREN
rw |
MSBFIRST
rw |
DATAINV
rw |
TXINV
rw |
RXINV
rw |
||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SWAP
rw |
LINEN
rw |
STOP
rw |
CLKEN
rw |
CPOL
rw |
CPHA
rw |
LBCL
rw |
LBDIE
rw |
LBDL
rw |
ADDM7
rw |
||||||
Bit 4: 7-bit Address Detection/4-bit Address Detection.
Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection
Bit 5: LIN break detection length.
Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection
Bit 6: LIN break detection interrupt enable.
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register
Bit 8: Last bit clock pulse.
Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin
Bit 9: Clock phase.
Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge
Bit 10: Clock polarity.
Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window
Bit 11: Clock enable.
Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled
Bits 12-13: STOP bits.
Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit
Bit 14: LIN mode enable.
Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled
Bit 15: Swap TX/RX pins.
Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped
Bit 16: RX pin active level inversion.
Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted
Bit 17: TX pin active level inversion.
Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted
Bit 18: Binary data inversion.
Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic
Bit 19: Most significant bit first.
Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit
Bit 20: Auto baud rate enable.
Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled
Bits 21-22: Auto baud rate mode.
Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection
Bit 23: Receiver timeout enable.
Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled
Bits 24-31: Address of the USART node.
Allowed values: 0x0-0xff
Control register 3
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
19/19 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
WUFIE
rw |
WUS
rw |
SCARCNT
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DEP
rw |
DEM
rw |
DDRE
rw |
OVRDIS
rw |
ONEBIT
rw |
CTSIE
rw |
CTSE
rw |
RTSE
rw |
DMAT
rw |
DMAR
rw |
SCEN
rw |
NACK
rw |
HDSEL
rw |
IRLP
rw |
IREN
rw |
EIE
rw |
Bit 0: Error interrupt enable.
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register
Bit 1: IrDA mode enable.
Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled
Bit 2: IrDA low-power.
Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode
Bit 3: Half-duplex selection.
Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected
Bit 4: Smartcard NACK enable.
Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled
Bit 5: Smartcard mode enable.
Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled
Bit 6: DMA enable receiver.
Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception
Bit 7: DMA enable transmitter.
Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission
Bit 8: RTS enable.
Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer
Bit 9: CTS enable.
Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted
Bit 10: CTS interrupt enable.
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register
Bit 11: One sample bit method enable.
Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method
Bit 12: Overrun Disable.
Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register
Bit 13: DMA Disable on Reception Error.
Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error
Bit 14: Driver enable mode.
Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin
Bit 15: Driver enable polarity selection.
Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low
Bits 17-19: Smartcard auto-retry count.
Allowed values: 0x0-0x7
Bits 20-21: Wakeup from Stop mode interrupt flag selection.
Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE
Bit 22: Wakeup from Stop mode interrupt enable.
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register
Baud rate register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BRR
rw |
|||||||||||||||
Guard time and prescaler register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
2/2 fields covered.
Receiver timeout register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
2/2 fields covered.
Request register
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
5/5 fields covered.
Bit 0: Auto baud rate request.
Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame
Bit 1: Send break request.
Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available
Bit 2: Mute mode request.
Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag
Bit 3: Receive data flush request.
Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition
Bit 4: Transmit data flush request.
Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data
Interrupt & status register
Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only
22/22 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
REACK
r |
TEACK
r |
WUF
r |
RWU
r |
SBKF
r |
CMF
r |
BUSY
r |
|||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ABRF
r |
ABRE
r |
EOBF
r |
RTOF
r |
CTS
r |
CTSIF
r |
LBDF
r |
TXE
r |
TC
r |
RXNE
r |
IDLE
r |
ORE
r |
NF
r |
FE
r |
PE
r |
|
Bit 0: Parity error.
Bit 1: Framing error.
Bit 2: Noise detected flag.
Bit 3: Overrun error.
Bit 4: Idle line detected.
Bit 5: Read data register not empty.
Bit 6: Transmission complete.
Bit 7: Transmit data register empty.
Bit 8: LIN break detection flag.
Bit 9: CTS interrupt flag.
Bit 10: CTS flag.
Bit 11: Receiver timeout.
Bit 12: End of block flag.
Bit 14: Auto baud rate error.
Bit 15: Auto baud rate flag.
Bit 16: Busy flag.
Bit 17: character match flag.
Bit 18: Send break flag.
Bit 19: Receiver wakeup from Mute mode.
Bit 20: Wakeup from Stop mode flag.
Bit 21: Transmit enable acknowledge flag.
Bit 22: Receive enable acknowledge flag.
Interrupt flag clear register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
12/12 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
WUCF
rw |
CMCF
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EOBCF
rw |
RTOCF
rw |
CTSCF
rw |
LBDCF
rw |
TCCF
rw |
IDLECF
rw |
ORECF
rw |
NCF
rw |
FECF
rw |
PECF
rw |
||||||
Bit 0: Parity error clear flag.
Allowed values:
1: Clear: Clears the PE flag in the ISR register
Bit 1: Framing error clear flag.
Allowed values:
1: Clear: Clears the FE flag in the ISR register
Bit 2: Noise detected clear flag.
Allowed values:
1: Clear: Clears the NF flag in the ISR register
Bit 3: Overrun error clear flag.
Allowed values:
1: Clear: Clears the ORE flag in the ISR register
Bit 4: Idle line detected clear flag.
Allowed values:
1: Clear: Clears the IDLE flag in the ISR register
Bit 6: Transmission complete clear flag.
Allowed values:
1: Clear: Clears the TC flag in the ISR register
Bit 8: LIN break detection clear flag.
Allowed values:
1: Clear: Clears the LBDF flag in the ISR register
Bit 9: CTS clear flag.
Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register
Bit 11: Receiver timeout clear flag.
Allowed values:
1: Clear: Clears the RTOF flag in the ISR register
Bit 12: End of timeout clear flag.
Allowed values:
1: Clear: Clears the EOBF flag in the ISR register
Bit 17: Character match clear flag.
Allowed values:
1: Clear: Clears the CMF flag in the ISR register
Bit 20: Wakeup from Stop mode clear flag.
Allowed values:
1: Clear: Clears the WUF flag in the ISR register
Receive data register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
RDR
r |
|||||||||||||||
Transmit data register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TDR
rw |
|||||||||||||||
0x40005c00: Universal serial bus full-speed device interface
71/111 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | EP0R | ||||||||||||||||||||||||||||||||
| 0x4 | EP1R | ||||||||||||||||||||||||||||||||
| 0x8 | EP2R | ||||||||||||||||||||||||||||||||
| 0xc | EP3R | ||||||||||||||||||||||||||||||||
| 0x10 | EP4R | ||||||||||||||||||||||||||||||||
| 0x14 | EP5R | ||||||||||||||||||||||||||||||||
| 0x18 | EP6R | ||||||||||||||||||||||||||||||||
| 0x1c | EP7R | ||||||||||||||||||||||||||||||||
| 0x40 | CNTR | ||||||||||||||||||||||||||||||||
| 0x44 | ISTR | ||||||||||||||||||||||||||||||||
| 0x48 | FNR | ||||||||||||||||||||||||||||||||
| 0x4c | DADDR | ||||||||||||||||||||||||||||||||
| 0x50 | BTABLE | ||||||||||||||||||||||||||||||||
endpoint 0 register
Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified
5/10 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CTR_RX
rw |
DTOG_RX
rw |
STAT_RX
rw |
SETUP
r |
EP_TYPE
rw |
EP_KIND
rw |
CTR_TX
rw |
DTOG_TX
rw |
STAT_TX
rw |
EA
rw |
||||||
Bits 0-3: Endpoint address.
Allowed values: 0x0-0xf
Bits 4-5: Status bits, for transmission transfers.
Allowed values:
0: Disabled: all transmission requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all transmission requests result in a STALL handshake
2: Nak: the endpoint is naked and all transmission requests result in a NAK handshake
3: Valid: this endpoint is enabled for transmission
Bit 6: Data Toggle, for transmission transfers.
Bit 7: Correct Transfer for transmission.
Bit 8: Endpoint kind.
Bits 9-10: Endpoint type.
Allowed values:
0: Bulk: Bulk endpoint
1: Control: Control endpoint
2: Iso: Iso endpoint
3: Interrupt: Interrupt endpoint
Bit 11: Setup transaction completed.
Bits 12-13: Status bits, for reception transfers.
Allowed values:
0: Disabled: all reception requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all reception requests result in a STALL handshake
2: Nak: the endpoint is naked and all reception requests result in a NAK handshake
3: Valid: this endpoint is enabled for reception
Bit 14: Data Toggle, for reception transfers.
Bit 15: Correct transfer for reception.
endpoint 1 register
Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified
5/10 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CTR_RX
rw |
DTOG_RX
rw |
STAT_RX
rw |
SETUP
r |
EP_TYPE
rw |
EP_KIND
rw |
CTR_TX
rw |
DTOG_TX
rw |
STAT_TX
rw |
EA
rw |
||||||
Bits 0-3: Endpoint address.
Allowed values: 0x0-0xf
Bits 4-5: Status bits, for transmission transfers.
Allowed values:
0: Disabled: all transmission requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all transmission requests result in a STALL handshake
2: Nak: the endpoint is naked and all transmission requests result in a NAK handshake
3: Valid: this endpoint is enabled for transmission
Bit 6: Data Toggle, for transmission transfers.
Bit 7: Correct Transfer for transmission.
Bit 8: Endpoint kind.
Bits 9-10: Endpoint type.
Allowed values:
0: Bulk: Bulk endpoint
1: Control: Control endpoint
2: Iso: Iso endpoint
3: Interrupt: Interrupt endpoint
Bit 11: Setup transaction completed.
Bits 12-13: Status bits, for reception transfers.
Allowed values:
0: Disabled: all reception requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all reception requests result in a STALL handshake
2: Nak: the endpoint is naked and all reception requests result in a NAK handshake
3: Valid: this endpoint is enabled for reception
Bit 14: Data Toggle, for reception transfers.
Bit 15: Correct transfer for reception.
endpoint 2 register
Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified
5/10 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CTR_RX
rw |
DTOG_RX
rw |
STAT_RX
rw |
SETUP
r |
EP_TYPE
rw |
EP_KIND
rw |
CTR_TX
rw |
DTOG_TX
rw |
STAT_TX
rw |
EA
rw |
||||||
Bits 0-3: Endpoint address.
Allowed values: 0x0-0xf
Bits 4-5: Status bits, for transmission transfers.
Allowed values:
0: Disabled: all transmission requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all transmission requests result in a STALL handshake
2: Nak: the endpoint is naked and all transmission requests result in a NAK handshake
3: Valid: this endpoint is enabled for transmission
Bit 6: Data Toggle, for transmission transfers.
Bit 7: Correct Transfer for transmission.
Bit 8: Endpoint kind.
Bits 9-10: Endpoint type.
Allowed values:
0: Bulk: Bulk endpoint
1: Control: Control endpoint
2: Iso: Iso endpoint
3: Interrupt: Interrupt endpoint
Bit 11: Setup transaction completed.
Bits 12-13: Status bits, for reception transfers.
Allowed values:
0: Disabled: all reception requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all reception requests result in a STALL handshake
2: Nak: the endpoint is naked and all reception requests result in a NAK handshake
3: Valid: this endpoint is enabled for reception
Bit 14: Data Toggle, for reception transfers.
Bit 15: Correct transfer for reception.
endpoint 3 register
Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified
5/10 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CTR_RX
rw |
DTOG_RX
rw |
STAT_RX
rw |
SETUP
r |
EP_TYPE
rw |
EP_KIND
rw |
CTR_TX
rw |
DTOG_TX
rw |
STAT_TX
rw |
EA
rw |
||||||
Bits 0-3: Endpoint address.
Allowed values: 0x0-0xf
Bits 4-5: Status bits, for transmission transfers.
Allowed values:
0: Disabled: all transmission requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all transmission requests result in a STALL handshake
2: Nak: the endpoint is naked and all transmission requests result in a NAK handshake
3: Valid: this endpoint is enabled for transmission
Bit 6: Data Toggle, for transmission transfers.
Bit 7: Correct Transfer for transmission.
Bit 8: Endpoint kind.
Bits 9-10: Endpoint type.
Allowed values:
0: Bulk: Bulk endpoint
1: Control: Control endpoint
2: Iso: Iso endpoint
3: Interrupt: Interrupt endpoint
Bit 11: Setup transaction completed.
Bits 12-13: Status bits, for reception transfers.
Allowed values:
0: Disabled: all reception requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all reception requests result in a STALL handshake
2: Nak: the endpoint is naked and all reception requests result in a NAK handshake
3: Valid: this endpoint is enabled for reception
Bit 14: Data Toggle, for reception transfers.
Bit 15: Correct transfer for reception.
endpoint 4 register
Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified
5/10 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CTR_RX
rw |
DTOG_RX
rw |
STAT_RX
rw |
SETUP
r |
EP_TYPE
rw |
EP_KIND
rw |
CTR_TX
rw |
DTOG_TX
rw |
STAT_TX
rw |
EA
rw |
||||||
Bits 0-3: Endpoint address.
Allowed values: 0x0-0xf
Bits 4-5: Status bits, for transmission transfers.
Allowed values:
0: Disabled: all transmission requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all transmission requests result in a STALL handshake
2: Nak: the endpoint is naked and all transmission requests result in a NAK handshake
3: Valid: this endpoint is enabled for transmission
Bit 6: Data Toggle, for transmission transfers.
Bit 7: Correct Transfer for transmission.
Bit 8: Endpoint kind.
Bits 9-10: Endpoint type.
Allowed values:
0: Bulk: Bulk endpoint
1: Control: Control endpoint
2: Iso: Iso endpoint
3: Interrupt: Interrupt endpoint
Bit 11: Setup transaction completed.
Bits 12-13: Status bits, for reception transfers.
Allowed values:
0: Disabled: all reception requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all reception requests result in a STALL handshake
2: Nak: the endpoint is naked and all reception requests result in a NAK handshake
3: Valid: this endpoint is enabled for reception
Bit 14: Data Toggle, for reception transfers.
Bit 15: Correct transfer for reception.
endpoint 5 register
Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified
5/10 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CTR_RX
rw |
DTOG_RX
rw |
STAT_RX
rw |
SETUP
r |
EP_TYPE
rw |
EP_KIND
rw |
CTR_TX
rw |
DTOG_TX
rw |
STAT_TX
rw |
EA
rw |
||||||
Bits 0-3: Endpoint address.
Allowed values: 0x0-0xf
Bits 4-5: Status bits, for transmission transfers.
Allowed values:
0: Disabled: all transmission requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all transmission requests result in a STALL handshake
2: Nak: the endpoint is naked and all transmission requests result in a NAK handshake
3: Valid: this endpoint is enabled for transmission
Bit 6: Data Toggle, for transmission transfers.
Bit 7: Correct Transfer for transmission.
Bit 8: Endpoint kind.
Bits 9-10: Endpoint type.
Allowed values:
0: Bulk: Bulk endpoint
1: Control: Control endpoint
2: Iso: Iso endpoint
3: Interrupt: Interrupt endpoint
Bit 11: Setup transaction completed.
Bits 12-13: Status bits, for reception transfers.
Allowed values:
0: Disabled: all reception requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all reception requests result in a STALL handshake
2: Nak: the endpoint is naked and all reception requests result in a NAK handshake
3: Valid: this endpoint is enabled for reception
Bit 14: Data Toggle, for reception transfers.
Bit 15: Correct transfer for reception.
endpoint 6 register
Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified
5/10 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CTR_RX
rw |
DTOG_RX
rw |
STAT_RX
rw |
SETUP
r |
EP_TYPE
rw |
EP_KIND
rw |
CTR_TX
rw |
DTOG_TX
rw |
STAT_TX
rw |
EA
rw |
||||||
Bits 0-3: Endpoint address.
Allowed values: 0x0-0xf
Bits 4-5: Status bits, for transmission transfers.
Allowed values:
0: Disabled: all transmission requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all transmission requests result in a STALL handshake
2: Nak: the endpoint is naked and all transmission requests result in a NAK handshake
3: Valid: this endpoint is enabled for transmission
Bit 6: Data Toggle, for transmission transfers.
Bit 7: Correct Transfer for transmission.
Bit 8: Endpoint kind.
Bits 9-10: Endpoint type.
Allowed values:
0: Bulk: Bulk endpoint
1: Control: Control endpoint
2: Iso: Iso endpoint
3: Interrupt: Interrupt endpoint
Bit 11: Setup transaction completed.
Bits 12-13: Status bits, for reception transfers.
Allowed values:
0: Disabled: all reception requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all reception requests result in a STALL handshake
2: Nak: the endpoint is naked and all reception requests result in a NAK handshake
3: Valid: this endpoint is enabled for reception
Bit 14: Data Toggle, for reception transfers.
Bit 15: Correct transfer for reception.
endpoint 7 register
Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified
5/10 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CTR_RX
rw |
DTOG_RX
rw |
STAT_RX
rw |
SETUP
r |
EP_TYPE
rw |
EP_KIND
rw |
CTR_TX
rw |
DTOG_TX
rw |
STAT_TX
rw |
EA
rw |
||||||
Bits 0-3: Endpoint address.
Allowed values: 0x0-0xf
Bits 4-5: Status bits, for transmission transfers.
Allowed values:
0: Disabled: all transmission requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all transmission requests result in a STALL handshake
2: Nak: the endpoint is naked and all transmission requests result in a NAK handshake
3: Valid: this endpoint is enabled for transmission
Bit 6: Data Toggle, for transmission transfers.
Bit 7: Correct Transfer for transmission.
Bit 8: Endpoint kind.
Bits 9-10: Endpoint type.
Allowed values:
0: Bulk: Bulk endpoint
1: Control: Control endpoint
2: Iso: Iso endpoint
3: Interrupt: Interrupt endpoint
Bit 11: Setup transaction completed.
Bits 12-13: Status bits, for reception transfers.
Allowed values:
0: Disabled: all reception requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all reception requests result in a STALL handshake
2: Nak: the endpoint is naked and all reception requests result in a NAK handshake
3: Valid: this endpoint is enabled for reception
Bit 14: Data Toggle, for reception transfers.
Bit 15: Correct transfer for reception.
control register
Offset: 0x40, size: 32, reset: 0x00000003, access: read-write
13/13 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CTRM
rw |
PMAOVRM
rw |
ERRM
rw |
WKUPM
rw |
SUSPM
rw |
RESETM
rw |
SOFM
rw |
ESOFM
rw |
RESUME
rw |
FSUSP
rw |
LPMODE
rw |
PDWN
rw |
FRES
rw |
|||
Bit 0: Force USB Reset.
Allowed values:
0: NoReset: Clear USB reset
1: Reset: Force a reset of the USB peripheral, exactly like a RESET signaling on the USB
Bit 1: Power down.
Allowed values:
0: Disabled: No power down
1: Enabled: Enter power down mode
Bit 2: Low-power mode.
Allowed values:
0: Disabled: No low-power mode
1: Enabled: Enter low-power mode
Bit 3: Force suspend.
Allowed values:
0: NoEffect: No effect
1: Suspend: Enter suspend mode. Clocks and static power dissipation in the analog transceiver are left unaffected
Bit 4: Resume request.
Allowed values:
1: Requested: Resume requested
Bit 8: Expected start of frame interrupt mask.
Allowed values:
0: Disabled: ESOF Interrupt disabled
1: Enabled: ESOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
Bit 9: Start of frame interrupt mask.
Allowed values:
0: Disabled: SOF Interrupt disabled
1: Enabled: SOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
Bit 10: USB reset interrupt mask.
Allowed values:
0: Disabled: RESET Interrupt disabled
1: Enabled: RESET Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
Bit 11: Suspend mode interrupt mask.
Allowed values:
0: Disabled: Suspend Mode Request SUSP Interrupt disabled
1: Enabled: SUSP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
Bit 12: Wakeup interrupt mask.
Allowed values:
0: Disabled: WKUP Interrupt disabled
1: Enabled: WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
Bit 13: Error interrupt mask.
Allowed values:
0: Disabled: ERR Interrupt disabled
1: Enabled: ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
Bit 14: Packet memory area over / underrun interrupt mask.
Allowed values:
0: Disabled: PMAOVR Interrupt disabled
1: Enabled: PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
Bit 15: Correct transfer interrupt mask.
Allowed values:
0: Disabled: Correct Transfer (CTR) Interrupt disabled
1: Enabled: CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
interrupt status register
Offset: 0x44, size: 32, reset: 0x00000000, access: Unspecified
10/10 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CTR
r |
PMAOVR
rw |
ERR
rw |
WKUP
rw |
SUSP
rw |
RESET
rw |
SOF
rw |
ESOF
rw |
DIR
r |
EP_ID
r |
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Bits 0-3: Endpoint Identifier.
Allowed values: 0x0-0xf
Bit 4: Direction of transaction.
Allowed values:
0: To: data transmitted by the USB peripheral to the host PC
1: From: data received by the USB peripheral from the host PC
Bit 8: Expected start frame.
Allowed values:
0: NotExpectedStartOfFrame: NotExpectedStartOfFrame
1: ExpectedStartOfFrame: an SOF packet is expected but not received
Bit 9: start of frame.
Allowed values:
0: NotStartOfFrame: NotStartOfFrame
1: StartOfFrame: beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus
Bit 10: reset request.
Allowed values:
0: NotReset: NotReset
1: Reset: peripheral detects an active USB RESET signal at its inputs
Bit 11: Suspend mode request.
Allowed values:
0: NotSuspend: NotSuspend
1: Suspend: no traffic has been received for 3 ms, indicating a suspend mode request from the USB bus
Bit 12: Wakeup.
Allowed values:
0: NotWakeup: NotWakeup
1: Wakeup: activity is detected that wakes up the USB peripheral
Bit 13: Error.
Allowed values:
0: NotOverrun: Errors are not occurred
1: Error: One of No ANSwer, Cyclic Redundancy Check, Bit Stuffing or Framing format Violation error occurred
Bit 14: Packet memory area over / underrun.
Allowed values:
0: NotOverrun: Overrun is not occurred
1: Overrun: microcontroller has not been able to respond in time to an USB memory request
Bit 15: Correct transfer.
Allowed values:
1: Completed: endpoint has successfully completed a transaction
frame number register
Offset: 0x48, size: 32, reset: 0x00000000, access: read-only
5/5 fields covered.
Bits 0-10: Frame number.
Allowed values: 0x0-0x7ff
Bits 11-12: Lost SOF.
Allowed values: 0x0-0x3
Bit 13: Locked.
Allowed values:
1: Locked: the frame timer remains in this state until an USB reset or USB suspend event occurs
Bit 14: Receive data - line status.
Allowed values:
1: Received: received data minus upstream port data line
Bit 15: Receive data + line status.
Allowed values:
1: Received: received data plus upstream port data line
device address
Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write
2/2 fields covered.
Buffer table address
Offset: 0x50, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BTABLE
rw |
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0x40002c00: Window watchdog
6/6 fields covered.
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR | ||||||||||||||||||||||||||||||||
| 0x4 | CFR | ||||||||||||||||||||||||||||||||
| 0x8 | SR | ||||||||||||||||||||||||||||||||
Control register
Offset: 0x0, size: 32, reset: 0x0000007F, access: read-write
2/2 fields covered.
Configuration register
Offset: 0x4, size: 32, reset: 0x0000007F, access: read-write
3/3 fields covered.
Bits 0-6: 7-bit window value.
Allowed values: 0x0-0x7f
Bits 7-8: Timer base.
Allowed values:
0: Div1: Counter clock (PCLK1 div 4096) div 1
1: Div2: Counter clock (PCLK1 div 4096) div 2
2: Div4: Counter clock (PCLK1 div 4096) div 4
3: Div8: Counter clock (PCLK1 div 4096) div 8
Bit 9: Early wakeup interrupt.
Allowed values:
1: Enable: interrupt occurs whenever the counter reaches the value 0x40
Status register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
EWIF
rw |
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