Overall: 5617/6571 fields covered

ADC1

0x50000000: Analog-to-Digital Converter

170/170 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 IER
0x8 CR
0xc CFGR
0x14 SMPR1
0x18 SMPR2
0x20 TR1
0x24 TR2
0x28 TR3
0x30 SQR1
0x34 SQR2
0x38 SQR3
0x3c SQR4
0x40 DR
0x4c JSQR
0x60 OFR1
0x64 OFR2
0x68 OFR3
0x6c OFR4
0x80 JDR1
0x84 JDR2
0x88 JDR3
0x8c JDR4
0xa0 AWD2CR
0xa4 AWD3CR
0xb0 DIFSEL
0xb4 CALFACT
Toggle registers

ISR

interrupt and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVF
rw 		AWD3
rw 		AWD2
rw 		AWD1
rw 		JEOS
rw 		JEOC
rw 		OVR
rw 		EOS
rw 		EOC
rw 		EOSMP
rw 		ADRDY
rw
Toggle fields

ADRDY

Bit 0: ADRDY.

Allowed values:
0: NotReady: ADC is not ready to start conversion
1: Ready: ADC is ready to start conversion

EOSMP

Bit 1: EOSMP.

Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached

EOC

Bit 2: EOC.

Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete

EOS

Bit 3: EOS.

Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete

OVR

Bit 4: OVR.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

JEOC

Bit 5: JEOC.

Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete

JEOS

Bit 6: JEOS.

Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete

AWD1

Bit 7: AWD1.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD2

Bit 8: AWD2.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD3

Bit 9: AWD3.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

JQOVF

Bit 10: JQOVF.

Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred

IER

interrupt enable register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVFIE
rw 		AWD3IE
rw 		AWD2IE
rw 		AWD1IE
rw 		JEOSIE
rw 		JEOCIE
rw 		OVRIE
rw 		EOSIE
rw 		EOCIE
rw 		EOSMPIE
rw 		ADRDYIE
rw
Toggle fields

ADRDYIE

Bit 0: ADRDYIE.

Allowed values:
0: Disabled: ADC ready interrupt disabled
1: Enabled: ADC ready interrupt enabled

EOSMPIE

Bit 1: EOSMPIE.

Allowed values:
0: Disabled: End of regular conversion sampling phase interrupt disabled
1: Enabled: End of regular conversion sampling phase interrupt enabled

EOCIE

Bit 2: EOCIE.

Allowed values:
0: Disabled: End of regular conversion interrupt disabled
1: Enabled: End of regular conversion interrupt enabled

EOSIE

Bit 3: EOSIE.

Allowed values:
0: Disabled: End of regular sequence interrupt disabled
1: Enabled: End of regular sequence interrupt enabled

OVRIE

Bit 4: OVRIE.

Allowed values:
0: Disabled: Overrun interrupt disabled
1: Enabled: Overrun interrupt enabled

JEOCIE

Bit 5: JEOCIE.

Allowed values:
0: Disabled: End of injected conversion interrupt disabled
1: Enabled: End of injected conversion interrupt enabled

JEOSIE

Bit 6: JEOSIE.

Allowed values:
0: Disabled: End of injected sequence interrupt disabled
1: Enabled: End of injected sequence interrupt enabled

AWD1IE

Bit 7: AWD1IE.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

AWD2IE

Bit 8: AWD2IE.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

AWD3IE

Bit 9: AWD3IE.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

JQOVFIE

Bit 10: JQOVFIE.

Allowed values:
0: Disabled: Injected context queue overflow interrupt disabled
1: Enabled: Injected context queue overflow interrupt enabled

CR

control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADCAL
rw 		ADCALDIF
rw 		ADVREGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JADSTP
rw 		ADSTP
rw 		JADSTART
rw 		ADSTART
rw 		ADDIS
rw 		ADEN
rw
Toggle fields

ADEN

Bit 0: ADEN.

Allowed values:
0: Disabled: ADC disabled
1: Enabled: ADC enabled

ADDIS

Bit 1: ADDIS.

Allowed values:
0: NotDisabling: No disable command active
1: Disabling: ADC disabling

ADSTART

Bit 2: ADSTART.

Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting

JADSTART

Bit 3: JADSTART.

Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting

ADSTP

Bit 4: ADSTP.

Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion

JADSTP

Bit 5: JADSTP.

Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion

ADVREGEN

Bits 28-29: ADVREGEN.

Allowed values:
0: Intermediate: Intermediate state required when moving the ADC voltage regulator between states
1: Enabled: ADC voltage regulator enabled
2: Disabled: ADC voltage regulator disabled

ADCALDIF

Bit 30: ADCALDIF.

Allowed values:
0: SingleEnded: Calibration for single-ended mode
1: Differential: Calibration for differential mode

ADCAL

Bit 31: ADCAL.

Allowed values:
0: Complete: Calibration complete
1: Calibration: Start the calibration of the ADC

CFGR

configuration register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD1CH
rw 		JAUTO
rw 		JAWD1EN
rw 		AWD1EN
rw 		AWD1SGL
rw 		JQM
rw 		JDISCEN
rw 		DISCNUM
rw 		DISCEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUTDLY
rw 		CONT
rw 		OVRMOD
rw 		EXTEN
rw 		EXTSEL
rw 		ALIGN
rw 		RES
rw 		DMACFG
rw 		DMAEN
rw
Toggle fields

DMAEN

Bit 0: DMAEN.

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

DMACFG

Bit 1: DMACFG.

Allowed values:
0: OneShot: DMA One Shot Mode selected
1: Circular: DMA circular mode selected

RES

Bits 3-4: RES.

Allowed values:
0: Bits12: 12-bit
1: Bits10: 10-bit
2: Bits8: 8-bit
3: Bits6: 6-bit

ALIGN

Bit 5: ALIGN.

Allowed values:
0: Right: Right alignment
1: Left: Left alignment

EXTSEL

Bits 6-9: EXTSEL.

Allowed values:
0: TIM1_CC1: Timer 1 CC1 event
1: TIM1_CC2: Timer 1 CC2 event
2: TIM1_CC3: Timer 1 CC3 event
3: TIM2_CC2: Timer 2 CC2 event
4: TIM3_TRGO: Timer 3 TRGO event
6: EXTI11: EXTI line 11
7: HRTIM_ADCTRG1: HRTIM_ADCTRG1 event
8: HRTIM_ADCTRG3: HRTIM_ADCTRG3 event
9: TIM1_TRGO: Timer 1 TRGO event
10: TIM1_TRGO2: Timer 1 TRGO2 event
11: TIM2_TRGO: Timer 2 TRGO event
13: TIM6_TRGO: Timer 6 TRGO event
14: TIM15_TRGO: Timer 15 TRGO event
15: TIM3_CC4: Timer 3 CC4 event

EXTEN

Bits 10-11: EXTEN.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

OVRMOD

Bit 12: OVRMOD.

Allowed values:
0: Preserve: Preserve DR register when an overrun is detected
1: Overwrite: Overwrite DR register when an overrun is detected

CONT

Bit 13: CONT.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

AUTDLY

Bit 14: AUTDLY.

Allowed values:
0: Off: Auto delayed conversion mode off
1: On: Auto delayed conversion mode on

DISCEN

Bit 16: DISCEN.

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

DISCNUM

Bits 17-19: DISCNUM.

Allowed values: 0x0-0x7

JDISCEN

Bit 20: JDISCEN.

Allowed values:
0: Disabled: Discontinuous mode on injected channels disabled
1: Enabled: Discontinuous mode on injected channels enabled

JQM

Bit 21: JQM.

Allowed values:
0: Mode0: JSQR Mode 0: Queue maintains the last written configuration into JSQR
1: Mode1: JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence

AWD1SGL

Bit 22: AWD1SGL.

Allowed values:
0: All: Analog watchdog 1 enabled on all channels
1: Single: Analog watchdog 1 enabled on single channel selected in AWD1CH

AWD1EN

Bit 23: AWD1EN.

Allowed values:
0: Disabled: Analog watchdog 1 disabled on regular channels
1: Enabled: Analog watchdog 1 enabled on regular channels

JAWD1EN

Bit 24: JAWD1EN.

Allowed values:
0: Disabled: Analog watchdog 1 disabled on injected channels
1: Enabled: Analog watchdog 1 enabled on injected channels

JAUTO

Bit 25: JAUTO.

Allowed values:
0: Disabled: Automatic injected group conversion disabled
1: Enabled: Automatic injected group conversion enabled

AWD1CH

Bits 26-30: AWDCH1CH.

Allowed values: 0x0-0x13

SMPR1

sample time register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP9
rw 		SMP8
rw 		SMP7
rw 		SMP6
rw 		SMP5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP5
rw 		SMP4
rw 		SMP3
rw 		SMP2
rw 		SMP1
rw
Toggle fields

SMP1

Bits 3-5: SMP1.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles

SMP2

Bits 6-8: SMP2.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles

SMP3

Bits 9-11: SMP3.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles

SMP4

Bits 12-14: SMP4.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles

SMP5

Bits 15-17: SMP5.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles

SMP6

Bits 18-20: SMP6.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles

SMP7

Bits 21-23: SMP7.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles

SMP8

Bits 24-26: SMP8.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles

SMP9

Bits 27-29: SMP9.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles

SMPR2

sample time register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP18
rw 		SMP17
rw 		SMP16
rw 		SMP15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP15
rw 		SMP14
rw 		SMP13
rw 		SMP12
rw 		SMP11
rw 		SMP10
rw
Toggle fields

SMP10

Bits 0-2: SMP10.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles

SMP11

Bits 3-5: SMP11.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles

SMP12

Bits 6-8: SMP12.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles

SMP13

Bits 9-11: SMP13.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles

SMP14

Bits 12-14: SMP14.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles

SMP15

Bits 15-17: SMP15.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles

SMP16

Bits 18-20: SMP16.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles

SMP17

Bits 21-23: SMP17.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles

SMP18

Bits 24-26: SMP18.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles

TR1

watchdog threshold register 1

Offset: 0x20, size: 32, reset: 0x0FFF0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT1
rw
Toggle fields

LT1

Bits 0-11: LT1.

Allowed values: 0x0-0xfff

HT1

Bits 16-27: HT1.

Allowed values: 0x0-0xfff

TR2

watchdog threshold register

Offset: 0x24, size: 32, reset: 0x0FFF0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT2
rw
Toggle fields

LT2

Bits 0-7: LT2.

Allowed values: 0x0-0xff

HT2

Bits 16-23: HT2.

Allowed values: 0x0-0xff

TR3

watchdog threshold register 3

Offset: 0x28, size: 32, reset: 0x0FFF0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT3
rw
Toggle fields

LT3

Bits 0-7: LT3.

Allowed values: 0x0-0xff

HT3

Bits 16-23: HT3.

Allowed values: 0x0-0xff

SQR1

regular sequence register 1

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ4
rw 		SQ3
rw 		SQ2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ2
rw 		SQ1
rw 		L
rw
Toggle fields

L

Bits 0-3: L3.

Allowed values: 0x0-0xf

SQ1

Bits 6-10: SQ1.

Allowed values: 0x0-0x13

SQ2

Bits 12-16: SQ2.

Allowed values: 0x0-0x13

SQ3

Bits 18-22: SQ3.

Allowed values: 0x0-0x13

SQ4

Bits 24-28: SQ4.

Allowed values: 0x0-0x13

SQR2

regular sequence register 2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ9
rw 		SQ8
rw 		SQ7
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ7
rw 		SQ6
rw 		SQ5
rw
Toggle fields

SQ5

Bits 0-4: SQ5.

Allowed values: 0x0-0x13

SQ6

Bits 6-10: SQ6.

Allowed values: 0x0-0x13

SQ7

Bits 12-16: SQ7.

Allowed values: 0x0-0x13

SQ8

Bits 18-22: SQ8.

Allowed values: 0x0-0x13

SQ9

Bits 24-28: SQ9.

Allowed values: 0x0-0x13

SQR3

regular sequence register 3

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ14
rw 		SQ13
rw 		SQ12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ12
rw 		SQ11
rw 		SQ10
rw
Toggle fields

SQ10

Bits 0-4: SQ10.

Allowed values: 0x0-0x13

SQ11

Bits 6-10: SQ11.

Allowed values: 0x0-0x13

SQ12

Bits 12-16: SQ12.

Allowed values: 0x0-0x13

SQ13

Bits 18-22: SQ13.

Allowed values: 0x0-0x13

SQ14

Bits 24-28: SQ14.

Allowed values: 0x0-0x13

SQR4

regular sequence register 4

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ16
rw 		SQ15
rw
Toggle fields

SQ15

Bits 0-4: SQ15.

Allowed values: 0x0-0x13

SQ16

Bits 6-10: SQ16.

Allowed values: 0x0-0x13

DR

regular Data Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
Toggle fields

RDATA

Bits 0-15: Regular data.

JSQR

injected sequence register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JSQ4
rw 		JSQ3
rw 		JSQ2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JSQ2
rw 		JSQ1
rw 		JEXTEN
rw 		JEXTSEL
rw 		JL
rw
Toggle fields

JL

Bits 0-1: JL.

Allowed values: 0x0-0x3

JEXTSEL

Bits 2-5: JEXTSEL.

Allowed values:
0: TIM1_TRGO: Timer 1 TRGO event
1: TIM1_CC4: Timer 1 CC4 event
2: TIM2_TRGO: Timer 2 TRGO event
3: TIM2_CC1: Timer 2 CC1 event
4: TIM3_CC4: Timer 3 CC4 event
6: EXTI15: EXTI line 15
8: TIM1_TRGO2: Timer 1 TRGO2 event
9: HRTIM_ADCTRG2: HRTIM_ADCTRG2 event
10: HRTIM_ADCTRG4: HRTIM_ADCTRG4 event
11: TIM3_CC3: Timer 3 CC3 event
12: TIM3_TRGO: Timer 3 TRGO event
13: TIM3_CC1: Timer 3 CC1 event
14: TIM6_TRGO: Timer 6 TRGO event
15: TIM15_TRGO: Timer 15 TRGO event

JEXTEN

Bits 6-7: JEXTEN.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

JSQ1

Bits 8-12: JSQ1.

Allowed values: 0x0-0x13

JSQ2

Bits 14-18: JSQ2.

Allowed values: 0x0-0x13

JSQ3

Bits 20-24: JSQ3.

Allowed values: 0x0-0x13

JSQ4

Bits 26-30: JSQ4.

Allowed values: 0x0-0x13

OFR1

offset register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET1_EN
rw 		OFFSET1_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET1
rw
Toggle fields

OFFSET1

Bits 0-11: OFFSET1.

Allowed values: 0x0-0xfff

OFFSET1_CH

Bits 26-30: OFFSET1_CH.

Allowed values: 0x0-0x1f

OFFSET1_EN

Bit 31: OFFSET1_EN.

Allowed values:
0: Disabled: Offset disabled
1: Enabled: Offset enabled

OFR2

offset register 2

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET2_EN
rw 		OFFSET2_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET2
rw
Toggle fields

OFFSET2

Bits 0-11: OFFSET2.

Allowed values: 0x0-0xfff

OFFSET2_CH

Bits 26-30: OFFSET2_CH.

Allowed values: 0x0-0x1f

OFFSET2_EN

Bit 31: OFFSET2_EN.

Allowed values:
0: Disabled: Offset disabled
1: Enabled: Offset enabled

OFR3

offset register 3

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET3_EN
rw 		OFFSET3_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET3
rw
Toggle fields

OFFSET3

Bits 0-11: OFFSET3.

Allowed values: 0x0-0xfff

OFFSET3_CH

Bits 26-30: OFFSET3_CH.

Allowed values: 0x0-0x1f

OFFSET3_EN

Bit 31: OFFSET3_EN.

Allowed values:
0: Disabled: Offset disabled
1: Enabled: Offset enabled

OFR4

offset register 4

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET4_EN
rw 		OFFSET4_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET4
rw
Toggle fields

OFFSET4

Bits 0-11: OFFSET4.

Allowed values: 0x0-0xfff

OFFSET4_CH

Bits 26-30: OFFSET4_CH.

Allowed values: 0x0-0x1f

OFFSET4_EN

Bit 31: OFFSET4_EN.

Allowed values:
0: Disabled: Offset disabled
1: Enabled: Offset enabled

JDR1

injected data register 1

Offset: 0x80, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA1
r
Toggle fields

JDATA1

Bits 0-15: JDATA1.

JDR2

injected data register 2

Offset: 0x84, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA2
r
Toggle fields

JDATA2

Bits 0-15: JDATA2.

JDR3

injected data register 3

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA3
r
Toggle fields

JDATA3

Bits 0-15: JDATA3.

JDR4

injected data register 4

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA4
r
Toggle fields

JDATA4

Bits 0-15: JDATA4.

AWD2CR

Analog Watchdog 2 Configuration Register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD2CH17
rw 		AWD2CH16
rw 		AWD2CH15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWD2CH14
rw 		AWD2CH13
rw 		AWD2CH12
rw 		AWD2CH11
rw 		AWD2CH10
rw 		AWD2CH9
rw 		AWD2CH8
rw 		AWD2CH7
rw 		AWD2CH6
rw 		AWD2CH5
rw 		AWD2CH4
rw 		AWD2CH3
rw 		AWD2CH2
rw 		AWD2CH1
rw 		AWD2CH0
rw
Toggle fields

AWD2CH0

Bit 1: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH1

Bit 2: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH2

Bit 3: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH3

Bit 4: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH4

Bit 5: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH5

Bit 6: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH6

Bit 7: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH7

Bit 8: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH8

Bit 9: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH9

Bit 10: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH10

Bit 11: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH11

Bit 12: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH12

Bit 13: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH13

Bit 14: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH14

Bit 15: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH15

Bit 16: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH16

Bit 17: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH17

Bit 18: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CR

Analog Watchdog 3 Configuration Register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD3CH17
rw 		AWD3CH16
rw 		AWD3CH15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWD3CH14
rw 		AWD3CH13
rw 		AWD3CH12
rw 		AWD3CH11
rw 		AWD3CH10
rw 		AWD3CH9
rw 		AWD3CH8
rw 		AWD3CH7
rw 		AWD3CH6
rw 		AWD3CH5
rw 		AWD3CH4
rw 		AWD3CH3
rw 		AWD3CH2
rw 		AWD3CH1
rw 		AWD3CH0
rw
Toggle fields

AWD3CH0

Bit 1: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH1

Bit 2: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH2

Bit 3: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH3

Bit 4: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH4

Bit 5: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH5

Bit 6: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH6

Bit 7: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH7

Bit 8: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH8

Bit 9: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH9

Bit 10: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH10

Bit 11: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH11

Bit 12: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH12

Bit 13: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH13

Bit 14: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH14

Bit 15: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH15

Bit 16: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH16

Bit 17: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH17

Bit 18: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

DIFSEL

Differential Mode Selection Register 2

Offset: 0xb0, size: 32, reset: 0x00000000, access: Unspecified

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIFSEL_117
N/A 		DIFSEL_116
N/A 		DIFSEL_115
N/A
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIFSEL_114
N/A 		DIFSEL_113
N/A 		DIFSEL_112
N/A 		DIFSEL_111
N/A 		DIFSEL_110
N/A 		DIFSEL_19
N/A 		DIFSEL_18
N/A 		DIFSEL_17
N/A 		DIFSEL_16
N/A 		DIFSEL_15
N/A 		DIFSEL_14
N/A 		DIFSEL_13
N/A 		DIFSEL_12
N/A 		DIFSEL_11
N/A 		DIFSEL_10
N/A
Toggle fields

DIFSEL_10

Bit 1: Differential mode for channels 15 to 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL_11

Bit 2: Differential mode for channels 15 to 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL_12

Bit 3: Differential mode for channels 15 to 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL_13

Bit 4: Differential mode for channels 15 to 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL_14

Bit 5: Differential mode for channels 15 to 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL_15

Bit 6: Differential mode for channels 15 to 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL_16

Bit 7: Differential mode for channels 15 to 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL_17

Bit 8: Differential mode for channels 15 to 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL_18

Bit 9: Differential mode for channels 15 to 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL_19

Bit 10: Differential mode for channels 15 to 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL_110

Bit 11: Differential mode for channels 15 to 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL_111

Bit 12: Differential mode for channels 15 to 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL_112

Bit 13: Differential mode for channels 15 to 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL_113

Bit 14: Differential mode for channels 15 to 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL_114

Bit 15: Differential mode for channels 15 to 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL_115

Bit 16: Differential mode for channels 15 to 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL_116

Bit 17: Differential mode for channels 15 to 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL_117

Bit 18: Differential mode for channels 15 to 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

CALFACT

Calibration Factors

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CALFACT_D
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALFACT_S
rw
Toggle fields

CALFACT_S

Bits 0-6: CALFACT_S.

Allowed values: 0x0-0x7f

CALFACT_D

Bits 16-22: CALFACT_D.

Allowed values: 0x0-0x7f

ADC1_2

0x50000300: ADC common registers

32/32 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CSR
0x8 CCR
0xc CDR
Toggle registers

CSR

ADC Common status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JQOVF_SLV
r 		AWD3_SLV
r 		AWD2_SLV
r 		AWD1_SLV
r 		JEOS_SLV
r 		JEOC_SLV
r 		OVR_SLV
r 		EOS_SLV
r 		EOC_SLV
r 		EOSMP_SLV
r 		ADRDY_SLV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVF_MST
r 		AWD3_MST
r 		AWD2_MST
r 		AWD1_MST
r 		JEOS_MST
r 		JEOC_MST
r 		OVR_MST
r 		EOS_MST
r 		EOC_MST
r 		EOSMP_MST
r 		ADRDY_MST
r
Toggle fields

ADRDY_MST

Bit 0: Master ADC ready.

Allowed values:
0: NotReady: ADC is not ready to start conversion
1: Ready: ADC is ready to start conversion

EOSMP_MST

Bit 1: End of Sampling phase flag of the master ADC.

Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached

EOC_MST

Bit 2: End of regular conversion of the master ADC.

Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete

EOS_MST

Bit 3: End of regular sequence flag of the master ADC.

Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete

OVR_MST

Bit 4: Overrun flag of the master ADC.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

JEOC_MST

Bit 5: End of injected conversion flag of the master ADC.

Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete

JEOS_MST

Bit 6: End of injected sequence flag of the master ADC.

Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete

AWD1_MST

Bit 7: Analog watchdog 1 flag of the master ADC.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD2_MST

Bit 8: Analog watchdog 2 flag of the master ADC.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD3_MST

Bit 9: Analog watchdog 3 flag of the master ADC.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

JQOVF_MST

Bit 10: Injected Context Queue Overflow flag of the master ADC.

Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred

ADRDY_SLV

Bit 16: Slave ADC ready.

Allowed values:
0: NotReady: ADC is not ready to start conversion
1: Ready: ADC is ready to start conversion

EOSMP_SLV

Bit 17: End of Sampling phase flag of the slave ADC.

Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached

EOC_SLV

Bit 18: End of regular conversion of the slave ADC.

Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete

EOS_SLV

Bit 19: End of regular sequence flag of the slave ADC.

Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete

OVR_SLV

Bit 20: Overrun flag of the slave ADC.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

JEOC_SLV

Bit 21: End of injected conversion flag of the slave ADC.

Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete

JEOS_SLV

Bit 22: End of injected sequence flag of the slave ADC.

Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete

AWD1_SLV

Bit 23: Analog watchdog 1 flag of the slave ADC.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD2_SLV

Bit 24: Analog watchdog 2 flag of the slave ADC.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD3_SLV

Bit 25: Analog watchdog 3 flag of the slave ADC.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

JQOVF_SLV

Bit 26: Injected Context Queue Overflow flag of the slave ADC.

Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred

CCR

ADC common control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VBATEN
rw 		TSEN
rw 		VREFEN
rw 		CKMODE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDMA
rw 		DMACFG
rw 		DELAY
rw 		DUAL
rw
Toggle fields

DUAL

Bits 0-4: Dual ADC mode selection.

Allowed values:
0: Independent: Independent mode
1: DualRJ: Dual, combined regular simultaneous + injected simultaneous mode
2: DualRA: Dual, combined regular simultaneous + alternate trigger mode
3: DualIJ: Dual, combined interleaved mode + injected simultaneous mode
5: DualJ: Dual, injected simultaneous mode only
6: DualR: Dual, regular simultaneous mode only
7: DualI: Dual, interleaved mode only
9: DualA: Dual, alternate trigger mode only

DELAY

Bits 8-11: Delay between 2 sampling phases.

Allowed values: 0x0-0xf

DMACFG

Bit 13: DMA configuration (for dual ADC mode).

Allowed values:
0: OneShot: DMA one shot mode selected
1: Circulator: DMA circular mode selected

MDMA

Bits 14-15: Direct memory access mode for dual ADC mode.

Allowed values:
0: Disabled: MDMA mode disabled
2: Bits12_10: MDMA mode enabled for 12 and 10-bit resolution
3: Bits8_6: MDMA mode enabled for 8 and 6-bit resolution

CKMODE

Bits 16-17: ADC clock mode.

Allowed values:
0: Asynchronous: Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock
1: SyncDiv1: Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck
2: SyncDiv2: Use AHB clock rcc_hclk3 divided by 2
3: SyncDiv4: Use AHB clock rcc_hclk3 divided by 4

VREFEN

Bit 22: VREFINT enable.

Allowed values:
0: Disabled: V_REFINT channel disabled
1: Enabled: V_REFINT channel enabled

TSEN

Bit 23: Temperature sensor enable.

Allowed values:
0: Disabled: Temperature sensor channel disabled
1: Enabled: Temperature sensor channel enabled

VBATEN

Bit 24: VBAT enable.

Allowed values:
0: Disabled: V_BAT channel disabled
1: Enabled: V_BAT channel enabled

CDR

ADC common regular data register for dual mode

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA_SLV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA_MST
r
Toggle fields

RDATA_MST

Bits 0-15: Regular data of the master ADC.

RDATA_SLV

Bits 16-31: Regular data of the slave ADC.

ADC2

0x50000100: Analog-to-Digital Converter

170/170 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 IER
0x8 CR
0xc CFGR
0x14 SMPR1
0x18 SMPR2
0x20 TR1
0x24 TR2
0x28 TR3
0x30 SQR1
0x34 SQR2
0x38 SQR3
0x3c SQR4
0x40 DR
0x4c JSQR
0x60 OFR1
0x64 OFR2
0x68 OFR3
0x6c OFR4
0x80 JDR1
0x84 JDR2
0x88 JDR3
0x8c JDR4
0xa0 AWD2CR
0xa4 AWD3CR
0xb0 DIFSEL
0xb4 CALFACT
Toggle registers

ISR

interrupt and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVF
rw 		AWD3
rw 		AWD2
rw 		AWD1
rw 		JEOS
rw 		JEOC
rw 		OVR
rw 		EOS
rw 		EOC
rw 		EOSMP
rw 		ADRDY
rw
Toggle fields

ADRDY

Bit 0: ADRDY.

Allowed values:
0: NotReady: ADC is not ready to start conversion
1: Ready: ADC is ready to start conversion

EOSMP

Bit 1: EOSMP.

Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached

EOC

Bit 2: EOC.

Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete

EOS

Bit 3: EOS.

Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete

OVR

Bit 4: OVR.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

JEOC

Bit 5: JEOC.

Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete

JEOS

Bit 6: JEOS.

Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete

AWD1

Bit 7: AWD1.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD2

Bit 8: AWD2.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD3

Bit 9: AWD3.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

JQOVF

Bit 10: JQOVF.

Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred

IER

interrupt enable register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVFIE
rw 		AWD3IE
rw 		AWD2IE
rw 		AWD1IE
rw 		JEOSIE
rw 		JEOCIE
rw 		OVRIE
rw 		EOSIE
rw 		EOCIE
rw 		EOSMPIE
rw 		ADRDYIE
rw
Toggle fields

ADRDYIE

Bit 0: ADRDYIE.

Allowed values:
0: Disabled: ADC ready interrupt disabled
1: Enabled: ADC ready interrupt enabled

EOSMPIE

Bit 1: EOSMPIE.

Allowed values:
0: Disabled: End of regular conversion sampling phase interrupt disabled
1: Enabled: End of regular conversion sampling phase interrupt enabled

EOCIE

Bit 2: EOCIE.

Allowed values:
0: Disabled: End of regular conversion interrupt disabled
1: Enabled: End of regular conversion interrupt enabled

EOSIE

Bit 3: EOSIE.

Allowed values:
0: Disabled: End of regular sequence interrupt disabled
1: Enabled: End of regular sequence interrupt enabled

OVRIE

Bit 4: OVRIE.

Allowed values:
0: Disabled: Overrun interrupt disabled
1: Enabled: Overrun interrupt enabled

JEOCIE

Bit 5: JEOCIE.

Allowed values:
0: Disabled: End of injected conversion interrupt disabled
1: Enabled: End of injected conversion interrupt enabled

JEOSIE

Bit 6: JEOSIE.

Allowed values:
0: Disabled: End of injected sequence interrupt disabled
1: Enabled: End of injected sequence interrupt enabled

AWD1IE

Bit 7: AWD1IE.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

AWD2IE

Bit 8: AWD2IE.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

AWD3IE

Bit 9: AWD3IE.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

JQOVFIE

Bit 10: JQOVFIE.

Allowed values:
0: Disabled: Injected context queue overflow interrupt disabled
1: Enabled: Injected context queue overflow interrupt enabled

CR

control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADCAL
rw 		ADCALDIF
rw 		ADVREGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JADSTP
rw 		ADSTP
rw 		JADSTART
rw 		ADSTART
rw 		ADDIS
rw 		ADEN
rw
Toggle fields

ADEN

Bit 0: ADEN.

Allowed values:
0: Disabled: ADC disabled
1: Enabled: ADC enabled

ADDIS

Bit 1: ADDIS.

Allowed values:
0: NotDisabling: No disable command active
1: Disabling: ADC disabling

ADSTART

Bit 2: ADSTART.

Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting

JADSTART

Bit 3: JADSTART.

Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting

ADSTP

Bit 4: ADSTP.

Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion

JADSTP

Bit 5: JADSTP.

Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion

ADVREGEN

Bits 28-29: ADVREGEN.

Allowed values:
0: Intermediate: Intermediate state required when moving the ADC voltage regulator between states
1: Enabled: ADC voltage regulator enabled
2: Disabled: ADC voltage regulator disabled

ADCALDIF

Bit 30: ADCALDIF.

Allowed values:
0: SingleEnded: Calibration for single-ended mode
1: Differential: Calibration for differential mode

ADCAL

Bit 31: ADCAL.

Allowed values:
0: Complete: Calibration complete
1: Calibration: Start the calibration of the ADC

CFGR

configuration register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD1CH
rw 		JAUTO
rw 		JAWD1EN
rw 		AWD1EN
rw 		AWD1SGL
rw 		JQM
rw 		JDISCEN
rw 		DISCNUM
rw 		DISCEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUTDLY
rw 		CONT
rw 		OVRMOD
rw 		EXTEN
rw 		EXTSEL
rw 		ALIGN
rw 		RES
rw 		DMACFG
rw 		DMAEN
rw
Toggle fields

DMAEN

Bit 0: DMAEN.

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

DMACFG

Bit 1: DMACFG.

Allowed values:
0: OneShot: DMA One Shot Mode selected
1: Circular: DMA circular mode selected

RES

Bits 3-4: RES.

Allowed values:
0: Bits12: 12-bit
1: Bits10: 10-bit
2: Bits8: 8-bit
3: Bits6: 6-bit

ALIGN

Bit 5: ALIGN.

Allowed values:
0: Right: Right alignment
1: Left: Left alignment

EXTSEL

Bits 6-9: EXTSEL.

Allowed values:
0: TIM1_CC1: Timer 1 CC1 event
1: TIM1_CC2: Timer 1 CC2 event
2: TIM1_CC3: Timer 1 CC3 event
3: TIM2_CC2: Timer 2 CC2 event
4: TIM3_TRGO: Timer 3 TRGO event
6: EXTI11: EXTI line 11
7: HRTIM_ADCTRG1: HRTIM_ADCTRG1 event
8: HRTIM_ADCTRG3: HRTIM_ADCTRG3 event
9: TIM1_TRGO: Timer 1 TRGO event
10: TIM1_TRGO2: Timer 1 TRGO2 event
11: TIM2_TRGO: Timer 2 TRGO event
13: TIM6_TRGO: Timer 6 TRGO event
14: TIM15_TRGO: Timer 15 TRGO event
15: TIM3_CC4: Timer 3 CC4 event

EXTEN

Bits 10-11: EXTEN.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

OVRMOD

Bit 12: OVRMOD.

Allowed values:
0: Preserve: Preserve DR register when an overrun is detected
1: Overwrite: Overwrite DR register when an overrun is detected

CONT

Bit 13: CONT.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

AUTDLY

Bit 14: AUTDLY.

Allowed values:
0: Off: Auto delayed conversion mode off
1: On: Auto delayed conversion mode on

DISCEN

Bit 16: DISCEN.

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

DISCNUM

Bits 17-19: DISCNUM.

Allowed values: 0x0-0x7

JDISCEN

Bit 20: JDISCEN.

Allowed values:
0: Disabled: Discontinuous mode on injected channels disabled
1: Enabled: Discontinuous mode on injected channels enabled

JQM

Bit 21: JQM.

Allowed values:
0: Mode0: JSQR Mode 0: Queue maintains the last written configuration into JSQR
1: Mode1: JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence

AWD1SGL

Bit 22: AWD1SGL.

Allowed values:
0: All: Analog watchdog 1 enabled on all channels
1: Single: Analog watchdog 1 enabled on single channel selected in AWD1CH

AWD1EN

Bit 23: AWD1EN.

Allowed values:
0: Disabled: Analog watchdog 1 disabled on regular channels
1: Enabled: Analog watchdog 1 enabled on regular channels

JAWD1EN

Bit 24: JAWD1EN.

Allowed values:
0: Disabled: Analog watchdog 1 disabled on injected channels
1: Enabled: Analog watchdog 1 enabled on injected channels

JAUTO

Bit 25: JAUTO.

Allowed values:
0: Disabled: Automatic injected group conversion disabled
1: Enabled: Automatic injected group conversion enabled

AWD1CH

Bits 26-30: AWDCH1CH.

Allowed values: 0x0-0x13

SMPR1

sample time register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP9
rw 		SMP8
rw 		SMP7
rw 		SMP6
rw 		SMP5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP5
rw 		SMP4
rw 		SMP3
rw 		SMP2
rw 		SMP1
rw
Toggle fields

SMP1

Bits 3-5: SMP1.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles

SMP2

Bits 6-8: SMP2.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles

SMP3

Bits 9-11: SMP3.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles

SMP4

Bits 12-14: SMP4.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles

SMP5

Bits 15-17: SMP5.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles

SMP6

Bits 18-20: SMP6.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles

SMP7

Bits 21-23: SMP7.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles

SMP8

Bits 24-26: SMP8.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles

SMP9

Bits 27-29: SMP9.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles

SMPR2

sample time register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP18
rw 		SMP17
rw 		SMP16
rw 		SMP15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP15
rw 		SMP14
rw 		SMP13
rw 		SMP12
rw 		SMP11
rw 		SMP10
rw
Toggle fields

SMP10

Bits 0-2: SMP10.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles

SMP11

Bits 3-5: SMP11.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles

SMP12

Bits 6-8: SMP12.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles

SMP13

Bits 9-11: SMP13.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles

SMP14

Bits 12-14: SMP14.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles

SMP15

Bits 15-17: SMP15.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles

SMP16

Bits 18-20: SMP16.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles

SMP17

Bits 21-23: SMP17.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles

SMP18

Bits 24-26: SMP18.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles4_5: 4.5 ADC clock cycles
3: Cycles7_5: 7.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles61_5: 61.5 ADC clock cycles
6: Cycles181_5: 181.5 ADC clock cycles
7: Cycles601_5: 601.5 ADC clock cycles

TR1

watchdog threshold register 1

Offset: 0x20, size: 32, reset: 0x0FFF0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT1
rw
Toggle fields

LT1

Bits 0-11: LT1.

Allowed values: 0x0-0xfff

HT1

Bits 16-27: HT1.

Allowed values: 0x0-0xfff

TR2

watchdog threshold register

Offset: 0x24, size: 32, reset: 0x0FFF0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT2
rw
Toggle fields

LT2

Bits 0-7: LT2.

Allowed values: 0x0-0xff

HT2

Bits 16-23: HT2.

Allowed values: 0x0-0xff

TR3

watchdog threshold register 3

Offset: 0x28, size: 32, reset: 0x0FFF0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT3
rw
Toggle fields

LT3

Bits 0-7: LT3.

Allowed values: 0x0-0xff

HT3

Bits 16-23: HT3.

Allowed values: 0x0-0xff

SQR1

regular sequence register 1

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ4
rw 		SQ3
rw 		SQ2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ2
rw 		SQ1
rw 		L
rw
Toggle fields

L

Bits 0-3: L3.

Allowed values: 0x0-0xf

SQ1

Bits 6-10: SQ1.

Allowed values: 0x0-0x13

SQ2

Bits 12-16: SQ2.

Allowed values: 0x0-0x13

SQ3

Bits 18-22: SQ3.

Allowed values: 0x0-0x13

SQ4

Bits 24-28: SQ4.

Allowed values: 0x0-0x13

SQR2

regular sequence register 2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ9
rw 		SQ8
rw 		SQ7
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ7
rw 		SQ6
rw 		SQ5
rw
Toggle fields

SQ5

Bits 0-4: SQ5.

Allowed values: 0x0-0x13

SQ6

Bits 6-10: SQ6.

Allowed values: 0x0-0x13

SQ7

Bits 12-16: SQ7.

Allowed values: 0x0-0x13

SQ8

Bits 18-22: SQ8.

Allowed values: 0x0-0x13

SQ9

Bits 24-28: SQ9.

Allowed values: 0x0-0x13

SQR3

regular sequence register 3

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ14
rw 		SQ13
rw 		SQ12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ12
rw 		SQ11
rw 		SQ10
rw
Toggle fields

SQ10

Bits 0-4: SQ10.

Allowed values: 0x0-0x13

SQ11

Bits 6-10: SQ11.

Allowed values: 0x0-0x13

SQ12

Bits 12-16: SQ12.

Allowed values: 0x0-0x13

SQ13

Bits 18-22: SQ13.

Allowed values: 0x0-0x13

SQ14

Bits 24-28: SQ14.

Allowed values: 0x0-0x13

SQR4

regular sequence register 4

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ16
rw 		SQ15
rw
Toggle fields

SQ15

Bits 0-4: SQ15.

Allowed values: 0x0-0x13

SQ16

Bits 6-10: SQ16.

Allowed values: 0x0-0x13

DR

regular Data Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
Toggle fields

RDATA

Bits 0-15: Regular data.

JSQR

injected sequence register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JSQ4
rw 		JSQ3
rw 		JSQ2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JSQ2
rw 		JSQ1
rw 		JEXTEN
rw 		JEXTSEL
rw 		JL
rw
Toggle fields

JL

Bits 0-1: JL.

Allowed values: 0x0-0x3

JEXTSEL

Bits 2-5: JEXTSEL.

Allowed values:
0: TIM1_TRGO: Timer 1 TRGO event
1: TIM1_CC4: Timer 1 CC4 event
2: TIM2_TRGO: Timer 2 TRGO event
3: TIM2_CC1: Timer 2 CC1 event
4: TIM3_CC4: Timer 3 CC4 event
6: EXTI15: EXTI line 15
8: TIM1_TRGO2: Timer 1 TRGO2 event
9: HRTIM_ADCTRG2: HRTIM_ADCTRG2 event
10: HRTIM_ADCTRG4: HRTIM_ADCTRG4 event
11: TIM3_CC3: Timer 3 CC3 event
12: TIM3_TRGO: Timer 3 TRGO event
13: TIM3_CC1: Timer 3 CC1 event
14: TIM6_TRGO: Timer 6 TRGO event
15: TIM15_TRGO: Timer 15 TRGO event

JEXTEN

Bits 6-7: JEXTEN.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

JSQ1

Bits 8-12: JSQ1.

Allowed values: 0x0-0x13

JSQ2

Bits 14-18: JSQ2.

Allowed values: 0x0-0x13

JSQ3

Bits 20-24: JSQ3.

Allowed values: 0x0-0x13

JSQ4

Bits 26-30: JSQ4.

Allowed values: 0x0-0x13

OFR1

offset register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET1_EN
rw 		OFFSET1_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET1
rw
Toggle fields

OFFSET1

Bits 0-11: OFFSET1.

Allowed values: 0x0-0xfff

OFFSET1_CH

Bits 26-30: OFFSET1_CH.

Allowed values: 0x0-0x1f

OFFSET1_EN

Bit 31: OFFSET1_EN.

Allowed values:
0: Disabled: Offset disabled
1: Enabled: Offset enabled

OFR2

offset register 2

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET2_EN
rw 		OFFSET2_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET2
rw
Toggle fields

OFFSET2

Bits 0-11: OFFSET2.

Allowed values: 0x0-0xfff

OFFSET2_CH

Bits 26-30: OFFSET2_CH.

Allowed values: 0x0-0x1f

OFFSET2_EN

Bit 31: OFFSET2_EN.

Allowed values:
0: Disabled: Offset disabled
1: Enabled: Offset enabled

OFR3

offset register 3

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET3_EN
rw 		OFFSET3_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET3
rw
Toggle fields

OFFSET3

Bits 0-11: OFFSET3.

Allowed values: 0x0-0xfff

OFFSET3_CH

Bits 26-30: OFFSET3_CH.

Allowed values: 0x0-0x1f

OFFSET3_EN

Bit 31: OFFSET3_EN.

Allowed values:
0: Disabled: Offset disabled
1: Enabled: Offset enabled

OFR4

offset register 4

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET4_EN
rw 		OFFSET4_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET4
rw
Toggle fields

OFFSET4

Bits 0-11: OFFSET4.

Allowed values: 0x0-0xfff

OFFSET4_CH

Bits 26-30: OFFSET4_CH.

Allowed values: 0x0-0x1f

OFFSET4_EN

Bit 31: OFFSET4_EN.

Allowed values:
0: Disabled: Offset disabled
1: Enabled: Offset enabled

JDR1

injected data register 1

Offset: 0x80, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA1
r
Toggle fields

JDATA1

Bits 0-15: JDATA1.

JDR2

injected data register 2

Offset: 0x84, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA2
r
Toggle fields

JDATA2

Bits 0-15: JDATA2.

JDR3

injected data register 3

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA3
r
Toggle fields

JDATA3

Bits 0-15: JDATA3.

JDR4

injected data register 4

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA4
r
Toggle fields

JDATA4

Bits 0-15: JDATA4.

AWD2CR

Analog Watchdog 2 Configuration Register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD2CH17
rw 		AWD2CH16
rw 		AWD2CH15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWD2CH14
rw 		AWD2CH13
rw 		AWD2CH12
rw 		AWD2CH11
rw 		AWD2CH10
rw 		AWD2CH9
rw 		AWD2CH8
rw 		AWD2CH7
rw 		AWD2CH6
rw 		AWD2CH5
rw 		AWD2CH4
rw 		AWD2CH3
rw 		AWD2CH2
rw 		AWD2CH1
rw 		AWD2CH0
rw
Toggle fields

AWD2CH0

Bit 1: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH1

Bit 2: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH2

Bit 3: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH3

Bit 4: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH4

Bit 5: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH5

Bit 6: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH6

Bit 7: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH7

Bit 8: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH8

Bit 9: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH9

Bit 10: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH10

Bit 11: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH11

Bit 12: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH12

Bit 13: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH13

Bit 14: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH14

Bit 15: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH15

Bit 16: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH16

Bit 17: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH17

Bit 18: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CR

Analog Watchdog 3 Configuration Register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD3CH17
rw 		AWD3CH16
rw 		AWD3CH15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWD3CH14
rw 		AWD3CH13
rw 		AWD3CH12
rw 		AWD3CH11
rw 		AWD3CH10
rw 		AWD3CH9
rw 		AWD3CH8
rw 		AWD3CH7
rw 		AWD3CH6
rw 		AWD3CH5
rw 		AWD3CH4
rw 		AWD3CH3
rw 		AWD3CH2
rw 		AWD3CH1
rw 		AWD3CH0
rw
Toggle fields

AWD3CH0

Bit 1: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH1

Bit 2: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH2

Bit 3: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH3

Bit 4: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH4

Bit 5: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH5

Bit 6: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH6

Bit 7: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH7

Bit 8: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH8

Bit 9: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH9

Bit 10: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH10

Bit 11: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH11

Bit 12: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH12

Bit 13: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH13

Bit 14: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH14

Bit 15: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH15

Bit 16: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH16

Bit 17: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH17

Bit 18: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

DIFSEL

Differential Mode Selection Register 2

Offset: 0xb0, size: 32, reset: 0x00000000, access: Unspecified

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIFSEL_117
N/A 		DIFSEL_116
N/A 		DIFSEL_115
N/A
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIFSEL_114
N/A 		DIFSEL_113
N/A 		DIFSEL_112
N/A 		DIFSEL_111
N/A 		DIFSEL_110
N/A 		DIFSEL_19
N/A 		DIFSEL_18
N/A 		DIFSEL_17
N/A 		DIFSEL_16
N/A 		DIFSEL_15
N/A 		DIFSEL_14
N/A 		DIFSEL_13
N/A 		DIFSEL_12
N/A 		DIFSEL_11
N/A 		DIFSEL_10
N/A
Toggle fields

DIFSEL_10

Bit 1: Differential mode for channels 15 to 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL_11

Bit 2: Differential mode for channels 15 to 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL_12

Bit 3: Differential mode for channels 15 to 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL_13

Bit 4: Differential mode for channels 15 to 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL_14

Bit 5: Differential mode for channels 15 to 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL_15

Bit 6: Differential mode for channels 15 to 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL_16

Bit 7: Differential mode for channels 15 to 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL_17

Bit 8: Differential mode for channels 15 to 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL_18

Bit 9: Differential mode for channels 15 to 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL_19

Bit 10: Differential mode for channels 15 to 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL_110

Bit 11: Differential mode for channels 15 to 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL_111

Bit 12: Differential mode for channels 15 to 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL_112

Bit 13: Differential mode for channels 15 to 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL_113

Bit 14: Differential mode for channels 15 to 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL_114

Bit 15: Differential mode for channels 15 to 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL_115

Bit 16: Differential mode for channels 15 to 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL_116

Bit 17: Differential mode for channels 15 to 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL_117

Bit 18: Differential mode for channels 15 to 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

CALFACT

Calibration Factors

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CALFACT_D
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALFACT_S
rw
Toggle fields

CALFACT_S

Bits 0-6: CALFACT_S.

Allowed values: 0x0-0x7f

CALFACT_D

Bits 16-22: CALFACT_D.

Allowed values: 0x0-0x7f

CAN

0x40006400: Controller area network

82/323 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MCR
0x4 MSR
0x8 TSR
0xc RF[0]R
0x10 RF[1]R
0x14 IER
0x18 ESR
0x1c BTR
0x180 TIR [0]
0x184 TDTR [0]
0x188 TDLR [0]
0x18c TDHR [0]
0x190 TIR [1]
0x194 TDTR [1]
0x198 TDLR [1]
0x19c TDHR [1]
0x1a0 TIR [2]
0x1a4 TDTR [2]
0x1a8 TDLR [2]
0x1ac TDHR [2]
0x1b0 RIR [0]
0x1b4 RDTR [0]
0x1b8 RDLR [0]
0x1bc RDHR [0]
0x1c0 RIR [1]
0x1c4 RDTR [1]
0x1c8 RDLR [1]
0x1cc RDHR [1]
0x200 FMR
0x204 FM1R
0x20c FS1R
0x214 FFA1R
0x21c FA1R
0x240 FR1 [0]
0x244 FR2 [0]
0x248 FR1 [1]
0x24c FR2 [1]
0x250 FR1 [2]
0x254 FR2 [2]
0x258 FR1 [3]
0x25c FR2 [3]
0x260 FR1 [4]
0x264 FR2 [4]
0x268 FR1 [5]
0x26c FR2 [5]
0x270 FR1 [6]
0x274 FR2 [6]
0x278 FR1 [7]
0x27c FR2 [7]
0x280 FR1 [8]
0x284 FR2 [8]
0x288 FR1 [9]
0x28c FR2 [9]
0x290 FR1 [10]
0x294 FR2 [10]
0x298 FR1 [11]
0x29c FR2 [11]
0x2a0 FR1 [12]
0x2a4 FR2 [12]
0x2a8 FR1 [13]
0x2ac FR2 [13]
0x2b0 FR1 [14]
0x2b4 FR2 [14]
0x2b8 FR1 [15]
0x2bc FR2 [15]
0x2c0 FR1 [16]
0x2c4 FR2 [16]
0x2c8 FR1 [17]
0x2cc FR2 [17]
0x2d0 FR1 [18]
0x2d4 FR2 [18]
0x2d8 FR1 [19]
0x2dc FR2 [19]
0x2e0 FR1 [20]
0x2e4 FR2 [20]
0x2e8 FR1 [21]
0x2ec FR2 [21]
0x2f0 FR1 [22]
0x2f4 FR2 [22]
0x2f8 FR1 [23]
0x2fc FR2 [23]
0x300 FR1 [24]
0x304 FR2 [24]
0x308 FR1 [25]
0x30c FR2 [25]
0x310 FR1 [26]
0x314 FR2 [26]
0x318 FR1 [27]
0x31c FR2 [27]
Toggle registers

MCR

master control register

Offset: 0x0, size: 32, reset: 0x00010002, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET
rw 		TTCM
rw 		ABOM
rw 		AWUM
rw 		NART
rw 		RFLM
rw 		TXFP
rw 		SLEEP
rw 		INRQ
rw
Toggle fields

INRQ

Bit 0: INRQ.

SLEEP

Bit 1: SLEEP.

TXFP

Bit 2: TXFP.

RFLM

Bit 3: RFLM.

NART

Bit 4: NART.

AWUM

Bit 5: AWUM.

ABOM

Bit 6: ABOM.

TTCM

Bit 7: TTCM.

RESET

Bit 15: RESET.

DBF

Bit 16: DBF.

MSR

master status register

Offset: 0x4, size: 32, reset: 0x00000C02, access: Unspecified

6/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX
r 		SAMP
r 		RXM
r 		TXM
r 		SLAKI
rw 		WKUI
rw 		ERRI
rw 		SLAK
r 		INAK
r
Toggle fields

INAK

Bit 0: INAK.

SLAK

Bit 1: SLAK.

ERRI

Bit 2: ERRI.

WKUI

Bit 3: WKUI.

SLAKI

Bit 4: SLAKI.

TXM

Bit 8: TXM.

RXM

Bit 9: RXM.

SAMP

Bit 10: SAMP.

RX

Bit 11: RX.

TSR

transmit status register

Offset: 0x8, size: 32, reset: 0x1C000000, access: Unspecified

7/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOW[2]
r 		LOW[1]
r 		LOW[0]
r 		TME[2]
r 		TME[1]
r 		TME[0]
r 		CODE
r 		ABRQ2
rw 		TERR2
rw 		ALST2
rw 		TXOK2
rw 		RQCP2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRQ1
rw 		TERR1
rw 		ALST1
rw 		TXOK1
rw 		RQCP1
rw 		ABRQ0
rw 		TERR0
rw 		ALST0
rw 		TXOK0
rw 		RQCP0
rw
Toggle fields

RQCP0

Bit 0: RQCP0.

TXOK0

Bit 1: TXOK0.

ALST0

Bit 2: ALST0.

TERR0

Bit 3: TERR0.

ABRQ0

Bit 7: ABRQ0.

RQCP1

Bit 8: RQCP1.

TXOK1

Bit 9: TXOK1.

ALST1

Bit 10: ALST1.

TERR1

Bit 11: TERR1.

ABRQ1

Bit 15: ABRQ1.

RQCP2

Bit 16: RQCP2.

TXOK2

Bit 17: TXOK2.

ALST2

Bit 18: ALST2.

TERR2

Bit 19: TERR2.

ABRQ2

Bit 23: ABRQ2.

CODE

Bits 24-25: CODE.

TME[0]

Bit 26: Lowest priority flag for mailbox 0.

TME[1]

Bit 27: Lowest priority flag for mailbox 1.

TME[2]

Bit 28: Lowest priority flag for mailbox 2.

LOW[0]

Bit 29: Lowest priority flag for mailbox 0.

LOW[1]

Bit 30: Lowest priority flag for mailbox 1.

LOW[2]

Bit 31: Lowest priority flag for mailbox 2.

RF[0]R

receive FIFO 0 register

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFOM
rw 		FOVR
rw 		FULL
rw 		FMP
r
Toggle fields

FMP

Bits 0-1: FMP0.

FULL

Bit 3: FULL0.

Allowed values:
0: NotFull: FIFO x is not full
1: Full: FIFO x is full

FOVR

Bit 4: FOVR0.

Allowed values:
0: NoOverrun: No FIFO x overrun
1: Overrun: FIFO x overrun

RFOM

Bit 5: RFOM0.

Allowed values:
1: Release: Set by software to release the output mailbox of the FIFO

RF[1]R

receive FIFO 1 register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFOM
rw 		FOVR
rw 		FULL
rw 		FMP
r
Toggle fields

FMP

Bits 0-1: FMP0.

FULL

Bit 3: FULL0.

Allowed values:
0: NotFull: FIFO x is not full
1: Full: FIFO x is full

FOVR

Bit 4: FOVR0.

Allowed values:
0: NoOverrun: No FIFO x overrun
1: Overrun: FIFO x overrun

RFOM

Bit 5: RFOM0.

Allowed values:
1: Release: Set by software to release the output mailbox of the FIFO

IER

interrupt enable register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLKIE
rw 		WKUIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRIE
rw 		LECIE
rw 		BOFIE
rw 		EPVIE
rw 		EWGIE
rw 		FOVIE1
rw 		FFIE1
rw 		FMPIE1
rw 		FOVIE0
rw 		FFIE0
rw 		FMPIE0
rw 		TMEIE
rw
Toggle fields

TMEIE

Bit 0: TMEIE.

Allowed values:
0: Disabled: No interrupt when RQCPx bit is set
1: Enabled: Interrupt generated when RQCPx bit is set

FMPIE0

Bit 1: FMPIE0.

Allowed values:
0: Disabled: No interrupt generated when state of FMP[1:0] bits are not 00
1: Enabled: Interrupt generated when state of FMP[1:0] bits are not 00b

FFIE0

Bit 2: FFIE0.

Allowed values:
0: Disabled: No interrupt when FULL bit is set
1: Enabled: Interrupt generated when FULL bit is set

FOVIE0

Bit 3: FOVIE0.

Allowed values:
0: Disabled: No interrupt when FOVR bit is set
1: Enabled: Interrupt generated when FOVR bit is set

FMPIE1

Bit 4: FMPIE1.

Allowed values:
0: Disabled: No interrupt generated when state of FMP[1:0] bits are not 00b
1: Enabled: Interrupt generated when state of FMP[1:0] bits are not 00b

FFIE1

Bit 5: FFIE1.

Allowed values:
0: Disabled: No interrupt when FULL bit is set
1: Enabled: Interrupt generated when FULL bit is set

FOVIE1

Bit 6: FOVIE1.

Allowed values:
0: Disabled: No interrupt when FOVR is set
1: Enabled: Interrupt generation when FOVR is set

EWGIE

Bit 8: EWGIE.

Allowed values:
0: Disabled: ERRI bit will not be set when EWGF is set
1: Enabled: ERRI bit will be set when EWGF is set

EPVIE

Bit 9: EPVIE.

Allowed values:
0: Disabled: ERRI bit will not be set when EPVF is set
1: Enabled: ERRI bit will be set when EPVF is set

BOFIE

Bit 10: BOFIE.

Allowed values:
0: Disabled: ERRI bit will not be set when BOFF is set
1: Enabled: ERRI bit will be set when BOFF is set

LECIE

Bit 11: LECIE.

Allowed values:
0: Disabled: ERRI bit will not be set when the error code in LEC[2:0] is set by hardware on error detection
1: Enabled: ERRI bit will be set when the error code in LEC[2:0] is set by hardware on error detection

ERRIE

Bit 15: ERRIE.

Allowed values:
0: Disabled: No interrupt will be generated when an error condition is pending in the CAN_ESR
1: Enabled: An interrupt will be generation when an error condition is pending in the CAN_ESR

WKUIE

Bit 16: WKUIE.

Allowed values:
0: Disabled: No interrupt when WKUI is set
1: Enabled: Interrupt generated when WKUI bit is set

SLKIE

Bit 17: SLKIE.

Allowed values:
0: Disabled: No interrupt when SLAKI bit is set
1: Enabled: Interrupt generated when SLAKI bit is set

ESR

error status register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REC
r 		TEC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LEC
rw 		BOFF
r 		EPVF
r 		EWGF
r
Toggle fields

EWGF

Bit 0: EWGF.

EPVF

Bit 1: EPVF.

BOFF

Bit 2: BOFF.

LEC

Bits 4-6: LEC.

Allowed values:
0: NoError: No Error
1: Stuff: Stuff Error
2: Form: Form Error
3: Ack: Acknowledgment Error
4: BitRecessive: Bit recessive Error
5: BitDominant: Bit dominant Error
6: Crc: CRC Error
7: Custom: Set by software

TEC

Bits 16-23: TEC.

REC

Bits 24-31: REC.

BTR

bit timing register

Offset: 0x1c, size: 32, reset: 0x01230000, access: read-write

2/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SILM
rw 		LBKM
rw 		SJW
rw 		TS2
rw 		TS1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRP
rw
Toggle fields

BRP

Bits 0-9: BRP.

TS1

Bits 16-19: TS1.

TS2

Bits 20-22: TS2.

SJW

Bits 24-25: SJW.

LBKM

Bit 30: LBKM.

Allowed values:
0: Disabled: Loop Back Mode disabled
1: Enabled: Loop Back Mode enabled

SILM

Bit 31: SILM.

Allowed values:
0: Normal: Normal operation
1: Silent: Silent Mode

TIR [0]

TX mailbox identifier register

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

2/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STID
rw 		EXID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXID
rw 		IDE
rw 		RTR
rw 		TXRQ
rw
Toggle fields

TXRQ

Bit 0: TXRQ.

RTR

Bit 1: RTR.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

IDE

Bit 2: IDE.

Allowed values:
0: Standard: Standard identifier
1: Extended: Extended identifier

EXID

Bits 3-20: EXID.

STID

Bits 21-31: STID.

TDTR [0]

mailbox data length control and time stamp register

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TGT
rw 		DLC
rw
Toggle fields

DLC

Bits 0-3: DLC.

Allowed values: 0x0-0x8

TGT

Bit 8: TGT.

TIME

Bits 16-31: TIME.

TDLR [0]

mailbox data low register

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA[3]
rw 		DATA[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA[1]
rw 		DATA[0]
rw
Toggle fields

DATA[0]

Bits 0-7: DATA0.

DATA[1]

Bits 8-15: DATA1.

DATA[2]

Bits 16-23: DATA2.

DATA[3]

Bits 24-31: DATA3.

TDHR [0]

mailbox data high register

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA[7]
rw 		DATA[6]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA[5]
rw 		DATA[4]
rw
Toggle fields

DATA[4]

Bits 0-7: DATA4.

DATA[5]

Bits 8-15: DATA5.

DATA[6]

Bits 16-23: DATA6.

DATA[7]

Bits 24-31: DATA7.

TIR [1]

TX mailbox identifier register

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

2/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STID
rw 		EXID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXID
rw 		IDE
rw 		RTR
rw 		TXRQ
rw
Toggle fields

TXRQ

Bit 0: TXRQ.

RTR

Bit 1: RTR.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

IDE

Bit 2: IDE.

Allowed values:
0: Standard: Standard identifier
1: Extended: Extended identifier

EXID

Bits 3-20: EXID.

STID

Bits 21-31: STID.

TDTR [1]

mailbox data length control and time stamp register

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TGT
rw 		DLC
rw
Toggle fields

DLC

Bits 0-3: DLC.

Allowed values: 0x0-0x8

TGT

Bit 8: TGT.

TIME

Bits 16-31: TIME.

TDLR [1]

mailbox data low register

Offset: 0x198, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA[3]
rw 		DATA[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA[1]
rw 		DATA[0]
rw
Toggle fields

DATA[0]

Bits 0-7: DATA0.

DATA[1]

Bits 8-15: DATA1.

DATA[2]

Bits 16-23: DATA2.

DATA[3]

Bits 24-31: DATA3.

TDHR [1]

mailbox data high register

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA[7]
rw 		DATA[6]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA[5]
rw 		DATA[4]
rw
Toggle fields

DATA[4]

Bits 0-7: DATA4.

DATA[5]

Bits 8-15: DATA5.

DATA[6]

Bits 16-23: DATA6.

DATA[7]

Bits 24-31: DATA7.

TIR [2]

TX mailbox identifier register

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

2/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STID
rw 		EXID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXID
rw 		IDE
rw 		RTR
rw 		TXRQ
rw
Toggle fields

TXRQ

Bit 0: TXRQ.

RTR

Bit 1: RTR.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

IDE

Bit 2: IDE.

Allowed values:
0: Standard: Standard identifier
1: Extended: Extended identifier

EXID

Bits 3-20: EXID.

STID

Bits 21-31: STID.

TDTR [2]

mailbox data length control and time stamp register

Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TGT
rw 		DLC
rw
Toggle fields

DLC

Bits 0-3: DLC.

Allowed values: 0x0-0x8

TGT

Bit 8: TGT.

TIME

Bits 16-31: TIME.

TDLR [2]

mailbox data low register

Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA[3]
rw 		DATA[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA[1]
rw 		DATA[0]
rw
Toggle fields

DATA[0]

Bits 0-7: DATA0.

DATA[1]

Bits 8-15: DATA1.

DATA[2]

Bits 16-23: DATA2.

DATA[3]

Bits 24-31: DATA3.

TDHR [2]

mailbox data high register

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA[7]
rw 		DATA[6]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA[5]
rw 		DATA[4]
rw
Toggle fields

DATA[4]

Bits 0-7: DATA4.

DATA[5]

Bits 8-15: DATA5.

DATA[6]

Bits 16-23: DATA6.

DATA[7]

Bits 24-31: DATA7.

RIR [0]

receive FIFO mailbox identifier register

Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STID
r 		EXID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXID
r 		IDE
r 		RTR
r
Toggle fields

RTR

Bit 1: RTR.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

IDE

Bit 2: IDE.

Allowed values:
0: Standard: Standard identifier
1: Extended: Extended identifier

EXID

Bits 3-20: EXID.

STID

Bits 21-31: STID.

RDTR [0]

receive FIFO mailbox data length control and time stamp register

Offset: 0x1b4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIME
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMI
r 		DLC
r
Toggle fields

DLC

Bits 0-3: DLC.

Allowed values: 0x0-0x8

FMI

Bits 8-15: FMI.

TIME

Bits 16-31: TIME.

RDLR [0]

receive FIFO mailbox data low register

Offset: 0x1b8, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA[3]
r 		DATA[2]
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA[1]
r 		DATA[0]
r
Toggle fields

DATA[0]

Bits 0-7: DATA0.

DATA[1]

Bits 8-15: DATA1.

DATA[2]

Bits 16-23: DATA2.

DATA[3]

Bits 24-31: DATA3.

RDHR [0]

receive FIFO mailbox data high register

Offset: 0x1bc, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA[7]
r 		DATA[6]
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA[5]
r 		DATA[4]
r
Toggle fields

DATA[4]

Bits 0-7: DATA4.

DATA[5]

Bits 8-15: DATA5.

DATA[6]

Bits 16-23: DATA6.

DATA[7]

Bits 24-31: DATA7.

RIR [1]

receive FIFO mailbox identifier register

Offset: 0x1c0, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STID
r 		EXID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXID
r 		IDE
r 		RTR
r
Toggle fields

RTR

Bit 1: RTR.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

IDE

Bit 2: IDE.

Allowed values:
0: Standard: Standard identifier
1: Extended: Extended identifier

EXID

Bits 3-20: EXID.

STID

Bits 21-31: STID.

RDTR [1]

receive FIFO mailbox data length control and time stamp register

Offset: 0x1c4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIME
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMI
r 		DLC
r
Toggle fields

DLC

Bits 0-3: DLC.

Allowed values: 0x0-0x8

FMI

Bits 8-15: FMI.

TIME

Bits 16-31: TIME.

RDLR [1]

receive FIFO mailbox data low register

Offset: 0x1c8, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA[3]
r 		DATA[2]
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA[1]
r 		DATA[0]
r
Toggle fields

DATA[0]

Bits 0-7: DATA0.

DATA[1]

Bits 8-15: DATA1.

DATA[2]

Bits 16-23: DATA2.

DATA[3]

Bits 24-31: DATA3.

RDHR [1]

receive FIFO mailbox data high register

Offset: 0x1cc, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA[7]
r 		DATA[6]
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA[5]
r 		DATA[4]
r
Toggle fields

DATA[4]

Bits 0-7: DATA4.

DATA[5]

Bits 8-15: DATA5.

DATA[6]

Bits 16-23: DATA6.

DATA[7]

Bits 24-31: DATA7.

FMR

filter master register

Offset: 0x200, size: 32, reset: 0x2A1C0E01, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAN2SB
rw 		FINIT
rw
Toggle fields

FINIT

Bit 0: Filter init mode.

CAN2SB

Bits 8-13: CAN2 start bank.

FM1R

filter mode register

Offset: 0x204, size: 32, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FBM[27]
rw 		FBM[26]
rw 		FBM[25]
rw 		FBM[24]
rw 		FBM[23]
rw 		FBM[22]
rw 		FBM[21]
rw 		FBM[20]
rw 		FBM[19]
rw 		FBM[18]
rw 		FBM[17]
rw 		FBM[16]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FBM[15]
rw 		FBM[14]
rw 		FBM[13]
rw 		FBM[12]
rw 		FBM[11]
rw 		FBM[10]
rw 		FBM[9]
rw 		FBM[8]
rw 		FBM[7]
rw 		FBM[6]
rw 		FBM[5]
rw 		FBM[4]
rw 		FBM[3]
rw 		FBM[2]
rw 		FBM[1]
rw 		FBM[0]
rw
Toggle fields

FBM[0]

Bit 0: Filter mode.

FBM[1]

Bit 1: Filter mode.

FBM[2]

Bit 2: Filter mode.

FBM[3]

Bit 3: Filter mode.

FBM[4]

Bit 4: Filter mode.

FBM[5]

Bit 5: Filter mode.

FBM[6]

Bit 6: Filter mode.

FBM[7]

Bit 7: Filter mode.

FBM[8]

Bit 8: Filter mode.

FBM[9]

Bit 9: Filter mode.

FBM[10]

Bit 10: Filter mode.

FBM[11]

Bit 11: Filter mode.

FBM[12]

Bit 12: Filter mode.

FBM[13]

Bit 13: Filter mode.

FBM[14]

Bit 14: Filter mode.

FBM[15]

Bit 15: Filter mode.

FBM[16]

Bit 16: Filter mode.

FBM[17]

Bit 17: Filter mode.

FBM[18]

Bit 18: Filter mode.

FBM[19]

Bit 19: Filter mode.

FBM[20]

Bit 20: Filter mode.

FBM[21]

Bit 21: Filter mode.

FBM[22]

Bit 22: Filter mode.

FBM[23]

Bit 23: Filter mode.

FBM[24]

Bit 24: Filter mode.

FBM[25]

Bit 25: Filter mode.

FBM[26]

Bit 26: Filter mode.

FBM[27]

Bit 27: Filter mode.

FS1R

filter scale register

Offset: 0x20c, size: 32, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSC[27]
rw 		FSC[26]
rw 		FSC[25]
rw 		FSC[24]
rw 		FSC[23]
rw 		FSC[22]
rw 		FSC[21]
rw 		FSC[20]
rw 		FSC[19]
rw 		FSC[18]
rw 		FSC[17]
rw 		FSC[16]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSC[15]
rw 		FSC[14]
rw 		FSC[13]
rw 		FSC[12]
rw 		FSC[11]
rw 		FSC[10]
rw 		FSC[9]
rw 		FSC[8]
rw 		FSC[7]
rw 		FSC[6]
rw 		FSC[5]
rw 		FSC[4]
rw 		FSC[3]
rw 		FSC[2]
rw 		FSC[1]
rw 		FSC[0]
rw
Toggle fields

FSC[0]

Bit 0: Filter scale configuration.

FSC[1]

Bit 1: Filter scale configuration.

FSC[2]

Bit 2: Filter scale configuration.

FSC[3]

Bit 3: Filter scale configuration.

FSC[4]

Bit 4: Filter scale configuration.

FSC[5]

Bit 5: Filter scale configuration.

FSC[6]

Bit 6: Filter scale configuration.

FSC[7]

Bit 7: Filter scale configuration.

FSC[8]

Bit 8: Filter scale configuration.

FSC[9]

Bit 9: Filter scale configuration.

FSC[10]

Bit 10: Filter scale configuration.

FSC[11]

Bit 11: Filter scale configuration.

FSC[12]

Bit 12: Filter scale configuration.

FSC[13]

Bit 13: Filter scale configuration.

FSC[14]

Bit 14: Filter scale configuration.

FSC[15]

Bit 15: Filter scale configuration.

FSC[16]

Bit 16: Filter scale configuration.

FSC[17]

Bit 17: Filter scale configuration.

FSC[18]

Bit 18: Filter scale configuration.

FSC[19]

Bit 19: Filter scale configuration.

FSC[20]

Bit 20: Filter scale configuration.

FSC[21]

Bit 21: Filter scale configuration.

FSC[22]

Bit 22: Filter scale configuration.

FSC[23]

Bit 23: Filter scale configuration.

FSC[24]

Bit 24: Filter scale configuration.

FSC[25]

Bit 25: Filter scale configuration.

FSC[26]

Bit 26: Filter scale configuration.

FSC[27]

Bit 27: Filter scale configuration.

FFA1R

filter FIFO assignment register

Offset: 0x214, size: 32, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FFA[27]
rw 		FFA[26]
rw 		FFA[25]
rw 		FFA[24]
rw 		FFA[23]
rw 		FFA[22]
rw 		FFA[21]
rw 		FFA[20]
rw 		FFA[19]
rw 		FFA[18]
rw 		FFA[17]
rw 		FFA[16]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FFA[15]
rw 		FFA[14]
rw 		FFA[13]
rw 		FFA[12]
rw 		FFA[11]
rw 		FFA[10]
rw 		FFA[9]
rw 		FFA[8]
rw 		FFA[7]
rw 		FFA[6]
rw 		FFA[5]
rw 		FFA[4]
rw 		FFA[3]
rw 		FFA[2]
rw 		FFA[1]
rw 		FFA[0]
rw
Toggle fields

FFA[0]

Bit 0: Filter FIFO assignment for filter 0.

FFA[1]

Bit 1: Filter FIFO assignment for filter 1.

FFA[2]

Bit 2: Filter FIFO assignment for filter 2.

FFA[3]

Bit 3: Filter FIFO assignment for filter 3.

FFA[4]

Bit 4: Filter FIFO assignment for filter 4.

FFA[5]

Bit 5: Filter FIFO assignment for filter 5.

FFA[6]

Bit 6: Filter FIFO assignment for filter 6.

FFA[7]

Bit 7: Filter FIFO assignment for filter 7.

FFA[8]

Bit 8: Filter FIFO assignment for filter 8.

FFA[9]

Bit 9: Filter FIFO assignment for filter 9.

FFA[10]

Bit 10: Filter FIFO assignment for filter 10.

FFA[11]

Bit 11: Filter FIFO assignment for filter 11.

FFA[12]

Bit 12: Filter FIFO assignment for filter 12.

FFA[13]

Bit 13: Filter FIFO assignment for filter 13.

FFA[14]

Bit 14: Filter FIFO assignment for filter 14.

FFA[15]

Bit 15: Filter FIFO assignment for filter 15.

FFA[16]

Bit 16: Filter FIFO assignment for filter 16.

FFA[17]

Bit 17: Filter FIFO assignment for filter 17.

FFA[18]

Bit 18: Filter FIFO assignment for filter 18.

FFA[19]

Bit 19: Filter FIFO assignment for filter 19.

FFA[20]

Bit 20: Filter FIFO assignment for filter 20.

FFA[21]

Bit 21: Filter FIFO assignment for filter 21.

FFA[22]

Bit 22: Filter FIFO assignment for filter 22.

FFA[23]

Bit 23: Filter FIFO assignment for filter 23.

FFA[24]

Bit 24: Filter FIFO assignment for filter 24.

FFA[25]

Bit 25: Filter FIFO assignment for filter 25.

FFA[26]

Bit 26: Filter FIFO assignment for filter 26.

FFA[27]

Bit 27: Filter FIFO assignment for filter 27.

FA1R

CAN filter activation register

Offset: 0x21c, size: 32, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FACT[27]
rw 		FACT[26]
rw 		FACT[25]
rw 		FACT[24]
rw 		FACT[23]
rw 		FACT[22]
rw 		FACT[21]
rw 		FACT[20]
rw 		FACT[19]
rw 		FACT[18]
rw 		FACT[17]
rw 		FACT[16]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FACT[15]
rw 		FACT[14]
rw 		FACT[13]
rw 		FACT[12]
rw 		FACT[11]
rw 		FACT[10]
rw 		FACT[9]
rw 		FACT[8]
rw 		FACT[7]
rw 		FACT[6]
rw 		FACT[5]
rw 		FACT[4]
rw 		FACT[3]
rw 		FACT[2]
rw 		FACT[1]
rw 		FACT[0]
rw
Toggle fields

FACT[0]

Bit 0: Filter active.

FACT[1]

Bit 1: Filter active.

FACT[2]

Bit 2: Filter active.

FACT[3]

Bit 3: Filter active.

FACT[4]

Bit 4: Filter active.

FACT[5]

Bit 5: Filter active.

FACT[6]

Bit 6: Filter active.

FACT[7]

Bit 7: Filter active.

FACT[8]

Bit 8: Filter active.

FACT[9]

Bit 9: Filter active.

FACT[10]

Bit 10: Filter active.

FACT[11]

Bit 11: Filter active.

FACT[12]

Bit 12: Filter active.

FACT[13]

Bit 13: Filter active.

FACT[14]

Bit 14: Filter active.

FACT[15]

Bit 15: Filter active.

FACT[16]

Bit 16: Filter active.

FACT[17]

Bit 17: Filter active.

FACT[18]

Bit 18: Filter active.

FACT[19]

Bit 19: Filter active.

FACT[20]

Bit 20: Filter active.

FACT[21]

Bit 21: Filter active.

FACT[22]

Bit 22: Filter active.

FACT[23]

Bit 23: Filter active.

FACT[24]

Bit 24: Filter active.

FACT[25]

Bit 25: Filter active.

FACT[26]

Bit 26: Filter active.

FACT[27]

Bit 27: Filter active.

FR1 [0]

Filter bank x register 1

Offset: 0x240, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [0]

Filter bank x register 2

Offset: 0x244, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [1]

Filter bank x register 1

Offset: 0x248, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [1]

Filter bank x register 2

Offset: 0x24c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [2]

Filter bank x register 1

Offset: 0x250, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [2]

Filter bank x register 2

Offset: 0x254, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [3]

Filter bank x register 1

Offset: 0x258, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [3]

Filter bank x register 2

Offset: 0x25c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [4]

Filter bank x register 1

Offset: 0x260, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [4]

Filter bank x register 2

Offset: 0x264, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [5]

Filter bank x register 1

Offset: 0x268, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [5]

Filter bank x register 2

Offset: 0x26c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [6]

Filter bank x register 1

Offset: 0x270, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [6]

Filter bank x register 2

Offset: 0x274, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [7]

Filter bank x register 1

Offset: 0x278, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [7]

Filter bank x register 2

Offset: 0x27c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [8]

Filter bank x register 1

Offset: 0x280, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [8]

Filter bank x register 2

Offset: 0x284, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [9]

Filter bank x register 1

Offset: 0x288, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [9]

Filter bank x register 2

Offset: 0x28c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [10]

Filter bank x register 1

Offset: 0x290, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [10]

Filter bank x register 2

Offset: 0x294, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [11]

Filter bank x register 1

Offset: 0x298, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [11]

Filter bank x register 2

Offset: 0x29c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [12]

Filter bank x register 1

Offset: 0x2a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [12]

Filter bank x register 2

Offset: 0x2a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [13]

Filter bank x register 1

Offset: 0x2a8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [13]

Filter bank x register 2

Offset: 0x2ac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [14]

Filter bank x register 1

Offset: 0x2b0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [14]

Filter bank x register 2

Offset: 0x2b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [15]

Filter bank x register 1

Offset: 0x2b8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [15]

Filter bank x register 2

Offset: 0x2bc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [16]

Filter bank x register 1

Offset: 0x2c0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [16]

Filter bank x register 2

Offset: 0x2c4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [17]

Filter bank x register 1

Offset: 0x2c8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [17]

Filter bank x register 2

Offset: 0x2cc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [18]

Filter bank x register 1

Offset: 0x2d0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [18]

Filter bank x register 2

Offset: 0x2d4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [19]

Filter bank x register 1

Offset: 0x2d8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [19]

Filter bank x register 2

Offset: 0x2dc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [20]

Filter bank x register 1

Offset: 0x2e0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [20]

Filter bank x register 2

Offset: 0x2e4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [21]

Filter bank x register 1

Offset: 0x2e8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [21]

Filter bank x register 2

Offset: 0x2ec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [22]

Filter bank x register 1

Offset: 0x2f0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [22]

Filter bank x register 2

Offset: 0x2f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [23]

Filter bank x register 1

Offset: 0x2f8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [23]

Filter bank x register 2

Offset: 0x2fc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [24]

Filter bank x register 1

Offset: 0x300, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [24]

Filter bank x register 2

Offset: 0x304, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [25]

Filter bank x register 1

Offset: 0x308, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [25]

Filter bank x register 2

Offset: 0x30c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [26]

Filter bank x register 1

Offset: 0x310, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [26]

Filter bank x register 2

Offset: 0x314, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [27]

Filter bank x register 1

Offset: 0x318, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [27]

Filter bank x register 2

Offset: 0x31c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

COMP

0x40010000: General purpose comparators

21/24 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x20 COMP2_CSR
0x28 COMP4_CSR
0x30 COMP6_CSR
Toggle registers

COMP2_CSR

control and status register

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

7/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COMP2LOCK
rw 		COMP2OUT
r 		COMP2INMSEL3
rw 		COMP2_BLANKING
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP2POL
rw 		COMP2OUTSEL
rw 		COMP2INMSEL
rw 		COMP2EN
rw
Toggle fields

COMP2EN

Bit 0: Comparator 2 enable.

Allowed values:
0: Disabled: Comparator disabled
1: Enabled: Comparator enabled

COMP2INMSEL

Bits 4-6: Comparator 2 inverting input selection.

Allowed values:
0: OneQuarterVRef: 1/4 of VRefint
1: OneHalfVRef: 1/2 of VRefint
2: ThreeQuarterVRef: 3/4 of VRefint
3: VRef: VRefint
4: PA4_DAC1_CH1: PA4 or DAC1_CH1 output if enabled
5: DAC1_CH2: DAC1_CH2
6: PA2: PA2

COMP2OUTSEL

Bits 10-13: Comparator 2 output selection.

Allowed values:
0: NoSelection: No selection
1: Timer1BreakInput: Timer 1 break input
2: Timer1BreakInput2: Timer 1 break input 2
6: Timer1OCRefClearInput: Timer 1 OCREF_CLR input
7: Timer1InputCapture1: Timer 1 input capture 1
8: Timer2InputCapture4: Timer 2 input capture 4
9: Timer2OCRefClearInput: Timer 2 OCREF_CLR input
10: Timer3InputCapture1: Timer 3 input capture 1
11: Timer3OCRefClearInput: Timer 3 OCREF_CLR input

COMP2POL

Bit 15: Comparator 2 output polarity.

Allowed values:
0: NotInverted: Output is not inverted
1: Inverted: Output is inverted

COMP2_BLANKING

Bits 18-20: Comparator 2 blanking source.

Allowed values:
0: NoBlanking: No blanking
1: TIM1OC5: TIM1 OC5 selected as blanking source
2: TIM2OC3: TIM2 OC3 selected as blanking source
3: TIM3OC3: TIM3 OC3 selected as blanking source

COMP2INMSEL3

Bit 22: Comparator 2 inverting input selection.

COMP2OUT

Bit 30: Comparator 2 output.

Allowed values:
0: Low: Non-inverting input below inverting input
1: High: Non-inverting input above inverting input

COMP2LOCK

Bit 31: Comparator 2 lock.

Allowed values:
0: Unlocked: Comparator CSR bits are read-write
1: Locked: Comparator CSR bits are read-only

COMP4_CSR

control and status register

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

7/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COMP4LOCK
rw 		COMP4OUT
r 		COMP4INMSEL3
rw 		COMP4_BLANKING
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP4POL
rw 		COMP4OUTSEL
rw 		COMP4INMSEL
rw 		COMP4EN
rw
Toggle fields

COMP4EN

Bit 0: Comparator 4 enable.

Allowed values:
0: Disabled: Comparator disabled
1: Enabled: Comparator enabled

COMP4INMSEL

Bits 4-6: Comparator 4 inverting input selection.

Allowed values:
0: OneQuarterVRef: 1/4 of VRefint
1: OneHalfVRef: 1/2 of VRefint
2: ThreeQuarterVRef: 3/4 of VRefint
3: VRef: VRefint
4: PA4_DAC1_CH1: PA4 or DAC1_CH1 output if enabled
5: DAC1_CH2: DAC1_CH2
7: PB2: PB2

COMP4OUTSEL

Bits 10-13: Comparator 4 output selection.

Allowed values:
0: NoSelection: No selection
1: Timer1BreakInput: Timer 1 break input
2: Timer1BreakInput2: Timer 1 break input 2
6: Timer3InputCapture3: Timer 3 input capture 3
8: Timer15InputCapture2: Timer 15 input capture 2
10: Timer15OCRefClearInput: Timer 15 OCREF_CLR input
11: Timer3OCRefClearInput: Timer 3 OCREF_CLR input

COMP4POL

Bit 15: Comparator 4 output polarity.

Allowed values:
0: NotInverted: Output is not inverted
1: Inverted: Output is inverted

COMP4_BLANKING

Bits 18-20: Comparator 4 blanking source.

Allowed values:
0: NoBlanking: No blanking
1: TIM3OC4: TIM3 OC4 selected as blanking source
3: TIM15OC1: TIM15 OC1 selected as blanking source

COMP4INMSEL3

Bit 22: Comparator 4 inverting input selection.

COMP4OUT

Bit 30: Comparator 4 output.

Allowed values:
0: Low: Non-inverting input below inverting input
1: High: Non-inverting input above inverting input

COMP4LOCK

Bit 31: Comparator 4 lock.

Allowed values:
0: Unlocked: Comparator CSR bits are read-write
1: Locked: Comparator CSR bits are read-only

COMP6_CSR

control and status register

Offset: 0x30, size: 32, reset: 0x00000000, access: Unspecified

7/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COMP6LOCK
rw 		COMP6OUT
r 		COMP6INMSEL3
rw 		COMP6_BLANKING
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP6POL
rw 		COMP6OUTSEL
rw 		COMP6INMSEL
rw 		COMP6EN
rw
Toggle fields

COMP6EN

Bit 0: Comparator 6 enable.

Allowed values:
0: Disabled: Comparator disabled
1: Enabled: Comparator enabled

COMP6INMSEL

Bits 4-6: Comparator 6 inverting input selection.

Allowed values:
0: OneQuarterVRef: 1/4 of VRefint
1: OneHalfVRef: 1/2 of VRefint
2: ThreeQuarterVRef: 3/4 of VRefint
3: VRef: VRefint
4: PA4_DAC1_CH1: PA4 or DAC1_CH1 output if enabled
5: DAC1_CH2: DAC1_CH2
7: PB15: PB15

COMP6OUTSEL

Bits 10-13: Comparator 6 output selection.

Allowed values:
0: NoSelection: No selection
1: Timer1BreakInput: Timer 1 break input
2: Timer1BreakInput2: Timer 1 break input 2
6: Timer2InputCapture2: Timer 2 input capture 2
8: Timer2OCRefClearInput: Timer 2 OCREF_CLR input
9: Timer16OCRefClearInput: Timer 16 OCREF_CLR input
10: Timer16InputCapture1: Timer 16 input capture 1

COMP6POL

Bit 15: Comparator 6 output polarity.

Allowed values:
0: NotInverted: Output is not inverted
1: Inverted: Output is inverted

COMP6_BLANKING

Bits 18-20: Comparator 6 blanking source.

Allowed values:
0: NoBlanking: No blanking
3: TIM2OC4: TIM2 OC4 selected as blanking source
4: TIM15OC2: TIM15 OC2 selected as blanking source

COMP6INMSEL3

Bit 22: Comparator 6 inverting input selection.

COMP6OUT

Bit 30: Comparator 6 output.

Allowed values:
0: Low: Non-inverting input below inverting input
1: High: Non-inverting input above inverting input

COMP6LOCK

Bit 31: Comparator 6 lock.

Allowed values:
0: Unlocked: Comparator CSR bits are read-write
1: Locked: Comparator CSR bits are read-only

CRC

0x40023000: cyclic redundancy check calculation unit

10/10 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 DR
0x0 (16-bit) DR16
0x0 (8-bit) DR8
0x4 IDR
0x8 CR
0x10 INIT
0x14 POL
Toggle registers

DR

Data register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-31: Data register bits.

Allowed values: 0x0-0xffffffff

DR16

Data register - half-word sized

Offset: 0x0, size: 16, reset: 0x0000FFFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR16
rw
Toggle fields

DR16

Bits 0-15: Data register bits.

Allowed values: 0x0-0xffff

DR8

Data register - byte sized

Offset: 0x0, size: 8, reset: 0x000000FF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR8
rw
Toggle fields

DR8

Bits 0-7: Data register bits.

Allowed values: 0x0-0xff

IDR

Independent data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR
rw
Toggle fields

IDR

Bits 0-31: General-purpose 8-bit data register bits.

Allowed values: 0x0-0xffffffff

CR

Control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REV_OUT
rw 		REV_IN
rw 		POLYSIZE
rw 		RESET
rw
Toggle fields

RESET

Bit 0: reset bit.

Allowed values:
1: Reset: Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF

POLYSIZE

Bits 3-4: Polynomial size.

Allowed values:
0: Polysize32: 32-bit polynomial
1: Polysize16: 16-bit polynomial
2: Polysize8: 8-bit polynomial
3: Polysize7: 7-bit polynomial

REV_IN

Bits 5-6: Reverse input data.

Allowed values:
0: Normal: Bit order not affected
1: Byte: Bit reversal done by byte
2: HalfWord: Bit reversal done by half-word
3: Word: Bit reversal done by word

REV_OUT

Bit 7: Reverse output data.

Allowed values:
0: Normal: Bit order not affected
1: Reversed: Bit reversed output

INIT

Initial CRC value

Offset: 0x10, size: 32, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INIT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INIT
rw
Toggle fields

INIT

Bits 0-31: Programmable initial CRC value.

Allowed values: 0x0-0xffffffff

POL

CRC polynomial

Offset: 0x14, size: 32, reset: 0x04C11DB7, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
POL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POL
rw
Toggle fields

POL

Bits 0-31: Programmable polynomial.

Allowed values: 0x0-0xffffffff

DAC1

0x40007400: Digital-to-analog converter

34/34 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SWTRIGR
0x8 DHR12R1
0xc DHR12L1
0x10 DHR8R1
0x14 DHR12R2
0x18 DHR12L2
0x1c DHR8R2
0x20 DHR12RD
0x24 DHR12LD
0x28 DHR8RD
0x2c DOR1
0x30 DOR2
0x34 SR
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAUDRIE2
rw 		DMAEN2
rw 		MAMP2
rw 		WAVE2
rw 		TSEL2
rw 		TEN2
rw 		BOFF2
rw 		EN2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAUDRIE1
rw 		DMAEN1
rw 		MAMP1
rw 		WAVE1
rw 		TSEL1
rw 		TEN1
rw 		BOFF1
rw 		EN1
rw
Toggle fields

EN1

Bit 0: DAC channel1 enable.

Allowed values:
0: Disabled: DAC channel X disabled
1: Enabled: DAC channel X enabled

BOFF1

Bit 1: DAC channel1 output buffer disable.

Allowed values:
0: Enabled: DAC channel X output buffer enabled
1: Disabled: DAC channel X output buffer disabled

TEN1

Bit 2: DAC channel1 trigger enable.

Allowed values:
0: Disabled: DAC channel X trigger disabled
1: Enabled: DAC channel X trigger enabled

TSEL1

Bits 3-5: DAC channel1 trigger selection.

Allowed values:
0: TIM6_TRGO: Timer 6 TRGO event
1: TIM3_TRGO: Timer 3 TRGO event
2: TIM7_TRGO: Timer 7 TRGO event
3: TIM15_TRGO: Timer 15 TRGO event
4: TIM2_TRGO: Timer 2 TRGO event
6: EXTI9: EXTI line9
7: SOFTWARE: Software trigger

WAVE1

Bits 6-7: DAC channel1 noise/triangle wave generation enable.

Allowed values:
0: Disabled: Wave generation disabled
1: Noise: Noise wave generation enabled
2: Triangle: Triangle wave generation enabled

MAMP1

Bits 8-11: DAC channel1 mask/amplitude selector.

Allowed values: 0x0-0xf

DMAEN1

Bit 12: DAC channel1 DMA enable.

Allowed values:
0: Disabled: DAC channel X DMA mode disabled
1: Enabled: DAC channel X DMA mode enabled

DMAUDRIE1

Bit 13: DAC channel1 DMA Underrun Interrupt enable.

Allowed values:
0: Disabled: DAC channel X DMA Underrun Interrupt disabled
1: Enabled: DAC channel X DMA Underrun Interrupt enabled

EN2

Bit 16: DAC channel2 enable.

Allowed values:
0: Disabled: DAC channel X disabled
1: Enabled: DAC channel X enabled

BOFF2

Bit 17: DAC channel2 output buffer disable.

Allowed values:
0: Enabled: DAC channel X output buffer enabled
1: Disabled: DAC channel X output buffer disabled

TEN2

Bit 18: DAC channel2 trigger enable.

Allowed values:
0: Disabled: DAC channel X trigger disabled
1: Enabled: DAC channel X trigger enabled

TSEL2

Bits 19-21: DAC channel2 trigger selection.

Allowed values:
0: TIM6_TRGO: Timer 6 TRGO event
1: TIM8_TRGO: Timer 8 TRGO event
2: TIM7_TRGO: Timer 7 TRGO event
3: TIM5_TRGO: Timer 5 TRGO event
4: TIM2_TRGO: Timer 2 TRGO event
5: TIM4_TRGO: Timer 4 TRGO event
6: EXTI9: EXTI line9
7: SOFTWARE: Software trigger

WAVE2

Bits 22-23: DAC channel2 noise/triangle wave generation enable.

Allowed values:
0: Disabled: Wave generation disabled
1: Noise: Noise wave generation enabled
2: Triangle: Triangle wave generation enabled

MAMP2

Bits 24-27: DAC channel2 mask/amplitude selector.

Allowed values: 0x0-0xf

DMAEN2

Bit 28: DAC channel2 DMA enable.

Allowed values:
0: Disabled: DAC channel X DMA mode disabled
1: Enabled: DAC channel X DMA mode enabled

DMAUDRIE2

Bit 29: DAC channel2 DMA underrun interrupt enable.

Allowed values:
0: Disabled: DAC channel X DMA Underrun Interrupt disabled
1: Enabled: DAC channel X DMA Underrun Interrupt enabled

SWTRIGR

software trigger register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWTRIG2
w 		SWTRIG1
w
Toggle fields

SWTRIG1

Bit 0: DAC channel1 software trigger.

Allowed values:
0: Disabled: DAC channel X software trigger disabled
1: Enabled: DAC channel X software trigger enabled

SWTRIG2

Bit 1: DAC channel2 software trigger.

Allowed values:
0: Disabled: DAC channel X software trigger disabled
1: Enabled: DAC channel X software trigger enabled

DHR12R1

channel1 12-bit right-aligned data holding register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 0-11: DAC channel1 12-bit right-aligned data.

Allowed values: 0x0-0xfff

DHR12L1

channel1 12-bit left aligned data holding register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 4-15: DAC channel1 12-bit left-aligned data.

Allowed values: 0x0-0xfff

DHR8R1

channel1 8-bit right aligned data holding register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 0-7: DAC channel1 8-bit right-aligned data.

Allowed values: 0x0-0xff

DHR12R2

channel2 12-bit right aligned data holding register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
Toggle fields

DACC2DHR

Bits 0-11: DAC channel2 12-bit right-aligned data.

Allowed values: 0x0-0xfff

DHR12L2

channel2 12-bit left aligned data holding register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
Toggle fields

DACC2DHR

Bits 4-15: DAC channel2 12-bit left-aligned data.

Allowed values: 0x0-0xfff

DHR8R2

channel2 8-bit right-aligned data holding register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
Toggle fields

DACC2DHR

Bits 0-7: DAC channel2 8-bit right-aligned data.

Allowed values: 0x0-0xff

DHR12RD

Dual DAC 12-bit right-aligned data holding register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACC2DHR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 0-11: DAC channel1 12-bit right-aligned data.

Allowed values: 0x0-0xfff

DACC2DHR

Bits 16-27: DAC channel2 12-bit right-aligned data.

Allowed values: 0x0-0xfff

DHR12LD

DUAL DAC 12-bit left aligned data holding register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACC2DHR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 4-15: DAC channel1 12-bit left-aligned data.

Allowed values: 0x0-0xfff

DACC2DHR

Bits 20-31: DAC channel2 12-bit left-aligned data.

Allowed values: 0x0-0xfff

DHR8RD

DUAL DAC 8-bit right aligned data holding register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw 		DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 0-7: DAC channel1 8-bit right-aligned data.

Allowed values: 0x0-0xff

DACC2DHR

Bits 8-15: DAC channel2 8-bit right-aligned data.

Allowed values: 0x0-0xff

DOR1

channel1 data output register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DOR
r
Toggle fields

DACC1DOR

Bits 0-11: DAC channel1 data output.

DOR2

channel2 data output register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DOR
r
Toggle fields

DACC2DOR

Bits 0-11: DAC channel2 data output.

SR

status register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAUDR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAUDR1
rw
Toggle fields

DMAUDR1

Bit 13: DAC channel1 DMA underrun flag.

Allowed values:
0: NoUnderrun: No DMA underrun error condition occurred for DAC channel X
1: Underrun: DMA underrun error condition occurred for DAC channel X

DMAUDR2

Bit 29: DAC channel2 DMA underrun flag.

Allowed values:
0: NoUnderrun: No DMA underrun error condition occurred for DAC channel X
1: Underrun: DMA underrun error condition occurred for DAC channel X

DAC2

0x40009800: Digital-to-analog converter

34/34 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SWTRIGR
0x8 DHR12R1
0xc DHR12L1
0x10 DHR8R1
0x14 DHR12R2
0x18 DHR12L2
0x1c DHR8R2
0x20 DHR12RD
0x24 DHR12LD
0x28 DHR8RD
0x2c DOR1
0x30 DOR2
0x34 SR
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAUDRIE2
rw 		DMAEN2
rw 		MAMP2
rw 		WAVE2
rw 		TSEL2
rw 		TEN2
rw 		BOFF2
rw 		EN2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAUDRIE1
rw 		DMAEN1
rw 		MAMP1
rw 		WAVE1
rw 		TSEL1
rw 		TEN1
rw 		BOFF1
rw 		EN1
rw
Toggle fields

EN1

Bit 0: DAC channel1 enable.

Allowed values:
0: Disabled: DAC channel X disabled
1: Enabled: DAC channel X enabled

BOFF1

Bit 1: DAC channel1 output buffer disable.

Allowed values:
0: Enabled: DAC channel X output buffer enabled
1: Disabled: DAC channel X output buffer disabled

TEN1

Bit 2: DAC channel1 trigger enable.

Allowed values:
0: Disabled: DAC channel X trigger disabled
1: Enabled: DAC channel X trigger enabled

TSEL1

Bits 3-5: DAC channel1 trigger selection.

Allowed values:
0: TIM6_TRGO: Timer 6 TRGO event
1: TIM3_TRGO: Timer 3 TRGO event
2: TIM7_TRGO: Timer 7 TRGO event
3: TIM15_TRGO: Timer 15 TRGO event
4: TIM2_TRGO: Timer 2 TRGO event
6: EXTI9: EXTI line9
7: SOFTWARE: Software trigger

WAVE1

Bits 6-7: DAC channel1 noise/triangle wave generation enable.

Allowed values:
0: Disabled: Wave generation disabled
1: Noise: Noise wave generation enabled
2: Triangle: Triangle wave generation enabled

MAMP1

Bits 8-11: DAC channel1 mask/amplitude selector.

Allowed values: 0x0-0xf

DMAEN1

Bit 12: DAC channel1 DMA enable.

Allowed values:
0: Disabled: DAC channel X DMA mode disabled
1: Enabled: DAC channel X DMA mode enabled

DMAUDRIE1

Bit 13: DAC channel1 DMA Underrun Interrupt enable.

Allowed values:
0: Disabled: DAC channel X DMA Underrun Interrupt disabled
1: Enabled: DAC channel X DMA Underrun Interrupt enabled

EN2

Bit 16: DAC channel2 enable.

Allowed values:
0: Disabled: DAC channel X disabled
1: Enabled: DAC channel X enabled

BOFF2

Bit 17: DAC channel2 output buffer disable.

Allowed values:
0: Enabled: DAC channel X output buffer enabled
1: Disabled: DAC channel X output buffer disabled

TEN2

Bit 18: DAC channel2 trigger enable.

Allowed values:
0: Disabled: DAC channel X trigger disabled
1: Enabled: DAC channel X trigger enabled

TSEL2

Bits 19-21: DAC channel2 trigger selection.

Allowed values:
0: TIM6_TRGO: Timer 6 TRGO event
1: TIM8_TRGO: Timer 8 TRGO event
2: TIM7_TRGO: Timer 7 TRGO event
3: TIM5_TRGO: Timer 5 TRGO event
4: TIM2_TRGO: Timer 2 TRGO event
5: TIM4_TRGO: Timer 4 TRGO event
6: EXTI9: EXTI line9
7: SOFTWARE: Software trigger

WAVE2

Bits 22-23: DAC channel2 noise/triangle wave generation enable.

Allowed values:
0: Disabled: Wave generation disabled
1: Noise: Noise wave generation enabled
2: Triangle: Triangle wave generation enabled

MAMP2

Bits 24-27: DAC channel2 mask/amplitude selector.

Allowed values: 0x0-0xf

DMAEN2

Bit 28: DAC channel2 DMA enable.

Allowed values:
0: Disabled: DAC channel X DMA mode disabled
1: Enabled: DAC channel X DMA mode enabled

DMAUDRIE2

Bit 29: DAC channel2 DMA underrun interrupt enable.

Allowed values:
0: Disabled: DAC channel X DMA Underrun Interrupt disabled
1: Enabled: DAC channel X DMA Underrun Interrupt enabled

SWTRIGR

software trigger register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWTRIG2
w 		SWTRIG1
w
Toggle fields

SWTRIG1

Bit 0: DAC channel1 software trigger.

Allowed values:
0: Disabled: DAC channel X software trigger disabled
1: Enabled: DAC channel X software trigger enabled

SWTRIG2

Bit 1: DAC channel2 software trigger.

Allowed values:
0: Disabled: DAC channel X software trigger disabled
1: Enabled: DAC channel X software trigger enabled

DHR12R1

channel1 12-bit right-aligned data holding register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 0-11: DAC channel1 12-bit right-aligned data.

Allowed values: 0x0-0xfff

DHR12L1

channel1 12-bit left aligned data holding register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 4-15: DAC channel1 12-bit left-aligned data.

Allowed values: 0x0-0xfff

DHR8R1

channel1 8-bit right aligned data holding register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 0-7: DAC channel1 8-bit right-aligned data.

Allowed values: 0x0-0xff

DHR12R2

channel2 12-bit right aligned data holding register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
Toggle fields

DACC2DHR

Bits 0-11: DAC channel2 12-bit right-aligned data.

Allowed values: 0x0-0xfff

DHR12L2

channel2 12-bit left aligned data holding register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
Toggle fields

DACC2DHR

Bits 4-15: DAC channel2 12-bit left-aligned data.

Allowed values: 0x0-0xfff

DHR8R2

channel2 8-bit right-aligned data holding register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
Toggle fields

DACC2DHR

Bits 0-7: DAC channel2 8-bit right-aligned data.

Allowed values: 0x0-0xff

DHR12RD

Dual DAC 12-bit right-aligned data holding register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACC2DHR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 0-11: DAC channel1 12-bit right-aligned data.

Allowed values: 0x0-0xfff

DACC2DHR

Bits 16-27: DAC channel2 12-bit right-aligned data.

Allowed values: 0x0-0xfff

DHR12LD

DUAL DAC 12-bit left aligned data holding register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACC2DHR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 4-15: DAC channel1 12-bit left-aligned data.

Allowed values: 0x0-0xfff

DACC2DHR

Bits 20-31: DAC channel2 12-bit left-aligned data.

Allowed values: 0x0-0xfff

DHR8RD

DUAL DAC 8-bit right aligned data holding register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw 		DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 0-7: DAC channel1 8-bit right-aligned data.

Allowed values: 0x0-0xff

DACC2DHR

Bits 8-15: DAC channel2 8-bit right-aligned data.

Allowed values: 0x0-0xff

DOR1

channel1 data output register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DOR
r
Toggle fields

DACC1DOR

Bits 0-11: DAC channel1 data output.

DOR2

channel2 data output register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DOR
r
Toggle fields

DACC2DOR

Bits 0-11: DAC channel2 data output.

SR

status register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAUDR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAUDR1
rw
Toggle fields

DMAUDR1

Bit 13: DAC channel1 DMA underrun flag.

Allowed values:
0: NoUnderrun: No DMA underrun error condition occurred for DAC channel X
1: Underrun: DMA underrun error condition occurred for DAC channel X

DMAUDR2

Bit 29: DAC channel2 DMA underrun flag.

Allowed values:
0: NoUnderrun: No DMA underrun error condition occurred for DAC channel X
1: Underrun: DMA underrun error condition occurred for DAC channel X

DBGMCU

0xe0042000: Debug support

2/27 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 IDCODE
0x4 CR
0x8 APB1_FZ
0xc APB2_FZ
Toggle registers

IDCODE

MCU Device ID Code Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REV_ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEV_ID
r
Toggle fields

DEV_ID

Bits 0-11: Device Identifier.

REV_ID

Bits 16-31: Revision Identifier.

CR

Debug MCU Configuration Register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRACE_MODE
rw 		TRACE_IOEN
rw 		DBG_STANDBY
rw 		DBG_STOP
rw 		DBG_SLEEP
rw
Toggle fields

DBG_SLEEP

Bit 0: Debug Sleep mode.

DBG_STOP

Bit 1: Debug Stop Mode.

DBG_STANDBY

Bit 2: Debug Standby Mode.

TRACE_IOEN

Bit 5: Trace pin assignment control.

TRACE_MODE

Bits 6-7: Trace pin assignment control.

APB1_FZ

APB Low Freeze Register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBG_CAN_STOP
rw 		I2C2_SMBUS_TIMEOUT
rw 		I2C1_SMBUS_TIMEOUT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_IWDG_STOP
rw 		DBG_WWDG_STOP
rw 		DBG_RTC_STOP
rw 		DBG_TIM18_STOP
rw 		DBG_TIMER14_STOP
rw 		DBG_TIM13_STOP
rw 		DBG_TIM12_STOP
rw 		DBG_TIM7_STOP
rw 		DBG_TIM6_STOP
rw 		DBG_TIM5_STOP
rw 		DBG_TIM4_STOP
rw 		DBG_TIM3_STOP
rw 		DBG_TIM2_STOP
rw
Toggle fields

DBG_TIM2_STOP

Bit 0: Debug Timer 2 stopped when Core is halted.

DBG_TIM3_STOP

Bit 1: Debug Timer 3 stopped when Core is halted.

DBG_TIM4_STOP

Bit 2: Debug Timer 4 stopped when Core is halted.

DBG_TIM5_STOP

Bit 3: Debug Timer 5 stopped when Core is halted.

DBG_TIM6_STOP

Bit 4: Debug Timer 6 stopped when Core is halted.

DBG_TIM7_STOP

Bit 5: Debug Timer 7 stopped when Core is halted.

DBG_TIM12_STOP

Bit 6: Debug Timer 12 stopped when Core is halted.

DBG_TIM13_STOP

Bit 7: Debug Timer 13 stopped when Core is halted.

DBG_TIMER14_STOP

Bit 8: Debug Timer 14 stopped when Core is halted.

DBG_TIM18_STOP

Bit 9: Debug Timer 18 stopped when Core is halted.

DBG_RTC_STOP

Bit 10: Debug RTC stopped when Core is halted.

DBG_WWDG_STOP

Bit 11: Debug Window Wachdog stopped when Core is halted.

DBG_IWDG_STOP

Bit 12: Debug Independent Wachdog stopped when Core is halted.

I2C1_SMBUS_TIMEOUT

Bit 21: SMBUS timeout mode stopped when Core is halted.

I2C2_SMBUS_TIMEOUT

Bit 22: SMBUS timeout mode stopped when Core is halted.

DBG_CAN_STOP

Bit 25: Debug CAN stopped when core is halted.

APB2_FZ

APB High Freeze Register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_TIM19_STOP
rw 		DBG_TIM17_STO
rw 		DBG_TIM16_STOP
rw 		DBG_TIM15_STOP
rw
Toggle fields

DBG_TIM15_STOP

Bit 2: Debug Timer 15 stopped when Core is halted.

DBG_TIM16_STOP

Bit 3: Debug Timer 16 stopped when Core is halted.

DBG_TIM17_STO

Bit 4: Debug Timer 17 stopped when Core is halted.

DBG_TIM19_STOP

Bit 5: Debug Timer 19 stopped when Core is halted.

DMA1

0x40020000: DMA controller 1

147/161 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 IFCR
0x8 CR [1]
0xc NDTR [1]
0x10 PAR [1]
0x14 MAR [1]
0x1c CR [2]
0x20 NDTR [2]
0x24 PAR [2]
0x28 MAR [2]
0x30 CR [3]
0x34 NDTR [3]
0x38 PAR [3]
0x3c MAR [3]
0x44 CR [4]
0x48 NDTR [4]
0x4c PAR [4]
0x50 MAR [4]
0x58 CR [5]
0x5c NDTR [5]
0x60 PAR [5]
0x64 MAR [5]
0x6c CR [6]
0x70 NDTR [6]
0x74 PAR [6]
0x78 MAR [6]
0x80 CR [7]
0x84 NDTR [7]
0x88 PAR [7]
0x8c MAR [7]
Toggle registers

ISR

DMA interrupt status register (DMA_ISR)

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEIF[7]
r 		HTIF[7]
r 		TCIF[7]
r 		GIF[7]
r 		TEIF[6]
r 		HTIF[6]
r 		TCIF[6]
r 		GIF[6]
r 		TEIF[5]
r 		HTIF[5]
r 		TCIF[5]
r 		GIF[5]
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEIF[4]
r 		HTIF[4]
r 		TCIF[4]
r 		GIF[4]
r 		TEIF[3]
r 		HTIF[3]
r 		TCIF[3]
r 		GIF[3]
r 		TEIF[2]
r 		HTIF[2]
r 		TCIF[2]
r 		GIF[2]
r 		TEIF[1]
r 		HTIF[1]
r 		TCIF[1]
r 		GIF[1]
r
Toggle fields

GIF[1]

Bit 0: Channel 1 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[1]

Bit 1: Channel 1 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[1]

Bit 2: Channel 1 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[1]

Bit 3: Channel 1 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[2]

Bit 4: Channel 2 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[2]

Bit 5: Channel 2 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[2]

Bit 6: Channel 2 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[2]

Bit 7: Channel 2 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[3]

Bit 8: Channel 3 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[3]

Bit 9: Channel 3 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[3]

Bit 10: Channel 3 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[3]

Bit 11: Channel 3 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[4]

Bit 12: Channel 4 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[4]

Bit 13: Channel 4 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[4]

Bit 14: Channel 4 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[4]

Bit 15: Channel 4 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[5]

Bit 16: Channel 5 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[5]

Bit 17: Channel 5 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[5]

Bit 18: Channel 5 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[5]

Bit 19: Channel 5 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[6]

Bit 20: Channel 6 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[6]

Bit 21: Channel 6 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[6]

Bit 22: Channel 6 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[6]

Bit 23: Channel 6 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[7]

Bit 24: Channel 7 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[7]

Bit 25: Channel 7 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[7]

Bit 26: Channel 7 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[7]

Bit 27: Channel 7 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

IFCR

DMA interrupt flag clear register (DMA_IFCR)

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTEIF[7]
w 		CHTIF[7]
w 		CTCIF[7]
w 		CGIF[7]
w 		CTEIF[6]
w 		CHTIF[6]
w 		CTCIF[6]
w 		CGIF[6]
w 		CTEIF[5]
w 		CHTIF[5]
w 		CTCIF[5]
w 		CGIF[5]
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTEIF[4]
w 		CHTIF[4]
w 		CTCIF[4]
w 		CGIF[4]
w 		CTEIF[3]
w 		CHTIF[3]
w 		CTCIF[3]
w 		CGIF[3]
w 		CTEIF[2]
w 		CHTIF[2]
w 		CTCIF[2]
w 		CGIF[2]
w 		CTEIF[1]
w 		CHTIF[1]
w 		CTCIF[1]
w 		CGIF[1]
w
Toggle fields

CGIF[1]

Bit 0: Channel 1 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[1]

Bit 1: Channel 1 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[1]

Bit 2: Channel 1 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[1]

Bit 3: Channel 1 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[2]

Bit 4: Channel 2 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[2]

Bit 5: Channel 2 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[2]

Bit 6: Channel 2 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[2]

Bit 7: Channel 2 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[3]

Bit 8: Channel 3 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[3]

Bit 9: Channel 3 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[3]

Bit 10: Channel 3 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[3]

Bit 11: Channel 3 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[4]

Bit 12: Channel 4 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[4]

Bit 13: Channel 4 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[4]

Bit 14: Channel 4 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[4]

Bit 15: Channel 4 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[5]

Bit 16: Channel 5 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[5]

Bit 17: Channel 5 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[5]

Bit 18: Channel 5 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[5]

Bit 19: Channel 5 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[6]

Bit 20: Channel 6 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[6]

Bit 21: Channel 6 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[6]

Bit 22: Channel 6 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[6]

Bit 23: Channel 6 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[7]

Bit 24: Channel 7 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[7]

Bit 25: Channel 7 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[7]

Bit 26: Channel 7 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[7]

Bit 27: Channel 7 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CR [1]

DMA channel configuration register (DMA_CCR)

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half Transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [1]

DMA channel 1 number of data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [1]

DMA channel 1 peripheral address register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

MAR [1]

DMA channel 1 memory address register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CR [2]

DMA channel configuration register (DMA_CCR)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half Transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [2]

DMA channel 1 number of data register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [2]

DMA channel 1 peripheral address register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

MAR [2]

DMA channel 1 memory address register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CR [3]

DMA channel configuration register (DMA_CCR)

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half Transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [3]

DMA channel 1 number of data register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [3]

DMA channel 1 peripheral address register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

MAR [3]

DMA channel 1 memory address register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CR [4]

DMA channel configuration register (DMA_CCR)

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half Transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [4]

DMA channel 1 number of data register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [4]

DMA channel 1 peripheral address register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

MAR [4]

DMA channel 1 memory address register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CR [5]

DMA channel configuration register (DMA_CCR)

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half Transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [5]

DMA channel 1 number of data register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [5]

DMA channel 1 peripheral address register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

MAR [5]

DMA channel 1 memory address register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CR [6]

DMA channel configuration register (DMA_CCR)

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half Transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [6]

DMA channel 1 number of data register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [6]

DMA channel 1 peripheral address register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

MAR [6]

DMA channel 1 memory address register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CR [7]

DMA channel configuration register (DMA_CCR)

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half Transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [7]

DMA channel 1 number of data register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [7]

DMA channel 1 peripheral address register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

MAR [7]

DMA channel 1 memory address register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

EXTI

0x40010400: External interrupt/event controller

184/184 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 IMR1
0x4 EMR1
0x8 RTSR1
0xc FTSR1
0x10 SWIER1
0x14 PR1
0x20 IMR2
0x24 EMR2
0x28 RTSR2
0x2c FTSR2
0x30 SWIER2
0x34 PR2
Toggle registers

IMR1

Interrupt mask register

Offset: 0x0, size: 32, reset: 0x1F800000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MR31
rw 		MR30
rw 		MR29
rw 		MR28
rw 		MR27
rw 		MR26
rw 		MR25
rw 		MR24
rw 		MR23
rw 		MR22
rw 		MR21
rw 		MR20
rw 		MR19
rw 		MR18
rw 		MR17
rw 		MR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR15
rw 		MR14
rw 		MR13
rw 		MR12
rw 		MR11
rw 		MR10
rw 		MR9
rw 		MR8
rw 		MR7
rw 		MR6
rw 		MR5
rw 		MR4
rw 		MR3
rw 		MR2
rw 		MR1
rw 		MR0
rw
Toggle fields

MR0

Bit 0: Interrupt Mask on line 0.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR1

Bit 1: Interrupt Mask on line 1.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR2

Bit 2: Interrupt Mask on line 2.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR3

Bit 3: Interrupt Mask on line 3.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR4

Bit 4: Interrupt Mask on line 4.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR5

Bit 5: Interrupt Mask on line 5.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR6

Bit 6: Interrupt Mask on line 6.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR7

Bit 7: Interrupt Mask on line 7.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR8

Bit 8: Interrupt Mask on line 8.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR9

Bit 9: Interrupt Mask on line 9.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR10

Bit 10: Interrupt Mask on line 10.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR11

Bit 11: Interrupt Mask on line 11.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR12

Bit 12: Interrupt Mask on line 12.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR13

Bit 13: Interrupt Mask on line 13.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR14

Bit 14: Interrupt Mask on line 14.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR15

Bit 15: Interrupt Mask on line 15.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR16

Bit 16: Interrupt Mask on line 16.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR17

Bit 17: Interrupt Mask on line 17.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR18

Bit 18: Interrupt Mask on line 18.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR19

Bit 19: Interrupt Mask on line 19.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR20

Bit 20: Interrupt Mask on line 20.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR21

Bit 21: Interrupt Mask on line 21.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR22

Bit 22: Interrupt Mask on line 22.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR23

Bit 23: Interrupt Mask on line 23.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR24

Bit 24: Interrupt Mask on line 24.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR25

Bit 25: Interrupt Mask on line 25.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR26

Bit 26: Interrupt Mask on line 26.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR27

Bit 27: Interrupt Mask on line 27.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR28

Bit 28: Interrupt Mask on line 28.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR29

Bit 29: Interrupt Mask on line 29.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR30

Bit 30: Interrupt Mask on line 30.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR31

Bit 31: Interrupt Mask on line 31.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EMR1

Event mask register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MR31
rw 		MR30
rw 		MR29
rw 		MR28
rw 		MR27
rw 		MR26
rw 		MR25
rw 		MR24
rw 		MR23
rw 		MR22
rw 		MR21
rw 		MR20
rw 		MR19
rw 		MR18
rw 		MR17
rw 		MR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR15
rw 		MR14
rw 		MR13
rw 		MR12
rw 		MR11
rw 		MR10
rw 		MR9
rw 		MR8
rw 		MR7
rw 		MR6
rw 		MR5
rw 		MR4
rw 		MR3
rw 		MR2
rw 		MR1
rw 		MR0
rw
Toggle fields

MR0

Bit 0: Event Mask on line 0.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR1

Bit 1: Event Mask on line 1.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR2

Bit 2: Event Mask on line 2.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR3

Bit 3: Event Mask on line 3.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR4

Bit 4: Event Mask on line 4.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR5

Bit 5: Event Mask on line 5.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR6

Bit 6: Event Mask on line 6.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR7

Bit 7: Event Mask on line 7.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR8

Bit 8: Event Mask on line 8.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR9

Bit 9: Event Mask on line 9.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR10

Bit 10: Event Mask on line 10.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR11

Bit 11: Event Mask on line 11.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR12

Bit 12: Event Mask on line 12.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR13

Bit 13: Event Mask on line 13.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR14

Bit 14: Event Mask on line 14.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR15

Bit 15: Event Mask on line 15.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR16

Bit 16: Event Mask on line 16.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR17

Bit 17: Event Mask on line 17.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR18

Bit 18: Event Mask on line 18.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR19

Bit 19: Event Mask on line 19.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR20

Bit 20: Event Mask on line 20.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR21

Bit 21: Event Mask on line 21.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR22

Bit 22: Event Mask on line 22.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR23

Bit 23: Event Mask on line 23.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR24

Bit 24: Event Mask on line 24.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR25

Bit 25: Event Mask on line 25.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR26

Bit 26: Event Mask on line 26.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR27

Bit 27: Event Mask on line 27.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR28

Bit 28: Event Mask on line 28.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR29

Bit 29: Event Mask on line 29.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR30

Bit 30: Event Mask on line 30.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR31

Bit 31: Event Mask on line 31.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

RTSR1

Rising Trigger selection register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

26/26 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TR31
rw 		TR30
rw 		TR29
rw 		TR22
rw 		TR21
rw 		TR20
rw 		TR19
rw 		TR18
rw 		TR17
rw 		TR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TR15
rw 		TR14
rw 		TR13
rw 		TR12
rw 		TR11
rw 		TR10
rw 		TR9
rw 		TR8
rw 		TR7
rw 		TR6
rw 		TR5
rw 		TR4
rw 		TR3
rw 		TR2
rw 		TR1
rw 		TR0
rw
Toggle fields

TR0

Bit 0: Rising trigger event configuration of line 0.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR1

Bit 1: Rising trigger event configuration of line 1.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR2

Bit 2: Rising trigger event configuration of line 2.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR3

Bit 3: Rising trigger event configuration of line 3.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR4

Bit 4: Rising trigger event configuration of line 4.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR5

Bit 5: Rising trigger event configuration of line 5.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR6

Bit 6: Rising trigger event configuration of line 6.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR7

Bit 7: Rising trigger event configuration of line 7.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR8

Bit 8: Rising trigger event configuration of line 8.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR9

Bit 9: Rising trigger event configuration of line 9.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR10

Bit 10: Rising trigger event configuration of line 10.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR11

Bit 11: Rising trigger event configuration of line 11.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR12

Bit 12: Rising trigger event configuration of line 12.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR13

Bit 13: Rising trigger event configuration of line 13.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR14

Bit 14: Rising trigger event configuration of line 14.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR15

Bit 15: Rising trigger event configuration of line 15.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR16

Bit 16: Rising trigger event configuration of line 16.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR17

Bit 17: Rising trigger event configuration of line 17.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR18

Bit 18: Rising trigger event configuration of line 18.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR19

Bit 19: Rising trigger event configuration of line 19.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR20

Bit 20: Rising trigger event configuration of line 20.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR21

Bit 21: Rising trigger event configuration of line 21.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR22

Bit 22: Rising trigger event configuration of line 22.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR29

Bit 29: Rising trigger event configuration of line 29.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR30

Bit 30: Rising trigger event configuration of line 30.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR31

Bit 31: Rising trigger event configuration of line 31.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

FTSR1

Falling Trigger selection register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

26/26 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TR31
rw 		TR30
rw 		TR29
rw 		TR22
rw 		TR21
rw 		TR20
rw 		TR19
rw 		TR18
rw 		TR17
rw 		TR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TR15
rw 		TR14
rw 		TR13
rw 		TR12
rw 		TR11
rw 		TR10
rw 		TR9
rw 		TR8
rw 		TR7
rw 		TR6
rw 		TR5
rw 		TR4
rw 		TR3
rw 		TR2
rw 		TR1
rw 		TR0
rw
Toggle fields

TR0

Bit 0: Falling trigger event configuration of line 0.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR1

Bit 1: Falling trigger event configuration of line 1.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR2

Bit 2: Falling trigger event configuration of line 2.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR3

Bit 3: Falling trigger event configuration of line 3.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR4

Bit 4: Falling trigger event configuration of line 4.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR5

Bit 5: Falling trigger event configuration of line 5.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR6

Bit 6: Falling trigger event configuration of line 6.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR7

Bit 7: Falling trigger event configuration of line 7.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR8

Bit 8: Falling trigger event configuration of line 8.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR9

Bit 9: Falling trigger event configuration of line 9.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR10

Bit 10: Falling trigger event configuration of line 10.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR11

Bit 11: Falling trigger event configuration of line 11.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR12

Bit 12: Falling trigger event configuration of line 12.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR13

Bit 13: Falling trigger event configuration of line 13.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR14

Bit 14: Falling trigger event configuration of line 14.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR15

Bit 15: Falling trigger event configuration of line 15.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR16

Bit 16: Falling trigger event configuration of line 16.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR17

Bit 17: Falling trigger event configuration of line 17.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR18

Bit 18: Falling trigger event configuration of line 18.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR19

Bit 19: Falling trigger event configuration of line 19.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR20

Bit 20: Falling trigger event configuration of line 20.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR21

Bit 21: Falling trigger event configuration of line 21.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR22

Bit 22: Falling trigger event configuration of line 22.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR29

Bit 29: Falling trigger event configuration of line 29.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR30

Bit 30: Falling trigger event configuration of line 30..

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR31

Bit 31: Falling trigger event configuration of line 31.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

SWIER1

Software interrupt event register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

26/26 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWIER31
rw 		SWIER30
rw 		SWIER29
rw 		SWIER22
rw 		SWIER21
rw 		SWIER20
rw 		SWIER19
rw 		SWIER18
rw 		SWIER17
rw 		SWIER16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWIER15
rw 		SWIER14
rw 		SWIER13
rw 		SWIER12
rw 		SWIER11
rw 		SWIER10
rw 		SWIER9
rw 		SWIER8
rw 		SWIER7
rw 		SWIER6
rw 		SWIER5
rw 		SWIER4
rw 		SWIER3
rw 		SWIER2
rw 		SWIER1
rw 		SWIER0
rw
Toggle fields

SWIER0

Bit 0: Software Interrupt on line 0.

Allowed values:
1: Pend: Generates an interrupt request

SWIER1

Bit 1: Software Interrupt on line 1.

Allowed values:
1: Pend: Generates an interrupt request

SWIER2

Bit 2: Software Interrupt on line 2.

Allowed values:
1: Pend: Generates an interrupt request

SWIER3

Bit 3: Software Interrupt on line 3.

Allowed values:
1: Pend: Generates an interrupt request

SWIER4

Bit 4: Software Interrupt on line 4.

Allowed values:
1: Pend: Generates an interrupt request

SWIER5

Bit 5: Software Interrupt on line 5.

Allowed values:
1: Pend: Generates an interrupt request

SWIER6

Bit 6: Software Interrupt on line 6.

Allowed values:
1: Pend: Generates an interrupt request

SWIER7

Bit 7: Software Interrupt on line 7.

Allowed values:
1: Pend: Generates an interrupt request

SWIER8

Bit 8: Software Interrupt on line 8.

Allowed values:
1: Pend: Generates an interrupt request

SWIER9

Bit 9: Software Interrupt on line 9.

Allowed values:
1: Pend: Generates an interrupt request

SWIER10

Bit 10: Software Interrupt on line 10.

Allowed values:
1: Pend: Generates an interrupt request

SWIER11

Bit 11: Software Interrupt on line 11.

Allowed values:
1: Pend: Generates an interrupt request

SWIER12

Bit 12: Software Interrupt on line 12.

Allowed values:
1: Pend: Generates an interrupt request

SWIER13

Bit 13: Software Interrupt on line 13.

Allowed values:
1: Pend: Generates an interrupt request

SWIER14

Bit 14: Software Interrupt on line 14.

Allowed values:
1: Pend: Generates an interrupt request

SWIER15

Bit 15: Software Interrupt on line 15.

Allowed values:
1: Pend: Generates an interrupt request

SWIER16

Bit 16: Software Interrupt on line 16.

Allowed values:
1: Pend: Generates an interrupt request

SWIER17

Bit 17: Software Interrupt on line 17.

Allowed values:
1: Pend: Generates an interrupt request

SWIER18

Bit 18: Software Interrupt on line 18.

Allowed values:
1: Pend: Generates an interrupt request

SWIER19

Bit 19: Software Interrupt on line 19.

Allowed values:
1: Pend: Generates an interrupt request

SWIER20

Bit 20: Software Interrupt on line 20.

Allowed values:
1: Pend: Generates an interrupt request

SWIER21

Bit 21: Software Interrupt on line 21.

Allowed values:
1: Pend: Generates an interrupt request

SWIER22

Bit 22: Software Interrupt on line 22.

Allowed values:
1: Pend: Generates an interrupt request

SWIER29

Bit 29: Software Interrupt on line 29.

Allowed values:
1: Pend: Generates an interrupt request

SWIER30

Bit 30: Software Interrupt on line 309.

Allowed values:
1: Pend: Generates an interrupt request

SWIER31

Bit 31: Software Interrupt on line 319.

Allowed values:
1: Pend: Generates an interrupt request

PR1

Pending register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

26/26 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PR31
rw 		PR30
rw 		PR29
rw 		PR22
rw 		PR21
rw 		PR20
rw 		PR19
rw 		PR18
rw 		PR17
rw 		PR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PR15
rw 		PR14
rw 		PR13
rw 		PR12
rw 		PR11
rw 		PR10
rw 		PR9
rw 		PR8
rw 		PR7
rw 		PR6
rw 		PR5
rw 		PR4
rw 		PR3
rw 		PR2
rw 		PR1
rw 		PR0
rw
Toggle fields

PR0

Bit 0: Pending bit 0.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR1

Bit 1: Pending bit 1.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR2

Bit 2: Pending bit 2.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR3

Bit 3: Pending bit 3.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR4

Bit 4: Pending bit 4.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR5

Bit 5: Pending bit 5.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR6

Bit 6: Pending bit 6.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR7

Bit 7: Pending bit 7.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR8

Bit 8: Pending bit 8.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR9

Bit 9: Pending bit 9.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR10

Bit 10: Pending bit 10.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR11

Bit 11: Pending bit 11.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR12

Bit 12: Pending bit 12.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR13

Bit 13: Pending bit 13.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR14

Bit 14: Pending bit 14.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR15

Bit 15: Pending bit 15.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR16

Bit 16: Pending bit 16.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR17

Bit 17: Pending bit 17.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR18

Bit 18: Pending bit 18.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR19

Bit 19: Pending bit 19.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR20

Bit 20: Pending bit 20.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR21

Bit 21: Pending bit 21.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR22

Bit 22: Pending bit 22.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR29

Bit 29: Pending bit 29.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR30

Bit 30: Pending bit 30.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR31

Bit 31: Pending bit 31.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

IMR2

Interrupt mask register

Offset: 0x20, size: 32, reset: 0xFFFFFFFC, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR35
rw 		MR34
rw 		MR33
rw 		MR32
rw
Toggle fields

MR32

Bit 0: Interrupt Mask on external/internal line 32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR33

Bit 1: Interrupt Mask on external/internal line 33.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR34

Bit 2: Interrupt Mask on external/internal line 34.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR35

Bit 3: Interrupt Mask on external/internal line 35.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EMR2

Event mask register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR35
rw 		MR34
rw 		MR33
rw 		MR32
rw
Toggle fields

MR32

Bit 0: Event mask on external/internal line 32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR33

Bit 1: Event mask on external/internal line 33.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR34

Bit 2: Event mask on external/internal line 34.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR35

Bit 3: Event mask on external/internal line 35.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

RTSR2

Rising Trigger selection register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TR33
rw 		TR32
rw
Toggle fields

TR32

Bit 0: Rising trigger event configuration bit of line 32.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR33

Bit 1: Rising trigger event configuration bit of line 33.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

FTSR2

Falling Trigger selection register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TR33
rw 		TR32
rw
Toggle fields

TR32

Bit 0: Falling trigger event configuration bit of line 32.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR33

Bit 1: Falling trigger event configuration bit of line 33.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

SWIER2

Software interrupt event register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWIER33
rw 		SWIER32
rw
Toggle fields

SWIER32

Bit 0: Software interrupt on line 32.

Allowed values:
1: Pend: Generates an interrupt request

SWIER33

Bit 1: Software interrupt on line 33.

Allowed values:
1: Pend: Generates an interrupt request

PR2

Pending register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PR33
rw 		PR32
rw
Toggle fields

PR32

Bit 0: Pending bit on line 32.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR33

Bit 1: Pending bit on line 33.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

FLASH

0x40022000: Flash

33/33 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ACR
0x4 KEYR
0x8 OPTKEYR
0xc SR
0x10 CR
0x14 AR
0x1c OBR
0x20 WRPR
Toggle registers

ACR

Flash access control register

Offset: 0x0, size: 32, reset: 0x00000030, access: Unspecified

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRFTBS
r 		PRFTBE
rw 		HLFCYA
rw 		LATENCY
rw
Toggle fields

LATENCY

Bits 0-2: LATENCY.

Allowed values:
0: WS0: 0 wait states, if 0 < HCLK <= 24 MHz
1: WS1: 1 wait state, if 24 < HCLK <= 48 MHz
2: WS2: 2 wait states, if 48 < HCLK <= 72 MHz

HLFCYA

Bit 3: Flash half cycle access enable.

Allowed values:
0: Disabled: Half cycle is disabled
1: Enabled: Half cycle is enabled

PRFTBE

Bit 4: PRFTBE.

Allowed values:
0: Disabled: Prefetch is disabled
1: Enabled: Prefetch is enabled

PRFTBS

Bit 5: PRFTBS.

Allowed values:
0: Disabled: Prefetch buffer is disabled
1: Enabled: Prefetch buffer is enabled

KEYR

Flash key register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FKEYR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FKEYR
w
Toggle fields

FKEYR

Bits 0-31: Flash Key.

Allowed values: 0x0-0xffffffff

OPTKEYR

Flash option key register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPTKEYR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPTKEYR
w
Toggle fields

OPTKEYR

Bits 0-31: Option byte key.

Allowed values: 0x0-0xffffffff

SR

Flash status register

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOP
rw 		WRPRTERR
rw 		PGERR
rw 		BSY
r
Toggle fields

BSY

Bit 0: Busy.

Allowed values:
0: Inactive: No write/erase operation is in progress
1: Active: No write/erase operation is in progress

PGERR

Bit 2: Programming error.

Allowed values:
0: NoError: No programming error occurred
1: Error: A programming error occurred

WRPRTERR

Bit 4: Write protection error.

Allowed values:
0: NoError: No write protection error occurred
1: Error: A write protection error occurred

EOP

Bit 5: End of operation.

Allowed values:
0: NoEvent: No EOP event occurred
1: Event: An EOP event occurred

CR

Flash control register

Offset: 0x10, size: 32, reset: 0x00000080, access: read-write

11/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OBL_LAUNCH
rw 		EOPIE
rw 		ERRIE
rw 		OPTWRE
rw 		LOCK
rw 		STRT
rw 		OPTER
rw 		OPTPG
rw 		MER
rw 		PER
rw 		PG
rw
Toggle fields

PG

Bit 0: Programming.

Allowed values:
1: Program: Flash programming activated

PER

Bit 1: Page erase.

Allowed values:
1: PageErase: Erase activated for selected page

MER

Bit 2: Mass erase.

Allowed values:
1: MassErase: Erase activated for all user sectors

OPTPG

Bit 4: Option byte programming.

Allowed values:
1: OptionByteProgramming: Program option byte activated

OPTER

Bit 5: Option byte erase.

Allowed values:
1: OptionByteErase: Erase option byte activated

STRT

Bit 6: Start.

Allowed values:
1: Start: Trigger an erase operation

LOCK

Bit 7: Lock.

Allowed values:
0: Unlocked: FLASH_CR register is unlocked
1: Locked: FLASH_CR register is locked

OPTWRE

Bit 9: Option bytes write enable.

Allowed values:
0: Disabled: Option byte write enabled
1: Enabled: Option byte write disabled

ERRIE

Bit 10: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt generation disabled
1: Enabled: Error interrupt generation enabled

EOPIE

Bit 12: End of operation interrupt enable.

Allowed values:
0: Disabled: End of operation interrupt disabled
1: Enabled: End of operation interrupt enabled

OBL_LAUNCH

Bit 13: Force option byte loading.

Allowed values:
0: Inactive: Force option byte loading inactive
1: Active: Force option byte loading active

AR

Flash address register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FAR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FAR
w
Toggle fields

FAR

Bits 0-31: Flash address.

Allowed values: 0x0-0xffffffff

OBR

Option byte register

Offset: 0x1c, size: 32, reset: 0xFFFFFF0F, access: read-only

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Data1
r 		Data0
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRAM_PARITY_CHECK
r 		VDDA_MONITOR
r 		nBOOT1
r 		nRST_STDBY
r 		nRST_STOP
r 		WDG_SW
r 		RDPRT
r 		OPTERR
r
Toggle fields

OPTERR

Bit 0: Option byte error.

Allowed values:
1: OptionByteError: The loaded option byte and its complement do not match

RDPRT

Bits 1-2: Read protection Level status.

Allowed values:
0: Level0: Level 0
1: Level1: Level 1
3: Level2: Level 2

WDG_SW

Bit 8: WDG_SW.

Allowed values:
0: Hardware: Hardware watchdog
1: Software: Software watchdog

nRST_STOP

Bit 9: nRST_STOP.

Allowed values:
0: Reset: Reset generated when entering Stop mode
1: NoReset: No reset generated

nRST_STDBY

Bit 10: nRST_STDBY.

Allowed values:
0: Reset: Reset generated when entering Standby mode
1: NoReset: No reset generated

nBOOT1

Bit 12: BOOT1.

Allowed values:
0: Disabled: Together with BOOT0, select the device boot mode
1: Enabled: Together with BOOT0, select the device boot mode

VDDA_MONITOR

Bit 13: VDDA_MONITOR.

Allowed values:
0: Disabled: VDDA power supply supervisor disabled
1: Enabled: VDDA power supply supervisor enabled

SRAM_PARITY_CHECK

Bit 14: SRAM_PARITY_CHECK.

Data0

Bits 16-23: Data0.

Allowed values: 0x0-0xff

Data1

Bits 24-31: Data1.

Allowed values: 0x0-0xff

WRPR

Write protection register

Offset: 0x20, size: 32, reset: 0xFFFFFFFF, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRP
r
Toggle fields

WRP

Bits 0-31: Write protect.

Allowed values: 0x0-0xffffffff

FPU

0xe000ef34: Floting point unit

0/24 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 FPCCR
0x4 FPCAR
0x8 FPSCR
Toggle registers

FPCCR

Floating-point context control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ASPEN
rw 		LSPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MONRDY
rw 		BFRDY
rw 		MMRDY
rw 		HFRDY
rw 		THREAD
rw 		USER
rw 		LSPACT
rw
Toggle fields

LSPACT

Bit 0: LSPACT.

USER

Bit 1: USER.

THREAD

Bit 3: THREAD.

HFRDY

Bit 4: HFRDY.

MMRDY

Bit 5: MMRDY.

BFRDY

Bit 6: BFRDY.

MONRDY

Bit 8: MONRDY.

LSPEN

Bit 30: LSPEN.

ASPEN

Bit 31: ASPEN.

FPCAR

Floating-point context address register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDRESS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRESS
rw
Toggle fields

ADDRESS

Bits 3-31: Location of unpopulated floating-point.

FPSCR

Floating-point status control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
N
rw 		Z
rw 		C
rw 		V
rw 		AHP
rw 		DN
rw 		FZ
rw 		RMode
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDC
rw 		IXC
rw 		UFC
rw 		OFC
rw 		DZC
rw 		IOC
rw
Toggle fields

IOC

Bit 0: Invalid operation cumulative exception bit.

DZC

Bit 1: Division by zero cumulative exception bit..

OFC

Bit 2: Overflow cumulative exception bit.

UFC

Bit 3: Underflow cumulative exception bit.

IXC

Bit 4: Inexact cumulative exception bit.

IDC

Bit 7: Input denormal cumulative exception bit..

RMode

Bits 22-23: Rounding Mode control field.

FZ

Bit 24: Flush-to-zero mode control bit:.

DN

Bit 25: Default NaN mode control bit.

AHP

Bit 26: Alternative half-precision control bit.

V

Bit 28: Overflow condition code flag.

C

Bit 29: Carry condition code flag.

Z

Bit 30: Zero condition code flag.

N

Bit 31: Negative condition code flag.

FPU_CPACR

0xe000ed88: Floating point unit CPACR

0/1 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CPACR
Toggle registers

CPACR

Coprocessor access control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

CP

Bits 20-23: CP.

GPIOA

0x48000000: General-purpose I/Os

177/177 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xA8000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw 		MODER[14]
rw 		MODER[13]
rw 		MODER[12]
rw 		MODER[11]
rw 		MODER[10]
rw 		MODER[9]
rw 		MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw 		MODER[6]
rw 		MODER[5]
rw 		MODER[4]
rw 		MODER[3]
rw 		MODER[2]
rw 		MODER[1]
rw 		MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT[15]
rw 		OT[14]
rw 		OT[13]
rw 		OT[12]
rw 		OT[11]
rw 		OT[10]
rw 		OT[9]
rw 		OT[8]
rw 		OT[7]
rw 		OT[6]
rw 		OT[5]
rw 		OT[4]
rw 		OT[3]
rw 		OT[2]
rw 		OT[1]
rw 		OT[0]
rw
Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0xC0000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR[15]
rw 		OSPEEDR[14]
rw 		OSPEEDR[13]
rw 		OSPEEDR[12]
rw 		OSPEEDR[11]
rw 		OSPEEDR[10]
rw 		OSPEEDR[9]
rw 		OSPEEDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR[7]
rw 		OSPEEDR[6]
rw 		OSPEEDR[5]
rw 		OSPEEDR[4]
rw 		OSPEEDR[3]
rw 		OSPEEDR[2]
rw 		OSPEEDR[1]
rw 		OSPEEDR[0]
rw
Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x64000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw 		PUPDR[14]
rw 		PUPDR[13]
rw 		PUPDR[12]
rw 		PUPDR[11]
rw 		PUPDR[10]
rw 		PUPDR[9]
rw 		PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw 		PUPDR[6]
rw 		PUPDR[5]
rw 		PUPDR[4]
rw 		PUPDR[3]
rw 		PUPDR[2]
rw 		PUPDR[1]
rw 		PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR[15]
r 		IDR[14]
r 		IDR[13]
r 		IDR[12]
r 		IDR[11]
r 		IDR[10]
r 		IDR[9]
r 		IDR[8]
r 		IDR[7]
r 		IDR[6]
r 		IDR[5]
r 		IDR[4]
r 		IDR[3]
r 		IDR[2]
r 		IDR[1]
r 		IDR[0]
r
Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR[15]
rw 		ODR[14]
rw 		ODR[13]
rw 		ODR[12]
rw 		ODR[11]
rw 		ODR[10]
rw 		ODR[9]
rw 		ODR[8]
rw 		ODR[7]
rw 		ODR[6]
rw 		ODR[5]
rw 		ODR[4]
rw 		ODR[3]
rw 		ODR[2]
rw 		ODR[1]
rw 		ODR[0]
rw
Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR[15]
w 		BR[14]
w 		BR[13]
w 		BR[12]
w 		BR[11]
w 		BR[10]
w 		BR[9]
w 		BR[8]
w 		BR[7]
w 		BR[6]
w 		BR[5]
w 		BR[4]
w 		BR[3]
w 		BR[2]
w 		BR[1]
w 		BR[0]
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS[15]
w 		BS[14]
w 		BS[13]
w 		BS[12]
w 		BS[11]
w 		BS[10]
w 		BS[9]
w 		BS[8]
w 		BS[7]
w 		BS[6]
w 		BS[5]
w 		BS[4]
w 		BS[3]
w 		BS[2]
w 		BS[1]
w 		BS[0]
w
Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw 		LCK[14]
rw 		LCK[13]
rw 		LCK[12]
rw 		LCK[11]
rw 		LCK[10]
rw 		LCK[9]
rw 		LCK[8]
rw 		LCK[7]
rw 		LCK[6]
rw 		LCK[5]
rw 		LCK[4]
rw 		LCK[3]
rw 		LCK[2]
rw 		LCK[1]
rw 		LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Lok Key.

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[L7]
rw 		AFR[L6]
rw 		AFR[L5]
rw 		AFR[L4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[L3]
rw 		AFR[L2]
rw 		AFR[L1]
rw 		AFR[L0]
rw
Toggle fields

AFR[L0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[H15]
rw 		AFR[H14]
rw 		AFR[H13]
rw 		AFR[H12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[H11]
rw 		AFR[H10]
rw 		AFR[H9]
rw 		AFR[H8]
rw
Toggle fields

AFR[H8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

Port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR[15]
w 		BR[14]
w 		BR[13]
w 		BR[12]
w 		BR[11]
w 		BR[10]
w 		BR[9]
w 		BR[8]
w 		BR[7]
w 		BR[6]
w 		BR[5]
w 		BR[4]
w 		BR[3]
w 		BR[2]
w 		BR[1]
w 		BR[0]
w
Toggle fields

BR[0]

Bit 0: Port x reset pin 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Port x reset pin 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Port x reset pin 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Port x reset pin 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Port x reset pin 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Port x reset pin 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Port x reset pin 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Port x reset pin 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Port x reset pin 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Port x reset pin 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Port x reset pin 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Port x reset pin 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Port x reset pin 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Port x reset pin 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Port x reset pin 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Port x reset pin 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

GPIOB

0x48000400: General-purpose I/Os

177/177 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0x00000280, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw 		MODER[14]
rw 		MODER[13]
rw 		MODER[12]
rw 		MODER[11]
rw 		MODER[10]
rw 		MODER[9]
rw 		MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw 		MODER[6]
rw 		MODER[5]
rw 		MODER[4]
rw 		MODER[3]
rw 		MODER[2]
rw 		MODER[1]
rw 		MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT[15]
rw 		OT[14]
rw 		OT[13]
rw 		OT[12]
rw 		OT[11]
rw 		OT[10]
rw 		OT[9]
rw 		OT[8]
rw 		OT[7]
rw 		OT[6]
rw 		OT[5]
rw 		OT[4]
rw 		OT[3]
rw 		OT[2]
rw 		OT[1]
rw 		OT[0]
rw
Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x000000C0, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR[15]
rw 		OSPEEDR[14]
rw 		OSPEEDR[13]
rw 		OSPEEDR[12]
rw 		OSPEEDR[11]
rw 		OSPEEDR[10]
rw 		OSPEEDR[9]
rw 		OSPEEDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR[7]
rw 		OSPEEDR[6]
rw 		OSPEEDR[5]
rw 		OSPEEDR[4]
rw 		OSPEEDR[3]
rw 		OSPEEDR[2]
rw 		OSPEEDR[1]
rw 		OSPEEDR[0]
rw
Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000100, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw 		PUPDR[14]
rw 		PUPDR[13]
rw 		PUPDR[12]
rw 		PUPDR[11]
rw 		PUPDR[10]
rw 		PUPDR[9]
rw 		PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw 		PUPDR[6]
rw 		PUPDR[5]
rw 		PUPDR[4]
rw 		PUPDR[3]
rw 		PUPDR[2]
rw 		PUPDR[1]
rw 		PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR[15]
r 		IDR[14]
r 		IDR[13]
r 		IDR[12]
r 		IDR[11]
r 		IDR[10]
r 		IDR[9]
r 		IDR[8]
r 		IDR[7]
r 		IDR[6]
r 		IDR[5]
r 		IDR[4]
r 		IDR[3]
r 		IDR[2]
r 		IDR[1]
r 		IDR[0]
r
Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR[15]
rw 		ODR[14]
rw 		ODR[13]
rw 		ODR[12]
rw 		ODR[11]
rw 		ODR[10]
rw 		ODR[9]
rw 		ODR[8]
rw 		ODR[7]
rw 		ODR[6]
rw 		ODR[5]
rw 		ODR[4]
rw 		ODR[3]
rw 		ODR[2]
rw 		ODR[1]
rw 		ODR[0]
rw
Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR[15]
w 		BR[14]
w 		BR[13]
w 		BR[12]
w 		BR[11]
w 		BR[10]
w 		BR[9]
w 		BR[8]
w 		BR[7]
w 		BR[6]
w 		BR[5]
w 		BR[4]
w 		BR[3]
w 		BR[2]
w 		BR[1]
w 		BR[0]
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS[15]
w 		BS[14]
w 		BS[13]
w 		BS[12]
w 		BS[11]
w 		BS[10]
w 		BS[9]
w 		BS[8]
w 		BS[7]
w 		BS[6]
w 		BS[5]
w 		BS[4]
w 		BS[3]
w 		BS[2]
w 		BS[1]
w 		BS[0]
w
Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw 		LCK[14]
rw 		LCK[13]
rw 		LCK[12]
rw 		LCK[11]
rw 		LCK[10]
rw 		LCK[9]
rw 		LCK[8]
rw 		LCK[7]
rw 		LCK[6]
rw 		LCK[5]
rw 		LCK[4]
rw 		LCK[3]
rw 		LCK[2]
rw 		LCK[1]
rw 		LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Lok Key.

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[L7]
rw 		AFR[L6]
rw 		AFR[L5]
rw 		AFR[L4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[L3]
rw 		AFR[L2]
rw 		AFR[L1]
rw 		AFR[L0]
rw
Toggle fields

AFR[L0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[H15]
rw 		AFR[H14]
rw 		AFR[H13]
rw 		AFR[H12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[H11]
rw 		AFR[H10]
rw 		AFR[H9]
rw 		AFR[H8]
rw
Toggle fields

AFR[H8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

Port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR[15]
w 		BR[14]
w 		BR[13]
w 		BR[12]
w 		BR[11]
w 		BR[10]
w 		BR[9]
w 		BR[8]
w 		BR[7]
w 		BR[6]
w 		BR[5]
w 		BR[4]
w 		BR[3]
w 		BR[2]
w 		BR[1]
w 		BR[0]
w
Toggle fields

BR[0]

Bit 0: Port x reset pin 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Port x reset pin 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Port x reset pin 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Port x reset pin 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Port x reset pin 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Port x reset pin 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Port x reset pin 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Port x reset pin 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Port x reset pin 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Port x reset pin 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Port x reset pin 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Port x reset pin 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Port x reset pin 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Port x reset pin 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Port x reset pin 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Port x reset pin 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

GPIOC

0x48000800: General-purpose I/Os

177/177 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw 		MODER[14]
rw 		MODER[13]
rw 		MODER[12]
rw 		MODER[11]
rw 		MODER[10]
rw 		MODER[9]
rw 		MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw 		MODER[6]
rw 		MODER[5]
rw 		MODER[4]
rw 		MODER[3]
rw 		MODER[2]
rw 		MODER[1]
rw 		MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT[15]
rw 		OT[14]
rw 		OT[13]
rw 		OT[12]
rw 		OT[11]
rw 		OT[10]
rw 		OT[9]
rw 		OT[8]
rw 		OT[7]
rw 		OT[6]
rw 		OT[5]
rw 		OT[4]
rw 		OT[3]
rw 		OT[2]
rw 		OT[1]
rw 		OT[0]
rw
Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR[15]
rw 		OSPEEDR[14]
rw 		OSPEEDR[13]
rw 		OSPEEDR[12]
rw 		OSPEEDR[11]
rw 		OSPEEDR[10]
rw 		OSPEEDR[9]
rw 		OSPEEDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR[7]
rw 		OSPEEDR[6]
rw 		OSPEEDR[5]
rw 		OSPEEDR[4]
rw 		OSPEEDR[3]
rw 		OSPEEDR[2]
rw 		OSPEEDR[1]
rw 		OSPEEDR[0]
rw
Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x0C000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw 		PUPDR[14]
rw 		PUPDR[13]
rw 		PUPDR[12]
rw 		PUPDR[11]
rw 		PUPDR[10]
rw 		PUPDR[9]
rw 		PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw 		PUPDR[6]
rw 		PUPDR[5]
rw 		PUPDR[4]
rw 		PUPDR[3]
rw 		PUPDR[2]
rw 		PUPDR[1]
rw 		PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR[15]
r 		IDR[14]
r 		IDR[13]
r 		IDR[12]
r 		IDR[11]
r 		IDR[10]
r 		IDR[9]
r 		IDR[8]
r 		IDR[7]
r 		IDR[6]
r 		IDR[5]
r 		IDR[4]
r 		IDR[3]
r 		IDR[2]
r 		IDR[1]
r 		IDR[0]
r
Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR[15]
rw 		ODR[14]
rw 		ODR[13]
rw 		ODR[12]
rw 		ODR[11]
rw 		ODR[10]
rw 		ODR[9]
rw 		ODR[8]
rw 		ODR[7]
rw 		ODR[6]
rw 		ODR[5]
rw 		ODR[4]
rw 		ODR[3]
rw 		ODR[2]
rw 		ODR[1]
rw 		ODR[0]
rw
Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR[15]
w 		BR[14]
w 		BR[13]
w 		BR[12]
w 		BR[11]
w 		BR[10]
w 		BR[9]
w 		BR[8]
w 		BR[7]
w 		BR[6]
w 		BR[5]
w 		BR[4]
w 		BR[3]
w 		BR[2]
w 		BR[1]
w 		BR[0]
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS[15]
w 		BS[14]
w 		BS[13]
w 		BS[12]
w 		BS[11]
w 		BS[10]
w 		BS[9]
w 		BS[8]
w 		BS[7]
w 		BS[6]
w 		BS[5]
w 		BS[4]
w 		BS[3]
w 		BS[2]
w 		BS[1]
w 		BS[0]
w
Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw 		LCK[14]
rw 		LCK[13]
rw 		LCK[12]
rw 		LCK[11]
rw 		LCK[10]
rw 		LCK[9]
rw 		LCK[8]
rw 		LCK[7]
rw 		LCK[6]
rw 		LCK[5]
rw 		LCK[4]
rw 		LCK[3]
rw 		LCK[2]
rw 		LCK[1]
rw 		LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Lok Key.

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[L7]
rw 		AFR[L6]
rw 		AFR[L5]
rw 		AFR[L4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[L3]
rw 		AFR[L2]
rw 		AFR[L1]
rw 		AFR[L0]
rw
Toggle fields

AFR[L0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[H15]
rw 		AFR[H14]
rw 		AFR[H13]
rw 		AFR[H12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[H11]
rw 		AFR[H10]
rw 		AFR[H9]
rw 		AFR[H8]
rw
Toggle fields

AFR[H8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

Port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR[15]
w 		BR[14]
w 		BR[13]
w 		BR[12]
w 		BR[11]
w 		BR[10]
w 		BR[9]
w 		BR[8]
w 		BR[7]
w 		BR[6]
w 		BR[5]
w 		BR[4]
w 		BR[3]
w 		BR[2]
w 		BR[1]
w 		BR[0]
w
Toggle fields

BR[0]

Bit 0: Port x reset pin 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Port x reset pin 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Port x reset pin 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Port x reset pin 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Port x reset pin 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Port x reset pin 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Port x reset pin 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Port x reset pin 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Port x reset pin 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Port x reset pin 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Port x reset pin 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Port x reset pin 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Port x reset pin 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Port x reset pin 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Port x reset pin 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Port x reset pin 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

GPIOD

0x48000c00: General-purpose I/Os

177/177 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw 		MODER[14]
rw 		MODER[13]
rw 		MODER[12]
rw 		MODER[11]
rw 		MODER[10]
rw 		MODER[9]
rw 		MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw 		MODER[6]
rw 		MODER[5]
rw 		MODER[4]
rw 		MODER[3]
rw 		MODER[2]
rw 		MODER[1]
rw 		MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT[15]
rw 		OT[14]
rw 		OT[13]
rw 		OT[12]
rw 		OT[11]
rw 		OT[10]
rw 		OT[9]
rw 		OT[8]
rw 		OT[7]
rw 		OT[6]
rw 		OT[5]
rw 		OT[4]
rw 		OT[3]
rw 		OT[2]
rw 		OT[1]
rw 		OT[0]
rw
Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR[15]
rw 		OSPEEDR[14]
rw 		OSPEEDR[13]
rw 		OSPEEDR[12]
rw 		OSPEEDR[11]
rw 		OSPEEDR[10]
rw 		OSPEEDR[9]
rw 		OSPEEDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR[7]
rw 		OSPEEDR[6]
rw 		OSPEEDR[5]
rw 		OSPEEDR[4]
rw 		OSPEEDR[3]
rw 		OSPEEDR[2]
rw 		OSPEEDR[1]
rw 		OSPEEDR[0]
rw
Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x0C000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw 		PUPDR[14]
rw 		PUPDR[13]
rw 		PUPDR[12]
rw 		PUPDR[11]
rw 		PUPDR[10]
rw 		PUPDR[9]
rw 		PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw 		PUPDR[6]
rw 		PUPDR[5]
rw 		PUPDR[4]
rw 		PUPDR[3]
rw 		PUPDR[2]
rw 		PUPDR[1]
rw 		PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR[15]
r 		IDR[14]
r 		IDR[13]
r 		IDR[12]
r 		IDR[11]
r 		IDR[10]
r 		IDR[9]
r 		IDR[8]
r 		IDR[7]
r 		IDR[6]
r 		IDR[5]
r 		IDR[4]
r 		IDR[3]
r 		IDR[2]
r 		IDR[1]
r 		IDR[0]
r
Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR[15]
rw 		ODR[14]
rw 		ODR[13]
rw 		ODR[12]
rw 		ODR[11]
rw 		ODR[10]
rw 		ODR[9]
rw 		ODR[8]
rw 		ODR[7]
rw 		ODR[6]
rw 		ODR[5]
rw 		ODR[4]
rw 		ODR[3]
rw 		ODR[2]
rw 		ODR[1]
rw 		ODR[0]
rw
Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR[15]
w 		BR[14]
w 		BR[13]
w 		BR[12]
w 		BR[11]
w 		BR[10]
w 		BR[9]
w 		BR[8]
w 		BR[7]
w 		BR[6]
w 		BR[5]
w 		BR[4]
w 		BR[3]
w 		BR[2]
w 		BR[1]
w 		BR[0]
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS[15]
w 		BS[14]
w 		BS[13]
w 		BS[12]
w 		BS[11]
w 		BS[10]
w 		BS[9]
w 		BS[8]
w 		BS[7]
w 		BS[6]
w 		BS[5]
w 		BS[4]
w 		BS[3]
w 		BS[2]
w 		BS[1]
w 		BS[0]
w
Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw 		LCK[14]
rw 		LCK[13]
rw 		LCK[12]
rw 		LCK[11]
rw 		LCK[10]
rw 		LCK[9]
rw 		LCK[8]
rw 		LCK[7]
rw 		LCK[6]
rw 		LCK[5]
rw 		LCK[4]
rw 		LCK[3]
rw 		LCK[2]
rw 		LCK[1]
rw 		LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Lok Key.

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[L7]
rw 		AFR[L6]
rw 		AFR[L5]
rw 		AFR[L4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[L3]
rw 		AFR[L2]
rw 		AFR[L1]
rw 		AFR[L0]
rw
Toggle fields

AFR[L0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[H15]
rw 		AFR[H14]
rw 		AFR[H13]
rw 		AFR[H12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[H11]
rw 		AFR[H10]
rw 		AFR[H9]
rw 		AFR[H8]
rw
Toggle fields

AFR[H8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

Port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR[15]
w 		BR[14]
w 		BR[13]
w 		BR[12]
w 		BR[11]
w 		BR[10]
w 		BR[9]
w 		BR[8]
w 		BR[7]
w 		BR[6]
w 		BR[5]
w 		BR[4]
w 		BR[3]
w 		BR[2]
w 		BR[1]
w 		BR[0]
w
Toggle fields

BR[0]

Bit 0: Port x reset pin 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Port x reset pin 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Port x reset pin 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Port x reset pin 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Port x reset pin 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Port x reset pin 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Port x reset pin 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Port x reset pin 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Port x reset pin 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Port x reset pin 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Port x reset pin 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Port x reset pin 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Port x reset pin 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Port x reset pin 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Port x reset pin 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Port x reset pin 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

GPIOF

0x48001400: General-purpose I/Os

177/177 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw 		MODER[14]
rw 		MODER[13]
rw 		MODER[12]
rw 		MODER[11]
rw 		MODER[10]
rw 		MODER[9]
rw 		MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw 		MODER[6]
rw 		MODER[5]
rw 		MODER[4]
rw 		MODER[3]
rw 		MODER[2]
rw 		MODER[1]
rw 		MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT[15]
rw 		OT[14]
rw 		OT[13]
rw 		OT[12]
rw 		OT[11]
rw 		OT[10]
rw 		OT[9]
rw 		OT[8]
rw 		OT[7]
rw 		OT[6]
rw 		OT[5]
rw 		OT[4]
rw 		OT[3]
rw 		OT[2]
rw 		OT[1]
rw 		OT[0]
rw
Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR[15]
rw 		OSPEEDR[14]
rw 		OSPEEDR[13]
rw 		OSPEEDR[12]
rw 		OSPEEDR[11]
rw 		OSPEEDR[10]
rw 		OSPEEDR[9]
rw 		OSPEEDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR[7]
rw 		OSPEEDR[6]
rw 		OSPEEDR[5]
rw 		OSPEEDR[4]
rw 		OSPEEDR[3]
rw 		OSPEEDR[2]
rw 		OSPEEDR[1]
rw 		OSPEEDR[0]
rw
Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
3: HighSpeed: High speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x0C000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw 		PUPDR[14]
rw 		PUPDR[13]
rw 		PUPDR[12]
rw 		PUPDR[11]
rw 		PUPDR[10]
rw 		PUPDR[9]
rw 		PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw 		PUPDR[6]
rw 		PUPDR[5]
rw 		PUPDR[4]
rw 		PUPDR[3]
rw 		PUPDR[2]
rw 		PUPDR[1]
rw 		PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR[15]
r 		IDR[14]
r 		IDR[13]
r 		IDR[12]
r 		IDR[11]
r 		IDR[10]
r 		IDR[9]
r 		IDR[8]
r 		IDR[7]
r 		IDR[6]
r 		IDR[5]
r 		IDR[4]
r 		IDR[3]
r 		IDR[2]
r 		IDR[1]
r 		IDR[0]
r
Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR[15]
rw 		ODR[14]
rw 		ODR[13]
rw 		ODR[12]
rw 		ODR[11]
rw 		ODR[10]
rw 		ODR[9]
rw 		ODR[8]
rw 		ODR[7]
rw 		ODR[6]
rw 		ODR[5]
rw 		ODR[4]
rw 		ODR[3]
rw 		ODR[2]
rw 		ODR[1]
rw 		ODR[0]
rw
Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR[15]
w 		BR[14]
w 		BR[13]
w 		BR[12]
w 		BR[11]
w 		BR[10]
w 		BR[9]
w 		BR[8]
w 		BR[7]
w 		BR[6]
w 		BR[5]
w 		BR[4]
w 		BR[3]
w 		BR[2]
w 		BR[1]
w 		BR[0]
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS[15]
w 		BS[14]
w 		BS[13]
w 		BS[12]
w 		BS[11]
w 		BS[10]
w 		BS[9]
w 		BS[8]
w 		BS[7]
w 		BS[6]
w 		BS[5]
w 		BS[4]
w 		BS[3]
w 		BS[2]
w 		BS[1]
w 		BS[0]
w
Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw 		LCK[14]
rw 		LCK[13]
rw 		LCK[12]
rw 		LCK[11]
rw 		LCK[10]
rw 		LCK[9]
rw 		LCK[8]
rw 		LCK[7]
rw 		LCK[6]
rw 		LCK[5]
rw 		LCK[4]
rw 		LCK[3]
rw 		LCK[2]
rw 		LCK[1]
rw 		LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Lok Key.

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[L7]
rw 		AFR[L6]
rw 		AFR[L5]
rw 		AFR[L4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[L3]
rw 		AFR[L2]
rw 		AFR[L1]
rw 		AFR[L0]
rw
Toggle fields

AFR[L0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[H15]
rw 		AFR[H14]
rw 		AFR[H13]
rw 		AFR[H12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[H11]
rw 		AFR[H10]
rw 		AFR[H9]
rw 		AFR[H8]
rw
Toggle fields

AFR[H8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

Port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR[15]
w 		BR[14]
w 		BR[13]
w 		BR[12]
w 		BR[11]
w 		BR[10]
w 		BR[9]
w 		BR[8]
w 		BR[7]
w 		BR[6]
w 		BR[5]
w 		BR[4]
w 		BR[3]
w 		BR[2]
w 		BR[1]
w 		BR[0]
w
Toggle fields

BR[0]

Bit 0: Port x reset pin 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Port x reset pin 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Port x reset pin 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Port x reset pin 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Port x reset pin 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Port x reset pin 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Port x reset pin 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Port x reset pin 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Port x reset pin 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Port x reset pin 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Port x reset pin 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Port x reset pin 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Port x reset pin 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Port x reset pin 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Port x reset pin 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Port x reset pin 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

HRTIM_Common

0x40017780: High Resolution Timer: Common functions

436/436 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 ISR
0xc ICR
0x10 IER
0x14 OENR
0x18 ODISR
0x1c ODSR
0x20 BMCR
0x24 BMTRGR
0x28 BMCMPR
0x2c BMPER
0x30 EECR1
0x34 EECR2
0x38 EECR3
0x3c ADC1R
0x40 ADC2R
0x44 ADC3R
0x48 ADC4R
0x4c DLLCR
0x50 FLTINR1
0x54 FLTINR2
0x58 BDMUPR
0x5c BDTAUPR
0x60 BDTBUPR
0x64 BDTCUPR
0x68 BDTDUPR
0x6c BDTEUPR
0x70 BDMADR
Toggle registers

CR1

Control Register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AD[4]USRC
rw 		AD[3]USRC
rw 		AD[2]USRC
rw 		AD[1]USRC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T[E]UDIS
rw 		T[D]UDIS
rw 		T[C]UDIS
rw 		T[B]UDIS
rw 		T[A]UDIS
rw 		MUDIS
rw
Toggle fields

MUDIS

Bit 0: Master Update Disable.

Allowed values:
0: Enabled: Timer update enabled
1: Disabled: Timer update disabled

T[A]UDIS

Bit 1: Timer A Update Disable.

Allowed values:
0: Enabled: Timer update enabled
1: Disabled: Timer update disabled

T[B]UDIS

Bit 2: Timer B Update Disable.

Allowed values:
0: Enabled: Timer update enabled
1: Disabled: Timer update disabled

T[C]UDIS

Bit 3: Timer C Update Disable.

Allowed values:
0: Enabled: Timer update enabled
1: Disabled: Timer update disabled

T[D]UDIS

Bit 4: Timer D Update Disable.

Allowed values:
0: Enabled: Timer update enabled
1: Disabled: Timer update disabled

T[E]UDIS

Bit 5: Timer E Update Disable.

Allowed values:
0: Enabled: Timer update enabled
1: Disabled: Timer update disabled

AD[1]USRC

Bits 16-18: ADC Trigger 1 Update Source.

Allowed values:
0: Master: ADC trigger update from master timer
1: TimerA: ADC trigger update from timer A
2: TimerB: ADC trigger update from timer B
3: TimerC: ADC trigger update from timer C
4: TimerD: ADC trigger update from timer D
5: TimerE: ADC trigger update from timer E

AD[2]USRC

Bits 19-21: ADC Trigger 2 Update Source.

Allowed values:
0: Master: ADC trigger update from master timer
1: TimerA: ADC trigger update from timer A
2: TimerB: ADC trigger update from timer B
3: TimerC: ADC trigger update from timer C
4: TimerD: ADC trigger update from timer D
5: TimerE: ADC trigger update from timer E

AD[3]USRC

Bits 22-24: ADC Trigger 3 Update Source.

Allowed values:
0: Master: ADC trigger update from master timer
1: TimerA: ADC trigger update from timer A
2: TimerB: ADC trigger update from timer B
3: TimerC: ADC trigger update from timer C
4: TimerD: ADC trigger update from timer D
5: TimerE: ADC trigger update from timer E

AD[4]USRC

Bits 25-27: ADC Trigger 4 Update Source.

Allowed values:
0: Master: ADC trigger update from master timer
1: TimerA: ADC trigger update from timer A
2: TimerB: ADC trigger update from timer B
3: TimerC: ADC trigger update from timer C
4: TimerD: ADC trigger update from timer D
5: TimerE: ADC trigger update from timer E

CR2

Control Register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T[E]RST
rw 		T[D]RST
rw 		T[C]RST
rw 		T[B]RST
rw 		T[A]RST
rw 		MRST
rw 		T[E]SWU
rw 		T[D]SWU
rw 		T[C]SWU
rw 		T[B]SWU
rw 		T[A]SWU
rw 		MSWU
rw
Toggle fields

MSWU

Bit 0: Master Timer Software update.

Allowed values:
1: Update: Force immediate update

T[A]SWU

Bit 1: Timer A Software Update.

Allowed values:
1: Update: Force immediate update

T[B]SWU

Bit 2: Timer B Software Update.

Allowed values:
1: Update: Force immediate update

T[C]SWU

Bit 3: Timer C Software Update.

Allowed values:
1: Update: Force immediate update

T[D]SWU

Bit 4: Timer D Software Update.

Allowed values:
1: Update: Force immediate update

T[E]SWU

Bit 5: Timer E Software Update.

Allowed values:
1: Update: Force immediate update

MRST

Bit 8: Master Counter software reset.

Allowed values:
1: Reset: Reset timer

T[A]RST

Bit 9: Timer A counter software reset.

Allowed values:
1: Reset: Reset timer

T[B]RST

Bit 10: Timer B counter software reset.

Allowed values:
1: Reset: Reset timer

T[C]RST

Bit 11: Timer C counter software reset.

Allowed values:
1: Reset: Reset timer

T[D]RST

Bit 12: Timer D counter software reset.

Allowed values:
1: Reset: Reset timer

T[E]RST

Bit 13: Timer E counter software reset.

Allowed values:
1: Reset: Reset timer

ISR

Interrupt Status Register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BMPER
r 		DLLRDY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYSFLT
rw 		FLT5
r 		FLT4
r 		FLT3
r 		FLT2
r 		FLT1
r
Toggle fields

FLT1

Bit 0: Fault 1 Interrupt Flag.

Allowed values:
0: NoEvent: No fault interrupt occurred
1: Event: Fault interrupt occurred

FLT2

Bit 1: Fault 2 Interrupt Flag.

Allowed values:
0: NoEvent: No fault interrupt occurred
1: Event: Fault interrupt occurred

FLT3

Bit 2: Fault 3 Interrupt Flag.

Allowed values:
0: NoEvent: No fault interrupt occurred
1: Event: Fault interrupt occurred

FLT4

Bit 3: Fault 4 Interrupt Flag.

Allowed values:
0: NoEvent: No fault interrupt occurred
1: Event: Fault interrupt occurred

FLT5

Bit 4: Fault 5 Interrupt Flag.

Allowed values:
0: NoEvent: No fault interrupt occurred
1: Event: Fault interrupt occurred

SYSFLT

Bit 5: System Fault Interrupt Flag.

Allowed values:
0: NoEvent: No fault interrupt occurred
1: Event: Fault interrupt occurred

DLLRDY

Bit 16: DLL Ready Interrupt Flag.

Allowed values:
0: NoEvent: No DLL calibration ready interrupt occurred
1: Event: DLL calibration ready interrupt occurred

BMPER

Bit 17: Burst mode Period Interrupt Flag.

Allowed values:
0: NoEvent: No burst mode period interrupt occurred
1: Event: Burst mode period interrupt occured

ICR

Interrupt Clear Register

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BMPERC
w 		DLLRDYC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYSFLTC
w 		FLT5C
w 		FLT4C
w 		FLT3C
w 		FLT2C
w 		FLT1C
w
Toggle fields

FLT1C

Bit 0: Fault 1 Interrupt Flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

FLT2C

Bit 1: Fault 2 Interrupt Flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

FLT3C

Bit 2: Fault 3 Interrupt Flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

FLT4C

Bit 3: Fault 4 Interrupt Flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

FLT5C

Bit 4: Fault 5 Interrupt Flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

SYSFLTC

Bit 5: System Fault Interrupt Flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

DLLRDYC

Bit 16: DLL Ready Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

BMPERC

Bit 17: Burst mode period flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

IER

Interrupt Enable Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BMPERIE
rw 		DLLRDYIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYSFLTIE
rw 		FLT5IE
rw 		FLT4IE
rw 		FLT3IE
rw 		FLT2IE
rw 		FLT1IE
rw
Toggle fields

FLT1IE

Bit 0: Fault 1 Interrupt Enable.

Allowed values:
0: Disabled: Fault interrupt disabled
1: Enabled: Fault interrupt enabled

FLT2IE

Bit 1: Fault 2 Interrupt Enable.

Allowed values:
0: Disabled: Fault interrupt disabled
1: Enabled: Fault interrupt enabled

FLT3IE

Bit 2: Fault 3 Interrupt Enable.

Allowed values:
0: Disabled: Fault interrupt disabled
1: Enabled: Fault interrupt enabled

FLT4IE

Bit 3: Fault 4 Interrupt Enable.

Allowed values:
0: Disabled: Fault interrupt disabled
1: Enabled: Fault interrupt enabled

FLT5IE

Bit 4: Fault 5 Interrupt Enable.

Allowed values:
0: Disabled: Fault interrupt disabled
1: Enabled: Fault interrupt enabled

SYSFLTIE

Bit 5: System Fault Interrupt Enable.

Allowed values:
0: Disabled: Fault interrupt disabled
1: Enabled: Fault interrupt enabled

DLLRDYIE

Bit 16: DLL Ready Interrupt Enable.

Allowed values:
0: Disabled: DLL ready interrupt disabled
1: Enabled: DLL Ready interrupt enabled

BMPERIE

Bit 17: Burst mode period Interrupt Enable.

Allowed values:
0: Disabled: Burst mode period interrupt disabled
1: Enabled: Burst mode period interrupt enabled

OENR

Output Enable Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T[E]2OEN
rw 		T[E]1OEN
rw 		T[D]2OEN
rw 		T[D]1OEN
rw 		T[C]2OEN
rw 		T[C]1OEN
rw 		T[B]2OEN
rw 		T[B]1OEN
rw 		T[A]2OEN
rw 		T[A]1OEN
rw
Toggle fields

T[A]1OEN

Bit 0: Timer A Output 1 Enable.

Allowed values:
0: Disabled: Output disabled
1: Enabled: Output enabled

T[A]2OEN

Bit 1: Timer A Output 2 Enable.

Allowed values:
0: Disabled: Output disabled
1: Enabled: Output enabled

T[B]1OEN

Bit 2: Timer B Output 1 Enable.

Allowed values:
0: Disabled: Output disabled
1: Enabled: Output enabled

T[B]2OEN

Bit 3: Timer B Output 2 Enable.

Allowed values:
0: Disabled: Output disabled
1: Enabled: Output enabled

T[C]1OEN

Bit 4: Timer C Output 1 Enable.

Allowed values:
0: Disabled: Output disabled
1: Enabled: Output enabled

T[C]2OEN

Bit 5: Timer C Output 2 Enable.

Allowed values:
0: Disabled: Output disabled
1: Enabled: Output enabled

T[D]1OEN

Bit 6: Timer D Output 1 Enable.

Allowed values:
0: Disabled: Output disabled
1: Enabled: Output enabled

T[D]2OEN

Bit 7: Timer D Output 2 Enable.

Allowed values:
0: Disabled: Output disabled
1: Enabled: Output enabled

T[E]1OEN

Bit 8: Timer E Output 1 Enable.

Allowed values:
0: Disabled: Output disabled
1: Enabled: Output enabled

T[E]2OEN

Bit 9: Timer E Output 2 Enable.

Allowed values:
0: Disabled: Output disabled
1: Enabled: Output enabled

ODISR

DISR

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T[E]2ODIS
w 		T[E]1ODIS
w 		T[D]2ODIS
w 		T[D]1ODIS
w 		T[C]2ODIS
w 		T[C]1ODIS
w 		T[B]2ODIS
w 		T[B]1ODIS
w 		T[A]2ODIS
w 		T[A]1ODIS
w
Toggle fields

T[A]1ODIS

Bit 0: TA1ODIS.

Allowed values:
1: Disable: Disable output

T[A]2ODIS

Bit 1: TA2ODIS.

Allowed values:
1: Disable: Disable output

T[B]1ODIS

Bit 2: TB1ODIS.

Allowed values:
1: Disable: Disable output

T[B]2ODIS

Bit 3: TB2ODIS.

Allowed values:
1: Disable: Disable output

T[C]1ODIS

Bit 4: TC1ODIS.

Allowed values:
1: Disable: Disable output

T[C]2ODIS

Bit 5: TC2ODIS.

Allowed values:
1: Disable: Disable output

T[D]1ODIS

Bit 6: TD1ODIS.

Allowed values:
1: Disable: Disable output

T[D]2ODIS

Bit 7: TD2ODIS.

Allowed values:
1: Disable: Disable output

T[E]1ODIS

Bit 8: TE1ODIS.

Allowed values:
1: Disable: Disable output

T[E]2ODIS

Bit 9: TE2ODIS.

Allowed values:
1: Disable: Disable output

ODSR

Output Disable Status Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T[E]2ODS
r 		T[E]1ODS
r 		T[D]2ODS
r 		T[D]1ODS
r 		T[C]2ODS
r 		T[C]1ODS
r 		T[B]2ODS
r 		T[B]1ODS
r 		T[A]2ODS
r 		T[A]1ODS
r
Toggle fields

T[A]1ODS

Bit 0: Timer A Output 1 disable status.

Allowed values:
0: Idle: Output disabled in idle state
1: Fault: Output disabled in fault state

T[A]2ODS

Bit 1: Timer A Output 2 disable status.

Allowed values:
0: Idle: Output disabled in idle state
1: Fault: Output disabled in fault state

T[B]1ODS

Bit 2: Timer B Output 1 disable status.

Allowed values:
0: Idle: Output disabled in idle state
1: Fault: Output disabled in fault state

T[B]2ODS

Bit 3: Timer B Output 2 disable status.

Allowed values:
0: Idle: Output disabled in idle state
1: Fault: Output disabled in fault state

T[C]1ODS

Bit 4: Timer C Output 1 disable status.

Allowed values:
0: Idle: Output disabled in idle state
1: Fault: Output disabled in fault state

T[C]2ODS

Bit 5: Timer C Output 2 disable status.

Allowed values:
0: Idle: Output disabled in idle state
1: Fault: Output disabled in fault state

T[D]1ODS

Bit 6: Timer D Output 1 disable status.

Allowed values:
0: Idle: Output disabled in idle state
1: Fault: Output disabled in fault state

T[D]2ODS

Bit 7: Timer D Output 2 disable status.

Allowed values:
0: Idle: Output disabled in idle state
1: Fault: Output disabled in fault state

T[E]1ODS

Bit 8: Timer E Output 1 disable status.

Allowed values:
0: Idle: Output disabled in idle state
1: Fault: Output disabled in fault state

T[E]2ODS

Bit 9: Timer E Output 2 disable status.

Allowed values:
0: Idle: Output disabled in idle state
1: Fault: Output disabled in fault state

BMCR

Burst Mode Control Register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BMSTAT
rw 		T[E]BM
rw 		T[D]BM
rw 		T[C]BM
rw 		T[B]BM
rw 		T[A]BM
rw 		MTBM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BMPREN
rw 		BMPRSC
rw 		BMCLK
rw 		BMOM
rw 		BME
rw
Toggle fields

BME

Bit 0: Burst Mode enable.

Allowed values:
0: Disabled: Burst mode disabled
1: Enabled: Burst mode enabled

BMOM

Bit 1: Burst Mode operating mode.

Allowed values:
0: SingleShot: Single-shot mode
1: Continuous: Continuous operation

BMCLK

Bits 2-5: Burst Mode Clock source.

Allowed values:
0: Master: Master timer reset/roll-over
1: TimerA: Timer A counter reset/roll-over
2: TimerB: Timer B counter reset/roll-over
3: TimerC: Timer C counter reset/roll-over
4: TimerD: Timer D counter reset/roll-over
5: TimerE: Timer E counter reset/roll-over
6: Event1: On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock
7: Event2: On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock
8: Event3: On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock
9: Event4: On-chip Event 4 (BMClk[4]), acting as a burst mode counter clock
10: Clock: Prescaled f_HRTIM clock (as per BMPRSC[3:0] setting

BMPRSC

Bits 6-9: Burst Mode Prescaler.

Allowed values:
0: Div1: Clock not divided
1: Div2: Division by 2
2: Div4: Division by 4
3: Div8: Division by 8
4: Div16: Division by 16
5: Div32: Division by 32
6: Div64: Division by 64
7: Div128: Division by 128
8: Div256: Division by 256
9: Div512: Division by 512
10: Div1024: Division by 1024
11: Div2048: Division by 2048
12: Div4096: Division by 4096
13: Div8192: Division by 8192
14: Div16384: Division by 16384
15: Div32768: Division by 32768

BMPREN

Bit 10: Burst Mode Preload Enable.

Allowed values:
0: Disabled: Preload disabled: the write access is directly done into active registers
1: Enabled: Preload enabled: the write access is done into preload registers

MTBM

Bit 16: Master Timer Burst Mode.

Allowed values:
0: Normal: Counter clock is maintained and timer operates normally
1: Stopped: Counter clock is stopped and counter is reset

T[A]BM

Bit 17: Timer A Burst Mode.

Allowed values:
0: Normal: Counter clock is maintained and timer operates normally
1: Stopped: Counter clock is stopped and counter is reset

T[B]BM

Bit 18: Timer B Burst Mode.

Allowed values:
0: Normal: Counter clock is maintained and timer operates normally
1: Stopped: Counter clock is stopped and counter is reset

T[C]BM

Bit 19: Timer C Burst Mode.

Allowed values:
0: Normal: Counter clock is maintained and timer operates normally
1: Stopped: Counter clock is stopped and counter is reset

T[D]BM

Bit 20: Timer D Burst Mode.

Allowed values:
0: Normal: Counter clock is maintained and timer operates normally
1: Stopped: Counter clock is stopped and counter is reset

T[E]BM

Bit 21: Timer E Burst Mode.

Allowed values:
0: Normal: Counter clock is maintained and timer operates normally
1: Stopped: Counter clock is stopped and counter is reset

BMSTAT

Bit 31: Burst Mode Status.

Allowed values:
0: Normal: Normal operation
1: Burst: Burst operation ongoing

BMTRGR

BMTRGR

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OCHPEV
rw 		EEV8
rw 		EEV7
rw 		TDEEV8
rw 		TAEEV7
rw 		TECMP2
rw 		TECMP1
rw 		TEREP
rw 		TERST
rw 		TDCMP2
rw 		TDCMP1
rw 		TDREP
rw 		TDRST
rw 		TCCMP2
rw 		TCCMP1
rw 		TCREP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCRST
rw 		TBCMP2
rw 		TBCMP1
rw 		TBREP
rw 		TBRST
rw 		TACMP2
rw 		TACMP1
rw 		TAREP
rw 		TARST
rw 		MSTCMP4
rw 		MSTCMP3
rw 		MSTCMP2
rw 		MSTCMP1
rw 		MSTREP
rw 		MSTRST
rw 		SW
rw
Toggle fields

SW

Bit 0: SW.

Allowed values:
0: NoEffect: No effect
1: Trigger: Trigger immediate burst mode operation

MSTRST

Bit 1: MSTRST.

Allowed values:
0: NoEffect: Master timer reset/roll-over event has no effect
1: Trigger: Master timer reset/roll-over event triggers a burst mode entry

MSTREP

Bit 2: MSTREP.

Allowed values:
0: NoEffect: Master timer repetition event has no effect
1: Trigger: Master timer repetition event triggers a burst mode entry

MSTCMP1

Bit 3: MSTCMP1.

Allowed values:
0: NoEffect: Master timer compare X event has no effect
1: Trigger: Master timer compare X event triggers a burst mode entry

MSTCMP2

Bit 4: MSTCMP2.

Allowed values:
0: NoEffect: Master timer compare X event has no effect
1: Trigger: Master timer compare X event triggers a burst mode entry

MSTCMP3

Bit 5: MSTCMP3.

Allowed values:
0: NoEffect: Master timer compare X event has no effect
1: Trigger: Master timer compare X event triggers a burst mode entry

MSTCMP4

Bit 6: MSTCMP4.

Allowed values:
0: NoEffect: Master timer compare X event has no effect
1: Trigger: Master timer compare X event triggers a burst mode entry

TARST

Bit 7: TARST.

Allowed values:
0: NoEffect: Timer X reset/roll-over event has no effect
1: Trigger: Timer X reset/roll-over event triggers a burst mode entry

TAREP

Bit 8: TAREP.

Allowed values:
0: NoEffect: Timer X repetition event has no effect
1: Trigger: Timer X repetition event triggers a burst mode entry

TACMP1

Bit 9: TACMP1.

Allowed values:
0: NoEffect: Timer X compare Y event has no effect
1: Trigger: Timer X compare Y event triggers a burst mode entry

TACMP2

Bit 10: TACMP2.

Allowed values:
0: NoEffect: Timer X compare Y event has no effect
1: Trigger: Timer X compare Y event triggers a burst mode entry

TBRST

Bit 11: TBRST.

Allowed values:
0: NoEffect: Timer X reset/roll-over event has no effect
1: Trigger: Timer X reset/roll-over event triggers a burst mode entry

TBREP

Bit 12: TBREP.

Allowed values:
0: NoEffect: Timer X repetition event has no effect
1: Trigger: Timer X repetition event triggers a burst mode entry

TBCMP1

Bit 13: TBCMP1.

Allowed values:
0: NoEffect: Timer X compare Y event has no effect
1: Trigger: Timer X compare Y event triggers a burst mode entry

TBCMP2

Bit 14: TBCMP2.

Allowed values:
0: NoEffect: Timer X compare Y event has no effect
1: Trigger: Timer X compare Y event triggers a burst mode entry

TCRST

Bit 15: TCRST.

Allowed values:
0: NoEffect: Timer X reset/roll-over event has no effect
1: Trigger: Timer X reset/roll-over event triggers a burst mode entry

TCREP

Bit 16: TCREP.

Allowed values:
0: NoEffect: Timer X repetition event has no effect
1: Trigger: Timer X repetition event triggers a burst mode entry

TCCMP1

Bit 17: TCCMP1.

Allowed values:
0: NoEffect: Timer X compare Y event has no effect
1: Trigger: Timer X compare Y event triggers a burst mode entry

TCCMP2

Bit 18: TCCMP2.

Allowed values:
0: NoEffect: Timer X compare Y event has no effect
1: Trigger: Timer X compare Y event triggers a burst mode entry

TDRST

Bit 19: TDRST.

Allowed values:
0: NoEffect: Timer X reset/roll-over event has no effect
1: Trigger: Timer X reset/roll-over event triggers a burst mode entry

TDREP

Bit 20: TDREP.

Allowed values:
0: NoEffect: Timer X repetition event has no effect
1: Trigger: Timer X repetition event triggers a burst mode entry

TDCMP1

Bit 21: TDCMP1.

Allowed values:
0: NoEffect: Timer X compare Y event has no effect
1: Trigger: Timer X compare Y event triggers a burst mode entry

TDCMP2

Bit 22: TDCMP2.

Allowed values:
0: NoEffect: Timer X compare Y event has no effect
1: Trigger: Timer X compare Y event triggers a burst mode entry

TERST

Bit 23: TERST.

Allowed values:
0: NoEffect: Timer X reset/roll-over event has no effect
1: Trigger: Timer X reset/roll-over event triggers a burst mode entry

TEREP

Bit 24: TEREP.

Allowed values:
0: NoEffect: Timer X repetition event has no effect
1: Trigger: Timer X repetition event triggers a burst mode entry

TECMP1

Bit 25: TECMP1.

Allowed values:
0: NoEffect: Timer X compare Y event has no effect
1: Trigger: Timer X compare Y event triggers a burst mode entry

TECMP2

Bit 26: TECMP2.

Allowed values:
0: NoEffect: Timer X compare Y event has no effect
1: Trigger: Timer X compare Y event triggers a burst mode entry

TAEEV7

Bit 27: TAEEV7.

Allowed values:
0: NoEffect: Timer X period following external event Y has no effect
1: Trigger: Timer X period following external event Y triggers a burst mode entry

TDEEV8

Bit 28: TDEEV8.

Allowed values:
0: NoEffect: Timer X period following external event Y has no effect
1: Trigger: Timer X period following external event Y triggers a burst mode entry

EEV7

Bit 29: EEV7.

Allowed values:
0: NoEffect: External event X has no effect
1: Trigger: External event X triggers a burst mode entry

EEV8

Bit 30: EEV8.

Allowed values:
0: NoEffect: External event X has no effect
1: Trigger: External event X triggers a burst mode entry

OCHPEV

Bit 31: OCHPEV.

Allowed values:
0: NoEffect: Rising edge on an on-chip event has no effect
1: Trigger: Rising edge on an on-chip event triggers a burst mode entry

BMCMPR

BMCMPR

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BMCMP
rw
Toggle fields

BMCMP

Bits 0-15: BMCMP.

Allowed values: 0x0-0xffff

BMPER

Burst Mode Period Register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BMPER
rw
Toggle fields

BMPER

Bits 0-15: Burst mode Period.

Allowed values: 0x0-0xffff

EECR1

Timer External Event Control Register 1

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EE[5]FAST
rw 		EE[5]SNS
rw 		EE[5]POL
rw 		EE[5]SRC
rw 		EE[4]FAST
rw 		EE[4]SNS
rw 		EE[4]POL
rw 		EE[4]SRC
rw 		EE[3]FAST
rw 		EE[3]SNS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EE[3]SNS
rw 		EE[3]POL
rw 		EE[3]SRC
rw 		EE[2]FAST
rw 		EE[2]SNS
rw 		EE[2]POL
rw 		EE[2]SRC
rw 		EE[1]FAST
rw 		EE[1]SNS
rw 		EE[1]POL
rw 		EE[1]SRC
rw
Toggle fields

EE[1]SRC

Bits 0-1: External Event 1 Source.

Allowed values:
0: Src1: Source 1
1: Src2: Source 2
2: Src3: Source 3
3: Src4: Source 4

EE[1]POL

Bit 2: External Event 1 Polarity.

Allowed values:
0: ActiveHigh: External event is active high
1: ActiveLow: External event is active low

EE[1]SNS

Bits 3-4: External Event 1 Sensitivity.

Allowed values:
0: Active: On active level defined by EExPOL bit
1: Rising: Rising edge
2: Falling: Falling edge
3: Both: Both edges

EE[1]FAST

Bit 5: External Event 1 Fast mode.

Allowed values:
0: Resynchronized: External event is re-synchronised by the HRTIM logic before acting on outputs
1: Asynchronous: External event is acting asynchronously on outputs (low-latency mode)

EE[2]SRC

Bits 6-7: External Event 2 Source.

Allowed values:
0: Src1: Source 1
1: Src2: Source 2
2: Src3: Source 3
3: Src4: Source 4

EE[2]POL

Bit 8: External Event 2 Polarity.

Allowed values:
0: ActiveHigh: External event is active high
1: ActiveLow: External event is active low

EE[2]SNS

Bits 9-10: External Event 2 Sensitivity.

Allowed values:
0: Active: On active level defined by EExPOL bit
1: Rising: Rising edge
2: Falling: Falling edge
3: Both: Both edges

EE[2]FAST

Bit 11: External Event 2 Fast mode.

Allowed values:
0: Resynchronized: External event is re-synchronised by the HRTIM logic before acting on outputs
1: Asynchronous: External event is acting asynchronously on outputs (low-latency mode)

EE[3]SRC

Bits 12-13: External Event 3 Source.

Allowed values:
0: Src1: Source 1
1: Src2: Source 2
2: Src3: Source 3
3: Src4: Source 4

EE[3]POL

Bit 14: External Event 3 Polarity.

Allowed values:
0: ActiveHigh: External event is active high
1: ActiveLow: External event is active low

EE[3]SNS

Bits 15-16: External Event 3 Sensitivity.

Allowed values:
0: Active: On active level defined by EExPOL bit
1: Rising: Rising edge
2: Falling: Falling edge
3: Both: Both edges

EE[3]FAST

Bit 17: External Event 3 Fast mode.

Allowed values:
0: Resynchronized: External event is re-synchronised by the HRTIM logic before acting on outputs
1: Asynchronous: External event is acting asynchronously on outputs (low-latency mode)

EE[4]SRC

Bits 18-19: External Event 4 Source.

Allowed values:
0: Src1: Source 1
1: Src2: Source 2
2: Src3: Source 3
3: Src4: Source 4

EE[4]POL

Bit 20: External Event 4 Polarity.

Allowed values:
0: ActiveHigh: External event is active high
1: ActiveLow: External event is active low

EE[4]SNS

Bits 21-22: External Event 4 Sensitivity.

Allowed values:
0: Active: On active level defined by EExPOL bit
1: Rising: Rising edge
2: Falling: Falling edge
3: Both: Both edges

EE[4]FAST

Bit 23: External Event 4 Fast mode.

Allowed values:
0: Resynchronized: External event is re-synchronised by the HRTIM logic before acting on outputs
1: Asynchronous: External event is acting asynchronously on outputs (low-latency mode)

EE[5]SRC

Bits 24-25: External Event 5 Source.

Allowed values:
0: Src1: Source 1
1: Src2: Source 2
2: Src3: Source 3
3: Src4: Source 4

EE[5]POL

Bit 26: External Event 5 Polarity.

Allowed values:
0: ActiveHigh: External event is active high
1: ActiveLow: External event is active low

EE[5]SNS

Bits 27-28: External Event 5 Sensitivity.

Allowed values:
0: Active: On active level defined by EExPOL bit
1: Rising: Rising edge
2: Falling: Falling edge
3: Both: Both edges

EE[5]FAST

Bit 29: External Event 5 Fast mode.

Allowed values:
0: Resynchronized: External event is re-synchronised by the HRTIM logic before acting on outputs
1: Asynchronous: External event is acting asynchronously on outputs (low-latency mode)

EECR2

Timer External Event Control Register 2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EE[10]SNS
rw 		EE[10]POL
rw 		EE[10]SRC
rw 		EE[9]SNS
rw 		EE[9]POL
rw 		EE[9]SRC
rw 		EE[8]SNS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EE[8]SNS
rw 		EE[8]POL
rw 		EE[8]SRC
rw 		EE[7]SNS
rw 		EE[7]POL
rw 		EE[7]SRC
rw 		EE[6]SNS
rw 		EE[6]POL
rw 		EE[6]SRC
rw
Toggle fields

EE[6]SRC

Bits 0-1: External Event 6 Source.

Allowed values:
0: Src1: Source 1
1: Src2: Source 2
2: Src3: Source 3
3: Src4: Source 4

EE[6]POL

Bit 2: External Event 6 Polarity.

Allowed values:
0: ActiveHigh: External event is active high
1: ActiveLow: External event is active low

EE[6]SNS

Bits 3-4: External Event 6 Sensitivity.

Allowed values:
0: Active: On active level defined by EExPOL bit
1: Rising: Rising edge
2: Falling: Falling edge
3: Both: Both edges

EE[7]SRC

Bits 6-7: External Event 7 Source.

Allowed values:
0: Src1: Source 1
1: Src2: Source 2
2: Src3: Source 3
3: Src4: Source 4

EE[7]POL

Bit 8: External Event 7 Polarity.

Allowed values:
0: ActiveHigh: External event is active high
1: ActiveLow: External event is active low

EE[7]SNS

Bits 9-10: External Event 7 Sensitivity.

Allowed values:
0: Active: On active level defined by EExPOL bit
1: Rising: Rising edge
2: Falling: Falling edge
3: Both: Both edges

EE[8]SRC

Bits 12-13: External Event 8 Source.

Allowed values:
0: Src1: Source 1
1: Src2: Source 2
2: Src3: Source 3
3: Src4: Source 4

EE[8]POL

Bit 14: External Event 8 Polarity.

Allowed values:
0: ActiveHigh: External event is active high
1: ActiveLow: External event is active low

EE[8]SNS

Bits 15-16: External Event 8 Sensitivity.

Allowed values:
0: Active: On active level defined by EExPOL bit
1: Rising: Rising edge
2: Falling: Falling edge
3: Both: Both edges

EE[9]SRC

Bits 18-19: External Event 9 Source.

Allowed values:
0: Src1: Source 1
1: Src2: Source 2
2: Src3: Source 3
3: Src4: Source 4

EE[9]POL

Bit 20: External Event 9 Polarity.

Allowed values:
0: ActiveHigh: External event is active high
1: ActiveLow: External event is active low

EE[9]SNS

Bits 21-22: External Event 9 Sensitivity.

Allowed values:
0: Active: On active level defined by EExPOL bit
1: Rising: Rising edge
2: Falling: Falling edge
3: Both: Both edges

EE[10]SRC

Bits 24-25: External Event 10 Source.

Allowed values:
0: Src1: Source 1
1: Src2: Source 2
2: Src3: Source 3
3: Src4: Source 4

EE[10]POL

Bit 26: External Event 10 Polarity.

Allowed values:
0: ActiveHigh: External event is active high
1: ActiveLow: External event is active low

EE[10]SNS

Bits 27-28: External Event 10 Sensitivity.

Allowed values:
0: Active: On active level defined by EExPOL bit
1: Rising: Rising edge
2: Falling: Falling edge
3: Both: Both edges

EECR3

Timer External Event Control Register 3

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EEVSD
rw 		EE[10]F
rw 		EE[9]F
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EE[8]F
rw 		EE[7]F
rw 		EE[6]F
rw
Toggle fields

EE[6]F

Bits 0-3: EE6F.

Allowed values:
0: Disabled: Filter disabled
1: Div1_N2: f_SAMPLING=f_HRTIM, N=2
2: Div1_N4: f_SAMPLING=f_HRTIM, N=4
3: Div1_N8: f_SAMPLING=f_HRTIM, N=8
4: Div2_N6: f_SAMPLING=f_HRTIM/2, N=6
5: Div2_N8: f_SAMPLING=f_HRTIM/2, N=8
6: Div4_N6: f_SAMPLING=f_HRTIM/4, N=6
7: Div4_N8: f_SAMPLING=f_HRTIM/4, N=8
8: Div8_N6: f_SAMPLING=f_HRTIM/8, N=6
9: Div8_N8: f_SAMPLING=f_HRTIM/8, N=8
10: Div16_N5: f_SAMPLING=f_HRTIM/16, N=5
11: Div16_N6: f_SAMPLING=f_HRTIM/16, N=6
12: Div16_N8: f_SAMPLING=f_HRTIM/16, N=8
13: Div32_N5: f_SAMPLING=f_HRTIM/32, N=5
14: Div32_N6: f_SAMPLING=f_HRTIM/32, N=6
15: Div32_N8: f_SAMPLING=f_HRTIM/32, N=8

EE[7]F

Bits 6-9: EE7F.

Allowed values:
0: Disabled: Filter disabled
1: Div1_N2: f_SAMPLING=f_HRTIM, N=2
2: Div1_N4: f_SAMPLING=f_HRTIM, N=4
3: Div1_N8: f_SAMPLING=f_HRTIM, N=8
4: Div2_N6: f_SAMPLING=f_HRTIM/2, N=6
5: Div2_N8: f_SAMPLING=f_HRTIM/2, N=8
6: Div4_N6: f_SAMPLING=f_HRTIM/4, N=6
7: Div4_N8: f_SAMPLING=f_HRTIM/4, N=8
8: Div8_N6: f_SAMPLING=f_HRTIM/8, N=6
9: Div8_N8: f_SAMPLING=f_HRTIM/8, N=8
10: Div16_N5: f_SAMPLING=f_HRTIM/16, N=5
11: Div16_N6: f_SAMPLING=f_HRTIM/16, N=6
12: Div16_N8: f_SAMPLING=f_HRTIM/16, N=8
13: Div32_N5: f_SAMPLING=f_HRTIM/32, N=5
14: Div32_N6: f_SAMPLING=f_HRTIM/32, N=6
15: Div32_N8: f_SAMPLING=f_HRTIM/32, N=8

EE[8]F

Bits 12-15: EE8F.

Allowed values:
0: Disabled: Filter disabled
1: Div1_N2: f_SAMPLING=f_HRTIM, N=2
2: Div1_N4: f_SAMPLING=f_HRTIM, N=4
3: Div1_N8: f_SAMPLING=f_HRTIM, N=8
4: Div2_N6: f_SAMPLING=f_HRTIM/2, N=6
5: Div2_N8: f_SAMPLING=f_HRTIM/2, N=8
6: Div4_N6: f_SAMPLING=f_HRTIM/4, N=6
7: Div4_N8: f_SAMPLING=f_HRTIM/4, N=8
8: Div8_N6: f_SAMPLING=f_HRTIM/8, N=6
9: Div8_N8: f_SAMPLING=f_HRTIM/8, N=8
10: Div16_N5: f_SAMPLING=f_HRTIM/16, N=5
11: Div16_N6: f_SAMPLING=f_HRTIM/16, N=6
12: Div16_N8: f_SAMPLING=f_HRTIM/16, N=8
13: Div32_N5: f_SAMPLING=f_HRTIM/32, N=5
14: Div32_N6: f_SAMPLING=f_HRTIM/32, N=6
15: Div32_N8: f_SAMPLING=f_HRTIM/32, N=8

EE[9]F

Bits 18-21: EE9F.

Allowed values:
0: Disabled: Filter disabled
1: Div1_N2: f_SAMPLING=f_HRTIM, N=2
2: Div1_N4: f_SAMPLING=f_HRTIM, N=4
3: Div1_N8: f_SAMPLING=f_HRTIM, N=8
4: Div2_N6: f_SAMPLING=f_HRTIM/2, N=6
5: Div2_N8: f_SAMPLING=f_HRTIM/2, N=8
6: Div4_N6: f_SAMPLING=f_HRTIM/4, N=6
7: Div4_N8: f_SAMPLING=f_HRTIM/4, N=8
8: Div8_N6: f_SAMPLING=f_HRTIM/8, N=6
9: Div8_N8: f_SAMPLING=f_HRTIM/8, N=8
10: Div16_N5: f_SAMPLING=f_HRTIM/16, N=5
11: Div16_N6: f_SAMPLING=f_HRTIM/16, N=6
12: Div16_N8: f_SAMPLING=f_HRTIM/16, N=8
13: Div32_N5: f_SAMPLING=f_HRTIM/32, N=5
14: Div32_N6: f_SAMPLING=f_HRTIM/32, N=6
15: Div32_N8: f_SAMPLING=f_HRTIM/32, N=8

EE[10]F

Bits 24-27: EE10F.

Allowed values:
0: Disabled: Filter disabled
1: Div1_N2: f_SAMPLING=f_HRTIM, N=2
2: Div1_N4: f_SAMPLING=f_HRTIM, N=4
3: Div1_N8: f_SAMPLING=f_HRTIM, N=8
4: Div2_N6: f_SAMPLING=f_HRTIM/2, N=6
5: Div2_N8: f_SAMPLING=f_HRTIM/2, N=8
6: Div4_N6: f_SAMPLING=f_HRTIM/4, N=6
7: Div4_N8: f_SAMPLING=f_HRTIM/4, N=8
8: Div8_N6: f_SAMPLING=f_HRTIM/8, N=6
9: Div8_N8: f_SAMPLING=f_HRTIM/8, N=8
10: Div16_N5: f_SAMPLING=f_HRTIM/16, N=5
11: Div16_N6: f_SAMPLING=f_HRTIM/16, N=6
12: Div16_N8: f_SAMPLING=f_HRTIM/16, N=8
13: Div32_N5: f_SAMPLING=f_HRTIM/32, N=5
14: Div32_N6: f_SAMPLING=f_HRTIM/32, N=6
15: Div32_N8: f_SAMPLING=f_HRTIM/32, N=8

EEVSD

Bits 30-31: EEVSD.

Allowed values:
0: Div1: f_EEVS=f_HRTIM
1: Div2: f_EEVS=f_HRTIM/2
2: Div4: f_EEVS=f_HRTIM/4
3: Div8: f_EEVS=f_HRTIM/8

ADC1R

ADC Trigger 1 Register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPER
rw 		EC4
rw 		EC3
rw 		EC2
rw 		DPER
rw 		DC4
rw 		DC3
rw 		DC2
rw 		CPER
rw 		CC4
rw 		CC3
rw 		CC2
rw 		BRST
rw 		BPER
rw 		BC4
rw 		BC3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BC2
rw 		ARST
rw 		APER
rw 		AC4
rw 		AC3
rw 		AC2
rw 		EEV[5]
rw 		EEV[4]
rw 		EEV[3]
rw 		EEV[2]
rw 		EEV[1]
rw 		MPER
rw 		MC[4]
rw 		MC[3]
rw 		MC[2]
rw 		MC[1]
rw
Toggle fields

MC[1]

Bit 0: ADC trigger 1 on Master Compare 1.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MC[2]

Bit 1: ADC trigger 1 on Master Compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MC[3]

Bit 2: ADC trigger 1 on Master Compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MC[4]

Bit 3: ADC trigger 1 on Master Compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MPER

Bit 4: ADC trigger 1 on Master Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

EEV[1]

Bit 5: ADC trigger 1 on External Event 1.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[2]

Bit 6: ADC trigger 1 on External Event 2.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[3]

Bit 7: ADC trigger 1 on External Event 3.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[4]

Bit 8: ADC trigger 1 on External Event 4.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[5]

Bit 9: ADC trigger 1 on External Event 5.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

AC2

Bit 10: ADC trigger 1 on Timer A compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

AC3

Bit 11: ADC trigger 1 on Timer A compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

AC4

Bit 12: ADC trigger 1 on Timer A compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

APER

Bit 13: ADC trigger 1 on Timer A Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

ARST

Bit 14: ADC trigger 1 on Timer A Reset.

Allowed values:
0: Disabled: No generation of ADC trigger on timer reset and roll-over
1: Enabled: Generation of ADC trigger on timer reset and roll-over

BC2

Bit 15: ADC trigger 1 on Timer B compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

BC3

Bit 16: ADC trigger 1 on Timer B compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

BC4

Bit 17: ADC trigger 1 on Timer B compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

BPER

Bit 18: ADC trigger 1 on Timer B Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

BRST

Bit 19: ADC trigger 1 on Timer B Reset.

Allowed values:
0: Disabled: No generation of ADC trigger on timer reset and roll-over
1: Enabled: Generation of ADC trigger on timer reset and roll-over

CC2

Bit 20: ADC trigger 1 on Timer C compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

CC3

Bit 21: ADC trigger 1 on Timer C compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

CC4

Bit 22: ADC trigger 1 on Timer C compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

CPER

Bit 23: ADC trigger 1 on Timer C Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

DC2

Bit 24: ADC trigger 1 on Timer D compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

DC3

Bit 25: ADC trigger 1 on Timer D compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

DC4

Bit 26: ADC trigger 1 on Timer D compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

DPER

Bit 27: ADC trigger 1 on Timer D Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

EC2

Bit 28: ADC trigger 1 on Timer E compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

EC3

Bit 29: ADC trigger 1 on Timer E compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

EC4

Bit 30: ADC trigger 1 on Timer E compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

EPER

Bit 31: ADC trigger 1 on Timer E Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

ADC2R

ADC Trigger 2 Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ERST
rw 		EC4
rw 		EC3
rw 		EC2
rw 		DRST
rw 		DPER
rw 		DC4
rw 		DC3
rw 		DC2
rw 		CRST
rw 		CPER
rw 		CC4
rw 		CC3
rw 		CC2
rw 		BPER
rw 		BC4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BC3
rw 		BC2
rw 		APER
rw 		AC4
rw 		AC3
rw 		AC2
rw 		EEV[10]
rw 		EEV[9]
rw 		EEV[8]
rw 		EEV[7]
rw 		EEV[6]
rw 		MPER
rw 		MC[4]
rw 		MC[3]
rw 		MC[2]
rw 		MC[1]
rw
Toggle fields

MC[1]

Bit 0: ADC trigger 2 on Master Compare 1.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MC[2]

Bit 1: ADC trigger 2 on Master Compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MC[3]

Bit 2: ADC trigger 2 on Master Compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MC[4]

Bit 3: ADC trigger 2 on Master Compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MPER

Bit 4: ADC trigger 2 on Master Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

EEV[6]

Bit 5: ADC trigger 2 on External Event 6.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[7]

Bit 6: ADC trigger 2 on External Event 7.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[8]

Bit 7: ADC trigger 2 on External Event 8.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[9]

Bit 8: ADC trigger 2 on External Event 9.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[10]

Bit 9: ADC trigger 2 on External Event 10.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

AC2

Bit 10: ADC trigger 2 on Timer A compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

AC3

Bit 11: ADC trigger 2 on Timer A compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

AC4

Bit 12: ADC trigger 2 on Timer A compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

APER

Bit 13: ADC trigger 2 on Timer A Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

BC2

Bit 14: ADC trigger 2 on Timer B compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

BC3

Bit 15: ADC trigger 2 on Timer B compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

BC4

Bit 16: ADC trigger 2 on Timer B compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

BPER

Bit 17: ADC trigger 2 on Timer B Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

CC2

Bit 18: ADC trigger 2 on Timer C compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

CC3

Bit 19: ADC trigger 2 on Timer C compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

CC4

Bit 20: ADC trigger 2 on Timer C compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

CPER

Bit 21: ADC trigger 2 on Timer C Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

CRST

Bit 22: ADC trigger 2 on Timer C Reset.

Allowed values:
0: Disabled: No generation of ADC trigger on timer reset and roll-over
1: Enabled: Generation of ADC trigger on timer reset and roll-over

DC2

Bit 23: ADC trigger 2 on Timer D compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

DC3

Bit 24: ADC trigger 2 on Timer D compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

DC4

Bit 25: ADC trigger 2 on Timer D compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

DPER

Bit 26: ADC trigger 2 on Timer D Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

DRST

Bit 27: ADC trigger 2 on Timer D Reset.

Allowed values:
0: Disabled: No generation of ADC trigger on timer reset and roll-over
1: Enabled: Generation of ADC trigger on timer reset and roll-over

EC2

Bit 28: ADC trigger 2 on Timer E compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

EC3

Bit 29: ADC trigger 2 on Timer E compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

EC4

Bit 30: ADC trigger 2 on Timer E compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

ERST

Bit 31: ADC trigger 2 on Timer E Reset.

Allowed values:
0: Disabled: No generation of ADC trigger on timer reset and roll-over
1: Enabled: Generation of ADC trigger on timer reset and roll-over

ADC3R

ADC Trigger 3 Register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPER
rw 		EC4
rw 		EC3
rw 		EC2
rw 		DPER
rw 		DC4
rw 		DC3
rw 		DC2
rw 		CPER
rw 		CC4
rw 		CC3
rw 		CC2
rw 		BRST
rw 		BPER
rw 		BC4
rw 		BC3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BC2
rw 		ARST
rw 		APER
rw 		AC4
rw 		AC3
rw 		AC2
rw 		EEV[5]
rw 		EEV[4]
rw 		EEV[3]
rw 		EEV[2]
rw 		EEV[1]
rw 		MPER
rw 		MC[4]
rw 		MC[3]
rw 		MC[2]
rw 		MC[1]
rw
Toggle fields

MC[1]

Bit 0: ADC trigger 1 on Master Compare 1.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MC[2]

Bit 1: ADC trigger 1 on Master Compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MC[3]

Bit 2: ADC trigger 1 on Master Compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MC[4]

Bit 3: ADC trigger 1 on Master Compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MPER

Bit 4: ADC trigger 1 on Master Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

EEV[1]

Bit 5: ADC trigger 1 on External Event 1.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[2]

Bit 6: ADC trigger 1 on External Event 2.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[3]

Bit 7: ADC trigger 1 on External Event 3.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[4]

Bit 8: ADC trigger 1 on External Event 4.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[5]

Bit 9: ADC trigger 1 on External Event 5.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

AC2

Bit 10: ADC trigger 1 on Timer A compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

AC3

Bit 11: ADC trigger 1 on Timer A compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

AC4

Bit 12: ADC trigger 1 on Timer A compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

APER

Bit 13: ADC trigger 1 on Timer A Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

ARST

Bit 14: ADC trigger 1 on Timer A Reset.

Allowed values:
0: Disabled: No generation of ADC trigger on timer reset and roll-over
1: Enabled: Generation of ADC trigger on timer reset and roll-over

BC2

Bit 15: ADC trigger 1 on Timer B compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

BC3

Bit 16: ADC trigger 1 on Timer B compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

BC4

Bit 17: ADC trigger 1 on Timer B compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

BPER

Bit 18: ADC trigger 1 on Timer B Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

BRST

Bit 19: ADC trigger 1 on Timer B Reset.

Allowed values:
0: Disabled: No generation of ADC trigger on timer reset and roll-over
1: Enabled: Generation of ADC trigger on timer reset and roll-over

CC2

Bit 20: ADC trigger 1 on Timer C compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

CC3

Bit 21: ADC trigger 1 on Timer C compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

CC4

Bit 22: ADC trigger 1 on Timer C compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

CPER

Bit 23: ADC trigger 1 on Timer C Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

DC2

Bit 24: ADC trigger 1 on Timer D compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

DC3

Bit 25: ADC trigger 1 on Timer D compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

DC4

Bit 26: ADC trigger 1 on Timer D compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

DPER

Bit 27: ADC trigger 1 on Timer D Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

EC2

Bit 28: ADC trigger 1 on Timer E compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

EC3

Bit 29: ADC trigger 1 on Timer E compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

EC4

Bit 30: ADC trigger 1 on Timer E compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

EPER

Bit 31: ADC trigger 1 on Timer E Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

ADC4R

ADC Trigger 4 Register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ERST
rw 		EC4
rw 		EC3
rw 		EC2
rw 		DRST
rw 		DPER
rw 		DC4
rw 		DC3
rw 		DC2
rw 		CRST
rw 		CPER
rw 		CC4
rw 		CC3
rw 		CC2
rw 		BPER
rw 		BC4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BC3
rw 		BC2
rw 		APER
rw 		AC4
rw 		AC3
rw 		AC2
rw 		EEV[10]
rw 		EEV[9]
rw 		EEV[8]
rw 		EEV[7]
rw 		EEV[6]
rw 		MPER
rw 		MC[4]
rw 		MC[3]
rw 		MC[2]
rw 		MC[1]
rw
Toggle fields

MC[1]

Bit 0: ADC trigger 2 on Master Compare 1.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MC[2]

Bit 1: ADC trigger 2 on Master Compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MC[3]

Bit 2: ADC trigger 2 on Master Compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MC[4]

Bit 3: ADC trigger 2 on Master Compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MPER

Bit 4: ADC trigger 2 on Master Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

EEV[6]

Bit 5: ADC trigger 2 on External Event 6.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[7]

Bit 6: ADC trigger 2 on External Event 7.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[8]

Bit 7: ADC trigger 2 on External Event 8.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[9]

Bit 8: ADC trigger 2 on External Event 9.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[10]

Bit 9: ADC trigger 2 on External Event 10.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

AC2

Bit 10: ADC trigger 2 on Timer A compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

AC3

Bit 11: ADC trigger 2 on Timer A compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

AC4

Bit 12: ADC trigger 2 on Timer A compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

APER

Bit 13: ADC trigger 2 on Timer A Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

BC2

Bit 14: ADC trigger 2 on Timer B compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

BC3

Bit 15: ADC trigger 2 on Timer B compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

BC4

Bit 16: ADC trigger 2 on Timer B compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

BPER

Bit 17: ADC trigger 2 on Timer B Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

CC2

Bit 18: ADC trigger 2 on Timer C compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

CC3

Bit 19: ADC trigger 2 on Timer C compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

CC4

Bit 20: ADC trigger 2 on Timer C compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

CPER

Bit 21: ADC trigger 2 on Timer C Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

CRST

Bit 22: ADC trigger 2 on Timer C Reset.

Allowed values:
0: Disabled: No generation of ADC trigger on timer reset and roll-over
1: Enabled: Generation of ADC trigger on timer reset and roll-over

DC2

Bit 23: ADC trigger 2 on Timer D compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

DC3

Bit 24: ADC trigger 2 on Timer D compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

DC4

Bit 25: ADC trigger 2 on Timer D compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

DPER

Bit 26: ADC trigger 2 on Timer D Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

DRST

Bit 27: ADC trigger 2 on Timer D Reset.

Allowed values:
0: Disabled: No generation of ADC trigger on timer reset and roll-over
1: Enabled: Generation of ADC trigger on timer reset and roll-over

EC2

Bit 28: ADC trigger 2 on Timer E compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

EC3

Bit 29: ADC trigger 2 on Timer E compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

EC4

Bit 30: ADC trigger 2 on Timer E compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

ERST

Bit 31: ADC trigger 2 on Timer E Reset.

Allowed values:
0: Disabled: No generation of ADC trigger on timer reset and roll-over
1: Enabled: Generation of ADC trigger on timer reset and roll-over

DLLCR

DLL Control Register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALRTE
rw 		CALEN
rw 		CAL
rw
Toggle fields

CAL

Bit 0: DLL Calibration Start.

Allowed values:
1: Start: Calibration start

CALEN

Bit 1: DLL Calibration Enable.

Allowed values:
0: Disabled: Periodic calibration disabled
1: Enabled: Calibration is performed periodically, as per CALRTE setting

CALRTE

Bits 2-3: DLL Calibration rate.

Allowed values:
0: Clk1048576: 1048576*t_HRTIM (6.168 ms for fHRTIM = 170 MHz)
1: Clk131072: 131072*t_HRTIM (771 µs for f_HRTIM = 170 MHz)
2: Clk16384: 16384*t_HRTIM (96 µs for f_HRTIM = 170 MHz)
3: Clk2048: 2048*t_HRTIM (12 µs for f_HRTIM = 170 MHz)

FLTINR1

HRTIM Fault Input Register 1

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLT4LCK
rw 		FLT[4]F
rw 		FLT[4]SRC
rw 		FLT[4]P
rw 		FLT[4]E
rw 		FLT3LCK
rw 		FLT[3]F
rw 		FLT[3]SRC
rw 		FLT[3]P
rw 		FLT[3]E
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLT2LCK
rw 		FLT[2]F
rw 		FLT[2]SRC
rw 		FLT[2]P
rw 		FLT[2]E
rw 		FLT1LCK
rw 		FLT[1]F
rw 		FLT[1]SRC
rw 		FLT[1]P
rw 		FLT[1]E
rw
Toggle fields

FLT[1]E

Bit 0: FLT1E.

Allowed values:
0: Disabled: Fault input disabled
1: Enabled: Fault input enabled

FLT[1]P

Bit 1: FLT1P.

Allowed values:
0: ActiveLow: Fault input is active low
1: ActiveHigh: Fault input is active high

FLT[1]SRC

Bit 2: Fault 1 source.

Allowed values:
0: Input: Fault input is FLTx input pin
1: Internal: Fault input is FLTn_Int signal

FLT[1]F

Bits 3-6: FLT1F.

Allowed values:
0: Disabled: No filter, FLTx acts asynchronously
1: Div1_N2: f_SAMPLING=f_HRTIM, N=2
2: Div1_N4: f_SAMPLING=f_HRTIM, N=4
3: Div1_N8: f_SAMPLING=f_HRTIM, N=8
4: Div2_N6: f_SAMPLING=f_HRTIM/2, N=6
5: Div2_N8: f_SAMPLING=f_HRTIM/2, N=8
6: Div4_N6: f_SAMPLING=f_HRTIM/4, N=6
7: Div4_N8: f_SAMPLING=f_HRTIM/4, N=8
8: Div8_N6: f_SAMPLING=f_HRTIM/8, N=6
9: Div8_N8: f_SAMPLING=f_HRTIM/8, N=8
10: Div16_N5: f_SAMPLING=f_HRTIM/16, N=5
11: Div16_N6: f_SAMPLING=f_HRTIM/16, N=6
12: Div16_N8: f_SAMPLING=f_HRTIM/16, N=8
13: Div32_N5: f_SAMPLING=f_HRTIM/32, N=5
14: Div32_N6: f_SAMPLING=f_HRTIM/32, N=6
15: Div32_N8: f_SAMPLING=f_HRTIM/32, N=8

FLT1LCK

Bit 7: FLT1LCK.

Allowed values:
0: Unlocked: Fault bits are read/write
1: Locked: Fault bits are read-only

FLT[2]E

Bit 8: FLT2E.

Allowed values:
0: Disabled: Fault input disabled
1: Enabled: Fault input enabled

FLT[2]P

Bit 9: FLT2P.

Allowed values:
0: ActiveLow: Fault input is active low
1: ActiveHigh: Fault input is active high

FLT[2]SRC

Bit 10: Fault 2 source.

Allowed values:
0: Input: Fault input is FLTx input pin
1: Internal: Fault input is FLTn_Int signal

FLT[2]F

Bits 11-14: FLT2F.

Allowed values:
0: Disabled: No filter, FLTx acts asynchronously
1: Div1_N2: f_SAMPLING=f_HRTIM, N=2
2: Div1_N4: f_SAMPLING=f_HRTIM, N=4
3: Div1_N8: f_SAMPLING=f_HRTIM, N=8
4: Div2_N6: f_SAMPLING=f_HRTIM/2, N=6
5: Div2_N8: f_SAMPLING=f_HRTIM/2, N=8
6: Div4_N6: f_SAMPLING=f_HRTIM/4, N=6
7: Div4_N8: f_SAMPLING=f_HRTIM/4, N=8
8: Div8_N6: f_SAMPLING=f_HRTIM/8, N=6
9: Div8_N8: f_SAMPLING=f_HRTIM/8, N=8
10: Div16_N5: f_SAMPLING=f_HRTIM/16, N=5
11: Div16_N6: f_SAMPLING=f_HRTIM/16, N=6
12: Div16_N8: f_SAMPLING=f_HRTIM/16, N=8
13: Div32_N5: f_SAMPLING=f_HRTIM/32, N=5
14: Div32_N6: f_SAMPLING=f_HRTIM/32, N=6
15: Div32_N8: f_SAMPLING=f_HRTIM/32, N=8

FLT2LCK

Bit 15: FLT2LCK.

Allowed values:
0: Unlocked: Fault bits are read/write
1: Locked: Fault bits are read-only

FLT[3]E

Bit 16: FLT3E.

Allowed values:
0: Disabled: Fault input disabled
1: Enabled: Fault input enabled

FLT[3]P

Bit 17: FLT3P.

Allowed values:
0: ActiveLow: Fault input is active low
1: ActiveHigh: Fault input is active high

FLT[3]SRC

Bit 18: Fault 3 source.

Allowed values:
0: Input: Fault input is FLTx input pin
1: Internal: Fault input is FLTn_Int signal

FLT[3]F

Bits 19-22: FLT3F.

Allowed values:
0: Disabled: No filter, FLTx acts asynchronously
1: Div1_N2: f_SAMPLING=f_HRTIM, N=2
2: Div1_N4: f_SAMPLING=f_HRTIM, N=4
3: Div1_N8: f_SAMPLING=f_HRTIM, N=8
4: Div2_N6: f_SAMPLING=f_HRTIM/2, N=6
5: Div2_N8: f_SAMPLING=f_HRTIM/2, N=8
6: Div4_N6: f_SAMPLING=f_HRTIM/4, N=6
7: Div4_N8: f_SAMPLING=f_HRTIM/4, N=8
8: Div8_N6: f_SAMPLING=f_HRTIM/8, N=6
9: Div8_N8: f_SAMPLING=f_HRTIM/8, N=8
10: Div16_N5: f_SAMPLING=f_HRTIM/16, N=5
11: Div16_N6: f_SAMPLING=f_HRTIM/16, N=6
12: Div16_N8: f_SAMPLING=f_HRTIM/16, N=8
13: Div32_N5: f_SAMPLING=f_HRTIM/32, N=5
14: Div32_N6: f_SAMPLING=f_HRTIM/32, N=6
15: Div32_N8: f_SAMPLING=f_HRTIM/32, N=8

FLT3LCK

Bit 23: FLT3LCK.

Allowed values:
0: Unlocked: Fault bits are read/write
1: Locked: Fault bits are read-only

FLT[4]E

Bit 24: FLT4E.

Allowed values:
0: Disabled: Fault input disabled
1: Enabled: Fault input enabled

FLT[4]P

Bit 25: FLT4P.

Allowed values:
0: ActiveLow: Fault input is active low
1: ActiveHigh: Fault input is active high

FLT[4]SRC

Bit 26: Fault 4 source.

Allowed values:
0: Input: Fault input is FLTx input pin
1: Internal: Fault input is FLTn_Int signal

FLT[4]F

Bits 27-30: FLT4F.

Allowed values:
0: Disabled: No filter, FLTx acts asynchronously
1: Div1_N2: f_SAMPLING=f_HRTIM, N=2
2: Div1_N4: f_SAMPLING=f_HRTIM, N=4
3: Div1_N8: f_SAMPLING=f_HRTIM, N=8
4: Div2_N6: f_SAMPLING=f_HRTIM/2, N=6
5: Div2_N8: f_SAMPLING=f_HRTIM/2, N=8
6: Div4_N6: f_SAMPLING=f_HRTIM/4, N=6
7: Div4_N8: f_SAMPLING=f_HRTIM/4, N=8
8: Div8_N6: f_SAMPLING=f_HRTIM/8, N=6
9: Div8_N8: f_SAMPLING=f_HRTIM/8, N=8
10: Div16_N5: f_SAMPLING=f_HRTIM/16, N=5
11: Div16_N6: f_SAMPLING=f_HRTIM/16, N=6
12: Div16_N8: f_SAMPLING=f_HRTIM/16, N=8
13: Div32_N5: f_SAMPLING=f_HRTIM/32, N=5
14: Div32_N6: f_SAMPLING=f_HRTIM/32, N=6
15: Div32_N8: f_SAMPLING=f_HRTIM/32, N=8

FLT4LCK

Bit 31: FLT4LCK.

Allowed values:
0: Unlocked: Fault bits are read/write
1: Locked: Fault bits are read-only

FLTINR2

HRTIM Fault Input Register 2

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLTSD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLT5LCK
rw 		FLT[5]F
rw 		FLT[5]SRC
rw 		FLT[5]P
rw 		FLT[5]E
rw
Toggle fields

FLT[5]E

Bit 0: FLT5E.

Allowed values:
0: Disabled: Fault input disabled
1: Enabled: Fault input enabled

FLT[5]P

Bit 1: FLT5P.

Allowed values:
0: ActiveLow: Fault input is active low
1: ActiveHigh: Fault input is active high

FLT[5]SRC

Bit 2: Fault 5 source.

Allowed values:
0: Input: Fault input is FLTx input pin
1: Internal: Fault input is FLTn_Int signal

FLT[5]F

Bits 3-6: FLT5F.

Allowed values:
0: Disabled: No filter, FLTx acts asynchronously
1: Div1_N2: f_SAMPLING=f_HRTIM, N=2
2: Div1_N4: f_SAMPLING=f_HRTIM, N=4
3: Div1_N8: f_SAMPLING=f_HRTIM, N=8
4: Div2_N6: f_SAMPLING=f_HRTIM/2, N=6
5: Div2_N8: f_SAMPLING=f_HRTIM/2, N=8
6: Div4_N6: f_SAMPLING=f_HRTIM/4, N=6
7: Div4_N8: f_SAMPLING=f_HRTIM/4, N=8
8: Div8_N6: f_SAMPLING=f_HRTIM/8, N=6
9: Div8_N8: f_SAMPLING=f_HRTIM/8, N=8
10: Div16_N5: f_SAMPLING=f_HRTIM/16, N=5
11: Div16_N6: f_SAMPLING=f_HRTIM/16, N=6
12: Div16_N8: f_SAMPLING=f_HRTIM/16, N=8
13: Div32_N5: f_SAMPLING=f_HRTIM/32, N=5
14: Div32_N6: f_SAMPLING=f_HRTIM/32, N=6
15: Div32_N8: f_SAMPLING=f_HRTIM/32, N=8

FLT5LCK

Bit 7: FLT5LCK.

Allowed values:
0: Unlocked: Fault bits are read/write
1: Locked: Fault bits are read-only

FLTSD

Bits 24-25: FLTSD.

Allowed values:
0: Div1: f_FLTS=f_HRTIM
1: Div2: f_FLTS=f_HRTIM/2
2: Div4: f_FLTS=f_HRTIM/4
3: Div8: f_FLTS=f_HRTIM/8

BDMUPR

BDMUPDR

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCMP4
rw 		MCMP3
rw 		MCMP2
rw 		MCMP1
rw 		MREP
rw 		MPER
rw 		MCNT
rw 		MDIER
rw 		MICR
rw 		MCR
rw
Toggle fields

MCR

Bit 0: MCR.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

MICR

Bit 1: MICR.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

MDIER

Bit 2: MDIER.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

MCNT

Bit 3: MCNT.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

MPER

Bit 4: MPER.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

MREP

Bit 5: MREP.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

MCMP1

Bit 6: MCMP1.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

MCMP2

Bit 7: MCMP2.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

MCMP3

Bit 8: MCMP3.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

MCMP4

Bit 9: MCMP4.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

BDTAUPR

Burst DMA Timerx update Register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

21/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLTR
rw 		OUTR
rw 		CHPR
rw 		RSTR
rw 		EEFR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EEFR1
rw 		RST2R
rw 		SET2R
rw 		RST1R
rw 		SET1R
rw 		_DTxR
rw 		CMP4
rw 		CMP3
rw 		CMP2
rw 		CMP1
rw 		REP
rw 		PER
rw 		CNT
rw 		DIER
rw 		ICR
rw 		CR
rw
Toggle fields

CR

Bit 0: HRTIM_TIMxCR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

ICR

Bit 1: HRTIM_TIMxICR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

DIER

Bit 2: HRTIM_TIMxDIER register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CNT

Bit 3: HRTIM_CNTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

PER

Bit 4: HRTIM_PERxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

REP

Bit 5: HRTIM_REPxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP1

Bit 6: HRTIM_CMP1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP2

Bit 7: HRTIM_CMP2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP3

Bit 8: HRTIM_CMP3xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP4

Bit 9: HRTIM_CMP4xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

_DTxR

Bit 10: HRTIM_DTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

SET1R

Bit 11: HRTIM_SET1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RST1R

Bit 12: HRTIM_RST1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

SET2R

Bit 13: HRTIM_SET2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RST2R

Bit 14: HRTIM_RST2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

EEFR1

Bit 15: HRTIM_EEFxR1 register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

EEFR2

Bit 16: HRTIM_EEFxR2 register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RSTR

Bit 17: HRTIM_RSTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CHPR

Bit 18: HRTIM_CHPxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

OUTR

Bit 19: HRTIM_OUTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

FLTR

Bit 20: HRTIM_FLTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

BDTBUPR

Burst DMA Timerx update Register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

21/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLTR
rw 		OUTR
rw 		CHPR
rw 		RSTR
rw 		EEFR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EEFR1
rw 		RST2R
rw 		SET2R
rw 		RST1R
rw 		SET1R
rw 		_DTxR
rw 		CMP4
rw 		CMP3
rw 		CMP2
rw 		CMP1
rw 		REP
rw 		PER
rw 		CNT
rw 		DIER
rw 		ICR
rw 		CR
rw
Toggle fields

CR

Bit 0: HRTIM_TIMxCR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

ICR

Bit 1: HRTIM_TIMxICR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

DIER

Bit 2: HRTIM_TIMxDIER register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CNT

Bit 3: HRTIM_CNTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

PER

Bit 4: HRTIM_PERxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

REP

Bit 5: HRTIM_REPxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP1

Bit 6: HRTIM_CMP1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP2

Bit 7: HRTIM_CMP2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP3

Bit 8: HRTIM_CMP3xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP4

Bit 9: HRTIM_CMP4xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

_DTxR

Bit 10: HRTIM_DTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

SET1R

Bit 11: HRTIM_SET1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RST1R

Bit 12: HRTIM_RST1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

SET2R

Bit 13: HRTIM_SET2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RST2R

Bit 14: HRTIM_RST2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

EEFR1

Bit 15: HRTIM_EEFxR1 register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

EEFR2

Bit 16: HRTIM_EEFxR2 register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RSTR

Bit 17: HRTIM_RSTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CHPR

Bit 18: HRTIM_CHPxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

OUTR

Bit 19: HRTIM_OUTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

FLTR

Bit 20: HRTIM_FLTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

BDTCUPR

Burst DMA Timerx update Register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

21/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLTR
rw 		OUTR
rw 		CHPR
rw 		RSTR
rw 		EEFR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EEFR1
rw 		RST2R
rw 		SET2R
rw 		RST1R
rw 		SET1R
rw 		_DTxR
rw 		CMP4
rw 		CMP3
rw 		CMP2
rw 		CMP1
rw 		REP
rw 		PER
rw 		CNT
rw 		DIER
rw 		ICR
rw 		CR
rw
Toggle fields

CR

Bit 0: HRTIM_TIMxCR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

ICR

Bit 1: HRTIM_TIMxICR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

DIER

Bit 2: HRTIM_TIMxDIER register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CNT

Bit 3: HRTIM_CNTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

PER

Bit 4: HRTIM_PERxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

REP

Bit 5: HRTIM_REPxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP1

Bit 6: HRTIM_CMP1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP2

Bit 7: HRTIM_CMP2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP3

Bit 8: HRTIM_CMP3xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP4

Bit 9: HRTIM_CMP4xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

_DTxR

Bit 10: HRTIM_DTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

SET1R

Bit 11: HRTIM_SET1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RST1R

Bit 12: HRTIM_RST1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

SET2R

Bit 13: HRTIM_SET2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RST2R

Bit 14: HRTIM_RST2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

EEFR1

Bit 15: HRTIM_EEFxR1 register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

EEFR2

Bit 16: HRTIM_EEFxR2 register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RSTR

Bit 17: HRTIM_RSTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CHPR

Bit 18: HRTIM_CHPxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

OUTR

Bit 19: HRTIM_OUTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

FLTR

Bit 20: HRTIM_FLTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

BDTDUPR

Burst DMA Timerx update Register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

21/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLTR
rw 		OUTR
rw 		CHPR
rw 		RSTR
rw 		EEFR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EEFR1
rw 		RST2R
rw 		SET2R
rw 		RST1R
rw 		SET1R
rw 		_DTxR
rw 		CMP4
rw 		CMP3
rw 		CMP2
rw 		CMP1
rw 		REP
rw 		PER
rw 		CNT
rw 		DIER
rw 		ICR
rw 		CR
rw
Toggle fields

CR

Bit 0: HRTIM_TIMxCR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

ICR

Bit 1: HRTIM_TIMxICR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

DIER

Bit 2: HRTIM_TIMxDIER register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CNT

Bit 3: HRTIM_CNTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

PER

Bit 4: HRTIM_PERxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

REP

Bit 5: HRTIM_REPxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP1

Bit 6: HRTIM_CMP1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP2

Bit 7: HRTIM_CMP2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP3

Bit 8: HRTIM_CMP3xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP4

Bit 9: HRTIM_CMP4xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

_DTxR

Bit 10: HRTIM_DTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

SET1R

Bit 11: HRTIM_SET1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RST1R

Bit 12: HRTIM_RST1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

SET2R

Bit 13: HRTIM_SET2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RST2R

Bit 14: HRTIM_RST2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

EEFR1

Bit 15: HRTIM_EEFxR1 register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

EEFR2

Bit 16: HRTIM_EEFxR2 register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RSTR

Bit 17: HRTIM_RSTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CHPR

Bit 18: HRTIM_CHPxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

OUTR

Bit 19: HRTIM_OUTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

FLTR

Bit 20: HRTIM_FLTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

BDTEUPR

Burst DMA Timerx update Register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

21/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLTR
rw 		OUTR
rw 		CHPR
rw 		RSTR
rw 		EEFR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EEFR1
rw 		RST2R
rw 		SET2R
rw 		RST1R
rw 		SET1R
rw 		_DTxR
rw 		CMP4
rw 		CMP3
rw 		CMP2
rw 		CMP1
rw 		REP
rw 		PER
rw 		CNT
rw 		DIER
rw 		ICR
rw 		CR
rw
Toggle fields

CR

Bit 0: HRTIM_TIMxCR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

ICR

Bit 1: HRTIM_TIMxICR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

DIER

Bit 2: HRTIM_TIMxDIER register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CNT

Bit 3: HRTIM_CNTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

PER

Bit 4: HRTIM_PERxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

REP

Bit 5: HRTIM_REPxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP1

Bit 6: HRTIM_CMP1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP2

Bit 7: HRTIM_CMP2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP3

Bit 8: HRTIM_CMP3xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP4

Bit 9: HRTIM_CMP4xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

_DTxR

Bit 10: HRTIM_DTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

SET1R

Bit 11: HRTIM_SET1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RST1R

Bit 12: HRTIM_RST1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

SET2R

Bit 13: HRTIM_SET2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RST2R

Bit 14: HRTIM_RST2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

EEFR1

Bit 15: HRTIM_EEFxR1 register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

EEFR2

Bit 16: HRTIM_EEFxR2 register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RSTR

Bit 17: HRTIM_RSTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CHPR

Bit 18: HRTIM_CHPxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

OUTR

Bit 19: HRTIM_OUTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

FLTR

Bit 20: HRTIM_FLTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

BDMADR

Burst DMA Data Register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BDMADR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BDMADR
rw
Toggle fields

BDMADR

Bits 0-31: Burst DMA Data register.

Allowed values: 0x0-0xffffffff

HRTIM_Master

0x40017400: High Resolution Timer: Master Timers

42/54 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 ISR
0x8 ICR
0xc DIER
0x10 CNTR
0x14 PERR
0x18 REPR
0x1c CMP1R
0x24 CMP2R
0x28 CMP3R
0x2c CMP4R
Toggle registers

CR

Master Timer Control Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRSTDMA
rw 		MREPU
rw 		PREEN
rw 		DACSYNC
rw 		T[E]CEN
rw 		T[D]CEN
rw 		T[C]CEN
rw 		T[B]CEN
rw 		T[A]CEN
rw 		MCEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNCSRC
rw 		SYNCOUT
rw 		SYNCSTRT
rw 		SYNCRST
rw 		SYNCIN
rw 		HALF
rw 		RETRIG
rw 		CONT
rw 		CKPSC
rw
Toggle fields

CKPSC

Bits 0-2: HRTIM Master Clock prescaler.

Allowed values: 0x0-0x7

CONT

Bit 3: Master Continuous mode.

Allowed values:
0: SingleShot: The timer operates in single-shot mode and stops when it reaches the MPER value
1: Continuous: The timer operates in continuous (free-running) mode and rolls over to zero when it reaches the MPER value

RETRIG

Bit 4: Master Re-triggerable mode.

Allowed values:
0: Disabled: The timer is not re-triggerable: a counter reset can be done only if the counter is stopped
1: Enabled: The timer is retriggerable: a counter reset is done whatever the counter state

HALF

Bit 5: Half mode enable.

Allowed values:
0: Disabled: Half mode disabled
1: Enabled: Half mode enabled

SYNCIN

Bits 8-9: ynchronization input.

Allowed values:
0: Disabled: Disabled. HRTIM is not synchronized and runs in standalone mode
2: Internal: Internal event: the HRTIM is synchronized with the on-chip timer
3: External: External event: a positive pulse on HRTIM_SCIN input triggers the HRTIM

SYNCRST

Bit 10: Synchronization Resets Master.

Allowed values:
0: Disabled: No effect on the master timer
1: Reset: A synchroniation input event resets the master timer

SYNCSTRT

Bit 11: Synchronization Starts Master.

Allowed values:
0: Disabled: No effect on the master timer
1: Start: A synchroniation input event starts the master timer

SYNCOUT

Bits 12-13: Synchronization output.

Allowed values:
0: Disabled: Disabled
2: PositivePulse: Positive pulse on SCOUT output (16x f_HRTIM clock cycles)
3: NegativePulse: Negative pulse on SCOUT output (16x f_HRTIM clock cycles)

SYNCSRC

Bits 14-15: Synchronization source.

Allowed values:
0: MasterStart: Master timer Start
1: MasterCompare1: Master timer Compare 1 event
2: TimerAStart: Timer A start/reset
3: TimerACompare1: Timer A Compare 1 event

MCEN

Bit 16: Master Counter enable.

Allowed values:
0: Disabled: Master timer counter disabled
1: Enabled: Master timer counter enabled

T[A]CEN

Bit 17: Timer A counter enable.

Allowed values:
0: Disabled: Timer counter disabled
1: Enabled: Timer counter enabled

T[B]CEN

Bit 18: Timer B counter enable.

Allowed values:
0: Disabled: Timer counter disabled
1: Enabled: Timer counter enabled

T[C]CEN

Bit 19: Timer C counter enable.

Allowed values:
0: Disabled: Timer counter disabled
1: Enabled: Timer counter enabled

T[D]CEN

Bit 20: Timer D counter enable.

Allowed values:
0: Disabled: Timer counter disabled
1: Enabled: Timer counter enabled

T[E]CEN

Bit 21: Timer E counter enable.

Allowed values:
0: Disabled: Timer counter disabled
1: Enabled: Timer counter enabled

DACSYNC

Bits 25-26: AC Synchronization.

Allowed values:
0: Disabled: No DAC trigger generated
1: DACSync1: Trigger generated on DACSync1
2: DACSync2: Trigger generated on DACSync2
3: DACSync3: Trigger generated on DACSync3

PREEN

Bit 27: Preload enable.

Allowed values:
0: Disabled: Preload disabled: the write access is directly done into the active register
1: Enabled: Preload enabled: the write access is done into the preload register

MREPU

Bit 29: Master Timer Repetition update.

Allowed values:
0: Disabled: Update on repetition disabled
1: Enabled: Update on repetition enabled

BRSTDMA

Bits 30-31: Burst DMA Update.

Allowed values:
0: Independent: Update done independently from the DMA burst transfer completion
1: Completion: Update done when the DMA burst transfer is completed
2: Rollover: Update done on master timer roll-over following a DMA burst transfer completion

ISR

Master Timer Interrupt Status Register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPD
r 		SYNC
r 		REP
r 		CMP[4]
r 		CMP[3]
r 		CMP[2]
r 		CMP[1]
r
Toggle fields

CMP[1]

Bit 0: Master Compare 1 Interrupt Flag.

Allowed values:
0: NoEvent: No master compare interrupt occurred
1: Event: Master compare interrupt occurred

CMP[2]

Bit 1: Master Compare 2 Interrupt Flag.

Allowed values:
0: NoEvent: No master compare interrupt occurred
1: Event: Master compare interrupt occurred

CMP[3]

Bit 2: Master Compare 3 Interrupt Flag.

Allowed values:
0: NoEvent: No master compare interrupt occurred
1: Event: Master compare interrupt occurred

CMP[4]

Bit 3: Master Compare 4 Interrupt Flag.

Allowed values:
0: NoEvent: No master compare interrupt occurred
1: Event: Master compare interrupt occurred

REP

Bit 4: Master Repetition Interrupt Flag.

Allowed values:
0: NoEvent: No master repetition interrupt occurred
1: Event: Master repetition interrupt occurred

SYNC

Bit 5: Sync Input Interrupt Flag.

Allowed values:
0: NoEvent: No sync input interrupt occurred
1: Event: Sync input interrupt occurred

UPD

Bit 6: Master Update Interrupt Flag.

Allowed values:
0: NoEvent: No master update interrupt occurred
1: Event: Master update interrupt occurred

ICR

Master Timer Interrupt Clear Register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPDC
w 		SYNCC
w 		REPC
w 		CMP[4]C
w 		CMP[3]C
w 		CMP[2]C
w 		CMP[1]C
w
Toggle fields

CMP[1]C

Bit 0: Master Compare 1 Interrupt flag clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CMP[2]C

Bit 1: Master Compare 2 Interrupt flag clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CMP[3]C

Bit 2: Master Compare 3 Interrupt flag clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CMP[4]C

Bit 3: Master Compare 4 Interrupt flag clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

REPC

Bit 4: Repetition Interrupt flag clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

SYNCC

Bit 5: Sync Input Interrupt flag clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

UPDC

Bit 6: Master update Interrupt flag clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

DIER

MDIER4

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

2/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPDDE
rw 		SYNCDE
rw 		REPDE
rw 		CMP[4]DE
rw 		CMP[3]DE
rw 		CMP[2]DE
rw 		CMP[1]DE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPDIE
rw 		SYNCIE
rw 		REPIE
rw 		CMP[4]IE
rw 		CMP[3]IE
rw 		CMP[2]IE
rw 		CMP[1]IE
rw
Toggle fields

CMP[1]IE

Bit 0: MCMP1IE.

CMP[2]IE

Bit 1: MCMP2IE.

CMP[3]IE

Bit 2: MCMP3IE.

CMP[4]IE

Bit 3: MCMP4IE.

REPIE

Bit 4: MREPIE.

SYNCIE

Bit 5: SYNCIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

UPDIE

Bit 6: MUPDIE.

CMP[1]DE

Bit 16: MCMP1DE.

CMP[2]DE

Bit 17: MCMP2DE.

CMP[3]DE

Bit 18: MCMP3DE.

CMP[4]DE

Bit 19: MCMP4DE.

REPDE

Bit 20: MREPDE.

SYNCDE

Bit 21: SYNCDE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

UPDDE

Bit 22: MUPDDE.

CNTR

Master Timer Counter Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: Counter value.

Allowed values: 0x0-0xffff

PERR

Master Timer Period Register

Offset: 0x14, size: 32, reset: 0x0000FFFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PER
rw
Toggle fields

PER

Bits 0-15: Master Timer Period value.

Allowed values: 0x0-0xffff

REPR

Master Timer Repetition Register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Master Timer Repetition counter value.

Allowed values: 0x0-0xff

CMP1R

Master Timer Compare 1 Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CMP2R

Master Timer Compare 2 Register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CMP3R

Master Timer Compare 3 Register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CMP4R

Master Timer Compare 4 Register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

HRTIM_TIMA

0x40017480: High Resolution Timer: TIMA

359/359 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 ISR
0x8 ICR
0xc DIER
0x10 CNTR
0x14 PERR
0x18 REPR
0x1c CMP1R
0x20 CMP1CR
0x24 CMP2R
0x28 CMP3R
0x2c CMP4R
0x30 CPT1R
0x34 CPT2R
0x38 DTR
0x3c SET1R
0x40 RST1R
0x44 SET2R
0x48 RST2R
0x4c EEFR1
0x50 EEFR2
0x54 RSTR
0x58 CHPR
0x5c CPT1CR
0x60 CPT2CR
0x64 OUTR
0x68 FLTR
Toggle registers

CR

Timerx Control Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPDGAT
rw 		PREEN
rw 		DACSYNC
rw 		MSTU
rw 		TEU
rw 		TDU
rw 		TCU
rw 		TBU
rw 		TRSTU
rw 		TREPU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DELCMP4
rw 		DELCMP2
rw 		SYNCSTRT
rw 		SYNCRST
rw 		PSHPLL
rw 		HALF
rw 		RETRIG
rw 		CONT
rw 		CKPSC
rw
Toggle fields

CKPSC

Bits 0-2: HRTIM Timer x Clock prescaler.

Allowed values: 0x0-0x7

CONT

Bit 3: Continuous mode.

Allowed values:
0: SingleShot: The timer operates in single-shot mode and stops when it reaches the TIMxPER value
1: Continuous: The timer operates in continuous (free-running) mode and rolls over to zero when it reaches the TIMxPER value

RETRIG

Bit 4: Re-triggerable mode.

Allowed values:
0: Disabled: The timer is not re-triggerable: a counter reset can be done only if the counter is stopped
1: Enabled: The timer is retriggerable: a counter reset is done whatever the counter state

HALF

Bit 5: Half mode enable.

Allowed values:
0: Disabled: Half mode disabled
1: Enabled: Half mode enabled

PSHPLL

Bit 6: Push-Pull mode enable.

Allowed values:
0: Disabled: Push-pull mode disabled
1: Enabled: Push-pull mode enabled

SYNCRST

Bit 10: Synchronization Resets Timer x.

Allowed values:
0: Disabled: Synchronization event has no effect on Timer x
1: Reset: Synchronization event resets Timer x

SYNCSTRT

Bit 11: Synchronization Starts Timer x.

Allowed values:
0: Disabled: Synchronization event has no effect on Timer x
1: Start: Synchronization event starts Timer x

DELCMP2

Bits 12-13: Delayed CMP2 mode.

Allowed values:
0: Standard: CMP2 register is always active (standard compare mode)
1: Capture1: CMP2 is recomputed and is active following a capture 1 event
2: Capture1_Compare1: CMP2 is recomputed and is active following a capture 1 event or a Compare 1 match
3: Capture1_Compare3: CMP2 is recomputed and is active following a capture 1 event or a Compare 3 match

DELCMP4

Bits 14-15: Delayed CMP4 mode.

Allowed values:
0: Standard: CMP4 register is always active (standard compare mode)
1: Capture2: CMP4 is recomputed and is active following a capture 2 event
2: Capture2_Compare1: CMP4 is recomputed and is active following a capture 2 event or a Compare 1 match
3: Capture_Compare3: CMP4 is recomputed and is active following a capture event or a Compare 3 match

TREPU

Bit 17: Timer x Repetition update.

Allowed values:
0: Disabled: Update by timer x repetition disabled
1: Enabled: Update by timer x repetition enabled

TRSTU

Bit 18: Timerx reset update.

Allowed values:
0: Disabled: Update by timer x reset/roll-over disabled
1: Enabled: Update by timer x reset/roll-over enabled

TBU

Bit 20: TBU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

TCU

Bit 21: TCU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

TDU

Bit 22: TDU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

TEU

Bit 23: TEU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

MSTU

Bit 24: Master Timer update.

Allowed values:
0: Disabled: Update by master timer disabled
1: Enabled: Update by master timer enabled

DACSYNC

Bits 25-26: AC Synchronization.

Allowed values:
0: Disabled: No DAC trigger generated
1: DACSync1: Trigger generated on DACSync1
2: DACSync2: Trigger generated on DACSync2
3: DACSync3: Trigger generated on DACSync3

PREEN

Bit 27: Preload enable.

Allowed values:
0: Disabled: Preload disabled: the write access is directly done into the active register
1: Enabled: Preload enabled: the write access is done into the preload register

UPDGAT

Bits 28-31: Update Gating.

Allowed values:
0: Independent: Update occurs independently from the DMA burst transfer
1: DMABurst: Update occurs when the DMA burst transfer is completed
2: DMABurst_Update: Update occurs on the update event following DMA burst transfer completion
3: Input1: Update occurs on a rising edge of HRTIM update enable input 1
4: Input2: Update occurs on a rising edge of HRTIM update enable input 2
5: Input3: Update occurs on a rising edge of HRTIM update enable input 3
6: Input1_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 1
7: Input2_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 2
8: Input3_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 3

ISR

Timerx Interrupt Status Register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
O2CPY
r 		O1CPY
r 		O2STAT
r 		O1STAT
r 		IPPSTAT
r 		CPPSTAT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYPRT
r 		RST
r 		RST2
r 		SET[2]
r 		RST1
r 		SET[1]
r 		CPT[2]
r 		CPT[1]
r 		UPD
r 		REP
r 		CMP[4]
r 		CMP[3]
r 		CMP[2]
r 		CMP[1]
r
Toggle fields

CMP[1]

Bit 0: Compare 1 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

CMP[2]

Bit 1: Compare 2 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

CMP[3]

Bit 2: Compare 3 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

CMP[4]

Bit 3: Compare 4 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

REP

Bit 4: Repetition Interrupt Flag.

Allowed values:
0: NoEvent: No timer repetition interrupt occurred
1: Event: Timer repetition interrupt occurred

UPD

Bit 6: Update Interrupt Flag.

Allowed values:
0: NoEvent: No timer update interrupt occurred
1: Event: Timer update interrupt occurred

CPT[1]

Bit 7: Capture1 Interrupt Flag.

Allowed values:
0: NoEvent: No timer x capture reset interrupt occurred
1: Event: Timer x capture reset interrupt occurred

CPT[2]

Bit 8: Capture2 Interrupt Flag.

Allowed values:
0: NoEvent: No timer x capture reset interrupt occurred
1: Event: Timer x capture reset interrupt occurred

SET[1]

Bit 9: Output 1 Set Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output set interrupt occurred
1: Event: Tx output set interrupt occurred

RST1

Bit 10: Output 1 Reset Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output reset interrupt occurred
1: Event: Tx output reset interrupt occurred

SET[2]

Bit 11: Output 2 Set Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output set interrupt occurred
1: Event: Tx output set interrupt occurred

RST2

Bit 12: Output 2 Reset Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output reset interrupt occurred
1: Event: Tx output reset interrupt occurred

RST

Bit 13: Reset Interrupt Flag.

Allowed values:
0: NoEvent: No TIMx counter reset/roll-over interrupt occurred
1: Event: TIMx counter reset/roll-over interrupt occurred

DLYPRT

Bit 14: Delayed Protection Flag.

Allowed values:
0: Inactive: Not in delayed idle or balanced idle mode
1: Active: Delayed idle or balanced idle mode entry

CPPSTAT

Bit 16: Current Push Pull Status.

Allowed values:
0: Output1Active: Signal applied on output 1 and output 2 forced inactive
1: Output2Active: Signal applied on output 2 and output 1 forced inactive

IPPSTAT

Bit 17: Idle Push Pull Status.

Allowed values:
0: Output1Active: Protection occurred when the output 1 was active and output 2 forced inactive
1: Output2Active: Protection occurred when the output 2 was active and output 1 forced inactive

O1STAT

Bit 18: Output 1 State.

Allowed values:
0: Inactive: Output was inactive
1: Active: Output was active

O2STAT

Bit 19: Output 2 State.

Allowed values:
0: Inactive: Output was inactive
1: Active: Output was active

O1CPY

Bit 20: Output 1 Copy.

Allowed values:
0: Inactive: Output is inactive
1: Active: Output is active

O2CPY

Bit 21: Output 2 Copy.

Allowed values:
0: Inactive: Output is inactive
1: Active: Output is active

ICR

Timerx Interrupt Clear Register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

14/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYPRTC
w 		RSTC
w 		RST2C
w 		SET[2]C
w 		RST1C
w 		SET[1]C
w 		CPT[2]C
w 		CPT[1]C
w 		UPDC
w 		REPC
w 		CMP[4]C
w 		CMP[3]C
w 		CMP[2]C
w 		CMP[1]C
w
Toggle fields

CMP[1]C

Bit 0: Compare 1 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CMP[2]C

Bit 1: Compare 2 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CMP[3]C

Bit 2: Compare 3 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CMP[4]C

Bit 3: Compare 4 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

REPC

Bit 4: Repetition Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

UPDC

Bit 6: Update Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CPT[1]C

Bit 7: Capture1 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CPT[2]C

Bit 8: Capture2 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

SET[1]C

Bit 9: Output 1 Set flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

RST1C

Bit 10: Output 1 Reset flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

SET[2]C

Bit 11: Output 2 Set flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

RST2C

Bit 12: Output 2 Reset flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

RSTC

Bit 13: Reset Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

DLYPRTC

Bit 14: Delayed Protection Flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

DIER

TIMxDIER5

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLYPRTDE
rw 		RSTDE
rw 		RST2DE
rw 		SET[2]DE
rw 		RST1DE
rw 		SET[1]DE
rw 		CPT[2]DE
rw 		CPT[1]DE
rw 		UPDDE
rw 		REPDE
rw 		CMP[4]DE
rw 		CMP[3]DE
rw 		CMP[2]DE
rw 		CMP[1]DE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYPRTIE
rw 		RSTIE
rw 		RST2IE
rw 		SET[2]IE
rw 		RST1IE
rw 		SET[1]IE
rw 		CPT[2]IE
rw 		CPT[1]IE
rw 		UPDIE
rw 		REPIE
rw 		CMP[4]IE
rw 		CMP[3]IE
rw 		CMP[2]IE
rw 		CMP[1]IE
rw
Toggle fields

CMP[1]IE

Bit 0: CMP1IE.

Allowed values:
0: Disabled: Compare interrupt disabled
1: Enabled: Compare interrupt enabled

CMP[2]IE

Bit 1: CMP2IE.

Allowed values:
0: Disabled: Compare interrupt disabled
1: Enabled: Compare interrupt enabled

CMP[3]IE

Bit 2: CMP3IE.

Allowed values:
0: Disabled: Compare interrupt disabled
1: Enabled: Compare interrupt enabled

CMP[4]IE

Bit 3: CMP4IE.

Allowed values:
0: Disabled: Compare interrupt disabled
1: Enabled: Compare interrupt enabled

REPIE

Bit 4: REPIE.

Allowed values:
0: Disabled: Repetition interrupt disabled
1: Enabled: Repetition interrupt enabled

UPDIE

Bit 6: UPDIE.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CPT[1]IE

Bit 7: CPT1IE.

Allowed values:
0: Disabled: Capture interrupt disabled
1: Enabled: Capture interrupt enabled

CPT[2]IE

Bit 8: CPT2IE.

Allowed values:
0: Disabled: Capture interrupt disabled
1: Enabled: Capture interrupt enabled

SET[1]IE

Bit 9: Output 1 set interrupt enable.

Allowed values:
0: Disabled: Tx output set interrupt disabled
1: Enabled: Tx output set interrupt enabled

RST1IE

Bit 10: RSTx1IE.

Allowed values:
0: Disabled: Tx output reset interrupt disabled
1: Enabled: Tx output reset interrupt enabled

SET[2]IE

Bit 11: Output 2 set interrupt enable.

Allowed values:
0: Disabled: Tx output set interrupt disabled
1: Enabled: Tx output set interrupt enabled

RST2IE

Bit 12: RSTx2IE.

Allowed values:
0: Disabled: Tx output reset interrupt disabled
1: Enabled: Tx output reset interrupt enabled

RSTIE

Bit 13: RSTIE.

Allowed values:
0: Disabled: Timer x counter/reset roll-over interrupt disabled
1: Enabled: Timer x counter/reset roll-over interrupt enabled

DLYPRTIE

Bit 14: DLYPRTIE.

Allowed values:
0: Disabled: Delayed protection interrupt disabled
1: Enabled: Delayed protection interrupt enabled

CMP[1]DE

Bit 16: CMP1DE.

Allowed values:
0: Disabled: Compare DMA request disabled
1: Enabled: Compare DMA request enabled

CMP[2]DE

Bit 17: CMP2DE.

Allowed values:
0: Disabled: Compare DMA request disabled
1: Enabled: Compare DMA request enabled

CMP[3]DE

Bit 18: CMP3DE.

Allowed values:
0: Disabled: Compare DMA request disabled
1: Enabled: Compare DMA request enabled

CMP[4]DE

Bit 19: CMP4DE.

Allowed values:
0: Disabled: Compare DMA request disabled
1: Enabled: Compare DMA request enabled

REPDE

Bit 20: REPDE.

Allowed values:
0: Disabled: Repetition DMA request disabled
1: Enabled: Repetition DMA request enabled

UPDDE

Bit 22: UPDDE.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CPT[1]DE

Bit 23: CPT1DE.

Allowed values:
0: Disabled: Capture DMA request disabled
1: Enabled: Capture DMA request enabled

CPT[2]DE

Bit 24: CPT2DE.

Allowed values:
0: Disabled: Capture DMA request disabled
1: Enabled: Capture DMA request enabled

SET[1]DE

Bit 25: Output 1 set DMA request enable.

Allowed values:
0: Disabled: Tx output set DMA request disabled
1: Enabled: Tx output set DMA request enabled

RST1DE

Bit 26: RSTx1DE.

Allowed values:
0: Disabled: Tx output reset DMA request disabled
1: Enabled: Tx output reset DMA request enabled

SET[2]DE

Bit 27: Output 2 set DMA request enable.

Allowed values:
0: Disabled: Tx output set DMA request disabled
1: Enabled: Tx output set DMA request enabled

RST2DE

Bit 28: RSTx2DE.

Allowed values:
0: Disabled: Tx output reset DMA request disabled
1: Enabled: Tx output reset DMA request enabled

RSTDE

Bit 29: RSTDE.

Allowed values:
0: Disabled: Timer x counter reset/roll-over DMA request disabled
1: Enabled: Timer x counter reset/roll-over DMA request enabled

DLYPRTDE

Bit 30: DLYPRTDE.

Allowed values:
0: Disabled: Delayed protection DMA request disabled
1: Enabled: Delayed protection DMA request enabled

CNTR

Timerx Counter Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: Counter value.

Allowed values: 0x0-0xffff

PERR

Timerx Period Register

Offset: 0x14, size: 32, reset: 0x0000FFFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PER
rw
Toggle fields

PER

Bits 0-15: Master Timer Period value.

Allowed values: 0x0-0xffff

REPR

Timerx Repetition Register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Master Timer Repetition counter value.

Allowed values: 0x0-0xff

CMP1R

Timerx Compare 1 Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CMP1CR

Timerx Compare 1 Compound Register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP1
rw
Toggle fields

CMP1

Bits 0-15: Timerx Compare 1 value.

Allowed values: 0x0-0xffff

REP

Bits 16-23: Timerx Repetition value (aliased from HRTIM_REPx register).

Allowed values: 0x0-0xff

CMP2R

Timerx Compare 2 Register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CMP3R

Timerx Compare 3 Register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CMP4R

Timerx Compare 4 Register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CPT1R

Timerx Capture 1 Register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPT
r
Toggle fields

CPT

Bits 0-15: Timerx Capture 1 value.

Allowed values: 0x0-0xffff

CPT2R

Timerx Capture 2 Register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPT
r
Toggle fields

CPT

Bits 0-15: Timerx Capture 1 value.

Allowed values: 0x0-0xffff

DTR

Timerx Deadtime Register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTFLK
rw 		DTFSLK
rw 		SDTF
rw 		DTF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTRLK
rw 		DTRSLK
rw 		DTPRSC
rw 		SDTR
rw 		DTR
rw
Toggle fields

DTR

Bits 0-8: Deadtime Rising value.

Allowed values: 0x0-0x1ff

SDTR

Bit 9: Sign Deadtime Rising value.

Allowed values:
0: Positive: Positive deadtime on rising edge
1: Negative: Negative deadtime on rising edge

DTPRSC

Bits 10-12: Deadtime Prescaler.

Allowed values: 0x0-0x7

DTRSLK

Bit 14: Deadtime Rising Sign Lock.

Allowed values:
0: Unlocked: Deadtime rising sign is writable
1: Locked: Deadtime rising sign is read-only

DTRLK

Bit 15: Deadtime Rising Lock.

Allowed values:
0: Unlocked: Deadtime rising value and sign is writable
1: Locked: Deadtime rising value and sign is read-only

DTF

Bits 16-24: Deadtime Falling value.

Allowed values: 0x0-0x1ff

SDTF

Bit 25: Sign Deadtime Falling value.

Allowed values:
0: Positive: Positive deadtime on falling edge
1: Negative: Negative deadtime on falling edge

DTFSLK

Bit 30: Deadtime Falling Sign Lock.

Allowed values:
0: Unlocked: Deadtime falling sign is writable
1: Locked: Deadtime falling sign is read-only

DTFLK

Bit 31: Deadtime Falling Lock.

Allowed values:
0: Unlocked: Deadtime falling value and sign is writable
1: Locked: Deadtime falling value and sign is read-only

SET1R

Timerx Output1 Set Register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPDATE
rw 		EXTEVNT[10]
rw 		EXTEVNT[9]
rw 		EXTEVNT[8]
rw 		EXTEVNT[7]
rw 		EXTEVNT[6]
rw 		EXTEVNT[5]
rw 		EXTEVNT[4]
rw 		EXTEVNT[3]
rw 		EXTEVNT[2]
rw 		EXTEVNT[1]
rw 		TIMECMP4
rw 		TIMECMP3
rw 		TIMDCMP2
rw 		TIMDCMP1
rw 		TIMCCMP3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMCCMP2
rw 		TIMBCMP4
rw 		TIMBCMP2
rw 		TIMBCMP1
rw 		MSTCMP[4]
rw 		MSTCMP[3]
rw 		MSTCMP[2]
rw 		MSTCMP[1]
rw 		MSTPER
rw 		CMP[4]
rw 		CMP[3]
rw 		CMP[2]
rw 		CMP[1]
rw 		PER
rw 		RESYNC
rw 		SST
rw
Toggle fields

SST

Bit 0: Software Set trigger.

Allowed values:
0: NoEffect: No effect
1: SetActive: Force output to its active state

RESYNC

Bit 1: Timer A resynchronizaton.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetActive: Timer reset event coming solely from software or SYNC input event forces the output to its active state

PER

Bit 2: Timer A Period.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetActive: Timer period event forces the output to its active state

CMP[1]

Bit 3: Timer A compare 1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[2]

Bit 4: Timer A compare 2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[3]

Bit 5: Timer A compare 3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[4]

Bit 6: Timer A compare 4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

MSTPER

Bit 7: Master Period.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetActive: Master timer counter roll-over/reset forces the output to its active state

MSTCMP[1]

Bit 8: Master Compare 1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[2]

Bit 9: Master Compare 2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[3]

Bit 10: Master Compare 3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[4]

Bit 11: Master Compare 4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

TIMBCMP1

Bit 12: Timer B Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMBCMP2

Bit 13: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMBCMP4

Bit 14: Timer B Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMCCMP2

Bit 15: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMCCMP3

Bit 16: Timer C Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMDCMP1

Bit 17: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMDCMP2

Bit 18: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMECMP3

Bit 19: Timer E Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMECMP4

Bit 20: Timer E Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

EXTEVNT[1]

Bit 21: External Event 1.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[2]

Bit 22: External Event 2.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[3]

Bit 23: External Event 3.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[4]

Bit 24: External Event 4.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[5]

Bit 25: External Event 5.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[6]

Bit 26: External Event 6.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[7]

Bit 27: External Event 7.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[8]

Bit 28: External Event 8.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[9]

Bit 29: External Event 9.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[10]

Bit 30: External Event 10.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

UPDATE

Bit 31: Registers update (transfer preload to active).

Allowed values:
0: NoEffect: Register update event has no effect
1: SetActive: Register update event forces the output to its active state

RST1R

Timerx Output1 Reset Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPDATE
rw 		EXTEVNT[10]
rw 		EXTEVNT[9]
rw 		EXTEVNT[8]
rw 		EXTEVNT[7]
rw 		EXTEVNT[6]
rw 		EXTEVNT[5]
rw 		EXTEVNT[4]
rw 		EXTEVNT[3]
rw 		EXTEVNT[2]
rw 		EXTEVNT[1]
rw 		TIMECMP4
rw 		TIMECMP3
rw 		TIMDCMP2
rw 		TIMDCMP1
rw 		TIMCCMP3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMCCMP2
rw 		TIMBCMP4
rw 		TIMBCMP2
rw 		TIMBCMP1
rw 		MSTCMP[4]
rw 		MSTCMP[3]
rw 		MSTCMP[2]
rw 		MSTCMP[1]
rw 		MSTPER
rw 		CMP[4]
rw 		CMP[3]
rw 		CMP[2]
rw 		CMP[1]
rw 		PER
rw 		RESYNC
rw 		SRT
rw
Toggle fields

SRT

Bit 0: SRT.

Allowed values:
0: NoEffect: No effect
1: SetInactive: Force output to its inactive state

RESYNC

Bit 1: RESYNC.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetInactive: Timer reset event coming solely from software or SYNC input event forces the output to its inactive state

PER

Bit 2: PER.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetInactive: Timer period event forces the output to its inactive state

CMP[1]

Bit 3: CMP1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[2]

Bit 4: CMP2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[3]

Bit 5: CMP3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[4]

Bit 6: CMP4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

MSTPER

Bit 7: MSTPER.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetInactive: Master timer counter roll-over/reset forces the output to its inactive state

MSTCMP[1]

Bit 8: MSTCMP1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[2]

Bit 9: MSTCMP2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[3]

Bit 10: MSTCMP3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[4]

Bit 11: MSTCMP4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

TIMBCMP1

Bit 12: Timer B Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMBCMP2

Bit 13: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMBCMP4

Bit 14: Timer B Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMCCMP2

Bit 15: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMCCMP3

Bit 16: Timer C Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMDCMP1

Bit 17: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMDCMP2

Bit 18: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMECMP3

Bit 19: Timer E Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMECMP4

Bit 20: Timer E Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

EXTEVNT[1]

Bit 21: EXTEVNT1.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[2]

Bit 22: EXTEVNT2.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[3]

Bit 23: EXTEVNT3.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[4]

Bit 24: EXTEVNT4.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[5]

Bit 25: EXTEVNT5.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[6]

Bit 26: EXTEVNT6.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[7]

Bit 27: EXTEVNT7.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[8]

Bit 28: EXTEVNT8.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[9]

Bit 29: EXTEVNT9.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[10]

Bit 30: EXTEVNT10.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

UPDATE

Bit 31: UPDATE.

Allowed values:
0: NoEffect: Register update event has no effect
1: SetInactive: Register update event forces the output to its inactive state

SET2R

Timerx Output2 Set Register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPDATE
rw 		EXTEVNT[10]
rw 		EXTEVNT[9]
rw 		EXTEVNT[8]
rw 		EXTEVNT[7]
rw 		EXTEVNT[6]
rw 		EXTEVNT[5]
rw 		EXTEVNT[4]
rw 		EXTEVNT[3]
rw 		EXTEVNT[2]
rw 		EXTEVNT[1]
rw 		TIMECMP4
rw 		TIMECMP3
rw 		TIMDCMP2
rw 		TIMDCMP1
rw 		TIMCCMP3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMCCMP2
rw 		TIMBCMP4
rw 		TIMBCMP2
rw 		TIMBCMP1
rw 		MSTCMP[4]
rw 		MSTCMP[3]
rw 		MSTCMP[2]
rw 		MSTCMP[1]
rw 		MSTPER
rw 		CMP[4]
rw 		CMP[3]
rw 		CMP[2]
rw 		CMP[1]
rw 		PER
rw 		RESYNC
rw 		SST
rw
Toggle fields

SST

Bit 0: Software Set trigger.

Allowed values:
0: NoEffect: No effect
1: SetActive: Force output to its active state

RESYNC

Bit 1: Timer A resynchronizaton.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetActive: Timer reset event coming solely from software or SYNC input event forces the output to its active state

PER

Bit 2: Timer A Period.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetActive: Timer period event forces the output to its active state

CMP[1]

Bit 3: Timer A compare 1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[2]

Bit 4: Timer A compare 2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[3]

Bit 5: Timer A compare 3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[4]

Bit 6: Timer A compare 4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

MSTPER

Bit 7: Master Period.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetActive: Master timer counter roll-over/reset forces the output to its active state

MSTCMP[1]

Bit 8: Master Compare 1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[2]

Bit 9: Master Compare 2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[3]

Bit 10: Master Compare 3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[4]

Bit 11: Master Compare 4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

TIMBCMP1

Bit 12: Timer B Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMBCMP2

Bit 13: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMBCMP4

Bit 14: Timer B Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMCCMP2

Bit 15: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMCCMP3

Bit 16: Timer C Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMDCMP1

Bit 17: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMDCMP2

Bit 18: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMECMP3

Bit 19: Timer E Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMECMP4

Bit 20: Timer E Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

EXTEVNT[1]

Bit 21: External Event 1.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[2]

Bit 22: External Event 2.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[3]

Bit 23: External Event 3.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[4]

Bit 24: External Event 4.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[5]

Bit 25: External Event 5.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[6]

Bit 26: External Event 6.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[7]

Bit 27: External Event 7.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[8]

Bit 28: External Event 8.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[9]

Bit 29: External Event 9.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[10]

Bit 30: External Event 10.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

UPDATE

Bit 31: Registers update (transfer preload to active).

Allowed values:
0: NoEffect: Register update event has no effect
1: SetActive: Register update event forces the output to its active state

RST2R

Timerx Output2 Reset Register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPDATE
rw 		EXTEVNT[10]
rw 		EXTEVNT[9]
rw 		EXTEVNT[8]
rw 		EXTEVNT[7]
rw 		EXTEVNT[6]
rw 		EXTEVNT[5]
rw 		EXTEVNT[4]
rw 		EXTEVNT[3]
rw 		EXTEVNT[2]
rw 		EXTEVNT[1]
rw 		TIMECMP4
rw 		TIMECMP3
rw 		TIMDCMP2
rw 		TIMDCMP1
rw 		TIMCCMP3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMCCMP2
rw 		TIMBCMP4
rw 		TIMBCMP2
rw 		TIMBCMP1
rw 		MSTCMP[4]
rw 		MSTCMP[3]
rw 		MSTCMP[2]
rw 		MSTCMP[1]
rw 		MSTPER
rw 		CMP[4]
rw 		CMP[3]
rw 		CMP[2]
rw 		CMP[1]
rw 		PER
rw 		RESYNC
rw 		SRT
rw
Toggle fields

SRT

Bit 0: SRT.

Allowed values:
0: NoEffect: No effect
1: SetInactive: Force output to its inactive state

RESYNC

Bit 1: RESYNC.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetInactive: Timer reset event coming solely from software or SYNC input event forces the output to its inactive state

PER

Bit 2: PER.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetInactive: Timer period event forces the output to its inactive state

CMP[1]

Bit 3: CMP1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[2]

Bit 4: CMP2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[3]

Bit 5: CMP3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[4]

Bit 6: CMP4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

MSTPER

Bit 7: MSTPER.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetInactive: Master timer counter roll-over/reset forces the output to its inactive state

MSTCMP[1]

Bit 8: MSTCMP1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[2]

Bit 9: MSTCMP2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[3]

Bit 10: MSTCMP3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[4]

Bit 11: MSTCMP4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

TIMBCMP1

Bit 12: Timer B Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMBCMP2

Bit 13: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMBCMP4

Bit 14: Timer B Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMCCMP2

Bit 15: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMCCMP3

Bit 16: Timer C Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMDCMP1

Bit 17: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMDCMP2

Bit 18: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMECMP3

Bit 19: Timer E Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMECMP4

Bit 20: Timer E Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

EXTEVNT[1]

Bit 21: EXTEVNT1.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[2]

Bit 22: EXTEVNT2.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[3]

Bit 23: EXTEVNT3.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[4]

Bit 24: EXTEVNT4.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[5]

Bit 25: EXTEVNT5.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[6]

Bit 26: EXTEVNT6.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[7]

Bit 27: EXTEVNT7.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[8]

Bit 28: EXTEVNT8.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[9]

Bit 29: EXTEVNT9.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[10]

Bit 30: EXTEVNT10.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

UPDATE

Bit 31: UPDATE.

Allowed values:
0: NoEffect: Register update event has no effect
1: SetInactive: Register update event forces the output to its inactive state

EEFR1

Timerx External Event Filtering Register 1

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EE[5]FLTR
rw 		EE[5]LTCH
rw 		EE[4]FLTR
rw 		EE[4]LTCH
rw 		EE[3]FLTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EE[3]FLTR
rw 		EE[3]LTCH
rw 		EE[2]FLTR
rw 		EE[2]LTCH
rw 		EE[1]FLTR
rw 		EE[1]LTCH
rw
Toggle fields

EE[1]LTCH

Bit 0: External Event 1 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[1]FLTR

Bits 1-4: External Event 1 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[2]LTCH

Bit 6: External Event 2 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[2]FLTR

Bits 7-10: External Event 2 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[3]LTCH

Bit 12: External Event 3 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[3]FLTR

Bits 13-16: External Event 3 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[4]LTCH

Bit 18: External Event 4 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[4]FLTR

Bits 19-22: External Event 4 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[5]LTCH

Bit 24: External Event 5 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[5]FLTR

Bits 25-28: External Event 5 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EEFR2

Timerx External Event Filtering Register 2

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EE[10]FLTR
rw 		EE[10]LTCH
rw 		EE[9]FLTR
rw 		EE[9]LTCH
rw 		EE[8]FLTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EE[8]FLTR
rw 		EE[8]LTCH
rw 		EE[7]FLTR
rw 		EE[7]LTCH
rw 		EE[6]FLTR
rw 		EE[6]LTCH
rw
Toggle fields

EE[6]LTCH

Bit 0: External Event 6 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[6]FLTR

Bits 1-4: External Event 6 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[7]LTCH

Bit 6: External Event 7 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[7]FLTR

Bits 7-10: External Event 7 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[8]LTCH

Bit 12: External Event 8 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[8]FLTR

Bits 13-16: External Event 8 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[9]LTCH

Bit 18: External Event 9 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[9]FLTR

Bits 19-22: External Event 9 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[10]LTCH

Bit 24: External Event 10 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[10]FLTR

Bits 25-28: External Event 10 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

RSTR

TimerA Reset Register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

30/30 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIMECMP4
rw 		TIMECMP2
rw 		TIMECMP1
rw 		TIMDCMP4
rw 		TIMDCMP2
rw 		TIMDCMP1
rw 		TIMCCMP4
rw 		TIMCCMP2
rw 		TIMCCMP1
rw 		TIMBCMP4
rw 		TIMBCMP2
rw 		TIMBCMP1
rw 		EXTEVNT10
rw 		EXTEVNT9
rw 		EXTEVNT8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTEVNT7
rw 		EXTEVNT6
rw 		EXTEVNT5
rw 		EXTEVNT4
rw 		EXTEVNT3
rw 		EXTEVNT2
rw 		EXTEVNT1
rw 		MSTCMP4
rw 		MSTCMP3
rw 		MSTCMP2
rw 		MSTCMP1
rw 		MSTPER
rw 		CMP4
rw 		CMP2
rw 		UPDT
rw
Toggle fields

UPDT

Bit 1: Timer A Update reset.

Allowed values:
0: NoEffect: Update event has no effect
1: ResetCounter: Timer X counter is reset upon update event

CMP2

Bit 2: Timer A compare 2 reset.

Allowed values:
0: NoEffect: Timer X compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer X compare Z event

CMP4

Bit 3: Timer A compare 4 reset.

Allowed values:
0: NoEffect: Timer X compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer X compare Z event

MSTPER

Bit 4: Master timer Period.

Allowed values:
0: NoEffect: Master timer period event has no effect
1: ResetCounter: Timer X counter is reset upon master timer period event

MSTCMP1

Bit 5: Master compare 1.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

MSTCMP2

Bit 6: Master compare 2.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

MSTCMP3

Bit 7: Master compare 3.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

MSTCMP4

Bit 8: Master compare 4.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

EXTEVNT1

Bit 9: External Event 1.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT2

Bit 10: External Event 2.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT3

Bit 11: External Event 3.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT4

Bit 12: External Event 4.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT5

Bit 13: External Event 5.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT6

Bit 14: External Event 6.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT7

Bit 15: External Event 7.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT8

Bit 16: External Event 8.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT9

Bit 17: External Event 9.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT10

Bit 18: External Event 10.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

TIMBCMP1

Bit 19: Timer B Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMBCMP2

Bit 20: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMBCMP4

Bit 21: Timer B Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMCCMP1

Bit 22: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMCCMP2

Bit 23: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMCCMP4

Bit 24: Timer C Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMDCMP1

Bit 25: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMDCMP2

Bit 26: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMDCMP4

Bit 27: Timer D Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMECMP1

Bit 28: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMECMP2

Bit 29: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMECMP4

Bit 30: Timer E Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

CHPR

Timerx Chopper Register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STRTPW
rw 		CARDTY
rw 		CARFRQ
rw
Toggle fields

CARFRQ

Bits 0-3: Timerx carrier frequency value.

Allowed values: 0x0-0xf

CARDTY

Bits 4-6: Timerx chopper duty cycle value.

Allowed values: 0x0-0x7

STRTPW

Bits 7-10: STRTPW.

Allowed values: 0x0-0xf

CPT1CR

Timerx Capture 2 Control Register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TECMP2
rw 		TECMP1
rw 		TE1RST
rw 		TE1SET
rw 		TDCMP2
rw 		TDCMP1
rw 		TD1RST
rw 		TD1SET
rw 		TCCMP2
rw 		TCCMP1
rw 		TC1RST
rw 		TC1SET
rw 		TBCMP2
rw 		TBCMP1
rw 		TB1RST
rw 		TB1SET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXEV[10]CPT
rw 		EXEV[9]CPT
rw 		EXEV[8]CPT
rw 		EXEV[7]CPT
rw 		EXEV[6]CPT
rw 		EXEV[5]CPT
rw 		EXEV[4]CPT
rw 		EXEV[3]CPT
rw 		EXEV[2]CPT
rw 		EXEV[1]CPT
rw 		UPDCPT
rw 		SWCPT
rw
Toggle fields

SWCPT

Bit 0: Software Capture.

Allowed values:
0: NoEffect: No effect
1: TriggerCapture: Force capture Z

UPDCPT

Bit 1: Update Capture.

Allowed values:
0: NoEffect: Update event has no effect
1: TriggerCapture: Update event triggers capture Z

EXEV[1]CPT

Bit 2: External Event 1 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[2]CPT

Bit 3: External Event 2 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[3]CPT

Bit 4: External Event 3 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[4]CPT

Bit 5: External Event 4 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[5]CPT

Bit 6: External Event 5 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[6]CPT

Bit 7: External Event 6 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[7]CPT

Bit 8: External Event 7 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[8]CPT

Bit 9: External Event 8 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[9]CPT

Bit 10: External Event 9 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[10]CPT

Bit 11: External Event 10 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

TB1SET

Bit 16: Timer B output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TB1RST

Bit 17: Timer B output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TBCMP1

Bit 18: Timer B Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TBCMP2

Bit 19: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TC1SET

Bit 20: Timer C output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TC1RST

Bit 21: Timer C output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TCCMP1

Bit 22: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TCCMP2

Bit 23: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TD1SET

Bit 24: Timer D output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TD1RST

Bit 25: Timer D output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TDCMP1

Bit 26: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TDCMP2

Bit 27: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TE1SET

Bit 28: Timer E output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TE1RST

Bit 29: Timer E output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TECMP1

Bit 30: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TECMP2

Bit 31: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

CPT2CR

CPT2xCR

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TECMP2
rw 		TECMP1
rw 		TE1RST
rw 		TE1SET
rw 		TDCMP2
rw 		TDCMP1
rw 		TD1RST
rw 		TD1SET
rw 		TCCMP2
rw 		TCCMP1
rw 		TC1RST
rw 		TC1SET
rw 		TBCMP2
rw 		TBCMP1
rw 		TB1RST
rw 		TB1SET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXEV[10]CPT
rw 		EXEV[9]CPT
rw 		EXEV[8]CPT
rw 		EXEV[7]CPT
rw 		EXEV[6]CPT
rw 		EXEV[5]CPT
rw 		EXEV[4]CPT
rw 		EXEV[3]CPT
rw 		EXEV[2]CPT
rw 		EXEV[1]CPT
rw 		UPDCPT
rw 		SWCPT
rw
Toggle fields

SWCPT

Bit 0: Software Capture.

Allowed values:
0: NoEffect: No effect
1: TriggerCapture: Force capture Z

UPDCPT

Bit 1: Update Capture.

Allowed values:
0: NoEffect: Update event has no effect
1: TriggerCapture: Update event triggers capture Z

EXEV[1]CPT

Bit 2: External Event 1 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[2]CPT

Bit 3: External Event 2 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[3]CPT

Bit 4: External Event 3 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[4]CPT

Bit 5: External Event 4 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[5]CPT

Bit 6: External Event 5 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[6]CPT

Bit 7: External Event 6 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[7]CPT

Bit 8: External Event 7 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[8]CPT

Bit 9: External Event 8 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[9]CPT

Bit 10: External Event 9 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[10]CPT

Bit 11: External Event 10 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

TB1SET

Bit 16: Timer B output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TB1RST

Bit 17: Timer B output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TBCMP1

Bit 18: Timer B Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TBCMP2

Bit 19: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TC1SET

Bit 20: Timer C output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TC1RST

Bit 21: Timer C output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TCCMP1

Bit 22: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TCCMP2

Bit 23: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TD1SET

Bit 24: Timer D output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TD1RST

Bit 25: Timer D output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TDCMP1

Bit 26: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TDCMP2

Bit 27: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TE1SET

Bit 28: Timer E output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TE1RST

Bit 29: Timer E output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TECMP1

Bit 30: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TECMP2

Bit 31: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

OUTR

Timerx Output Register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIDL2
rw 		CHP2
rw 		FAULT2
rw 		IDLES2
rw 		IDLEM2
rw 		POL2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYPRT
rw 		DLYPRTEN
rw 		DTEN
rw 		DIDL1
rw 		CHP1
rw 		FAULT1
rw 		IDLES1
rw 		IDLEM1
rw 		POL1
rw
Toggle fields

POL1

Bit 1: Output 1 polarity.

Allowed values:
0: ActiveHigh: Positive polarity (output active high)
1: ActiveLow: Negative polarity (output active low)

IDLEM1

Bit 2: Output 1 Idle mode.

Allowed values:
0: NoEffect: No action: the output is not affected by the burst mode operation
1: SetIdle: The output is in idle state when requested by the burst mode controller

IDLES1

Bit 3: Output 1 Idle State.

Allowed values:
0: Inactive: Output idle state is inactive
1: Active: Output idle state is active

FAULT1

Bits 4-5: Output 1 Fault state.

Allowed values:
0: Disabled: No action: the output is not affected by the fault input and stays in run mode
1: SetActive: Output goes to active state after a fault event
2: SetInactive: Output goes to inactive state after a fault event
3: SetHighZ: Output goes to high-z state after a fault event

CHP1

Bit 6: Output 1 Chopper enable.

Allowed values:
0: Disabled: Output signal not altered
1: Enabled: Output signal is chopped by a carrier signal

DIDL1

Bit 7: Output 1 Deadtime upon burst mode Idle entry.

Allowed values:
0: Disabled: The programmed idle state is applied immediately to the output
1: Enabled: Deadtime (inactive level) is inserted on output before entering the idle mode

DTEN

Bit 8: Deadtime enable.

Allowed values:
0: Disabled: Output 1 and 2 signals are independent
1: Enabled: Deadtime is inserted between output 1 and output 2

DLYPRTEN

Bit 9: Delayed Protection Enable.

Allowed values:
0: Disabled: No action
1: Enabled: Delayed protection is enabled, as per DLYPRT bits

DLYPRT

Bits 10-12: Delayed Protection.

Allowed values:
0: Output1_EE6: Output 1 delayed idle on external event 6
1: Output2_EE6: Output 2 delayed idle on external event 6
2: Output1_2_EE6: Output 1 and 2 delayed idle on external event 6
3: Balanced_EE6: Balanced idle on external event 6
4: Output1_EE7: Output 1 delayed idle on external event 7
5: Output2_EE7: Output 2 delayed idle on external event 7
6: Output1_2_EE7: Output 1 and 2 delayed idle on external event 7
7: Balanced_EE7: Balanced idle on external event 7

POL2

Bit 17: Output 2 polarity.

Allowed values:
0: ActiveHigh: Positive polarity (output active high)
1: ActiveLow: Negative polarity (output active low)

IDLEM2

Bit 18: Output 2 Idle mode.

Allowed values:
0: NoEffect: No action: the output is not affected by the burst mode operation
1: SetIdle: The output is in idle state when requested by the burst mode controller

IDLES2

Bit 19: Output 2 Idle State.

Allowed values:
0: Inactive: Output idle state is inactive
1: Active: Output idle state is active

FAULT2

Bits 20-21: Output 2 Fault state.

Allowed values:
0: Disabled: No action: the output is not affected by the fault input and stays in run mode
1: SetActive: Output goes to active state after a fault event
2: SetInactive: Output goes to inactive state after a fault event
3: SetHighZ: Output goes to high-z state after a fault event

CHP2

Bit 22: Output 2 Chopper enable.

Allowed values:
0: Disabled: Output signal not altered
1: Enabled: Output signal is chopped by a carrier signal

DIDL2

Bit 23: Output 2 Deadtime upon burst mode Idle entry.

Allowed values:
0: Disabled: The programmed idle state is applied immediately to the output
1: Enabled: Deadtime (inactive level) is inserted on output before entering the idle mode

FLTR

Timerx Fault Register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLTLCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLT[5]EN
rw 		FLT[4]EN
rw 		FLT[3]EN
rw 		FLT[2]EN
rw 		FLT[1]EN
rw
Toggle fields

FLT[1]EN

Bit 0: Fault 1 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[2]EN

Bit 1: Fault 2 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[3]EN

Bit 2: Fault 3 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[4]EN

Bit 3: Fault 4 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[5]EN

Bit 4: Fault 5 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLTLCK

Bit 31: Fault sources Lock.

Allowed values:
0: Unlocked: FLT1EN..FLT5EN bits are read/write
1: Locked: FLT1EN..FLT5EN bits are read only

HRTIM_TIMB

0x40017500: High Resolution Timer: TIMB

359/359 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 ISR
0x8 ICR
0xc DIER
0x10 CNTR
0x14 PERR
0x18 REPR
0x1c CMP1R
0x20 CMP1CR
0x24 CMP2R
0x28 CMP3R
0x2c CMP4R
0x30 CPT1R
0x34 CPT2R
0x38 DTR
0x3c SET1R
0x40 RST1R
0x44 SET2R
0x48 RST2R
0x4c EEFR1
0x50 EEFR2
0x54 RSTR
0x58 CHPR
0x5c CPT1CR
0x60 CPT2CR
0x64 OUTR
0x68 FLTR
Toggle registers

CR

Timerx Control Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPDGAT
rw 		PREEN
rw 		DACSYNC
rw 		MSTU
rw 		TEU
rw 		TDU
rw 		TCU
rw 		TBU
rw 		TRSTU
rw 		TREPU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DELCMP4
rw 		DELCMP2
rw 		SYNCSTRT
rw 		SYNCRST
rw 		PSHPLL
rw 		HALF
rw 		RETRIG
rw 		CONT
rw 		CKPSC
rw
Toggle fields

CKPSC

Bits 0-2: HRTIM Timer x Clock prescaler.

Allowed values: 0x0-0x7

CONT

Bit 3: Continuous mode.

Allowed values:
0: SingleShot: The timer operates in single-shot mode and stops when it reaches the TIMxPER value
1: Continuous: The timer operates in continuous (free-running) mode and rolls over to zero when it reaches the TIMxPER value

RETRIG

Bit 4: Re-triggerable mode.

Allowed values:
0: Disabled: The timer is not re-triggerable: a counter reset can be done only if the counter is stopped
1: Enabled: The timer is retriggerable: a counter reset is done whatever the counter state

HALF

Bit 5: Half mode enable.

Allowed values:
0: Disabled: Half mode disabled
1: Enabled: Half mode enabled

PSHPLL

Bit 6: Push-Pull mode enable.

Allowed values:
0: Disabled: Push-pull mode disabled
1: Enabled: Push-pull mode enabled

SYNCRST

Bit 10: Synchronization Resets Timer x.

Allowed values:
0: Disabled: Synchronization event has no effect on Timer x
1: Reset: Synchronization event resets Timer x

SYNCSTRT

Bit 11: Synchronization Starts Timer x.

Allowed values:
0: Disabled: Synchronization event has no effect on Timer x
1: Start: Synchronization event starts Timer x

DELCMP2

Bits 12-13: Delayed CMP2 mode.

Allowed values:
0: Standard: CMP2 register is always active (standard compare mode)
1: Capture1: CMP2 is recomputed and is active following a capture 1 event
2: Capture1_Compare1: CMP2 is recomputed and is active following a capture 1 event or a Compare 1 match
3: Capture1_Compare3: CMP2 is recomputed and is active following a capture 1 event or a Compare 3 match

DELCMP4

Bits 14-15: Delayed CMP4 mode.

Allowed values:
0: Standard: CMP4 register is always active (standard compare mode)
1: Capture2: CMP4 is recomputed and is active following a capture 2 event
2: Capture2_Compare1: CMP4 is recomputed and is active following a capture 2 event or a Compare 1 match
3: Capture_Compare3: CMP4 is recomputed and is active following a capture event or a Compare 3 match

TREPU

Bit 17: Timer x Repetition update.

Allowed values:
0: Disabled: Update by timer x repetition disabled
1: Enabled: Update by timer x repetition enabled

TRSTU

Bit 18: Timerx reset update.

Allowed values:
0: Disabled: Update by timer x reset/roll-over disabled
1: Enabled: Update by timer x reset/roll-over enabled

TBU

Bit 20: TBU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

TCU

Bit 21: TCU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

TDU

Bit 22: TDU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

TEU

Bit 23: TEU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

MSTU

Bit 24: Master Timer update.

Allowed values:
0: Disabled: Update by master timer disabled
1: Enabled: Update by master timer enabled

DACSYNC

Bits 25-26: AC Synchronization.

Allowed values:
0: Disabled: No DAC trigger generated
1: DACSync1: Trigger generated on DACSync1
2: DACSync2: Trigger generated on DACSync2
3: DACSync3: Trigger generated on DACSync3

PREEN

Bit 27: Preload enable.

Allowed values:
0: Disabled: Preload disabled: the write access is directly done into the active register
1: Enabled: Preload enabled: the write access is done into the preload register

UPDGAT

Bits 28-31: Update Gating.

Allowed values:
0: Independent: Update occurs independently from the DMA burst transfer
1: DMABurst: Update occurs when the DMA burst transfer is completed
2: DMABurst_Update: Update occurs on the update event following DMA burst transfer completion
3: Input1: Update occurs on a rising edge of HRTIM update enable input 1
4: Input2: Update occurs on a rising edge of HRTIM update enable input 2
5: Input3: Update occurs on a rising edge of HRTIM update enable input 3
6: Input1_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 1
7: Input2_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 2
8: Input3_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 3

ISR

Timerx Interrupt Status Register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
O2CPY
r 		O1CPY
r 		O2STAT
r 		O1STAT
r 		IPPSTAT
r 		CPPSTAT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYPRT
r 		RST
r 		RST2
r 		SET[2]
r 		RST1
r 		SET[1]
r 		CPT[2]
r 		CPT[1]
r 		UPD
r 		REP
r 		CMP[4]
r 		CMP[3]
r 		CMP[2]
r 		CMP[1]
r
Toggle fields

CMP[1]

Bit 0: Compare 1 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

CMP[2]

Bit 1: Compare 2 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

CMP[3]

Bit 2: Compare 3 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

CMP[4]

Bit 3: Compare 4 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

REP

Bit 4: Repetition Interrupt Flag.

Allowed values:
0: NoEvent: No timer repetition interrupt occurred
1: Event: Timer repetition interrupt occurred

UPD

Bit 6: Update Interrupt Flag.

Allowed values:
0: NoEvent: No timer update interrupt occurred
1: Event: Timer update interrupt occurred

CPT[1]

Bit 7: Capture1 Interrupt Flag.

Allowed values:
0: NoEvent: No timer x capture reset interrupt occurred
1: Event: Timer x capture reset interrupt occurred

CPT[2]

Bit 8: Capture2 Interrupt Flag.

Allowed values:
0: NoEvent: No timer x capture reset interrupt occurred
1: Event: Timer x capture reset interrupt occurred

SET[1]

Bit 9: Output 1 Set Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output set interrupt occurred
1: Event: Tx output set interrupt occurred

RST1

Bit 10: Output 1 Reset Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output reset interrupt occurred
1: Event: Tx output reset interrupt occurred

SET[2]

Bit 11: Output 2 Set Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output set interrupt occurred
1: Event: Tx output set interrupt occurred

RST2

Bit 12: Output 2 Reset Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output reset interrupt occurred
1: Event: Tx output reset interrupt occurred

RST

Bit 13: Reset Interrupt Flag.

Allowed values:
0: NoEvent: No TIMx counter reset/roll-over interrupt occurred
1: Event: TIMx counter reset/roll-over interrupt occurred

DLYPRT

Bit 14: Delayed Protection Flag.

Allowed values:
0: Inactive: Not in delayed idle or balanced idle mode
1: Active: Delayed idle or balanced idle mode entry

CPPSTAT

Bit 16: Current Push Pull Status.

Allowed values:
0: Output1Active: Signal applied on output 1 and output 2 forced inactive
1: Output2Active: Signal applied on output 2 and output 1 forced inactive

IPPSTAT

Bit 17: Idle Push Pull Status.

Allowed values:
0: Output1Active: Protection occurred when the output 1 was active and output 2 forced inactive
1: Output2Active: Protection occurred when the output 2 was active and output 1 forced inactive

O1STAT

Bit 18: Output 1 State.

Allowed values:
0: Inactive: Output was inactive
1: Active: Output was active

O2STAT

Bit 19: Output 2 State.

Allowed values:
0: Inactive: Output was inactive
1: Active: Output was active

O1CPY

Bit 20: Output 1 Copy.

Allowed values:
0: Inactive: Output is inactive
1: Active: Output is active

O2CPY

Bit 21: Output 2 Copy.

Allowed values:
0: Inactive: Output is inactive
1: Active: Output is active

ICR

Timerx Interrupt Clear Register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

14/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYPRTC
w 		RSTC
w 		RST2C
w 		SET[2]C
w 		RST1C
w 		SET[1]C
w 		CPT[2]C
w 		CPT[1]C
w 		UPDC
w 		REPC
w 		CMP[4]C
w 		CMP[3]C
w 		CMP[2]C
w 		CMP[1]C
w
Toggle fields

CMP[1]C

Bit 0: Compare 1 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CMP[2]C

Bit 1: Compare 2 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CMP[3]C

Bit 2: Compare 3 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CMP[4]C

Bit 3: Compare 4 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

REPC

Bit 4: Repetition Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

UPDC

Bit 6: Update Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CPT[1]C

Bit 7: Capture1 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CPT[2]C

Bit 8: Capture2 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

SET[1]C

Bit 9: Output 1 Set flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

RST1C

Bit 10: Output 1 Reset flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

SET[2]C

Bit 11: Output 2 Set flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

RST2C

Bit 12: Output 2 Reset flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

RSTC

Bit 13: Reset Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

DLYPRTC

Bit 14: Delayed Protection Flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

DIER

TIMxDIER5

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLYPRTDE
rw 		RSTDE
rw 		RST2DE
rw 		SET[2]DE
rw 		RST1DE
rw 		SET[1]DE
rw 		CPT[2]DE
rw 		CPT[1]DE
rw 		UPDDE
rw 		REPDE
rw 		CMP[4]DE
rw 		CMP[3]DE
rw 		CMP[2]DE
rw 		CMP[1]DE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYPRTIE
rw 		RSTIE
rw 		RST2IE
rw 		SET[2]IE
rw 		RST1IE
rw 		SET[1]IE
rw 		CPT[2]IE
rw 		CPT[1]IE
rw 		UPDIE
rw 		REPIE
rw 		CMP[4]IE
rw 		CMP[3]IE
rw 		CMP[2]IE
rw 		CMP[1]IE
rw
Toggle fields

CMP[1]IE

Bit 0: CMP1IE.

Allowed values:
0: Disabled: Compare interrupt disabled
1: Enabled: Compare interrupt enabled

CMP[2]IE

Bit 1: CMP2IE.

Allowed values:
0: Disabled: Compare interrupt disabled
1: Enabled: Compare interrupt enabled

CMP[3]IE

Bit 2: CMP3IE.

Allowed values:
0: Disabled: Compare interrupt disabled
1: Enabled: Compare interrupt enabled

CMP[4]IE

Bit 3: CMP4IE.

Allowed values:
0: Disabled: Compare interrupt disabled
1: Enabled: Compare interrupt enabled

REPIE

Bit 4: REPIE.

Allowed values:
0: Disabled: Repetition interrupt disabled
1: Enabled: Repetition interrupt enabled

UPDIE

Bit 6: UPDIE.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CPT[1]IE

Bit 7: CPT1IE.

Allowed values:
0: Disabled: Capture interrupt disabled
1: Enabled: Capture interrupt enabled

CPT[2]IE

Bit 8: CPT2IE.

Allowed values:
0: Disabled: Capture interrupt disabled
1: Enabled: Capture interrupt enabled

SET[1]IE

Bit 9: Output 1 set interrupt enable.

Allowed values:
0: Disabled: Tx output set interrupt disabled
1: Enabled: Tx output set interrupt enabled

RST1IE

Bit 10: RSTx1IE.

Allowed values:
0: Disabled: Tx output reset interrupt disabled
1: Enabled: Tx output reset interrupt enabled

SET[2]IE

Bit 11: Output 2 set interrupt enable.

Allowed values:
0: Disabled: Tx output set interrupt disabled
1: Enabled: Tx output set interrupt enabled

RST2IE

Bit 12: RSTx2IE.

Allowed values:
0: Disabled: Tx output reset interrupt disabled
1: Enabled: Tx output reset interrupt enabled

RSTIE

Bit 13: RSTIE.

Allowed values:
0: Disabled: Timer x counter/reset roll-over interrupt disabled
1: Enabled: Timer x counter/reset roll-over interrupt enabled

DLYPRTIE

Bit 14: DLYPRTIE.

Allowed values:
0: Disabled: Delayed protection interrupt disabled
1: Enabled: Delayed protection interrupt enabled

CMP[1]DE

Bit 16: CMP1DE.

Allowed values:
0: Disabled: Compare DMA request disabled
1: Enabled: Compare DMA request enabled

CMP[2]DE

Bit 17: CMP2DE.

Allowed values:
0: Disabled: Compare DMA request disabled
1: Enabled: Compare DMA request enabled

CMP[3]DE

Bit 18: CMP3DE.

Allowed values:
0: Disabled: Compare DMA request disabled
1: Enabled: Compare DMA request enabled

CMP[4]DE

Bit 19: CMP4DE.

Allowed values:
0: Disabled: Compare DMA request disabled
1: Enabled: Compare DMA request enabled

REPDE

Bit 20: REPDE.

Allowed values:
0: Disabled: Repetition DMA request disabled
1: Enabled: Repetition DMA request enabled

UPDDE

Bit 22: UPDDE.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CPT[1]DE

Bit 23: CPT1DE.

Allowed values:
0: Disabled: Capture DMA request disabled
1: Enabled: Capture DMA request enabled

CPT[2]DE

Bit 24: CPT2DE.

Allowed values:
0: Disabled: Capture DMA request disabled
1: Enabled: Capture DMA request enabled

SET[1]DE

Bit 25: Output 1 set DMA request enable.

Allowed values:
0: Disabled: Tx output set DMA request disabled
1: Enabled: Tx output set DMA request enabled

RST1DE

Bit 26: RSTx1DE.

Allowed values:
0: Disabled: Tx output reset DMA request disabled
1: Enabled: Tx output reset DMA request enabled

SET[2]DE

Bit 27: Output 2 set DMA request enable.

Allowed values:
0: Disabled: Tx output set DMA request disabled
1: Enabled: Tx output set DMA request enabled

RST2DE

Bit 28: RSTx2DE.

Allowed values:
0: Disabled: Tx output reset DMA request disabled
1: Enabled: Tx output reset DMA request enabled

RSTDE

Bit 29: RSTDE.

Allowed values:
0: Disabled: Timer x counter reset/roll-over DMA request disabled
1: Enabled: Timer x counter reset/roll-over DMA request enabled

DLYPRTDE

Bit 30: DLYPRTDE.

Allowed values:
0: Disabled: Delayed protection DMA request disabled
1: Enabled: Delayed protection DMA request enabled

CNTR

Timerx Counter Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: Counter value.

Allowed values: 0x0-0xffff

PERR

Timerx Period Register

Offset: 0x14, size: 32, reset: 0x0000FFFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PER
rw
Toggle fields

PER

Bits 0-15: Master Timer Period value.

Allowed values: 0x0-0xffff

REPR

Timerx Repetition Register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Master Timer Repetition counter value.

Allowed values: 0x0-0xff

CMP1R

Timerx Compare 1 Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CMP1CR

Timerx Compare 1 Compound Register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP1
rw
Toggle fields

CMP1

Bits 0-15: Timerx Compare 1 value.

Allowed values: 0x0-0xffff

REP

Bits 16-23: Timerx Repetition value (aliased from HRTIM_REPx register).

Allowed values: 0x0-0xff

CMP2R

Timerx Compare 2 Register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CMP3R

Timerx Compare 3 Register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CMP4R

Timerx Compare 4 Register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CPT1R

Timerx Capture 1 Register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPT
r
Toggle fields

CPT

Bits 0-15: Timerx Capture 1 value.

Allowed values: 0x0-0xffff

CPT2R

Timerx Capture 2 Register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPT
r
Toggle fields

CPT

Bits 0-15: Timerx Capture 1 value.

Allowed values: 0x0-0xffff

DTR

Timerx Deadtime Register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTFLK
rw 		DTFSLK
rw 		SDTF
rw 		DTF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTRLK
rw 		DTRSLK
rw 		DTPRSC
rw 		SDTR
rw 		DTR
rw
Toggle fields

DTR

Bits 0-8: Deadtime Rising value.

Allowed values: 0x0-0x1ff

SDTR

Bit 9: Sign Deadtime Rising value.

Allowed values:
0: Positive: Positive deadtime on rising edge
1: Negative: Negative deadtime on rising edge

DTPRSC

Bits 10-12: Deadtime Prescaler.

Allowed values: 0x0-0x7

DTRSLK

Bit 14: Deadtime Rising Sign Lock.

Allowed values:
0: Unlocked: Deadtime rising sign is writable
1: Locked: Deadtime rising sign is read-only

DTRLK

Bit 15: Deadtime Rising Lock.

Allowed values:
0: Unlocked: Deadtime rising value and sign is writable
1: Locked: Deadtime rising value and sign is read-only

DTF

Bits 16-24: Deadtime Falling value.

Allowed values: 0x0-0x1ff

SDTF

Bit 25: Sign Deadtime Falling value.

Allowed values:
0: Positive: Positive deadtime on falling edge
1: Negative: Negative deadtime on falling edge

DTFSLK

Bit 30: Deadtime Falling Sign Lock.

Allowed values:
0: Unlocked: Deadtime falling sign is writable
1: Locked: Deadtime falling sign is read-only

DTFLK

Bit 31: Deadtime Falling Lock.

Allowed values:
0: Unlocked: Deadtime falling value and sign is writable
1: Locked: Deadtime falling value and sign is read-only

SET1R

Timerx Output1 Set Register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPDATE
rw 		EXTEVNT[10]
rw 		EXTEVNT[9]
rw 		EXTEVNT[8]
rw 		EXTEVNT[7]
rw 		EXTEVNT[6]
rw 		EXTEVNT[5]
rw 		EXTEVNT[4]
rw 		EXTEVNT[3]
rw 		EXTEVNT[2]
rw 		EXTEVNT[1]
rw 		TIMECMP2
rw 		TIMECMP1
rw 		TIMDCMP4
rw 		TIMDCMP3
rw 		TIMCCMP4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMCCMP3
rw 		TIMACMP4
rw 		TIMACMP2
rw 		TIMACMP1
rw 		MSTCMP[4]
rw 		MSTCMP[3]
rw 		MSTCMP[2]
rw 		MSTCMP[1]
rw 		MSTPER
rw 		CMP[4]
rw 		CMP[3]
rw 		CMP[2]
rw 		CMP[1]
rw 		PER
rw 		RESYNC
rw 		SST
rw
Toggle fields

SST

Bit 0: Software Set trigger.

Allowed values:
0: NoEffect: No effect
1: SetActive: Force output to its active state

RESYNC

Bit 1: Timer A resynchronizaton.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetActive: Timer reset event coming solely from software or SYNC input event forces the output to its active state

PER

Bit 2: Timer A Period.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetActive: Timer period event forces the output to its active state

CMP[1]

Bit 3: Timer A compare 1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[2]

Bit 4: Timer A compare 2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[3]

Bit 5: Timer A compare 3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[4]

Bit 6: Timer A compare 4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

MSTPER

Bit 7: Master Period.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetActive: Master timer counter roll-over/reset forces the output to its active state

MSTCMP[1]

Bit 8: Master Compare 1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[2]

Bit 9: Master Compare 2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[3]

Bit 10: Master Compare 3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[4]

Bit 11: Master Compare 4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

TIMACMP1

Bit 12: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMACMP2

Bit 13: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMACMP4

Bit 14: Timer A Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMCCMP3

Bit 15: Timer C Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMCCMP4

Bit 16: Timer C Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMDCMP3

Bit 17: Timer D Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMDCMP4

Bit 18: Timer D Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMECMP1

Bit 19: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMECMP2

Bit 20: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

EXTEVNT[1]

Bit 21: External Event 1.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[2]

Bit 22: External Event 2.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[3]

Bit 23: External Event 3.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[4]

Bit 24: External Event 4.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[5]

Bit 25: External Event 5.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[6]

Bit 26: External Event 6.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[7]

Bit 27: External Event 7.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[8]

Bit 28: External Event 8.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[9]

Bit 29: External Event 9.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[10]

Bit 30: External Event 10.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

UPDATE

Bit 31: Registers update (transfer preload to active).

Allowed values:
0: NoEffect: Register update event has no effect
1: SetActive: Register update event forces the output to its active state

RST1R

Timerx Output1 Reset Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPDATE
rw 		EXTEVNT[10]
rw 		EXTEVNT[9]
rw 		EXTEVNT[8]
rw 		EXTEVNT[7]
rw 		EXTEVNT[6]
rw 		EXTEVNT[5]
rw 		EXTEVNT[4]
rw 		EXTEVNT[3]
rw 		EXTEVNT[2]
rw 		EXTEVNT[1]
rw 		TIMECMP2
rw 		TIMECMP1
rw 		TIMDCMP4
rw 		TIMDCMP3
rw 		TIMCCMP4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMCCMP3
rw 		TIMACMP4
rw 		TIMACMP2
rw 		TIMACMP1
rw 		MSTCMP[4]
rw 		MSTCMP[3]
rw 		MSTCMP[2]
rw 		MSTCMP[1]
rw 		MSTPER
rw 		CMP[4]
rw 		CMP[3]
rw 		CMP[2]
rw 		CMP[1]
rw 		PER
rw 		RESYNC
rw 		SRT
rw
Toggle fields

SRT

Bit 0: SRT.

Allowed values:
0: NoEffect: No effect
1: SetInactive: Force output to its inactive state

RESYNC

Bit 1: RESYNC.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetInactive: Timer reset event coming solely from software or SYNC input event forces the output to its inactive state

PER

Bit 2: PER.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetInactive: Timer period event forces the output to its inactive state

CMP[1]

Bit 3: CMP1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[2]

Bit 4: CMP2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[3]

Bit 5: CMP3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[4]

Bit 6: CMP4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

MSTPER

Bit 7: MSTPER.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetInactive: Master timer counter roll-over/reset forces the output to its inactive state

MSTCMP[1]

Bit 8: MSTCMP1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[2]

Bit 9: MSTCMP2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[3]

Bit 10: MSTCMP3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[4]

Bit 11: MSTCMP4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

TIMACMP1

Bit 12: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMACMP2

Bit 13: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMACMP4

Bit 14: Timer A Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMCCMP3

Bit 15: Timer C Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMCCMP4

Bit 16: Timer C Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMDCMP3

Bit 17: Timer D Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMDCMP4

Bit 18: Timer D Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMECMP1

Bit 19: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMECMP2

Bit 20: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

EXTEVNT[1]

Bit 21: EXTEVNT1.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[2]

Bit 22: EXTEVNT2.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[3]

Bit 23: EXTEVNT3.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[4]

Bit 24: EXTEVNT4.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[5]

Bit 25: EXTEVNT5.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[6]

Bit 26: EXTEVNT6.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[7]

Bit 27: EXTEVNT7.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[8]

Bit 28: EXTEVNT8.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[9]

Bit 29: EXTEVNT9.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[10]

Bit 30: EXTEVNT10.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

UPDATE

Bit 31: UPDATE.

Allowed values:
0: NoEffect: Register update event has no effect
1: SetInactive: Register update event forces the output to its inactive state

SET2R

Timerx Output2 Set Register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPDATE
rw 		EXTEVNT[10]
rw 		EXTEVNT[9]
rw 		EXTEVNT[8]
rw 		EXTEVNT[7]
rw 		EXTEVNT[6]
rw 		EXTEVNT[5]
rw 		EXTEVNT[4]
rw 		EXTEVNT[3]
rw 		EXTEVNT[2]
rw 		EXTEVNT[1]
rw 		TIMECMP2
rw 		TIMECMP1
rw 		TIMDCMP4
rw 		TIMDCMP3
rw 		TIMCCMP4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMCCMP3
rw 		TIMACMP4
rw 		TIMACMP2
rw 		TIMACMP1
rw 		MSTCMP[4]
rw 		MSTCMP[3]
rw 		MSTCMP[2]
rw 		MSTCMP[1]
rw 		MSTPER
rw 		CMP[4]
rw 		CMP[3]
rw 		CMP[2]
rw 		CMP[1]
rw 		PER
rw 		RESYNC
rw 		SST
rw
Toggle fields

SST

Bit 0: Software Set trigger.

Allowed values:
0: NoEffect: No effect
1: SetActive: Force output to its active state

RESYNC

Bit 1: Timer A resynchronizaton.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetActive: Timer reset event coming solely from software or SYNC input event forces the output to its active state

PER

Bit 2: Timer A Period.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetActive: Timer period event forces the output to its active state

CMP[1]

Bit 3: Timer A compare 1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[2]

Bit 4: Timer A compare 2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[3]

Bit 5: Timer A compare 3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[4]

Bit 6: Timer A compare 4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

MSTPER

Bit 7: Master Period.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetActive: Master timer counter roll-over/reset forces the output to its active state

MSTCMP[1]

Bit 8: Master Compare 1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[2]

Bit 9: Master Compare 2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[3]

Bit 10: Master Compare 3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[4]

Bit 11: Master Compare 4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

TIMACMP1

Bit 12: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMACMP2

Bit 13: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMACMP4

Bit 14: Timer A Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMCCMP3

Bit 15: Timer C Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMCCMP4

Bit 16: Timer C Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMDCMP3

Bit 17: Timer D Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMDCMP4

Bit 18: Timer D Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMECMP1

Bit 19: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMECMP2

Bit 20: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

EXTEVNT[1]

Bit 21: External Event 1.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[2]

Bit 22: External Event 2.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[3]

Bit 23: External Event 3.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[4]

Bit 24: External Event 4.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[5]

Bit 25: External Event 5.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[6]

Bit 26: External Event 6.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[7]

Bit 27: External Event 7.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[8]

Bit 28: External Event 8.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[9]

Bit 29: External Event 9.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[10]

Bit 30: External Event 10.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

UPDATE

Bit 31: Registers update (transfer preload to active).

Allowed values:
0: NoEffect: Register update event has no effect
1: SetActive: Register update event forces the output to its active state

RST2R

Timerx Output2 Reset Register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPDATE
rw 		EXTEVNT[10]
rw 		EXTEVNT[9]
rw 		EXTEVNT[8]
rw 		EXTEVNT[7]
rw 		EXTEVNT[6]
rw 		EXTEVNT[5]
rw 		EXTEVNT[4]
rw 		EXTEVNT[3]
rw 		EXTEVNT[2]
rw 		EXTEVNT[1]
rw 		TIMECMP2
rw 		TIMECMP1
rw 		TIMDCMP4
rw 		TIMDCMP3
rw 		TIMCCMP4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMCCMP3
rw 		TIMACMP4
rw 		TIMACMP2
rw 		TIMACMP1
rw 		MSTCMP[4]
rw 		MSTCMP[3]
rw 		MSTCMP[2]
rw 		MSTCMP[1]
rw 		MSTPER
rw 		CMP[4]
rw 		CMP[3]
rw 		CMP[2]
rw 		CMP[1]
rw 		PER
rw 		RESYNC
rw 		SRT
rw
Toggle fields

SRT

Bit 0: SRT.

Allowed values:
0: NoEffect: No effect
1: SetInactive: Force output to its inactive state

RESYNC

Bit 1: RESYNC.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetInactive: Timer reset event coming solely from software or SYNC input event forces the output to its inactive state

PER

Bit 2: PER.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetInactive: Timer period event forces the output to its inactive state

CMP[1]

Bit 3: CMP1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[2]

Bit 4: CMP2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[3]

Bit 5: CMP3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[4]

Bit 6: CMP4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

MSTPER

Bit 7: MSTPER.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetInactive: Master timer counter roll-over/reset forces the output to its inactive state

MSTCMP[1]

Bit 8: MSTCMP1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[2]

Bit 9: MSTCMP2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[3]

Bit 10: MSTCMP3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[4]

Bit 11: MSTCMP4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

TIMACMP1

Bit 12: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMACMP2

Bit 13: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMACMP4

Bit 14: Timer A Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMCCMP3

Bit 15: Timer C Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMCCMP4

Bit 16: Timer C Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMDCMP3

Bit 17: Timer D Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMDCMP4

Bit 18: Timer D Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMECMP1

Bit 19: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMECMP2

Bit 20: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

EXTEVNT[1]

Bit 21: EXTEVNT1.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[2]

Bit 22: EXTEVNT2.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[3]

Bit 23: EXTEVNT3.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[4]

Bit 24: EXTEVNT4.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[5]

Bit 25: EXTEVNT5.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[6]

Bit 26: EXTEVNT6.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[7]

Bit 27: EXTEVNT7.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[8]

Bit 28: EXTEVNT8.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[9]

Bit 29: EXTEVNT9.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[10]

Bit 30: EXTEVNT10.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

UPDATE

Bit 31: UPDATE.

Allowed values:
0: NoEffect: Register update event has no effect
1: SetInactive: Register update event forces the output to its inactive state

EEFR1

Timerx External Event Filtering Register 1

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EE[5]FLTR
rw 		EE[5]LTCH
rw 		EE[4]FLTR
rw 		EE[4]LTCH
rw 		EE[3]FLTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EE[3]FLTR
rw 		EE[3]LTCH
rw 		EE[2]FLTR
rw 		EE[2]LTCH
rw 		EE[1]FLTR
rw 		EE[1]LTCH
rw
Toggle fields

EE[1]LTCH

Bit 0: External Event 1 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[1]FLTR

Bits 1-4: External Event 1 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[2]LTCH

Bit 6: External Event 2 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[2]FLTR

Bits 7-10: External Event 2 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[3]LTCH

Bit 12: External Event 3 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[3]FLTR

Bits 13-16: External Event 3 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[4]LTCH

Bit 18: External Event 4 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[4]FLTR

Bits 19-22: External Event 4 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[5]LTCH

Bit 24: External Event 5 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[5]FLTR

Bits 25-28: External Event 5 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EEFR2

Timerx External Event Filtering Register 2

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EE[10]FLTR
rw 		EE[10]LTCH
rw 		EE[9]FLTR
rw 		EE[9]LTCH
rw 		EE[8]FLTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EE[8]FLTR
rw 		EE[8]LTCH
rw 		EE[7]FLTR
rw 		EE[7]LTCH
rw 		EE[6]FLTR
rw 		EE[6]LTCH
rw
Toggle fields

EE[6]LTCH

Bit 0: External Event 6 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[6]FLTR

Bits 1-4: External Event 6 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[7]LTCH

Bit 6: External Event 7 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[7]FLTR

Bits 7-10: External Event 7 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[8]LTCH

Bit 12: External Event 8 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[8]FLTR

Bits 13-16: External Event 8 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[9]LTCH

Bit 18: External Event 9 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[9]FLTR

Bits 19-22: External Event 9 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[10]LTCH

Bit 24: External Event 10 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[10]FLTR

Bits 25-28: External Event 10 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

RSTR

TimerA Reset Register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

30/30 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIMECMP4
rw 		TIMECMP2
rw 		TIMECMP1
rw 		TIMDCMP4
rw 		TIMDCMP2
rw 		TIMDCMP1
rw 		TIMCCMP4
rw 		TIMCCMP2
rw 		TIMCCMP1
rw 		TIMACMP4
rw 		TIMACMP2
rw 		TIMACMP1
rw 		EXTEVNT10
rw 		EXTEVNT9
rw 		EXTEVNT8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTEVNT7
rw 		EXTEVNT6
rw 		EXTEVNT5
rw 		EXTEVNT4
rw 		EXTEVNT3
rw 		EXTEVNT2
rw 		EXTEVNT1
rw 		MSTCMP4
rw 		MSTCMP3
rw 		MSTCMP2
rw 		MSTCMP1
rw 		MSTPER
rw 		CMP4
rw 		CMP2
rw 		UPDT
rw
Toggle fields

UPDT

Bit 1: Timer A Update reset.

Allowed values:
0: NoEffect: Update event has no effect
1: ResetCounter: Timer X counter is reset upon update event

CMP2

Bit 2: Timer A compare 2 reset.

Allowed values:
0: NoEffect: Timer X compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer X compare Z event

CMP4

Bit 3: Timer A compare 4 reset.

Allowed values:
0: NoEffect: Timer X compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer X compare Z event

MSTPER

Bit 4: Master timer Period.

Allowed values:
0: NoEffect: Master timer period event has no effect
1: ResetCounter: Timer X counter is reset upon master timer period event

MSTCMP1

Bit 5: Master compare 1.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

MSTCMP2

Bit 6: Master compare 2.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

MSTCMP3

Bit 7: Master compare 3.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

MSTCMP4

Bit 8: Master compare 4.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

EXTEVNT1

Bit 9: External Event 1.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT2

Bit 10: External Event 2.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT3

Bit 11: External Event 3.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT4

Bit 12: External Event 4.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT5

Bit 13: External Event 5.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT6

Bit 14: External Event 6.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT7

Bit 15: External Event 7.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT8

Bit 16: External Event 8.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT9

Bit 17: External Event 9.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT10

Bit 18: External Event 10.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

TIMACMP1

Bit 19: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMACMP2

Bit 20: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMACMP4

Bit 21: Timer A Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMCCMP1

Bit 22: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMCCMP2

Bit 23: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMCCMP4

Bit 24: Timer C Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMDCMP1

Bit 25: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMDCMP2

Bit 26: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMDCMP4

Bit 27: Timer D Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMECMP1

Bit 28: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMECMP2

Bit 29: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMECMP4

Bit 30: Timer E Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

CHPR

Timerx Chopper Register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STRTPW
rw 		CARDTY
rw 		CARFRQ
rw
Toggle fields

CARFRQ

Bits 0-3: Timerx carrier frequency value.

Allowed values: 0x0-0xf

CARDTY

Bits 4-6: Timerx chopper duty cycle value.

Allowed values: 0x0-0x7

STRTPW

Bits 7-10: STRTPW.

Allowed values: 0x0-0xf

CPT1CR

Timerx Capture 2 Control Register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TECMP2
rw 		TECMP1
rw 		TE1RST
rw 		TE1SET
rw 		TDCMP2
rw 		TDCMP1
rw 		TD1RST
rw 		TD1SET
rw 		TCCMP2
rw 		TCCMP1
rw 		TC1RST
rw 		TC1SET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TACMP2
rw 		TACMP1
rw 		TA1RST
rw 		TA1SET
rw 		EXEV[10]CPT
rw 		EXEV[9]CPT
rw 		EXEV[8]CPT
rw 		EXEV[7]CPT
rw 		EXEV[6]CPT
rw 		EXEV[5]CPT
rw 		EXEV[4]CPT
rw 		EXEV[3]CPT
rw 		EXEV[2]CPT
rw 		EXEV[1]CPT
rw 		UPDCPT
rw 		SWCPT
rw
Toggle fields

SWCPT

Bit 0: Software Capture.

Allowed values:
0: NoEffect: No effect
1: TriggerCapture: Force capture Z

UPDCPT

Bit 1: Update Capture.

Allowed values:
0: NoEffect: Update event has no effect
1: TriggerCapture: Update event triggers capture Z

EXEV[1]CPT

Bit 2: External Event 1 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[2]CPT

Bit 3: External Event 2 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[3]CPT

Bit 4: External Event 3 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[4]CPT

Bit 5: External Event 4 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[5]CPT

Bit 6: External Event 5 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[6]CPT

Bit 7: External Event 6 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[7]CPT

Bit 8: External Event 7 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[8]CPT

Bit 9: External Event 8 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[9]CPT

Bit 10: External Event 9 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[10]CPT

Bit 11: External Event 10 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

TA1SET

Bit 12: Timer A output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TA1RST

Bit 13: Timer A output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TACMP1

Bit 14: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TACMP2

Bit 15: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TC1SET

Bit 20: Timer C output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TC1RST

Bit 21: Timer C output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TCCMP1

Bit 22: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TCCMP2

Bit 23: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TD1SET

Bit 24: Timer D output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TD1RST

Bit 25: Timer D output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TDCMP1

Bit 26: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TDCMP2

Bit 27: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TE1SET

Bit 28: Timer E output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TE1RST

Bit 29: Timer E output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TECMP1

Bit 30: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TECMP2

Bit 31: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

CPT2CR

CPT2xCR

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TECMP2
rw 		TECMP1
rw 		TE1RST
rw 		TE1SET
rw 		TDCMP2
rw 		TDCMP1
rw 		TD1RST
rw 		TD1SET
rw 		TCCMP2
rw 		TCCMP1
rw 		TC1RST
rw 		TC1SET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TACMP2
rw 		TACMP1
rw 		TA1RST
rw 		TA1SET
rw 		EXEV[10]CPT
rw 		EXEV[9]CPT
rw 		EXEV[8]CPT
rw 		EXEV[7]CPT
rw 		EXEV[6]CPT
rw 		EXEV[5]CPT
rw 		EXEV[4]CPT
rw 		EXEV[3]CPT
rw 		EXEV[2]CPT
rw 		EXEV[1]CPT
rw 		UPDCPT
rw 		SWCPT
rw
Toggle fields

SWCPT

Bit 0: Software Capture.

Allowed values:
0: NoEffect: No effect
1: TriggerCapture: Force capture Z

UPDCPT

Bit 1: Update Capture.

Allowed values:
0: NoEffect: Update event has no effect
1: TriggerCapture: Update event triggers capture Z

EXEV[1]CPT

Bit 2: External Event 1 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[2]CPT

Bit 3: External Event 2 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[3]CPT

Bit 4: External Event 3 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[4]CPT

Bit 5: External Event 4 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[5]CPT

Bit 6: External Event 5 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[6]CPT

Bit 7: External Event 6 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[7]CPT

Bit 8: External Event 7 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[8]CPT

Bit 9: External Event 8 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[9]CPT

Bit 10: External Event 9 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[10]CPT

Bit 11: External Event 10 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

TA1SET

Bit 12: Timer A output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TA1RST

Bit 13: Timer A output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TACMP1

Bit 14: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TACMP2

Bit 15: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TC1SET

Bit 20: Timer C output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TC1RST

Bit 21: Timer C output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TCCMP1

Bit 22: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TCCMP2

Bit 23: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TD1SET

Bit 24: Timer D output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TD1RST

Bit 25: Timer D output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TDCMP1

Bit 26: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TDCMP2

Bit 27: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TE1SET

Bit 28: Timer E output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TE1RST

Bit 29: Timer E output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TECMP1

Bit 30: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TECMP2

Bit 31: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

OUTR

Timerx Output Register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIDL2
rw 		CHP2
rw 		FAULT2
rw 		IDLES2
rw 		IDLEM2
rw 		POL2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYPRT
rw 		DLYPRTEN
rw 		DTEN
rw 		DIDL1
rw 		CHP1
rw 		FAULT1
rw 		IDLES1
rw 		IDLEM1
rw 		POL1
rw
Toggle fields

POL1

Bit 1: Output 1 polarity.

Allowed values:
0: ActiveHigh: Positive polarity (output active high)
1: ActiveLow: Negative polarity (output active low)

IDLEM1

Bit 2: Output 1 Idle mode.

Allowed values:
0: NoEffect: No action: the output is not affected by the burst mode operation
1: SetIdle: The output is in idle state when requested by the burst mode controller

IDLES1

Bit 3: Output 1 Idle State.

Allowed values:
0: Inactive: Output idle state is inactive
1: Active: Output idle state is active

FAULT1

Bits 4-5: Output 1 Fault state.

Allowed values:
0: Disabled: No action: the output is not affected by the fault input and stays in run mode
1: SetActive: Output goes to active state after a fault event
2: SetInactive: Output goes to inactive state after a fault event
3: SetHighZ: Output goes to high-z state after a fault event

CHP1

Bit 6: Output 1 Chopper enable.

Allowed values:
0: Disabled: Output signal not altered
1: Enabled: Output signal is chopped by a carrier signal

DIDL1

Bit 7: Output 1 Deadtime upon burst mode Idle entry.

Allowed values:
0: Disabled: The programmed idle state is applied immediately to the output
1: Enabled: Deadtime (inactive level) is inserted on output before entering the idle mode

DTEN

Bit 8: Deadtime enable.

Allowed values:
0: Disabled: Output 1 and 2 signals are independent
1: Enabled: Deadtime is inserted between output 1 and output 2

DLYPRTEN

Bit 9: Delayed Protection Enable.

Allowed values:
0: Disabled: No action
1: Enabled: Delayed protection is enabled, as per DLYPRT bits

DLYPRT

Bits 10-12: Delayed Protection.

Allowed values:
0: Output1_EE6: Output 1 delayed idle on external event 6
1: Output2_EE6: Output 2 delayed idle on external event 6
2: Output1_2_EE6: Output 1 and 2 delayed idle on external event 6
3: Balanced_EE6: Balanced idle on external event 6
4: Output1_EE7: Output 1 delayed idle on external event 7
5: Output2_EE7: Output 2 delayed idle on external event 7
6: Output1_2_EE7: Output 1 and 2 delayed idle on external event 7
7: Balanced_EE7: Balanced idle on external event 7

POL2

Bit 17: Output 2 polarity.

Allowed values:
0: ActiveHigh: Positive polarity (output active high)
1: ActiveLow: Negative polarity (output active low)

IDLEM2

Bit 18: Output 2 Idle mode.

Allowed values:
0: NoEffect: No action: the output is not affected by the burst mode operation
1: SetIdle: The output is in idle state when requested by the burst mode controller

IDLES2

Bit 19: Output 2 Idle State.

Allowed values:
0: Inactive: Output idle state is inactive
1: Active: Output idle state is active

FAULT2

Bits 20-21: Output 2 Fault state.

Allowed values:
0: Disabled: No action: the output is not affected by the fault input and stays in run mode
1: SetActive: Output goes to active state after a fault event
2: SetInactive: Output goes to inactive state after a fault event
3: SetHighZ: Output goes to high-z state after a fault event

CHP2

Bit 22: Output 2 Chopper enable.

Allowed values:
0: Disabled: Output signal not altered
1: Enabled: Output signal is chopped by a carrier signal

DIDL2

Bit 23: Output 2 Deadtime upon burst mode Idle entry.

Allowed values:
0: Disabled: The programmed idle state is applied immediately to the output
1: Enabled: Deadtime (inactive level) is inserted on output before entering the idle mode

FLTR

Timerx Fault Register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLTLCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLT[5]EN
rw 		FLT[4]EN
rw 		FLT[3]EN
rw 		FLT[2]EN
rw 		FLT[1]EN
rw
Toggle fields

FLT[1]EN

Bit 0: Fault 1 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[2]EN

Bit 1: Fault 2 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[3]EN

Bit 2: Fault 3 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[4]EN

Bit 3: Fault 4 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[5]EN

Bit 4: Fault 5 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLTLCK

Bit 31: Fault sources Lock.

Allowed values:
0: Unlocked: FLT1EN..FLT5EN bits are read/write
1: Locked: FLT1EN..FLT5EN bits are read only

HRTIM_TIMC

0x40017580: High Resolution Timer: TIMC

359/359 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 ISR
0x8 ICR
0xc DIER
0x10 CNTR
0x14 PERR
0x18 REPR
0x1c CMP1R
0x20 CMP1CR
0x24 CMP2R
0x28 CMP3R
0x2c CMP4R
0x30 CPT1R
0x34 CPT2R
0x38 DTR
0x3c SET1R
0x40 RST1R
0x44 SET2R
0x48 RST2R
0x4c EEFR1
0x50 EEFR2
0x54 RSTR
0x58 CHPR
0x5c CPT1CR
0x60 CPT2CR
0x64 OUTR
0x68 FLTR
Toggle registers

CR

Timerx Control Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPDGAT
rw 		PREEN
rw 		DACSYNC
rw 		MSTU
rw 		TEU
rw 		TDU
rw 		TCU
rw 		TBU
rw 		TRSTU
rw 		TREPU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DELCMP4
rw 		DELCMP2
rw 		SYNCSTRT
rw 		SYNCRST
rw 		PSHPLL
rw 		HALF
rw 		RETRIG
rw 		CONT
rw 		CKPSC
rw
Toggle fields

CKPSC

Bits 0-2: HRTIM Timer x Clock prescaler.

Allowed values: 0x0-0x7

CONT

Bit 3: Continuous mode.

Allowed values:
0: SingleShot: The timer operates in single-shot mode and stops when it reaches the TIMxPER value
1: Continuous: The timer operates in continuous (free-running) mode and rolls over to zero when it reaches the TIMxPER value

RETRIG

Bit 4: Re-triggerable mode.

Allowed values:
0: Disabled: The timer is not re-triggerable: a counter reset can be done only if the counter is stopped
1: Enabled: The timer is retriggerable: a counter reset is done whatever the counter state

HALF

Bit 5: Half mode enable.

Allowed values:
0: Disabled: Half mode disabled
1: Enabled: Half mode enabled

PSHPLL

Bit 6: Push-Pull mode enable.

Allowed values:
0: Disabled: Push-pull mode disabled
1: Enabled: Push-pull mode enabled

SYNCRST

Bit 10: Synchronization Resets Timer x.

Allowed values:
0: Disabled: Synchronization event has no effect on Timer x
1: Reset: Synchronization event resets Timer x

SYNCSTRT

Bit 11: Synchronization Starts Timer x.

Allowed values:
0: Disabled: Synchronization event has no effect on Timer x
1: Start: Synchronization event starts Timer x

DELCMP2

Bits 12-13: Delayed CMP2 mode.

Allowed values:
0: Standard: CMP2 register is always active (standard compare mode)
1: Capture1: CMP2 is recomputed and is active following a capture 1 event
2: Capture1_Compare1: CMP2 is recomputed and is active following a capture 1 event or a Compare 1 match
3: Capture1_Compare3: CMP2 is recomputed and is active following a capture 1 event or a Compare 3 match

DELCMP4

Bits 14-15: Delayed CMP4 mode.

Allowed values:
0: Standard: CMP4 register is always active (standard compare mode)
1: Capture2: CMP4 is recomputed and is active following a capture 2 event
2: Capture2_Compare1: CMP4 is recomputed and is active following a capture 2 event or a Compare 1 match
3: Capture_Compare3: CMP4 is recomputed and is active following a capture event or a Compare 3 match

TREPU

Bit 17: Timer x Repetition update.

Allowed values:
0: Disabled: Update by timer x repetition disabled
1: Enabled: Update by timer x repetition enabled

TRSTU

Bit 18: Timerx reset update.

Allowed values:
0: Disabled: Update by timer x reset/roll-over disabled
1: Enabled: Update by timer x reset/roll-over enabled

TBU

Bit 20: TBU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

TCU

Bit 21: TCU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

TDU

Bit 22: TDU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

TEU

Bit 23: TEU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

MSTU

Bit 24: Master Timer update.

Allowed values:
0: Disabled: Update by master timer disabled
1: Enabled: Update by master timer enabled

DACSYNC

Bits 25-26: AC Synchronization.

Allowed values:
0: Disabled: No DAC trigger generated
1: DACSync1: Trigger generated on DACSync1
2: DACSync2: Trigger generated on DACSync2
3: DACSync3: Trigger generated on DACSync3

PREEN

Bit 27: Preload enable.

Allowed values:
0: Disabled: Preload disabled: the write access is directly done into the active register
1: Enabled: Preload enabled: the write access is done into the preload register

UPDGAT

Bits 28-31: Update Gating.

Allowed values:
0: Independent: Update occurs independently from the DMA burst transfer
1: DMABurst: Update occurs when the DMA burst transfer is completed
2: DMABurst_Update: Update occurs on the update event following DMA burst transfer completion
3: Input1: Update occurs on a rising edge of HRTIM update enable input 1
4: Input2: Update occurs on a rising edge of HRTIM update enable input 2
5: Input3: Update occurs on a rising edge of HRTIM update enable input 3
6: Input1_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 1
7: Input2_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 2
8: Input3_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 3

ISR

Timerx Interrupt Status Register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
O2CPY
r 		O1CPY
r 		O2STAT
r 		O1STAT
r 		IPPSTAT
r 		CPPSTAT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYPRT
r 		RST
r 		RST2
r 		SET[2]
r 		RST1
r 		SET[1]
r 		CPT[2]
r 		CPT[1]
r 		UPD
r 		REP
r 		CMP[4]
r 		CMP[3]
r 		CMP[2]
r 		CMP[1]
r
Toggle fields

CMP[1]

Bit 0: Compare 1 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

CMP[2]

Bit 1: Compare 2 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

CMP[3]

Bit 2: Compare 3 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

CMP[4]

Bit 3: Compare 4 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

REP

Bit 4: Repetition Interrupt Flag.

Allowed values:
0: NoEvent: No timer repetition interrupt occurred
1: Event: Timer repetition interrupt occurred

UPD

Bit 6: Update Interrupt Flag.

Allowed values:
0: NoEvent: No timer update interrupt occurred
1: Event: Timer update interrupt occurred

CPT[1]

Bit 7: Capture1 Interrupt Flag.

Allowed values:
0: NoEvent: No timer x capture reset interrupt occurred
1: Event: Timer x capture reset interrupt occurred

CPT[2]

Bit 8: Capture2 Interrupt Flag.

Allowed values:
0: NoEvent: No timer x capture reset interrupt occurred
1: Event: Timer x capture reset interrupt occurred

SET[1]

Bit 9: Output 1 Set Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output set interrupt occurred
1: Event: Tx output set interrupt occurred

RST1

Bit 10: Output 1 Reset Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output reset interrupt occurred
1: Event: Tx output reset interrupt occurred

SET[2]

Bit 11: Output 2 Set Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output set interrupt occurred
1: Event: Tx output set interrupt occurred

RST2

Bit 12: Output 2 Reset Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output reset interrupt occurred
1: Event: Tx output reset interrupt occurred

RST

Bit 13: Reset Interrupt Flag.

Allowed values:
0: NoEvent: No TIMx counter reset/roll-over interrupt occurred
1: Event: TIMx counter reset/roll-over interrupt occurred

DLYPRT

Bit 14: Delayed Protection Flag.

Allowed values:
0: Inactive: Not in delayed idle or balanced idle mode
1: Active: Delayed idle or balanced idle mode entry

CPPSTAT

Bit 16: Current Push Pull Status.

Allowed values:
0: Output1Active: Signal applied on output 1 and output 2 forced inactive
1: Output2Active: Signal applied on output 2 and output 1 forced inactive

IPPSTAT

Bit 17: Idle Push Pull Status.

Allowed values:
0: Output1Active: Protection occurred when the output 1 was active and output 2 forced inactive
1: Output2Active: Protection occurred when the output 2 was active and output 1 forced inactive

O1STAT

Bit 18: Output 1 State.

Allowed values:
0: Inactive: Output was inactive
1: Active: Output was active

O2STAT

Bit 19: Output 2 State.

Allowed values:
0: Inactive: Output was inactive
1: Active: Output was active

O1CPY

Bit 20: Output 1 Copy.

Allowed values:
0: Inactive: Output is inactive
1: Active: Output is active

O2CPY

Bit 21: Output 2 Copy.

Allowed values:
0: Inactive: Output is inactive
1: Active: Output is active

ICR

Timerx Interrupt Clear Register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

14/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYPRTC
w 		RSTC
w 		RST2C
w 		SET[2]C
w 		RST1C
w 		SET[1]C
w 		CPT[2]C
w 		CPT[1]C
w 		UPDC
w 		REPC
w 		CMP[4]C
w 		CMP[3]C
w 		CMP[2]C
w 		CMP[1]C
w
Toggle fields

CMP[1]C

Bit 0: Compare 1 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CMP[2]C

Bit 1: Compare 2 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CMP[3]C

Bit 2: Compare 3 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CMP[4]C

Bit 3: Compare 4 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

REPC

Bit 4: Repetition Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

UPDC

Bit 6: Update Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CPT[1]C

Bit 7: Capture1 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CPT[2]C

Bit 8: Capture2 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

SET[1]C

Bit 9: Output 1 Set flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

RST1C

Bit 10: Output 1 Reset flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

SET[2]C

Bit 11: Output 2 Set flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

RST2C

Bit 12: Output 2 Reset flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

RSTC

Bit 13: Reset Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

DLYPRTC

Bit 14: Delayed Protection Flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

DIER

TIMxDIER5

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLYPRTDE
rw 		RSTDE
rw 		RST2DE
rw 		SET[2]DE
rw 		RST1DE
rw 		SET[1]DE
rw 		CPT[2]DE
rw 		CPT[1]DE
rw 		UPDDE
rw 		REPDE
rw 		CMP[4]DE
rw 		CMP[3]DE
rw 		CMP[2]DE
rw 		CMP[1]DE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYPRTIE
rw 		RSTIE
rw 		RST2IE
rw 		SET[2]IE
rw 		RST1IE
rw 		SET[1]IE
rw 		CPT[2]IE
rw 		CPT[1]IE
rw 		UPDIE
rw 		REPIE
rw 		CMP[4]IE
rw 		CMP[3]IE
rw 		CMP[2]IE
rw 		CMP[1]IE
rw
Toggle fields

CMP[1]IE

Bit 0: CMP1IE.

Allowed values:
0: Disabled: Compare interrupt disabled
1: Enabled: Compare interrupt enabled

CMP[2]IE

Bit 1: CMP2IE.

Allowed values:
0: Disabled: Compare interrupt disabled
1: Enabled: Compare interrupt enabled

CMP[3]IE

Bit 2: CMP3IE.

Allowed values:
0: Disabled: Compare interrupt disabled
1: Enabled: Compare interrupt enabled

CMP[4]IE

Bit 3: CMP4IE.

Allowed values:
0: Disabled: Compare interrupt disabled
1: Enabled: Compare interrupt enabled

REPIE

Bit 4: REPIE.

Allowed values:
0: Disabled: Repetition interrupt disabled
1: Enabled: Repetition interrupt enabled

UPDIE

Bit 6: UPDIE.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CPT[1]IE

Bit 7: CPT1IE.

Allowed values:
0: Disabled: Capture interrupt disabled
1: Enabled: Capture interrupt enabled

CPT[2]IE

Bit 8: CPT2IE.

Allowed values:
0: Disabled: Capture interrupt disabled
1: Enabled: Capture interrupt enabled

SET[1]IE

Bit 9: Output 1 set interrupt enable.

Allowed values:
0: Disabled: Tx output set interrupt disabled
1: Enabled: Tx output set interrupt enabled

RST1IE

Bit 10: RSTx1IE.

Allowed values:
0: Disabled: Tx output reset interrupt disabled
1: Enabled: Tx output reset interrupt enabled

SET[2]IE

Bit 11: Output 2 set interrupt enable.

Allowed values:
0: Disabled: Tx output set interrupt disabled
1: Enabled: Tx output set interrupt enabled

RST2IE

Bit 12: RSTx2IE.

Allowed values:
0: Disabled: Tx output reset interrupt disabled
1: Enabled: Tx output reset interrupt enabled

RSTIE

Bit 13: RSTIE.

Allowed values:
0: Disabled: Timer x counter/reset roll-over interrupt disabled
1: Enabled: Timer x counter/reset roll-over interrupt enabled

DLYPRTIE

Bit 14: DLYPRTIE.

Allowed values:
0: Disabled: Delayed protection interrupt disabled
1: Enabled: Delayed protection interrupt enabled

CMP[1]DE

Bit 16: CMP1DE.

Allowed values:
0: Disabled: Compare DMA request disabled
1: Enabled: Compare DMA request enabled

CMP[2]DE

Bit 17: CMP2DE.

Allowed values:
0: Disabled: Compare DMA request disabled
1: Enabled: Compare DMA request enabled

CMP[3]DE

Bit 18: CMP3DE.

Allowed values:
0: Disabled: Compare DMA request disabled
1: Enabled: Compare DMA request enabled

CMP[4]DE

Bit 19: CMP4DE.

Allowed values:
0: Disabled: Compare DMA request disabled
1: Enabled: Compare DMA request enabled

REPDE

Bit 20: REPDE.

Allowed values:
0: Disabled: Repetition DMA request disabled
1: Enabled: Repetition DMA request enabled

UPDDE

Bit 22: UPDDE.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CPT[1]DE

Bit 23: CPT1DE.

Allowed values:
0: Disabled: Capture DMA request disabled
1: Enabled: Capture DMA request enabled

CPT[2]DE

Bit 24: CPT2DE.

Allowed values:
0: Disabled: Capture DMA request disabled
1: Enabled: Capture DMA request enabled

SET[1]DE

Bit 25: Output 1 set DMA request enable.

Allowed values:
0: Disabled: Tx output set DMA request disabled
1: Enabled: Tx output set DMA request enabled

RST1DE

Bit 26: RSTx1DE.

Allowed values:
0: Disabled: Tx output reset DMA request disabled
1: Enabled: Tx output reset DMA request enabled

SET[2]DE

Bit 27: Output 2 set DMA request enable.

Allowed values:
0: Disabled: Tx output set DMA request disabled
1: Enabled: Tx output set DMA request enabled

RST2DE

Bit 28: RSTx2DE.

Allowed values:
0: Disabled: Tx output reset DMA request disabled
1: Enabled: Tx output reset DMA request enabled

RSTDE

Bit 29: RSTDE.

Allowed values:
0: Disabled: Timer x counter reset/roll-over DMA request disabled
1: Enabled: Timer x counter reset/roll-over DMA request enabled

DLYPRTDE

Bit 30: DLYPRTDE.

Allowed values:
0: Disabled: Delayed protection DMA request disabled
1: Enabled: Delayed protection DMA request enabled

CNTR

Timerx Counter Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: Counter value.

Allowed values: 0x0-0xffff

PERR

Timerx Period Register

Offset: 0x14, size: 32, reset: 0x0000FFFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PER
rw
Toggle fields

PER

Bits 0-15: Master Timer Period value.

Allowed values: 0x0-0xffff

REPR

Timerx Repetition Register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Master Timer Repetition counter value.

Allowed values: 0x0-0xff

CMP1R

Timerx Compare 1 Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CMP1CR

Timerx Compare 1 Compound Register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP1
rw
Toggle fields

CMP1

Bits 0-15: Timerx Compare 1 value.

Allowed values: 0x0-0xffff

REP

Bits 16-23: Timerx Repetition value (aliased from HRTIM_REPx register).

Allowed values: 0x0-0xff

CMP2R

Timerx Compare 2 Register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CMP3R

Timerx Compare 3 Register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CMP4R

Timerx Compare 4 Register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CPT1R

Timerx Capture 1 Register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPT
r
Toggle fields

CPT

Bits 0-15: Timerx Capture 1 value.

Allowed values: 0x0-0xffff

CPT2R

Timerx Capture 2 Register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPT
r
Toggle fields

CPT

Bits 0-15: Timerx Capture 1 value.

Allowed values: 0x0-0xffff

DTR

Timerx Deadtime Register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTFLK
rw 		DTFSLK
rw 		SDTF
rw 		DTF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTRLK
rw 		DTRSLK
rw 		DTPRSC
rw 		SDTR
rw 		DTR
rw
Toggle fields

DTR

Bits 0-8: Deadtime Rising value.

Allowed values: 0x0-0x1ff

SDTR

Bit 9: Sign Deadtime Rising value.

Allowed values:
0: Positive: Positive deadtime on rising edge
1: Negative: Negative deadtime on rising edge

DTPRSC

Bits 10-12: Deadtime Prescaler.

Allowed values: 0x0-0x7

DTRSLK

Bit 14: Deadtime Rising Sign Lock.

Allowed values:
0: Unlocked: Deadtime rising sign is writable
1: Locked: Deadtime rising sign is read-only

DTRLK

Bit 15: Deadtime Rising Lock.

Allowed values:
0: Unlocked: Deadtime rising value and sign is writable
1: Locked: Deadtime rising value and sign is read-only

DTF

Bits 16-24: Deadtime Falling value.

Allowed values: 0x0-0x1ff

SDTF

Bit 25: Sign Deadtime Falling value.

Allowed values:
0: Positive: Positive deadtime on falling edge
1: Negative: Negative deadtime on falling edge

DTFSLK

Bit 30: Deadtime Falling Sign Lock.

Allowed values:
0: Unlocked: Deadtime falling sign is writable
1: Locked: Deadtime falling sign is read-only

DTFLK

Bit 31: Deadtime Falling Lock.

Allowed values:
0: Unlocked: Deadtime falling value and sign is writable
1: Locked: Deadtime falling value and sign is read-only

SET1R

Timerx Output1 Set Register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPDATE
rw 		EXTEVNT[10]
rw 		EXTEVNT[9]
rw 		EXTEVNT[8]
rw 		EXTEVNT[7]
rw 		EXTEVNT[6]
rw 		EXTEVNT[5]
rw 		EXTEVNT[4]
rw 		EXTEVNT[3]
rw 		EXTEVNT[2]
rw 		EXTEVNT[1]
rw 		TIMECMP4
rw 		TIMECMP3
rw 		TIMECMP2
rw 		TIMDCMP4
rw 		TIMDCMP2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMBCMP3
rw 		TIMBCMP2
rw 		TIMACMP3
rw 		TIMACMP2
rw 		MSTCMP[4]
rw 		MSTCMP[3]
rw 		MSTCMP[2]
rw 		MSTCMP[1]
rw 		MSTPER
rw 		CMP[4]
rw 		CMP[3]
rw 		CMP[2]
rw 		CMP[1]
rw 		PER
rw 		RESYNC
rw 		SST
rw
Toggle fields

SST

Bit 0: Software Set trigger.

Allowed values:
0: NoEffect: No effect
1: SetActive: Force output to its active state

RESYNC

Bit 1: Timer A resynchronizaton.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetActive: Timer reset event coming solely from software or SYNC input event forces the output to its active state

PER

Bit 2: Timer A Period.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetActive: Timer period event forces the output to its active state

CMP[1]

Bit 3: Timer A compare 1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[2]

Bit 4: Timer A compare 2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[3]

Bit 5: Timer A compare 3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[4]

Bit 6: Timer A compare 4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

MSTPER

Bit 7: Master Period.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetActive: Master timer counter roll-over/reset forces the output to its active state

MSTCMP[1]

Bit 8: Master Compare 1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[2]

Bit 9: Master Compare 2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[3]

Bit 10: Master Compare 3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[4]

Bit 11: Master Compare 4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

TIMACMP2

Bit 12: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMACMP3

Bit 13: Timer A Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMBCMP2

Bit 14: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMBCMP3

Bit 15: Timer B Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMDCMP2

Bit 16: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMDCMP4

Bit 17: Timer D Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMECMP2

Bit 18: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMECMP3

Bit 19: Timer E Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMECMP4

Bit 20: Timer E Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

EXTEVNT[1]

Bit 21: External Event 1.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[2]

Bit 22: External Event 2.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[3]

Bit 23: External Event 3.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[4]

Bit 24: External Event 4.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[5]

Bit 25: External Event 5.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[6]

Bit 26: External Event 6.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[7]

Bit 27: External Event 7.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[8]

Bit 28: External Event 8.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[9]

Bit 29: External Event 9.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[10]

Bit 30: External Event 10.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

UPDATE

Bit 31: Registers update (transfer preload to active).

Allowed values:
0: NoEffect: Register update event has no effect
1: SetActive: Register update event forces the output to its active state

RST1R

Timerx Output1 Reset Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPDATE
rw 		EXTEVNT[10]
rw 		EXTEVNT[9]
rw 		EXTEVNT[8]
rw 		EXTEVNT[7]
rw 		EXTEVNT[6]
rw 		EXTEVNT[5]
rw 		EXTEVNT[4]
rw 		EXTEVNT[3]
rw 		EXTEVNT[2]
rw 		EXTEVNT[1]
rw 		TIMECMP4
rw 		TIMECMP3
rw 		TIMECMP2
rw 		TIMDCMP4
rw 		TIMDCMP2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMBCMP3
rw 		TIMBCMP2
rw 		TIMACMP3
rw 		TIMACMP2
rw 		MSTCMP[4]
rw 		MSTCMP[3]
rw 		MSTCMP[2]
rw 		MSTCMP[1]
rw 		MSTPER
rw 		CMP[4]
rw 		CMP[3]
rw 		CMP[2]
rw 		CMP[1]
rw 		PER
rw 		RESYNC
rw 		SRT
rw
Toggle fields

SRT

Bit 0: SRT.

Allowed values:
0: NoEffect: No effect
1: SetInactive: Force output to its inactive state

RESYNC

Bit 1: RESYNC.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetInactive: Timer reset event coming solely from software or SYNC input event forces the output to its inactive state

PER

Bit 2: PER.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetInactive: Timer period event forces the output to its inactive state

CMP[1]

Bit 3: CMP1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[2]

Bit 4: CMP2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[3]

Bit 5: CMP3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[4]

Bit 6: CMP4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

MSTPER

Bit 7: MSTPER.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetInactive: Master timer counter roll-over/reset forces the output to its inactive state

MSTCMP[1]

Bit 8: MSTCMP1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[2]

Bit 9: MSTCMP2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[3]

Bit 10: MSTCMP3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[4]

Bit 11: MSTCMP4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

TIMACMP2

Bit 12: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMACMP3

Bit 13: Timer A Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMBCMP2

Bit 14: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMBCMP3

Bit 15: Timer B Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMDCMP2

Bit 16: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMDCMP4

Bit 17: Timer D Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMECMP2

Bit 18: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMECMP3

Bit 19: Timer E Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMECMP4

Bit 20: Timer E Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

EXTEVNT[1]

Bit 21: EXTEVNT1.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[2]

Bit 22: EXTEVNT2.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[3]

Bit 23: EXTEVNT3.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[4]

Bit 24: EXTEVNT4.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[5]

Bit 25: EXTEVNT5.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[6]

Bit 26: EXTEVNT6.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[7]

Bit 27: EXTEVNT7.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[8]

Bit 28: EXTEVNT8.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[9]

Bit 29: EXTEVNT9.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[10]

Bit 30: EXTEVNT10.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

UPDATE

Bit 31: UPDATE.

Allowed values:
0: NoEffect: Register update event has no effect
1: SetInactive: Register update event forces the output to its inactive state

SET2R

Timerx Output2 Set Register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPDATE
rw 		EXTEVNT[10]
rw 		EXTEVNT[9]
rw 		EXTEVNT[8]
rw 		EXTEVNT[7]
rw 		EXTEVNT[6]
rw 		EXTEVNT[5]
rw 		EXTEVNT[4]
rw 		EXTEVNT[3]
rw 		EXTEVNT[2]
rw 		EXTEVNT[1]
rw 		TIMECMP4
rw 		TIMECMP3
rw 		TIMECMP2
rw 		TIMDCMP4
rw 		TIMDCMP2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMBCMP3
rw 		TIMBCMP2
rw 		TIMACMP3
rw 		TIMACMP2
rw 		MSTCMP[4]
rw 		MSTCMP[3]
rw 		MSTCMP[2]
rw 		MSTCMP[1]
rw 		MSTPER
rw 		CMP[4]
rw 		CMP[3]
rw 		CMP[2]
rw 		CMP[1]
rw 		PER
rw 		RESYNC
rw 		SST
rw
Toggle fields

SST

Bit 0: Software Set trigger.

Allowed values:
0: NoEffect: No effect
1: SetActive: Force output to its active state

RESYNC

Bit 1: Timer A resynchronizaton.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetActive: Timer reset event coming solely from software or SYNC input event forces the output to its active state

PER

Bit 2: Timer A Period.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetActive: Timer period event forces the output to its active state

CMP[1]

Bit 3: Timer A compare 1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[2]

Bit 4: Timer A compare 2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[3]

Bit 5: Timer A compare 3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[4]

Bit 6: Timer A compare 4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

MSTPER

Bit 7: Master Period.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetActive: Master timer counter roll-over/reset forces the output to its active state

MSTCMP[1]

Bit 8: Master Compare 1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[2]

Bit 9: Master Compare 2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[3]

Bit 10: Master Compare 3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[4]

Bit 11: Master Compare 4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

TIMACMP2

Bit 12: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMACMP3

Bit 13: Timer A Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMBCMP2

Bit 14: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMBCMP3

Bit 15: Timer B Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMDCMP2

Bit 16: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMDCMP4

Bit 17: Timer D Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMECMP2

Bit 18: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMECMP3

Bit 19: Timer E Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMECMP4

Bit 20: Timer E Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

EXTEVNT[1]

Bit 21: External Event 1.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[2]

Bit 22: External Event 2.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[3]

Bit 23: External Event 3.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[4]

Bit 24: External Event 4.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[5]

Bit 25: External Event 5.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[6]

Bit 26: External Event 6.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[7]

Bit 27: External Event 7.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[8]

Bit 28: External Event 8.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[9]

Bit 29: External Event 9.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[10]

Bit 30: External Event 10.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

UPDATE

Bit 31: Registers update (transfer preload to active).

Allowed values:
0: NoEffect: Register update event has no effect
1: SetActive: Register update event forces the output to its active state

RST2R

Timerx Output2 Reset Register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPDATE
rw 		EXTEVNT[10]
rw 		EXTEVNT[9]
rw 		EXTEVNT[8]
rw 		EXTEVNT[7]
rw 		EXTEVNT[6]
rw 		EXTEVNT[5]
rw 		EXTEVNT[4]
rw 		EXTEVNT[3]
rw 		EXTEVNT[2]
rw 		EXTEVNT[1]
rw 		TIMECMP4
rw 		TIMECMP3
rw 		TIMECMP2
rw 		TIMDCMP4
rw 		TIMDCMP2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMBCMP3
rw 		TIMBCMP2
rw 		TIMACMP3
rw 		TIMACMP2
rw 		MSTCMP[4]
rw 		MSTCMP[3]
rw 		MSTCMP[2]
rw 		MSTCMP[1]
rw 		MSTPER
rw 		CMP[4]
rw 		CMP[3]
rw 		CMP[2]
rw 		CMP[1]
rw 		PER
rw 		RESYNC
rw 		SRT
rw
Toggle fields

SRT

Bit 0: SRT.

Allowed values:
0: NoEffect: No effect
1: SetInactive: Force output to its inactive state

RESYNC

Bit 1: RESYNC.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetInactive: Timer reset event coming solely from software or SYNC input event forces the output to its inactive state

PER

Bit 2: PER.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetInactive: Timer period event forces the output to its inactive state

CMP[1]

Bit 3: CMP1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[2]

Bit 4: CMP2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[3]

Bit 5: CMP3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[4]

Bit 6: CMP4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

MSTPER

Bit 7: MSTPER.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetInactive: Master timer counter roll-over/reset forces the output to its inactive state

MSTCMP[1]

Bit 8: MSTCMP1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[2]

Bit 9: MSTCMP2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[3]

Bit 10: MSTCMP3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[4]

Bit 11: MSTCMP4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

TIMACMP2

Bit 12: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMACMP3

Bit 13: Timer A Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMBCMP2

Bit 14: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMBCMP3

Bit 15: Timer B Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMDCMP2

Bit 16: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMDCMP4

Bit 17: Timer D Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMECMP2

Bit 18: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMECMP3

Bit 19: Timer E Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMECMP4

Bit 20: Timer E Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

EXTEVNT[1]

Bit 21: EXTEVNT1.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[2]

Bit 22: EXTEVNT2.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[3]

Bit 23: EXTEVNT3.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[4]

Bit 24: EXTEVNT4.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[5]

Bit 25: EXTEVNT5.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[6]

Bit 26: EXTEVNT6.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[7]

Bit 27: EXTEVNT7.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[8]

Bit 28: EXTEVNT8.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[9]

Bit 29: EXTEVNT9.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[10]

Bit 30: EXTEVNT10.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

UPDATE

Bit 31: UPDATE.

Allowed values:
0: NoEffect: Register update event has no effect
1: SetInactive: Register update event forces the output to its inactive state

EEFR1

Timerx External Event Filtering Register 1

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EE[5]FLTR
rw 		EE[5]LTCH
rw 		EE[4]FLTR
rw 		EE[4]LTCH
rw 		EE[3]FLTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EE[3]FLTR
rw 		EE[3]LTCH
rw 		EE[2]FLTR
rw 		EE[2]LTCH
rw 		EE[1]FLTR
rw 		EE[1]LTCH
rw
Toggle fields

EE[1]LTCH

Bit 0: External Event 1 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[1]FLTR

Bits 1-4: External Event 1 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[2]LTCH

Bit 6: External Event 2 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[2]FLTR

Bits 7-10: External Event 2 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[3]LTCH

Bit 12: External Event 3 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[3]FLTR

Bits 13-16: External Event 3 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[4]LTCH

Bit 18: External Event 4 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[4]FLTR

Bits 19-22: External Event 4 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[5]LTCH

Bit 24: External Event 5 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[5]FLTR

Bits 25-28: External Event 5 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EEFR2

Timerx External Event Filtering Register 2

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EE[10]FLTR
rw 		EE[10]LTCH
rw 		EE[9]FLTR
rw 		EE[9]LTCH
rw 		EE[8]FLTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EE[8]FLTR
rw 		EE[8]LTCH
rw 		EE[7]FLTR
rw 		EE[7]LTCH
rw 		EE[6]FLTR
rw 		EE[6]LTCH
rw
Toggle fields

EE[6]LTCH

Bit 0: External Event 6 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[6]FLTR

Bits 1-4: External Event 6 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[7]LTCH

Bit 6: External Event 7 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[7]FLTR

Bits 7-10: External Event 7 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[8]LTCH

Bit 12: External Event 8 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[8]FLTR

Bits 13-16: External Event 8 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[9]LTCH

Bit 18: External Event 9 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[9]FLTR

Bits 19-22: External Event 9 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[10]LTCH

Bit 24: External Event 10 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[10]FLTR

Bits 25-28: External Event 10 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

RSTR

TimerA Reset Register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

30/30 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIMECMP4
rw 		TIMECMP2
rw 		TIMECMP1
rw 		TIMDCMP4
rw 		TIMDCMP2
rw 		TIMDCMP1
rw 		TIMBCMP4
rw 		TIMBCMP2
rw 		TIMBCMP1
rw 		TIMACMP4
rw 		TIMACMP2
rw 		TIMACMP1
rw 		EXTEVNT10
rw 		EXTEVNT9
rw 		EXTEVNT8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTEVNT7
rw 		EXTEVNT6
rw 		EXTEVNT5
rw 		EXTEVNT4
rw 		EXTEVNT3
rw 		EXTEVNT2
rw 		EXTEVNT1
rw 		MSTCMP4
rw 		MSTCMP3
rw 		MSTCMP2
rw 		MSTCMP1
rw 		MSTPER
rw 		CMP4
rw 		CMP2
rw 		UPDT
rw
Toggle fields

UPDT

Bit 1: Timer A Update reset.

Allowed values:
0: NoEffect: Update event has no effect
1: ResetCounter: Timer X counter is reset upon update event

CMP2

Bit 2: Timer A compare 2 reset.

Allowed values:
0: NoEffect: Timer X compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer X compare Z event

CMP4

Bit 3: Timer A compare 4 reset.

Allowed values:
0: NoEffect: Timer X compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer X compare Z event

MSTPER

Bit 4: Master timer Period.

Allowed values:
0: NoEffect: Master timer period event has no effect
1: ResetCounter: Timer X counter is reset upon master timer period event

MSTCMP1

Bit 5: Master compare 1.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

MSTCMP2

Bit 6: Master compare 2.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

MSTCMP3

Bit 7: Master compare 3.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

MSTCMP4

Bit 8: Master compare 4.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

EXTEVNT1

Bit 9: External Event 1.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT2

Bit 10: External Event 2.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT3

Bit 11: External Event 3.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT4

Bit 12: External Event 4.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT5

Bit 13: External Event 5.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT6

Bit 14: External Event 6.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT7

Bit 15: External Event 7.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT8

Bit 16: External Event 8.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT9

Bit 17: External Event 9.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT10

Bit 18: External Event 10.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

TIMACMP1

Bit 19: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMACMP2

Bit 20: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMACMP4

Bit 21: Timer A Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMBCMP1

Bit 22: Timer B Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMBCMP2

Bit 23: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMBCMP4

Bit 24: Timer B Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMDCMP1

Bit 25: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMDCMP2

Bit 26: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMDCMP4

Bit 27: Timer D Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMECMP1

Bit 28: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMECMP2

Bit 29: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMECMP4

Bit 30: Timer E Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

CHPR

Timerx Chopper Register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STRTPW
rw 		CARDTY
rw 		CARFRQ
rw
Toggle fields

CARFRQ

Bits 0-3: Timerx carrier frequency value.

Allowed values: 0x0-0xf

CARDTY

Bits 4-6: Timerx chopper duty cycle value.

Allowed values: 0x0-0x7

STRTPW

Bits 7-10: STRTPW.

Allowed values: 0x0-0xf

CPT1CR

Timerx Capture 2 Control Register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TECMP2
rw 		TECMP1
rw 		TE1RST
rw 		TE1SET
rw 		TDCMP2
rw 		TDCMP1
rw 		TD1RST
rw 		TD1SET
rw 		TBCMP2
rw 		TBCMP1
rw 		TB1RST
rw 		TB1SET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TACMP2
rw 		TACMP1
rw 		TA1RST
rw 		TA1SET
rw 		EXEV[10]CPT
rw 		EXEV[9]CPT
rw 		EXEV[8]CPT
rw 		EXEV[7]CPT
rw 		EXEV[6]CPT
rw 		EXEV[5]CPT
rw 		EXEV[4]CPT
rw 		EXEV[3]CPT
rw 		EXEV[2]CPT
rw 		EXEV[1]CPT
rw 		UPDCPT
rw 		SWCPT
rw
Toggle fields

SWCPT

Bit 0: Software Capture.

Allowed values:
0: NoEffect: No effect
1: TriggerCapture: Force capture Z

UPDCPT

Bit 1: Update Capture.

Allowed values:
0: NoEffect: Update event has no effect
1: TriggerCapture: Update event triggers capture Z

EXEV[1]CPT

Bit 2: External Event 1 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[2]CPT

Bit 3: External Event 2 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[3]CPT

Bit 4: External Event 3 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[4]CPT

Bit 5: External Event 4 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[5]CPT

Bit 6: External Event 5 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[6]CPT

Bit 7: External Event 6 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[7]CPT

Bit 8: External Event 7 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[8]CPT

Bit 9: External Event 8 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[9]CPT

Bit 10: External Event 9 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[10]CPT

Bit 11: External Event 10 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

TA1SET

Bit 12: Timer A output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TA1RST

Bit 13: Timer A output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TACMP1

Bit 14: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TACMP2

Bit 15: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TB1SET

Bit 16: Timer B output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TB1RST

Bit 17: Timer B output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TBCMP1

Bit 18: Timer B Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TBCMP2

Bit 19: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TD1SET

Bit 24: Timer D output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TD1RST

Bit 25: Timer D output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TDCMP1

Bit 26: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TDCMP2

Bit 27: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TE1SET

Bit 28: Timer E output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TE1RST

Bit 29: Timer E output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TECMP1

Bit 30: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TECMP2

Bit 31: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

CPT2CR

CPT2xCR

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TECMP2
rw 		TECMP1
rw 		TE1RST
rw 		TE1SET
rw 		TDCMP2
rw 		TDCMP1
rw 		TD1RST
rw 		TD1SET
rw 		TBCMP2
rw 		TBCMP1
rw 		TB1RST
rw 		TB1SET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TACMP2
rw 		TACMP1
rw 		TA1RST
rw 		TA1SET
rw 		EXEV[10]CPT
rw 		EXEV[9]CPT
rw 		EXEV[8]CPT
rw 		EXEV[7]CPT
rw 		EXEV[6]CPT
rw 		EXEV[5]CPT
rw 		EXEV[4]CPT
rw 		EXEV[3]CPT
rw 		EXEV[2]CPT
rw 		EXEV[1]CPT
rw 		UPDCPT
rw 		SWCPT
rw
Toggle fields

SWCPT

Bit 0: Software Capture.

Allowed values:
0: NoEffect: No effect
1: TriggerCapture: Force capture Z

UPDCPT

Bit 1: Update Capture.

Allowed values:
0: NoEffect: Update event has no effect
1: TriggerCapture: Update event triggers capture Z

EXEV[1]CPT

Bit 2: External Event 1 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[2]CPT

Bit 3: External Event 2 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[3]CPT

Bit 4: External Event 3 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[4]CPT

Bit 5: External Event 4 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[5]CPT

Bit 6: External Event 5 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[6]CPT

Bit 7: External Event 6 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[7]CPT

Bit 8: External Event 7 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[8]CPT

Bit 9: External Event 8 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[9]CPT

Bit 10: External Event 9 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[10]CPT

Bit 11: External Event 10 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

TA1SET

Bit 12: Timer A output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TA1RST

Bit 13: Timer A output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TACMP1

Bit 14: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TACMP2

Bit 15: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TB1SET

Bit 16: Timer B output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TB1RST

Bit 17: Timer B output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TBCMP1

Bit 18: Timer B Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TBCMP2

Bit 19: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TD1SET

Bit 24: Timer D output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TD1RST

Bit 25: Timer D output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TDCMP1

Bit 26: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TDCMP2

Bit 27: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TE1SET

Bit 28: Timer E output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TE1RST

Bit 29: Timer E output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TECMP1

Bit 30: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TECMP2

Bit 31: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

OUTR

Timerx Output Register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIDL2
rw 		CHP2
rw 		FAULT2
rw 		IDLES2
rw 		IDLEM2
rw 		POL2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYPRT
rw 		DLYPRTEN
rw 		DTEN
rw 		DIDL1
rw 		CHP1
rw 		FAULT1
rw 		IDLES1
rw 		IDLEM1
rw 		POL1
rw
Toggle fields

POL1

Bit 1: Output 1 polarity.

Allowed values:
0: ActiveHigh: Positive polarity (output active high)
1: ActiveLow: Negative polarity (output active low)

IDLEM1

Bit 2: Output 1 Idle mode.

Allowed values:
0: NoEffect: No action: the output is not affected by the burst mode operation
1: SetIdle: The output is in idle state when requested by the burst mode controller

IDLES1

Bit 3: Output 1 Idle State.

Allowed values:
0: Inactive: Output idle state is inactive
1: Active: Output idle state is active

FAULT1

Bits 4-5: Output 1 Fault state.

Allowed values:
0: Disabled: No action: the output is not affected by the fault input and stays in run mode
1: SetActive: Output goes to active state after a fault event
2: SetInactive: Output goes to inactive state after a fault event
3: SetHighZ: Output goes to high-z state after a fault event

CHP1

Bit 6: Output 1 Chopper enable.

Allowed values:
0: Disabled: Output signal not altered
1: Enabled: Output signal is chopped by a carrier signal

DIDL1

Bit 7: Output 1 Deadtime upon burst mode Idle entry.

Allowed values:
0: Disabled: The programmed idle state is applied immediately to the output
1: Enabled: Deadtime (inactive level) is inserted on output before entering the idle mode

DTEN

Bit 8: Deadtime enable.

Allowed values:
0: Disabled: Output 1 and 2 signals are independent
1: Enabled: Deadtime is inserted between output 1 and output 2

DLYPRTEN

Bit 9: Delayed Protection Enable.

Allowed values:
0: Disabled: No action
1: Enabled: Delayed protection is enabled, as per DLYPRT bits

DLYPRT

Bits 10-12: Delayed Protection.

Allowed values:
0: Output1_EE6: Output 1 delayed idle on external event 6
1: Output2_EE6: Output 2 delayed idle on external event 6
2: Output1_2_EE6: Output 1 and 2 delayed idle on external event 6
3: Balanced_EE6: Balanced idle on external event 6
4: Output1_EE7: Output 1 delayed idle on external event 7
5: Output2_EE7: Output 2 delayed idle on external event 7
6: Output1_2_EE7: Output 1 and 2 delayed idle on external event 7
7: Balanced_EE7: Balanced idle on external event 7

POL2

Bit 17: Output 2 polarity.

Allowed values:
0: ActiveHigh: Positive polarity (output active high)
1: ActiveLow: Negative polarity (output active low)

IDLEM2

Bit 18: Output 2 Idle mode.

Allowed values:
0: NoEffect: No action: the output is not affected by the burst mode operation
1: SetIdle: The output is in idle state when requested by the burst mode controller

IDLES2

Bit 19: Output 2 Idle State.

Allowed values:
0: Inactive: Output idle state is inactive
1: Active: Output idle state is active

FAULT2

Bits 20-21: Output 2 Fault state.

Allowed values:
0: Disabled: No action: the output is not affected by the fault input and stays in run mode
1: SetActive: Output goes to active state after a fault event
2: SetInactive: Output goes to inactive state after a fault event
3: SetHighZ: Output goes to high-z state after a fault event

CHP2

Bit 22: Output 2 Chopper enable.

Allowed values:
0: Disabled: Output signal not altered
1: Enabled: Output signal is chopped by a carrier signal

DIDL2

Bit 23: Output 2 Deadtime upon burst mode Idle entry.

Allowed values:
0: Disabled: The programmed idle state is applied immediately to the output
1: Enabled: Deadtime (inactive level) is inserted on output before entering the idle mode

FLTR

Timerx Fault Register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLTLCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLT[5]EN
rw 		FLT[4]EN
rw 		FLT[3]EN
rw 		FLT[2]EN
rw 		FLT[1]EN
rw
Toggle fields

FLT[1]EN

Bit 0: Fault 1 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[2]EN

Bit 1: Fault 2 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[3]EN

Bit 2: Fault 3 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[4]EN

Bit 3: Fault 4 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[5]EN

Bit 4: Fault 5 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLTLCK

Bit 31: Fault sources Lock.

Allowed values:
0: Unlocked: FLT1EN..FLT5EN bits are read/write
1: Locked: FLT1EN..FLT5EN bits are read only

HRTIM_TIMD

0x40017600: High Resolution Timer: TIMD

359/359 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 ISR
0x8 ICR
0xc DIER
0x10 CNTR
0x14 PERR
0x18 REPR
0x1c CMP1R
0x20 CMP1CR
0x24 CMP2R
0x28 CMP3R
0x2c CMP4R
0x30 CPT1R
0x34 CPT2R
0x38 DTR
0x3c SET1R
0x40 RST1R
0x44 SET2R
0x48 RST2R
0x4c EEFR1
0x50 EEFR2
0x54 RSTR
0x58 CHPR
0x5c CPT1CR
0x60 CPT2CR
0x64 OUTR
0x68 FLTR
Toggle registers

CR

Timerx Control Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPDGAT
rw 		PREEN
rw 		DACSYNC
rw 		MSTU
rw 		TEU
rw 		TDU
rw 		TCU
rw 		TBU
rw 		TRSTU
rw 		TREPU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DELCMP4
rw 		DELCMP2
rw 		SYNCSTRT
rw 		SYNCRST
rw 		PSHPLL
rw 		HALF
rw 		RETRIG
rw 		CONT
rw 		CKPSC
rw
Toggle fields

CKPSC

Bits 0-2: HRTIM Timer x Clock prescaler.

Allowed values: 0x0-0x7

CONT

Bit 3: Continuous mode.

Allowed values:
0: SingleShot: The timer operates in single-shot mode and stops when it reaches the TIMxPER value
1: Continuous: The timer operates in continuous (free-running) mode and rolls over to zero when it reaches the TIMxPER value

RETRIG

Bit 4: Re-triggerable mode.

Allowed values:
0: Disabled: The timer is not re-triggerable: a counter reset can be done only if the counter is stopped
1: Enabled: The timer is retriggerable: a counter reset is done whatever the counter state

HALF

Bit 5: Half mode enable.

Allowed values:
0: Disabled: Half mode disabled
1: Enabled: Half mode enabled

PSHPLL

Bit 6: Push-Pull mode enable.

Allowed values:
0: Disabled: Push-pull mode disabled
1: Enabled: Push-pull mode enabled

SYNCRST

Bit 10: Synchronization Resets Timer x.

Allowed values:
0: Disabled: Synchronization event has no effect on Timer x
1: Reset: Synchronization event resets Timer x

SYNCSTRT

Bit 11: Synchronization Starts Timer x.

Allowed values:
0: Disabled: Synchronization event has no effect on Timer x
1: Start: Synchronization event starts Timer x

DELCMP2

Bits 12-13: Delayed CMP2 mode.

Allowed values:
0: Standard: CMP2 register is always active (standard compare mode)
1: Capture1: CMP2 is recomputed and is active following a capture 1 event
2: Capture1_Compare1: CMP2 is recomputed and is active following a capture 1 event or a Compare 1 match
3: Capture1_Compare3: CMP2 is recomputed and is active following a capture 1 event or a Compare 3 match

DELCMP4

Bits 14-15: Delayed CMP4 mode.

Allowed values:
0: Standard: CMP4 register is always active (standard compare mode)
1: Capture2: CMP4 is recomputed and is active following a capture 2 event
2: Capture2_Compare1: CMP4 is recomputed and is active following a capture 2 event or a Compare 1 match
3: Capture_Compare3: CMP4 is recomputed and is active following a capture event or a Compare 3 match

TREPU

Bit 17: Timer x Repetition update.

Allowed values:
0: Disabled: Update by timer x repetition disabled
1: Enabled: Update by timer x repetition enabled

TRSTU

Bit 18: Timerx reset update.

Allowed values:
0: Disabled: Update by timer x reset/roll-over disabled
1: Enabled: Update by timer x reset/roll-over enabled

TBU

Bit 20: TBU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

TCU

Bit 21: TCU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

TDU

Bit 22: TDU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

TEU

Bit 23: TEU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

MSTU

Bit 24: Master Timer update.

Allowed values:
0: Disabled: Update by master timer disabled
1: Enabled: Update by master timer enabled

DACSYNC

Bits 25-26: AC Synchronization.

Allowed values:
0: Disabled: No DAC trigger generated
1: DACSync1: Trigger generated on DACSync1
2: DACSync2: Trigger generated on DACSync2
3: DACSync3: Trigger generated on DACSync3

PREEN

Bit 27: Preload enable.

Allowed values:
0: Disabled: Preload disabled: the write access is directly done into the active register
1: Enabled: Preload enabled: the write access is done into the preload register

UPDGAT

Bits 28-31: Update Gating.

Allowed values:
0: Independent: Update occurs independently from the DMA burst transfer
1: DMABurst: Update occurs when the DMA burst transfer is completed
2: DMABurst_Update: Update occurs on the update event following DMA burst transfer completion
3: Input1: Update occurs on a rising edge of HRTIM update enable input 1
4: Input2: Update occurs on a rising edge of HRTIM update enable input 2
5: Input3: Update occurs on a rising edge of HRTIM update enable input 3
6: Input1_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 1
7: Input2_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 2
8: Input3_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 3

ISR

Timerx Interrupt Status Register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
O2CPY
r 		O1CPY
r 		O2STAT
r 		O1STAT
r 		IPPSTAT
r 		CPPSTAT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYPRT
r 		RST
r 		RST2
r 		SET[2]
r 		RST1
r 		SET[1]
r 		CPT[2]
r 		CPT[1]
r 		UPD
r 		REP
r 		CMP[4]
r 		CMP[3]
r 		CMP[2]
r 		CMP[1]
r
Toggle fields

CMP[1]

Bit 0: Compare 1 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

CMP[2]

Bit 1: Compare 2 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

CMP[3]

Bit 2: Compare 3 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

CMP[4]

Bit 3: Compare 4 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

REP

Bit 4: Repetition Interrupt Flag.

Allowed values:
0: NoEvent: No timer repetition interrupt occurred
1: Event: Timer repetition interrupt occurred

UPD

Bit 6: Update Interrupt Flag.

Allowed values:
0: NoEvent: No timer update interrupt occurred
1: Event: Timer update interrupt occurred

CPT[1]

Bit 7: Capture1 Interrupt Flag.

Allowed values:
0: NoEvent: No timer x capture reset interrupt occurred
1: Event: Timer x capture reset interrupt occurred

CPT[2]

Bit 8: Capture2 Interrupt Flag.

Allowed values:
0: NoEvent: No timer x capture reset interrupt occurred
1: Event: Timer x capture reset interrupt occurred

SET[1]

Bit 9: Output 1 Set Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output set interrupt occurred
1: Event: Tx output set interrupt occurred

RST1

Bit 10: Output 1 Reset Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output reset interrupt occurred
1: Event: Tx output reset interrupt occurred

SET[2]

Bit 11: Output 2 Set Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output set interrupt occurred
1: Event: Tx output set interrupt occurred

RST2

Bit 12: Output 2 Reset Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output reset interrupt occurred
1: Event: Tx output reset interrupt occurred

RST

Bit 13: Reset Interrupt Flag.

Allowed values:
0: NoEvent: No TIMx counter reset/roll-over interrupt occurred
1: Event: TIMx counter reset/roll-over interrupt occurred

DLYPRT

Bit 14: Delayed Protection Flag.

Allowed values:
0: Inactive: Not in delayed idle or balanced idle mode
1: Active: Delayed idle or balanced idle mode entry

CPPSTAT

Bit 16: Current Push Pull Status.

Allowed values:
0: Output1Active: Signal applied on output 1 and output 2 forced inactive
1: Output2Active: Signal applied on output 2 and output 1 forced inactive

IPPSTAT

Bit 17: Idle Push Pull Status.

Allowed values:
0: Output1Active: Protection occurred when the output 1 was active and output 2 forced inactive
1: Output2Active: Protection occurred when the output 2 was active and output 1 forced inactive

O1STAT

Bit 18: Output 1 State.

Allowed values:
0: Inactive: Output was inactive
1: Active: Output was active

O2STAT

Bit 19: Output 2 State.

Allowed values:
0: Inactive: Output was inactive
1: Active: Output was active

O1CPY

Bit 20: Output 1 Copy.

Allowed values:
0: Inactive: Output is inactive
1: Active: Output is active

O2CPY

Bit 21: Output 2 Copy.

Allowed values:
0: Inactive: Output is inactive
1: Active: Output is active

ICR

Timerx Interrupt Clear Register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

14/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYPRTC
w 		RSTC
w 		RST2C
w 		SET[2]C
w 		RST1C
w 		SET[1]C
w 		CPT[2]C
w 		CPT[1]C
w 		UPDC
w 		REPC
w 		CMP[4]C
w 		CMP[3]C
w 		CMP[2]C
w 		CMP[1]C
w
Toggle fields

CMP[1]C

Bit 0: Compare 1 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CMP[2]C

Bit 1: Compare 2 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CMP[3]C

Bit 2: Compare 3 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CMP[4]C

Bit 3: Compare 4 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

REPC

Bit 4: Repetition Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

UPDC

Bit 6: Update Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CPT[1]C

Bit 7: Capture1 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CPT[2]C

Bit 8: Capture2 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

SET[1]C

Bit 9: Output 1 Set flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

RST1C

Bit 10: Output 1 Reset flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

SET[2]C

Bit 11: Output 2 Set flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

RST2C

Bit 12: Output 2 Reset flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

RSTC

Bit 13: Reset Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

DLYPRTC

Bit 14: Delayed Protection Flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

DIER

TIMxDIER5

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLYPRTDE
rw 		RSTDE
rw 		RST2DE
rw 		SET[2]DE
rw 		RST1DE
rw 		SET[1]DE
rw 		CPT[2]DE
rw 		CPT[1]DE
rw 		UPDDE
rw 		REPDE
rw 		CMP[4]DE
rw 		CMP[3]DE
rw 		CMP[2]DE
rw 		CMP[1]DE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYPRTIE
rw 		RSTIE
rw 		RST2IE
rw 		SET[2]IE
rw 		RST1IE
rw 		SET[1]IE
rw 		CPT[2]IE
rw 		CPT[1]IE
rw 		UPDIE
rw 		REPIE
rw 		CMP[4]IE
rw 		CMP[3]IE
rw 		CMP[2]IE
rw 		CMP[1]IE
rw
Toggle fields

CMP[1]IE

Bit 0: CMP1IE.

Allowed values:
0: Disabled: Compare interrupt disabled
1: Enabled: Compare interrupt enabled

CMP[2]IE

Bit 1: CMP2IE.

Allowed values:
0: Disabled: Compare interrupt disabled
1: Enabled: Compare interrupt enabled

CMP[3]IE

Bit 2: CMP3IE.

Allowed values:
0: Disabled: Compare interrupt disabled
1: Enabled: Compare interrupt enabled

CMP[4]IE

Bit 3: CMP4IE.

Allowed values:
0: Disabled: Compare interrupt disabled
1: Enabled: Compare interrupt enabled

REPIE

Bit 4: REPIE.

Allowed values:
0: Disabled: Repetition interrupt disabled
1: Enabled: Repetition interrupt enabled

UPDIE

Bit 6: UPDIE.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CPT[1]IE

Bit 7: CPT1IE.

Allowed values:
0: Disabled: Capture interrupt disabled
1: Enabled: Capture interrupt enabled

CPT[2]IE

Bit 8: CPT2IE.

Allowed values:
0: Disabled: Capture interrupt disabled
1: Enabled: Capture interrupt enabled

SET[1]IE

Bit 9: Output 1 set interrupt enable.

Allowed values:
0: Disabled: Tx output set interrupt disabled
1: Enabled: Tx output set interrupt enabled

RST1IE

Bit 10: RSTx1IE.

Allowed values:
0: Disabled: Tx output reset interrupt disabled
1: Enabled: Tx output reset interrupt enabled

SET[2]IE

Bit 11: Output 2 set interrupt enable.

Allowed values:
0: Disabled: Tx output set interrupt disabled
1: Enabled: Tx output set interrupt enabled

RST2IE

Bit 12: RSTx2IE.

Allowed values:
0: Disabled: Tx output reset interrupt disabled
1: Enabled: Tx output reset interrupt enabled

RSTIE

Bit 13: RSTIE.

Allowed values:
0: Disabled: Timer x counter/reset roll-over interrupt disabled
1: Enabled: Timer x counter/reset roll-over interrupt enabled

DLYPRTIE

Bit 14: DLYPRTIE.

Allowed values:
0: Disabled: Delayed protection interrupt disabled
1: Enabled: Delayed protection interrupt enabled

CMP[1]DE

Bit 16: CMP1DE.

Allowed values:
0: Disabled: Compare DMA request disabled
1: Enabled: Compare DMA request enabled

CMP[2]DE

Bit 17: CMP2DE.

Allowed values:
0: Disabled: Compare DMA request disabled
1: Enabled: Compare DMA request enabled

CMP[3]DE

Bit 18: CMP3DE.

Allowed values:
0: Disabled: Compare DMA request disabled
1: Enabled: Compare DMA request enabled

CMP[4]DE

Bit 19: CMP4DE.

Allowed values:
0: Disabled: Compare DMA request disabled
1: Enabled: Compare DMA request enabled

REPDE

Bit 20: REPDE.

Allowed values:
0: Disabled: Repetition DMA request disabled
1: Enabled: Repetition DMA request enabled

UPDDE

Bit 22: UPDDE.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CPT[1]DE

Bit 23: CPT1DE.

Allowed values:
0: Disabled: Capture DMA request disabled
1: Enabled: Capture DMA request enabled

CPT[2]DE

Bit 24: CPT2DE.

Allowed values:
0: Disabled: Capture DMA request disabled
1: Enabled: Capture DMA request enabled

SET[1]DE

Bit 25: Output 1 set DMA request enable.

Allowed values:
0: Disabled: Tx output set DMA request disabled
1: Enabled: Tx output set DMA request enabled

RST1DE

Bit 26: RSTx1DE.

Allowed values:
0: Disabled: Tx output reset DMA request disabled
1: Enabled: Tx output reset DMA request enabled

SET[2]DE

Bit 27: Output 2 set DMA request enable.

Allowed values:
0: Disabled: Tx output set DMA request disabled
1: Enabled: Tx output set DMA request enabled

RST2DE

Bit 28: RSTx2DE.

Allowed values:
0: Disabled: Tx output reset DMA request disabled
1: Enabled: Tx output reset DMA request enabled

RSTDE

Bit 29: RSTDE.

Allowed values:
0: Disabled: Timer x counter reset/roll-over DMA request disabled
1: Enabled: Timer x counter reset/roll-over DMA request enabled

DLYPRTDE

Bit 30: DLYPRTDE.

Allowed values:
0: Disabled: Delayed protection DMA request disabled
1: Enabled: Delayed protection DMA request enabled

CNTR

Timerx Counter Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: Counter value.

Allowed values: 0x0-0xffff

PERR

Timerx Period Register

Offset: 0x14, size: 32, reset: 0x0000FFFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PER
rw
Toggle fields

PER

Bits 0-15: Master Timer Period value.

Allowed values: 0x0-0xffff

REPR

Timerx Repetition Register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Master Timer Repetition counter value.

Allowed values: 0x0-0xff

CMP1R

Timerx Compare 1 Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CMP1CR

Timerx Compare 1 Compound Register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP1
rw
Toggle fields

CMP1

Bits 0-15: Timerx Compare 1 value.

Allowed values: 0x0-0xffff

REP

Bits 16-23: Timerx Repetition value (aliased from HRTIM_REPx register).

Allowed values: 0x0-0xff

CMP2R

Timerx Compare 2 Register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CMP3R

Timerx Compare 3 Register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CMP4R

Timerx Compare 4 Register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CPT1R

Timerx Capture 1 Register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPT
r
Toggle fields

CPT

Bits 0-15: Timerx Capture 1 value.

Allowed values: 0x0-0xffff

CPT2R

Timerx Capture 2 Register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPT
r
Toggle fields

CPT

Bits 0-15: Timerx Capture 1 value.

Allowed values: 0x0-0xffff

DTR

Timerx Deadtime Register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTFLK
rw 		DTFSLK
rw 		SDTF
rw 		DTF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTRLK
rw 		DTRSLK
rw 		DTPRSC
rw 		SDTR
rw 		DTR
rw
Toggle fields

DTR

Bits 0-8: Deadtime Rising value.

Allowed values: 0x0-0x1ff

SDTR

Bit 9: Sign Deadtime Rising value.

Allowed values:
0: Positive: Positive deadtime on rising edge
1: Negative: Negative deadtime on rising edge

DTPRSC

Bits 10-12: Deadtime Prescaler.

Allowed values: 0x0-0x7

DTRSLK

Bit 14: Deadtime Rising Sign Lock.

Allowed values:
0: Unlocked: Deadtime rising sign is writable
1: Locked: Deadtime rising sign is read-only

DTRLK

Bit 15: Deadtime Rising Lock.

Allowed values:
0: Unlocked: Deadtime rising value and sign is writable
1: Locked: Deadtime rising value and sign is read-only

DTF

Bits 16-24: Deadtime Falling value.

Allowed values: 0x0-0x1ff

SDTF

Bit 25: Sign Deadtime Falling value.

Allowed values:
0: Positive: Positive deadtime on falling edge
1: Negative: Negative deadtime on falling edge

DTFSLK

Bit 30: Deadtime Falling Sign Lock.

Allowed values:
0: Unlocked: Deadtime falling sign is writable
1: Locked: Deadtime falling sign is read-only

DTFLK

Bit 31: Deadtime Falling Lock.

Allowed values:
0: Unlocked: Deadtime falling value and sign is writable
1: Locked: Deadtime falling value and sign is read-only

SET1R

Timerx Output1 Set Register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPDATE
rw 		EXTEVNT[10]
rw 		EXTEVNT[9]
rw 		EXTEVNT[8]
rw 		EXTEVNT[7]
rw 		EXTEVNT[6]
rw 		EXTEVNT[5]
rw 		EXTEVNT[4]
rw 		EXTEVNT[3]
rw 		EXTEVNT[2]
rw 		EXTEVNT[1]
rw 		TIMECMP2
rw 		TIMECMP1
rw 		TIMCCMP4
rw 		TIMCCMP3
rw 		TIMCCMP1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMBCMP4
rw 		TIMBCMP2
rw 		TIMACMP4
rw 		TIMACMP1
rw 		MSTCMP[4]
rw 		MSTCMP[3]
rw 		MSTCMP[2]
rw 		MSTCMP[1]
rw 		MSTPER
rw 		CMP[4]
rw 		CMP[3]
rw 		CMP[2]
rw 		CMP[1]
rw 		PER
rw 		RESYNC
rw 		SST
rw
Toggle fields

SST

Bit 0: Software Set trigger.

Allowed values:
0: NoEffect: No effect
1: SetActive: Force output to its active state

RESYNC

Bit 1: Timer A resynchronizaton.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetActive: Timer reset event coming solely from software or SYNC input event forces the output to its active state

PER

Bit 2: Timer A Period.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetActive: Timer period event forces the output to its active state

CMP[1]

Bit 3: Timer A compare 1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[2]

Bit 4: Timer A compare 2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[3]

Bit 5: Timer A compare 3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[4]

Bit 6: Timer A compare 4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

MSTPER

Bit 7: Master Period.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetActive: Master timer counter roll-over/reset forces the output to its active state

MSTCMP[1]

Bit 8: Master Compare 1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[2]

Bit 9: Master Compare 2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[3]

Bit 10: Master Compare 3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[4]

Bit 11: Master Compare 4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

TIMACMP1

Bit 12: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMACMP4

Bit 13: Timer A Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMBCMP2

Bit 14: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMBCMP4

Bit 15: Timer B Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMCCMP1

Bit 16: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMCCMP3

Bit 17: Timer C Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMCCMP4

Bit 18: Timer C Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMECMP1

Bit 19: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMECMP2

Bit 20: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

EXTEVNT[1]

Bit 21: External Event 1.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[2]

Bit 22: External Event 2.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[3]

Bit 23: External Event 3.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[4]

Bit 24: External Event 4.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[5]

Bit 25: External Event 5.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[6]

Bit 26: External Event 6.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[7]

Bit 27: External Event 7.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[8]

Bit 28: External Event 8.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[9]

Bit 29: External Event 9.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[10]

Bit 30: External Event 10.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

UPDATE

Bit 31: Registers update (transfer preload to active).

Allowed values:
0: NoEffect: Register update event has no effect
1: SetActive: Register update event forces the output to its active state

RST1R

Timerx Output1 Reset Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPDATE
rw 		EXTEVNT[10]
rw 		EXTEVNT[9]
rw 		EXTEVNT[8]
rw 		EXTEVNT[7]
rw 		EXTEVNT[6]
rw 		EXTEVNT[5]
rw 		EXTEVNT[4]
rw 		EXTEVNT[3]
rw 		EXTEVNT[2]
rw 		EXTEVNT[1]
rw 		TIMECMP2
rw 		TIMECMP1
rw 		TIMCCMP4
rw 		TIMCCMP3
rw 		TIMCCMP1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMBCMP4
rw 		TIMBCMP2
rw 		TIMACMP4
rw 		TIMACMP1
rw 		MSTCMP[4]
rw 		MSTCMP[3]
rw 		MSTCMP[2]
rw 		MSTCMP[1]
rw 		MSTPER
rw 		CMP[4]
rw 		CMP[3]
rw 		CMP[2]
rw 		CMP[1]
rw 		PER
rw 		RESYNC
rw 		SRT
rw
Toggle fields

SRT

Bit 0: SRT.

Allowed values:
0: NoEffect: No effect
1: SetInactive: Force output to its inactive state

RESYNC

Bit 1: RESYNC.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetInactive: Timer reset event coming solely from software or SYNC input event forces the output to its inactive state

PER

Bit 2: PER.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetInactive: Timer period event forces the output to its inactive state

CMP[1]

Bit 3: CMP1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[2]

Bit 4: CMP2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[3]

Bit 5: CMP3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[4]

Bit 6: CMP4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

MSTPER

Bit 7: MSTPER.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetInactive: Master timer counter roll-over/reset forces the output to its inactive state

MSTCMP[1]

Bit 8: MSTCMP1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[2]

Bit 9: MSTCMP2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[3]

Bit 10: MSTCMP3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[4]

Bit 11: MSTCMP4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

TIMACMP1

Bit 12: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMACMP4

Bit 13: Timer A Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMBCMP2

Bit 14: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMBCMP4

Bit 15: Timer B Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMCCMP1

Bit 16: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMCCMP3

Bit 17: Timer C Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMCCMP4

Bit 18: Timer C Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMECMP1

Bit 19: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMECMP2

Bit 20: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

EXTEVNT[1]

Bit 21: EXTEVNT1.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[2]

Bit 22: EXTEVNT2.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[3]

Bit 23: EXTEVNT3.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[4]

Bit 24: EXTEVNT4.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[5]

Bit 25: EXTEVNT5.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[6]

Bit 26: EXTEVNT6.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[7]

Bit 27: EXTEVNT7.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[8]

Bit 28: EXTEVNT8.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[9]

Bit 29: EXTEVNT9.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[10]

Bit 30: EXTEVNT10.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

UPDATE

Bit 31: UPDATE.

Allowed values:
0: NoEffect: Register update event has no effect
1: SetInactive: Register update event forces the output to its inactive state

SET2R

Timerx Output2 Set Register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPDATE
rw 		EXTEVNT[10]
rw 		EXTEVNT[9]
rw 		EXTEVNT[8]
rw 		EXTEVNT[7]
rw 		EXTEVNT[6]
rw 		EXTEVNT[5]
rw 		EXTEVNT[4]
rw 		EXTEVNT[3]
rw 		EXTEVNT[2]
rw 		EXTEVNT[1]
rw 		TIMECMP2
rw 		TIMECMP1
rw 		TIMCCMP4
rw 		TIMCCMP3
rw 		TIMCCMP1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMBCMP4
rw 		TIMBCMP2
rw 		TIMACMP4
rw 		TIMACMP1
rw 		MSTCMP[4]
rw 		MSTCMP[3]
rw 		MSTCMP[2]
rw 		MSTCMP[1]
rw 		MSTPER
rw 		CMP[4]
rw 		CMP[3]
rw 		CMP[2]
rw 		CMP[1]
rw 		PER
rw 		RESYNC
rw 		SST
rw
Toggle fields

SST

Bit 0: Software Set trigger.

Allowed values:
0: NoEffect: No effect
1: SetActive: Force output to its active state

RESYNC

Bit 1: Timer A resynchronizaton.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetActive: Timer reset event coming solely from software or SYNC input event forces the output to its active state

PER

Bit 2: Timer A Period.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetActive: Timer period event forces the output to its active state

CMP[1]

Bit 3: Timer A compare 1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[2]

Bit 4: Timer A compare 2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[3]

Bit 5: Timer A compare 3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[4]

Bit 6: Timer A compare 4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

MSTPER

Bit 7: Master Period.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetActive: Master timer counter roll-over/reset forces the output to its active state

MSTCMP[1]

Bit 8: Master Compare 1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[2]

Bit 9: Master Compare 2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[3]

Bit 10: Master Compare 3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[4]

Bit 11: Master Compare 4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

TIMACMP1

Bit 12: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMACMP4

Bit 13: Timer A Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMBCMP2

Bit 14: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMBCMP4

Bit 15: Timer B Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMCCMP1

Bit 16: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMCCMP3

Bit 17: Timer C Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMCCMP4

Bit 18: Timer C Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMECMP1

Bit 19: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMECMP2

Bit 20: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

EXTEVNT[1]

Bit 21: External Event 1.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[2]

Bit 22: External Event 2.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[3]

Bit 23: External Event 3.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[4]

Bit 24: External Event 4.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[5]

Bit 25: External Event 5.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[6]

Bit 26: External Event 6.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[7]

Bit 27: External Event 7.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[8]

Bit 28: External Event 8.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[9]

Bit 29: External Event 9.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[10]

Bit 30: External Event 10.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

UPDATE

Bit 31: Registers update (transfer preload to active).

Allowed values:
0: NoEffect: Register update event has no effect
1: SetActive: Register update event forces the output to its active state

RST2R

Timerx Output2 Reset Register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPDATE
rw 		EXTEVNT[10]
rw 		EXTEVNT[9]
rw 		EXTEVNT[8]
rw 		EXTEVNT[7]
rw 		EXTEVNT[6]
rw 		EXTEVNT[5]
rw 		EXTEVNT[4]
rw 		EXTEVNT[3]
rw 		EXTEVNT[2]
rw 		EXTEVNT[1]
rw 		TIMECMP2
rw 		TIMECMP1
rw 		TIMCCMP4
rw 		TIMCCMP3
rw 		TIMCCMP1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMBCMP4
rw 		TIMBCMP2
rw 		TIMACMP4
rw 		TIMACMP1
rw 		MSTCMP[4]
rw 		MSTCMP[3]
rw 		MSTCMP[2]
rw 		MSTCMP[1]
rw 		MSTPER
rw 		CMP[4]
rw 		CMP[3]
rw 		CMP[2]
rw 		CMP[1]
rw 		PER
rw 		RESYNC
rw 		SRT
rw
Toggle fields

SRT

Bit 0: SRT.

Allowed values:
0: NoEffect: No effect
1: SetInactive: Force output to its inactive state

RESYNC

Bit 1: RESYNC.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetInactive: Timer reset event coming solely from software or SYNC input event forces the output to its inactive state

PER

Bit 2: PER.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetInactive: Timer period event forces the output to its inactive state

CMP[1]

Bit 3: CMP1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[2]

Bit 4: CMP2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[3]

Bit 5: CMP3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[4]

Bit 6: CMP4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

MSTPER

Bit 7: MSTPER.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetInactive: Master timer counter roll-over/reset forces the output to its inactive state

MSTCMP[1]

Bit 8: MSTCMP1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[2]

Bit 9: MSTCMP2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[3]

Bit 10: MSTCMP3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[4]

Bit 11: MSTCMP4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

TIMACMP1

Bit 12: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMACMP4

Bit 13: Timer A Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMBCMP2

Bit 14: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMBCMP4

Bit 15: Timer B Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMCCMP1

Bit 16: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMCCMP3

Bit 17: Timer C Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMCCMP4

Bit 18: Timer C Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMECMP1

Bit 19: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMECMP2

Bit 20: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

EXTEVNT[1]

Bit 21: EXTEVNT1.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[2]

Bit 22: EXTEVNT2.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[3]

Bit 23: EXTEVNT3.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[4]

Bit 24: EXTEVNT4.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[5]

Bit 25: EXTEVNT5.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[6]

Bit 26: EXTEVNT6.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[7]

Bit 27: EXTEVNT7.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[8]

Bit 28: EXTEVNT8.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[9]

Bit 29: EXTEVNT9.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[10]

Bit 30: EXTEVNT10.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

UPDATE

Bit 31: UPDATE.

Allowed values:
0: NoEffect: Register update event has no effect
1: SetInactive: Register update event forces the output to its inactive state

EEFR1

Timerx External Event Filtering Register 1

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EE[5]FLTR
rw 		EE[5]LTCH
rw 		EE[4]FLTR
rw 		EE[4]LTCH
rw 		EE[3]FLTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EE[3]FLTR
rw 		EE[3]LTCH
rw 		EE[2]FLTR
rw 		EE[2]LTCH
rw 		EE[1]FLTR
rw 		EE[1]LTCH
rw
Toggle fields

EE[1]LTCH

Bit 0: External Event 1 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[1]FLTR

Bits 1-4: External Event 1 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[2]LTCH

Bit 6: External Event 2 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[2]FLTR

Bits 7-10: External Event 2 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[3]LTCH

Bit 12: External Event 3 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[3]FLTR

Bits 13-16: External Event 3 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[4]LTCH

Bit 18: External Event 4 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[4]FLTR

Bits 19-22: External Event 4 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[5]LTCH

Bit 24: External Event 5 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[5]FLTR

Bits 25-28: External Event 5 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EEFR2

Timerx External Event Filtering Register 2

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EE[10]FLTR
rw 		EE[10]LTCH
rw 		EE[9]FLTR
rw 		EE[9]LTCH
rw 		EE[8]FLTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EE[8]FLTR
rw 		EE[8]LTCH
rw 		EE[7]FLTR
rw 		EE[7]LTCH
rw 		EE[6]FLTR
rw 		EE[6]LTCH
rw
Toggle fields

EE[6]LTCH

Bit 0: External Event 6 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[6]FLTR

Bits 1-4: External Event 6 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[7]LTCH

Bit 6: External Event 7 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[7]FLTR

Bits 7-10: External Event 7 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[8]LTCH

Bit 12: External Event 8 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[8]FLTR

Bits 13-16: External Event 8 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[9]LTCH

Bit 18: External Event 9 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[9]FLTR

Bits 19-22: External Event 9 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[10]LTCH

Bit 24: External Event 10 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[10]FLTR

Bits 25-28: External Event 10 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

RSTR

TimerA Reset Register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

30/30 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIMECMP4
rw 		TIMECMP2
rw 		TIMECMP1
rw 		TIMCCMP4
rw 		TIMCCMP2
rw 		TIMCCMP1
rw 		TIMBCMP4
rw 		TIMBCMP2
rw 		TIMBCMP1
rw 		TIMACMP4
rw 		TIMACMP2
rw 		TIMACMP1
rw 		EXTEVNT10
rw 		EXTEVNT9
rw 		EXTEVNT8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTEVNT7
rw 		EXTEVNT6
rw 		EXTEVNT5
rw 		EXTEVNT4
rw 		EXTEVNT3
rw 		EXTEVNT2
rw 		EXTEVNT1
rw 		MSTCMP4
rw 		MSTCMP3
rw 		MSTCMP2
rw 		MSTCMP1
rw 		MSTPER
rw 		CMP4
rw 		CMP2
rw 		UPDT
rw
Toggle fields

UPDT

Bit 1: Timer A Update reset.

Allowed values:
0: NoEffect: Update event has no effect
1: ResetCounter: Timer X counter is reset upon update event

CMP2

Bit 2: Timer A compare 2 reset.

Allowed values:
0: NoEffect: Timer X compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer X compare Z event

CMP4

Bit 3: Timer A compare 4 reset.

Allowed values:
0: NoEffect: Timer X compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer X compare Z event

MSTPER

Bit 4: Master timer Period.

Allowed values:
0: NoEffect: Master timer period event has no effect
1: ResetCounter: Timer X counter is reset upon master timer period event

MSTCMP1

Bit 5: Master compare 1.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

MSTCMP2

Bit 6: Master compare 2.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

MSTCMP3

Bit 7: Master compare 3.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

MSTCMP4

Bit 8: Master compare 4.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

EXTEVNT1

Bit 9: External Event 1.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT2

Bit 10: External Event 2.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT3

Bit 11: External Event 3.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT4

Bit 12: External Event 4.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT5

Bit 13: External Event 5.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT6

Bit 14: External Event 6.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT7

Bit 15: External Event 7.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT8

Bit 16: External Event 8.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT9

Bit 17: External Event 9.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT10

Bit 18: External Event 10.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

TIMACMP1

Bit 19: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMACMP2

Bit 20: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMACMP4

Bit 21: Timer A Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMBCMP1

Bit 22: Timer B Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMBCMP2

Bit 23: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMBCMP4

Bit 24: Timer B Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMCCMP1

Bit 25: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMCCMP2

Bit 26: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMCCMP4

Bit 27: Timer C Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMECMP1

Bit 28: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMECMP2

Bit 29: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMECMP4

Bit 30: Timer E Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

CHPR

Timerx Chopper Register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STRTPW
rw 		CARDTY
rw 		CARFRQ
rw
Toggle fields

CARFRQ

Bits 0-3: Timerx carrier frequency value.

Allowed values: 0x0-0xf

CARDTY

Bits 4-6: Timerx chopper duty cycle value.

Allowed values: 0x0-0x7

STRTPW

Bits 7-10: STRTPW.

Allowed values: 0x0-0xf

CPT1CR

Timerx Capture 2 Control Register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TECMP2
rw 		TECMP1
rw 		TE1RST
rw 		TE1SET
rw 		TCCMP2
rw 		TCCMP1
rw 		TC1RST
rw 		TC1SET
rw 		TBCMP2
rw 		TBCMP1
rw 		TB1RST
rw 		TB1SET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TACMP2
rw 		TACMP1
rw 		TA1RST
rw 		TA1SET
rw 		EXEV[10]CPT
rw 		EXEV[9]CPT
rw 		EXEV[8]CPT
rw 		EXEV[7]CPT
rw 		EXEV[6]CPT
rw 		EXEV[5]CPT
rw 		EXEV[4]CPT
rw 		EXEV[3]CPT
rw 		EXEV[2]CPT
rw 		EXEV[1]CPT
rw 		UPDCPT
rw 		SWCPT
rw
Toggle fields

SWCPT

Bit 0: Software Capture.

Allowed values:
0: NoEffect: No effect
1: TriggerCapture: Force capture Z

UPDCPT

Bit 1: Update Capture.

Allowed values:
0: NoEffect: Update event has no effect
1: TriggerCapture: Update event triggers capture Z

EXEV[1]CPT

Bit 2: External Event 1 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[2]CPT

Bit 3: External Event 2 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[3]CPT

Bit 4: External Event 3 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[4]CPT

Bit 5: External Event 4 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[5]CPT

Bit 6: External Event 5 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[6]CPT

Bit 7: External Event 6 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[7]CPT

Bit 8: External Event 7 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[8]CPT

Bit 9: External Event 8 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[9]CPT

Bit 10: External Event 9 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[10]CPT

Bit 11: External Event 10 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

TA1SET

Bit 12: Timer A output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TA1RST

Bit 13: Timer A output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TACMP1

Bit 14: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TACMP2

Bit 15: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TB1SET

Bit 16: Timer B output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TB1RST

Bit 17: Timer B output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TBCMP1

Bit 18: Timer B Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TBCMP2

Bit 19: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TC1SET

Bit 20: Timer C output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TC1RST

Bit 21: Timer C output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TCCMP1

Bit 22: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TCCMP2

Bit 23: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TE1SET

Bit 28: Timer E output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TE1RST

Bit 29: Timer E output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TECMP1

Bit 30: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TECMP2

Bit 31: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

CPT2CR

CPT2xCR

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TECMP2
rw 		TECMP1
rw 		TE1RST
rw 		TE1SET
rw 		TCCMP2
rw 		TCCMP1
rw 		TC1RST
rw 		TC1SET
rw 		TBCMP2
rw 		TBCMP1
rw 		TB1RST
rw 		TB1SET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TACMP2
rw 		TACMP1
rw 		TA1RST
rw 		TA1SET
rw 		EXEV[10]CPT
rw 		EXEV[9]CPT
rw 		EXEV[8]CPT
rw 		EXEV[7]CPT
rw 		EXEV[6]CPT
rw 		EXEV[5]CPT
rw 		EXEV[4]CPT
rw 		EXEV[3]CPT
rw 		EXEV[2]CPT
rw 		EXEV[1]CPT
rw 		UPDCPT
rw 		SWCPT
rw
Toggle fields

SWCPT

Bit 0: Software Capture.

Allowed values:
0: NoEffect: No effect
1: TriggerCapture: Force capture Z

UPDCPT

Bit 1: Update Capture.

Allowed values:
0: NoEffect: Update event has no effect
1: TriggerCapture: Update event triggers capture Z

EXEV[1]CPT

Bit 2: External Event 1 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[2]CPT

Bit 3: External Event 2 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[3]CPT

Bit 4: External Event 3 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[4]CPT

Bit 5: External Event 4 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[5]CPT

Bit 6: External Event 5 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[6]CPT

Bit 7: External Event 6 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[7]CPT

Bit 8: External Event 7 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[8]CPT

Bit 9: External Event 8 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[9]CPT

Bit 10: External Event 9 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[10]CPT

Bit 11: External Event 10 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

TA1SET

Bit 12: Timer A output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TA1RST

Bit 13: Timer A output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TACMP1

Bit 14: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TACMP2

Bit 15: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TB1SET

Bit 16: Timer B output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TB1RST

Bit 17: Timer B output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TBCMP1

Bit 18: Timer B Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TBCMP2

Bit 19: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TC1SET

Bit 20: Timer C output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TC1RST

Bit 21: Timer C output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TCCMP1

Bit 22: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TCCMP2

Bit 23: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TE1SET

Bit 28: Timer E output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TE1RST

Bit 29: Timer E output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TECMP1

Bit 30: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TECMP2

Bit 31: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

OUTR

Timerx Output Register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIDL2
rw 		CHP2
rw 		FAULT2
rw 		IDLES2
rw 		IDLEM2
rw 		POL2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYPRT
rw 		DLYPRTEN
rw 		DTEN
rw 		DIDL1
rw 		CHP1
rw 		FAULT1
rw 		IDLES1
rw 		IDLEM1
rw 		POL1
rw
Toggle fields

POL1

Bit 1: Output 1 polarity.

Allowed values:
0: ActiveHigh: Positive polarity (output active high)
1: ActiveLow: Negative polarity (output active low)

IDLEM1

Bit 2: Output 1 Idle mode.

Allowed values:
0: NoEffect: No action: the output is not affected by the burst mode operation
1: SetIdle: The output is in idle state when requested by the burst mode controller

IDLES1

Bit 3: Output 1 Idle State.

Allowed values:
0: Inactive: Output idle state is inactive
1: Active: Output idle state is active

FAULT1

Bits 4-5: Output 1 Fault state.

Allowed values:
0: Disabled: No action: the output is not affected by the fault input and stays in run mode
1: SetActive: Output goes to active state after a fault event
2: SetInactive: Output goes to inactive state after a fault event
3: SetHighZ: Output goes to high-z state after a fault event

CHP1

Bit 6: Output 1 Chopper enable.

Allowed values:
0: Disabled: Output signal not altered
1: Enabled: Output signal is chopped by a carrier signal

DIDL1

Bit 7: Output 1 Deadtime upon burst mode Idle entry.

Allowed values:
0: Disabled: The programmed idle state is applied immediately to the output
1: Enabled: Deadtime (inactive level) is inserted on output before entering the idle mode

DTEN

Bit 8: Deadtime enable.

Allowed values:
0: Disabled: Output 1 and 2 signals are independent
1: Enabled: Deadtime is inserted between output 1 and output 2

DLYPRTEN

Bit 9: Delayed Protection Enable.

Allowed values:
0: Disabled: No action
1: Enabled: Delayed protection is enabled, as per DLYPRT bits

DLYPRT

Bits 10-12: Delayed Protection.

Allowed values:
0: Output1_EE6: Output 1 delayed idle on external event 6
1: Output2_EE6: Output 2 delayed idle on external event 6
2: Output1_2_EE6: Output 1 and 2 delayed idle on external event 6
3: Balanced_EE6: Balanced idle on external event 6
4: Output1_EE7: Output 1 delayed idle on external event 7
5: Output2_EE7: Output 2 delayed idle on external event 7
6: Output1_2_EE7: Output 1 and 2 delayed idle on external event 7
7: Balanced_EE7: Balanced idle on external event 7

POL2

Bit 17: Output 2 polarity.

Allowed values:
0: ActiveHigh: Positive polarity (output active high)
1: ActiveLow: Negative polarity (output active low)

IDLEM2

Bit 18: Output 2 Idle mode.

Allowed values:
0: NoEffect: No action: the output is not affected by the burst mode operation
1: SetIdle: The output is in idle state when requested by the burst mode controller

IDLES2

Bit 19: Output 2 Idle State.

Allowed values:
0: Inactive: Output idle state is inactive
1: Active: Output idle state is active

FAULT2

Bits 20-21: Output 2 Fault state.

Allowed values:
0: Disabled: No action: the output is not affected by the fault input and stays in run mode
1: SetActive: Output goes to active state after a fault event
2: SetInactive: Output goes to inactive state after a fault event
3: SetHighZ: Output goes to high-z state after a fault event

CHP2

Bit 22: Output 2 Chopper enable.

Allowed values:
0: Disabled: Output signal not altered
1: Enabled: Output signal is chopped by a carrier signal

DIDL2

Bit 23: Output 2 Deadtime upon burst mode Idle entry.

Allowed values:
0: Disabled: The programmed idle state is applied immediately to the output
1: Enabled: Deadtime (inactive level) is inserted on output before entering the idle mode

FLTR

Timerx Fault Register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLTLCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLT[5]EN
rw 		FLT[4]EN
rw 		FLT[3]EN
rw 		FLT[2]EN
rw 		FLT[1]EN
rw
Toggle fields

FLT[1]EN

Bit 0: Fault 1 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[2]EN

Bit 1: Fault 2 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[3]EN

Bit 2: Fault 3 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[4]EN

Bit 3: Fault 4 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[5]EN

Bit 4: Fault 5 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLTLCK

Bit 31: Fault sources Lock.

Allowed values:
0: Unlocked: FLT1EN..FLT5EN bits are read/write
1: Locked: FLT1EN..FLT5EN bits are read only

HRTIM_TIME

0x40017680: High Resolution Timer: TIME

359/359 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 ISR
0x8 ICR
0xc DIER
0x10 CNTR
0x14 PERR
0x18 REPR
0x1c CMP1R
0x20 CMP1CR
0x24 CMP2R
0x28 CMP3R
0x2c CMP4R
0x30 CPT1R
0x34 CPT2R
0x38 DTR
0x3c SET1R
0x40 RST1R
0x44 SET2R
0x48 RST2R
0x4c EEFR1
0x50 EEFR2
0x54 RSTR
0x58 CHPR
0x5c CPT1CR
0x60 CPT2CR
0x64 OUTR
0x68 FLTR
Toggle registers

CR

Timerx Control Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPDGAT
rw 		PREEN
rw 		DACSYNC
rw 		MSTU
rw 		TEU
rw 		TDU
rw 		TCU
rw 		TBU
rw 		TRSTU
rw 		TREPU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DELCMP4
rw 		DELCMP2
rw 		SYNCSTRT
rw 		SYNCRST
rw 		PSHPLL
rw 		HALF
rw 		RETRIG
rw 		CONT
rw 		CKPSC
rw
Toggle fields

CKPSC

Bits 0-2: HRTIM Timer x Clock prescaler.

Allowed values: 0x0-0x7

CONT

Bit 3: Continuous mode.

Allowed values:
0: SingleShot: The timer operates in single-shot mode and stops when it reaches the TIMxPER value
1: Continuous: The timer operates in continuous (free-running) mode and rolls over to zero when it reaches the TIMxPER value

RETRIG

Bit 4: Re-triggerable mode.

Allowed values:
0: Disabled: The timer is not re-triggerable: a counter reset can be done only if the counter is stopped
1: Enabled: The timer is retriggerable: a counter reset is done whatever the counter state

HALF

Bit 5: Half mode enable.

Allowed values:
0: Disabled: Half mode disabled
1: Enabled: Half mode enabled

PSHPLL

Bit 6: Push-Pull mode enable.

Allowed values:
0: Disabled: Push-pull mode disabled
1: Enabled: Push-pull mode enabled

SYNCRST

Bit 10: Synchronization Resets Timer x.

Allowed values:
0: Disabled: Synchronization event has no effect on Timer x
1: Reset: Synchronization event resets Timer x

SYNCSTRT

Bit 11: Synchronization Starts Timer x.

Allowed values:
0: Disabled: Synchronization event has no effect on Timer x
1: Start: Synchronization event starts Timer x

DELCMP2

Bits 12-13: Delayed CMP2 mode.

Allowed values:
0: Standard: CMP2 register is always active (standard compare mode)
1: Capture1: CMP2 is recomputed and is active following a capture 1 event
2: Capture1_Compare1: CMP2 is recomputed and is active following a capture 1 event or a Compare 1 match
3: Capture1_Compare3: CMP2 is recomputed and is active following a capture 1 event or a Compare 3 match

DELCMP4

Bits 14-15: Delayed CMP4 mode.

Allowed values:
0: Standard: CMP4 register is always active (standard compare mode)
1: Capture2: CMP4 is recomputed and is active following a capture 2 event
2: Capture2_Compare1: CMP4 is recomputed and is active following a capture 2 event or a Compare 1 match
3: Capture_Compare3: CMP4 is recomputed and is active following a capture event or a Compare 3 match

TREPU

Bit 17: Timer x Repetition update.

Allowed values:
0: Disabled: Update by timer x repetition disabled
1: Enabled: Update by timer x repetition enabled

TRSTU

Bit 18: Timerx reset update.

Allowed values:
0: Disabled: Update by timer x reset/roll-over disabled
1: Enabled: Update by timer x reset/roll-over enabled

TBU

Bit 20: TBU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

TCU

Bit 21: TCU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

TDU

Bit 22: TDU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

TEU

Bit 23: TEU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

MSTU

Bit 24: Master Timer update.

Allowed values:
0: Disabled: Update by master timer disabled
1: Enabled: Update by master timer enabled

DACSYNC

Bits 25-26: AC Synchronization.

Allowed values:
0: Disabled: No DAC trigger generated
1: DACSync1: Trigger generated on DACSync1
2: DACSync2: Trigger generated on DACSync2
3: DACSync3: Trigger generated on DACSync3

PREEN

Bit 27: Preload enable.

Allowed values:
0: Disabled: Preload disabled: the write access is directly done into the active register
1: Enabled: Preload enabled: the write access is done into the preload register

UPDGAT

Bits 28-31: Update Gating.

Allowed values:
0: Independent: Update occurs independently from the DMA burst transfer
1: DMABurst: Update occurs when the DMA burst transfer is completed
2: DMABurst_Update: Update occurs on the update event following DMA burst transfer completion
3: Input1: Update occurs on a rising edge of HRTIM update enable input 1
4: Input2: Update occurs on a rising edge of HRTIM update enable input 2
5: Input3: Update occurs on a rising edge of HRTIM update enable input 3
6: Input1_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 1
7: Input2_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 2
8: Input3_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 3

ISR

Timerx Interrupt Status Register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
O2CPY
r 		O1CPY
r 		O2STAT
r 		O1STAT
r 		IPPSTAT
r 		CPPSTAT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYPRT
r 		RST
r 		RST2
r 		SET[2]
r 		RST1
r 		SET[1]
r 		CPT[2]
r 		CPT[1]
r 		UPD
r 		REP
r 		CMP[4]
r 		CMP[3]
r 		CMP[2]
r 		CMP[1]
r
Toggle fields

CMP[1]

Bit 0: Compare 1 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

CMP[2]

Bit 1: Compare 2 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

CMP[3]

Bit 2: Compare 3 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

CMP[4]

Bit 3: Compare 4 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

REP

Bit 4: Repetition Interrupt Flag.

Allowed values:
0: NoEvent: No timer repetition interrupt occurred
1: Event: Timer repetition interrupt occurred

UPD

Bit 6: Update Interrupt Flag.

Allowed values:
0: NoEvent: No timer update interrupt occurred
1: Event: Timer update interrupt occurred

CPT[1]

Bit 7: Capture1 Interrupt Flag.

Allowed values:
0: NoEvent: No timer x capture reset interrupt occurred
1: Event: Timer x capture reset interrupt occurred

CPT[2]

Bit 8: Capture2 Interrupt Flag.

Allowed values:
0: NoEvent: No timer x capture reset interrupt occurred
1: Event: Timer x capture reset interrupt occurred

SET[1]

Bit 9: Output 1 Set Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output set interrupt occurred
1: Event: Tx output set interrupt occurred

RST1

Bit 10: Output 1 Reset Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output reset interrupt occurred
1: Event: Tx output reset interrupt occurred

SET[2]

Bit 11: Output 2 Set Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output set interrupt occurred
1: Event: Tx output set interrupt occurred

RST2

Bit 12: Output 2 Reset Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output reset interrupt occurred
1: Event: Tx output reset interrupt occurred

RST

Bit 13: Reset Interrupt Flag.

Allowed values:
0: NoEvent: No TIMx counter reset/roll-over interrupt occurred
1: Event: TIMx counter reset/roll-over interrupt occurred

DLYPRT

Bit 14: Delayed Protection Flag.

Allowed values:
0: Inactive: Not in delayed idle or balanced idle mode
1: Active: Delayed idle or balanced idle mode entry

CPPSTAT

Bit 16: Current Push Pull Status.

Allowed values:
0: Output1Active: Signal applied on output 1 and output 2 forced inactive
1: Output2Active: Signal applied on output 2 and output 1 forced inactive

IPPSTAT

Bit 17: Idle Push Pull Status.

Allowed values:
0: Output1Active: Protection occurred when the output 1 was active and output 2 forced inactive
1: Output2Active: Protection occurred when the output 2 was active and output 1 forced inactive

O1STAT

Bit 18: Output 1 State.

Allowed values:
0: Inactive: Output was inactive
1: Active: Output was active

O2STAT

Bit 19: Output 2 State.

Allowed values:
0: Inactive: Output was inactive
1: Active: Output was active

O1CPY

Bit 20: Output 1 Copy.

Allowed values:
0: Inactive: Output is inactive
1: Active: Output is active

O2CPY

Bit 21: Output 2 Copy.

Allowed values:
0: Inactive: Output is inactive
1: Active: Output is active

ICR

Timerx Interrupt Clear Register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

14/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYPRTC
w 		RSTC
w 		RST2C
w 		SET[2]C
w 		RST1C
w 		SET[1]C
w 		CPT[2]C
w 		CPT[1]C
w 		UPDC
w 		REPC
w 		CMP[4]C
w 		CMP[3]C
w 		CMP[2]C
w 		CMP[1]C
w
Toggle fields

CMP[1]C

Bit 0: Compare 1 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CMP[2]C

Bit 1: Compare 2 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CMP[3]C

Bit 2: Compare 3 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CMP[4]C

Bit 3: Compare 4 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

REPC

Bit 4: Repetition Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

UPDC

Bit 6: Update Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CPT[1]C

Bit 7: Capture1 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CPT[2]C

Bit 8: Capture2 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

SET[1]C

Bit 9: Output 1 Set flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

RST1C

Bit 10: Output 1 Reset flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

SET[2]C

Bit 11: Output 2 Set flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

RST2C

Bit 12: Output 2 Reset flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

RSTC

Bit 13: Reset Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

DLYPRTC

Bit 14: Delayed Protection Flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

DIER

TIMxDIER5

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLYPRTDE
rw 		RSTDE
rw 		RST2DE
rw 		SET[2]DE
rw 		RST1DE
rw 		SET[1]DE
rw 		CPT[2]DE
rw 		CPT[1]DE
rw 		UPDDE
rw 		REPDE
rw 		CMP[4]DE
rw 		CMP[3]DE
rw 		CMP[2]DE
rw 		CMP[1]DE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYPRTIE
rw 		RSTIE
rw 		RST2IE
rw 		SET[2]IE
rw 		RST1IE
rw 		SET[1]IE
rw 		CPT[2]IE
rw 		CPT[1]IE
rw 		UPDIE
rw 		REPIE
rw 		CMP[4]IE
rw 		CMP[3]IE
rw 		CMP[2]IE
rw 		CMP[1]IE
rw
Toggle fields

CMP[1]IE

Bit 0: CMP1IE.

Allowed values:
0: Disabled: Compare interrupt disabled
1: Enabled: Compare interrupt enabled

CMP[2]IE

Bit 1: CMP2IE.

Allowed values:
0: Disabled: Compare interrupt disabled
1: Enabled: Compare interrupt enabled

CMP[3]IE

Bit 2: CMP3IE.

Allowed values:
0: Disabled: Compare interrupt disabled
1: Enabled: Compare interrupt enabled

CMP[4]IE

Bit 3: CMP4IE.

Allowed values:
0: Disabled: Compare interrupt disabled
1: Enabled: Compare interrupt enabled

REPIE

Bit 4: REPIE.

Allowed values:
0: Disabled: Repetition interrupt disabled
1: Enabled: Repetition interrupt enabled

UPDIE

Bit 6: UPDIE.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CPT[1]IE

Bit 7: CPT1IE.

Allowed values:
0: Disabled: Capture interrupt disabled
1: Enabled: Capture interrupt enabled

CPT[2]IE

Bit 8: CPT2IE.

Allowed values:
0: Disabled: Capture interrupt disabled
1: Enabled: Capture interrupt enabled

SET[1]IE

Bit 9: Output 1 set interrupt enable.

Allowed values:
0: Disabled: Tx output set interrupt disabled
1: Enabled: Tx output set interrupt enabled

RST1IE

Bit 10: RSTx1IE.

Allowed values:
0: Disabled: Tx output reset interrupt disabled
1: Enabled: Tx output reset interrupt enabled

SET[2]IE

Bit 11: Output 2 set interrupt enable.

Allowed values:
0: Disabled: Tx output set interrupt disabled
1: Enabled: Tx output set interrupt enabled

RST2IE

Bit 12: RSTx2IE.

Allowed values:
0: Disabled: Tx output reset interrupt disabled
1: Enabled: Tx output reset interrupt enabled

RSTIE

Bit 13: RSTIE.

Allowed values:
0: Disabled: Timer x counter/reset roll-over interrupt disabled
1: Enabled: Timer x counter/reset roll-over interrupt enabled

DLYPRTIE

Bit 14: DLYPRTIE.

Allowed values:
0: Disabled: Delayed protection interrupt disabled
1: Enabled: Delayed protection interrupt enabled

CMP[1]DE

Bit 16: CMP1DE.

Allowed values:
0: Disabled: Compare DMA request disabled
1: Enabled: Compare DMA request enabled

CMP[2]DE

Bit 17: CMP2DE.

Allowed values:
0: Disabled: Compare DMA request disabled
1: Enabled: Compare DMA request enabled

CMP[3]DE

Bit 18: CMP3DE.

Allowed values:
0: Disabled: Compare DMA request disabled
1: Enabled: Compare DMA request enabled

CMP[4]DE

Bit 19: CMP4DE.

Allowed values:
0: Disabled: Compare DMA request disabled
1: Enabled: Compare DMA request enabled

REPDE

Bit 20: REPDE.

Allowed values:
0: Disabled: Repetition DMA request disabled
1: Enabled: Repetition DMA request enabled

UPDDE

Bit 22: UPDDE.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CPT[1]DE

Bit 23: CPT1DE.

Allowed values:
0: Disabled: Capture DMA request disabled
1: Enabled: Capture DMA request enabled

CPT[2]DE

Bit 24: CPT2DE.

Allowed values:
0: Disabled: Capture DMA request disabled
1: Enabled: Capture DMA request enabled

SET[1]DE

Bit 25: Output 1 set DMA request enable.

Allowed values:
0: Disabled: Tx output set DMA request disabled
1: Enabled: Tx output set DMA request enabled

RST1DE

Bit 26: RSTx1DE.

Allowed values:
0: Disabled: Tx output reset DMA request disabled
1: Enabled: Tx output reset DMA request enabled

SET[2]DE

Bit 27: Output 2 set DMA request enable.

Allowed values:
0: Disabled: Tx output set DMA request disabled
1: Enabled: Tx output set DMA request enabled

RST2DE

Bit 28: RSTx2DE.

Allowed values:
0: Disabled: Tx output reset DMA request disabled
1: Enabled: Tx output reset DMA request enabled

RSTDE

Bit 29: RSTDE.

Allowed values:
0: Disabled: Timer x counter reset/roll-over DMA request disabled
1: Enabled: Timer x counter reset/roll-over DMA request enabled

DLYPRTDE

Bit 30: DLYPRTDE.

Allowed values:
0: Disabled: Delayed protection DMA request disabled
1: Enabled: Delayed protection DMA request enabled

CNTR

Timerx Counter Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: Counter value.

Allowed values: 0x0-0xffff

PERR

Timerx Period Register

Offset: 0x14, size: 32, reset: 0x0000FFFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PER
rw
Toggle fields

PER

Bits 0-15: Master Timer Period value.

Allowed values: 0x0-0xffff

REPR

Timerx Repetition Register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Master Timer Repetition counter value.

Allowed values: 0x0-0xff

CMP1R

Timerx Compare 1 Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CMP1CR

Timerx Compare 1 Compound Register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP1
rw
Toggle fields

CMP1

Bits 0-15: Timerx Compare 1 value.

Allowed values: 0x0-0xffff

REP

Bits 16-23: Timerx Repetition value (aliased from HRTIM_REPx register).

Allowed values: 0x0-0xff

CMP2R

Timerx Compare 2 Register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CMP3R

Timerx Compare 3 Register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CMP4R

Timerx Compare 4 Register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CPT1R

Timerx Capture 1 Register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPT
r
Toggle fields

CPT

Bits 0-15: Timerx Capture 1 value.

Allowed values: 0x0-0xffff

CPT2R

Timerx Capture 2 Register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPT
r
Toggle fields

CPT

Bits 0-15: Timerx Capture 1 value.

Allowed values: 0x0-0xffff

DTR

Timerx Deadtime Register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTFLK
rw 		DTFSLK
rw 		SDTF
rw 		DTF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTRLK
rw 		DTRSLK
rw 		DTPRSC
rw 		SDTR
rw 		DTR
rw
Toggle fields

DTR

Bits 0-8: Deadtime Rising value.

Allowed values: 0x0-0x1ff

SDTR

Bit 9: Sign Deadtime Rising value.

Allowed values:
0: Positive: Positive deadtime on rising edge
1: Negative: Negative deadtime on rising edge

DTPRSC

Bits 10-12: Deadtime Prescaler.

Allowed values: 0x0-0x7

DTRSLK

Bit 14: Deadtime Rising Sign Lock.

Allowed values:
0: Unlocked: Deadtime rising sign is writable
1: Locked: Deadtime rising sign is read-only

DTRLK

Bit 15: Deadtime Rising Lock.

Allowed values:
0: Unlocked: Deadtime rising value and sign is writable
1: Locked: Deadtime rising value and sign is read-only

DTF

Bits 16-24: Deadtime Falling value.

Allowed values: 0x0-0x1ff

SDTF

Bit 25: Sign Deadtime Falling value.

Allowed values:
0: Positive: Positive deadtime on falling edge
1: Negative: Negative deadtime on falling edge

DTFSLK

Bit 30: Deadtime Falling Sign Lock.

Allowed values:
0: Unlocked: Deadtime falling sign is writable
1: Locked: Deadtime falling sign is read-only

DTFLK

Bit 31: Deadtime Falling Lock.

Allowed values:
0: Unlocked: Deadtime falling value and sign is writable
1: Locked: Deadtime falling value and sign is read-only

SET1R

Timerx Output1 Set Register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPDATE
rw 		EXTEVNT[10]
rw 		EXTEVNT[9]
rw 		EXTEVNT[8]
rw 		EXTEVNT[7]
rw 		EXTEVNT[6]
rw 		EXTEVNT[5]
rw 		EXTEVNT[4]
rw 		EXTEVNT[3]
rw 		EXTEVNT[2]
rw 		EXTEVNT[1]
rw 		TIMDCMP4
rw 		TIMDCMP2
rw 		TIMDCMP1
rw 		TIMCCMP2
rw 		TIMCCMP1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMBCMP4
rw 		TIMBCMP3
rw 		TIMACMP4
rw 		TIMACMP3
rw 		MSTCMP[4]
rw 		MSTCMP[3]
rw 		MSTCMP[2]
rw 		MSTCMP[1]
rw 		MSTPER
rw 		CMP[4]
rw 		CMP[3]
rw 		CMP[2]
rw 		CMP[1]
rw 		PER
rw 		RESYNC
rw 		SST
rw
Toggle fields

SST

Bit 0: Software Set trigger.

Allowed values:
0: NoEffect: No effect
1: SetActive: Force output to its active state

RESYNC

Bit 1: Timer A resynchronizaton.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetActive: Timer reset event coming solely from software or SYNC input event forces the output to its active state

PER

Bit 2: Timer A Period.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetActive: Timer period event forces the output to its active state

CMP[1]

Bit 3: Timer A compare 1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[2]

Bit 4: Timer A compare 2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[3]

Bit 5: Timer A compare 3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[4]

Bit 6: Timer A compare 4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

MSTPER

Bit 7: Master Period.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetActive: Master timer counter roll-over/reset forces the output to its active state

MSTCMP[1]

Bit 8: Master Compare 1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[2]

Bit 9: Master Compare 2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[3]

Bit 10: Master Compare 3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[4]

Bit 11: Master Compare 4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

TIMACMP3

Bit 12: Timer A Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMACMP4

Bit 13: Timer A Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMBCMP3

Bit 14: Timer B Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMBCMP4

Bit 15: Timer B Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMCCMP1

Bit 16: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMCCMP2

Bit 17: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMDCMP1

Bit 18: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMDCMP2

Bit 19: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMDCMP4

Bit 20: Timer D Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

EXTEVNT[1]

Bit 21: External Event 1.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[2]

Bit 22: External Event 2.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[3]

Bit 23: External Event 3.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[4]

Bit 24: External Event 4.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[5]

Bit 25: External Event 5.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[6]

Bit 26: External Event 6.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[7]

Bit 27: External Event 7.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[8]

Bit 28: External Event 8.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[9]

Bit 29: External Event 9.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[10]

Bit 30: External Event 10.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

UPDATE

Bit 31: Registers update (transfer preload to active).

Allowed values:
0: NoEffect: Register update event has no effect
1: SetActive: Register update event forces the output to its active state

RST1R

Timerx Output1 Reset Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPDATE
rw 		EXTEVNT[10]
rw 		EXTEVNT[9]
rw 		EXTEVNT[8]
rw 		EXTEVNT[7]
rw 		EXTEVNT[6]
rw 		EXTEVNT[5]
rw 		EXTEVNT[4]
rw 		EXTEVNT[3]
rw 		EXTEVNT[2]
rw 		EXTEVNT[1]
rw 		TIMDCMP4
rw 		TIMDCMP2
rw 		TIMDCMP1
rw 		TIMCCMP2
rw 		TIMCCMP1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMBCMP4
rw 		TIMBCMP3
rw 		TIMACMP4
rw 		TIMACMP3
rw 		MSTCMP[4]
rw 		MSTCMP[3]
rw 		MSTCMP[2]
rw 		MSTCMP[1]
rw 		MSTPER
rw 		CMP[4]
rw 		CMP[3]
rw 		CMP[2]
rw 		CMP[1]
rw 		PER
rw 		RESYNC
rw 		SRT
rw
Toggle fields

SRT

Bit 0: SRT.

Allowed values:
0: NoEffect: No effect
1: SetInactive: Force output to its inactive state

RESYNC

Bit 1: RESYNC.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetInactive: Timer reset event coming solely from software or SYNC input event forces the output to its inactive state

PER

Bit 2: PER.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetInactive: Timer period event forces the output to its inactive state

CMP[1]

Bit 3: CMP1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[2]

Bit 4: CMP2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[3]

Bit 5: CMP3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[4]

Bit 6: CMP4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

MSTPER

Bit 7: MSTPER.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetInactive: Master timer counter roll-over/reset forces the output to its inactive state

MSTCMP[1]

Bit 8: MSTCMP1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[2]

Bit 9: MSTCMP2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[3]

Bit 10: MSTCMP3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[4]

Bit 11: MSTCMP4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

TIMACMP3

Bit 12: Timer A Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMACMP4

Bit 13: Timer A Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMBCMP3

Bit 14: Timer B Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMBCMP4

Bit 15: Timer B Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMCCMP1

Bit 16: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMCCMP2

Bit 17: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMDCMP1

Bit 18: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMDCMP2

Bit 19: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMDCMP4

Bit 20: Timer D Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

EXTEVNT[1]

Bit 21: EXTEVNT1.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[2]

Bit 22: EXTEVNT2.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[3]

Bit 23: EXTEVNT3.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[4]

Bit 24: EXTEVNT4.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[5]

Bit 25: EXTEVNT5.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[6]

Bit 26: EXTEVNT6.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[7]

Bit 27: EXTEVNT7.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[8]

Bit 28: EXTEVNT8.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[9]

Bit 29: EXTEVNT9.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[10]

Bit 30: EXTEVNT10.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

UPDATE

Bit 31: UPDATE.

Allowed values:
0: NoEffect: Register update event has no effect
1: SetInactive: Register update event forces the output to its inactive state

SET2R

Timerx Output2 Set Register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPDATE
rw 		EXTEVNT[10]
rw 		EXTEVNT[9]
rw 		EXTEVNT[8]
rw 		EXTEVNT[7]
rw 		EXTEVNT[6]
rw 		EXTEVNT[5]
rw 		EXTEVNT[4]
rw 		EXTEVNT[3]
rw 		EXTEVNT[2]
rw 		EXTEVNT[1]
rw 		TIMDCMP4
rw 		TIMDCMP2
rw 		TIMDCMP1
rw 		TIMCCMP2
rw 		TIMCCMP1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMBCMP4
rw 		TIMBCMP3
rw 		TIMACMP4
rw 		TIMACMP3
rw 		MSTCMP[4]
rw 		MSTCMP[3]
rw 		MSTCMP[2]
rw 		MSTCMP[1]
rw 		MSTPER
rw 		CMP[4]
rw 		CMP[3]
rw 		CMP[2]
rw 		CMP[1]
rw 		PER
rw 		RESYNC
rw 		SST
rw
Toggle fields

SST

Bit 0: Software Set trigger.

Allowed values:
0: NoEffect: No effect
1: SetActive: Force output to its active state

RESYNC

Bit 1: Timer A resynchronizaton.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetActive: Timer reset event coming solely from software or SYNC input event forces the output to its active state

PER

Bit 2: Timer A Period.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetActive: Timer period event forces the output to its active state

CMP[1]

Bit 3: Timer A compare 1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[2]

Bit 4: Timer A compare 2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[3]

Bit 5: Timer A compare 3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[4]

Bit 6: Timer A compare 4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

MSTPER

Bit 7: Master Period.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetActive: Master timer counter roll-over/reset forces the output to its active state

MSTCMP[1]

Bit 8: Master Compare 1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[2]

Bit 9: Master Compare 2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[3]

Bit 10: Master Compare 3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[4]

Bit 11: Master Compare 4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

TIMACMP3

Bit 12: Timer A Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMACMP4

Bit 13: Timer A Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMBCMP3

Bit 14: Timer B Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMBCMP4

Bit 15: Timer B Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMCCMP1

Bit 16: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMCCMP2

Bit 17: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMDCMP1

Bit 18: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMDCMP2

Bit 19: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMDCMP4

Bit 20: Timer D Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

EXTEVNT[1]

Bit 21: External Event 1.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[2]

Bit 22: External Event 2.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[3]

Bit 23: External Event 3.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[4]

Bit 24: External Event 4.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[5]

Bit 25: External Event 5.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[6]

Bit 26: External Event 6.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[7]

Bit 27: External Event 7.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[8]

Bit 28: External Event 8.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[9]

Bit 29: External Event 9.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[10]

Bit 30: External Event 10.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

UPDATE

Bit 31: Registers update (transfer preload to active).

Allowed values:
0: NoEffect: Register update event has no effect
1: SetActive: Register update event forces the output to its active state

RST2R

Timerx Output2 Reset Register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPDATE
rw 		EXTEVNT[10]
rw 		EXTEVNT[9]
rw 		EXTEVNT[8]
rw 		EXTEVNT[7]
rw 		EXTEVNT[6]
rw 		EXTEVNT[5]
rw 		EXTEVNT[4]
rw 		EXTEVNT[3]
rw 		EXTEVNT[2]
rw 		EXTEVNT[1]
rw 		TIMDCMP4
rw 		TIMDCMP2
rw 		TIMDCMP1
rw 		TIMCCMP2
rw 		TIMCCMP1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMBCMP4
rw 		TIMBCMP3
rw 		TIMACMP4
rw 		TIMACMP3
rw 		MSTCMP[4]
rw 		MSTCMP[3]
rw 		MSTCMP[2]
rw 		MSTCMP[1]
rw 		MSTPER
rw 		CMP[4]
rw 		CMP[3]
rw 		CMP[2]
rw 		CMP[1]
rw 		PER
rw 		RESYNC
rw 		SRT
rw
Toggle fields

SRT

Bit 0: SRT.

Allowed values:
0: NoEffect: No effect
1: SetInactive: Force output to its inactive state

RESYNC

Bit 1: RESYNC.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetInactive: Timer reset event coming solely from software or SYNC input event forces the output to its inactive state

PER

Bit 2: PER.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetInactive: Timer period event forces the output to its inactive state

CMP[1]

Bit 3: CMP1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[2]

Bit 4: CMP2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[3]

Bit 5: CMP3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[4]

Bit 6: CMP4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

MSTPER

Bit 7: MSTPER.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetInactive: Master timer counter roll-over/reset forces the output to its inactive state

MSTCMP[1]

Bit 8: MSTCMP1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[2]

Bit 9: MSTCMP2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[3]

Bit 10: MSTCMP3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[4]

Bit 11: MSTCMP4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

TIMACMP3

Bit 12: Timer A Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMACMP4

Bit 13: Timer A Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMBCMP3

Bit 14: Timer B Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMBCMP4

Bit 15: Timer B Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMCCMP1

Bit 16: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMCCMP2

Bit 17: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMDCMP1

Bit 18: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMDCMP2

Bit 19: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMDCMP4

Bit 20: Timer D Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

EXTEVNT[1]

Bit 21: EXTEVNT1.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[2]

Bit 22: EXTEVNT2.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[3]

Bit 23: EXTEVNT3.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[4]

Bit 24: EXTEVNT4.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[5]

Bit 25: EXTEVNT5.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[6]

Bit 26: EXTEVNT6.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[7]

Bit 27: EXTEVNT7.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[8]

Bit 28: EXTEVNT8.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[9]

Bit 29: EXTEVNT9.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[10]

Bit 30: EXTEVNT10.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

UPDATE

Bit 31: UPDATE.

Allowed values:
0: NoEffect: Register update event has no effect
1: SetInactive: Register update event forces the output to its inactive state

EEFR1

Timerx External Event Filtering Register 1

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EE[5]FLTR
rw 		EE[5]LTCH
rw 		EE[4]FLTR
rw 		EE[4]LTCH
rw 		EE[3]FLTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EE[3]FLTR
rw 		EE[3]LTCH
rw 		EE[2]FLTR
rw 		EE[2]LTCH
rw 		EE[1]FLTR
rw 		EE[1]LTCH
rw
Toggle fields

EE[1]LTCH

Bit 0: External Event 1 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[1]FLTR

Bits 1-4: External Event 1 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[2]LTCH

Bit 6: External Event 2 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[2]FLTR

Bits 7-10: External Event 2 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[3]LTCH

Bit 12: External Event 3 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[3]FLTR

Bits 13-16: External Event 3 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[4]LTCH

Bit 18: External Event 4 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[4]FLTR

Bits 19-22: External Event 4 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[5]LTCH

Bit 24: External Event 5 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[5]FLTR

Bits 25-28: External Event 5 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EEFR2

Timerx External Event Filtering Register 2

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EE[10]FLTR
rw 		EE[10]LTCH
rw 		EE[9]FLTR
rw 		EE[9]LTCH
rw 		EE[8]FLTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EE[8]FLTR
rw 		EE[8]LTCH
rw 		EE[7]FLTR
rw 		EE[7]LTCH
rw 		EE[6]FLTR
rw 		EE[6]LTCH
rw
Toggle fields

EE[6]LTCH

Bit 0: External Event 6 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[6]FLTR

Bits 1-4: External Event 6 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[7]LTCH

Bit 6: External Event 7 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[7]FLTR

Bits 7-10: External Event 7 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[8]LTCH

Bit 12: External Event 8 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[8]FLTR

Bits 13-16: External Event 8 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[9]LTCH

Bit 18: External Event 9 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[9]FLTR

Bits 19-22: External Event 9 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[10]LTCH

Bit 24: External Event 10 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[10]FLTR

Bits 25-28: External Event 10 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

RSTR

TimerA Reset Register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

30/30 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIMDCMP4
rw 		TIMDCMP2
rw 		TIMDCMP1
rw 		TIMCCMP4
rw 		TIMCCMP2
rw 		TIMCCMP1
rw 		TIMBCMP4
rw 		TIMBCMP2
rw 		TIMBCMP1
rw 		TIMACMP4
rw 		TIMACMP2
rw 		TIMACMP1
rw 		EXTEVNT10
rw 		EXTEVNT9
rw 		EXTEVNT8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTEVNT7
rw 		EXTEVNT6
rw 		EXTEVNT5
rw 		EXTEVNT4
rw 		EXTEVNT3
rw 		EXTEVNT2
rw 		EXTEVNT1
rw 		MSTCMP4
rw 		MSTCMP3
rw 		MSTCMP2
rw 		MSTCMP1
rw 		MSTPER
rw 		CMP4
rw 		CMP2
rw 		UPDT
rw
Toggle fields

UPDT

Bit 1: Timer A Update reset.

Allowed values:
0: NoEffect: Update event has no effect
1: ResetCounter: Timer X counter is reset upon update event

CMP2

Bit 2: Timer A compare 2 reset.

Allowed values:
0: NoEffect: Timer X compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer X compare Z event

CMP4

Bit 3: Timer A compare 4 reset.

Allowed values:
0: NoEffect: Timer X compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer X compare Z event

MSTPER

Bit 4: Master timer Period.

Allowed values:
0: NoEffect: Master timer period event has no effect
1: ResetCounter: Timer X counter is reset upon master timer period event

MSTCMP1

Bit 5: Master compare 1.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

MSTCMP2

Bit 6: Master compare 2.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

MSTCMP3

Bit 7: Master compare 3.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

MSTCMP4

Bit 8: Master compare 4.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

EXTEVNT1

Bit 9: External Event 1.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT2

Bit 10: External Event 2.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT3

Bit 11: External Event 3.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT4

Bit 12: External Event 4.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT5

Bit 13: External Event 5.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT6

Bit 14: External Event 6.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT7

Bit 15: External Event 7.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT8

Bit 16: External Event 8.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT9

Bit 17: External Event 9.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT10

Bit 18: External Event 10.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

TIMACMP1

Bit 19: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMACMP2

Bit 20: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMACMP4

Bit 21: Timer A Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMBCMP1

Bit 22: Timer B Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMBCMP2

Bit 23: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMBCMP4

Bit 24: Timer B Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMCCMP1

Bit 25: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMCCMP2

Bit 26: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMCCMP4

Bit 27: Timer C Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMDCMP1

Bit 28: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMDCMP2

Bit 29: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMDCMP4

Bit 30: Timer D Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

CHPR

Timerx Chopper Register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STRTPW
rw 		CARDTY
rw 		CARFRQ
rw
Toggle fields

CARFRQ

Bits 0-3: Timerx carrier frequency value.

Allowed values: 0x0-0xf

CARDTY

Bits 4-6: Timerx chopper duty cycle value.

Allowed values: 0x0-0x7

STRTPW

Bits 7-10: STRTPW.

Allowed values: 0x0-0xf

CPT1CR

Timerx Capture 2 Control Register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDCMP2
rw 		TDCMP1
rw 		TD1RST
rw 		TD1SET
rw 		TCCMP2
rw 		TCCMP1
rw 		TC1RST
rw 		TC1SET
rw 		TBCMP2
rw 		TBCMP1
rw 		TB1RST
rw 		TB1SET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TACMP2
rw 		TACMP1
rw 		TA1RST
rw 		TA1SET
rw 		EXEV[10]CPT
rw 		EXEV[9]CPT
rw 		EXEV[8]CPT
rw 		EXEV[7]CPT
rw 		EXEV[6]CPT
rw 		EXEV[5]CPT
rw 		EXEV[4]CPT
rw 		EXEV[3]CPT
rw 		EXEV[2]CPT
rw 		EXEV[1]CPT
rw 		UPDCPT
rw 		SWCPT
rw
Toggle fields

SWCPT

Bit 0: Software Capture.

Allowed values:
0: NoEffect: No effect
1: TriggerCapture: Force capture Z

UPDCPT

Bit 1: Update Capture.

Allowed values:
0: NoEffect: Update event has no effect
1: TriggerCapture: Update event triggers capture Z

EXEV[1]CPT

Bit 2: External Event 1 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[2]CPT

Bit 3: External Event 2 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[3]CPT

Bit 4: External Event 3 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[4]CPT

Bit 5: External Event 4 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[5]CPT

Bit 6: External Event 5 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[6]CPT

Bit 7: External Event 6 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[7]CPT

Bit 8: External Event 7 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[8]CPT

Bit 9: External Event 8 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[9]CPT

Bit 10: External Event 9 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[10]CPT

Bit 11: External Event 10 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

TA1SET

Bit 12: Timer A output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TA1RST

Bit 13: Timer A output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TACMP1

Bit 14: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TACMP2

Bit 15: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TB1SET

Bit 16: Timer B output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TB1RST

Bit 17: Timer B output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TBCMP1

Bit 18: Timer B Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TBCMP2

Bit 19: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TC1SET

Bit 20: Timer C output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TC1RST

Bit 21: Timer C output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TCCMP1

Bit 22: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TCCMP2

Bit 23: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TD1SET

Bit 24: Timer D output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TD1RST

Bit 25: Timer D output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TDCMP1

Bit 26: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TDCMP2

Bit 27: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

CPT2CR

CPT2xCR

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDCMP2
rw 		TDCMP1
rw 		TD1RST
rw 		TD1SET
rw 		TCCMP2
rw 		TCCMP1
rw 		TC1RST
rw 		TC1SET
rw 		TBCMP2
rw 		TBCMP1
rw 		TB1RST
rw 		TB1SET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TACMP2
rw 		TACMP1
rw 		TA1RST
rw 		TA1SET
rw 		EXEV[10]CPT
rw 		EXEV[9]CPT
rw 		EXEV[8]CPT
rw 		EXEV[7]CPT
rw 		EXEV[6]CPT
rw 		EXEV[5]CPT
rw 		EXEV[4]CPT
rw 		EXEV[3]CPT
rw 		EXEV[2]CPT
rw 		EXEV[1]CPT
rw 		UPDCPT
rw 		SWCPT
rw
Toggle fields

SWCPT

Bit 0: Software Capture.

Allowed values:
0: NoEffect: No effect
1: TriggerCapture: Force capture Z

UPDCPT

Bit 1: Update Capture.

Allowed values:
0: NoEffect: Update event has no effect
1: TriggerCapture: Update event triggers capture Z

EXEV[1]CPT

Bit 2: External Event 1 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[2]CPT

Bit 3: External Event 2 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[3]CPT

Bit 4: External Event 3 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[4]CPT

Bit 5: External Event 4 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[5]CPT

Bit 6: External Event 5 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[6]CPT

Bit 7: External Event 6 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[7]CPT

Bit 8: External Event 7 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[8]CPT

Bit 9: External Event 8 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[9]CPT

Bit 10: External Event 9 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[10]CPT

Bit 11: External Event 10 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

TA1SET

Bit 12: Timer A output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TA1RST

Bit 13: Timer A output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TACMP1

Bit 14: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TACMP2

Bit 15: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TB1SET

Bit 16: Timer B output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TB1RST

Bit 17: Timer B output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TBCMP1

Bit 18: Timer B Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TBCMP2

Bit 19: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TC1SET

Bit 20: Timer C output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TC1RST

Bit 21: Timer C output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TCCMP1

Bit 22: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TCCMP2

Bit 23: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TD1SET

Bit 24: Timer D output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TD1RST

Bit 25: Timer D output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TDCMP1

Bit 26: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TDCMP2

Bit 27: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

OUTR

Timerx Output Register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIDL2
rw 		CHP2
rw 		FAULT2
rw 		IDLES2
rw 		IDLEM2
rw 		POL2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYPRT
rw 		DLYPRTEN
rw 		DTEN
rw 		DIDL1
rw 		CHP1
rw 		FAULT1
rw 		IDLES1
rw 		IDLEM1
rw 		POL1
rw
Toggle fields

POL1

Bit 1: Output 1 polarity.

Allowed values:
0: ActiveHigh: Positive polarity (output active high)
1: ActiveLow: Negative polarity (output active low)

IDLEM1

Bit 2: Output 1 Idle mode.

Allowed values:
0: NoEffect: No action: the output is not affected by the burst mode operation
1: SetIdle: The output is in idle state when requested by the burst mode controller

IDLES1

Bit 3: Output 1 Idle State.

Allowed values:
0: Inactive: Output idle state is inactive
1: Active: Output idle state is active

FAULT1

Bits 4-5: Output 1 Fault state.

Allowed values:
0: Disabled: No action: the output is not affected by the fault input and stays in run mode
1: SetActive: Output goes to active state after a fault event
2: SetInactive: Output goes to inactive state after a fault event
3: SetHighZ: Output goes to high-z state after a fault event

CHP1

Bit 6: Output 1 Chopper enable.

Allowed values:
0: Disabled: Output signal not altered
1: Enabled: Output signal is chopped by a carrier signal

DIDL1

Bit 7: Output 1 Deadtime upon burst mode Idle entry.

Allowed values:
0: Disabled: The programmed idle state is applied immediately to the output
1: Enabled: Deadtime (inactive level) is inserted on output before entering the idle mode

DTEN

Bit 8: Deadtime enable.

Allowed values:
0: Disabled: Output 1 and 2 signals are independent
1: Enabled: Deadtime is inserted between output 1 and output 2

DLYPRTEN

Bit 9: Delayed Protection Enable.

Allowed values:
0: Disabled: No action
1: Enabled: Delayed protection is enabled, as per DLYPRT bits

DLYPRT

Bits 10-12: Delayed Protection.

Allowed values:
0: Output1_EE6: Output 1 delayed idle on external event 6
1: Output2_EE6: Output 2 delayed idle on external event 6
2: Output1_2_EE6: Output 1 and 2 delayed idle on external event 6
3: Balanced_EE6: Balanced idle on external event 6
4: Output1_EE7: Output 1 delayed idle on external event 7
5: Output2_EE7: Output 2 delayed idle on external event 7
6: Output1_2_EE7: Output 1 and 2 delayed idle on external event 7
7: Balanced_EE7: Balanced idle on external event 7

POL2

Bit 17: Output 2 polarity.

Allowed values:
0: ActiveHigh: Positive polarity (output active high)
1: ActiveLow: Negative polarity (output active low)

IDLEM2

Bit 18: Output 2 Idle mode.

Allowed values:
0: NoEffect: No action: the output is not affected by the burst mode operation
1: SetIdle: The output is in idle state when requested by the burst mode controller

IDLES2

Bit 19: Output 2 Idle State.

Allowed values:
0: Inactive: Output idle state is inactive
1: Active: Output idle state is active

FAULT2

Bits 20-21: Output 2 Fault state.

Allowed values:
0: Disabled: No action: the output is not affected by the fault input and stays in run mode
1: SetActive: Output goes to active state after a fault event
2: SetInactive: Output goes to inactive state after a fault event
3: SetHighZ: Output goes to high-z state after a fault event

CHP2

Bit 22: Output 2 Chopper enable.

Allowed values:
0: Disabled: Output signal not altered
1: Enabled: Output signal is chopped by a carrier signal

DIDL2

Bit 23: Output 2 Deadtime upon burst mode Idle entry.

Allowed values:
0: Disabled: The programmed idle state is applied immediately to the output
1: Enabled: Deadtime (inactive level) is inserted on output before entering the idle mode

FLTR

Timerx Fault Register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLTLCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLT[5]EN
rw 		FLT[4]EN
rw 		FLT[3]EN
rw 		FLT[2]EN
rw 		FLT[1]EN
rw
Toggle fields

FLT[1]EN

Bit 0: Fault 1 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[2]EN

Bit 1: Fault 2 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[3]EN

Bit 2: Fault 3 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[4]EN

Bit 3: Fault 4 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[5]EN

Bit 4: Fault 5 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLTLCK

Bit 31: Fault sources Lock.

Allowed values:
0: Unlocked: FLT1EN..FLT5EN bits are read/write
1: Locked: FLT1EN..FLT5EN bits are read only

I2C1

0x40005400: Inter-integrated circuit

76/77 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 TIMINGR
0x14 TIMEOUTR
0x18 ISR
0x1c ICR
0x20 PECR
0x24 RXDR
0x28 TXDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

20/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw 		ALERTEN
rw 		SMBDEN
rw 		SMBHEN
rw 		GCEN
rw 		WUPEN
rw 		NOSTRETCH
rw 		SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw 		TXDMAEN
rw 		SWRST
w 		ANFOFF
rw 		DNF
rw 		ERRIE
rw 		TCIE
rw 		STOPIE
rw 		NACKIE
rw 		ADDRIE
rw 		RXIE
rw 		TXIE
rw 		PE
rw
Toggle fields

PE

Bit 0: Peripheral enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

TXIE

Bit 1: TX Interrupt enable.

Allowed values:
0: Disabled: Transmit (TXIS) interrupt disabled
1: Enabled: Transmit (TXIS) interrupt enabled

RXIE

Bit 2: RX Interrupt enable.

Allowed values:
0: Disabled: Receive (RXNE) interrupt disabled
1: Enabled: Receive (RXNE) interrupt enabled

ADDRIE

Bit 3: Address match interrupt enable (slave only).

Allowed values:
0: Disabled: Address match (ADDR) interrupts disabled
1: Enabled: Address match (ADDR) interrupts enabled

NACKIE

Bit 4: Not acknowledge received interrupt enable.

Allowed values:
0: Disabled: Not acknowledge (NACKF) received interrupts disabled
1: Enabled: Not acknowledge (NACKF) received interrupts enabled

STOPIE

Bit 5: STOP detection Interrupt enable.

Allowed values:
0: Disabled: Stop detection (STOPF) interrupt disabled
1: Enabled: Stop detection (STOPF) interrupt enabled

TCIE

Bit 6: Transfer Complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

ERRIE

Bit 7: Error interrupts enable.

Allowed values:
0: Disabled: Error detection interrupts disabled
1: Enabled: Error detection interrupts enabled

DNF

Bits 8-11: Digital noise filter.

Allowed values:
0: NoFilter: Digital filter disabled
1: Filter1: Digital filter enabled and filtering capability up to 1 tI2CCLK
2: Filter2: Digital filter enabled and filtering capability up to 2 tI2CCLK
3: Filter3: Digital filter enabled and filtering capability up to 3 tI2CCLK
4: Filter4: Digital filter enabled and filtering capability up to 4 tI2CCLK
5: Filter5: Digital filter enabled and filtering capability up to 5 tI2CCLK
6: Filter6: Digital filter enabled and filtering capability up to 6 tI2CCLK
7: Filter7: Digital filter enabled and filtering capability up to 7 tI2CCLK
8: Filter8: Digital filter enabled and filtering capability up to 8 tI2CCLK
9: Filter9: Digital filter enabled and filtering capability up to 9 tI2CCLK
10: Filter10: Digital filter enabled and filtering capability up to 10 tI2CCLK
11: Filter11: Digital filter enabled and filtering capability up to 11 tI2CCLK
12: Filter12: Digital filter enabled and filtering capability up to 12 tI2CCLK
13: Filter13: Digital filter enabled and filtering capability up to 13 tI2CCLK
14: Filter14: Digital filter enabled and filtering capability up to 14 tI2CCLK
15: Filter15: Digital filter enabled and filtering capability up to 15 tI2CCLK

ANFOFF

Bit 12: Analog noise filter OFF.

Allowed values:
0: Enabled: Analog noise filter enabled
1: Disabled: Analog noise filter disabled

SWRST

Bit 13: Software reset.

TXDMAEN

Bit 14: DMA transmission requests enable.

Allowed values:
0: Disabled: DMA mode disabled for transmission
1: Enabled: DMA mode enabled for transmission

RXDMAEN

Bit 15: DMA reception requests enable.

Allowed values:
0: Disabled: DMA mode disabled for reception
1: Enabled: DMA mode enabled for reception

SBC

Bit 16: Slave byte control.

Allowed values:
0: Disabled: Slave byte control disabled
1: Enabled: Slave byte control enabled

NOSTRETCH

Bit 17: Clock stretching disable.

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

WUPEN

Bit 18: Wakeup from STOP enable.

Allowed values:
0: Disabled: Wakeup from Stop mode disabled
1: Enabled: Wakeup from Stop mode enabled

GCEN

Bit 19: General call enable.

Allowed values:
0: Disabled: General call disabled. Address 0b00000000 is NACKed
1: Enabled: General call enabled. Address 0b00000000 is ACKed

SMBHEN

Bit 20: SMBus Host address enable.

Allowed values:
0: Disabled: Host address disabled. Address 0b0001000x is NACKed
1: Enabled: Host address enabled. Address 0b0001000x is ACKed

SMBDEN

Bit 21: SMBus Device Default address enable.

Allowed values:
0: Disabled: Device default address disabled. Address 0b1100001x is NACKed
1: Enabled: Device default address enabled. Address 0b1100001x is ACKed

ALERTEN

Bit 22: SMBUS alert enable.

Allowed values:
0: Disabled: In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
1: Enabled: In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported

PECEN

Bit 23: PEC enable.

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw 		AUTOEND
rw 		RELOAD
rw 		NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw 		STOP
rw 		START
rw 		HEAD10R
rw 		ADD10
rw 		RD_WRN
rw 		SADD
rw
Toggle fields

SADD

Bits 0-9: Slave address bit 9:8 (master mode).

Allowed values: 0x0-0x3ff

RD_WRN

Bit 10: Transfer direction (master mode).

Allowed values:
0: Write: Master requests a write transfer
1: Read: Master requests a read transfer

ADD10

Bit 11: 10-bit addressing mode (master mode).

Allowed values:
0: Bit7: The master operates in 7-bit addressing mode
1: Bit10: The master operates in 10-bit addressing mode

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

Allowed values:
0: Complete: The master sends the complete 10 bit slave address read sequence
1: Partial: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction

START

Bit 13: Start generation.

Allowed values:
0: NoStart: No Start generation
1: Start: Restart/Start generation

STOP

Bit 14: Stop generation (master mode).

Allowed values:
0: NoStop: No Stop generation
1: Stop: Stop generation after current byte transfer

NACK

Bit 15: NACK generation (slave mode).

Allowed values:
0: Ack: an ACK is sent after current received byte
1: Nack: a NACK is sent after current received byte

NBYTES

Bits 16-23: Number of bytes.

Allowed values: 0x0-0xff

RELOAD

Bit 24: NBYTES reload mode.

Allowed values:
0: Completed: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)
1: NotCompleted: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)

AUTOEND

Bit 25: Automatic end mode (master mode).

Allowed values:
0: Software: Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low
1: Automatic: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred

PECBYTE

Bit 26: Packet error checking byte.

Allowed values:
0: NoPec: No PEC transfer
1: Pec: PEC transmission/reception is requested

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw 		OA1MODE
rw 		OA1
rw
Toggle fields

OA1

Bits 0-9: Interface address.

Allowed values: 0x0-0x3ff

OA1MODE

Bit 10: Own Address 1 10-bit mode.

Allowed values:
0: Bit7: Own address 1 is a 7-bit address
1: Bit10: Own address 1 is a 10-bit address

OA1EN

Bit 15: Own Address 1 enable.

Allowed values:
0: Disabled: Own address 1 disabled. The received slave address OA1 is NACKed
1: Enabled: Own address 1 enabled. The received slave address OA1 is ACKed

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw 		OA2MSK
rw 		OA2
rw
Toggle fields

OA2

Bits 1-7: Interface address.

Allowed values: 0x0-0x7f

OA2MSK

Bits 8-10: Own Address 2 masks.

Allowed values:
0: NoMask: No mask
1: Mask1: OA2[1] is masked and don’t care. Only OA2[7:2] are compared
2: Mask2: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
3: Mask3: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
4: Mask4: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
5: Mask5: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
6: Mask6: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
7: Mask7: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged

OA2EN

Bit 15: Own Address 2 enable.

Allowed values:
0: Disabled: Own address 2 disabled. The received slave address OA2 is NACKed
1: Enabled: Own address 2 enabled. The received slave address OA2 is ACKed

TIMINGR

Timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw 		SCLDEL
rw 		SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw 		SCLL
rw
Toggle fields

SCLL

Bits 0-7: SCL low period (master mode).

Allowed values: 0x0-0xff

SCLH

Bits 8-15: SCL high period (master mode).

Allowed values: 0x0-0xff

SDADEL

Bits 16-19: Data hold time.

Allowed values: 0x0-0xf

SCLDEL

Bits 20-23: Data setup time.

Allowed values: 0x0-0xf

PRESC

Bits 28-31: Timing prescaler.

Allowed values: 0x0-0xf

TIMEOUTR

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw 		TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw 		TIDLE
rw 		TIMEOUTA
rw
Toggle fields

TIMEOUTA

Bits 0-11: Bus timeout A.

Allowed values: 0x0-0xfff

TIDLE

Bit 12: Idle clock timeout detection.

Allowed values:
0: Disabled: TIMEOUTA is used to detect SCL low timeout
1: Enabled: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)

TIMOUTEN

Bit 15: Clock timeout enable.

Allowed values:
0: Disabled: SCL timeout detection is disabled
1: Enabled: SCL timeout detection is enabled

TIMEOUTB

Bits 16-27: Bus timeout B.

Allowed values: 0x0-0xfff

TEXTEN

Bit 31: Extended clock timeout enable.

Allowed values:
0: Disabled: Extended clock timeout detection is disabled
1: Enabled: Extended clock timeout detection is enabled

ISR

Interrupt and Status register

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r 		DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		ALERT
r 		TIMEOUT
r 		PECERR
r 		OVR
r 		ARLO
r 		BERR
r 		TCR
r 		TC
r 		STOPF
r 		NACKF
r 		ADDR
r 		RXNE
r 		TXIS
rw 		TXE
rw
Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters).

Allowed values:
0: NotEmpty: TXDR register not empty
1: Empty: TXDR register empty

TXIS

Bit 1: Transmit interrupt status (transmitters).

Allowed values:
0: NotEmpty: The TXDR register is not empty
1: Empty: The TXDR register is empty and the data to be transmitted must be written in the TXDR register

RXNE

Bit 2: Receive data register not empty (receivers).

Allowed values:
0: Empty: The RXDR register is empty
1: NotEmpty: Received data is copied into the RXDR register, and is ready to be read

ADDR

Bit 3: Address matched (slave mode).

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

NACKF

Bit 4: Not acknowledge received flag.

Allowed values:
0: NoNack: No NACK has been received
1: Nack: NACK has been received

STOPF

Bit 5: Stop detection flag.

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

TC

Bit 6: Transfer Complete (master mode).

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

TCR

Bit 7: Transfer Complete Reload.

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

BERR

Bit 8: Bus error.

Allowed values:
0: NoError: No bus error
1: Error: Misplaced Start and Stop condition is detected

ARLO

Bit 9: Arbitration lost.

Allowed values:
0: NotLost: No arbitration lost
1: Lost: Arbitration lost

OVR

Bit 10: Overrun/Underrun (slave mode).

Allowed values:
0: NoOverrun: No overrun/underrun error occurs
1: Overrun: slave mode with NOSTRETCH=1, when an overrun/underrun error occurs

PECERR

Bit 11: PEC Error in reception.

Allowed values:
0: Match: Received PEC does match with PEC register
1: NoMatch: Received PEC does not match with PEC register

TIMEOUT

Bit 12: Timeout or t_low detection flag.

Allowed values:
0: NoTimeout: No timeout occured
1: Timeout: Timeout occured

ALERT

Bit 13: SMBus alert.

Allowed values:
0: NoAlert: SMBA alert is not detected
1: Alert: SMBA alert event is detected on SMBA pin

BUSY

Bit 15: Bus busy.

Allowed values:
0: NotBusy: No communication is in progress on the bus
1: Busy: A communication is in progress on the bus

DIR

Bit 16: Transfer direction (Slave mode).

Allowed values:
0: Write: Write transfer, slave enters receiver mode
1: Read: Read transfer, slave enters transmitter mode

ADDCODE

Bits 17-23: Address match code (Slave mode).

Allowed values: 0x0-0x7f

ICR

Interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w 		TIMOUTCF
w 		PECCF
w 		OVRCF
w 		ARLOCF
w 		BERRCF
w 		STOPCF
w 		NACKCF
w 		ADDRCF
w
Toggle fields

ADDRCF

Bit 3: Address Matched flag clear.

Allowed values:
1: Clear: Clears the ADDR flag in ISR register

NACKCF

Bit 4: Not Acknowledge flag clear.

Allowed values:
1: Clear: Clears the NACK flag in ISR register

STOPCF

Bit 5: Stop detection flag clear.

Allowed values:
1: Clear: Clears the STOP flag in ISR register

BERRCF

Bit 8: Bus error flag clear.

Allowed values:
1: Clear: Clears the BERR flag in ISR register

ARLOCF

Bit 9: Arbitration lost flag clear.

Allowed values:
1: Clear: Clears the ARLO flag in ISR register

OVRCF

Bit 10: Overrun/Underrun flag clear.

Allowed values:
1: Clear: Clears the OVR flag in ISR register

PECCF

Bit 11: PEC Error flag clear.

Allowed values:
1: Clear: Clears the PEC flag in ISR register

TIMOUTCF

Bit 12: Timeout detection flag clear.

Allowed values:
1: Clear: Clears the TIMOUT flag in ISR register

ALERTCF

Bit 13: Alert flag clear.

Allowed values:
1: Clear: Clears the ALERT flag in ISR register

PECR

PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle fields

PEC

Bits 0-7: Packet error checking register.

Allowed values: 0x0-0xff

RXDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: 8-bit receive data.

Allowed values: 0x0-0xff

TXDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data.

Allowed values: 0x0-0xff

I2C2

0x40005800: Inter-integrated circuit

76/77 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 TIMINGR
0x14 TIMEOUTR
0x18 ISR
0x1c ICR
0x20 PECR
0x24 RXDR
0x28 TXDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

20/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw 		ALERTEN
rw 		SMBDEN
rw 		SMBHEN
rw 		GCEN
rw 		WUPEN
rw 		NOSTRETCH
rw 		SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw 		TXDMAEN
rw 		SWRST
w 		ANFOFF
rw 		DNF
rw 		ERRIE
rw 		TCIE
rw 		STOPIE
rw 		NACKIE
rw 		ADDRIE
rw 		RXIE
rw 		TXIE
rw 		PE
rw
Toggle fields

PE

Bit 0: Peripheral enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

TXIE

Bit 1: TX Interrupt enable.

Allowed values:
0: Disabled: Transmit (TXIS) interrupt disabled
1: Enabled: Transmit (TXIS) interrupt enabled

RXIE

Bit 2: RX Interrupt enable.

Allowed values:
0: Disabled: Receive (RXNE) interrupt disabled
1: Enabled: Receive (RXNE) interrupt enabled

ADDRIE

Bit 3: Address match interrupt enable (slave only).

Allowed values:
0: Disabled: Address match (ADDR) interrupts disabled
1: Enabled: Address match (ADDR) interrupts enabled

NACKIE

Bit 4: Not acknowledge received interrupt enable.

Allowed values:
0: Disabled: Not acknowledge (NACKF) received interrupts disabled
1: Enabled: Not acknowledge (NACKF) received interrupts enabled

STOPIE

Bit 5: STOP detection Interrupt enable.

Allowed values:
0: Disabled: Stop detection (STOPF) interrupt disabled
1: Enabled: Stop detection (STOPF) interrupt enabled

TCIE

Bit 6: Transfer Complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

ERRIE

Bit 7: Error interrupts enable.

Allowed values:
0: Disabled: Error detection interrupts disabled
1: Enabled: Error detection interrupts enabled

DNF

Bits 8-11: Digital noise filter.

Allowed values:
0: NoFilter: Digital filter disabled
1: Filter1: Digital filter enabled and filtering capability up to 1 tI2CCLK
2: Filter2: Digital filter enabled and filtering capability up to 2 tI2CCLK
3: Filter3: Digital filter enabled and filtering capability up to 3 tI2CCLK
4: Filter4: Digital filter enabled and filtering capability up to 4 tI2CCLK
5: Filter5: Digital filter enabled and filtering capability up to 5 tI2CCLK
6: Filter6: Digital filter enabled and filtering capability up to 6 tI2CCLK
7: Filter7: Digital filter enabled and filtering capability up to 7 tI2CCLK
8: Filter8: Digital filter enabled and filtering capability up to 8 tI2CCLK
9: Filter9: Digital filter enabled and filtering capability up to 9 tI2CCLK
10: Filter10: Digital filter enabled and filtering capability up to 10 tI2CCLK
11: Filter11: Digital filter enabled and filtering capability up to 11 tI2CCLK
12: Filter12: Digital filter enabled and filtering capability up to 12 tI2CCLK
13: Filter13: Digital filter enabled and filtering capability up to 13 tI2CCLK
14: Filter14: Digital filter enabled and filtering capability up to 14 tI2CCLK
15: Filter15: Digital filter enabled and filtering capability up to 15 tI2CCLK

ANFOFF

Bit 12: Analog noise filter OFF.

Allowed values:
0: Enabled: Analog noise filter enabled
1: Disabled: Analog noise filter disabled

SWRST

Bit 13: Software reset.

TXDMAEN

Bit 14: DMA transmission requests enable.

Allowed values:
0: Disabled: DMA mode disabled for transmission
1: Enabled: DMA mode enabled for transmission

RXDMAEN

Bit 15: DMA reception requests enable.

Allowed values:
0: Disabled: DMA mode disabled for reception
1: Enabled: DMA mode enabled for reception

SBC

Bit 16: Slave byte control.

Allowed values:
0: Disabled: Slave byte control disabled
1: Enabled: Slave byte control enabled

NOSTRETCH

Bit 17: Clock stretching disable.

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

WUPEN

Bit 18: Wakeup from STOP enable.

Allowed values:
0: Disabled: Wakeup from Stop mode disabled
1: Enabled: Wakeup from Stop mode enabled

GCEN

Bit 19: General call enable.

Allowed values:
0: Disabled: General call disabled. Address 0b00000000 is NACKed
1: Enabled: General call enabled. Address 0b00000000 is ACKed

SMBHEN

Bit 20: SMBus Host address enable.

Allowed values:
0: Disabled: Host address disabled. Address 0b0001000x is NACKed
1: Enabled: Host address enabled. Address 0b0001000x is ACKed

SMBDEN

Bit 21: SMBus Device Default address enable.

Allowed values:
0: Disabled: Device default address disabled. Address 0b1100001x is NACKed
1: Enabled: Device default address enabled. Address 0b1100001x is ACKed

ALERTEN

Bit 22: SMBUS alert enable.

Allowed values:
0: Disabled: In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
1: Enabled: In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported

PECEN

Bit 23: PEC enable.

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw 		AUTOEND
rw 		RELOAD
rw 		NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw 		STOP
rw 		START
rw 		HEAD10R
rw 		ADD10
rw 		RD_WRN
rw 		SADD
rw
Toggle fields

SADD

Bits 0-9: Slave address bit 9:8 (master mode).

Allowed values: 0x0-0x3ff

RD_WRN

Bit 10: Transfer direction (master mode).

Allowed values:
0: Write: Master requests a write transfer
1: Read: Master requests a read transfer

ADD10

Bit 11: 10-bit addressing mode (master mode).

Allowed values:
0: Bit7: The master operates in 7-bit addressing mode
1: Bit10: The master operates in 10-bit addressing mode

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

Allowed values:
0: Complete: The master sends the complete 10 bit slave address read sequence
1: Partial: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction

START

Bit 13: Start generation.

Allowed values:
0: NoStart: No Start generation
1: Start: Restart/Start generation

STOP

Bit 14: Stop generation (master mode).

Allowed values:
0: NoStop: No Stop generation
1: Stop: Stop generation after current byte transfer

NACK

Bit 15: NACK generation (slave mode).

Allowed values:
0: Ack: an ACK is sent after current received byte
1: Nack: a NACK is sent after current received byte

NBYTES

Bits 16-23: Number of bytes.

Allowed values: 0x0-0xff

RELOAD

Bit 24: NBYTES reload mode.

Allowed values:
0: Completed: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)
1: NotCompleted: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)

AUTOEND

Bit 25: Automatic end mode (master mode).

Allowed values:
0: Software: Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low
1: Automatic: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred

PECBYTE

Bit 26: Packet error checking byte.

Allowed values:
0: NoPec: No PEC transfer
1: Pec: PEC transmission/reception is requested

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw 		OA1MODE
rw 		OA1
rw
Toggle fields

OA1

Bits 0-9: Interface address.

Allowed values: 0x0-0x3ff

OA1MODE

Bit 10: Own Address 1 10-bit mode.

Allowed values:
0: Bit7: Own address 1 is a 7-bit address
1: Bit10: Own address 1 is a 10-bit address

OA1EN

Bit 15: Own Address 1 enable.

Allowed values:
0: Disabled: Own address 1 disabled. The received slave address OA1 is NACKed
1: Enabled: Own address 1 enabled. The received slave address OA1 is ACKed

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw 		OA2MSK
rw 		OA2
rw
Toggle fields

OA2

Bits 1-7: Interface address.

Allowed values: 0x0-0x7f

OA2MSK

Bits 8-10: Own Address 2 masks.

Allowed values:
0: NoMask: No mask
1: Mask1: OA2[1] is masked and don’t care. Only OA2[7:2] are compared
2: Mask2: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
3: Mask3: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
4: Mask4: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
5: Mask5: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
6: Mask6: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
7: Mask7: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged

OA2EN

Bit 15: Own Address 2 enable.

Allowed values:
0: Disabled: Own address 2 disabled. The received slave address OA2 is NACKed
1: Enabled: Own address 2 enabled. The received slave address OA2 is ACKed

TIMINGR

Timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw 		SCLDEL
rw 		SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw 		SCLL
rw
Toggle fields

SCLL

Bits 0-7: SCL low period (master mode).

Allowed values: 0x0-0xff

SCLH

Bits 8-15: SCL high period (master mode).

Allowed values: 0x0-0xff

SDADEL

Bits 16-19: Data hold time.

Allowed values: 0x0-0xf

SCLDEL

Bits 20-23: Data setup time.

Allowed values: 0x0-0xf

PRESC

Bits 28-31: Timing prescaler.

Allowed values: 0x0-0xf

TIMEOUTR

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw 		TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw 		TIDLE
rw 		TIMEOUTA
rw
Toggle fields

TIMEOUTA

Bits 0-11: Bus timeout A.

Allowed values: 0x0-0xfff

TIDLE

Bit 12: Idle clock timeout detection.

Allowed values:
0: Disabled: TIMEOUTA is used to detect SCL low timeout
1: Enabled: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)

TIMOUTEN

Bit 15: Clock timeout enable.

Allowed values:
0: Disabled: SCL timeout detection is disabled
1: Enabled: SCL timeout detection is enabled

TIMEOUTB

Bits 16-27: Bus timeout B.

Allowed values: 0x0-0xfff

TEXTEN

Bit 31: Extended clock timeout enable.

Allowed values:
0: Disabled: Extended clock timeout detection is disabled
1: Enabled: Extended clock timeout detection is enabled

ISR

Interrupt and Status register

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r 		DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		ALERT
r 		TIMEOUT
r 		PECERR
r 		OVR
r 		ARLO
r 		BERR
r 		TCR
r 		TC
r 		STOPF
r 		NACKF
r 		ADDR
r 		RXNE
r 		TXIS
rw 		TXE
rw
Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters).

Allowed values:
0: NotEmpty: TXDR register not empty
1: Empty: TXDR register empty

TXIS

Bit 1: Transmit interrupt status (transmitters).

Allowed values:
0: NotEmpty: The TXDR register is not empty
1: Empty: The TXDR register is empty and the data to be transmitted must be written in the TXDR register

RXNE

Bit 2: Receive data register not empty (receivers).

Allowed values:
0: Empty: The RXDR register is empty
1: NotEmpty: Received data is copied into the RXDR register, and is ready to be read

ADDR

Bit 3: Address matched (slave mode).

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

NACKF

Bit 4: Not acknowledge received flag.

Allowed values:
0: NoNack: No NACK has been received
1: Nack: NACK has been received

STOPF

Bit 5: Stop detection flag.

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

TC

Bit 6: Transfer Complete (master mode).

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

TCR

Bit 7: Transfer Complete Reload.

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

BERR

Bit 8: Bus error.

Allowed values:
0: NoError: No bus error
1: Error: Misplaced Start and Stop condition is detected

ARLO

Bit 9: Arbitration lost.

Allowed values:
0: NotLost: No arbitration lost
1: Lost: Arbitration lost

OVR

Bit 10: Overrun/Underrun (slave mode).

Allowed values:
0: NoOverrun: No overrun/underrun error occurs
1: Overrun: slave mode with NOSTRETCH=1, when an overrun/underrun error occurs

PECERR

Bit 11: PEC Error in reception.

Allowed values:
0: Match: Received PEC does match with PEC register
1: NoMatch: Received PEC does not match with PEC register

TIMEOUT

Bit 12: Timeout or t_low detection flag.

Allowed values:
0: NoTimeout: No timeout occured
1: Timeout: Timeout occured

ALERT

Bit 13: SMBus alert.

Allowed values:
0: NoAlert: SMBA alert is not detected
1: Alert: SMBA alert event is detected on SMBA pin

BUSY

Bit 15: Bus busy.

Allowed values:
0: NotBusy: No communication is in progress on the bus
1: Busy: A communication is in progress on the bus

DIR

Bit 16: Transfer direction (Slave mode).

Allowed values:
0: Write: Write transfer, slave enters receiver mode
1: Read: Read transfer, slave enters transmitter mode

ADDCODE

Bits 17-23: Address match code (Slave mode).

Allowed values: 0x0-0x7f

ICR

Interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w 		TIMOUTCF
w 		PECCF
w 		OVRCF
w 		ARLOCF
w 		BERRCF
w 		STOPCF
w 		NACKCF
w 		ADDRCF
w
Toggle fields

ADDRCF

Bit 3: Address Matched flag clear.

Allowed values:
1: Clear: Clears the ADDR flag in ISR register

NACKCF

Bit 4: Not Acknowledge flag clear.

Allowed values:
1: Clear: Clears the NACK flag in ISR register

STOPCF

Bit 5: Stop detection flag clear.

Allowed values:
1: Clear: Clears the STOP flag in ISR register

BERRCF

Bit 8: Bus error flag clear.

Allowed values:
1: Clear: Clears the BERR flag in ISR register

ARLOCF

Bit 9: Arbitration lost flag clear.

Allowed values:
1: Clear: Clears the ARLO flag in ISR register

OVRCF

Bit 10: Overrun/Underrun flag clear.

Allowed values:
1: Clear: Clears the OVR flag in ISR register

PECCF

Bit 11: PEC Error flag clear.

Allowed values:
1: Clear: Clears the PEC flag in ISR register

TIMOUTCF

Bit 12: Timeout detection flag clear.

Allowed values:
1: Clear: Clears the TIMOUT flag in ISR register

ALERTCF

Bit 13: Alert flag clear.

Allowed values:
1: Clear: Clears the ALERT flag in ISR register

PECR

PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle fields

PEC

Bits 0-7: Packet error checking register.

Allowed values: 0x0-0xff

RXDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: 8-bit receive data.

Allowed values: 0x0-0xff

TXDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data.

Allowed values: 0x0-0xff

I2C3

0x40007800: Inter-integrated circuit

76/77 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 TIMINGR
0x14 TIMEOUTR
0x18 ISR
0x1c ICR
0x20 PECR
0x24 RXDR
0x28 TXDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

20/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw 		ALERTEN
rw 		SMBDEN
rw 		SMBHEN
rw 		GCEN
rw 		WUPEN
rw 		NOSTRETCH
rw 		SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw 		TXDMAEN
rw 		SWRST
w 		ANFOFF
rw 		DNF
rw 		ERRIE
rw 		TCIE
rw 		STOPIE
rw 		NACKIE
rw 		ADDRIE
rw 		RXIE
rw 		TXIE
rw 		PE
rw
Toggle fields

PE

Bit 0: Peripheral enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

TXIE

Bit 1: TX Interrupt enable.

Allowed values:
0: Disabled: Transmit (TXIS) interrupt disabled
1: Enabled: Transmit (TXIS) interrupt enabled

RXIE

Bit 2: RX Interrupt enable.

Allowed values:
0: Disabled: Receive (RXNE) interrupt disabled
1: Enabled: Receive (RXNE) interrupt enabled

ADDRIE

Bit 3: Address match interrupt enable (slave only).

Allowed values:
0: Disabled: Address match (ADDR) interrupts disabled
1: Enabled: Address match (ADDR) interrupts enabled

NACKIE

Bit 4: Not acknowledge received interrupt enable.

Allowed values:
0: Disabled: Not acknowledge (NACKF) received interrupts disabled
1: Enabled: Not acknowledge (NACKF) received interrupts enabled

STOPIE

Bit 5: STOP detection Interrupt enable.

Allowed values:
0: Disabled: Stop detection (STOPF) interrupt disabled
1: Enabled: Stop detection (STOPF) interrupt enabled

TCIE

Bit 6: Transfer Complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

ERRIE

Bit 7: Error interrupts enable.

Allowed values:
0: Disabled: Error detection interrupts disabled
1: Enabled: Error detection interrupts enabled

DNF

Bits 8-11: Digital noise filter.

Allowed values:
0: NoFilter: Digital filter disabled
1: Filter1: Digital filter enabled and filtering capability up to 1 tI2CCLK
2: Filter2: Digital filter enabled and filtering capability up to 2 tI2CCLK
3: Filter3: Digital filter enabled and filtering capability up to 3 tI2CCLK
4: Filter4: Digital filter enabled and filtering capability up to 4 tI2CCLK
5: Filter5: Digital filter enabled and filtering capability up to 5 tI2CCLK
6: Filter6: Digital filter enabled and filtering capability up to 6 tI2CCLK
7: Filter7: Digital filter enabled and filtering capability up to 7 tI2CCLK
8: Filter8: Digital filter enabled and filtering capability up to 8 tI2CCLK
9: Filter9: Digital filter enabled and filtering capability up to 9 tI2CCLK
10: Filter10: Digital filter enabled and filtering capability up to 10 tI2CCLK
11: Filter11: Digital filter enabled and filtering capability up to 11 tI2CCLK
12: Filter12: Digital filter enabled and filtering capability up to 12 tI2CCLK
13: Filter13: Digital filter enabled and filtering capability up to 13 tI2CCLK
14: Filter14: Digital filter enabled and filtering capability up to 14 tI2CCLK
15: Filter15: Digital filter enabled and filtering capability up to 15 tI2CCLK

ANFOFF

Bit 12: Analog noise filter OFF.

Allowed values:
0: Enabled: Analog noise filter enabled
1: Disabled: Analog noise filter disabled

SWRST

Bit 13: Software reset.

TXDMAEN

Bit 14: DMA transmission requests enable.

Allowed values:
0: Disabled: DMA mode disabled for transmission
1: Enabled: DMA mode enabled for transmission

RXDMAEN

Bit 15: DMA reception requests enable.

Allowed values:
0: Disabled: DMA mode disabled for reception
1: Enabled: DMA mode enabled for reception

SBC

Bit 16: Slave byte control.

Allowed values:
0: Disabled: Slave byte control disabled
1: Enabled: Slave byte control enabled

NOSTRETCH

Bit 17: Clock stretching disable.

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

WUPEN

Bit 18: Wakeup from STOP enable.

Allowed values:
0: Disabled: Wakeup from Stop mode disabled
1: Enabled: Wakeup from Stop mode enabled

GCEN

Bit 19: General call enable.

Allowed values:
0: Disabled: General call disabled. Address 0b00000000 is NACKed
1: Enabled: General call enabled. Address 0b00000000 is ACKed

SMBHEN

Bit 20: SMBus Host address enable.

Allowed values:
0: Disabled: Host address disabled. Address 0b0001000x is NACKed
1: Enabled: Host address enabled. Address 0b0001000x is ACKed

SMBDEN

Bit 21: SMBus Device Default address enable.

Allowed values:
0: Disabled: Device default address disabled. Address 0b1100001x is NACKed
1: Enabled: Device default address enabled. Address 0b1100001x is ACKed

ALERTEN

Bit 22: SMBUS alert enable.

Allowed values:
0: Disabled: In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
1: Enabled: In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported

PECEN

Bit 23: PEC enable.

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw 		AUTOEND
rw 		RELOAD
rw 		NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw 		STOP
rw 		START
rw 		HEAD10R
rw 		ADD10
rw 		RD_WRN
rw 		SADD
rw
Toggle fields

SADD

Bits 0-9: Slave address bit 9:8 (master mode).

Allowed values: 0x0-0x3ff

RD_WRN

Bit 10: Transfer direction (master mode).

Allowed values:
0: Write: Master requests a write transfer
1: Read: Master requests a read transfer

ADD10

Bit 11: 10-bit addressing mode (master mode).

Allowed values:
0: Bit7: The master operates in 7-bit addressing mode
1: Bit10: The master operates in 10-bit addressing mode

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

Allowed values:
0: Complete: The master sends the complete 10 bit slave address read sequence
1: Partial: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction

START

Bit 13: Start generation.

Allowed values:
0: NoStart: No Start generation
1: Start: Restart/Start generation

STOP

Bit 14: Stop generation (master mode).

Allowed values:
0: NoStop: No Stop generation
1: Stop: Stop generation after current byte transfer

NACK

Bit 15: NACK generation (slave mode).

Allowed values:
0: Ack: an ACK is sent after current received byte
1: Nack: a NACK is sent after current received byte

NBYTES

Bits 16-23: Number of bytes.

Allowed values: 0x0-0xff

RELOAD

Bit 24: NBYTES reload mode.

Allowed values:
0: Completed: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)
1: NotCompleted: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)

AUTOEND

Bit 25: Automatic end mode (master mode).

Allowed values:
0: Software: Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low
1: Automatic: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred

PECBYTE

Bit 26: Packet error checking byte.

Allowed values:
0: NoPec: No PEC transfer
1: Pec: PEC transmission/reception is requested

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw 		OA1MODE
rw 		OA1
rw
Toggle fields

OA1

Bits 0-9: Interface address.

Allowed values: 0x0-0x3ff

OA1MODE

Bit 10: Own Address 1 10-bit mode.

Allowed values:
0: Bit7: Own address 1 is a 7-bit address
1: Bit10: Own address 1 is a 10-bit address

OA1EN

Bit 15: Own Address 1 enable.

Allowed values:
0: Disabled: Own address 1 disabled. The received slave address OA1 is NACKed
1: Enabled: Own address 1 enabled. The received slave address OA1 is ACKed

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw 		OA2MSK
rw 		OA2
rw
Toggle fields

OA2

Bits 1-7: Interface address.

Allowed values: 0x0-0x7f

OA2MSK

Bits 8-10: Own Address 2 masks.

Allowed values:
0: NoMask: No mask
1: Mask1: OA2[1] is masked and don’t care. Only OA2[7:2] are compared
2: Mask2: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
3: Mask3: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
4: Mask4: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
5: Mask5: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
6: Mask6: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
7: Mask7: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged

OA2EN

Bit 15: Own Address 2 enable.

Allowed values:
0: Disabled: Own address 2 disabled. The received slave address OA2 is NACKed
1: Enabled: Own address 2 enabled. The received slave address OA2 is ACKed

TIMINGR

Timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw 		SCLDEL
rw 		SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw 		SCLL
rw
Toggle fields

SCLL

Bits 0-7: SCL low period (master mode).

Allowed values: 0x0-0xff

SCLH

Bits 8-15: SCL high period (master mode).

Allowed values: 0x0-0xff

SDADEL

Bits 16-19: Data hold time.

Allowed values: 0x0-0xf

SCLDEL

Bits 20-23: Data setup time.

Allowed values: 0x0-0xf

PRESC

Bits 28-31: Timing prescaler.

Allowed values: 0x0-0xf

TIMEOUTR

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw 		TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw 		TIDLE
rw 		TIMEOUTA
rw
Toggle fields

TIMEOUTA

Bits 0-11: Bus timeout A.

Allowed values: 0x0-0xfff

TIDLE

Bit 12: Idle clock timeout detection.

Allowed values:
0: Disabled: TIMEOUTA is used to detect SCL low timeout
1: Enabled: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)

TIMOUTEN

Bit 15: Clock timeout enable.

Allowed values:
0: Disabled: SCL timeout detection is disabled
1: Enabled: SCL timeout detection is enabled

TIMEOUTB

Bits 16-27: Bus timeout B.

Allowed values: 0x0-0xfff

TEXTEN

Bit 31: Extended clock timeout enable.

Allowed values:
0: Disabled: Extended clock timeout detection is disabled
1: Enabled: Extended clock timeout detection is enabled

ISR

Interrupt and Status register

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r 		DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		ALERT
r 		TIMEOUT
r 		PECERR
r 		OVR
r 		ARLO
r 		BERR
r 		TCR
r 		TC
r 		STOPF
r 		NACKF
r 		ADDR
r 		RXNE
r 		TXIS
rw 		TXE
rw
Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters).

Allowed values:
0: NotEmpty: TXDR register not empty
1: Empty: TXDR register empty

TXIS

Bit 1: Transmit interrupt status (transmitters).

Allowed values:
0: NotEmpty: The TXDR register is not empty
1: Empty: The TXDR register is empty and the data to be transmitted must be written in the TXDR register

RXNE

Bit 2: Receive data register not empty (receivers).

Allowed values:
0: Empty: The RXDR register is empty
1: NotEmpty: Received data is copied into the RXDR register, and is ready to be read

ADDR

Bit 3: Address matched (slave mode).

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

NACKF

Bit 4: Not acknowledge received flag.

Allowed values:
0: NoNack: No NACK has been received
1: Nack: NACK has been received

STOPF

Bit 5: Stop detection flag.

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

TC

Bit 6: Transfer Complete (master mode).

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

TCR

Bit 7: Transfer Complete Reload.

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

BERR

Bit 8: Bus error.

Allowed values:
0: NoError: No bus error
1: Error: Misplaced Start and Stop condition is detected

ARLO

Bit 9: Arbitration lost.

Allowed values:
0: NotLost: No arbitration lost
1: Lost: Arbitration lost

OVR

Bit 10: Overrun/Underrun (slave mode).

Allowed values:
0: NoOverrun: No overrun/underrun error occurs
1: Overrun: slave mode with NOSTRETCH=1, when an overrun/underrun error occurs

PECERR

Bit 11: PEC Error in reception.

Allowed values:
0: Match: Received PEC does match with PEC register
1: NoMatch: Received PEC does not match with PEC register

TIMEOUT

Bit 12: Timeout or t_low detection flag.

Allowed values:
0: NoTimeout: No timeout occured
1: Timeout: Timeout occured

ALERT

Bit 13: SMBus alert.

Allowed values:
0: NoAlert: SMBA alert is not detected
1: Alert: SMBA alert event is detected on SMBA pin

BUSY

Bit 15: Bus busy.

Allowed values:
0: NotBusy: No communication is in progress on the bus
1: Busy: A communication is in progress on the bus

DIR

Bit 16: Transfer direction (Slave mode).

Allowed values:
0: Write: Write transfer, slave enters receiver mode
1: Read: Read transfer, slave enters transmitter mode

ADDCODE

Bits 17-23: Address match code (Slave mode).

Allowed values: 0x0-0x7f

ICR

Interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w 		TIMOUTCF
w 		PECCF
w 		OVRCF
w 		ARLOCF
w 		BERRCF
w 		STOPCF
w 		NACKCF
w 		ADDRCF
w
Toggle fields

ADDRCF

Bit 3: Address Matched flag clear.

Allowed values:
1: Clear: Clears the ADDR flag in ISR register

NACKCF

Bit 4: Not Acknowledge flag clear.

Allowed values:
1: Clear: Clears the NACK flag in ISR register

STOPCF

Bit 5: Stop detection flag clear.

Allowed values:
1: Clear: Clears the STOP flag in ISR register

BERRCF

Bit 8: Bus error flag clear.

Allowed values:
1: Clear: Clears the BERR flag in ISR register

ARLOCF

Bit 9: Arbitration lost flag clear.

Allowed values:
1: Clear: Clears the ARLO flag in ISR register

OVRCF

Bit 10: Overrun/Underrun flag clear.

Allowed values:
1: Clear: Clears the OVR flag in ISR register

PECCF

Bit 11: PEC Error flag clear.

Allowed values:
1: Clear: Clears the PEC flag in ISR register

TIMOUTCF

Bit 12: Timeout detection flag clear.

Allowed values:
1: Clear: Clears the TIMOUT flag in ISR register

ALERTCF

Bit 13: Alert flag clear.

Allowed values:
1: Clear: Clears the ALERT flag in ISR register

PECR

PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle fields

PEC

Bits 0-7: Packet error checking register.

Allowed values: 0x0-0xff

RXDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: 8-bit receive data.

Allowed values: 0x0-0xff

TXDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data.

Allowed values: 0x0-0xff

I2S2ext

0x40003400: Serial peripheral interface/Inter-IC2

53/53 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) CR1
0x4 (16-bit) CR2
0x8 (16-bit) SR
0xc (16-bit) DR
0xc (8-bit) DR8
0x10 (16-bit) CRCPR
0x14 (16-bit) RXCRCR
0x18 (16-bit) TXCRCR
0x1c (16-bit) I2SCFGR
0x20 (16-bit) I2SPR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

14/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw 		BIDIOE
rw 		CRCEN
rw 		CRCNEXT
rw 		CRCL
rw 		RXONLY
rw 		SSM
rw 		SSI
rw 		LSBFIRST
rw 		SPE
rw 		BR
rw 		MSTR
rw 		CPOL
rw 		CPHA
rw
Toggle fields

CPHA

Bit 0: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 1: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

MSTR

Bit 2: Master selection.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

BR

Bits 3-5: Baud rate control.

Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256

SPE

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LSBFIRST

Bit 7: Frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SSI

Bit 8: Internal slave select.

Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored

SSM

Bit 9: Software slave management.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

RXONLY

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)

CRCL

Bit 11: CRC length.

Allowed values:
0: EightBit: 8-bit CRC length
1: SixteenBit: 16-bit CRC length

CRCNEXT

Bit 12: CRC transfer next.

Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register

CRCEN

Bit 13: Hardware CRC calculation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BIDIOE

Bit 14: Output enable in bidirectional mode.

Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)

BIDIMODE

Bit 15: Bidirectional data mode enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CR2

control register 2

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDMA_TX
rw 		LDMA_RX
rw 		FRXTH
rw 		DS
rw 		TXEIE
rw 		RXNEIE
rw 		ERRIE
rw 		FRF
rw 		NSSP
rw 		SSOE
rw 		TXDMAEN
rw 		RXDMAEN
rw
Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 1: Tx buffer DMA enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

SSOE

Bit 2: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

NSSP

Bit 3: NSS pulse management.

Allowed values:
0: NoPulse: No NSS pulse
1: PulseGenerated: NSS pulse generated

FRF

Bit 4: Frame format.

Allowed values:
0: Motorola: SPI Motorola mode
1: TI: SPI TI mode

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked

TXEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked

DS

Bits 8-11: Data size.

Allowed values:
3: FourBit: 4-bit
4: FiveBit: 5-bit
5: SixBit: 6-bit
6: SevenBit: 7-bit
7: EightBit: 8-bit
8: NineBit: 9-bit
9: TenBit: 10-bit
10: ElevenBit: 11-bit
11: TwelveBit: 12-bit
12: ThirteenBit: 13-bit
13: FourteenBit: 14-bit
14: FifteenBit: 15-bit
15: SixteenBit: 16-bit

FRXTH

Bit 12: FIFO reception threshold.

Allowed values:
0: Half: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)
1: Quarter: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)

LDMA_RX

Bit 13: Last DMA transfer for reception.

Allowed values:
0: Even: Number of data to transfer for receive is even
1: Odd: Number of data to transfer for receive is odd

LDMA_TX

Bit 14: Last DMA transfer for transmission.

Allowed values:
0: Even: Number of data to transfer for transmit is even
1: Odd: Number of data to transfer for transmit is odd

SR

status register

Offset: 0x8, size: 16, reset: 0x00000002, access: Unspecified

11/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTLVL
r 		FRLVL
r 		FRE
r 		BSY
r 		OVR
r 		MODF
r 		CRCERR
rw 		UDR
r 		CHSIDE
r 		TXE
r 		RXNE
r
Toggle fields

RXNE

Bit 0: Receive buffer not empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXE

Bit 1: Transmit buffer empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

CHSIDE

Bit 2: Channel side.

Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received

UDR

Bit 3: Underrun flag.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

CRCERR

Bit 4: CRC error flag.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

MODF

Bit 5: Mode fault.

Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred

OVR

Bit 6: Overrun flag.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

BSY

Bit 7: Busy flag.

Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy

FRE

Bit 8: Frame format error.

Allowed values:
0: NoError: No frame format error
1: Error: A frame format error occurred

FRLVL

Bits 9-10: FIFO reception level.

Allowed values:
0: Empty: Rx FIFO Empty
1: Quarter: Rx 1/4 FIFO
2: Half: Rx 1/2 FIFO
3: Full: Rx FIFO full

FTLVL

Bits 11-12: FIFO transmission level.

Allowed values:
0: Empty: Tx FIFO Empty
1: Quarter: Tx 1/4 FIFO
2: Half: Tx 1/2 FIFO
3: Full: Tx FIFO full

DR

data register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-15: Data register.

Allowed values: 0x0-0xffff

DR8

Direct 8-bit access to data register

Offset: 0xc, size: 8, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-7: Data register.

Allowed values: 0x0-0xff

CRCPR

CRC polynomial register

Offset: 0x10, size: 16, reset: 0x00000007, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0x0-0xffff

RXCRCR

RX CRC register

Offset: 0x14, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

Allowed values: 0x0-0xffff

TXCRCR

TX CRC register

Offset: 0x18, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

Allowed values: 0x0-0xffff

I2SCFGR

I2S configuration register

Offset: 0x1c, size: 16, reset: 0x00000000, access: read-write

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SMOD
rw 		I2SE
rw 		I2SCFG
rw 		PCMSYNC
rw 		I2SSTD
rw 		CKPOL
rw 		DATLEN
rw 		CHLEN
rw
Toggle fields

CHLEN

Bit 0: Channel length (number of bits per audio channel).

Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide

DATLEN

Bits 1-2: Data length to be transferred.

Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length

CKPOL

Bit 3: Steady state clock polarity.

Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level

I2SSTD

Bits 4-5: I2S standard selection.

Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard

PCMSYNC

Bit 7: PCM frame synchronization.

Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation

I2SCFG

Bits 8-9: I2S configuration mode.

Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive

I2SE

Bit 10: I2S Enable.

Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled

I2SMOD

Bit 11: I2S mode selection.

Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected

I2SPR

I2S prescaler register

Offset: 0x20, size: 16, reset: 0x00000010, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOE
rw 		ODD
rw 		I2SDIV
rw
Toggle fields

I2SDIV

Bits 0-7: I2S Linear prescaler.

Allowed values: 0x2-0xff

ODD

Bit 8: Odd factor for the prescaler.

Allowed values:
0: Even: Real divider value is I2SDIV * 2
1: Odd: Real divider value is (I2SDIV * 2) + 1

MCKOE

Bit 9: Master clock output enable.

Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled

I2S3ext

0x40004000: Serial peripheral interface/Inter-IC2

53/53 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) CR1
0x4 (16-bit) CR2
0x8 (16-bit) SR
0xc (16-bit) DR
0xc (8-bit) DR8
0x10 (16-bit) CRCPR
0x14 (16-bit) RXCRCR
0x18 (16-bit) TXCRCR
0x1c (16-bit) I2SCFGR
0x20 (16-bit) I2SPR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

14/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw 		BIDIOE
rw 		CRCEN
rw 		CRCNEXT
rw 		CRCL
rw 		RXONLY
rw 		SSM
rw 		SSI
rw 		LSBFIRST
rw 		SPE
rw 		BR
rw 		MSTR
rw 		CPOL
rw 		CPHA
rw
Toggle fields

CPHA

Bit 0: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 1: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

MSTR

Bit 2: Master selection.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

BR

Bits 3-5: Baud rate control.

Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256

SPE

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LSBFIRST

Bit 7: Frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SSI

Bit 8: Internal slave select.

Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored

SSM

Bit 9: Software slave management.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

RXONLY

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)

CRCL

Bit 11: CRC length.

Allowed values:
0: EightBit: 8-bit CRC length
1: SixteenBit: 16-bit CRC length

CRCNEXT

Bit 12: CRC transfer next.

Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register

CRCEN

Bit 13: Hardware CRC calculation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BIDIOE

Bit 14: Output enable in bidirectional mode.

Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)

BIDIMODE

Bit 15: Bidirectional data mode enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CR2

control register 2

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDMA_TX
rw 		LDMA_RX
rw 		FRXTH
rw 		DS
rw 		TXEIE
rw 		RXNEIE
rw 		ERRIE
rw 		FRF
rw 		NSSP
rw 		SSOE
rw 		TXDMAEN
rw 		RXDMAEN
rw
Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 1: Tx buffer DMA enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

SSOE

Bit 2: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

NSSP

Bit 3: NSS pulse management.

Allowed values:
0: NoPulse: No NSS pulse
1: PulseGenerated: NSS pulse generated

FRF

Bit 4: Frame format.

Allowed values:
0: Motorola: SPI Motorola mode
1: TI: SPI TI mode

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked

TXEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked

DS

Bits 8-11: Data size.

Allowed values:
3: FourBit: 4-bit
4: FiveBit: 5-bit
5: SixBit: 6-bit
6: SevenBit: 7-bit
7: EightBit: 8-bit
8: NineBit: 9-bit
9: TenBit: 10-bit
10: ElevenBit: 11-bit
11: TwelveBit: 12-bit
12: ThirteenBit: 13-bit
13: FourteenBit: 14-bit
14: FifteenBit: 15-bit
15: SixteenBit: 16-bit

FRXTH

Bit 12: FIFO reception threshold.

Allowed values:
0: Half: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)
1: Quarter: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)

LDMA_RX

Bit 13: Last DMA transfer for reception.

Allowed values:
0: Even: Number of data to transfer for receive is even
1: Odd: Number of data to transfer for receive is odd

LDMA_TX

Bit 14: Last DMA transfer for transmission.

Allowed values:
0: Even: Number of data to transfer for transmit is even
1: Odd: Number of data to transfer for transmit is odd

SR

status register

Offset: 0x8, size: 16, reset: 0x00000002, access: Unspecified

11/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTLVL
r 		FRLVL
r 		FRE
r 		BSY
r 		OVR
r 		MODF
r 		CRCERR
rw 		UDR
r 		CHSIDE
r 		TXE
r 		RXNE
r
Toggle fields

RXNE

Bit 0: Receive buffer not empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXE

Bit 1: Transmit buffer empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

CHSIDE

Bit 2: Channel side.

Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received

UDR

Bit 3: Underrun flag.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

CRCERR

Bit 4: CRC error flag.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

MODF

Bit 5: Mode fault.

Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred

OVR

Bit 6: Overrun flag.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

BSY

Bit 7: Busy flag.

Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy

FRE

Bit 8: Frame format error.

Allowed values:
0: NoError: No frame format error
1: Error: A frame format error occurred

FRLVL

Bits 9-10: FIFO reception level.

Allowed values:
0: Empty: Rx FIFO Empty
1: Quarter: Rx 1/4 FIFO
2: Half: Rx 1/2 FIFO
3: Full: Rx FIFO full

FTLVL

Bits 11-12: FIFO transmission level.

Allowed values:
0: Empty: Tx FIFO Empty
1: Quarter: Tx 1/4 FIFO
2: Half: Tx 1/2 FIFO
3: Full: Tx FIFO full

DR

data register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-15: Data register.

Allowed values: 0x0-0xffff

DR8

Direct 8-bit access to data register

Offset: 0xc, size: 8, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-7: Data register.

Allowed values: 0x0-0xff

CRCPR

CRC polynomial register

Offset: 0x10, size: 16, reset: 0x00000007, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0x0-0xffff

RXCRCR

RX CRC register

Offset: 0x14, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

Allowed values: 0x0-0xffff

TXCRCR

TX CRC register

Offset: 0x18, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

Allowed values: 0x0-0xffff

I2SCFGR

I2S configuration register

Offset: 0x1c, size: 16, reset: 0x00000000, access: read-write

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SMOD
rw 		I2SE
rw 		I2SCFG
rw 		PCMSYNC
rw 		I2SSTD
rw 		CKPOL
rw 		DATLEN
rw 		CHLEN
rw
Toggle fields

CHLEN

Bit 0: Channel length (number of bits per audio channel).

Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide

DATLEN

Bits 1-2: Data length to be transferred.

Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length

CKPOL

Bit 3: Steady state clock polarity.

Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level

I2SSTD

Bits 4-5: I2S standard selection.

Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard

PCMSYNC

Bit 7: PCM frame synchronization.

Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation

I2SCFG

Bits 8-9: I2S configuration mode.

Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive

I2SE

Bit 10: I2S Enable.

Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled

I2SMOD

Bit 11: I2S mode selection.

Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected

I2SPR

I2S prescaler register

Offset: 0x20, size: 16, reset: 0x00000010, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOE
rw 		ODD
rw 		I2SDIV
rw
Toggle fields

I2SDIV

Bits 0-7: I2S Linear prescaler.

Allowed values: 0x2-0xff

ODD

Bit 8: Odd factor for the prescaler.

Allowed values:
0: Even: Real divider value is I2SDIV * 2
1: Odd: Real divider value is (I2SDIV * 2) + 1

MCKOE

Bit 9: Master clock output enable.

Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled

IWDG

0x40003000: Independent watchdog

7/7 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 KR
0x4 PR
0x8 RLR
0xc SR
0x10 WINR
Toggle registers

KR

Key register

Offset: 0x0, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-15: Key value.

Allowed values:
21845: Unlock: Enable access to PR, RLR and WINR registers
43690: Feed: Feed watchdog with RLR register value
52428: Start: Start the watchdog

PR

Prescaler register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PR
rw
Toggle fields

PR

Bits 0-2: Prescaler divider.

Allowed values:
0: DivideBy4: Divider /4
1: DivideBy8: Divider /8
2: DivideBy16: Divider /16
3: DivideBy32: Divider /32
4: DivideBy64: Divider /64
5: DivideBy128: Divider /128
6: DivideBy256: Divider /256

RLR

Reload register

Offset: 0x8, size: 32, reset: 0x00000FFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RL
rw
Toggle fields

RL

Bits 0-11: Watchdog counter reload value.

Allowed values: 0x0-0xfff

SR

Status register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WVU
r 		RVU
r 		PVU
r
Toggle fields

PVU

Bit 0: Watchdog prescaler value update.

RVU

Bit 1: Watchdog counter reload value update.

WVU

Bit 2: Watchdog counter window value update.

WINR

Window register

Offset: 0x10, size: 32, reset: 0x00000FFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WIN
rw
Toggle fields

WIN

Bits 0-11: Watchdog counter window value.

Allowed values: 0x0-0xfff

MPU

0xe000ed90: Memory protection unit

6/19 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 TYPER
0x4 CTRL
0x8 RNR
0xc RBAR
0x10 RASR
Toggle registers

TYPER

MPU type register

Offset: 0x0, size: 32, reset: 0x00000800, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IREGION
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DREGION
r 		SEPARATE
r
Toggle fields

SEPARATE

Bit 0: Separate flag.

DREGION

Bits 8-15: Number of MPU data regions.

IREGION

Bits 16-23: Number of MPU instruction regions.

CTRL

MPU control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIVDEFENA
r 		HFNMIENA
r 		ENABLE
r
Toggle fields

ENABLE

Bit 0: Enables the MPU.

HFNMIENA

Bit 1: Enables the operation of MPU during hard fault.

PRIVDEFENA

Bit 2: Enable priviliged software access to default memory map.

RNR

MPU region number register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGION
rw
Toggle fields

REGION

Bits 0-7: MPU region.

RBAR

MPU region base address register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
rw 		VALID
rw 		REGION
rw
Toggle fields

REGION

Bits 0-3: MPU region field.

VALID

Bit 4: MPU region number valid.

ADDR

Bits 5-31: Region base address field.

RASR

MPU region attribute and size register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
XN
rw 		AP
rw 		TEX
rw 		S
rw 		C
rw 		B
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRD
rw 		SIZE
rw 		ENABLE
rw
Toggle fields

ENABLE

Bit 0: Region enable bit..

SIZE

Bits 1-5: Size of the MPU protection region.

SRD

Bits 8-15: Subregion disable bits.

B

Bit 16: memory attribute.

C

Bit 17: memory attribute.

S

Bit 18: Shareable memory attribute.

TEX

Bits 19-21: memory attribute.

AP

Bits 24-26: Access permission.

XN

Bit 28: Instruction access disable bit.

NVIC

0xe000e100: Nested Vectored Interrupt Controller

3/99 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISER0
0x4 ISER1
0x8 ISER2
0x80 ICER0
0x84 ICER1
0x88 ICER2
0x100 ISPR0
0x104 ISPR1
0x108 ISPR2
0x180 ICPR0
0x184 ICPR1
0x188 ICPR2
0x200 IABR0
0x204 IABR1
0x208 IABR2
0x300 IPR0
0x304 IPR1
0x308 IPR2
0x30c IPR3
0x310 IPR4
0x314 IPR5
0x318 IPR6
0x31c IPR7
0x320 IPR8
0x324 IPR9
0x328 IPR10
0x32c IPR11
0x330 IPR12
0x334 IPR13
0x338 IPR14
0x33c IPR15
0x340 IPR16
0x344 IPR17
0x348 IPR18
0x34c IPR19
0x350 IPR20
Toggle registers

ISER0

Interrupt Set-Enable Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle fields

SETENA

Bits 0-31: SETENA.

ISER1

Interrupt Set-Enable Register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle fields

SETENA

Bits 0-31: SETENA.

ISER2

Interrupt Set-Enable Register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle fields

SETENA

Bits 0-31: SETENA.

ICER0

Interrupt Clear-Enable Register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle fields

CLRENA

Bits 0-31: CLRENA.

ICER1

Interrupt Clear-Enable Register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle fields

CLRENA

Bits 0-31: CLRENA.

ICER2

Interrupt Clear-Enable Register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle fields

CLRENA

Bits 0-31: CLRENA.

ISPR0

Interrupt Set-Pending Register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle fields

SETPEND

Bits 0-31: SETPEND.

ISPR1

Interrupt Set-Pending Register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle fields

SETPEND

Bits 0-31: SETPEND.

ISPR2

Interrupt Set-Pending Register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle fields

SETPEND

Bits 0-31: SETPEND.

ICPR0

Interrupt Clear-Pending Register

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle fields

CLRPEND

Bits 0-31: CLRPEND.

ICPR1

Interrupt Clear-Pending Register

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle fields

CLRPEND

Bits 0-31: CLRPEND.

ICPR2

Interrupt Clear-Pending Register

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle fields

CLRPEND

Bits 0-31: CLRPEND.

IABR0

Interrupt Active Bit Register

Offset: 0x200, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACTIVE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACTIVE
r
Toggle fields

ACTIVE

Bits 0-31: ACTIVE.

IABR1

Interrupt Active Bit Register

Offset: 0x204, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACTIVE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACTIVE
r
Toggle fields

ACTIVE

Bits 0-31: ACTIVE.

IABR2

Interrupt Active Bit Register

Offset: 0x208, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACTIVE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACTIVE
r
Toggle fields

ACTIVE

Bits 0-31: ACTIVE.

IPR0

Interrupt Priority Register

Offset: 0x300, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR1

Interrupt Priority Register

Offset: 0x304, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR2

Interrupt Priority Register

Offset: 0x308, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR3

Interrupt Priority Register

Offset: 0x30c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR4

Interrupt Priority Register

Offset: 0x310, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR5

Interrupt Priority Register

Offset: 0x314, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR6

Interrupt Priority Register

Offset: 0x318, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR7

Interrupt Priority Register

Offset: 0x31c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR8

Interrupt Priority Register

Offset: 0x320, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR9

Interrupt Priority Register

Offset: 0x324, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR10

Interrupt Priority Register

Offset: 0x328, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR11

Interrupt Priority Register

Offset: 0x32c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR12

Interrupt Priority Register

Offset: 0x330, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR13

Interrupt Priority Register

Offset: 0x334, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR14

Interrupt Priority Register

Offset: 0x338, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR15

Interrupt Priority Register

Offset: 0x33c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR16

Interrupt Priority Register

Offset: 0x340, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR17

Interrupt Priority Register

Offset: 0x344, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR18

Interrupt Priority Register

Offset: 0x348, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR19

Interrupt Priority Register

Offset: 0x34c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR20

Interrupt Priority Register

Offset: 0x350, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

NVIC_STIR

0xe000ef00: Nested vectored interrupt controller

0/1 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 STIR
Toggle registers

STIR

Software trigger interrupt register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTID
rw
Toggle fields

INTID

Bits 0-8: Software generated interrupt ID.

OPAMP

0x40010000: Operational Amplifier

16/16 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x3c OPAMP2_CSR
Toggle registers

OPAMP2_CSR

OPAMP2 control register

Offset: 0x3c, size: 32, reset: 0x00000000, access: Unspecified

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw 		OUTCAL
r 		TSTREF
rw 		TRIMOFFSETN
rw 		TRIMOFFSETP
rw 		USER_TRIM
rw 		PGA_GAIN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PGA_GAIN
rw 		CALSEL
rw 		CALON
rw 		VPS_SEL
rw 		VMS_SEL
rw 		TCM_EN
rw 		VM_SEL
rw 		VP_SEL
rw 		FORCE_VP
rw 		OPAMP2EN
rw
Toggle fields

OPAMP2EN

Bit 0: OPAMP2 enable.

Allowed values:
0: Disabled: OPAMP2 is disabled
1: Enabled: OPAMP2 is enabled

FORCE_VP

Bit 1: FORCE_VP.

Allowed values:
0: Normal: Normal operating mode
1: Calibration: Calibration mode. Non-inverting input connected to calibration reference

VP_SEL

Bits 2-3: OPAMP Non inverting input selection.

Allowed values:
1: PB14: PB14 used as OPAMP2 non-inverting input
2: PB0: PB0 used as OPAMP2 non-inverting input
3: PA7: PA7 used as OPAMP2 non-inverting input

VM_SEL

Bits 5-6: OPAMP inverting input selection.

Allowed values:
0: PC5: PC5 (VM0) used as OPAMP2 inverting input
1: PA5: PA5 (VM1) used as OPAMP2 inverting input
2: PGA: Resistor feedback output (PGA mode)
3: Follower: Follower mode

TCM_EN

Bit 7: Timer controlled Mux mode enable.

Allowed values:
0: Disabled: Timer controlled mux disabled
1: Enabled: Timer controlled mux enabled

VMS_SEL

Bit 8: OPAMP inverting input secondary selection.

Allowed values:
0: PC5: PC5 (VM0) used as OPAMP2 inverting input when TCM_EN=1
1: PA5: PA5 (VM1) used as OPAMP2 inverting input when TCM_EN=1

VPS_SEL

Bits 9-10: OPAMP Non inverting input secondary selection.

Allowed values:
1: PB14: PB14 used as OPAMP2 non-inverting input when TCM_EN=1
2: PB0: PB0 used as OPAMP2 non-inverting input when TCM_EN=1
3: PA7: PA7 used as OPAMP2 non-inverting input when TCM_EN=1

CALON

Bit 11: Calibration mode enable.

Allowed values:
0: Disabled: Calibration mode disabled
1: Enabled: Calibration mode enabled

CALSEL

Bits 12-13: Calibration selection.

Allowed values:
0: Percent3_3: VREFOPAMP=3.3% VDDA
1: Percent10: VREFOPAMP=10% VDDA
2: Percent50: VREFOPAMP=50% VDDA
3: Percent90: VREFOPAMP=90% VDDA

PGA_GAIN

Bits 14-17: Gain in PGA mode.

Allowed values:
0: Gain2: Gain 2
1: Gain4: Gain 4
2: Gain8: Gain 8
4: Gain16: Gain 16
8: Gain2_VM0: Gain 2, feedback connected to VM0
9: Gain4_VM0: Gain 4, feedback connected to VM0
10: Gain8_VM0: Gain 8, feedback connected to VM0
11: Gain16_VM0: Gain 16, feedback connected to VM0
12: Gain2_VM1: Gain 2, feedback connected to VM1
13: Gain4_VM1: Gain 4, feedback connected to VM1
14: Gain8_VM1: Gain 8, feedback connected to VM1
15: Gain16_VM1: Gain 16, feedback connected to VM1

USER_TRIM

Bit 18: User trimming enable.

Allowed values:
0: Disabled: User trimming disabled
1: Enabled: User trimming enabled

TRIMOFFSETP

Bits 19-23: Offset trimming value (PMOS).

Allowed values: 0x0-0x1f

TRIMOFFSETN

Bits 24-28: Offset trimming value (NMOS).

Allowed values: 0x0-0x1f

TSTREF

Bit 29: TSTREF.

Allowed values:
0: Output: VREFOPAMP2 is output
1: NotOutput: VREFOPAMP2 is not output

OUTCAL

Bit 30: OPAMP ouput status flag.

Allowed values:
0: Low: Non-inverting < inverting
1: High: Non-inverting > inverting

LOCK

Bit 31: OPAMP lock.

Allowed values:
0: Unlocked: Comparator CSR bits are read-write
1: Locked: Comparator CSR bits are read-only

PWR

0x40007000: Power control

4/12 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 CSR
Toggle registers

CR

power control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

1/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBP
rw 		PLS
rw 		PVDE
rw 		CSBF
rw 		CWUF
rw 		PDDS
rw 		LPDS
rw
Toggle fields

LPDS

Bit 0: Low-power deep sleep.

PDDS

Bit 1: Power down deepsleep.

Allowed values:
0: STOP_MODE: Enter Stop mode when the CPU enters deepsleep
1: STANDBY_MODE: Enter Standby mode when the CPU enters deepsleep

CWUF

Bit 2: Clear wakeup flag.

CSBF

Bit 3: Clear standby flag.

PVDE

Bit 4: Power voltage detector enable.

PLS

Bits 5-7: PVD level selection.

DBP

Bit 8: Disable backup domain write protection.

CSR

power control/status register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

3/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWUP2
rw 		EWUP1
rw 		PVDO
r 		SBF
r 		WUF
r
Toggle fields

WUF

Bit 0: Wakeup flag.

SBF

Bit 1: Standby flag.

PVDO

Bit 2: PVD output.

EWUP1

Bit 8: Enable WKUP1 pin.

EWUP2

Bit 9: Enable WKUP2 pin.

RCC

0x40021000: Reset and clock control

120/120 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 CFGR
0x8 CIR
0xc APB2RSTR
0x10 APB1RSTR
0x14 AHBENR
0x18 APB2ENR
0x1c APB1ENR
0x20 BDCR
0x24 CSR
0x28 AHBRSTR
0x2c CFGR2
0x30 CFGR3
Toggle registers

CR

Clock control register

Offset: 0x0, size: 32, reset: 0x00000083, access: Unspecified

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLRDY
r 		PLLON
rw 		CSSON
rw 		HSEBYP
rw 		HSERDY
r 		HSEON
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSICAL
r 		HSITRIM
rw 		HSIRDY
r 		HSION
rw
Toggle fields

HSION

Bit 0: Internal High Speed clock enable.

Allowed values:
0: Off: Clock Off
1: On: Clock On

HSIRDY

Bit 1: Internal High Speed clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

HSITRIM

Bits 3-7: Internal High Speed clock trimming.

Allowed values: 0x0-0x1f

HSICAL

Bits 8-15: Internal High Speed clock Calibration.

Allowed values: 0x0-0xff

HSEON

Bit 16: External High Speed clock enable.

Allowed values:
0: Off: Clock Off
1: On: Clock On

HSERDY

Bit 17: External High Speed clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

HSEBYP

Bit 18: External High Speed clock Bypass.

Allowed values:
0: NotBypassed: HSE crystal oscillator not bypassed
1: Bypassed: HSE crystal oscillator bypassed with external clock

CSSON

Bit 19: Clock Security System enable.

Allowed values:
0: Off: Clock security system disabled (clock detector OFF)
1: On: Clock security system enable (clock detector ON if the HSE is ready, OFF if not)

PLLON

Bit 24: PLL enable.

Allowed values:
0: Off: Clock Off
1: On: Clock On

PLLRDY

Bit 25: PLL clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

CFGR

Clock configuration register (RCC_CFGR)

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLNODIV
N/A 		MCOPRE
N/A 		MCO
rw 		PLLMUL
rw 		PLLXTPRE
rw 		PLLSRC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PPRE2
rw 		PPRE1
rw 		HPRE
rw 		SWS
r 		SW
rw
Toggle fields

SW

Bits 0-1: System clock Switch.

Allowed values:
0: HSI: HSI selected as system clock
1: HSE: HSE selected as system clock
2: PLL: PLL selected as system clock

SWS

Bits 2-3: System Clock Switch Status.

Allowed values:
0: HSI: HSI oscillator used as system clock
1: HSE: HSE oscillator used as system clock
2: PLL: PLL used as system clock

HPRE

Bits 4-7: AHB prescaler.

Allowed values:
8: Div2: SYSCLK divided by 2
9: Div4: SYSCLK divided by 4
10: Div8: SYSCLK divided by 8
11: Div16: SYSCLK divided by 16
12: Div64: SYSCLK divided by 64
13: Div128: SYSCLK divided by 128
14: Div256: SYSCLK divided by 256
15: Div512: SYSCLK divided by 512
0 (+): Div1: SYSCLK not divided

PPRE1

Bits 8-10: APB Low speed prescaler (APB1).

Allowed values:
4: Div2: HCLK divided by 2
5: Div4: HCLK divided by 4
6: Div8: HCLK divided by 8
7: Div16: HCLK divided by 16
0 (+): Div1: HCLK not divided

PPRE2

Bits 11-13: APB high speed prescaler (APB2).

Allowed values:
4: Div2: HCLK divided by 2
5: Div4: HCLK divided by 4
6: Div8: HCLK divided by 8
7: Div16: HCLK divided by 16
0 (+): Div1: HCLK not divided

PLLSRC

Bit 16: PLL entry clock source.

Allowed values:
0: HSI_Div2: HSI divided by 2 selected as PLL input clock
1: HSE_Div_PREDIV: HSE divided by PREDIV selected as PLL input clock

PLLXTPRE

Bit 17: HSE divider for PLL entry.

Allowed values:
0: Div1: HSE clock not divided
1: Div2: HSE clock divided by 2

PLLMUL

Bits 18-21: PLL Multiplication Factor.

Allowed values:
0: Mul2: PLL input clock x2
1: Mul3: PLL input clock x3
2: Mul4: PLL input clock x4
3: Mul5: PLL input clock x5
4: Mul6: PLL input clock x6
5: Mul7: PLL input clock x7
6: Mul8: PLL input clock x8
7: Mul9: PLL input clock x9
8: Mul10: PLL input clock x10
9: Mul11: PLL input clock x11
10: Mul12: PLL input clock x12
11: Mul13: PLL input clock x13
12: Mul14: PLL input clock x14
13: Mul15: PLL input clock x15
14: Mul16: PLL input clock x16
15: Mul16x: PLL input clock x16

MCO

Bits 24-26: Microcontroller clock output.

Allowed values:
0: NoMCO: MCO output disabled, no clock on MCO
2: LSI: Internal low speed (LSI) oscillator clock selected
3: LSE: External low speed (LSE) oscillator clock selected
4: SYSCLK: System clock selected
5: HSI: Internal RC 8 MHz (HSI) oscillator clock selected
6: HSE: External 4-32 MHz (HSE) oscillator clock selected
7: PLL: PLL clock selected (divided by 1 or 2, depending en PLLNODIV)

MCOPRE

Bits 28-30: Microcontroller Clock Output Prescaler.

Allowed values:
0: Div1: MCO is divided by 1
1: Div2: MCO is divided by 2
2: Div4: MCO is divided by 4
3: Div8: MCO is divided by 8
4: Div16: MCO is divided by 16
5: Div32: MCO is divided by 32
6: Div64: MCO is divided by 64
7: Div128: MCO is divided by 128

PLLNODIV

Bit 31: Do not divide PLL to MCO.

Allowed values:
0: Div2: PLL is divided by 2 for MCO
1: Div1: PLL is not divided for MCO

CIR

Clock interrupt register (RCC_CIR)

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSSC
w 		PLLRDYC
w 		HSERDYC
w 		HSIRDYC
w 		LSERDYC
w 		LSIRDYC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLRDYIE
rw 		HSERDYIE
rw 		HSIRDYIE
rw 		LSERDYIE
rw 		LSIRDYIE
rw 		CSSF
r 		PLLRDYF
r 		HSERDYF
r 		HSIRDYF
r 		LSERDYF
r 		LSIRDYF
r
Toggle fields

LSIRDYF

Bit 0: LSI Ready Interrupt flag.

Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt

LSERDYF

Bit 1: LSE Ready Interrupt flag.

Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt

HSIRDYF

Bit 2: HSI Ready Interrupt flag.

Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt

HSERDYF

Bit 3: HSE Ready Interrupt flag.

Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt

PLLRDYF

Bit 4: PLL Ready Interrupt flag.

Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt

CSSF

Bit 7: Clock Security System Interrupt flag.

Allowed values:
0: NotInterrupted: No clock security interrupt caused by HSE clock failure
1: Interrupted: Clock security interrupt caused by HSE clock failure

LSIRDYIE

Bit 8: LSI Ready Interrupt Enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

LSERDYIE

Bit 9: LSE Ready Interrupt Enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

HSIRDYIE

Bit 10: HSI Ready Interrupt Enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

HSERDYIE

Bit 11: HSE Ready Interrupt Enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

PLLRDYIE

Bit 12: PLL Ready Interrupt Enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

LSIRDYC

Bit 16: LSI Ready Interrupt Clear.

Allowed values:
1: Clear: Clear interrupt flag

LSERDYC

Bit 17: LSE Ready Interrupt Clear.

Allowed values:
1: Clear: Clear interrupt flag

HSIRDYC

Bit 18: HSI Ready Interrupt Clear.

Allowed values:
1: Clear: Clear interrupt flag

HSERDYC

Bit 19: HSE Ready Interrupt Clear.

Allowed values:
1: Clear: Clear interrupt flag

PLLRDYC

Bit 20: PLL Ready Interrupt Clear.

Allowed values:
1: Clear: Clear interrupt flag

CSSC

Bit 23: Clock security system interrupt clear.

Allowed values:
1: Clear: Clear CSSF flag

APB2RSTR

APB2 peripheral reset register (RCC_APB2RSTR)

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HRTIM1RST
rw 		TIM17RST
rw 		TIM16RST
rw 		TIM15RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1RST
rw 		SPI1RST
rw 		TIM1RST
rw 		SYSCFGRST
rw
Toggle fields

SYSCFGRST

Bit 0: SYSCFG and COMP reset.

Allowed values:
1: Reset: Reset the selected module

TIM1RST

Bit 11: TIM1 timer reset.

Allowed values:
1: Reset: Reset the selected module

SPI1RST

Bit 12: SPI 1 reset.

Allowed values:
1: Reset: Reset the selected module

USART1RST

Bit 14: USART1 reset.

Allowed values:
1: Reset: Reset the selected module

TIM15RST

Bit 16: TIM15 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIM16RST

Bit 17: TIM16 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIM17RST

Bit 18: TIM17 timer reset.

Allowed values:
1: Reset: Reset the selected module

HRTIM1RST

Bit 29: High Resolution Timer1 reset.

Allowed values:
1: Reset: Reset the selected module

APB1RSTR

APB1 peripheral reset register (RCC_APB1RSTR)

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAC1RST
rw 		PWRRST
rw 		DAC2RST
rw 		CANRST
rw 		I2C1RST
rw 		USART3RST
rw 		USART2RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WWDGRST
rw 		TIM7RST
rw 		TIM6RST
rw 		TIM3RST
rw 		TIM2RST
rw
Toggle fields

TIM2RST

Bit 0: Timer 2 reset.

Allowed values:
1: Reset: Reset the selected module

TIM3RST

Bit 1: Timer 3 reset.

Allowed values:
1: Reset: Reset the selected module

TIM6RST

Bit 4: Timer 6 reset.

Allowed values:
1: Reset: Reset the selected module

TIM7RST

Bit 5: Timer 7 reset.

Allowed values:
1: Reset: Reset the selected module

WWDGRST

Bit 11: Window watchdog reset.

Allowed values:
1: Reset: Reset the selected module

USART2RST

Bit 17: USART 2 reset.

Allowed values:
1: Reset: Reset the selected module

USART3RST

Bit 18: USART3 reset.

Allowed values:
1: Reset: Reset the selected module

I2C1RST

Bit 21: I2C1 reset.

Allowed values:
1: Reset: Reset the selected module

CANRST

Bit 25: CAN reset.

Allowed values:
1: Reset: Reset the selected module

DAC2RST

Bit 26: DAC2 interface reset.

Allowed values:
1: Reset: Reset the selected module

PWRRST

Bit 28: Power interface reset.

Allowed values:
1: Reset: Reset the selected module

DAC1RST

Bit 29: DAC interface reset.

Allowed values:
1: Reset: Reset the selected module

AHBENR

AHB Peripheral Clock enable register (RCC_AHBENR)

Offset: 0x14, size: 32, reset: 0x00000014, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADC34EN
rw 		ADC12EN
rw 		TSCEN
rw 		IOPFEN
rw 		IOPDEN
rw 		IOPCEN
rw 		IOPBEN
rw 		IOPAEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCEN
rw 		FLITFEN
rw 		SRAMEN
rw 		DMA1EN
rw
Toggle fields

DMA1EN

Bit 0: DMA1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SRAMEN

Bit 2: SRAM interface clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

FLITFEN

Bit 4: FLITF clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

CRCEN

Bit 6: CRC clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

IOPAEN

Bit 17: I/O port A clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

IOPBEN

Bit 18: I/O port B clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

IOPCEN

Bit 19: I/O port C clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

IOPDEN

Bit 20: I/O port D clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

IOPFEN

Bit 22: I/O port F clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TSCEN

Bit 24: Touch sensing controller clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

ADC12EN

Bit 28: ADC1 and ADC2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

ADC34EN

Bit 29: ADC3 and ADC4 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

APB2ENR

APB2 peripheral clock enable register (RCC_APB2ENR)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HRTIM1EN
rw 		TIM17EN
rw 		TIM16EN
rw 		TIM15EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1EN
rw 		SPI1EN
rw 		TIM1EN
rw 		SYSCFGEN
rw
Toggle fields

SYSCFGEN

Bit 0: SYSCFG clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM1EN

Bit 11: TIM1 Timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SPI1EN

Bit 12: SPI 1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USART1EN

Bit 14: USART1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM15EN

Bit 16: TIM15 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM16EN

Bit 17: TIM16 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM17EN

Bit 18: TIM17 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

HRTIM1EN

Bit 29: High Resolution Timer 1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

APB1ENR

APB1 peripheral clock enable register (RCC_APB1ENR)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAC1EN
rw 		PWREN
rw 		DAC2EN
rw 		CANEN
rw 		I2C1EN
rw 		USART3EN
rw 		USART2EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WWDGEN
rw 		TIM7EN
rw 		TIM6EN
rw 		TIM3EN
rw 		TIM2EN
rw
Toggle fields

TIM2EN

Bit 0: Timer 2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM3EN

Bit 1: Timer 3 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM6EN

Bit 4: Timer 6 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM7EN

Bit 5: Timer 7 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

WWDGEN

Bit 11: Window watchdog clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USART2EN

Bit 17: USART 2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USART3EN

Bit 18: USART3 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

I2C1EN

Bit 21: I2C 1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

CANEN

Bit 25: CAN clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

DAC2EN

Bit 26: DAC2 interface clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

PWREN

Bit 28: Power interface clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

DAC1EN

Bit 29: DAC interface clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

BDCR

Backup domain control register (RCC_BDCR)

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BDRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCEN
rw 		RTCSEL
rw 		LSEDRV
rw 		LSEBYP
rw 		LSERDY
r 		LSEON
rw
Toggle fields

LSEON

Bit 0: External Low Speed oscillator enable.

Allowed values:
0: Off: LSE oscillator Off
1: On: LSE oscillator On

LSERDY

Bit 1: External Low Speed oscillator ready.

Allowed values:
0: NotReady: LSE oscillator not ready
1: Ready: LSE oscillator ready

LSEBYP

Bit 2: External Low Speed oscillator bypass.

Allowed values:
0: NotBypassed: LSE crystal oscillator not bypassed
1: Bypassed: LSE crystal oscillator bypassed with external clock

LSEDRV

Bits 3-4: LSE oscillator drive capability.

Allowed values:
0: Low: Low drive capacity
1: MediumHigh: Medium-high drive capacity
2: MediumLow: Medium-low drive capacity
3: High: High drive capacity

RTCSEL

Bits 8-9: RTC clock source selection.

Allowed values:
0: NoClock: No clock
1: LSE: LSE oscillator clock used as RTC clock
2: LSI: LSI oscillator clock used as RTC clock
3: HSE: HSE oscillator clock divided by a prescaler used as RTC clock

RTCEN

Bit 15: RTC clock enable.

Allowed values:
0: Disabled: RTC clock disabled
1: Enabled: RTC clock enabled

BDRST

Bit 16: Backup domain software reset.

Allowed values:
0: Disabled: Reset not activated
1: Enabled: Reset the entire RTC domain

CSR

Control/status register (RCC_CSR)

Offset: 0x24, size: 32, reset: 0x0C000000, access: Unspecified

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPWRRSTF
rw 		WWDGRSTF
rw 		IWDGRSTF
rw 		SFTRSTF
rw 		PORRSTF
rw 		PINRSTF
rw 		OBLRSTF
rw 		RMVF
rw 		V18PWRRSTF
N/A
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSIRDY
r 		LSION
rw
Toggle fields

LSION

Bit 0: Internal low speed oscillator enable.

Allowed values:
0: Off: LSI oscillator Off
1: On: LSI oscillator On

LSIRDY

Bit 1: Internal low speed oscillator ready.

Allowed values:
0: NotReady: LSI oscillator not ready
1: Ready: LSI oscillator ready

V18PWRRSTF

Bit 23: Reset flag of the 1.8 V domain.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

RMVF

Bit 24: Remove reset flag.

Allowed values:
1: Clear: Clears the reset flag

OBLRSTF

Bit 25: Option byte loader reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

PINRSTF

Bit 26: PIN reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

PORRSTF

Bit 27: POR/PDR reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

SFTRSTF

Bit 28: Software reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

IWDGRSTF

Bit 29: Independent watchdog reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

WWDGRSTF

Bit 30: Window watchdog reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

LPWRRSTF

Bit 31: Low-power reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

AHBRSTR

AHB peripheral reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADC12RST
rw 		TSCRST
rw 		IOPFRST
rw 		IOPDRST
rw 		IOPCRST
rw 		IOPBRST
rw 		IOPARST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

IOPARST

Bit 17: I/O port A reset.

Allowed values:
1: Reset: Reset the selected module

IOPBRST

Bit 18: I/O port B reset.

Allowed values:
1: Reset: Reset the selected module

IOPCRST

Bit 19: I/O port C reset.

Allowed values:
1: Reset: Reset the selected module

IOPDRST

Bit 20: I/O port D reset.

Allowed values:
1: Reset: Reset the selected module

IOPFRST

Bit 22: I/O port F reset.

Allowed values:
1: Reset: Reset the selected module

TSCRST

Bit 24: Touch sensing controller reset.

Allowed values:
1: Reset: Reset the selected module

ADC12RST

Bit 28: ADC1 and ADC2 reset.

Allowed values:
1: Reset: Reset the selected module

CFGR2

Clock configuration register 2

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADC12PRES
rw 		PREDIV
rw
Toggle fields

PREDIV

Bits 0-3: PREDIV division factor.

Allowed values:
0: Div1: PREDIV input clock not divided
1: Div2: PREDIV input clock divided by 2
2: Div3: PREDIV input clock divided by 3
3: Div4: PREDIV input clock divided by 4
4: Div5: PREDIV input clock divided by 5
5: Div6: PREDIV input clock divided by 6
6: Div7: PREDIV input clock divided by 7
7: Div8: PREDIV input clock divided by 8
8: Div9: PREDIV input clock divided by 9
9: Div10: PREDIV input clock divided by 10
10: Div11: PREDIV input clock divided by 11
11: Div12: PREDIV input clock divided by 12
12: Div13: PREDIV input clock divided by 13
13: Div14: PREDIV input clock divided by 14
14: Div15: PREDIV input clock divided by 15
15: Div16: PREDIV input clock divided by 16

ADC12PRES

Bits 4-8: ADC1 and ADC2 prescaler.

Allowed values:
0: NoClock: No clock
16: Div1: PLL clock not divided
17: Div2: PLL clock divided by 2
18: Div4: PLL clock divided by 4
19: Div6: PLL clock divided by 6
20: Div8: PLL clock divided by 8
21: Div10: PLL clock divided by 10
22: Div12: PLL clock divided by 12
23: Div16: PLL clock divided by 16
24: Div32: PLL clock divided by 32
25: Div64: PLL clock divided by 64
26: Div128: PLL clock divided by 128
27: Div256: PLL clock divided by 256

CFGR3

Clock configuration register 3

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIM1SW
rw 		I2C1SW
rw 		USART1SW
rw
Toggle fields

USART1SW

Bits 0-1: USART1 clock source selection.

Allowed values:
0: PCLK: PCLK selected as USART clock source
1: SYSCLK: SYSCLK selected as USART clock source
2: LSE: LSE selected as USART clock source
3: HSI: HSI selected as USART clock source

I2C1SW

Bit 4: I2C1 clock source selection.

Allowed values:
0: HSI: HSI clock selected as I2C clock source
1: SYSCLK: SYSCLK clock selected as I2C clock source

TIM1SW

Bit 8: Timer1 clock source selection.

Allowed values:
0: PCLK2: PCLK2 clock (doubled frequency when prescaled)
1: PLL: PLL vco output (running up to 144 MHz)

RTC

0x40002800: Real-time clock

159/159 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 TR
0x4 DR
0x8 CR
0xc ISR
0x10 PRER
0x14 WUTR
0x1c ALRM[A]R
0x20 ALRM[B]R
0x24 WPR
0x28 SSR
0x2c SHIFTR
0x30 TSTR
0x34 TSDR
0x38 TSSSR
0x3c CALR
0x40 TAFCR
0x44 ALRM[A]SSR
0x48 ALRM[B]SSR
0x50 BKP[0]R
0x54 BKP[1]R
0x58 BKP[2]R
0x5c BKP[3]R
0x60 BKP[4]R
0x64 BKP[5]R
0x68 BKP[6]R
0x6c BKP[7]R
0x70 BKP[8]R
0x74 BKP[9]R
0x78 BKP[10]R
0x7c BKP[11]R
0x80 BKP[12]R
0x84 BKP[13]R
0x88 BKP[14]R
0x8c BKP[15]R
0x90 BKP[16]R
0x94 BKP[17]R
0x98 BKP[18]R
0x9c BKP[19]R
0xa0 BKP[20]R
0xa4 BKP[21]R
0xa8 BKP[22]R
0xac BKP[23]R
0xb0 BKP[24]R
0xb4 BKP[25]R
0xb8 BKP[26]R
0xbc BKP[27]R
0xc0 BKP[28]R
0xc4 BKP[29]R
0xc8 BKP[30]R
0xcc BKP[31]R
Toggle registers

TR

time register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PM
rw 		HT
rw 		HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MNT
rw 		MNU
rw 		ST
rw 		SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

Allowed values: 0x0-0xf

ST

Bits 4-6: Second tens in BCD format.

Allowed values: 0x0-0x7

MNU

Bits 8-11: Minute units in BCD format.

Allowed values: 0x0-0xf

MNT

Bits 12-14: Minute tens in BCD format.

Allowed values: 0x0-0x7

HU

Bits 16-19: Hour units in BCD format.

Allowed values: 0x0-0xf

HT

Bits 20-21: Hour tens in BCD format.

Allowed values: 0x0-0x3

PM

Bit 22: AM/PM notation.

Allowed values:
0: AM: AM or 24-hour format
1: PM: PM

DR

date register

Offset: 0x4, size: 32, reset: 0x00002101, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
YT
rw 		YU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDU
rw 		MT
rw 		MU
rw 		DT
rw 		DU
rw
Toggle fields

DU

Bits 0-3: Date units in BCD format.

Allowed values: 0x0-0xf

DT

Bits 4-5: Date tens in BCD format.

Allowed values: 0x0-0x3

MU

Bits 8-11: Month units in BCD format.

Allowed values: 0x0-0xf

MT

Bit 12: Month tens in BCD format.

Allowed values:
0: Zero: Month tens is 0
1: One: Month tens is 1

WDU

Bits 13-15: Week day units.

Allowed values: 0x1-0x7

YU

Bits 16-19: Year units in BCD format.

Allowed values: 0x0-0xf

YT

Bits 20-23: Year tens in BCD format.

Allowed values: 0x0-0xf

CR

control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COE
rw 		OSEL
rw 		POL
rw 		COSEL
rw 		BKP
rw 		SUB1H
rw 		ADD1H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSIE
rw 		WUTIE
rw 		ALRBIE
rw 		ALRAIE
rw 		TSE
rw 		WUTE
rw 		ALRBE
rw 		ALRAE
rw 		FMT
rw 		BYPSHAD
rw 		REFCKON
rw 		TSEDGE
rw 		WUCKSEL
rw
Toggle fields

WUCKSEL

Bits 0-2: Wakeup clock selection.

Allowed values:
0: Div16: RTC/16 clock is selected
1: Div8: RTC/8 clock is selected
2: Div4: RTC/4 clock is selected
3: Div2: RTC/2 clock is selected
4: ClockSpare: ck_spre (usually 1 Hz) clock is selected
6: ClockSpareWithOffset: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value

TSEDGE

Bit 3: Time-stamp event active edge.

Allowed values:
0: RisingEdge: RTC_TS input rising edge generates a time-stamp event
1: FallingEdge: RTC_TS input falling edge generates a time-stamp event

REFCKON

Bit 4: Reference clock detection enable (50 or 60 Hz).

Allowed values:
0: Disabled: RTC_REFIN detection disabled
1: Enabled: RTC_REFIN detection enabled

BYPSHAD

Bit 5: Bypass the shadow registers.

Allowed values:
0: ShadowReg: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles
1: BypassShadowReg: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters

FMT

Bit 6: Hour format.

Allowed values:
0: Twenty_Four_Hour: 24 hour/day format
1: AM_PM: AM/PM hour format

ALRAE

Bit 8: Alarm A enable.

Allowed values:
0: Disabled: Alarm A disabled
1: Enabled: Alarm A enabled

ALRBE

Bit 9: Alarm B enable.

Allowed values:
0: Disabled: Alarm B disabled
1: Enabled: Alarm B enabled

WUTE

Bit 10: Wakeup timer enable.

Allowed values:
0: Disabled: Wakeup timer disabled
1: Enabled: Wakeup timer enabled

TSE

Bit 11: Time stamp enable.

Allowed values:
0: Disabled: Timestamp disabled
1: Enabled: Timestamp enabled

ALRAIE

Bit 12: Alarm A interrupt enable.

Allowed values:
0: Disabled: Alarm A interrupt disabled
1: Enabled: Alarm A interrupt enabled

ALRBIE

Bit 13: Alarm B interrupt enable.

Allowed values:
0: Disabled: Alarm B Interrupt disabled
1: Enabled: Alarm B Interrupt enabled

WUTIE

Bit 14: Wakeup timer interrupt enable.

Allowed values:
0: Disabled: Wakeup timer interrupt disabled
1: Enabled: Wakeup timer interrupt enabled

TSIE

Bit 15: Time-stamp interrupt enable.

Allowed values:
0: Disabled: Time-stamp Interrupt disabled
1: Enabled: Time-stamp Interrupt enabled

ADD1H

Bit 16: Add 1 hour (summer time change).

Allowed values:
1: Add1: Adds 1 hour to the current time. This can be used for summer time change outside initialization mode

SUB1H

Bit 17: Subtract 1 hour (winter time change).

Allowed values:
1: Sub1: Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode

BKP

Bit 18: Backup.

Allowed values:
0: DST_Not_Changed: Daylight Saving Time change has not been performed
1: DST_Changed: Daylight Saving Time change has been performed

COSEL

Bit 19: Calibration output selection.

Allowed values:
0: CalFreq_512Hz: Calibration output is 512 Hz (with default prescaler setting)
1: CalFreq_1Hz: Calibration output is 1 Hz (with default prescaler setting)

POL

Bit 20: Output polarity.

Allowed values:
0: High: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])
1: Low: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])

OSEL

Bits 21-22: Output selection.

Allowed values:
0: Disabled: Output disabled
1: AlarmA: Alarm A output enabled
2: AlarmB: Alarm B output enabled
3: Wakeup: Wakeup output enabled

COE

Bit 23: Calibration output enable.

Allowed values:
0: Disabled: Calibration output disabled
1: Enabled: Calibration output enabled

ISR

initialization and status register

Offset: 0xc, size: 32, reset: 0x00000007, access: Unspecified

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RECALPF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP3F
rw 		TAMP2F
rw 		TAMP1F
rw 		TSOVF
rw 		TSF
rw 		WUTF
rw 		ALRBF
rw 		ALRAF
rw 		INIT
rw 		INITF
r 		RSF
rw 		INITS
r 		SHPF
rw 		WUTWF
r 		ALRBWF
r 		ALRAWF
r
Toggle fields

ALRAWF

Bit 0: Alarm A write flag.

Allowed values:
0: UpdateNotAllowed: Alarm update not allowed
1: UpdateAllowed: Alarm update allowed

ALRBWF

Bit 1: Alarm B write flag.

Allowed values:
0: UpdateNotAllowed: Alarm update not allowed
1: UpdateAllowed: Alarm update allowed

WUTWF

Bit 2: Wakeup timer write flag.

Allowed values:
0: UpdateNotAllowed: Wakeup timer configuration update not allowed
1: UpdateAllowed: Wakeup timer configuration update allowed

SHPF

Bit 3: Shift operation pending.

Allowed values:
0: NoShiftPending: No shift operation is pending
1: ShiftPending: A shift operation is pending

INITS

Bit 4: Initialization status flag.

Allowed values:
0: NotInitalized: Calendar has not been initialized
1: Initalized: Calendar has been initialized

RSF

Bit 5: Registers synchronization flag.

Allowed values:
0: NotSynced: Calendar shadow registers not yet synchronized
1: Synced: Calendar shadow registers synchronized

INITF

Bit 6: Initialization flag.

Allowed values:
0: NotAllowed: Calendar registers update is not allowed
1: Allowed: Calendar registers update is allowed

INIT

Bit 7: Initialization mode.

Allowed values:
0: FreeRunningMode: Free running mode
1: InitMode: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.

ALRAF

Bit 8: Alarm A flag.

Allowed values:
1: Match: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR)

ALRBF

Bit 9: Alarm B flag.

Allowed values:
1: Match: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR)

WUTF

Bit 10: Wakeup timer flag.

Allowed values:
1: Zero: This flag is set by hardware when the wakeup auto-reload counter reaches 0

TSF

Bit 11: Time-stamp flag.

Allowed values:
1: TimestampEvent: This flag is set by hardware when a time-stamp event occurs

TSOVF

Bit 12: Time-stamp overflow flag.

Allowed values:
1: Overflow: This flag is set by hardware when a time-stamp event occurs while TSF is already set

TAMP1F

Bit 13: Tamper detection flag.

Allowed values:
1: Tampered: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input

TAMP2F

Bit 14: RTC_TAMP2 detection flag.

Allowed values:
1: Tampered: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input

TAMP3F

Bit 15: RTC_TAMP3 detection flag.

Allowed values:
1: Tampered: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input

RECALPF

Bit 16: Recalibration pending Flag.

Allowed values:
1: Pending: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0

PRER

prescaler register

Offset: 0x10, size: 32, reset: 0x007F00FF, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PREDIV_A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PREDIV_S
rw
Toggle fields

PREDIV_S

Bits 0-14: Synchronous prescaler factor.

Allowed values: 0x0-0x7fff

PREDIV_A

Bits 16-22: Asynchronous prescaler factor.

Allowed values: 0x0-0x7f

WUTR

wakeup timer register

Offset: 0x14, size: 32, reset: 0x0000FFFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WUT
rw
Toggle fields

WUT

Bits 0-15: Wakeup auto-reload value bits.

Allowed values: 0x0-0xffff

ALRM[A]R

Alarm A register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSK4
rw 		WDSEL
rw 		DT
rw 		DU
rw 		MSK3
rw 		PM
rw 		HT
rw 		HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSK2
rw 		MNT
rw 		MNU
rw 		MSK1
rw 		ST
rw 		SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

Allowed values: 0x0-0xf

ST

Bits 4-6: Second tens in BCD format.

Allowed values: 0x0-0x7

MSK1

Bit 7: Alarm seconds mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

MNU

Bits 8-11: Minute units in BCD format.

Allowed values: 0x0-0xf

MNT

Bits 12-14: Minute tens in BCD format.

Allowed values: 0x0-0x7

MSK2

Bit 15: Alarm minutes mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

HU

Bits 16-19: Hour units in BCD format.

Allowed values: 0x0-0xf

HT

Bits 20-21: Hour tens in BCD format.

Allowed values: 0x0-0x3

PM

Bit 22: AM/PM notation.

Allowed values:
0: AM: AM or 24-hour format
1: PM: PM

MSK3

Bit 23: Alarm hours mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

DU

Bits 24-27: Date units or day in BCD format.

Allowed values: 0x0-0xf

DT

Bits 28-29: Date tens in BCD format.

Allowed values: 0x0-0x3

WDSEL

Bit 30: Week day selection.

Allowed values:
0: DateUnits: DU[3:0] represents the date units
1: WeekDay: DU[3:0] represents the week day. DT[1:0] is don’t care.

MSK4

Bit 31: Alarm date mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

ALRM[B]R

Alarm B register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSK4
rw 		WDSEL
rw 		DT
rw 		DU
rw 		MSK3
rw 		PM
rw 		HT
rw 		HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSK2
rw 		MNT
rw 		MNU
rw 		MSK1
rw 		ST
rw 		SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

Allowed values: 0x0-0xf

ST

Bits 4-6: Second tens in BCD format.

Allowed values: 0x0-0x7

MSK1

Bit 7: Alarm seconds mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

MNU

Bits 8-11: Minute units in BCD format.

Allowed values: 0x0-0xf

MNT

Bits 12-14: Minute tens in BCD format.

Allowed values: 0x0-0x7

MSK2

Bit 15: Alarm minutes mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

HU

Bits 16-19: Hour units in BCD format.

Allowed values: 0x0-0xf

HT

Bits 20-21: Hour tens in BCD format.

Allowed values: 0x0-0x3

PM

Bit 22: AM/PM notation.

Allowed values:
0: AM: AM or 24-hour format
1: PM: PM

MSK3

Bit 23: Alarm hours mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

DU

Bits 24-27: Date units or day in BCD format.

Allowed values: 0x0-0xf

DT

Bits 28-29: Date tens in BCD format.

Allowed values: 0x0-0x3

WDSEL

Bit 30: Week day selection.

Allowed values:
0: DateUnits: DU[3:0] represents the date units
1: WeekDay: DU[3:0] represents the week day. DT[1:0] is don’t care.

MSK4

Bit 31: Alarm date mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

WPR

write protection register

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-7: Write protection key.

Allowed values: 0x0-0xff

SSR

sub second register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
r
Toggle fields

SS

Bits 0-15: Sub second value.

Allowed values: 0x0-0xffff

SHIFTR

shift control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: write-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD1S
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUBFS
w
Toggle fields

SUBFS

Bits 0-14: Subtract a fraction of a second.

Allowed values: 0x0-0x7fff

ADD1S

Bit 31: Add one second.

Allowed values:
1: Add1: Add one second to the clock/calendar

TSTR

time stamp time register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PM
rw 		HT
rw 		HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MNT
rw 		MNU
rw 		ST
rw 		SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

Allowed values: 0x0-0xf

ST

Bits 4-6: Second tens in BCD format.

Allowed values: 0x0-0x7

MNU

Bits 8-11: Minute units in BCD format.

Allowed values: 0x0-0xf

MNT

Bits 12-14: Minute tens in BCD format.

Allowed values: 0x0-0x7

HU

Bits 16-19: Hour units in BCD format.

Allowed values: 0x0-0xf

HT

Bits 20-21: Hour tens in BCD format.

Allowed values: 0x0-0x3

PM

Bit 22: AM/PM notation.

Allowed values:
0: AM: AM or 24-hour format
1: PM: PM

TSDR

time stamp date register

Offset: 0x34, size: 32, reset: 0x00002101, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
YT
rw 		YU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDU
rw 		MT
rw 		MU
rw 		DT
rw 		DU
rw
Toggle fields

DU

Bits 0-3: Date units in BCD format.

Allowed values: 0x0-0xf

DT

Bits 4-5: Date tens in BCD format.

Allowed values: 0x0-0x3

MU

Bits 8-11: Month units in BCD format.

Allowed values: 0x0-0xf

MT

Bit 12: Month tens in BCD format.

Allowed values:
0: Zero: Month tens is 0
1: One: Month tens is 1

WDU

Bits 13-15: Week day units.

Allowed values: 0x1-0x7

YU

Bits 16-19: Year units in BCD format.

Allowed values: 0x0-0xf

YT

Bits 20-23: Year tens in BCD format.

Allowed values: 0x0-0xf

TSSSR

timestamp sub second register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
r
Toggle fields

SS

Bits 0-15: Sub second value.

Allowed values: 0x0-0xffff

CALR

calibration register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALP
rw 		CALW8
rw 		CALW16
rw 		CALM
rw
Toggle fields

CALM

Bits 0-8: Calibration minus.

Allowed values: 0x0-0x1ff

CALW16

Bit 13: Use a 16-second calibration cycle period.

Allowed values:
1: Sixteen_Second: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1

CALW8

Bit 14: Use an 8-second calibration cycle period.

Allowed values:
1: Eight_Second: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected

CALP

Bit 15: Increase frequency of RTC by 488.5 ppm.

Allowed values:
0: NoChange: No RTCCLK pulses are added
1: IncreaseFreq: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm)

TAFCR

tamper and alternate function configuration register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PC15MODE
rw 		PC15VALUE
rw 		PC14MODE
rw 		PC14VALUE
rw 		PC13MODE
rw 		PC13VALUE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMPPUDIS
rw 		TAMPPRCH
rw 		TAMPFLT
rw 		TAMPFREQ
rw 		TAMPTS
rw 		TAMP3TRG
rw 		TAMP3E
rw 		TAMP2TRG
rw 		TAMP2E
rw 		TAMPIE
rw 		TAMP1TRG
rw 		TAMP1E
rw
Toggle fields

TAMP1E

Bit 0: Tamper 1 detection enable.

Allowed values:
0: Disabled: RTC_TAMPx input detection disabled
1: Enabled: RTC_TAMPx input detection enabled

TAMP1TRG

Bit 1: Active level for tamper 1.

Allowed values:
0: RisingEdge: If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event.
1: FallingEdge: If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event

TAMPIE

Bit 2: Tamper interrupt enable.

Allowed values:
0: Disabled: Tamper interrupt disabled
1: Enabled: Tamper interrupt enabled

TAMP2E

Bit 3: Tamper 2 detection enable.

Allowed values:
0: Disabled: RTC_TAMPx input detection disabled
1: Enabled: RTC_TAMPx input detection enabled

TAMP2TRG

Bit 4: Active level for tamper 2.

Allowed values:
0: RisingEdge: If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event.
1: FallingEdge: If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event

TAMP3E

Bit 5: Tamper 3 detection enable.

Allowed values:
0: Disabled: RTC_TAMPx input detection disabled
1: Enabled: RTC_TAMPx input detection enabled

TAMP3TRG

Bit 6: Active level for tamper 3.

Allowed values:
0: RisingEdge: If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event.
1: FallingEdge: If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event

TAMPTS

Bit 7: Activate timestamp on tamper detection event.

Allowed values:
0: NoSave: Tamper detection event does not cause a timestamp to be saved
1: Save: Save timestamp on tamper detection event

TAMPFREQ

Bits 8-10: Tamper sampling frequency.

Allowed values:
0: Div32768: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz)
1: Div16384: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz)
2: Div8192: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz)
3: Div4096: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz)
4: Div2048: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz)
5: Div1024: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz)
6: Div512: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz)
7: Div256: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)

TAMPFLT

Bits 11-12: Tamper filter count.

Allowed values:
0: Immediate: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input)
1: Samples2: Tamper event is activated after 2 consecutive samples at the active level
2: Samples4: Tamper event is activated after 4 consecutive samples at the active level
3: Samples8: Tamper event is activated after 8 consecutive samples at the active level

TAMPPRCH

Bits 13-14: Tamper precharge duration.

Allowed values:
0: Cycles1: 1 RTCCLK cycle
1: Cycles2: 2 RTCCLK cycles
2: Cycles4: 4 RTCCLK cycles
3: Cycles8: 8 RTCCLK cycles

TAMPPUDIS

Bit 15: TAMPER pull-up disable.

Allowed values:
0: Enabled: Precharge RTC_TAMPx pins before sampling (enable internal pull-up)
1: Disabled: Disable precharge of RTC_TAMPx pins

PC13VALUE

Bit 18: PC13 value.

Allowed values:
0: Low: If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic low
1: High: If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic high

PC13MODE

Bit 19: PC13 mode.

Allowed values:
0: Floating: PCx is controlled by the GPIO configuration Register. Consequently PC15 is floating in Standby mode
1: PushPull: PCx is forced to push-pull output if LSE is disabled

PC14VALUE

Bit 20: PC14 value.

Allowed values:
0: Low: If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic low
1: High: If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic high

PC14MODE

Bit 21: PC 14 mode.

Allowed values:
0: Floating: PCx is controlled by the GPIO configuration Register. Consequently PC15 is floating in Standby mode
1: PushPull: PCx is forced to push-pull output if LSE is disabled

PC15VALUE

Bit 22: PC15 value.

Allowed values:
0: Low: If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic low
1: High: If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic high

PC15MODE

Bit 23: PC15 mode.

Allowed values:
0: Floating: PCx is controlled by the GPIO configuration Register. Consequently PC15 is floating in Standby mode
1: PushPull: PCx is forced to push-pull output if LSE is disabled

ALRM[A]SSR

Alarm A sub-second register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASKSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
rw
Toggle fields

SS

Bits 0-14: Sub seconds value.

Allowed values: 0x0-0x7fff

MASKSS

Bits 24-27: Mask the most-significant bits starting at this bit.

Allowed values: 0x0-0xf

ALRM[B]SSR

Alarm B sub-second register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASKSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
rw
Toggle fields

SS

Bits 0-14: Sub seconds value.

Allowed values: 0x0-0x7fff

MASKSS

Bits 24-27: Mask the most-significant bits starting at this bit.

Allowed values: 0x0-0xf

BKP[0]R

backup register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[1]R

backup register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[2]R

backup register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[3]R

backup register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[4]R

backup register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[5]R

backup register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[6]R

backup register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[7]R

backup register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[8]R

backup register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[9]R

backup register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[10]R

backup register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[11]R

backup register

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[12]R

backup register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[13]R

backup register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[14]R

backup register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[15]R

backup register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[16]R

backup register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[17]R

backup register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[18]R

backup register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[19]R

backup register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[20]R

backup register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[21]R

backup register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[22]R

backup register

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[23]R

backup register

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[24]R

backup register

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[25]R

backup register

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[26]R

backup register

Offset: 0xb8, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[27]R

backup register

Offset: 0xbc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[28]R

backup register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[29]R

backup register

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[30]R

backup register

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[31]R

backup register

Offset: 0xcc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

SCB

0xe000ed00: System control block

5/74 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CPUID
0x4 ICSR
0x8 VTOR
0xc AIRCR
0x10 SCR
0x14 CCR
0x18 SHPR1
0x1c SHPR2
0x20 SHPR3
0x24 SHCRS
0x28 CFSR_UFSR_BFSR_MMFSR
0x2c HFSR
0x34 MMFAR
0x38 BFAR
0x3c AFSR
Toggle registers

CPUID

CPUID base register

Offset: 0x0, size: 32, reset: 0x410FC241, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Implementer
r 		Variant
r 		Constant
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PartNo
r 		Revision
r
Toggle fields

Revision

Bits 0-3: Revision number.

PartNo

Bits 4-15: Part number of the processor.

Constant

Bits 16-19: Reads as 0xF.

Variant

Bits 20-23: Variant number.

Implementer

Bits 24-31: Implementer code.

ICSR

Interrupt control and state register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NMIPENDSET
rw 		PENDSVSET
rw 		PENDSVCLR
rw 		PENDSTSET
rw 		PENDSTCLR
rw 		ISRPENDING
rw 		VECTPENDING
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VECTPENDING
rw 		RETTOBASE
rw 		VECTACTIVE
rw
Toggle fields

VECTACTIVE

Bits 0-8: Active vector.

RETTOBASE

Bit 11: Return to base level.

VECTPENDING

Bits 12-18: Pending vector.

ISRPENDING

Bit 22: Interrupt pending flag.

PENDSTCLR

Bit 25: SysTick exception clear-pending bit.

PENDSTSET

Bit 26: SysTick exception set-pending bit.

PENDSVCLR

Bit 27: PendSV clear-pending bit.

PENDSVSET

Bit 28: PendSV set-pending bit.

NMIPENDSET

Bit 31: NMI set-pending bit..

VTOR

Vector table offset register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TBLOFF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBLOFF
rw
Toggle fields

TBLOFF

Bits 9-29: Vector table base offset field.

AIRCR

Application interrupt and reset control register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VECTKEYSTAT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENDIANESS
rw 		PRIGROUP
rw 		SYSRESETREQ
rw 		VECTCLRACTIVE
rw 		VECTRESET
rw
Toggle fields

VECTRESET

Bit 0: VECTRESET.

VECTCLRACTIVE

Bit 1: VECTCLRACTIVE.

SYSRESETREQ

Bit 2: SYSRESETREQ.

PRIGROUP

Bits 8-10: PRIGROUP.

ENDIANESS

Bit 15: ENDIANESS.

VECTKEYSTAT

Bits 16-31: Register key.

SCR

System control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEVEONPEND
rw 		SLEEPDEEP
rw 		SLEEPONEXIT
rw
Toggle fields

SLEEPONEXIT

Bit 1: SLEEPONEXIT.

SLEEPDEEP

Bit 2: SLEEPDEEP.

SEVEONPEND

Bit 4: Send Event on Pending bit.

CCR

Configuration and control register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STKALIGN
rw 		BFHFNMIGN
rw 		DIV_0_TRP
rw 		UNALIGN__TRP
rw 		USERSETMPEND
rw 		NONBASETHRDENA
rw
Toggle fields

NONBASETHRDENA

Bit 0: Configures how the processor enters Thread mode.

USERSETMPEND

Bit 1: USERSETMPEND.

UNALIGN__TRP

Bit 3: UNALIGN_ TRP.

DIV_0_TRP

Bit 4: DIV_0_TRP.

BFHFNMIGN

Bit 8: BFHFNMIGN.

STKALIGN

Bit 9: STKALIGN.

SHPR1

System handler priority registers

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRI_6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_5
rw 		PRI_4
rw
Toggle fields

PRI_4

Bits 0-7: Priority of system handler 4.

PRI_5

Bits 8-15: Priority of system handler 5.

PRI_6

Bits 16-23: Priority of system handler 6.

SHPR2

System handler priority registers

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRI_11
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

PRI_11

Bits 24-31: Priority of system handler 11.

SHPR3

System handler priority registers

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRI_15
rw 		PRI_14
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

PRI_14

Bits 16-23: Priority of system handler 14.

PRI_15

Bits 24-31: Priority of system handler 15.

SHCRS

System handler control and state register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USGFAULTENA
rw 		BUSFAULTENA
rw 		MEMFAULTENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SVCALLPENDED
rw 		BUSFAULTPENDED
rw 		MEMFAULTPENDED
rw 		USGFAULTPENDED
rw 		SYSTICKACT
rw 		PENDSVACT
rw 		MONITORACT
rw 		SVCALLACT
rw 		USGFAULTACT
rw 		BUSFAULTACT
rw 		MEMFAULTACT
rw
Toggle fields

MEMFAULTACT

Bit 0: Memory management fault exception active bit.

BUSFAULTACT

Bit 1: Bus fault exception active bit.

USGFAULTACT

Bit 3: Usage fault exception active bit.

SVCALLACT

Bit 7: SVC call active bit.

MONITORACT

Bit 8: Debug monitor active bit.

PENDSVACT

Bit 10: PendSV exception active bit.

SYSTICKACT

Bit 11: SysTick exception active bit.

USGFAULTPENDED

Bit 12: Usage fault exception pending bit.

MEMFAULTPENDED

Bit 13: Memory management fault exception pending bit.

BUSFAULTPENDED

Bit 14: Bus fault exception pending bit.

SVCALLPENDED

Bit 15: SVC call pending bit.

MEMFAULTENA

Bit 16: Memory management fault enable bit.

BUSFAULTENA

Bit 17: Bus fault enable bit.

USGFAULTENA

Bit 18: Usage fault enable bit.

CFSR_UFSR_BFSR_MMFSR

Configurable fault status register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIVBYZERO
rw 		UNALIGNED
rw 		NOCP
rw 		INVPC
rw 		INVSTATE
rw 		UNDEFINSTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BFARVALID
rw 		LSPERR
rw 		STKERR
rw 		UNSTKERR
rw 		IMPRECISERR
rw 		PRECISERR
rw 		IBUSERR
rw 		MMARVALID
rw 		MLSPERR
rw 		MSTKERR
rw 		MUNSTKERR
rw 		IACCVIOL
rw
Toggle fields

IACCVIOL

Bit 1: Instruction access violation flag.

MUNSTKERR

Bit 3: Memory manager fault on unstacking for a return from exception.

MSTKERR

Bit 4: Memory manager fault on stacking for exception entry..

MLSPERR

Bit 5: MLSPERR.

MMARVALID

Bit 7: Memory Management Fault Address Register (MMAR) valid flag.

IBUSERR

Bit 8: Instruction bus error.

PRECISERR

Bit 9: Precise data bus error.

IMPRECISERR

Bit 10: Imprecise data bus error.

UNSTKERR

Bit 11: Bus fault on unstacking for a return from exception.

STKERR

Bit 12: Bus fault on stacking for exception entry.

LSPERR

Bit 13: Bus fault on floating-point lazy state preservation.

BFARVALID

Bit 15: Bus Fault Address Register (BFAR) valid flag.

UNDEFINSTR

Bit 16: Undefined instruction usage fault.

INVSTATE

Bit 17: Invalid state usage fault.

INVPC

Bit 18: Invalid PC load usage fault.

NOCP

Bit 19: No coprocessor usage fault..

UNALIGNED

Bit 24: Unaligned access usage fault.

DIVBYZERO

Bit 25: Divide by zero usage fault.

HFSR

Hard fault status register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DEBUG_VT
rw 		FORCED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VECTTBL
rw
Toggle fields

VECTTBL

Bit 1: Vector table hard fault.

FORCED

Bit 30: Forced hard fault.

DEBUG_VT

Bit 31: Reserved for Debug use.

MMFAR

Memory management fault address register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMFAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMFAR
rw
Toggle fields

MMFAR

Bits 0-31: Memory management fault address.

BFAR

Bus fault address register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BFAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BFAR
rw
Toggle fields

BFAR

Bits 0-31: Bus fault address.

AFSR

Auxiliary fault status register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IMPDEF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IMPDEF
rw
Toggle fields

IMPDEF

Bits 0-31: Implementation defined.

SCB_ACTRL

0xe000e008: System control block ACTLR

0/5 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ACTRL
Toggle registers

ACTRL

Auxiliary control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISOOFP
rw 		DISFPCA
rw 		DISFOLD
rw 		DISDEFWBUF
rw 		DISMCYCINT
rw
Toggle fields

DISMCYCINT

Bit 0: DISMCYCINT.

DISDEFWBUF

Bit 1: DISDEFWBUF.

DISFOLD

Bit 2: DISFOLD.

DISFPCA

Bit 8: DISFPCA.

DISOOFP

Bit 9: DISOOFP.

SPI1

0x40013000: Serial peripheral interface/Inter-IC2

53/53 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) CR1
0x4 (16-bit) CR2
0x8 (16-bit) SR
0xc (16-bit) DR
0xc (8-bit) DR8
0x10 (16-bit) CRCPR
0x14 (16-bit) RXCRCR
0x18 (16-bit) TXCRCR
0x1c (16-bit) I2SCFGR
0x20 (16-bit) I2SPR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

14/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw 		BIDIOE
rw 		CRCEN
rw 		CRCNEXT
rw 		CRCL
rw 		RXONLY
rw 		SSM
rw 		SSI
rw 		LSBFIRST
rw 		SPE
rw 		BR
rw 		MSTR
rw 		CPOL
rw 		CPHA
rw
Toggle fields

CPHA

Bit 0: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 1: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

MSTR

Bit 2: Master selection.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

BR

Bits 3-5: Baud rate control.

Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256

SPE

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LSBFIRST

Bit 7: Frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SSI

Bit 8: Internal slave select.

Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored

SSM

Bit 9: Software slave management.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

RXONLY

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)

CRCL

Bit 11: Data frame format.

Allowed values:
0: EightBit: 8-bit CRC length
1: SixteenBit: 16-bit CRC length

CRCNEXT

Bit 12: CRC transfer next.

Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register

CRCEN

Bit 13: Hardware CRC calculation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BIDIOE

Bit 14: Output enable in bidirectional mode.

Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)

BIDIMODE

Bit 15: Bidirectional data mode enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CR2

control register 2

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDMA_TX
rw 		LDMA_RX
rw 		FRXTH
rw 		DS
rw 		TXEIE
rw 		RXNEIE
rw 		ERRIE
rw 		FRF
rw 		NSSP
rw 		SSOE
rw 		TXDMAEN
rw 		RXDMAEN
rw
Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 1: Tx buffer DMA enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

SSOE

Bit 2: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

NSSP

Bit 3: NSS pulse management.

Allowed values:
0: NoPulse: No NSS pulse
1: PulseGenerated: NSS pulse generated

FRF

Bit 4: Frame format.

Allowed values:
0: Motorola: SPI Motorola mode
1: TI: SPI TI mode

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked

TXEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked

DS

Bits 8-11: Data size.

Allowed values:
3: FourBit: 4-bit
4: FiveBit: 5-bit
5: SixBit: 6-bit
6: SevenBit: 7-bit
7: EightBit: 8-bit
8: NineBit: 9-bit
9: TenBit: 10-bit
10: ElevenBit: 11-bit
11: TwelveBit: 12-bit
12: ThirteenBit: 13-bit
13: FourteenBit: 14-bit
14: FifteenBit: 15-bit
15: SixteenBit: 16-bit

FRXTH

Bit 12: FIFO reception threshold.

Allowed values:
0: Half: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)
1: Quarter: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)

LDMA_RX

Bit 13: Last DMA transfer for reception.

Allowed values:
0: Even: Number of data to transfer for receive is even
1: Odd: Number of data to transfer for receive is odd

LDMA_TX

Bit 14: Last DMA transfer for transmission.

Allowed values:
0: Even: Number of data to transfer for transmit is even
1: Odd: Number of data to transfer for transmit is odd

SR

status register

Offset: 0x8, size: 16, reset: 0x00000002, access: Unspecified

11/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTLVL
r 		FRLVL
r 		FRE
r 		BSY
r 		OVR
r 		MODF
r 		CRCERR
rw 		UDR
r 		CHSIDE
r 		TXE
r 		RXNE
r
Toggle fields

RXNE

Bit 0: Receive buffer not empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXE

Bit 1: Transmit buffer empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

CHSIDE

Bit 2: Channel side.

Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received

UDR

Bit 3: Underrun flag.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

CRCERR

Bit 4: CRC error flag.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

MODF

Bit 5: Mode fault.

Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred

OVR

Bit 6: Overrun flag.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

BSY

Bit 7: Busy flag.

Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy

FRE

Bit 8: Frame format error.

Allowed values:
0: NoError: No frame format error
1: Error: A frame format error occurred

FRLVL

Bits 9-10: FIFO reception level.

Allowed values:
0: Empty: Rx FIFO Empty
1: Quarter: Rx 1/4 FIFO
2: Half: Rx 1/2 FIFO
3: Full: Rx FIFO full

FTLVL

Bits 11-12: FIFO transmission level.

Allowed values:
0: Empty: Tx FIFO Empty
1: Quarter: Tx 1/4 FIFO
2: Half: Tx 1/2 FIFO
3: Full: Tx FIFO full

DR

data register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-15: Data register.

Allowed values: 0x0-0xffff

DR8

Direct 8-bit access to data register

Offset: 0xc, size: 8, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-7: Data register.

Allowed values: 0x0-0xff

CRCPR

CRC polynomial register

Offset: 0x10, size: 16, reset: 0x00000007, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0x0-0xffff

RXCRCR

RX CRC register

Offset: 0x14, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

Allowed values: 0x0-0xffff

TXCRCR

TX CRC register

Offset: 0x18, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

Allowed values: 0x0-0xffff

I2SCFGR

I2S configuration register

Offset: 0x1c, size: 16, reset: 0x00000000, access: read-write

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SMOD
rw 		I2SE
rw 		I2SCFG
rw 		PCMSYNC
rw 		I2SSTD
rw 		CKPOL
rw 		DATLEN
rw 		CHLEN
rw
Toggle fields

CHLEN

Bit 0: Channel length (number of bits per audio channel).

Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide

DATLEN

Bits 1-2: Data length to be transferred.

Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length

CKPOL

Bit 3: Steady state clock polarity.

Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level

I2SSTD

Bits 4-5: I2S standard selection.

Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard

PCMSYNC

Bit 7: PCM frame synchronization.

Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation

I2SCFG

Bits 8-9: I2S configuration mode.

Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive

I2SE

Bit 10: I2S Enable.

Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled

I2SMOD

Bit 11: I2S mode selection.

Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected

I2SPR

I2S prescaler register

Offset: 0x20, size: 16, reset: 0x00000010, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOE
rw 		ODD
rw 		I2SDIV
rw
Toggle fields

I2SDIV

Bits 0-7: I2S Linear prescaler.

Allowed values: 0x2-0xff

ODD

Bit 8: Odd factor for the prescaler.

Allowed values:
0: Even: Real divider value is I2SDIV * 2
1: Odd: Real divider value is (I2SDIV * 2) + 1

MCKOE

Bit 9: Master clock output enable.

Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled

SPI2

0x40003800: Serial peripheral interface/Inter-IC2

53/53 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) CR1
0x4 (16-bit) CR2
0x8 (16-bit) SR
0xc (16-bit) DR
0xc (8-bit) DR8
0x10 (16-bit) CRCPR
0x14 (16-bit) RXCRCR
0x18 (16-bit) TXCRCR
0x1c (16-bit) I2SCFGR
0x20 (16-bit) I2SPR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

14/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw 		BIDIOE
rw 		CRCEN
rw 		CRCNEXT
rw 		CRCL
rw 		RXONLY
rw 		SSM
rw 		SSI
rw 		LSBFIRST
rw 		SPE
rw 		BR
rw 		MSTR
rw 		CPOL
rw 		CPHA
rw
Toggle fields

CPHA

Bit 0: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 1: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

MSTR

Bit 2: Master selection.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

BR

Bits 3-5: Baud rate control.

Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256

SPE

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LSBFIRST

Bit 7: Frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SSI

Bit 8: Internal slave select.

Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored

SSM

Bit 9: Software slave management.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

RXONLY

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)

CRCL

Bit 11: CRC length.

Allowed values:
0: EightBit: 8-bit CRC length
1: SixteenBit: 16-bit CRC length

CRCNEXT

Bit 12: CRC transfer next.

Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register

CRCEN

Bit 13: Hardware CRC calculation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BIDIOE

Bit 14: Output enable in bidirectional mode.

Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)

BIDIMODE

Bit 15: Bidirectional data mode enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CR2

control register 2

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDMA_TX
rw 		LDMA_RX
rw 		FRXTH
rw 		DS
rw 		TXEIE
rw 		RXNEIE
rw 		ERRIE
rw 		FRF
rw 		NSSP
rw 		SSOE
rw 		TXDMAEN
rw 		RXDMAEN
rw
Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 1: Tx buffer DMA enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

SSOE

Bit 2: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

NSSP

Bit 3: NSS pulse management.

Allowed values:
0: NoPulse: No NSS pulse
1: PulseGenerated: NSS pulse generated

FRF

Bit 4: Frame format.

Allowed values:
0: Motorola: SPI Motorola mode
1: TI: SPI TI mode

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked

TXEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked

DS

Bits 8-11: Data size.

Allowed values:
3: FourBit: 4-bit
4: FiveBit: 5-bit
5: SixBit: 6-bit
6: SevenBit: 7-bit
7: EightBit: 8-bit
8: NineBit: 9-bit
9: TenBit: 10-bit
10: ElevenBit: 11-bit
11: TwelveBit: 12-bit
12: ThirteenBit: 13-bit
13: FourteenBit: 14-bit
14: FifteenBit: 15-bit
15: SixteenBit: 16-bit

FRXTH

Bit 12: FIFO reception threshold.

Allowed values:
0: Half: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)
1: Quarter: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)

LDMA_RX

Bit 13: Last DMA transfer for reception.

Allowed values:
0: Even: Number of data to transfer for receive is even
1: Odd: Number of data to transfer for receive is odd

LDMA_TX

Bit 14: Last DMA transfer for transmission.

Allowed values:
0: Even: Number of data to transfer for transmit is even
1: Odd: Number of data to transfer for transmit is odd

SR

status register

Offset: 0x8, size: 16, reset: 0x00000002, access: Unspecified

11/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTLVL
r 		FRLVL
r 		FRE
r 		BSY
r 		OVR
r 		MODF
r 		CRCERR
rw 		UDR
r 		CHSIDE
r 		TXE
r 		RXNE
r
Toggle fields

RXNE

Bit 0: Receive buffer not empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXE

Bit 1: Transmit buffer empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

CHSIDE

Bit 2: Channel side.

Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received

UDR

Bit 3: Underrun flag.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

CRCERR

Bit 4: CRC error flag.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

MODF

Bit 5: Mode fault.

Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred

OVR

Bit 6: Overrun flag.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

BSY

Bit 7: Busy flag.

Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy

FRE

Bit 8: Frame format error.

Allowed values:
0: NoError: No frame format error
1: Error: A frame format error occurred

FRLVL

Bits 9-10: FIFO reception level.

Allowed values:
0: Empty: Rx FIFO Empty
1: Quarter: Rx 1/4 FIFO
2: Half: Rx 1/2 FIFO
3: Full: Rx FIFO full

FTLVL

Bits 11-12: FIFO transmission level.

Allowed values:
0: Empty: Tx FIFO Empty
1: Quarter: Tx 1/4 FIFO
2: Half: Tx 1/2 FIFO
3: Full: Tx FIFO full

DR

data register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-15: Data register.

Allowed values: 0x0-0xffff

DR8

Direct 8-bit access to data register

Offset: 0xc, size: 8, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-7: Data register.

Allowed values: 0x0-0xff

CRCPR

CRC polynomial register

Offset: 0x10, size: 16, reset: 0x00000007, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0x0-0xffff

RXCRCR

RX CRC register

Offset: 0x14, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

Allowed values: 0x0-0xffff

TXCRCR

TX CRC register

Offset: 0x18, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

Allowed values: 0x0-0xffff

I2SCFGR

I2S configuration register

Offset: 0x1c, size: 16, reset: 0x00000000, access: read-write

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SMOD
rw 		I2SE
rw 		I2SCFG
rw 		PCMSYNC
rw 		I2SSTD
rw 		CKPOL
rw 		DATLEN
rw 		CHLEN
rw
Toggle fields

CHLEN

Bit 0: Channel length (number of bits per audio channel).

Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide

DATLEN

Bits 1-2: Data length to be transferred.

Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length

CKPOL

Bit 3: Steady state clock polarity.

Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level

I2SSTD

Bits 4-5: I2S standard selection.

Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard

PCMSYNC

Bit 7: PCM frame synchronization.

Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation

I2SCFG

Bits 8-9: I2S configuration mode.

Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive

I2SE

Bit 10: I2S Enable.

Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled

I2SMOD

Bit 11: I2S mode selection.

Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected

I2SPR

I2S prescaler register

Offset: 0x20, size: 16, reset: 0x00000010, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOE
rw 		ODD
rw 		I2SDIV
rw
Toggle fields

I2SDIV

Bits 0-7: I2S Linear prescaler.

Allowed values: 0x2-0xff

ODD

Bit 8: Odd factor for the prescaler.

Allowed values:
0: Even: Real divider value is I2SDIV * 2
1: Odd: Real divider value is (I2SDIV * 2) + 1

MCKOE

Bit 9: Master clock output enable.

Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled

SPI3

0x40003c00: Serial peripheral interface/Inter-IC2

53/53 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) CR1
0x4 (16-bit) CR2
0x8 (16-bit) SR
0xc (16-bit) DR
0xc (8-bit) DR8
0x10 (16-bit) CRCPR
0x14 (16-bit) RXCRCR
0x18 (16-bit) TXCRCR
0x1c (16-bit) I2SCFGR
0x20 (16-bit) I2SPR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

14/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw 		BIDIOE
rw 		CRCEN
rw 		CRCNEXT
rw 		CRCL
rw 		RXONLY
rw 		SSM
rw 		SSI
rw 		LSBFIRST
rw 		SPE
rw 		BR
rw 		MSTR
rw 		CPOL
rw 		CPHA
rw
Toggle fields

CPHA

Bit 0: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 1: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

MSTR

Bit 2: Master selection.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

BR

Bits 3-5: Baud rate control.

Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256

SPE

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LSBFIRST

Bit 7: Frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SSI

Bit 8: Internal slave select.

Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored

SSM

Bit 9: Software slave management.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

RXONLY

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)

CRCL

Bit 11: Data frame format.

Allowed values:
0: EightBit: 8-bit CRC length
1: SixteenBit: 16-bit CRC length

CRCNEXT

Bit 12: CRC transfer next.

Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register

CRCEN

Bit 13: Hardware CRC calculation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BIDIOE

Bit 14: Output enable in bidirectional mode.

Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)

BIDIMODE

Bit 15: Bidirectional data mode enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CR2

control register 2

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDMA_TX
rw 		LDMA_RX
rw 		FRXTH
rw 		DS
rw 		TXEIE
rw 		RXNEIE
rw 		ERRIE
rw 		FRF
rw 		NSSP
rw 		SSOE
rw 		TXDMAEN
rw 		RXDMAEN
rw
Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 1: Tx buffer DMA enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

SSOE

Bit 2: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

NSSP

Bit 3: NSS pulse management.

Allowed values:
0: NoPulse: No NSS pulse
1: PulseGenerated: NSS pulse generated

FRF

Bit 4: Frame format.

Allowed values:
0: Motorola: SPI Motorola mode
1: TI: SPI TI mode

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked

TXEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked

DS

Bits 8-11: Data size.

Allowed values:
3: FourBit: 4-bit
4: FiveBit: 5-bit
5: SixBit: 6-bit
6: SevenBit: 7-bit
7: EightBit: 8-bit
8: NineBit: 9-bit
9: TenBit: 10-bit
10: ElevenBit: 11-bit
11: TwelveBit: 12-bit
12: ThirteenBit: 13-bit
13: FourteenBit: 14-bit
14: FifteenBit: 15-bit
15: SixteenBit: 16-bit

FRXTH

Bit 12: FIFO reception threshold.

Allowed values:
0: Half: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)
1: Quarter: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)

LDMA_RX

Bit 13: Last DMA transfer for reception.

Allowed values:
0: Even: Number of data to transfer for receive is even
1: Odd: Number of data to transfer for receive is odd

LDMA_TX

Bit 14: Last DMA transfer for transmission.

Allowed values:
0: Even: Number of data to transfer for transmit is even
1: Odd: Number of data to transfer for transmit is odd

SR

status register

Offset: 0x8, size: 16, reset: 0x00000002, access: Unspecified

11/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTLVL
r 		FRLVL
r 		FRE
r 		BSY
r 		OVR
r 		MODF
r 		CRCERR
rw 		UDR
r 		CHSIDE
r 		TXE
r 		RXNE
r
Toggle fields

RXNE

Bit 0: Receive buffer not empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXE

Bit 1: Transmit buffer empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

CHSIDE

Bit 2: Channel side.

Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received

UDR

Bit 3: Underrun flag.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

CRCERR

Bit 4: CRC error flag.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

MODF

Bit 5: Mode fault.

Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred

OVR

Bit 6: Overrun flag.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

BSY

Bit 7: Busy flag.

Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy

FRE

Bit 8: Frame format error.

Allowed values:
0: NoError: No frame format error
1: Error: A frame format error occurred

FRLVL

Bits 9-10: FIFO reception level.

Allowed values:
0: Empty: Rx FIFO Empty
1: Quarter: Rx 1/4 FIFO
2: Half: Rx 1/2 FIFO
3: Full: Rx FIFO full

FTLVL

Bits 11-12: FIFO transmission level.

Allowed values:
0: Empty: Tx FIFO Empty
1: Quarter: Tx 1/4 FIFO
2: Half: Tx 1/2 FIFO
3: Full: Tx FIFO full

DR

data register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-15: Data register.

Allowed values: 0x0-0xffff

DR8

Direct 8-bit access to data register

Offset: 0xc, size: 8, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-7: Data register.

Allowed values: 0x0-0xff

CRCPR

CRC polynomial register

Offset: 0x10, size: 16, reset: 0x00000007, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0x0-0xffff

RXCRCR

RX CRC register

Offset: 0x14, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

Allowed values: 0x0-0xffff

TXCRCR

TX CRC register

Offset: 0x18, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

Allowed values: 0x0-0xffff

I2SCFGR

I2S configuration register

Offset: 0x1c, size: 16, reset: 0x00000000, access: read-write

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SMOD
rw 		I2SE
rw 		I2SCFG
rw 		PCMSYNC
rw 		I2SSTD
rw 		CKPOL
rw 		DATLEN
rw 		CHLEN
rw
Toggle fields

CHLEN

Bit 0: Channel length (number of bits per audio channel).

Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide

DATLEN

Bits 1-2: Data length to be transferred.

Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length

CKPOL

Bit 3: Steady state clock polarity.

Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level

I2SSTD

Bits 4-5: I2S standard selection.

Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard

PCMSYNC

Bit 7: PCM frame synchronization.

Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation

I2SCFG

Bits 8-9: I2S configuration mode.

Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive

I2SE

Bit 10: I2S Enable.

Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled

I2SMOD

Bit 11: I2S mode selection.

Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected

I2SPR

I2S prescaler register

Offset: 0x20, size: 16, reset: 0x00000010, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOE
rw 		ODD
rw 		I2SDIV
rw
Toggle fields

I2SDIV

Bits 0-7: I2S Linear prescaler.

Allowed values: 0x2-0xff

ODD

Bit 8: Odd factor for the prescaler.

Allowed values:
0: Even: Real divider value is I2SDIV * 2
1: Odd: Real divider value is (I2SDIV * 2) + 1

MCKOE

Bit 9: Master clock output enable.

Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled

STK

0xe000e010: SysTick timer

0/9 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CTRL
0x4 LOAD
0x8 VAL
0xc CALIB
Toggle registers

CTRL

SysTick control and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COUNTFLAG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLKSOURCE
rw 		TICKINT
rw 		ENABLE
rw
Toggle fields

ENABLE

Bit 0: Counter enable.

TICKINT

Bit 1: SysTick exception request enable.

CLKSOURCE

Bit 2: Clock source selection.

COUNTFLAG

Bit 16: COUNTFLAG.

LOAD

SysTick reload value register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RELOAD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RELOAD
rw
Toggle fields

RELOAD

Bits 0-23: RELOAD value.

VAL

SysTick current value register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CURRENT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURRENT
rw
Toggle fields

CURRENT

Bits 0-23: Current counter value.

CALIB

SysTick calibration value register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NOREF
rw 		SKEW
rw 		TENMS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TENMS
rw
Toggle fields

TENMS

Bits 0-23: Calibration value.

SKEW

Bit 30: SKEW flag: Indicates whether the TENMS value is exact.

NOREF

Bit 31: NOREF flag. Reads as zero.

SYSCFG

0x40010000: System configuration controller

53/53 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CFGR1
0x4 RCR
0x8 EXTICR1
0xc EXTICR2
0x10 EXTICR3
0x14 EXTICR4
0x18 CFGR2
0x50 CFGR3
Toggle registers

CFGR1

configuration register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

21/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FPU_IE5
rw 		FPU_IE4
rw 		FPU_IE3
rw 		FPU_IE2
rw 		FPU_IE1
rw 		FPU_IE0
rw 		ENCODER_MODE
rw 		I2C2_FMP
rw 		I2C1_FMP
rw 		I2C_PB9_FMP
rw 		I2C_PB8_FMP
rw 		I2C_PB7_FMP
rw 		I2C_PB6_FMP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC2_CH1_DMA_RMP
rw 		TIM7_DAC1_CH2_DMA_RMP
rw 		TIM6_DAC1_CH1_DMA_RMP
rw 		TIM17_DMA_RMP
rw 		TIM16_DMA_RMP
rw 		DAC_TRIG_RMP
rw 		TIM1_ITR3_RMP
rw 		MEM_MODE
rw
Toggle fields

MEM_MODE

Bits 0-1: Memory mapping selection bits.

Allowed values:
0: MainFlash: Main Flash memory mapped at 0x0000_0000
1: SystemFlash: System Flash memory mapped at 0x0000_0000
2: MainFlash2: Main Flash memory mapped at 0x0000_0000
3: SRAM: Embedded SRAM mapped at 0x0000_0000

TIM1_ITR3_RMP

Bit 6: Timer 1 ITR3 selection.

Allowed values:
0: NotRemapped: Not remapped
1: Remapped: TIM1_ITR3 = TIM17_OC

DAC_TRIG_RMP

Bit 7: DAC trigger remap (when TSEL = 001).

Allowed values:
0: NotRemapped: Not remapped
1: Remapped: DAC trigger is TIM3_TRGO

TIM16_DMA_RMP

Bit 11: TIM16 DMA request remapping bit.

Allowed values:
0: NotRemapped: TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3
1: Remapped: TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4

TIM17_DMA_RMP

Bit 12: TIM17 DMA request remapping bit.

Allowed values:
0: NotRemapped: TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1
1: Remapped: TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2

TIM6_DAC1_CH1_DMA_RMP

Bit 13: TIM6 and DAC1 DMA request remapping bit.

Allowed values:
0: NotRemapped: TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3
1: Remapped: TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3

TIM7_DAC1_CH2_DMA_RMP

Bit 14: TIM7 and DAC2 DMA request remapping bit.

Allowed values:
0: NotRemapped: Not remapped
1: Remapped: TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4

DAC2_CH1_DMA_RMP

Bit 15: DAC2 channel1 DMA remap.

Allowed values:
0: NotRemapped: Not remapped
1: Remapped: DAC2_CH1 DMA requests mapped on DMA1 channel 5

I2C_PB6_FMP

Bit 16: Fast Mode Plus (FM+) driving capability activation bits..

Allowed values:
0: Standard: PB6 pin operate in standard mode
1: FMP: I2C FM+ mode enabled on PB6 and the Speed control is bypassed

I2C_PB7_FMP

Bit 17: Fast Mode Plus (FM+) driving capability activation bits..

Allowed values:
0: Standard: PB7 pin operate in standard mode
1: FMP: I2C FM+ mode enabled on PB7 and the Speed control is bypassed

I2C_PB8_FMP

Bit 18: Fast Mode Plus (FM+) driving capability activation bits..

Allowed values:
0: Standard: PB8 pin operate in standard mode
1: FMP: I2C FM+ mode enabled on PB8 and the Speed control is bypassed

I2C_PB9_FMP

Bit 19: Fast Mode Plus (FM+) driving capability activation bits..

Allowed values:
0: Standard: PB9 pin operate in standard mode
1: FMP: I2C FM+ mode enabled on PB9 and the Speed control is bypassed

I2C1_FMP

Bit 20: I2C1 Fast Mode Plus.

Allowed values:
0: Standard: FM+ mode is controlled by I2C_Pxx_FMP bits only
1: FMP: FM+ mode is enabled on all I2C1 pins selected through selection through IOPORT control registers AF selection bits

I2C2_FMP

Bit 21: I2C2 Fast Mode Plus.

Allowed values:
0: Standard: FM+ mode is controlled by I2C_Pxx_FMP bits only
1: FMP: FM+ mode is enabled on all I2C2 pins selected through selection through IOPORT control registers AF selection bits

ENCODER_MODE

Bits 22-23: Encoder mode.

Allowed values:
0: NoRedirection: No redirection
1: MapTim2Tim15: TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
2: MapTim3Tim15: TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively

FPU_IE0

Bit 26: Invalid operation interrupt enable.

Allowed values:
0: Disabled: Invalid operation interrupt disable
1: Enabled: Invalid operation interrupt enable

FPU_IE1

Bit 27: Devide-by-zero interrupt enable.

Allowed values:
0: Disabled: Devide-by-zero interrupt disable
1: Enabled: Devide-by-zero interrupt enable

FPU_IE2

Bit 28: Underflow interrupt enable.

Allowed values:
0: Disabled: Underflow interrupt disable
1: Enabled: Underflow interrupt enable

FPU_IE3

Bit 29: Overflow interrupt enable.

Allowed values:
0: Disabled: Overflow interrupt disable
1: Enabled: Overflow interrupt enable

FPU_IE4

Bit 30: Input denormal interrupt enable.

Allowed values:
0: Disabled: Input denormal interrupt disable
1: Enabled: Input denormal interrupt enable

FPU_IE5

Bit 31: Inexact interrupt enable.

Allowed values:
0: Disabled: Inexact interrupt disable
1: Enabled: Inexact interrupt enable

RCR

CCM SRAM protection register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAGE3_WP
rw 		PAGE2_WP
rw 		PAGE1_WP
rw 		PAGE0_WP
rw
Toggle fields

PAGE0_WP

Bit 0: CCM SRAM page write protection bit.

Allowed values:
0: Disabled: Write protection of pagex is disabled
1: Enabled: Write protection of pagex is enabled

PAGE1_WP

Bit 1: CCM SRAM page write protection bit.

Allowed values:
0: Disabled: Write protection of pagex is disabled
1: Enabled: Write protection of pagex is enabled

PAGE2_WP

Bit 2: CCM SRAM page write protection bit.

Allowed values:
0: Disabled: Write protection of pagex is disabled
1: Enabled: Write protection of pagex is enabled

PAGE3_WP

Bit 3: CCM SRAM page write protection bit.

Allowed values:
0: Disabled: Write protection of pagex is disabled
1: Enabled: Write protection of pagex is enabled

EXTICR1

external interrupt configuration register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI3
rw 		EXTI2
rw 		EXTI1
rw 		EXTI0
rw
Toggle fields

EXTI0

Bits 0-3: EXTI 0 configuration bits.

Allowed values:
0: PA0: Select PA0 as the source input for the EXTI0 external interrupt
1: PB0: Select PB0 as the source input for the EXTI0 external interrupt
2: PC0: Select PC0 as the source input for the EXTI0 external interrupt
3: PD0: Select PD0 as the source input for the EXTI0 external interrupt
4: PE0: Select PE0 as the source input for the EXTI0 external interrupt
5: PF0: Select PF0 as the source input for the EXTI0 external interrupt

EXTI1

Bits 4-7: EXTI 1 configuration bits.

Allowed values:
0: PA1: Select PA1 as the source input for the EXTI1 external interrupt
1: PB1: Select PB1 as the source input for the EXTI1 external interrupt
2: PC1: Select PC1 as the source input for the EXTI1 external interrupt
3: PD1: Select PD1 as the source input for the EXTI1 external interrupt
4: PE1: Select PE1 as the source input for the EXTI1 external interrupt
5: PF1: Select PF1 as the source input for the EXTI1 external interrupt

EXTI2

Bits 8-11: EXTI 2 configuration bits.

Allowed values:
0: PA2: Select PA2 as the source input for the EXTI2 external interrupt
1: PB2: Select PB2 as the source input for the EXTI2 external interrupt
2: PC2: Select PC2 as the source input for the EXTI2 external interrupt
3: PD2: Select PD2 as the source input for the EXTI2 external interrupt
4: PE2: Select PE2 as the source input for the EXTI2 external interrupt
5: PF2: Select PF2 as the source input for the EXTI2 external interrupt

EXTI3

Bits 12-15: EXTI 3 configuration bits.

Allowed values:
0: PA3: Select PA3 as the source input for the EXTI3 external interrupt
1: PB3: Select PB3 as the source input for the EXTI3 external interrupt
2: PC3: Select PC3 as the source input for the EXTI3 external interrupt
3: PD3: Select PD3 as the source input for the EXTI3 external interrupt
4: PE3: Select PE3 as the source input for the EXTI3 external interrupt

EXTICR2

external interrupt configuration register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI7
rw 		EXTI6
rw 		EXTI5
rw 		EXTI4
rw
Toggle fields

EXTI4

Bits 0-3: EXTI 4 configuration bits.

Allowed values:
0: PA4: Select PA4 as the source input for the EXTI4 external interrupt
1: PB4: Select PB4 as the source input for the EXTI4 external interrupt
2: PC4: Select PC4 as the source input for the EXTI4 external interrupt
3: PD4: Select PD4 as the source input for the EXTI4 external interrupt
4: PE4: Select PE4 as the source input for the EXTI4 external interrupt
5: PF4: Select PF4 as the source input for the EXTI4 external interrupt

EXTI5

Bits 4-7: EXTI 5 configuration bits.

Allowed values:
0: PA5: Select PA5 as the source input for the EXTI5 external interrupt
1: PB5: Select PB5 as the source input for the EXTI5 external interrupt
2: PC5: Select PC5 as the source input for the EXTI5 external interrupt
3: PD5: Select PD5 as the source input for the EXTI5 external interrupt
4: PE5: Select PE5 as the source input for the EXTI5 external interrupt
5: PF5: Select PF5 as the source input for the EXTI5 external interrupt

EXTI6

Bits 8-11: EXTI 6 configuration bits.

Allowed values:
0: PA6: Select PA6 as the source input for the EXTI6 external interrupt
1: PB6: Select PB6 as the source input for the EXTI6 external interrupt
2: PC6: Select PC6 as the source input for the EXTI6 external interrupt
3: PD6: Select PD6 as the source input for the EXTI6 external interrupt
4: PE6: Select PE6 as the source input for the EXTI6 external interrupt
5: PF6: Select PF6 as the source input for the EXTI6 external interrupt

EXTI7

Bits 12-15: EXTI 7 configuration bits.

Allowed values:
0: PA7: Select PA7 as the source input for the EXTI7 external interrupt
1: PB7: Select PB7 as the source input for the EXTI7 external interrupt
2: PC7: Select PC7 as the source input for the EXTI7 external interrupt
3: PD7: Select PD7 as the source input for the EXTI7 external interrupt
4: PE7: Select PE7 as the source input for the EXTI7 external interrupt

EXTICR3

external interrupt configuration register 3

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI11
rw 		EXTI10
rw 		EXTI9
rw 		EXTI8
rw
Toggle fields

EXTI8

Bits 0-3: EXTI 8 configuration bits.

Allowed values:
0: PA8: Select PA8 as the source input for the EXTI8 external interrupt
1: PB8: Select PB8 as the source input for the EXTI8 external interrupt
2: PC8: Select PC8 as the source input for the EXTI8 external interrupt
3: PD8: Select PD8 as the source input for the EXTI8 external interrupt
4: PE8: Select PE8 as the source input for the EXTI8 external interrupt

EXTI9

Bits 4-7: EXTI 9 configuration bits.

Allowed values:
0: PA9: Select PA9 as the source input for the EXTI9 external interrupt
1: PB9: Select PB9 as the source input for the EXTI9 external interrupt
2: PC9: Select PC9 as the source input for the EXTI9 external interrupt
3: PD9: Select PD9 as the source input for the EXTI9 external interrupt
4: PE9: Select PE9 as the source input for the EXTI9 external interrupt
5: PF9: Select PF9 as the source input for the EXTI9 external interrupt

EXTI10

Bits 8-11: EXTI 10 configuration bits.

Allowed values:
0: PA10: Select PA10 as the source input for the EXTI10 external interrupt
1: PB10: Select PB10 as the source input for the EXTI10 external interrupt
2: PC10: Select PC10 as the source input for the EXTI10 external interrupt
3: PD10: Select PD10 as the source input for the EXTI10 external interrupt
4: PE10: Select PE10 as the source input for the EXTI10 external interrupt
5: PF10: Select PF10 as the source input for the EXTI10 external interrupt

EXTI11

Bits 12-15: EXTI 11 configuration bits.

Allowed values:
0: PA11: Select PA11 as the source input for the EXTI11 external interrupt
1: PB11: Select PB11 as the source input for the EXTI11 external interrupt
2: PC11: Select PC11 as the source input for the EXTI11 external interrupt
3: PD11: Select PD11 as the source input for the EXTI11 external interrupt
4: PE11: Select PE11 as the source input for the EXTI11 external interrupt

EXTICR4

external interrupt configuration register 4

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI15
rw 		EXTI14
rw 		EXTI13
rw 		EXTI12
rw
Toggle fields

EXTI12

Bits 0-3: EXTI 12 configuration bits.

Allowed values:
0: PA12: Select PA12 as the source input for the EXTI12 external interrupt
1: PB12: Select PB12 as the source input for the EXTI12 external interrupt
2: PC12: Select PC12 as the source input for the EXTI12 external interrupt
3: PD12: Select PD12 as the source input for the EXTI12 external interrupt
4: PE12: Select PE12 as the source input for the EXTI12 external interrupt

EXTI13

Bits 4-7: EXTI 13 configuration bits.

Allowed values:
0: PA13: Select PA13 as the source input for the EXTI13 external interrupt
1: PB13: Select PB13 as the source input for the EXTI13 external interrupt
2: PC13: Select PC13 as the source input for the EXTI13 external interrupt
3: PD13: Select PD13 as the source input for the EXTI13 external interrupt
4: PE13: Select PE13 as the source input for the EXTI13 external interrupt

EXTI14

Bits 8-11: EXTI 14 configuration bits.

Allowed values:
0: PA14: Select PA14 as the source input for the EXTI14 external interrupt
1: PB14: Select PB14 as the source input for the EXTI14 external interrupt
2: PC14: Select PC14 as the source input for the EXTI14 external interrupt
3: PD14: Select PD14 as the source input for the EXTI14 external interrupt
4: PE14: Select PE14 as the source input for the EXTI14 external interrupt

EXTI15

Bits 12-15: EXTI 15 configuration bits.

Allowed values:
0: PA15: Select PA15 as the source input for the EXTI15 external interrupt
1: PB15: Select PB15 as the source input for the EXTI15 external interrupt
2: PC15: Select PC15 as the source input for the EXTI15 external interrupt
3: PD15: Select PD15 as the source input for the EXTI15 external interrupt
4: PE15: Select PE15 as the source input for the EXTI15 external interrupt

CFGR2

configuration register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRAM_PEF
rw 		BYP_ADDR_PAR
rw 		PVD_LOCK
rw 		SRAM_PARITY_LOCK
rw 		LOCKUP_LOCK
rw
Toggle fields

LOCKUP_LOCK

Bit 0: Cortex-M0 LOCKUP bit enable bit.

Allowed values:
0: Disconnected: Cortex-M4 LOCKUP output disconnected from TIM1/15/16/17 Break inputs and HRTIM1 SYSFLT.
1: Connected: Cortex-M4 LOCKUP output connected to TIM1/15/16/17 and HRTIM1 SYSFLT Break inputs

SRAM_PARITY_LOCK

Bit 1: SRAM parity lock bit.

Allowed values:
0: Disconnected: SRAM parity error signal disconnected from TIM1/15/16/17 and HRTIM1 SYSFLT Break inputs
1: Connected: SRAM parity error signal connected to TIM1/15/16/17 and HRTIM1 SYSFLT Break inputs

PVD_LOCK

Bit 2: PVD lock enable bit.

Allowed values:
0: Disconnected: PVD interrupt disconnected from TIM15/16/17 Break input
1: Connected: PVD interrupt connected to TIM15/16/17 Break input

BYP_ADDR_PAR

Bit 4: Bypass address bit 29 in parity calculation.

Allowed values:
0: NoBypass: The ramload operation is performed taking into consideration bit 29 of the address when the parity is calculated
1: Bypass: The ramload operation is performed without taking into consideration bit 29 of the address when the parity is calculated

SRAM_PEF

Bit 8: SRAM parity flag.

Allowed values:
0: NoParityError: No SRAM parity error detected
1: ParityErrorDetected: SRAM parity error detected

CFGR3

configuration register 3

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAC1_TRIG5_RMP
rw 		DAC1_TRIG3_RMP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADC2_DMA_RMP
rw 		I2C1_TX_DMA_RMP
rw 		I2C1_RX_DMA_RMP
rw 		SPI1_TX_DMA_RMP
rw 		SPI1_RX_DMA_RMP
rw
Toggle fields

SPI1_RX_DMA_RMP

Bits 0-1: SPI1_RX DMA remapping bit.

Allowed values:
0: MapDma1Ch3: SPI1_RX mapped on DMA1 CH2
1: MapDma1Ch5: SPI1_RX mapped on DMA1 CH4
2: MapDma1Ch7: SPI1_RX mapped on DMA1 CH6

SPI1_TX_DMA_RMP

Bits 2-3: SPI1_TX DMA remapping bit.

Allowed values:
0: MapDma1Ch3: SPI1_TX mapped on DMA1 CH3
1: MapDma1Ch5: SPI1_TX mapped on DMA1 CH5
2: MapDma1Ch7: SPI1_TX mapped on DMA1 CH7

I2C1_RX_DMA_RMP

Bits 4-5: I2C1_RX DMA remapping bit.

Allowed values:
0: MapDma1Ch7: I2C1_RX mapped on DMA1 CH7
1: MapDma1Ch3: I2C1_RX mapped on DMA1 CH3
2: MapDma1Ch5: I2C1_RX mapped on DMA1 CH5

I2C1_TX_DMA_RMP

Bits 6-7: I2C1_TX DMA remapping bit.

Allowed values:
0: MapDma1Ch6: I2C1_TX mapped on DMA1 CH6
1: MapDma1Ch2: I2C1_TX mapped on DMA1 CH2
2: MapDma1Ch4: I2C1_TX mapped on DMA1 CH4

ADC2_DMA_RMP

Bits 8-9: ADC2 DMA remapping bit.

Allowed values:
0: MapDma2: ADC2 mapped on DMA2
2: MapDma1Ch2: ADC2 mapped on DMA1 channel 2
3: MapDma1Ch4: ADC2 mapped on DMA1 channel 4

DAC1_TRIG3_RMP

Bit 16: DAC1_CH1 / DAC1_CH2 Trigger remap.

Allowed values:
0: Tim15: DAC trigger is TIM15_TRGO
1: HrTim1: DAC trigger is HRTIM1_DAC1_TRIG1

DAC1_TRIG5_RMP

Bit 17: DAC1_CH1 / DAC1_CH2 Trigger remap.

Allowed values:
0: NotRemapped: Not remapped
1: Remapped: DAC trigger is HRTIM1_DAC1_TRIG2

TIM1

0x40012c00: Advanced timer

107/168 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR[1]
0x38 CCR[2]
0x3c CCR[3]
0x40 CCR[4]
0x44 BDTR
0x48 DCR
0x4c DMAR
0x54 CCMR3_Output
0x58 CCR5
0x5c CCR6
0x60 OR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

12/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMS2
rw 		OIS[6]
rw 		OIS[5]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS[4]
rw 		OIS[3]N
rw 		OIS[3]
rw 		OIS[2]N
rw 		OIS[2]
rw 		OIS[1]N
rw 		OIS[1]
rw 		TI1S
rw 		MMS
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

OIS[1]

Bit 8: Output Idle state (OC1 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[1]N

Bit 9: Output Idle state (OC1N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[2]

Bit 10: Output Idle state (OC2 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[2]N

Bit 11: Output Idle state (OC2N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[3]

Bit 12: Output Idle state (OC3 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[3]N

Bit 13: Output Idle state (OC3N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[4]

Bit 14: Output Idle state (OC4 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[5]

Bit 16: Output Idle state (OC5 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[6]

Bit 18: Output Idle state (OC6 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

MMS2

Bits 20-23: Master mode selection 2.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

7/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMS3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		OCCS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

OCCS

Bit 3: OCREF clear selection.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

SMS3

Bit 16: Slave mode selection bit 3.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

12/15 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		COMDE
rw 		CC[4]DE
rw 		CC[3]DE
rw 		CC[2]DE
rw 		CC[1]DE
rw 		UDE
rw 		BIE
rw 		TIE
rw 		COMIE
rw 		CC[4]IE
rw 		CC[3]IE
rw 		CC[2]IE
rw 		CC[1]IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

COMIE

Bit 5: COM interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
C6IF
rw 		C5IF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]OF
rw 		CC[3]OF
rw 		CC[2]OF
rw 		CC[1]OF
rw 		B2IF
rw 		BIF
rw 		TIF
rw 		COMIF
rw 		CC[4]IF
rw 		CC[3]IF
rw 		CC[2]IF
rw 		CC[1]IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

BIF

Bit 7: Break interrupt flag.

B2IF

Bit 8: Break 2 interrupt flag.

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

C5IF

Bit 16: Capture/Compare 5 interrupt flag.

C6IF

Bit 17: Capture/Compare 6 interrupt flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

6/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2G
w 		BG
w 		TG
w 		COMG
w 		CC[4]G
w 		CC[3]G
w 		CC[2]G
w 		CC[1]G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

BG

Bit 7: Break generation.

B2G

Bit 8: Break 2 generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw 		IC[2]PSC
rw 		CC[2]S
rw 		IC[1]F
rw 		IC[1]PSC
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

8/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[2]M_3
rw 		OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]CE
rw 		OC[2]M
rw 		OC[2]PE
rw 		OC[2]FE
rw 		CC[2]S
rw 		OC[1]CE
rw 		OC[1]M
rw 		OC[1]PE
rw 		OC[1]FE
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[2]M_3

Bit 24: Output compare 2 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[4]F
rw 		IC[4]PSC
rw 		CC[4]S
rw 		IC[3]F
rw 		IC[3]PSC
rw 		CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0x0-0x3

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values: 0x0-0xf

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0x0-0x3

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values: 0x0-0xf

CCMR2_Output

capture/compare mode register (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

8/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[4]M_3
rw 		OC[3]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[4]CE
rw 		OC[4]M
rw 		OC[4]PE
rw 		OC[4]FE
rw 		CC[4]S
rw 		OC[3]CE
rw 		OC[3]M
rw 		OC[3]PE
rw 		OC[3]FE
rw 		CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

OC[3]M_3

Bit 16: Output compare 3 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[4]M_3

Bit 24: Output compare 4 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC[6]P
rw 		CC[6]E
rw 		CC[5]P
rw 		CC[5]E
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]NP
rw 		CC[4]P
rw 		CC[4]E
rw 		CC[3]NP
rw 		CC[3]NE
rw 		CC[3]P
rw 		CC[3]E
rw 		CC[2]NP
rw 		CC[2]NE
rw 		CC[2]P
rw 		CC[2]E
rw 		CC[1]NP
rw 		CC[1]NE
rw 		CC[1]P
rw 		CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[1]NE

Bit 2: Capture/Compare 1 complementary output enable.

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

CC[2]NE

Bit 6: Capture/Compare 2 complementary output enable.

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CC[3]E

Bit 8: Capture/Compare 3 output enable.

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

CC[3]NE

Bit 10: Capture/Compare 3 complementary output enable.

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

CC[4]E

Bit 12: Capture/Compare 4 output enable.

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

CC[4]NP

Bit 15: Capture/Compare 4 output Polarity.

CC[5]E

Bit 16: Capture/Compare 5 output enable.

CC[5]P

Bit 17: Capture/Compare 5 output Polarity.

CC[6]E

Bit 20: Capture/Compare 6 output enable.

CC[6]P

Bit 21: Capture/Compare 6 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

Allowed values: 0x0-0xffff

UIFCPY

Bit 31: UIF copy.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-15: Repetition counter value.

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

10/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BK2P
rw 		BK2E
rw 		BK2F
rw 		BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

Allowed values: 0x0-0xff

LOCK

Bits 8-9: Lock configuration.

Allowed values:
0: Off: No bit is write protected
1: Level1: Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
2: Level2: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
3: Level3: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written

OSSI

Bit 10: Off-state selection for Idle mode.

Allowed values:
0: Disabled: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are forced to idle level

OSSR

Bit 11: Off-state selection for Run mode.

Allowed values:
0: Disabled: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are enabled with their inactive level

BKE

Bit 12: Break enable.

Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x disabled

BKP

Bit 13: Break polarity.

Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high

AOE

Bit 14: Automatic output enable.

Allowed values:
0: Manual: MOE can be set only by software
1: Automatic: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)

MOE

Bit 15: Main output enable.

Allowed values:
0: DisabledIdle: OC/OCN are disabled or forced idle depending on OSSI
1: Enabled: OC/OCN are enabled if CCxE/CCxNE are set

BKF

Bits 16-19: Break filter.

BK2F

Bits 20-23: Break 2 filter.

BK2E

Bit 24: Break 2 enable.

Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x disabled

BK2P

Bit 25: Break 2 polarity.

Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

CCMR3_Output

capture/compare mode register 3 (output mode)

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

4/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[6]M_3
rw 		OC[5]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[6]CE
rw 		OC[6]M
rw 		OC[6]PE
rw 		OC[6]FE
rw 		OC[5]CE
rw 		OC[5]M
rw 		OC[5]PE
rw 		OC[5]FE
rw
Toggle fields

OC[5]FE

Bit 2: Output compare 5 fast enable.

OC[5]PE

Bit 3: Output compare 5 preload enable.

OC[5]M

Bits 4-6: Output compare 5 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[5]CE

Bit 7: Output compare 5 clear enable.

OC[6]FE

Bit 10: Output compare 6 fast enable.

OC[6]PE

Bit 11: Output compare 6 preload enable.

OC[6]M

Bits 12-14: Output compare 6 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[6]CE

Bit 15: Output compare 6 clear enable.

OC[5]M_3

Bit 16: Output compare 5 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[6]M_3

Bit 24: Output compare 6 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCR5

capture/compare register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GC5C3
rw 		GC5C2
rw 		GC5C1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

GC5C1

Bit 29: Group Channel 5 and Channel 1.

GC5C2

Bit 30: Group Channel 5 and Channel 2.

GC5C3

Bit 31: Group Channel 5 and Channel 3.

CCR6

capture/compare register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

OR

option registers

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIM1_ETR_ADC4_RMP
rw 		TIM1_ETR_ADC1_RMP
rw
Toggle fields

TIM1_ETR_ADC1_RMP

Bits 0-1: TIM1_ETR_ADC1 remapping capability.

TIM1_ETR_ADC4_RMP

Bits 2-3: TIM1_ETR_ADC4 remapping capability.

TIM15

0x40014000: General purpose timers

15/86 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR[1]
0x38 CCR[2]
0x44 BDTR
0x48 DCR
0x4c DMAR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

6/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS2
rw 		OIS1N
rw 		OIS1
rw 		TI1S
rw 		MMS
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

OIS2

Bit 10: Output Idle state 2.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMS_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

SMS_3

Bit 16: Slave mode selection bit 3.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		COMDE
rw 		CC[2]DE
rw 		CC[1]DE
rw 		UDE
rw 		BIE
rw 		TIE
rw 		COMIE
rw 		CC[2]IE
rw 		CC[1]IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[2]OF
rw 		CC[1]OF
rw 		BIF
rw 		TIF
rw 		COMIF
rw 		CC[2]IF
rw 		CC[1]IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

BIF

Bit 7: Break interrupt flag.

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

1/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w 		TG
w 		COMG
w 		CC[2]G
w 		CC[1]G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

CC[2]G

Bit 2: Capture/compare 2 generation.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw 		IC[2]PSC
rw 		CC[2]S
rw 		IC[1]F
rw 		IC[1]PSC
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

IC[2]F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[2]M_3
rw 		OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]M
rw 		OC[2]PE
rw 		OC[2]FE
rw 		CC[2]S
rw 		OC[1]M
rw 		OC[1]PE
rw 		OC[1]FE
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / Reserved
7: PwmMode2: Inversely to PwmMode1 / Reserved

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

OC[2]FE

Bit 10: Output compare 2 fast enable.

OC[2]PE

Bit 11: Output compare 2 preload enable.

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / Reserved
7: PwmMode2: Inversely to PwmMode1 / Reserved

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[2]M_3

Bit 24: Output compare 2 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[2]NP
rw 		CC[2]P
rw 		CC[2]E
rw 		CC[1]NP
rw 		CC[1]NE
rw 		CC[1]P
rw 		CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[1]NE

Bit 2: Capture/Compare 1 complementary output enable.

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

UIFCPY

Bit 31: UIF copy.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition counter value.

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKF

Bits 16-19: Break filter.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

TIM16

0x40014400: General-purpose-timers

21/62 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR[1]
0x44 BDTR
0x48 DCR
0x4c DMAR
0x50 OR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

6/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS1N
rw 		OIS1
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

Allowed values:
0: NotPreloaded: CCxE, CCxNE and OCxM bits are not preloaded
1: Preloaded: CCxE, CCxNE and OCxM bits are preloaded

CCUS

Bit 2: Capture/compare control update selection.

Allowed values:
0: Default: Capture/compare are updated only by setting the COMG bit
1: WithRisingEdge: Capture/compare are updated by setting the COMG bit or when an rising edge occurs on TRGI

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

OIS1

Bit 8: Output Idle state 1.

Allowed values:
0: Reset: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
1: Set: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0

OIS1N

Bit 9: Output Idle state 1.

Allowed values:
0: Reset: OC1N=0 after a dead-time when MOE=0
1: Set: OC1N=1 after a dead-time when MOE=0

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

5/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		COMDE
rw 		CC[1]DE
rw 		UDE
rw 		BIE
rw 		TIE
rw 		COMIE
rw 		CC[1]IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CC1 interrupt disabled
1: Enabled: CC1 interrupt enabled

COMIE

Bit 5: COM interrupt enable.

Allowed values:
0: Disabled: COM interrupt disabled
1: Enabled: COM interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

BIE

Bit 7: Break interrupt enable.

Allowed values:
0: Disabled: Break interrupt disabled
1: Enabled: Break interrupt enabled

UDE

Bit 8: Update DMA request enable.

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CC1 DMA request disabled
1: Enabled: CC1 DMA request enabled

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]OF
rw 		BIF
rw 		TIF
rw 		COMIF
rw 		CC[1]IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

BIF

Bit 7: Break interrupt flag.

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

1/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w 		TG
w 		COMG
w 		CC[1]G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[1]F
rw 		IC[1]PSC
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[1]M
rw 		OC[1]PE
rw 		OC[1]FE
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]NP
rw 		CC[1]NE
rw 		CC[1]P
rw 		CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[1]NE

Bit 2: Capture/Compare 1 complementary output enable.

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition counter value.

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKF

Bits 16-19: Break filter.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

OR

option register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

Toggle fields

TIM17

0x40014800: General purpose timer

12/62 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR[1]
0x44 BDTR
0x48 DCR
0x4c DMAR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

6/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS1N
rw 		OIS1
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		COMDE
rw 		CC[1]DE
rw 		UDE
rw 		BIE
rw 		TIE
rw 		COMIE
rw 		CC[1]IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]OF
rw 		BIF
rw 		TIF
rw 		COMIF
rw 		CC[1]IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

BIF

Bit 7: Break interrupt flag.

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

1/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w 		TG
w 		COMG
w 		CC[1]G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[1]F
rw 		IC[1]PSC
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[1]M
rw 		OC[1]PE
rw 		OC[1]FE
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]NP
rw 		CC[1]NE
rw 		CC[1]P
rw 		CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[1]NE

Bit 2: Capture/Compare 1 complementary output enable.

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition counter value.

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKF

Bits 16-19: Break filter.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

TIM2

0x40000000: General purpose timer

81/107 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR[1]
0x38 CCR[2]
0x3c CCR[3]
0x40 CCR[4]
0x48 DCR
0x4c DMAR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw 		MMS
rw 		CCDS
rw
Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

7/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMS_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		OCCS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

OCCS

Bit 3: OCREF clear selection.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

SMS_3

Bit 16: Slave mode selection bit3.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		CC[4]DE
rw 		CC[3]DE
rw 		CC[2]DE
rw 		CC[1]DE
rw 		UDE
rw 		TIE
rw 		CC[4]IE
rw 		CC[3]IE
rw 		CC[2]IE
rw 		CC[1]IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]OF
rw 		CC[3]OF
rw 		CC[2]OF
rw 		CC[1]OF
rw 		TIF
rw 		CC[4]IF
rw 		CC[3]IF
rw 		CC[2]IF
rw 		CC[1]IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w 		CC[4]G
w 		CC[3]G
w 		CC[2]G
w 		CC[1]G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw 		IC[2]PSC
rw 		CC[2]S
rw 		IC[1]F
rw 		IC[1]PSC
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

8/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[2]M_3
rw 		OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]CE
rw 		OC[2]M
rw 		OC[2]PE
rw 		OC[2]FE
rw 		CC[2]S
rw 		OC[1]CE
rw 		OC[1]M
rw 		OC[1]PE
rw 		OC[1]FE
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[2]M_3

Bit 24: Output compare 2 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[4]F
rw 		IC[4]PSC
rw 		CC[4]S
rw 		IC[3]F
rw 		IC[3]PSC
rw 		CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0x0-0x3

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values: 0x0-0xf

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0x0-0x3

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values: 0x0-0xf

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

8/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[4]M_3
rw 		OC[3]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[4]CE
rw 		OC[4]M
rw 		OC[4]PE
rw 		OC[4]FE
rw 		CC[4]S
rw 		OC[3]CE
rw 		OC[3]M
rw 		OC[3]PE
rw 		OC[3]FE
rw 		CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

OC[3]M_3

Bit 16: Output compare 3 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[4]M_3

Bit 24: Output compare 4 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]NP
rw 		CC[4]P
rw 		CC[4]E
rw 		CC[3]NP
rw 		CC[3]P
rw 		CC[3]E
rw 		CC[2]NP
rw 		CC[2]P
rw 		CC[2]E
rw 		CC[1]NP
rw 		CC[1]P
rw 		CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CC[3]E

Bit 8: Capture/Compare 3 output enable.

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

CC[4]E

Bit 12: Capture/Compare 4 output enable.

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

CC[4]NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-31: Low counter value.

Allowed values: 0x0-0xffffffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-31: Low Auto-reload value.

Allowed values: 0x0-0xffffffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

TIM3

0x40000400: General purpose timer

81/104 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR[1]
0x38 CCR[2]
0x3c CCR[3]
0x40 CCR[4]
0x48 DCR
0x4c DMAR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw 		MMS
rw 		CCDS
rw
Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		CC[4]DE
rw 		CC[3]DE
rw 		CC[2]DE
rw 		CC[1]DE
rw 		UDE
rw 		TIE
rw 		CC[4]IE
rw 		CC[3]IE
rw 		CC[2]IE
rw 		CC[1]IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]OF
rw 		CC[3]OF
rw 		CC[2]OF
rw 		CC[1]OF
rw 		TIF
rw 		CC[4]IF
rw 		CC[3]IF
rw 		CC[2]IF
rw 		CC[1]IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w 		CC[4]G
w 		CC[3]G
w 		CC[2]G
w 		CC[1]G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw 		IC[2]PSC
rw 		CC[2]S
rw 		IC[1]F
rw 		IC[1]PSC
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

8/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[2]M_3
rw 		OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]CE
rw 		OC[2]M
rw 		OC[2]PE
rw 		OC[2]FE
rw 		CC[2]S
rw 		OC[1]CE
rw 		OC[1]M
rw 		OC[1]PE
rw 		OC[1]FE
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[2]M_3

Bit 24: Output compare 2 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[4]F
rw 		IC[4]PSC
rw 		CC[4]S
rw 		IC[3]F
rw 		IC[3]PSC
rw 		CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0x0-0x3

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values: 0x0-0xf

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0x0-0x3

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values: 0x0-0xf

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

8/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[4]M_3
rw 		OC[3]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[4]CE
rw 		OC[4]M
rw 		OC[4]PE
rw 		OC[4]FE
rw 		CC[4]S
rw 		OC[3]CE
rw 		OC[3]M
rw 		OC[3]PE
rw 		OC[3]FE
rw 		CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

OC[3]M_3

Bit 16: Output compare 3 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[4]M_3

Bit 24: Output compare 4 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]NP
rw 		CC[4]P
rw 		CC[4]E
rw 		CC[3]NP
rw 		CC[3]P
rw 		CC[3]E
rw 		CC[2]NP
rw 		CC[2]P
rw 		CC[2]E
rw 		CC[1]NP
rw 		CC[1]P
rw 		CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CC[3]E

Bit 8: Capture/Compare 3 output enable.

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

CC[4]E

Bit 12: Capture/Compare 4 output enable.

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

CC[4]NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

Allowed values: 0x0-0xffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

TIM6

0x40001000: Basic timers

14/15 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x24 CNT
0x28 PSC
0x2c ARR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

5/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle fields

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: Use UG bit from TIMx_EGR register
1: Enable: Use CNT bit from TIMx_CEN register
2: Update: Use the update event

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: Low counter value.

Allowed values: 0x0-0xffff

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Low Auto-reload value.

Allowed values: 0x0-0xffff

TIM7

0x40001400: Basic timers

14/15 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x24 CNT
0x28 PSC
0x2c ARR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

5/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle fields

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: Use UG bit from TIMx_EGR register
1: Enable: Use CNT bit from TIMx_CEN register
2: Update: Use the update event

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: Low counter value.

Allowed values: 0x0-0xffff

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Low Auto-reload value.

Allowed values: 0x0-0xffff

TSC

0x40024000: Touch sensing controller

14/170 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 IER
0x8 ICR
0xc ISR
0x10 IOHCR
0x18 IOASCR
0x20 IOSCR
0x28 IOCCR
0x30 IOGCSR
0x34 IOG[1]CR
0x38 IOG[2]CR
0x3c IOG[3]CR
0x40 IOG[4]CR
0x44 IOG[5]CR
0x48 IOG[6]CR
0x4c IOG[7]CR
0x50 IOG[8]CR
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTPH
rw 		CTPL
rw 		SSD
rw 		SSE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSPSC
rw 		PGPSC
rw 		MCV
rw 		IODEF
rw 		SYNCPOL
rw 		AM
rw 		START
rw 		TSCE
rw
Toggle fields

TSCE

Bit 0: Touch sensing controller enable.

START

Bit 1: Start a new acquisition.

AM

Bit 2: Acquisition mode.

SYNCPOL

Bit 3: Synchronization pin polarity.

IODEF

Bit 4: I/O Default mode.

MCV

Bits 5-7: Max count value.

PGPSC

Bits 12-14: pulse generator prescaler.

SSPSC

Bit 15: Spread spectrum prescaler.

SSE

Bit 16: Spread spectrum enable.

SSD

Bits 17-23: Spread spectrum deviation.

CTPL

Bits 24-27: Charge transfer pulse low.

CTPH

Bits 28-31: Charge transfer pulse high.

IER

interrupt enable register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCEIE
rw 		EOAIE
rw
Toggle fields

EOAIE

Bit 0: End of acquisition interrupt enable.

MCEIE

Bit 1: Max count error interrupt enable.

ICR

interrupt clear register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCEIC
rw 		EOAIC
rw
Toggle fields

EOAIC

Bit 0: End of acquisition interrupt clear.

MCEIC

Bit 1: Max count error interrupt clear.

ISR

interrupt status register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCEF
rw 		EOAF
rw
Toggle fields

EOAF

Bit 0: End of acquisition flag.

MCEF

Bit 1: Max count error flag.

IOHCR

I/O hysteresis control register

Offset: 0x10, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
G8_IO4
rw 		G8_IO3
rw 		G8_IO2
rw 		G8_IO1
rw 		G7_IO4
rw 		G7_IO3
rw 		G7_IO2
rw 		G7_IO1
rw 		G6_IO4
rw 		G6_IO3
rw 		G6_IO2
rw 		G6_IO1
rw 		G5_IO4
rw 		G5_IO3
rw 		G5_IO2
rw 		G5_IO1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
G4_IO4
rw 		G4_IO3
rw 		G4_IO2
rw 		G4_IO1
rw 		G3_IO4
rw 		G3_IO3
rw 		G3_IO2
rw 		G3_IO1
rw 		G2_IO4
rw 		G2_IO3
rw 		G2_IO2
rw 		G2_IO1
rw 		G1_IO4
rw 		G1_IO3
rw 		G1_IO2
rw 		G1_IO1
rw
Toggle fields

G1_IO1

Bit 0: G1_IO1 Schmitt trigger hysteresis mode.

G1_IO2

Bit 1: G1_IO2 Schmitt trigger hysteresis mode.

G1_IO3

Bit 2: G1_IO3 Schmitt trigger hysteresis mode.

G1_IO4

Bit 3: G1_IO4 Schmitt trigger hysteresis mode.

G2_IO1

Bit 4: G2_IO1 Schmitt trigger hysteresis mode.

G2_IO2

Bit 5: G2_IO2 Schmitt trigger hysteresis mode.

G2_IO3

Bit 6: G2_IO3 Schmitt trigger hysteresis mode.

G2_IO4

Bit 7: G2_IO4 Schmitt trigger hysteresis mode.

G3_IO1

Bit 8: G3_IO1 Schmitt trigger hysteresis mode.

G3_IO2

Bit 9: G3_IO2 Schmitt trigger hysteresis mode.

G3_IO3

Bit 10: G3_IO3 Schmitt trigger hysteresis mode.

G3_IO4

Bit 11: G3_IO4 Schmitt trigger hysteresis mode.

G4_IO1

Bit 12: G4_IO1 Schmitt trigger hysteresis mode.

G4_IO2

Bit 13: G4_IO2 Schmitt trigger hysteresis mode.

G4_IO3

Bit 14: G4_IO3 Schmitt trigger hysteresis mode.

G4_IO4

Bit 15: G4_IO4 Schmitt trigger hysteresis mode.

G5_IO1

Bit 16: G5_IO1 Schmitt trigger hysteresis mode.

G5_IO2

Bit 17: G5_IO2 Schmitt trigger hysteresis mode.

G5_IO3

Bit 18: G5_IO3 Schmitt trigger hysteresis mode.

G5_IO4

Bit 19: G5_IO4 Schmitt trigger hysteresis mode.

G6_IO1

Bit 20: G6_IO1 Schmitt trigger hysteresis mode.

G6_IO2

Bit 21: G6_IO2 Schmitt trigger hysteresis mode.

G6_IO3

Bit 22: G6_IO3 Schmitt trigger hysteresis mode.

G6_IO4

Bit 23: G6_IO4 Schmitt trigger hysteresis mode.

G7_IO1

Bit 24: G7_IO1 Schmitt trigger hysteresis mode.

G7_IO2

Bit 25: G7_IO2 Schmitt trigger hysteresis mode.

G7_IO3

Bit 26: G7_IO3 Schmitt trigger hysteresis mode.

G7_IO4

Bit 27: G7_IO4 Schmitt trigger hysteresis mode.

G8_IO1

Bit 28: G8_IO1 Schmitt trigger hysteresis mode.

G8_IO2

Bit 29: G8_IO2 Schmitt trigger hysteresis mode.

G8_IO3

Bit 30: G8_IO3 Schmitt trigger hysteresis mode.

G8_IO4

Bit 31: G8_IO4 Schmitt trigger hysteresis mode.

IOASCR

I/O analog switch control register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
G8_IO4
rw 		G8_IO3
rw 		G8_IO2
rw 		G8_IO1
rw 		G7_IO4
rw 		G7_IO3
rw 		G7_IO2
rw 		G7_IO1
rw 		G6_IO4
rw 		G6_IO3
rw 		G6_IO2
rw 		G6_IO1
rw 		G5_IO4
rw 		G5_IO3
rw 		G5_IO2
rw 		G5_IO1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
G4_IO4
rw 		G4_IO3
rw 		G4_IO2
rw 		G4_IO1
rw 		G3_IO4
rw 		G3_IO3
rw 		G3_IO2
rw 		G3_IO1
rw 		G2_IO4
rw 		G2_IO3
rw 		G2_IO2
rw 		G2_IO1
rw 		G1_IO4
rw 		G1_IO3
rw 		G1_IO2
rw 		G1_IO1
rw
Toggle fields

G1_IO1

Bit 0: G1_IO1 analog switch enable.

G1_IO2

Bit 1: G1_IO2 analog switch enable.

G1_IO3

Bit 2: G1_IO3 analog switch enable.

G1_IO4

Bit 3: G1_IO4 analog switch enable.

G2_IO1

Bit 4: G2_IO1 analog switch enable.

G2_IO2

Bit 5: G2_IO2 analog switch enable.

G2_IO3

Bit 6: G2_IO3 analog switch enable.

G2_IO4

Bit 7: G2_IO4 analog switch enable.

G3_IO1

Bit 8: G3_IO1 analog switch enable.

G3_IO2

Bit 9: G3_IO2 analog switch enable.

G3_IO3

Bit 10: G3_IO3 analog switch enable.

G3_IO4

Bit 11: G3_IO4 analog switch enable.

G4_IO1

Bit 12: G4_IO1 analog switch enable.

G4_IO2

Bit 13: G4_IO2 analog switch enable.

G4_IO3

Bit 14: G4_IO3 analog switch enable.

G4_IO4

Bit 15: G4_IO4 analog switch enable.

G5_IO1

Bit 16: G5_IO1 analog switch enable.

G5_IO2

Bit 17: G5_IO2 analog switch enable.

G5_IO3

Bit 18: G5_IO3 analog switch enable.

G5_IO4

Bit 19: G5_IO4 analog switch enable.

G6_IO1

Bit 20: G6_IO1 analog switch enable.

G6_IO2

Bit 21: G6_IO2 analog switch enable.

G6_IO3

Bit 22: G6_IO3 analog switch enable.

G6_IO4

Bit 23: G6_IO4 analog switch enable.

G7_IO1

Bit 24: G7_IO1 analog switch enable.

G7_IO2

Bit 25: G7_IO2 analog switch enable.

G7_IO3

Bit 26: G7_IO3 analog switch enable.

G7_IO4

Bit 27: G7_IO4 analog switch enable.

G8_IO1

Bit 28: G8_IO1 analog switch enable.

G8_IO2

Bit 29: G8_IO2 analog switch enable.

G8_IO3

Bit 30: G8_IO3 analog switch enable.

G8_IO4

Bit 31: G8_IO4 analog switch enable.

IOSCR

I/O sampling control register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
G8_IO4
rw 		G8_IO3
rw 		G8_IO2
rw 		G8_IO1
rw 		G7_IO4
rw 		G7_IO3
rw 		G7_IO2
rw 		G7_IO1
rw 		G6_IO4
rw 		G6_IO3
rw 		G6_IO2
rw 		G6_IO1
rw 		G5_IO4
rw 		G5_IO3
rw 		G5_IO2
rw 		G5_IO1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
G4_IO4
rw 		G4_IO3
rw 		G4_IO2
rw 		G4_IO1
rw 		G3_IO4
rw 		G3_IO3
rw 		G3_IO2
rw 		G3_IO1
rw 		G2_IO4
rw 		G2_IO3
rw 		G2_IO2
rw 		G2_IO1
rw 		G1_IO4
rw 		G1_IO3
rw 		G1_IO2
rw 		G1_IO1
rw
Toggle fields

G1_IO1

Bit 0: G1_IO1 sampling mode.

G1_IO2

Bit 1: G1_IO2 sampling mode.

G1_IO3

Bit 2: G1_IO3 sampling mode.

G1_IO4

Bit 3: G1_IO4 sampling mode.

G2_IO1

Bit 4: G2_IO1 sampling mode.

G2_IO2

Bit 5: G2_IO2 sampling mode.

G2_IO3

Bit 6: G2_IO3 sampling mode.

G2_IO4

Bit 7: G2_IO4 sampling mode.

G3_IO1

Bit 8: G3_IO1 sampling mode.

G3_IO2

Bit 9: G3_IO2 sampling mode.

G3_IO3

Bit 10: G3_IO3 sampling mode.

G3_IO4

Bit 11: G3_IO4 sampling mode.

G4_IO1

Bit 12: G4_IO1 sampling mode.

G4_IO2

Bit 13: G4_IO2 sampling mode.

G4_IO3

Bit 14: G4_IO3 sampling mode.

G4_IO4

Bit 15: G4_IO4 sampling mode.

G5_IO1

Bit 16: G5_IO1 sampling mode.

G5_IO2

Bit 17: G5_IO2 sampling mode.

G5_IO3

Bit 18: G5_IO3 sampling mode.

G5_IO4

Bit 19: G5_IO4 sampling mode.

G6_IO1

Bit 20: G6_IO1 sampling mode.

G6_IO2

Bit 21: G6_IO2 sampling mode.

G6_IO3

Bit 22: G6_IO3 sampling mode.

G6_IO4

Bit 23: G6_IO4 sampling mode.

G7_IO1

Bit 24: G7_IO1 sampling mode.

G7_IO2

Bit 25: G7_IO2 sampling mode.

G7_IO3

Bit 26: G7_IO3 sampling mode.

G7_IO4

Bit 27: G7_IO4 sampling mode.

G8_IO1

Bit 28: G8_IO1 sampling mode.

G8_IO2

Bit 29: G8_IO2 sampling mode.

G8_IO3

Bit 30: G8_IO3 sampling mode.

G8_IO4

Bit 31: G8_IO4 sampling mode.

IOCCR

I/O channel control register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
G8_IO4
rw 		G8_IO3
rw 		G8_IO2
rw 		G8_IO1
rw 		G7_IO4
rw 		G7_IO3
rw 		G7_IO2
rw 		G7_IO1
rw 		G6_IO4
rw 		G6_IO3
rw 		G6_IO2
rw 		G6_IO1
rw 		G5_IO4
rw 		G5_IO3
rw 		G5_IO2
rw 		G5_IO1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
G4_IO4
rw 		G4_IO3
rw 		G4_IO2
rw 		G4_IO1
rw 		G3_IO4
rw 		G3_IO3
rw 		G3_IO2
rw 		G3_IO1
rw 		G2_IO4
rw 		G2_IO3
rw 		G2_IO2
rw 		G2_IO1
rw 		G1_IO4
rw 		G1_IO3
rw 		G1_IO2
rw 		G1_IO1
rw
Toggle fields

G1_IO1

Bit 0: G1_IO1 channel mode.

G1_IO2

Bit 1: G1_IO2 channel mode.

G1_IO3

Bit 2: G1_IO3 channel mode.

G1_IO4

Bit 3: G1_IO4 channel mode.

G2_IO1

Bit 4: G2_IO1 channel mode.

G2_IO2

Bit 5: G2_IO2 channel mode.

G2_IO3

Bit 6: G2_IO3 channel mode.

G2_IO4

Bit 7: G2_IO4 channel mode.

G3_IO1

Bit 8: G3_IO1 channel mode.

G3_IO2

Bit 9: G3_IO2 channel mode.

G3_IO3

Bit 10: G3_IO3 channel mode.

G3_IO4

Bit 11: G3_IO4 channel mode.

G4_IO1

Bit 12: G4_IO1 channel mode.

G4_IO2

Bit 13: G4_IO2 channel mode.

G4_IO3

Bit 14: G4_IO3 channel mode.

G4_IO4

Bit 15: G4_IO4 channel mode.

G5_IO1

Bit 16: G5_IO1 channel mode.

G5_IO2

Bit 17: G5_IO2 channel mode.

G5_IO3

Bit 18: G5_IO3 channel mode.

G5_IO4

Bit 19: G5_IO4 channel mode.

G6_IO1

Bit 20: G6_IO1 channel mode.

G6_IO2

Bit 21: G6_IO2 channel mode.

G6_IO3

Bit 22: G6_IO3 channel mode.

G6_IO4

Bit 23: G6_IO4 channel mode.

G7_IO1

Bit 24: G7_IO1 channel mode.

G7_IO2

Bit 25: G7_IO2 channel mode.

G7_IO3

Bit 26: G7_IO3 channel mode.

G7_IO4

Bit 27: G7_IO4 channel mode.

G8_IO1

Bit 28: G8_IO1 channel mode.

G8_IO2

Bit 29: G8_IO2 channel mode.

G8_IO3

Bit 30: G8_IO3 channel mode.

G8_IO4

Bit 31: G8_IO4 channel mode.

IOGCSR

I/O group control status register

Offset: 0x30, size: 32, reset: 0x00000000, access: Unspecified

6/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
G8S
rw 		G7S
rw 		G6S
r 		G5S
r 		G4S
r 		G3S
r 		G2S
r 		G1S
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
G8E
rw 		G7E
rw 		G6E
rw 		G5E
rw 		G4E
rw 		G3E
rw 		G2E
rw 		G1E
rw
Toggle fields

G1E

Bit 0: Analog I/O group x enable.

G2E

Bit 1: Analog I/O group x enable.

G3E

Bit 2: Analog I/O group x enable.

G4E

Bit 3: Analog I/O group x enable.

G5E

Bit 4: Analog I/O group x enable.

G6E

Bit 5: Analog I/O group x enable.

G7E

Bit 6: Analog I/O group x enable.

G8E

Bit 7: Analog I/O group x enable.

G1S

Bit 16: Analog I/O group x status.

G2S

Bit 17: Analog I/O group x status.

G3S

Bit 18: Analog I/O group x status.

G4S

Bit 19: Analog I/O group x status.

G5S

Bit 20: Analog I/O group x status.

G6S

Bit 21: Analog I/O group x status.

G7S

Bit 22: Analog I/O group x status.

G8S

Bit 23: Analog I/O group x status.

IOG[1]CR

I/O group x counter register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG[2]CR

I/O group x counter register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG[3]CR

I/O group x counter register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG[4]CR

I/O group x counter register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG[5]CR

I/O group x counter register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG[6]CR

I/O group x counter register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG[7]CR

I/O group x counter register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG[8]CR

I/O group x counter register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

USART1

0x40013800: Universal synchronous asynchronous receiver-transmitter

103/103 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EOBIE
rw 		RTOIE
rw 		DEAT
rw 		DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle fields

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8

DEDT

Bits 16-20: Driver Enable deassertion time.

Allowed values: 0x0-0x1f

DEAT

Bits 21-25: Driver Enable assertion time.

Allowed values: 0x0-0x1f

RTOIE

Bit 26: Receiver timeout interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register

EOBIE

Bit 27: End of Block interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw 		RTOEN
rw 		ABRMOD
rw 		ABREN
rw 		MSBFIRST
rw 		DATAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADDM7
rw
Toggle fields

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

LBDL

Bit 5: LIN break detection length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register

LBCL

Bit 8: Last bit clock pulse.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ABREN

Bit 20: Auto baud rate enable.

Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled

ABRMOD

Bits 21-22: Auto baud rate mode.

Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable.

Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0x0-0xff

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUFIE
rw 		WUS
rw 		SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

IREN

Bit 1: IrDA mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: IrDA low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

OVRDIS

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

SCARCNT

Bits 17-19: Smartcard auto-retry count.

Allowed values: 0x0-0x7

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: mantissa of USARTDIV.

Allowed values: 0x0-0xffff

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

Allowed values: 0x0-0xff

GT

Bits 8-15: Guard time value.

Allowed values: 0x0-0xff

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw 		RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

Allowed values: 0x0-0xffffff

BLEN

Bits 24-31: Block Length.

Allowed values: 0x0-0xff

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
rw 		RXFRQ
rw 		MMRQ
rw 		SBKRQ
rw 		ABRRQ
rw
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: Transmit data flush request.

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: Parity error.

FE

Bit 1: Framing error.

NF

Bit 2: Noise detected flag.

ORE

Bit 3: Overrun error.

IDLE

Bit 4: Idle line detected.

RXNE

Bit 5: Read data register not empty.

TC

Bit 6: Transmission complete.

TXE

Bit 7: Transmit data register empty.

LBDF

Bit 8: LIN break detection flag.

CTSIF

Bit 9: CTS interrupt flag.

CTS

Bit 10: CTS flag.

RTOF

Bit 11: Receiver timeout.

EOBF

Bit 12: End of block flag.

ABRE

Bit 14: Auto baud rate error.

ABRF

Bit 15: Auto baud rate flag.

BUSY

Bit 16: Busy flag.

CMF

Bit 17: character match flag.

SBKF

Bit 18: Send break flag.

RWU

Bit 19: Receiver wakeup from Mute mode.

WUF

Bit 20: Wakeup from Stop mode flag.

TEACK

Bit 21: Transmit enable acknowledge flag.

REACK

Bit 22: Receive enable acknowledge flag.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
rw 		CMCF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOBCF
rw 		RTOCF
rw 		CTSCF
rw 		LBDCF
rw 		TCCF
rw 		IDLECF
rw 		ORECF
rw 		NCF
rw 		FECF
rw 		PECF
rw
Toggle fields

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

LBDCF

Bit 8: LIN break detection clear flag.

Allowed values:
1: Clear: Clears the LBDF flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

RTOCF

Bit 11: Receiver timeout clear flag.

Allowed values:
1: Clear: Clears the RTOF flag in the ISR register

EOBCF

Bit 12: End of timeout clear flag.

Allowed values:
1: Clear: Clears the EOBF flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

Allowed values: 0x0-0x1ff

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

Allowed values: 0x0-0x1ff

USART2

0x40004400: Universal synchronous asynchronous receiver-transmitter

103/103 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EOBIE
rw 		RTOIE
rw 		DEAT
rw 		DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle fields

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8

DEDT

Bits 16-20: Driver Enable deassertion time.

Allowed values: 0x0-0x1f

DEAT

Bits 21-25: Driver Enable assertion time.

Allowed values: 0x0-0x1f

RTOIE

Bit 26: Receiver timeout interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register

EOBIE

Bit 27: End of Block interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw 		RTOEN
rw 		ABRMOD
rw 		ABREN
rw 		MSBFIRST
rw 		DATAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADDM7
rw
Toggle fields

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

LBDL

Bit 5: LIN break detection length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register

LBCL

Bit 8: Last bit clock pulse.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ABREN

Bit 20: Auto baud rate enable.

Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled

ABRMOD

Bits 21-22: Auto baud rate mode.

Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable.

Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0x0-0xff

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUFIE
rw 		WUS
rw 		SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

IREN

Bit 1: IrDA mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: IrDA low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

OVRDIS

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

SCARCNT

Bits 17-19: Smartcard auto-retry count.

Allowed values: 0x0-0x7

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: mantissa of USARTDIV.

Allowed values: 0x0-0xffff

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

Allowed values: 0x0-0xff

GT

Bits 8-15: Guard time value.

Allowed values: 0x0-0xff

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw 		RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

Allowed values: 0x0-0xffffff

BLEN

Bits 24-31: Block Length.

Allowed values: 0x0-0xff

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
rw 		RXFRQ
rw 		MMRQ
rw 		SBKRQ
rw 		ABRRQ
rw
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: Transmit data flush request.

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: Parity error.

FE

Bit 1: Framing error.

NF

Bit 2: Noise detected flag.

ORE

Bit 3: Overrun error.

IDLE

Bit 4: Idle line detected.

RXNE

Bit 5: Read data register not empty.

TC

Bit 6: Transmission complete.

TXE

Bit 7: Transmit data register empty.

LBDF

Bit 8: LIN break detection flag.

CTSIF

Bit 9: CTS interrupt flag.

CTS

Bit 10: CTS flag.

RTOF

Bit 11: Receiver timeout.

EOBF

Bit 12: End of block flag.

ABRE

Bit 14: Auto baud rate error.

ABRF

Bit 15: Auto baud rate flag.

BUSY

Bit 16: Busy flag.

CMF

Bit 17: character match flag.

SBKF

Bit 18: Send break flag.

RWU

Bit 19: Receiver wakeup from Mute mode.

WUF

Bit 20: Wakeup from Stop mode flag.

TEACK

Bit 21: Transmit enable acknowledge flag.

REACK

Bit 22: Receive enable acknowledge flag.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
rw 		CMCF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOBCF
rw 		RTOCF
rw 		CTSCF
rw 		LBDCF
rw 		TCCF
rw 		IDLECF
rw 		ORECF
rw 		NCF
rw 		FECF
rw 		PECF
rw
Toggle fields

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

LBDCF

Bit 8: LIN break detection clear flag.

Allowed values:
1: Clear: Clears the LBDF flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

RTOCF

Bit 11: Receiver timeout clear flag.

Allowed values:
1: Clear: Clears the RTOF flag in the ISR register

EOBCF

Bit 12: End of timeout clear flag.

Allowed values:
1: Clear: Clears the EOBF flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

Allowed values: 0x0-0x1ff

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

Allowed values: 0x0-0x1ff

USART3

0x40004800: Universal synchronous asynchronous receiver-transmitter

103/103 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EOBIE
rw 		RTOIE
rw 		DEAT
rw 		DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle fields

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8

DEDT

Bits 16-20: Driver Enable deassertion time.

Allowed values: 0x0-0x1f

DEAT

Bits 21-25: Driver Enable assertion time.

Allowed values: 0x0-0x1f

RTOIE

Bit 26: Receiver timeout interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register

EOBIE

Bit 27: End of Block interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw 		RTOEN
rw 		ABRMOD
rw 		ABREN
rw 		MSBFIRST
rw 		DATAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADDM7
rw
Toggle fields

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

LBDL

Bit 5: LIN break detection length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register

LBCL

Bit 8: Last bit clock pulse.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ABREN

Bit 20: Auto baud rate enable.

Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled

ABRMOD

Bits 21-22: Auto baud rate mode.

Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable.

Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0x0-0xff

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUFIE
rw 		WUS
rw 		SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

IREN

Bit 1: IrDA mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: IrDA low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

OVRDIS

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

SCARCNT

Bits 17-19: Smartcard auto-retry count.

Allowed values: 0x0-0x7

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: mantissa of USARTDIV.

Allowed values: 0x0-0xffff

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

Allowed values: 0x0-0xff

GT

Bits 8-15: Guard time value.

Allowed values: 0x0-0xff

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw 		RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

Allowed values: 0x0-0xffffff

BLEN

Bits 24-31: Block Length.

Allowed values: 0x0-0xff

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
rw 		RXFRQ
rw 		MMRQ
rw 		SBKRQ
rw 		ABRRQ
rw
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: Transmit data flush request.

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: Parity error.

FE

Bit 1: Framing error.

NF

Bit 2: Noise detected flag.

ORE

Bit 3: Overrun error.

IDLE

Bit 4: Idle line detected.

RXNE

Bit 5: Read data register not empty.

TC

Bit 6: Transmission complete.

TXE

Bit 7: Transmit data register empty.

LBDF

Bit 8: LIN break detection flag.

CTSIF

Bit 9: CTS interrupt flag.

CTS

Bit 10: CTS flag.

RTOF

Bit 11: Receiver timeout.

EOBF

Bit 12: End of block flag.

ABRE

Bit 14: Auto baud rate error.

ABRF

Bit 15: Auto baud rate flag.

BUSY

Bit 16: Busy flag.

CMF

Bit 17: character match flag.

SBKF

Bit 18: Send break flag.

RWU

Bit 19: Receiver wakeup from Mute mode.

WUF

Bit 20: Wakeup from Stop mode flag.

TEACK

Bit 21: Transmit enable acknowledge flag.

REACK

Bit 22: Receive enable acknowledge flag.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
rw 		CMCF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOBCF
rw 		RTOCF
rw 		CTSCF
rw 		LBDCF
rw 		TCCF
rw 		IDLECF
rw 		ORECF
rw 		NCF
rw 		FECF
rw 		PECF
rw
Toggle fields

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

LBDCF

Bit 8: LIN break detection clear flag.

Allowed values:
1: Clear: Clears the LBDF flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

RTOCF

Bit 11: Receiver timeout clear flag.

Allowed values:
1: Clear: Clears the RTOF flag in the ISR register

EOBCF

Bit 12: End of timeout clear flag.

Allowed values:
1: Clear: Clears the EOBF flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

Allowed values: 0x0-0x1ff

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

Allowed values: 0x0-0x1ff

WWDG

0x40002c00: Window watchdog

6/6 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 CFR
0x8 SR
Toggle registers

CR

Control register

Offset: 0x0, size: 32, reset: 0x0000007F, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDGA
rw 		T
rw
Toggle fields

T

Bits 0-6: 7-bit counter.

Allowed values: 0x0-0x7f

WDGA

Bit 7: Activation bit.

Allowed values:
0: Disabled: Watchdog disabled
1: Enabled: Watchdog enabled

CFR

Configuration register

Offset: 0x4, size: 32, reset: 0x0000007F, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWI
rw 		WDGTB
rw 		W
rw
Toggle fields

W

Bits 0-6: 7-bit window value.

Allowed values: 0x0-0x7f

WDGTB

Bits 7-8: Timer base.

Allowed values:
0: Div1: Counter clock (PCLK1 div 4096) div 1
1: Div2: Counter clock (PCLK1 div 4096) div 2
2: Div4: Counter clock (PCLK1 div 4096) div 4
3: Div8: Counter clock (PCLK1 div 4096) div 8

EWI

Bit 9: Early wakeup interrupt.

Allowed values:
1: Enable: interrupt occurs whenever the counter reaches the value 0x40

SR

Status register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWIF
rw
Toggle fields

EWIF

Bit 0: Early wakeup interrupt flag.

Allowed values:
0: Finished: The EWI Interrupt Service Routine has been serviced
1: Pending: The EWI Interrupt Service Routine has been triggered