STM32F411 Peripheral Coverage

ADC1

0x40012000: Analog-to-digital converter

84/84 fields covered.

Toggle register map

Offset	Name	30	29	27	26	25	24	23	22	21	20	19	17	15	14	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	SR																						OVR	STRT	JSTRT	JEOC	EOC	AWD
0x4	CR1				OVRIE	RES		AWDEN	JAWDEN					DISCNUM		JDISCEN	DISCEN	JAUTO	AWDSGL	SCAN	JEOCIE	AWDIE	EOCIE	AWDCH
0x8	CR2	SWSTART	EXTEN	EXTSEL					JSWSTART	JEXTEN		JEXTSEL					ALIGN	EOCS	DDS	DMA							CONT	ADON
0xc	SMPR1				SMP18			SMP17			SMP16		SMP15	SMP15	SMP14		SMP13			SMP12			SMP11			SMP10
0x10	SMPR2		SMP9		SMP8			SMP7			SMP6		SMP5	SMP5	SMP4		SMP3			SMP2			SMP1			SMP0
0x14	JOFR[1]																JOFFSET
0x18	JOFR[2]																JOFFSET
0x1c	JOFR[3]																JOFFSET
0x20	JOFR[4]																JOFFSET
0x24	HTR																HT
0x28	LTR																LT
0x2c	SQR1							L				SQ16		SQ16	SQ15				SQ14					SQ13
0x30	SQR2		SQ12				SQ11					SQ10		SQ10	SQ9				SQ8					SQ7
0x34	SQR3		SQ6				SQ5					SQ4		SQ4	SQ3				SQ2					SQ1
0x38	JSQR									JL		JSQ4		JSQ4	JSQ3				JSQ2					JSQ1
0x3c	JDR[1]													JDATA
0x40	JDR[2]													JDATA
0x44	JDR[3]													JDATA
0x48	JDR[4]													JDATA
0x4c	DR													DATA

Toggle registers

SR

status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										OVR rw	STRT rw	JSTRT rw	JEOC rw	EOC rw	AWD rw

Toggle fields

AWD

Bit 0: Analog watchdog flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

EOC

Bit 1: Regular channel end of conversion.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

JEOC

Bit 2: Injected channel end of conversion.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

JSTRT

Bit 3: Injected channel start flag.

Allowed values:
0: NotStarted: No injected channel conversion started
1: Started: Injected channel conversion has started

STRT

Bit 4: Regular channel start flag.

Allowed values:
0: NotStarted: No regular channel conversion started
1: Started: Regular channel conversion has started

OVR

Bit 5: Overrun.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

CR1

control register 1

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					OVRIE rw	RES rw		AWDEN rw	JAWDEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DISCNUM rw			JDISCEN rw	DISCEN rw	JAUTO rw	AWDSGL rw	SCAN rw	JEOCIE rw	AWDIE rw	EOCIE rw	AWDCH rw

Toggle fields

AWDCH

Bits 0-4: Analog watchdog channel select bits.

Allowed values: 0x0-0x12

EOCIE

Bit 5: Interrupt enable for EOC.

Allowed values:
0: Disabled: EOC interrupt disabled
1: Enabled: EOC interrupt enabled

AWDIE

Bit 6: Analog watchdog interrupt enable.

Allowed values:
0: Disabled: Analogue watchdog interrupt disabled
1: Enabled: Analogue watchdog interrupt enabled

JEOCIE

Bit 7: Interrupt enable for injected channels.

Allowed values:
0: Disabled: JEOC interrupt disabled
1: Enabled: JEOC interrupt enabled

SCAN

Bit 8: Scan mode.

Allowed values:
0: Disabled: Scan mode disabled
1: Enabled: Scan mode enabled

AWDSGL

Bit 9: Enable the watchdog on a single channel in scan mode.

Allowed values:
0: AllChannels: Analog watchdog enabled on all channels
1: SingleChannel: Analog watchdog enabled on a single channel

JAUTO

Bit 10: Automatic injected group conversion.

Allowed values:
0: Disabled: Automatic injected group conversion disabled
1: Enabled: Automatic injected group conversion enabled

DISCEN

Bit 11: Discontinuous mode on regular channels.

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

JDISCEN

Bit 12: Discontinuous mode on injected channels.

Allowed values:
0: Disabled: Discontinuous mode on injected channels disabled
1: Enabled: Discontinuous mode on injected channels enabled

DISCNUM

Bits 13-15: Discontinuous mode channel count.

Allowed values: 0x0-0x7

JAWDEN

Bit 22: Analog watchdog enable on injected channels.

Allowed values:
0: Disabled: Analog watchdog disabled on injected channels
1: Enabled: Analog watchdog enabled on injected channels

AWDEN

Bit 23: Analog watchdog enable on regular channels.

Allowed values:
0: Disabled: Analog watchdog disabled on regular channels
1: Enabled: Analog watchdog enabled on regular channels

RES

Bits 24-25: Resolution.

Allowed values:
0: TwelveBit: 12-bit (15 ADCCLK cycles)
1: TenBit: 10-bit (13 ADCCLK cycles)
2: EightBit: 8-bit (11 ADCCLK cycles)
3: SixBit: 6-bit (9 ADCCLK cycles)

OVRIE

Bit 26: Overrun interrupt enable.

Allowed values:
0: Disabled: Overrun interrupt disabled
1: Enabled: Overrun interrupt enabled

CR2

control register 2

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	SWSTART rw	EXTEN rw		EXTSEL rw					JSWSTART rw	JEXTEN rw		JEXTSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				ALIGN rw	EOCS rw	DDS rw	DMA rw							CONT rw	ADON rw

Toggle fields

ADON

Bit 0: A/D Converter ON / OFF.

Allowed values:
0: Disabled: Disable ADC conversion and go to power down mode
1: Enabled: Enable ADC

CONT

Bit 1: Continuous conversion.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

DMA

Bit 8: Direct memory access mode (for single ADC mode).

Allowed values:
0: Disabled: DMA mode disabled
1: Enabled: DMA mode enabled

DDS

Bit 9: DMA disable selection (for single ADC mode).

Allowed values:
0: Single: No new DMA request is issued after the last transfer
1: Continuous: DMA requests are issued as long as data are converted and DMA=1

EOCS

Bit 10: End of conversion selection.

Allowed values:
0: EachSequence: The EOC bit is set at the end of each sequence of regular conversions
1: EachConversion: The EOC bit is set at the end of each regular conversion

ALIGN

Bit 11: Data alignment.

Allowed values:
0: Right: Right alignment
1: Left: Left alignment

JEXTSEL

Bits 16-19: External event select for injected group.

Allowed values:
0: TIM1CC4: Timer 1 CC4 event
1: TIM1TRGO: Timer 1 TRGO event
2: TIM2CC1: Timer 2 CC1 event
3: TIM2TRGO: Timer 2 TRGO event
4: TIM3CC2: Timer 3 CC2 event
5: TIM3CC4: Timer 3 CC4 event
6: TIM4CC1: Timer 4 CC1 event
7: TIM4CC2: Timer 4 CC2 event
8: TIM4CC3: Timer 4 CC3 event
9: TIM4TRGO: Timer 4 TRGO event
10: TIM5CC4: Timer 5 CC4 event
11: TIM5TRGO: Timer 5 TRGO event
15: EXTI15: EXTI line 15

JEXTEN

Bits 20-21: External trigger enable for injected channels.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

JSWSTART

Bit 22: Start conversion of injected channels.

Allowed values:
1: Start: Starts conversion of injected channels

EXTSEL

Bits 24-27: External event select for regular group.

Allowed values:
0: TIM1CC1: Timer 1 CC1 event
1: TIM1CC2: Timer 1 CC2 event
2: TIM1CC3: Timer 1 CC3 event
3: TIM2CC2: Timer 2 CC2 event
4: TIM2CC3: Timer 2 CC3 event
5: TIM2CC4: Timer 2 CC4 event
6: TIM2TRGO: Timer 2 TRGO event
7: TIM3CC1: Timer 3 CC1 event
8: TIM3TRGO: Timer 3 TRGO event
9: TIM4CC4: Timer 4 CC4 event
10: TIM5CC1: Timer 5 CC1 event
11: TIM5CC2: Timer 5 CC2 event
12: TIM5CC3: Timer 5 CC3 event
15: EXTI11: EXTI line 11

EXTEN

Bits 28-29: External trigger enable for regular channels.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

SWSTART

Bit 30: Start conversion of regular channels.

Allowed values:
1: Start: Starts conversion of regular channels

SMPR1

sample time register 1

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					SMP18 rw			SMP17 rw			SMP16 rw			SMP15 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SMP15 rw	SMP14 rw			SMP13 rw			SMP12 rw			SMP11 rw			SMP10 rw

Toggle fields

SMP10

Bits 0-2: Channel 10 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP11

Bits 3-5: Channel 11 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP12

Bits 6-8: Channel 12 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP13

Bits 9-11: Channel 13 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP14

Bits 12-14: Channel 14 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP15

Bits 15-17: Channel 15 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP16

Bits 18-20: Channel 16 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP17

Bits 21-23: Channel 17 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP18

Bits 24-26: Channel 18 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMPR2

sample time register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		SMP9 rw			SMP8 rw			SMP7 rw			SMP6 rw			SMP5 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SMP5 rw	SMP4 rw			SMP3 rw			SMP2 rw			SMP1 rw			SMP0 rw

Toggle fields

SMP0

Bits 0-2: Channel 0 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP1

Bits 3-5: Channel 1 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP2

Bits 6-8: Channel 2 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP3

Bits 9-11: Channel 3 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP4

Bits 12-14: Channel 4 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP5

Bits 15-17: Channel 5 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP6

Bits 18-20: Channel 6 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP7

Bits 21-23: Channel 7 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP8

Bits 24-26: Channel 8 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP9

Bits 27-29: Channel 9 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

JOFR[1]

injected channel data offset register x

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				JOFFSET rw

Toggle fields

JOFFSET

Bits 0-11: Data offset for injected channel x.

Allowed values: 0x0-0xfff

JOFR[2]

injected channel data offset register x

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				JOFFSET rw

Toggle fields

JOFFSET

Bits 0-11: Data offset for injected channel x.

Allowed values: 0x0-0xfff

JOFR[3]

injected channel data offset register x

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				JOFFSET rw

Toggle fields

JOFFSET

Bits 0-11: Data offset for injected channel x.

Allowed values: 0x0-0xfff

JOFR[4]

injected channel data offset register x

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				JOFFSET rw

Toggle fields

JOFFSET

Bits 0-11: Data offset for injected channel x.

Allowed values: 0x0-0xfff

HTR

watchdog higher threshold register

Offset: 0x24, size: 32, reset: 0x00000FFF, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				HT rw

Toggle fields

HT

Bits 0-11: Analog watchdog higher threshold.

Allowed values: 0x0-0xfff

LTR

watchdog lower threshold register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				LT rw

Toggle fields

LT

Bits 0-11: Analog watchdog lower threshold.

Allowed values: 0x0-0xfff

SQR1

regular sequence register 1

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								L rw				SQ16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SQ16 rw	SQ15 rw					SQ14 rw					SQ13 rw

Toggle fields

SQ13

Bits 0-4: 13th conversion in regular sequence.

Allowed values: 0x0-0x12

SQ14

Bits 5-9: 14th conversion in regular sequence.

Allowed values: 0x0-0x12

SQ15

Bits 10-14: 15th conversion in regular sequence.

Allowed values: 0x0-0x12

SQ16

Bits 15-19: 16th conversion in regular sequence.

Allowed values: 0x0-0x12

L

Bits 20-23: Regular channel sequence length.

Allowed values: 0x0-0xf

SQR2

regular sequence register 2

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		SQ12 rw					SQ11 rw					SQ10 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SQ10 rw	SQ9 rw					SQ8 rw					SQ7 rw

Toggle fields

SQ7

Bits 0-4: 7th conversion in regular sequence.

Allowed values: 0x0-0x12

SQ8

Bits 5-9: 8th conversion in regular sequence.

Allowed values: 0x0-0x12

SQ9

Bits 10-14: 9th conversion in regular sequence.

Allowed values: 0x0-0x12

SQ10

Bits 15-19: 10th conversion in regular sequence.

Allowed values: 0x0-0x12

SQ11

Bits 20-24: 11th conversion in regular sequence.

Allowed values: 0x0-0x12

SQ12

Bits 25-29: 12th conversion in regular sequence.

Allowed values: 0x0-0x12

SQR3

regular sequence register 3

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		SQ6 rw					SQ5 rw					SQ4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SQ4 rw	SQ3 rw					SQ2 rw					SQ1 rw

Toggle fields

SQ1

Bits 0-4: 1st conversion in regular sequence.

Allowed values: 0x0-0x12

SQ2

Bits 5-9: 2nd conversion in regular sequence.

Allowed values: 0x0-0x12

SQ3

Bits 10-14: 3rd conversion in regular sequence.

Allowed values: 0x0-0x12

SQ4

Bits 15-19: 4th conversion in regular sequence.

Allowed values: 0x0-0x12

SQ5

Bits 20-24: 5th conversion in regular sequence.

Allowed values: 0x0-0x12

SQ6

Bits 25-29: 6th conversion in regular sequence.

Allowed values: 0x0-0x12

JSQR

injected sequence register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										JL rw		JSQ4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JSQ4 rw	JSQ3 rw					JSQ2 rw					JSQ1 rw

Toggle fields

JSQ1

Bits 0-4: 1st conversion in injected sequence.

Allowed values: 0x0-0x12

JSQ2

Bits 5-9: 2nd conversion in injected sequence.

Allowed values: 0x0-0x12

JSQ3

Bits 10-14: 3rd conversion in injected sequence.

Allowed values: 0x0-0x12

JSQ4

Bits 15-19: 4th conversion in injected sequence.

Allowed values: 0x0-0x12

JL

Bits 20-21: Injected sequence length.

Allowed values: 0x0-0x3

JDR[1]

injected data register x

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JDATA r

Toggle fields

JDATA

Bits 0-15: Injected data.

JDR[2]

injected data register x

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JDATA r

Toggle fields

JDATA

Bits 0-15: Injected data.

JDR[3]

injected data register x

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JDATA r

Toggle fields

JDATA

Bits 0-15: Injected data.

JDR[4]

injected data register x

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JDATA r

Toggle fields

JDATA

Bits 0-15: Injected data.

DR

regular data register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATA r

Toggle fields

DATA

Bits 0-15: Regular data.

ADC_Common

0x40012300: ADC common registers

3/3 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x4	CCR									TSVREFE	VBATE					ADCPRE

Toggle registers

CCR

ADC common control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								TSVREFE rw	VBATE rw					ADCPRE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

ADCPRE

Bits 16-17: ADC prescaler.

Allowed values:
0: Div2: PCLK2 divided by 2
1: Div4: PCLK2 divided by 4
2: Div6: PCLK2 divided by 6
3: Div8: PCLK2 divided by 8

VBATE

Bit 22: VBAT enable.

Allowed values:
0: Disabled: V_BAT channel disabled
1: Enabled: V_BAT channel enabled

TSVREFE

Bit 23: Temperature sensor and VREFINT enable.

Allowed values:
0: Disabled: Temperature sensor and V_REFINT channel disabled
1: Enabled: Temperature sensor and V_REFINT channel enabled

CRC

0x40023000: Cryptographic processor

3/3 fields covered.

Toggle register map

Offset	Name	31	15	7	0
0x0	DR	DR	DR
0x4	IDR			IDR
0x8	CR				RESET

Toggle registers

DR

Data register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR rw

Toggle fields

DR

Bits 0-31: Data Register.

Allowed values: 0x0-0xffffffff

IDR

Independent Data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IDR rw

Toggle fields

IDR

Bits 0-7: Independent Data register.

Allowed values: 0x0-0xff

CR

Control register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															RESET w

Toggle fields

RESET

Bit 0: Control regidter.

Allowed values:
1: Reset: Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF

DBGMCU

0xe0042000: Debug support

2/21 fields covered.

Toggle register map

Offset	Name	31	23	22	21	18	17	16	12	11	10	7	5	3	2	1	0
0x0	IDCODE	REV_ID								DEV_ID
0x4	CR											TRACE_MODE	TRACE_IOEN		DBG_STANDBY	DBG_STOP	DBG_SLEEP
0x8	APB1_FZ		DBG_I2C3SMBUS_TIMEOUT	DBG_I2C2_SMBUS_TIMEOUT	DBG_I2C1_SMBUS_TIMEOUT				DBG_IWDG_STOP	DBG_WWDG_STOP	DBG_RTC_Stop			DBG_TIM5_STOP	DBG_TIM4_STOP	DBG_TIM3_STOP	DBG_TIM2_STOP
0xc	APB2_FZ					DBG_TIM11_STOP	DBG_TIM10_STOP	DBG_TIM9_STOP									DBG_TIM1_STOP

Toggle registers

IDCODE

Offset: 0x0, size: 32, reset: 0x10006411, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
REV_ID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				DEV_ID r

Toggle fields

DEV_ID

Bits 0-11: DEV_ID.

REV_ID

Bits 16-31: REV_ID.

CR

Control Register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TRACE_MODE rw		TRACE_IOEN rw			DBG_STANDBY rw	DBG_STOP rw	DBG_SLEEP rw

Toggle fields

DBG_SLEEP

Bit 0: DBG_SLEEP.

DBG_STOP

Bit 1: DBG_STOP.

DBG_STANDBY

Bit 2: DBG_STANDBY.

TRACE_IOEN

Bit 5: TRACE_IOEN.

TRACE_MODE

Bits 6-7: TRACE_MODE.

APB1_FZ

Debug MCU APB1 Freeze registe

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								DBG_I2C3SMBUS_TIMEOUT rw	DBG_I2C2_SMBUS_TIMEOUT rw	DBG_I2C1_SMBUS_TIMEOUT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBG_IWDG_STOP rw	DBG_WWDG_STOP rw	DBG_RTC_Stop rw							DBG_TIM5_STOP rw	DBG_TIM4_STOP rw	DBG_TIM3_STOP rw	DBG_TIM2_STOP rw

Toggle fields

DBG_TIM2_STOP

Bit 0: DBG_TIM2_STOP.

DBG_TIM3_STOP

Bit 1: DBG_TIM3 _STOP.

DBG_TIM4_STOP

Bit 2: DBG_TIM4_STOP.

DBG_TIM5_STOP

Bit 3: DBG_TIM5_STOP.

DBG_RTC_Stop

Bit 10: RTC stopped when Core is halted.

DBG_WWDG_STOP

Bit 11: DBG_WWDG_STOP.

DBG_IWDG_STOP

Bit 12: DBG_IWDEG_STOP.

DBG_I2C1_SMBUS_TIMEOUT

Bit 21: DBG_J2C1_SMBUS_TIMEOUT.

DBG_I2C2_SMBUS_TIMEOUT

Bit 22: DBG_J2C2_SMBUS_TIMEOUT.

DBG_I2C3SMBUS_TIMEOUT

Bit 23: DBG_J2C3SMBUS_TIMEOUT.

APB2_FZ

Debug MCU APB2 Freeze registe

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													DBG_TIM11_STOP rw	DBG_TIM10_STOP rw	DBG_TIM9_STOP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															DBG_TIM1_STOP rw

Toggle fields

DBG_TIM1_STOP

Bit 0: TIM1 counter stopped when core is halted.

DBG_TIM9_STOP

Bit 16: TIM9 counter stopped when core is halted.

DBG_TIM10_STOP

Bit 17: TIM10 counter stopped when core is halted.

DBG_TIM11_STOP

Bit 18: TIM11 counter stopped when core is halted.

DMA1

0x40026000: DMA controller

272/296 fields covered.

Toggle register map

Offset	Name	31	27	26	25	24	22	21	20	19	18	17	16	15	14	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	LISR		TCIF3	HTIF3	TEIF3	DMEIF3	FEIF3	TCIF2	HTIF2	TEIF2	DMEIF2		FEIF2				TCIF1	HTIF1	TEIF1	DMEIF1		FEIF1	TCIF0	HTIF0	TEIF0	DMEIF0		FEIF0
0x4	HISR		TCIF7	HTIF7	TEIF7	DMEIF7	FEIF7	TCIF6	HTIF6	TEIF6	DMEIF6		FEIF6				TCIF5	HTIF5	TEIF5	DMEIF5		FEIF5	TCIF4	HTIF4	TEIF4	DMEIF4		FEIF4
0x8	LIFCR		CTCIF3	CHTIF3	CTEIF3	CDMEIF3	CFEIF3	CTCIF2	CHTIF2	CTEIF2	CDMEIF2		CFEIF2				CTCIF1	CHTIF1	CTEIF1	CDMEIF1		CFEIF1	CTCIF0	CHTIF0	CTEIF0	CDMEIF0		CFEIF0
0xc	HIFCR		CTCIF7	CHTIF7	CTEIF7	CDMEIF7	CFEIF7	CTCIF6	CHTIF6	CTEIF6	CDMEIF6		CFEIF6				CTCIF5	CHTIF5	CTEIF5	CDMEIF5		CFEIF5	CTCIF4	CHTIF4	CTEIF4	CDMEIF4		CFEIF4
0x10	CR [0]		CHSEL			MBURST	PBURST			CT	DBM	PL		PINCOS	MSIZE	PSIZE		MINC	PINC	CIRC	DIR		PFCTRL	TCIE	HTIE	TEIE	DMEIE	EN
0x14	NDTR [0]													NDT
0x18	PAR [0]	PA												PA
0x1c	M0AR [0]	M0A												M0A
0x20	M1AR [0]	M1A												M1A
0x24	FCR [0]																				FEIE		FS			DMDIS	FTH
0x28	CR [1]		CHSEL			MBURST	PBURST			CT	DBM	PL		PINCOS	MSIZE	PSIZE		MINC	PINC	CIRC	DIR		PFCTRL	TCIE	HTIE	TEIE	DMEIE	EN
0x2c	NDTR [1]													NDT
0x30	PAR [1]	PA												PA
0x34	M0AR [1]	M0A												M0A
0x38	M1AR [1]	M1A												M1A
0x3c	FCR [1]																				FEIE		FS			DMDIS	FTH
0x40	CR [2]		CHSEL			MBURST	PBURST			CT	DBM	PL		PINCOS	MSIZE	PSIZE		MINC	PINC	CIRC	DIR		PFCTRL	TCIE	HTIE	TEIE	DMEIE	EN
0x44	NDTR [2]													NDT
0x48	PAR [2]	PA												PA
0x4c	M0AR [2]	M0A												M0A
0x50	M1AR [2]	M1A												M1A
0x54	FCR [2]																				FEIE		FS			DMDIS	FTH
0x58	CR [3]		CHSEL			MBURST	PBURST			CT	DBM	PL		PINCOS	MSIZE	PSIZE		MINC	PINC	CIRC	DIR		PFCTRL	TCIE	HTIE	TEIE	DMEIE	EN
0x5c	NDTR [3]													NDT
0x60	PAR [3]	PA												PA
0x64	M0AR [3]	M0A												M0A
0x68	M1AR [3]	M1A												M1A
0x6c	FCR [3]																				FEIE		FS			DMDIS	FTH
0x70	CR [4]		CHSEL			MBURST	PBURST			CT	DBM	PL		PINCOS	MSIZE	PSIZE		MINC	PINC	CIRC	DIR		PFCTRL	TCIE	HTIE	TEIE	DMEIE	EN
0x74	NDTR [4]													NDT
0x78	PAR [4]	PA												PA
0x7c	M0AR [4]	M0A												M0A
0x80	M1AR [4]	M1A												M1A
0x84	FCR [4]																				FEIE		FS			DMDIS	FTH
0x88	CR [5]		CHSEL			MBURST	PBURST			CT	DBM	PL		PINCOS	MSIZE	PSIZE		MINC	PINC	CIRC	DIR		PFCTRL	TCIE	HTIE	TEIE	DMEIE	EN
0x8c	NDTR [5]													NDT
0x90	PAR [5]	PA												PA
0x94	M0AR [5]	M0A												M0A
0x98	M1AR [5]	M1A												M1A
0x9c	FCR [5]																				FEIE		FS			DMDIS	FTH
0xa0	CR [6]		CHSEL			MBURST	PBURST			CT	DBM	PL		PINCOS	MSIZE	PSIZE		MINC	PINC	CIRC	DIR		PFCTRL	TCIE	HTIE	TEIE	DMEIE	EN
0xa4	NDTR [6]													NDT
0xa8	PAR [6]	PA												PA
0xac	M0AR [6]	M0A												M0A
0xb0	M1AR [6]	M1A												M1A
0xb4	FCR [6]																				FEIE		FS			DMDIS	FTH
0xb8	CR [7]		CHSEL			MBURST	PBURST			CT	DBM	PL		PINCOS	MSIZE	PSIZE		MINC	PINC	CIRC	DIR		PFCTRL	TCIE	HTIE	TEIE	DMEIE	EN
0xbc	NDTR [7]													NDT
0xc0	PAR [7]	PA												PA
0xc4	M0AR [7]	M0A												M0A
0xc8	M1AR [7]	M1A												M1A
0xcc	FCR [7]																				FEIE		FS			DMDIS	FTH

Toggle registers

LISR

low interrupt status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

20/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TCIF3 r	HTIF3 r	TEIF3 r	DMEIF3 r		FEIF3 r	TCIF2 r	HTIF2 r	TEIF2 r	DMEIF2 r		FEIF2 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				TCIF1 r	HTIF1 r	TEIF1 r	DMEIF1 r		FEIF1 r	TCIF0 r	HTIF0 r	TEIF0 r	DMEIF0 r		FEIF0 r

Toggle fields

FEIF0

Bit 0: Stream x FIFO error interrupt flag (x=3..0).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF0

Bit 2: Stream x direct mode error interrupt flag (x=3..0).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF0

Bit 3: Stream x transfer error interrupt flag (x=3..0).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF0

Bit 4: Stream x half transfer interrupt flag (x=3..0).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF0

Bit 5: Stream x transfer complete interrupt flag (x = 3..0).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

FEIF1

Bit 6: Stream x FIFO error interrupt flag (x=3..0).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF1

Bit 8: Stream x direct mode error interrupt flag (x=3..0).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF1

Bit 9: Stream x transfer error interrupt flag (x=3..0).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF1

Bit 10: Stream x half transfer interrupt flag (x=3..0).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF1

Bit 11: Stream x transfer complete interrupt flag (x = 3..0).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

FEIF2

Bit 16: Stream x FIFO error interrupt flag (x=3..0).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF2

Bit 18: Stream x direct mode error interrupt flag (x=3..0).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF2

Bit 19: Stream x transfer error interrupt flag (x=3..0).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF2

Bit 20: Stream x half transfer interrupt flag (x=3..0).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF2

Bit 21: Stream x transfer complete interrupt flag (x = 3..0).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

FEIF3

Bit 22: Stream x FIFO error interrupt flag (x=3..0).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF3

Bit 24: Stream x direct mode error interrupt flag (x=3..0).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF3

Bit 25: Stream x transfer error interrupt flag (x=3..0).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF3

Bit 26: Stream x half transfer interrupt flag (x=3..0).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF3

Bit 27: Stream x transfer complete interrupt flag (x = 3..0).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

HISR

high interrupt status register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

20/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TCIF7 r	HTIF7 r	TEIF7 r	DMEIF7 r		FEIF7 r	TCIF6 r	HTIF6 r	TEIF6 r	DMEIF6 r		FEIF6 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				TCIF5 r	HTIF5 r	TEIF5 r	DMEIF5 r		FEIF5 r	TCIF4 r	HTIF4 r	TEIF4 r	DMEIF4 r		FEIF4 r

Toggle fields

FEIF4

Bit 0: Stream x FIFO error interrupt flag (x=7..4).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF4

Bit 2: Stream x direct mode error interrupt flag (x=7..4).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF4

Bit 3: Stream x transfer error interrupt flag (x=7..4).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF4

Bit 4: Stream x half transfer interrupt flag (x=7..4).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF4

Bit 5: Stream x transfer complete interrupt flag (x=7..4).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

FEIF5

Bit 6: Stream x FIFO error interrupt flag (x=7..4).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF5

Bit 8: Stream x direct mode error interrupt flag (x=7..4).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF5

Bit 9: Stream x transfer error interrupt flag (x=7..4).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF5

Bit 10: Stream x half transfer interrupt flag (x=7..4).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF5

Bit 11: Stream x transfer complete interrupt flag (x=7..4).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

FEIF6

Bit 16: Stream x FIFO error interrupt flag (x=7..4).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF6

Bit 18: Stream x direct mode error interrupt flag (x=7..4).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF6

Bit 19: Stream x transfer error interrupt flag (x=7..4).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF6

Bit 20: Stream x half transfer interrupt flag (x=7..4).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF6

Bit 21: Stream x transfer complete interrupt flag (x=7..4).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

FEIF7

Bit 22: Stream x FIFO error interrupt flag (x=7..4).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF7

Bit 24: Stream x direct mode error interrupt flag (x=7..4).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF7

Bit 25: Stream x transfer error interrupt flag (x=7..4).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF7

Bit 26: Stream x half transfer interrupt flag (x=7..4).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF7

Bit 27: Stream x transfer complete interrupt flag (x=7..4).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

LIFCR

low interrupt flag clear register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

20/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				CTCIF3 w	CHTIF3 w	CTEIF3 w	CDMEIF3 w		CFEIF3 w	CTCIF2 w	CHTIF2 w	CTEIF2 w	CDMEIF2 w		CFEIF2 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				CTCIF1 w	CHTIF1 w	CTEIF1 w	CDMEIF1 w		CFEIF1 w	CTCIF0 w	CHTIF0 w	CTEIF0 w	CDMEIF0 w		CFEIF0 w

Toggle fields

CFEIF0

Bit 0: Stream x clear FIFO error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF0

Bit 2: Stream x clear direct mode error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF0

Bit 3: Stream x clear transfer error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF0

Bit 4: Stream x clear half transfer interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF0

Bit 5: Stream x clear transfer complete interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CFEIF1

Bit 6: Stream x clear FIFO error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF1

Bit 8: Stream x clear direct mode error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF1

Bit 9: Stream x clear transfer error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF1

Bit 10: Stream x clear half transfer interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF1

Bit 11: Stream x clear transfer complete interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CFEIF2

Bit 16: Stream x clear FIFO error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF2

Bit 18: Stream x clear direct mode error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF2

Bit 19: Stream x clear transfer error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF2

Bit 20: Stream x clear half transfer interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF2

Bit 21: Stream x clear transfer complete interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CFEIF3

Bit 22: Stream x clear FIFO error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF3

Bit 24: Stream x clear direct mode error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF3

Bit 25: Stream x clear transfer error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF3

Bit 26: Stream x clear half transfer interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF3

Bit 27: Stream x clear transfer complete interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

HIFCR

high interrupt flag clear register

Offset: 0xc, size: 32, reset: 0x00000000, access: write-only

20/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				CTCIF7 w	CHTIF7 w	CTEIF7 w	CDMEIF7 w		CFEIF7 w	CTCIF6 w	CHTIF6 w	CTEIF6 w	CDMEIF6 w		CFEIF6 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				CTCIF5 w	CHTIF5 w	CTEIF5 w	CDMEIF5 w		CFEIF5 w	CTCIF4 w	CHTIF4 w	CTEIF4 w	CDMEIF4 w		CFEIF4 w

Toggle fields

CFEIF4

Bit 0: Stream x clear FIFO error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF4

Bit 2: Stream x clear direct mode error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF4

Bit 3: Stream x clear transfer error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF4

Bit 4: Stream x clear half transfer interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF4

Bit 5: Stream x clear transfer complete interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CFEIF5

Bit 6: Stream x clear FIFO error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF5

Bit 8: Stream x clear direct mode error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF5

Bit 9: Stream x clear transfer error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF5

Bit 10: Stream x clear half transfer interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF5

Bit 11: Stream x clear transfer complete interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CFEIF6

Bit 16: Stream x clear FIFO error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF6

Bit 18: Stream x clear direct mode error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF6

Bit 19: Stream x clear transfer error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF6

Bit 20: Stream x clear half transfer interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF6

Bit 21: Stream x clear transfer complete interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CFEIF7

Bit 22: Stream x clear FIFO error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF7

Bit 24: Stream x clear direct mode error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF7

Bit 25: Stream x clear transfer error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF7

Bit 26: Stream x clear half transfer interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF7

Bit 27: Stream x clear transfer complete interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CR [0]

stream x configuration register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				CHSEL rw			MBURST rw		PBURST rw			CT rw	DBM rw	PL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PINCOS rw	MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw		PFCTRL rw	TCIE rw	HTIE rw	TEIE rw	DMEIE rw	EN rw

Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

DMEIE

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

TEIE

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

HTIE

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TCIE

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

PFCTRL

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

DIR

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

CIRC

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PINCOS

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

PL

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

DBM

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

PBURST

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

MBURST

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

CHSEL

Bits 25-27: Channel selection.

Allowed values: 0x0-0x7

NDTR [0]

stream x number of data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

PAR [0]

stream x peripheral address register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [0]

stream x memory 0 address register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
M0A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
M0A rw

Toggle fields

M0A

Bits 0-31: Memory 0 address.

M1AR [0]

stream x memory 1 address register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
M1A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
M1A rw

Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

FCR [0]

stream x FIFO control register

Offset: 0x24, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								FEIE rw		FS r			DMDIS rw	FTH rw

Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

DMDIS

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

FS

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

FEIE

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

CR [1]

stream x configuration register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				CHSEL rw			MBURST rw		PBURST rw			CT rw	DBM rw	PL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PINCOS rw	MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw		PFCTRL rw	TCIE rw	HTIE rw	TEIE rw	DMEIE rw	EN rw

Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

DMEIE

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

TEIE

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

HTIE

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TCIE

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

PFCTRL

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

DIR

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

CIRC

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PINCOS

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

PL

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

DBM

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

PBURST

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

MBURST

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

CHSEL

Bits 25-27: Channel selection.

Allowed values: 0x0-0x7

NDTR [1]

stream x number of data register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

PAR [1]

stream x peripheral address register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [1]

stream x memory 0 address register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
M0A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
M0A rw

Toggle fields

M0A

Bits 0-31: Memory 0 address.

M1AR [1]

stream x memory 1 address register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
M1A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
M1A rw

Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

FCR [1]

stream x FIFO control register

Offset: 0x3c, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								FEIE rw		FS r			DMDIS rw	FTH rw

Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

DMDIS

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

FS

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

FEIE

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

CR [2]

stream x configuration register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				CHSEL rw			MBURST rw		PBURST rw			CT rw	DBM rw	PL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PINCOS rw	MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw		PFCTRL rw	TCIE rw	HTIE rw	TEIE rw	DMEIE rw	EN rw

Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

DMEIE

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

TEIE

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

HTIE

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TCIE

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

PFCTRL

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

DIR

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

CIRC

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PINCOS

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

PL

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

DBM

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

PBURST

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

MBURST

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

CHSEL

Bits 25-27: Channel selection.

Allowed values: 0x0-0x7

NDTR [2]

stream x number of data register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

PAR [2]

stream x peripheral address register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [2]

stream x memory 0 address register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
M0A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
M0A rw

Toggle fields

M0A

Bits 0-31: Memory 0 address.

M1AR [2]

stream x memory 1 address register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
M1A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
M1A rw

Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

FCR [2]

stream x FIFO control register

Offset: 0x54, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								FEIE rw		FS r			DMDIS rw	FTH rw

Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

DMDIS

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

FS

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

FEIE

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

CR [3]

stream x configuration register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				CHSEL rw			MBURST rw		PBURST rw			CT rw	DBM rw	PL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PINCOS rw	MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw		PFCTRL rw	TCIE rw	HTIE rw	TEIE rw	DMEIE rw	EN rw

Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

DMEIE

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

TEIE

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

HTIE

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TCIE

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

PFCTRL

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

DIR

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

CIRC

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PINCOS

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

PL

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

DBM

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

PBURST

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

MBURST

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

CHSEL

Bits 25-27: Channel selection.

Allowed values: 0x0-0x7

NDTR [3]

stream x number of data register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

PAR [3]

stream x peripheral address register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [3]

stream x memory 0 address register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
M0A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
M0A rw

Toggle fields

M0A

Bits 0-31: Memory 0 address.

M1AR [3]

stream x memory 1 address register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
M1A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
M1A rw

Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

FCR [3]

stream x FIFO control register

Offset: 0x6c, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								FEIE rw		FS r			DMDIS rw	FTH rw

Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

DMDIS

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

FS

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

FEIE

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

CR [4]

stream x configuration register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				CHSEL rw			MBURST rw		PBURST rw			CT rw	DBM rw	PL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PINCOS rw	MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw		PFCTRL rw	TCIE rw	HTIE rw	TEIE rw	DMEIE rw	EN rw

Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

DMEIE

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

TEIE

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

HTIE

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TCIE

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

PFCTRL

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

DIR

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

CIRC

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PINCOS

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

PL

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

DBM

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

PBURST

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

MBURST

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

CHSEL

Bits 25-27: Channel selection.

Allowed values: 0x0-0x7

NDTR [4]

stream x number of data register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

PAR [4]

stream x peripheral address register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [4]

stream x memory 0 address register

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
M0A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
M0A rw

Toggle fields

M0A

Bits 0-31: Memory 0 address.

M1AR [4]

stream x memory 1 address register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
M1A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
M1A rw

Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

FCR [4]

stream x FIFO control register

Offset: 0x84, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								FEIE rw		FS r			DMDIS rw	FTH rw

Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

DMDIS

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

FS

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

FEIE

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

CR [5]

stream x configuration register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				CHSEL rw			MBURST rw		PBURST rw			CT rw	DBM rw	PL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PINCOS rw	MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw		PFCTRL rw	TCIE rw	HTIE rw	TEIE rw	DMEIE rw	EN rw

Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

DMEIE

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

TEIE

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

HTIE

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TCIE

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

PFCTRL

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

DIR

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

CIRC

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PINCOS

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

PL

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

DBM

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

PBURST

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

MBURST

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

CHSEL

Bits 25-27: Channel selection.

Allowed values: 0x0-0x7

NDTR [5]

stream x number of data register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

PAR [5]

stream x peripheral address register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [5]

stream x memory 0 address register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
M0A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
M0A rw

Toggle fields

M0A

Bits 0-31: Memory 0 address.

M1AR [5]

stream x memory 1 address register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
M1A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
M1A rw

Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

FCR [5]

stream x FIFO control register

Offset: 0x9c, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								FEIE rw		FS r			DMDIS rw	FTH rw

Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

DMDIS

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

FS

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

FEIE

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

CR [6]

stream x configuration register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				CHSEL rw			MBURST rw		PBURST rw			CT rw	DBM rw	PL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PINCOS rw	MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw		PFCTRL rw	TCIE rw	HTIE rw	TEIE rw	DMEIE rw	EN rw

Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

DMEIE

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

TEIE

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

HTIE

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TCIE

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

PFCTRL

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

DIR

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

CIRC

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PINCOS

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

PL

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

DBM

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

PBURST

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

MBURST

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

CHSEL

Bits 25-27: Channel selection.

Allowed values: 0x0-0x7

NDTR [6]

stream x number of data register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

PAR [6]

stream x peripheral address register

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [6]

stream x memory 0 address register

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
M0A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
M0A rw

Toggle fields

M0A

Bits 0-31: Memory 0 address.

M1AR [6]

stream x memory 1 address register

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
M1A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
M1A rw

Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

FCR [6]

stream x FIFO control register

Offset: 0xb4, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								FEIE rw		FS r			DMDIS rw	FTH rw

Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

DMDIS

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

FS

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

FEIE

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

CR [7]

stream x configuration register

Offset: 0xb8, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				CHSEL rw			MBURST rw		PBURST rw			CT rw	DBM rw	PL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PINCOS rw	MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw		PFCTRL rw	TCIE rw	HTIE rw	TEIE rw	DMEIE rw	EN rw

Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

DMEIE

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

TEIE

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

HTIE

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TCIE

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

PFCTRL

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

DIR

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

CIRC

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PINCOS

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

PL

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

DBM

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

PBURST

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

MBURST

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

CHSEL

Bits 25-27: Channel selection.

Allowed values: 0x0-0x7

NDTR [7]

stream x number of data register

Offset: 0xbc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

PAR [7]

stream x peripheral address register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [7]

stream x memory 0 address register

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
M0A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
M0A rw

Toggle fields

M0A

Bits 0-31: Memory 0 address.

M1AR [7]

stream x memory 1 address register

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
M1A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
M1A rw

Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

FCR [7]

stream x FIFO control register

Offset: 0xcc, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								FEIE rw		FS r			DMDIS rw	FTH rw

Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

DMDIS

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

FS

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

FEIE

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

DMA2

0x40026400: DMA controller

272/296 fields covered.

Toggle register map

Offset	Name	31	27	26	25	24	22	21	20	19	18	17	16	15	14	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	LISR		TCIF3	HTIF3	TEIF3	DMEIF3	FEIF3	TCIF2	HTIF2	TEIF2	DMEIF2		FEIF2				TCIF1	HTIF1	TEIF1	DMEIF1		FEIF1	TCIF0	HTIF0	TEIF0	DMEIF0		FEIF0
0x4	HISR		TCIF7	HTIF7	TEIF7	DMEIF7	FEIF7	TCIF6	HTIF6	TEIF6	DMEIF6		FEIF6				TCIF5	HTIF5	TEIF5	DMEIF5		FEIF5	TCIF4	HTIF4	TEIF4	DMEIF4		FEIF4
0x8	LIFCR		CTCIF3	CHTIF3	CTEIF3	CDMEIF3	CFEIF3	CTCIF2	CHTIF2	CTEIF2	CDMEIF2		CFEIF2				CTCIF1	CHTIF1	CTEIF1	CDMEIF1		CFEIF1	CTCIF0	CHTIF0	CTEIF0	CDMEIF0		CFEIF0
0xc	HIFCR		CTCIF7	CHTIF7	CTEIF7	CDMEIF7	CFEIF7	CTCIF6	CHTIF6	CTEIF6	CDMEIF6		CFEIF6				CTCIF5	CHTIF5	CTEIF5	CDMEIF5		CFEIF5	CTCIF4	CHTIF4	CTEIF4	CDMEIF4		CFEIF4
0x10	CR [0]		CHSEL			MBURST	PBURST			CT	DBM	PL		PINCOS	MSIZE	PSIZE		MINC	PINC	CIRC	DIR		PFCTRL	TCIE	HTIE	TEIE	DMEIE	EN
0x14	NDTR [0]													NDT
0x18	PAR [0]	PA												PA
0x1c	M0AR [0]	M0A												M0A
0x20	M1AR [0]	M1A												M1A
0x24	FCR [0]																				FEIE		FS			DMDIS	FTH
0x28	CR [1]		CHSEL			MBURST	PBURST			CT	DBM	PL		PINCOS	MSIZE	PSIZE		MINC	PINC	CIRC	DIR		PFCTRL	TCIE	HTIE	TEIE	DMEIE	EN
0x2c	NDTR [1]													NDT
0x30	PAR [1]	PA												PA
0x34	M0AR [1]	M0A												M0A
0x38	M1AR [1]	M1A												M1A
0x3c	FCR [1]																				FEIE		FS			DMDIS	FTH
0x40	CR [2]		CHSEL			MBURST	PBURST			CT	DBM	PL		PINCOS	MSIZE	PSIZE		MINC	PINC	CIRC	DIR		PFCTRL	TCIE	HTIE	TEIE	DMEIE	EN
0x44	NDTR [2]													NDT
0x48	PAR [2]	PA												PA
0x4c	M0AR [2]	M0A												M0A
0x50	M1AR [2]	M1A												M1A
0x54	FCR [2]																				FEIE		FS			DMDIS	FTH
0x58	CR [3]		CHSEL			MBURST	PBURST			CT	DBM	PL		PINCOS	MSIZE	PSIZE		MINC	PINC	CIRC	DIR		PFCTRL	TCIE	HTIE	TEIE	DMEIE	EN
0x5c	NDTR [3]													NDT
0x60	PAR [3]	PA												PA
0x64	M0AR [3]	M0A												M0A
0x68	M1AR [3]	M1A												M1A
0x6c	FCR [3]																				FEIE		FS			DMDIS	FTH
0x70	CR [4]		CHSEL			MBURST	PBURST			CT	DBM	PL		PINCOS	MSIZE	PSIZE		MINC	PINC	CIRC	DIR		PFCTRL	TCIE	HTIE	TEIE	DMEIE	EN
0x74	NDTR [4]													NDT
0x78	PAR [4]	PA												PA
0x7c	M0AR [4]	M0A												M0A
0x80	M1AR [4]	M1A												M1A
0x84	FCR [4]																				FEIE		FS			DMDIS	FTH
0x88	CR [5]		CHSEL			MBURST	PBURST			CT	DBM	PL		PINCOS	MSIZE	PSIZE		MINC	PINC	CIRC	DIR		PFCTRL	TCIE	HTIE	TEIE	DMEIE	EN
0x8c	NDTR [5]													NDT
0x90	PAR [5]	PA												PA
0x94	M0AR [5]	M0A												M0A
0x98	M1AR [5]	M1A												M1A
0x9c	FCR [5]																				FEIE		FS			DMDIS	FTH
0xa0	CR [6]		CHSEL			MBURST	PBURST			CT	DBM	PL		PINCOS	MSIZE	PSIZE		MINC	PINC	CIRC	DIR		PFCTRL	TCIE	HTIE	TEIE	DMEIE	EN
0xa4	NDTR [6]													NDT
0xa8	PAR [6]	PA												PA
0xac	M0AR [6]	M0A												M0A
0xb0	M1AR [6]	M1A												M1A
0xb4	FCR [6]																				FEIE		FS			DMDIS	FTH
0xb8	CR [7]		CHSEL			MBURST	PBURST			CT	DBM	PL		PINCOS	MSIZE	PSIZE		MINC	PINC	CIRC	DIR		PFCTRL	TCIE	HTIE	TEIE	DMEIE	EN
0xbc	NDTR [7]													NDT
0xc0	PAR [7]	PA												PA
0xc4	M0AR [7]	M0A												M0A
0xc8	M1AR [7]	M1A												M1A
0xcc	FCR [7]																				FEIE		FS			DMDIS	FTH

Toggle registers

LISR

low interrupt status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

20/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TCIF3 r	HTIF3 r	TEIF3 r	DMEIF3 r		FEIF3 r	TCIF2 r	HTIF2 r	TEIF2 r	DMEIF2 r		FEIF2 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				TCIF1 r	HTIF1 r	TEIF1 r	DMEIF1 r		FEIF1 r	TCIF0 r	HTIF0 r	TEIF0 r	DMEIF0 r		FEIF0 r

Toggle fields

FEIF0

Bit 0: Stream x FIFO error interrupt flag (x=3..0).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF0

Bit 2: Stream x direct mode error interrupt flag (x=3..0).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF0

Bit 3: Stream x transfer error interrupt flag (x=3..0).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF0

Bit 4: Stream x half transfer interrupt flag (x=3..0).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF0

Bit 5: Stream x transfer complete interrupt flag (x = 3..0).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

FEIF1

Bit 6: Stream x FIFO error interrupt flag (x=3..0).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF1

Bit 8: Stream x direct mode error interrupt flag (x=3..0).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF1

Bit 9: Stream x transfer error interrupt flag (x=3..0).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF1

Bit 10: Stream x half transfer interrupt flag (x=3..0).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF1

Bit 11: Stream x transfer complete interrupt flag (x = 3..0).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

FEIF2

Bit 16: Stream x FIFO error interrupt flag (x=3..0).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF2

Bit 18: Stream x direct mode error interrupt flag (x=3..0).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF2

Bit 19: Stream x transfer error interrupt flag (x=3..0).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF2

Bit 20: Stream x half transfer interrupt flag (x=3..0).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF2

Bit 21: Stream x transfer complete interrupt flag (x = 3..0).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

FEIF3

Bit 22: Stream x FIFO error interrupt flag (x=3..0).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF3

Bit 24: Stream x direct mode error interrupt flag (x=3..0).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF3

Bit 25: Stream x transfer error interrupt flag (x=3..0).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF3

Bit 26: Stream x half transfer interrupt flag (x=3..0).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF3

Bit 27: Stream x transfer complete interrupt flag (x = 3..0).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

HISR

high interrupt status register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

20/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TCIF7 r	HTIF7 r	TEIF7 r	DMEIF7 r		FEIF7 r	TCIF6 r	HTIF6 r	TEIF6 r	DMEIF6 r		FEIF6 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				TCIF5 r	HTIF5 r	TEIF5 r	DMEIF5 r		FEIF5 r	TCIF4 r	HTIF4 r	TEIF4 r	DMEIF4 r		FEIF4 r

Toggle fields

FEIF4

Bit 0: Stream x FIFO error interrupt flag (x=7..4).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF4

Bit 2: Stream x direct mode error interrupt flag (x=7..4).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF4

Bit 3: Stream x transfer error interrupt flag (x=7..4).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF4

Bit 4: Stream x half transfer interrupt flag (x=7..4).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF4

Bit 5: Stream x transfer complete interrupt flag (x=7..4).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

FEIF5

Bit 6: Stream x FIFO error interrupt flag (x=7..4).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF5

Bit 8: Stream x direct mode error interrupt flag (x=7..4).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF5

Bit 9: Stream x transfer error interrupt flag (x=7..4).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF5

Bit 10: Stream x half transfer interrupt flag (x=7..4).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF5

Bit 11: Stream x transfer complete interrupt flag (x=7..4).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

FEIF6

Bit 16: Stream x FIFO error interrupt flag (x=7..4).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF6

Bit 18: Stream x direct mode error interrupt flag (x=7..4).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF6

Bit 19: Stream x transfer error interrupt flag (x=7..4).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF6

Bit 20: Stream x half transfer interrupt flag (x=7..4).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF6

Bit 21: Stream x transfer complete interrupt flag (x=7..4).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

FEIF7

Bit 22: Stream x FIFO error interrupt flag (x=7..4).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF7

Bit 24: Stream x direct mode error interrupt flag (x=7..4).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF7

Bit 25: Stream x transfer error interrupt flag (x=7..4).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF7

Bit 26: Stream x half transfer interrupt flag (x=7..4).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF7

Bit 27: Stream x transfer complete interrupt flag (x=7..4).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

LIFCR

low interrupt flag clear register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

20/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				CTCIF3 w	CHTIF3 w	CTEIF3 w	CDMEIF3 w		CFEIF3 w	CTCIF2 w	CHTIF2 w	CTEIF2 w	CDMEIF2 w		CFEIF2 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				CTCIF1 w	CHTIF1 w	CTEIF1 w	CDMEIF1 w		CFEIF1 w	CTCIF0 w	CHTIF0 w	CTEIF0 w	CDMEIF0 w		CFEIF0 w

Toggle fields

CFEIF0

Bit 0: Stream x clear FIFO error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF0

Bit 2: Stream x clear direct mode error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF0

Bit 3: Stream x clear transfer error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF0

Bit 4: Stream x clear half transfer interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF0

Bit 5: Stream x clear transfer complete interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CFEIF1

Bit 6: Stream x clear FIFO error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF1

Bit 8: Stream x clear direct mode error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF1

Bit 9: Stream x clear transfer error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF1

Bit 10: Stream x clear half transfer interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF1

Bit 11: Stream x clear transfer complete interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CFEIF2

Bit 16: Stream x clear FIFO error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF2

Bit 18: Stream x clear direct mode error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF2

Bit 19: Stream x clear transfer error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF2

Bit 20: Stream x clear half transfer interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF2

Bit 21: Stream x clear transfer complete interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CFEIF3

Bit 22: Stream x clear FIFO error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF3

Bit 24: Stream x clear direct mode error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF3

Bit 25: Stream x clear transfer error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF3

Bit 26: Stream x clear half transfer interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF3

Bit 27: Stream x clear transfer complete interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

HIFCR

high interrupt flag clear register

Offset: 0xc, size: 32, reset: 0x00000000, access: write-only

20/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				CTCIF7 w	CHTIF7 w	CTEIF7 w	CDMEIF7 w		CFEIF7 w	CTCIF6 w	CHTIF6 w	CTEIF6 w	CDMEIF6 w		CFEIF6 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				CTCIF5 w	CHTIF5 w	CTEIF5 w	CDMEIF5 w		CFEIF5 w	CTCIF4 w	CHTIF4 w	CTEIF4 w	CDMEIF4 w		CFEIF4 w

Toggle fields

CFEIF4

Bit 0: Stream x clear FIFO error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF4

Bit 2: Stream x clear direct mode error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF4

Bit 3: Stream x clear transfer error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF4

Bit 4: Stream x clear half transfer interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF4

Bit 5: Stream x clear transfer complete interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CFEIF5

Bit 6: Stream x clear FIFO error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF5

Bit 8: Stream x clear direct mode error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF5

Bit 9: Stream x clear transfer error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF5

Bit 10: Stream x clear half transfer interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF5

Bit 11: Stream x clear transfer complete interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CFEIF6

Bit 16: Stream x clear FIFO error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF6

Bit 18: Stream x clear direct mode error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF6

Bit 19: Stream x clear transfer error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF6

Bit 20: Stream x clear half transfer interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF6

Bit 21: Stream x clear transfer complete interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CFEIF7

Bit 22: Stream x clear FIFO error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF7

Bit 24: Stream x clear direct mode error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF7

Bit 25: Stream x clear transfer error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF7

Bit 26: Stream x clear half transfer interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF7

Bit 27: Stream x clear transfer complete interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CR [0]

stream x configuration register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				CHSEL rw			MBURST rw		PBURST rw			CT rw	DBM rw	PL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PINCOS rw	MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw		PFCTRL rw	TCIE rw	HTIE rw	TEIE rw	DMEIE rw	EN rw

Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

DMEIE

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

TEIE

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

HTIE

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TCIE

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

PFCTRL

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

DIR

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

CIRC

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PINCOS

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

PL

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

DBM

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

PBURST

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

MBURST

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

CHSEL

Bits 25-27: Channel selection.

Allowed values: 0x0-0x7

NDTR [0]

stream x number of data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

PAR [0]

stream x peripheral address register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [0]

stream x memory 0 address register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
M0A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
M0A rw

Toggle fields

M0A

Bits 0-31: Memory 0 address.

M1AR [0]

stream x memory 1 address register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
M1A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
M1A rw

Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

FCR [0]

stream x FIFO control register

Offset: 0x24, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								FEIE rw		FS r			DMDIS rw	FTH rw

Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

DMDIS

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

FS

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

FEIE

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

CR [1]

stream x configuration register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				CHSEL rw			MBURST rw		PBURST rw			CT rw	DBM rw	PL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PINCOS rw	MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw		PFCTRL rw	TCIE rw	HTIE rw	TEIE rw	DMEIE rw	EN rw

Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

DMEIE

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

TEIE

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

HTIE

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TCIE

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

PFCTRL

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

DIR

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

CIRC

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PINCOS

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

PL

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

DBM

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

PBURST

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

MBURST

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

CHSEL

Bits 25-27: Channel selection.

Allowed values: 0x0-0x7

NDTR [1]

stream x number of data register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

PAR [1]

stream x peripheral address register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [1]

stream x memory 0 address register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
M0A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
M0A rw

Toggle fields

M0A

Bits 0-31: Memory 0 address.

M1AR [1]

stream x memory 1 address register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
M1A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
M1A rw

Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

FCR [1]

stream x FIFO control register

Offset: 0x3c, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								FEIE rw		FS r			DMDIS rw	FTH rw

Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

DMDIS

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

FS

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

FEIE

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

CR [2]

stream x configuration register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				CHSEL rw			MBURST rw		PBURST rw			CT rw	DBM rw	PL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PINCOS rw	MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw		PFCTRL rw	TCIE rw	HTIE rw	TEIE rw	DMEIE rw	EN rw

Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

DMEIE

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

TEIE

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

HTIE

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TCIE

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

PFCTRL

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

DIR

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

CIRC

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PINCOS

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

PL

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

DBM

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

PBURST

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

MBURST

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

CHSEL

Bits 25-27: Channel selection.

Allowed values: 0x0-0x7

NDTR [2]

stream x number of data register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

PAR [2]

stream x peripheral address register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [2]

stream x memory 0 address register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
M0A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
M0A rw

Toggle fields

M0A

Bits 0-31: Memory 0 address.

M1AR [2]

stream x memory 1 address register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
M1A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
M1A rw

Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

FCR [2]

stream x FIFO control register

Offset: 0x54, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								FEIE rw		FS r			DMDIS rw	FTH rw

Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

DMDIS

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

FS

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

FEIE

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

CR [3]

stream x configuration register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				CHSEL rw			MBURST rw		PBURST rw			CT rw	DBM rw	PL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PINCOS rw	MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw		PFCTRL rw	TCIE rw	HTIE rw	TEIE rw	DMEIE rw	EN rw

Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

DMEIE

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

TEIE

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

HTIE

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TCIE

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

PFCTRL

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

DIR

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

CIRC

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PINCOS

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

PL

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

DBM

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

PBURST

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

MBURST

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

CHSEL

Bits 25-27: Channel selection.

Allowed values: 0x0-0x7

NDTR [3]

stream x number of data register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

PAR [3]

stream x peripheral address register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [3]

stream x memory 0 address register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
M0A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
M0A rw

Toggle fields

M0A

Bits 0-31: Memory 0 address.

M1AR [3]

stream x memory 1 address register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
M1A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
M1A rw

Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

FCR [3]

stream x FIFO control register

Offset: 0x6c, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								FEIE rw		FS r			DMDIS rw	FTH rw

Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

DMDIS

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

FS

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

FEIE

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

CR [4]

stream x configuration register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				CHSEL rw			MBURST rw		PBURST rw			CT rw	DBM rw	PL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PINCOS rw	MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw		PFCTRL rw	TCIE rw	HTIE rw	TEIE rw	DMEIE rw	EN rw

Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

DMEIE

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

TEIE

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

HTIE

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TCIE

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

PFCTRL

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

DIR

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

CIRC

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PINCOS

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

PL

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

DBM

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

PBURST

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

MBURST

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

CHSEL

Bits 25-27: Channel selection.

Allowed values: 0x0-0x7

NDTR [4]

stream x number of data register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

PAR [4]

stream x peripheral address register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [4]

stream x memory 0 address register

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
M0A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
M0A rw

Toggle fields

M0A

Bits 0-31: Memory 0 address.

M1AR [4]

stream x memory 1 address register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
M1A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
M1A rw

Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

FCR [4]

stream x FIFO control register

Offset: 0x84, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								FEIE rw		FS r			DMDIS rw	FTH rw

Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

DMDIS

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

FS

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

FEIE

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

CR [5]

stream x configuration register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				CHSEL rw			MBURST rw		PBURST rw			CT rw	DBM rw	PL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PINCOS rw	MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw		PFCTRL rw	TCIE rw	HTIE rw	TEIE rw	DMEIE rw	EN rw

Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

DMEIE

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

TEIE

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

HTIE

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TCIE

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

PFCTRL

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

DIR

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

CIRC

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PINCOS

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

PL

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

DBM

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

PBURST

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

MBURST

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

CHSEL

Bits 25-27: Channel selection.

Allowed values: 0x0-0x7

NDTR [5]

stream x number of data register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

PAR [5]

stream x peripheral address register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [5]

stream x memory 0 address register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
M0A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
M0A rw

Toggle fields

M0A

Bits 0-31: Memory 0 address.

M1AR [5]

stream x memory 1 address register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
M1A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
M1A rw

Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

FCR [5]

stream x FIFO control register

Offset: 0x9c, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								FEIE rw		FS r			DMDIS rw	FTH rw

Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

DMDIS

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

FS

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

FEIE

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

CR [6]

stream x configuration register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				CHSEL rw			MBURST rw		PBURST rw			CT rw	DBM rw	PL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PINCOS rw	MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw		PFCTRL rw	TCIE rw	HTIE rw	TEIE rw	DMEIE rw	EN rw

Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

DMEIE

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

TEIE

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

HTIE

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TCIE

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

PFCTRL

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

DIR

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

CIRC

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PINCOS

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

PL

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

DBM

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

PBURST

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

MBURST

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

CHSEL

Bits 25-27: Channel selection.

Allowed values: 0x0-0x7

NDTR [6]

stream x number of data register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

PAR [6]

stream x peripheral address register

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [6]

stream x memory 0 address register

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
M0A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
M0A rw

Toggle fields

M0A

Bits 0-31: Memory 0 address.

M1AR [6]

stream x memory 1 address register

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
M1A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
M1A rw

Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

FCR [6]

stream x FIFO control register

Offset: 0xb4, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								FEIE rw		FS r			DMDIS rw	FTH rw

Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

DMDIS

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

FS

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

FEIE

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

CR [7]

stream x configuration register

Offset: 0xb8, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				CHSEL rw			MBURST rw		PBURST rw			CT rw	DBM rw	PL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PINCOS rw	MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw		PFCTRL rw	TCIE rw	HTIE rw	TEIE rw	DMEIE rw	EN rw

Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

DMEIE

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

TEIE

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

HTIE

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TCIE

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

PFCTRL

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

DIR

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

CIRC

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PINCOS

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

PL

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

DBM

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

PBURST

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

MBURST

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

CHSEL

Bits 25-27: Channel selection.

Allowed values: 0x0-0x7

NDTR [7]

stream x number of data register

Offset: 0xbc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

PAR [7]

stream x peripheral address register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [7]

stream x memory 0 address register

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
M0A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
M0A rw

Toggle fields

M0A

Bits 0-31: Memory 0 address.

M1AR [7]

stream x memory 1 address register

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
M1A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
M1A rw

Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

FCR [7]

stream x FIFO control register

Offset: 0xcc, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								FEIE rw		FS r			DMDIS rw	FTH rw

Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

DMDIS

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

FS

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

FEIE

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

EXTI

0x40013c00: External interrupt/event controller

138/138 fields covered.

Toggle register map

Offset	Name	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	IMR	MR22	MR21	MR20	MR19	MR18	MR17	MR16	MR15	MR14	MR13	MR12	MR11	MR10	MR9	MR8	MR7	MR6	MR5	MR4	MR3	MR2	MR1	MR0
0x4	EMR	MR22	MR21	MR20	MR19	MR18	MR17	MR16	MR15	MR14	MR13	MR12	MR11	MR10	MR9	MR8	MR7	MR6	MR5	MR4	MR3	MR2	MR1	MR0
0x8	RTSR	TR22	TR21	TR20	TR19	TR18	TR17	TR16	TR15	TR14	TR13	TR12	TR11	TR10	TR9	TR8	TR7	TR6	TR5	TR4	TR3	TR2	TR1	TR0
0xc	FTSR	TR22	TR21	TR20	TR19	TR18	TR17	TR16	TR15	TR14	TR13	TR12	TR11	TR10	TR9	TR8	TR7	TR6	TR5	TR4	TR3	TR2	TR1	TR0
0x10	SWIER	SWIER22	SWIER21	SWIER20	SWIER19	SWIER18	SWIER17	SWIER16	SWIER15	SWIER14	SWIER13	SWIER12	SWIER11	SWIER10	SWIER9	SWIER8	SWIER7	SWIER6	SWIER5	SWIER4	SWIER3	SWIER2	SWIER1	SWIER0
0x14	PR	PR22	PR21	PR20	PR19	PR18	PR17	PR16	PR15	PR14	PR13	PR12	PR11	PR10	PR9	PR8	PR7	PR6	PR5	PR4	PR3	PR2	PR1	PR0

Toggle registers

IMR

Interrupt mask register (EXTI_IMR)

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

23/23 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									MR22 rw	MR21 rw	MR20 rw	MR19 rw	MR18 rw	MR17 rw	MR16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MR15 rw	MR14 rw	MR13 rw	MR12 rw	MR11 rw	MR10 rw	MR9 rw	MR8 rw	MR7 rw	MR6 rw	MR5 rw	MR4 rw	MR3 rw	MR2 rw	MR1 rw	MR0 rw

Toggle fields

MR0

Bit 0: Interrupt Mask on line 0.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR1

Bit 1: Interrupt Mask on line 1.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR2

Bit 2: Interrupt Mask on line 2.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR3

Bit 3: Interrupt Mask on line 3.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR4

Bit 4: Interrupt Mask on line 4.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR5

Bit 5: Interrupt Mask on line 5.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR6

Bit 6: Interrupt Mask on line 6.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR7

Bit 7: Interrupt Mask on line 7.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR8

Bit 8: Interrupt Mask on line 8.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR9

Bit 9: Interrupt Mask on line 9.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR10

Bit 10: Interrupt Mask on line 10.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR11

Bit 11: Interrupt Mask on line 11.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR12

Bit 12: Interrupt Mask on line 12.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR13

Bit 13: Interrupt Mask on line 13.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR14

Bit 14: Interrupt Mask on line 14.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR15

Bit 15: Interrupt Mask on line 15.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR16

Bit 16: Interrupt Mask on line 16.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR17

Bit 17: Interrupt Mask on line 17.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR18

Bit 18: Interrupt Mask on line 18.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR19

Bit 19: Interrupt Mask on line 19.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR20

Bit 20: Interrupt Mask on line 20.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR21

Bit 21: Interrupt Mask on line 21.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR22

Bit 22: Interrupt Mask on line 22.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EMR

Event mask register (EXTI_EMR)

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

23/23 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									MR22 rw	MR21 rw	MR20 rw	MR19 rw	MR18 rw	MR17 rw	MR16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MR15 rw	MR14 rw	MR13 rw	MR12 rw	MR11 rw	MR10 rw	MR9 rw	MR8 rw	MR7 rw	MR6 rw	MR5 rw	MR4 rw	MR3 rw	MR2 rw	MR1 rw	MR0 rw

Toggle fields

MR0

Bit 0: Event Mask on line 0.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR1

Bit 1: Event Mask on line 1.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR2

Bit 2: Event Mask on line 2.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR3

Bit 3: Event Mask on line 3.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR4

Bit 4: Event Mask on line 4.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR5

Bit 5: Event Mask on line 5.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR6

Bit 6: Event Mask on line 6.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR7

Bit 7: Event Mask on line 7.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR8

Bit 8: Event Mask on line 8.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR9

Bit 9: Event Mask on line 9.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR10

Bit 10: Event Mask on line 10.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR11

Bit 11: Event Mask on line 11.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR12

Bit 12: Event Mask on line 12.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR13

Bit 13: Event Mask on line 13.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR14

Bit 14: Event Mask on line 14.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR15

Bit 15: Event Mask on line 15.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR16

Bit 16: Event Mask on line 16.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR17

Bit 17: Event Mask on line 17.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR18

Bit 18: Event Mask on line 18.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR19

Bit 19: Event Mask on line 19.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR20

Bit 20: Event Mask on line 20.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR21

Bit 21: Event Mask on line 21.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR22

Bit 22: Event Mask on line 22.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

RTSR

Rising Trigger selection register (EXTI_RTSR)

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

23/23 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									TR22 rw	TR21 rw	TR20 rw	TR19 rw	TR18 rw	TR17 rw	TR16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TR15 rw	TR14 rw	TR13 rw	TR12 rw	TR11 rw	TR10 rw	TR9 rw	TR8 rw	TR7 rw	TR6 rw	TR5 rw	TR4 rw	TR3 rw	TR2 rw	TR1 rw	TR0 rw

Toggle fields

TR0

Bit 0: Rising trigger event configuration of line 0.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR1

Bit 1: Rising trigger event configuration of line 1.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR2

Bit 2: Rising trigger event configuration of line 2.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR3

Bit 3: Rising trigger event configuration of line 3.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR4

Bit 4: Rising trigger event configuration of line 4.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR5

Bit 5: Rising trigger event configuration of line 5.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR6

Bit 6: Rising trigger event configuration of line 6.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR7

Bit 7: Rising trigger event configuration of line 7.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR8

Bit 8: Rising trigger event configuration of line 8.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR9

Bit 9: Rising trigger event configuration of line 9.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR10

Bit 10: Rising trigger event configuration of line 10.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR11

Bit 11: Rising trigger event configuration of line 11.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR12

Bit 12: Rising trigger event configuration of line 12.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR13

Bit 13: Rising trigger event configuration of line 13.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR14

Bit 14: Rising trigger event configuration of line 14.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR15

Bit 15: Rising trigger event configuration of line 15.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR16

Bit 16: Rising trigger event configuration of line 16.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR17

Bit 17: Rising trigger event configuration of line 17.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR18

Bit 18: Rising trigger event configuration of line 18.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR19

Bit 19: Rising trigger event configuration of line 19.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR20

Bit 20: Rising trigger event configuration of line 20.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR21

Bit 21: Rising trigger event configuration of line 21.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR22

Bit 22: Rising trigger event configuration of line 22.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

FTSR

Falling Trigger selection register (EXTI_FTSR)

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

23/23 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									TR22 rw	TR21 rw	TR20 rw	TR19 rw	TR18 rw	TR17 rw	TR16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TR15 rw	TR14 rw	TR13 rw	TR12 rw	TR11 rw	TR10 rw	TR9 rw	TR8 rw	TR7 rw	TR6 rw	TR5 rw	TR4 rw	TR3 rw	TR2 rw	TR1 rw	TR0 rw

Toggle fields

TR0

Bit 0: Falling trigger event configuration of line 0.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR1

Bit 1: Falling trigger event configuration of line 1.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR2

Bit 2: Falling trigger event configuration of line 2.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR3

Bit 3: Falling trigger event configuration of line 3.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR4

Bit 4: Falling trigger event configuration of line 4.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR5

Bit 5: Falling trigger event configuration of line 5.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR6

Bit 6: Falling trigger event configuration of line 6.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR7

Bit 7: Falling trigger event configuration of line 7.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR8

Bit 8: Falling trigger event configuration of line 8.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR9

Bit 9: Falling trigger event configuration of line 9.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR10

Bit 10: Falling trigger event configuration of line 10.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR11

Bit 11: Falling trigger event configuration of line 11.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR12

Bit 12: Falling trigger event configuration of line 12.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR13

Bit 13: Falling trigger event configuration of line 13.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR14

Bit 14: Falling trigger event configuration of line 14.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR15

Bit 15: Falling trigger event configuration of line 15.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR16

Bit 16: Falling trigger event configuration of line 16.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR17

Bit 17: Falling trigger event configuration of line 17.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR18

Bit 18: Falling trigger event configuration of line 18.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR19

Bit 19: Falling trigger event configuration of line 19.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR20

Bit 20: Falling trigger event configuration of line 20.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR21

Bit 21: Falling trigger event configuration of line 21.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR22

Bit 22: Falling trigger event configuration of line 22.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

SWIER

Software interrupt event register (EXTI_SWIER)

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

23/23 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									SWIER22 rw	SWIER21 rw	SWIER20 rw	SWIER19 rw	SWIER18 rw	SWIER17 rw	SWIER16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWIER15 rw	SWIER14 rw	SWIER13 rw	SWIER12 rw	SWIER11 rw	SWIER10 rw	SWIER9 rw	SWIER8 rw	SWIER7 rw	SWIER6 rw	SWIER5 rw	SWIER4 rw	SWIER3 rw	SWIER2 rw	SWIER1 rw	SWIER0 rw

Toggle fields

SWIER0

Bit 0: Software Interrupt on line 0.

Allowed values:
1: Pend: Generates an interrupt request

SWIER1

Bit 1: Software Interrupt on line 1.

Allowed values:
1: Pend: Generates an interrupt request

SWIER2

Bit 2: Software Interrupt on line 2.

Allowed values:
1: Pend: Generates an interrupt request

SWIER3

Bit 3: Software Interrupt on line 3.

Allowed values:
1: Pend: Generates an interrupt request

SWIER4

Bit 4: Software Interrupt on line 4.

Allowed values:
1: Pend: Generates an interrupt request

SWIER5

Bit 5: Software Interrupt on line 5.

Allowed values:
1: Pend: Generates an interrupt request

SWIER6

Bit 6: Software Interrupt on line 6.

Allowed values:
1: Pend: Generates an interrupt request

SWIER7

Bit 7: Software Interrupt on line 7.

Allowed values:
1: Pend: Generates an interrupt request

SWIER8

Bit 8: Software Interrupt on line 8.

Allowed values:
1: Pend: Generates an interrupt request

SWIER9

Bit 9: Software Interrupt on line 9.

Allowed values:
1: Pend: Generates an interrupt request

SWIER10

Bit 10: Software Interrupt on line 10.

Allowed values:
1: Pend: Generates an interrupt request

SWIER11

Bit 11: Software Interrupt on line 11.

Allowed values:
1: Pend: Generates an interrupt request

SWIER12

Bit 12: Software Interrupt on line 12.

Allowed values:
1: Pend: Generates an interrupt request

SWIER13

Bit 13: Software Interrupt on line 13.

Allowed values:
1: Pend: Generates an interrupt request

SWIER14

Bit 14: Software Interrupt on line 14.

Allowed values:
1: Pend: Generates an interrupt request

SWIER15

Bit 15: Software Interrupt on line 15.

Allowed values:
1: Pend: Generates an interrupt request

SWIER16

Bit 16: Software Interrupt on line 16.

Allowed values:
1: Pend: Generates an interrupt request

SWIER17

Bit 17: Software Interrupt on line 17.

Allowed values:
1: Pend: Generates an interrupt request

SWIER18

Bit 18: Software Interrupt on line 18.

Allowed values:
1: Pend: Generates an interrupt request

SWIER19

Bit 19: Software Interrupt on line 19.

Allowed values:
1: Pend: Generates an interrupt request

SWIER20

Bit 20: Software Interrupt on line 20.

Allowed values:
1: Pend: Generates an interrupt request

SWIER21

Bit 21: Software Interrupt on line 21.

Allowed values:
1: Pend: Generates an interrupt request

SWIER22

Bit 22: Software Interrupt on line 22.

Allowed values:
1: Pend: Generates an interrupt request

PR

Pending register (EXTI_PR)

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

23/23 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									PR22 rw	PR21 rw	PR20 rw	PR19 rw	PR18 rw	PR17 rw	PR16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PR15 rw	PR14 rw	PR13 rw	PR12 rw	PR11 rw	PR10 rw	PR9 rw	PR8 rw	PR7 rw	PR6 rw	PR5 rw	PR4 rw	PR3 rw	PR2 rw	PR1 rw	PR0 rw

Toggle fields

PR0

Bit 0: Pending bit 0.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR1

Bit 1: Pending bit 1.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR2

Bit 2: Pending bit 2.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR3

Bit 3: Pending bit 3.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR4

Bit 4: Pending bit 4.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR5

Bit 5: Pending bit 5.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR6

Bit 6: Pending bit 6.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR7

Bit 7: Pending bit 7.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR8

Bit 8: Pending bit 8.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR9

Bit 9: Pending bit 9.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR10

Bit 10: Pending bit 10.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR11

Bit 11: Pending bit 11.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR12

Bit 12: Pending bit 12.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR13

Bit 13: Pending bit 13.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR14

Bit 14: Pending bit 14.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR15

Bit 15: Pending bit 15.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR16

Bit 16: Pending bit 16.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR17

Bit 17: Pending bit 17.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR18

Bit 18: Pending bit 18.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR19

Bit 19: Pending bit 19.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR20

Bit 20: Pending bit 20.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR21

Bit 21: Pending bit 21.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR22

Bit 22: Pending bit 22.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

FLASH

0x40023c00: FLASH

24/32 fields covered.

Toggle register map

Offset	Name	31	27	25	24	16	15	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	ACR							DCRST	ICRST	DCEN	ICEN	PRFTEN					LATENCY
0x4	KEYR	KEY					KEY
0x8	OPTKEYR	OPTKEY					OPTKEY
0xc	SR					BSY							PGSERR	PGPERR	PGAERR	WRPERR			OPERR	EOP
0x10	CR	LOCK		ERRIE	EOPIE	STRT					PSIZE			SNB				MER	SER	PG
0x14	OPTCR		nWRP				RDP						nRST_STDBY	nRST_STOP	WDG_SW		BOR_LEV		OPTSTRT	OPTLOCK

Toggle registers

ACR

Flash access control register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DCRST rw	ICRST w	DCEN rw	ICEN rw	PRFTEN rw					LATENCY rw

Toggle fields

LATENCY

Bits 0-3: Latency.

Allowed values:
0: WS0: 0 wait states
1: WS1: 1 wait states
2: WS2: 2 wait states
3: WS3: 3 wait states
4: WS4: 4 wait states
5: WS5: 5 wait states
6: WS6: 6 wait states
7: WS7: 7 wait states
8: WS8: 8 wait states
9: WS9: 9 wait states
10: WS10: 10 wait states
11: WS11: 11 wait states
12: WS12: 12 wait states
13: WS13: 13 wait states
14: WS14: 14 wait states
15: WS15: 15 wait states

PRFTEN

Bit 8: Prefetch enable.

Allowed values:
0: Disabled: Prefetch is disabled
1: Enabled: Prefetch is enabled

ICEN

Bit 9: Instruction cache enable.

Allowed values:
0: Disabled: Instruction cache is disabled
1: Enabled: Instruction cache is enabled

DCEN

Bit 10: Data cache enable.

Allowed values:
0: Disabled: Data cache is disabled
1: Enabled: Data cache is enabled

ICRST

Bit 11: Instruction cache reset.

Allowed values:
0: NotReset: Instruction cache is not reset
1: Reset: Instruction cache is reset

DCRST

Bit 12: Data cache reset.

Allowed values:
0: NotReset: Data cache is not reset
1: Reset: Data cache is reset

KEYR

Flash key register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
KEY w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY w

Toggle fields

KEY

Bits 0-31: FPEC key.

Allowed values: 0x0-0xffffffff

OPTKEYR

Flash option key register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OPTKEY w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OPTKEY w

Toggle fields

OPTKEY

Bits 0-31: Option byte key.

Allowed values: 0x0-0xffffffff

SR

Status register

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

7/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															BSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PGSERR rw	PGPERR rw	PGAERR rw	WRPERR rw			OPERR rw	EOP rw

Toggle fields

EOP

Bit 0: End of operation.

Allowed values:
1: Clear: Clear error flag

OPERR

Bit 1: Operation error.

Allowed values:
1: Clear: Clear error flag

WRPERR

Bit 4: Write protection error.

Allowed values:
1: Clear: Clear error flag

PGAERR

Bit 5: Programming alignment error.

Allowed values:
1: Clear: Clear error flag

PGPERR

Bit 6: Programming parallelism error.

Allowed values:
1: Clear: Clear error flag

PGSERR

Bit 7: Programming sequence error.

Allowed values:
1: Clear: Clear error flag

BSY

Bit 16: Busy.

Allowed values:
0: NotBusy: no Flash memory operation ongoing
1: Busy: Flash memory operation ongoing

CR

Control register

Offset: 0x10, size: 32, reset: 0x80000000, access: read-write

9/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw						ERRIE rw	EOPIE rw								STRT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						PSIZE rw			SNB rw				MER rw	SER rw	PG rw

Toggle fields

PG

Bit 0: Programming.

Allowed values:
1: Program: Flash programming activated

SER

Bit 1: Sector Erase.

Allowed values:
1: SectorErase: Erase activated for selected sector

MER

Bit 2: Mass Erase.

Allowed values:
1: MassErase: Erase activated for all user sectors

SNB

Bits 3-6: Sector number.

Allowed values: 0x0-0xb

PSIZE

Bits 8-9: Program size.

Allowed values:
0: PSIZE8: Program x8
1: PSIZE16: Program x16
2: PSIZE32: Program x32
3: PSIZE64: Program x64

STRT

Bit 16: Start.

Allowed values:
1: Start: Trigger an erase operation

EOPIE

Bit 24: End of operation interrupt enable.

Allowed values:
0: Disabled: End of operation interrupt disabled
1: Enabled: End of operation interrupt enabled

ERRIE

Bit 25: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt generation disabled
1: Enabled: Error interrupt generation enabled

LOCK

Bit 31: Lock.

Allowed values:
0: Unlocked: FLASH_CR register is unlocked
1: Locked: FLASH_CR register is locked

OPTCR

Flash option control register

Offset: 0x14, size: 32, reset: 0x00000014, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				nWRP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RDP rw								nRST_STDBY rw	nRST_STOP rw	WDG_SW rw		BOR_LEV rw		OPTSTRT rw	OPTLOCK rw

Toggle fields

OPTLOCK

Bit 0: Option lock.

OPTSTRT

Bit 1: Option start.

BOR_LEV

Bits 2-3: BOR reset Level.

WDG_SW

Bit 5: WDG_SW User option bytes.

nRST_STOP

Bit 6: nRST_STOP User option bytes.

nRST_STDBY

Bit 7: nRST_STDBY User option bytes.

RDP

Bits 8-15: Read protect.

nWRP

Bits 16-27: Not write protect.

FPU

0xe000ef34: Floting point unit

0/24 fields covered.

Toggle register map

Offset	Name	31	30	29	28	26	25	24	23	15	8	7	6	5	4	3	2	1	0
0x0	FPCCR	ASPEN	LSPEN								MONRDY		BFRDY	MMRDY	HFRDY	THREAD		USER	LSPACT
0x4	FPCAR	ADDRESS								ADDRESS
0x8	FPSCR	N	Z	C	V	AHP	DN	FZ	RMode			IDC			IXC	UFC	OFC	DZC	IOC

Toggle registers

FPCCR

Floating-point context control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ASPEN rw	LSPEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							MONRDY rw		BFRDY rw	MMRDY rw	HFRDY rw	THREAD rw		USER rw	LSPACT rw

Toggle fields

LSPACT

Bit 0: LSPACT.

USER

Bit 1: USER.

THREAD

Bit 3: THREAD.

HFRDY

Bit 4: HFRDY.

MMRDY

Bit 5: MMRDY.

BFRDY

Bit 6: BFRDY.

MONRDY

Bit 8: MONRDY.

LSPEN

Bit 30: LSPEN.

ASPEN

Bit 31: ASPEN.

FPCAR

Floating-point context address register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADDRESS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDRESS rw

Toggle fields

ADDRESS

Bits 3-31: Location of unpopulated floating-point.

FPSCR

Floating-point status control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
N rw	Z rw	C rw	V rw		AHP rw	DN rw	FZ rw	RMode rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IDC rw			IXC rw	UFC rw	OFC rw	DZC rw	IOC rw

Toggle fields

IOC

Bit 0: Invalid operation cumulative exception bit.

DZC

Bit 1: Division by zero cumulative exception bit..

OFC

Bit 2: Overflow cumulative exception bit.

UFC

Bit 3: Underflow cumulative exception bit.

IXC

Bit 4: Inexact cumulative exception bit.

IDC

Bit 7: Input denormal cumulative exception bit..

RMode

Bits 22-23: Rounding Mode control field.

FZ

Bit 24: Flush-to-zero mode control bit:.

DN

Bit 25: Default NaN mode control bit.

AHP

Bit 26: Alternative half-precision control bit.

V

Bit 28: Overflow condition code flag.

C

Bit 29: Carry condition code flag.

Z

Bit 30: Zero condition code flag.

N

Bit 31: Negative condition code flag.

FPU_CPACR

0xe000ed88: Floating point unit CPACR

0/1 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CPACR									CP

Toggle registers

CPACR

Coprocessor access control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								CP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

CP

Bits 20-23: CP.

GPIOA

0x40020000: General-purpose I/Os

161/161 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	MODER	MODER[15]		MODER[14]		MODER[13]		MODER[12]		MODER[11]		MODER[10]		MODER[9]		MODER[8]		MODER[7]		MODER[6]		MODER[5]		MODER[4]		MODER[3]		MODER[2]		MODER[1]		MODER[0]
0x4	OTYPER																	OT[15]	OT[14]	OT[13]	OT[12]	OT[11]	OT[10]	OT[9]	OT[8]	OT[7]	OT[6]	OT[5]	OT[4]	OT[3]	OT[2]	OT[1]	OT[0]
0x8	OSPEEDR	OSPEEDR[15]		OSPEEDR[14]		OSPEEDR[13]		OSPEEDR[12]		OSPEEDR[11]		OSPEEDR[10]		OSPEEDR[9]		OSPEEDR[8]		OSPEEDR[7]		OSPEEDR[6]		OSPEEDR[5]		OSPEEDR[4]		OSPEEDR[3]		OSPEEDR[2]		OSPEEDR[1]		OSPEEDR[0]
0xc	PUPDR	PUPDR[15]		PUPDR[14]		PUPDR[13]		PUPDR[12]		PUPDR[11]		PUPDR[10]		PUPDR[9]		PUPDR[8]		PUPDR[7]		PUPDR[6]		PUPDR[5]		PUPDR[4]		PUPDR[3]		PUPDR[2]		PUPDR[1]		PUPDR[0]
0x10	IDR																	IDR[15]	IDR[14]	IDR[13]	IDR[12]	IDR[11]	IDR[10]	IDR[9]	IDR[8]	IDR[7]	IDR[6]	IDR[5]	IDR[4]	IDR[3]	IDR[2]	IDR[1]	IDR[0]
0x14	ODR																	ODR[15]	ODR[14]	ODR[13]	ODR[12]	ODR[11]	ODR[10]	ODR[9]	ODR[8]	ODR[7]	ODR[6]	ODR[5]	ODR[4]	ODR[3]	ODR[2]	ODR[1]	ODR[0]
0x18	BSRR	BR[15]	BR[14]	BR[13]	BR[12]	BR[11]	BR[10]	BR[9]	BR[8]	BR[7]	BR[6]	BR[5]	BR[4]	BR[3]	BR[2]	BR[1]	BR[0]	BS[15]	BS[14]	BS[13]	BS[12]	BS[11]	BS[10]	BS[9]	BS[8]	BS[7]	BS[6]	BS[5]	BS[4]	BS[3]	BS[2]	BS[1]	BS[0]
0x1c	LCKR																LCKK	LCK[15]	LCK[14]	LCK[13]	LCK[12]	LCK[11]	LCK[10]	LCK[9]	LCK[8]	LCK[7]	LCK[6]	LCK[5]	LCK[4]	LCK[3]	LCK[2]	LCK[1]	LCK[0]
0x20	AFRL	AFR[L7]				AFR[L6]				AFR[L5]				AFR[L4]				AFR[L3]				AFR[L2]				AFR[L1]				AFR[L0]
0x24	AFRH	AFR[H15]				AFR[H14]				AFR[H13]				AFR[H12]				AFR[H11]				AFR[H10]				AFR[H9]				AFR[H8]

Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xA8000000, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODER[15] rw		MODER[14] rw		MODER[13] rw		MODER[12] rw		MODER[11] rw		MODER[10] rw		MODER[9] rw		MODER[8] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODER[7] rw		MODER[6] rw		MODER[5] rw		MODER[4] rw		MODER[3] rw		MODER[2] rw		MODER[1] rw		MODER[0] rw

Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT[15] rw	OT[14] rw	OT[13] rw	OT[12] rw	OT[11] rw	OT[10] rw	OT[9] rw	OT[8] rw	OT[7] rw	OT[6] rw	OT[5] rw	OT[4] rw	OT[3] rw	OT[2] rw	OT[1] rw	OT[0] rw

Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEEDR[15] rw		OSPEEDR[14] rw		OSPEEDR[13] rw		OSPEEDR[12] rw		OSPEEDR[11] rw		OSPEEDR[10] rw		OSPEEDR[9] rw		OSPEEDR[8] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEEDR[7] rw		OSPEEDR[6] rw		OSPEEDR[5] rw		OSPEEDR[4] rw		OSPEEDR[3] rw		OSPEEDR[2] rw		OSPEEDR[1] rw		OSPEEDR[0] rw

Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x64000000, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPDR[15] rw		PUPDR[14] rw		PUPDR[13] rw		PUPDR[12] rw		PUPDR[11] rw		PUPDR[10] rw		PUPDR[9] rw		PUPDR[8] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPDR[7] rw		PUPDR[6] rw		PUPDR[5] rw		PUPDR[4] rw		PUPDR[3] rw		PUPDR[2] rw		PUPDR[1] rw		PUPDR[0] rw

Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IDR[15] r	IDR[14] r	IDR[13] r	IDR[12] r	IDR[11] r	IDR[10] r	IDR[9] r	IDR[8] r	IDR[7] r	IDR[6] r	IDR[5] r	IDR[4] r	IDR[3] r	IDR[2] r	IDR[1] r	IDR[0] r

Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ODR[15] rw	ODR[14] rw	ODR[13] rw	ODR[12] rw	ODR[11] rw	ODR[10] rw	ODR[9] rw	ODR[8] rw	ODR[7] rw	ODR[6] rw	ODR[5] rw	ODR[4] rw	ODR[3] rw	ODR[2] rw	ODR[1] rw	ODR[0] rw

Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR[15] w	BR[14] w	BR[13] w	BR[12] w	BR[11] w	BR[10] w	BR[9] w	BR[8] w	BR[7] w	BR[6] w	BR[5] w	BR[4] w	BR[3] w	BR[2] w	BR[1] w	BR[0] w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS[15] w	BS[14] w	BS[13] w	BS[12] w	BS[11] w	BS[10] w	BS[9] w	BS[8] w	BS[7] w	BS[6] w	BS[5] w	BS[4] w	BS[3] w	BS[2] w	BS[1] w	BS[0] w

Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK[15] rw	LCK[14] rw	LCK[13] rw	LCK[12] rw	LCK[11] rw	LCK[10] rw	LCK[9] rw	LCK[8] rw	LCK[7] rw	LCK[6] rw	LCK[5] rw	LCK[4] rw	LCK[3] rw	LCK[2] rw	LCK[1] rw	LCK[0] rw

Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFR[L7] rw				AFR[L6] rw				AFR[L5] rw				AFR[L4] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFR[L3] rw				AFR[L2] rw				AFR[L1] rw				AFR[L0] rw

Toggle fields

AFR[L0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFR[H15] rw				AFR[H14] rw				AFR[H13] rw				AFR[H12] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFR[H11] rw				AFR[H10] rw				AFR[H9] rw				AFR[H8] rw

Toggle fields

AFR[H8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

GPIOB

0x40020400: General-purpose I/Os

161/161 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	MODER	MODER[15]		MODER[14]		MODER[13]		MODER[12]		MODER[11]		MODER[10]		MODER[9]		MODER[8]		MODER[7]		MODER[6]		MODER[5]		MODER[4]		MODER[3]		MODER[2]		MODER[1]		MODER[0]
0x4	OTYPER																	OT[15]	OT[14]	OT[13]	OT[12]	OT[11]	OT[10]	OT[9]	OT[8]	OT[7]	OT[6]	OT[5]	OT[4]	OT[3]	OT[2]	OT[1]	OT[0]
0x8	OSPEEDR	OSPEEDR[15]		OSPEEDR[14]		OSPEEDR[13]		OSPEEDR[12]		OSPEEDR[11]		OSPEEDR[10]		OSPEEDR[9]		OSPEEDR[8]		OSPEEDR[7]		OSPEEDR[6]		OSPEEDR[5]		OSPEEDR[4]		OSPEEDR[3]		OSPEEDR[2]		OSPEEDR[1]		OSPEEDR[0]
0xc	PUPDR	PUPDR[15]		PUPDR[14]		PUPDR[13]		PUPDR[12]		PUPDR[11]		PUPDR[10]		PUPDR[9]		PUPDR[8]		PUPDR[7]		PUPDR[6]		PUPDR[5]		PUPDR[4]		PUPDR[3]		PUPDR[2]		PUPDR[1]		PUPDR[0]
0x10	IDR																	IDR[15]	IDR[14]	IDR[13]	IDR[12]	IDR[11]	IDR[10]	IDR[9]	IDR[8]	IDR[7]	IDR[6]	IDR[5]	IDR[4]	IDR[3]	IDR[2]	IDR[1]	IDR[0]
0x14	ODR																	ODR[15]	ODR[14]	ODR[13]	ODR[12]	ODR[11]	ODR[10]	ODR[9]	ODR[8]	ODR[7]	ODR[6]	ODR[5]	ODR[4]	ODR[3]	ODR[2]	ODR[1]	ODR[0]
0x18	BSRR	BR[15]	BR[14]	BR[13]	BR[12]	BR[11]	BR[10]	BR[9]	BR[8]	BR[7]	BR[6]	BR[5]	BR[4]	BR[3]	BR[2]	BR[1]	BR[0]	BS[15]	BS[14]	BS[13]	BS[12]	BS[11]	BS[10]	BS[9]	BS[8]	BS[7]	BS[6]	BS[5]	BS[4]	BS[3]	BS[2]	BS[1]	BS[0]
0x1c	LCKR																LCKK	LCK[15]	LCK[14]	LCK[13]	LCK[12]	LCK[11]	LCK[10]	LCK[9]	LCK[8]	LCK[7]	LCK[6]	LCK[5]	LCK[4]	LCK[3]	LCK[2]	LCK[1]	LCK[0]
0x20	AFRL	AFR[L7]				AFR[L6]				AFR[L5]				AFR[L4]				AFR[L3]				AFR[L2]				AFR[L1]				AFR[L0]
0x24	AFRH	AFR[H15]				AFR[H14]				AFR[H13]				AFR[H12]				AFR[H11]				AFR[H10]				AFR[H9]				AFR[H8]

Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0x00000280, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODER[15] rw		MODER[14] rw		MODER[13] rw		MODER[12] rw		MODER[11] rw		MODER[10] rw		MODER[9] rw		MODER[8] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODER[7] rw		MODER[6] rw		MODER[5] rw		MODER[4] rw		MODER[3] rw		MODER[2] rw		MODER[1] rw		MODER[0] rw

Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT[15] rw	OT[14] rw	OT[13] rw	OT[12] rw	OT[11] rw	OT[10] rw	OT[9] rw	OT[8] rw	OT[7] rw	OT[6] rw	OT[5] rw	OT[4] rw	OT[3] rw	OT[2] rw	OT[1] rw	OT[0] rw

Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x000000C0, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEEDR[15] rw		OSPEEDR[14] rw		OSPEEDR[13] rw		OSPEEDR[12] rw		OSPEEDR[11] rw		OSPEEDR[10] rw		OSPEEDR[9] rw		OSPEEDR[8] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEEDR[7] rw		OSPEEDR[6] rw		OSPEEDR[5] rw		OSPEEDR[4] rw		OSPEEDR[3] rw		OSPEEDR[2] rw		OSPEEDR[1] rw		OSPEEDR[0] rw

Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000100, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPDR[15] rw		PUPDR[14] rw		PUPDR[13] rw		PUPDR[12] rw		PUPDR[11] rw		PUPDR[10] rw		PUPDR[9] rw		PUPDR[8] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPDR[7] rw		PUPDR[6] rw		PUPDR[5] rw		PUPDR[4] rw		PUPDR[3] rw		PUPDR[2] rw		PUPDR[1] rw		PUPDR[0] rw

Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IDR[15] r	IDR[14] r	IDR[13] r	IDR[12] r	IDR[11] r	IDR[10] r	IDR[9] r	IDR[8] r	IDR[7] r	IDR[6] r	IDR[5] r	IDR[4] r	IDR[3] r	IDR[2] r	IDR[1] r	IDR[0] r

Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ODR[15] rw	ODR[14] rw	ODR[13] rw	ODR[12] rw	ODR[11] rw	ODR[10] rw	ODR[9] rw	ODR[8] rw	ODR[7] rw	ODR[6] rw	ODR[5] rw	ODR[4] rw	ODR[3] rw	ODR[2] rw	ODR[1] rw	ODR[0] rw

Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR[15] w	BR[14] w	BR[13] w	BR[12] w	BR[11] w	BR[10] w	BR[9] w	BR[8] w	BR[7] w	BR[6] w	BR[5] w	BR[4] w	BR[3] w	BR[2] w	BR[1] w	BR[0] w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS[15] w	BS[14] w	BS[13] w	BS[12] w	BS[11] w	BS[10] w	BS[9] w	BS[8] w	BS[7] w	BS[6] w	BS[5] w	BS[4] w	BS[3] w	BS[2] w	BS[1] w	BS[0] w

Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK[15] rw	LCK[14] rw	LCK[13] rw	LCK[12] rw	LCK[11] rw	LCK[10] rw	LCK[9] rw	LCK[8] rw	LCK[7] rw	LCK[6] rw	LCK[5] rw	LCK[4] rw	LCK[3] rw	LCK[2] rw	LCK[1] rw	LCK[0] rw

Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFR[L7] rw				AFR[L6] rw				AFR[L5] rw				AFR[L4] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFR[L3] rw				AFR[L2] rw				AFR[L1] rw				AFR[L0] rw

Toggle fields

AFR[L0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFR[H15] rw				AFR[H14] rw				AFR[H13] rw				AFR[H12] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFR[H11] rw				AFR[H10] rw				AFR[H9] rw				AFR[H8] rw

Toggle fields

AFR[H8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

GPIOC

0x40020800: General-purpose I/Os

161/161 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	MODER	MODER[15]		MODER[14]		MODER[13]		MODER[12]		MODER[11]		MODER[10]		MODER[9]		MODER[8]		MODER[7]		MODER[6]		MODER[5]		MODER[4]		MODER[3]		MODER[2]		MODER[1]		MODER[0]
0x4	OTYPER																	OT[15]	OT[14]	OT[13]	OT[12]	OT[11]	OT[10]	OT[9]	OT[8]	OT[7]	OT[6]	OT[5]	OT[4]	OT[3]	OT[2]	OT[1]	OT[0]
0x8	OSPEEDR	OSPEEDR[15]		OSPEEDR[14]		OSPEEDR[13]		OSPEEDR[12]		OSPEEDR[11]		OSPEEDR[10]		OSPEEDR[9]		OSPEEDR[8]		OSPEEDR[7]		OSPEEDR[6]		OSPEEDR[5]		OSPEEDR[4]		OSPEEDR[3]		OSPEEDR[2]		OSPEEDR[1]		OSPEEDR[0]
0xc	PUPDR	PUPDR[15]		PUPDR[14]		PUPDR[13]		PUPDR[12]		PUPDR[11]		PUPDR[10]		PUPDR[9]		PUPDR[8]		PUPDR[7]		PUPDR[6]		PUPDR[5]		PUPDR[4]		PUPDR[3]		PUPDR[2]		PUPDR[1]		PUPDR[0]
0x10	IDR																	IDR[15]	IDR[14]	IDR[13]	IDR[12]	IDR[11]	IDR[10]	IDR[9]	IDR[8]	IDR[7]	IDR[6]	IDR[5]	IDR[4]	IDR[3]	IDR[2]	IDR[1]	IDR[0]
0x14	ODR																	ODR[15]	ODR[14]	ODR[13]	ODR[12]	ODR[11]	ODR[10]	ODR[9]	ODR[8]	ODR[7]	ODR[6]	ODR[5]	ODR[4]	ODR[3]	ODR[2]	ODR[1]	ODR[0]
0x18	BSRR	BR[15]	BR[14]	BR[13]	BR[12]	BR[11]	BR[10]	BR[9]	BR[8]	BR[7]	BR[6]	BR[5]	BR[4]	BR[3]	BR[2]	BR[1]	BR[0]	BS[15]	BS[14]	BS[13]	BS[12]	BS[11]	BS[10]	BS[9]	BS[8]	BS[7]	BS[6]	BS[5]	BS[4]	BS[3]	BS[2]	BS[1]	BS[0]
0x1c	LCKR																LCKK	LCK[15]	LCK[14]	LCK[13]	LCK[12]	LCK[11]	LCK[10]	LCK[9]	LCK[8]	LCK[7]	LCK[6]	LCK[5]	LCK[4]	LCK[3]	LCK[2]	LCK[1]	LCK[0]
0x20	AFRL	AFR[L7]				AFR[L6]				AFR[L5]				AFR[L4]				AFR[L3]				AFR[L2]				AFR[L1]				AFR[L0]
0x24	AFRH	AFR[H15]				AFR[H14]				AFR[H13]				AFR[H12]				AFR[H11]				AFR[H10]				AFR[H9]				AFR[H8]

Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODER[15] rw		MODER[14] rw		MODER[13] rw		MODER[12] rw		MODER[11] rw		MODER[10] rw		MODER[9] rw		MODER[8] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODER[7] rw		MODER[6] rw		MODER[5] rw		MODER[4] rw		MODER[3] rw		MODER[2] rw		MODER[1] rw		MODER[0] rw

Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT[15] rw	OT[14] rw	OT[13] rw	OT[12] rw	OT[11] rw	OT[10] rw	OT[9] rw	OT[8] rw	OT[7] rw	OT[6] rw	OT[5] rw	OT[4] rw	OT[3] rw	OT[2] rw	OT[1] rw	OT[0] rw

Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEEDR[15] rw		OSPEEDR[14] rw		OSPEEDR[13] rw		OSPEEDR[12] rw		OSPEEDR[11] rw		OSPEEDR[10] rw		OSPEEDR[9] rw		OSPEEDR[8] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEEDR[7] rw		OSPEEDR[6] rw		OSPEEDR[5] rw		OSPEEDR[4] rw		OSPEEDR[3] rw		OSPEEDR[2] rw		OSPEEDR[1] rw		OSPEEDR[0] rw

Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPDR[15] rw		PUPDR[14] rw		PUPDR[13] rw		PUPDR[12] rw		PUPDR[11] rw		PUPDR[10] rw		PUPDR[9] rw		PUPDR[8] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPDR[7] rw		PUPDR[6] rw		PUPDR[5] rw		PUPDR[4] rw		PUPDR[3] rw		PUPDR[2] rw		PUPDR[1] rw		PUPDR[0] rw

Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IDR[15] r	IDR[14] r	IDR[13] r	IDR[12] r	IDR[11] r	IDR[10] r	IDR[9] r	IDR[8] r	IDR[7] r	IDR[6] r	IDR[5] r	IDR[4] r	IDR[3] r	IDR[2] r	IDR[1] r	IDR[0] r

Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ODR[15] rw	ODR[14] rw	ODR[13] rw	ODR[12] rw	ODR[11] rw	ODR[10] rw	ODR[9] rw	ODR[8] rw	ODR[7] rw	ODR[6] rw	ODR[5] rw	ODR[4] rw	ODR[3] rw	ODR[2] rw	ODR[1] rw	ODR[0] rw

Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR[15] w	BR[14] w	BR[13] w	BR[12] w	BR[11] w	BR[10] w	BR[9] w	BR[8] w	BR[7] w	BR[6] w	BR[5] w	BR[4] w	BR[3] w	BR[2] w	BR[1] w	BR[0] w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS[15] w	BS[14] w	BS[13] w	BS[12] w	BS[11] w	BS[10] w	BS[9] w	BS[8] w	BS[7] w	BS[6] w	BS[5] w	BS[4] w	BS[3] w	BS[2] w	BS[1] w	BS[0] w

Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK[15] rw	LCK[14] rw	LCK[13] rw	LCK[12] rw	LCK[11] rw	LCK[10] rw	LCK[9] rw	LCK[8] rw	LCK[7] rw	LCK[6] rw	LCK[5] rw	LCK[4] rw	LCK[3] rw	LCK[2] rw	LCK[1] rw	LCK[0] rw

Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFR[L7] rw				AFR[L6] rw				AFR[L5] rw				AFR[L4] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFR[L3] rw				AFR[L2] rw				AFR[L1] rw				AFR[L0] rw

Toggle fields

AFR[L0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFR[H15] rw				AFR[H14] rw				AFR[H13] rw				AFR[H12] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFR[H11] rw				AFR[H10] rw				AFR[H9] rw				AFR[H8] rw

Toggle fields

AFR[H8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

GPIOD

0x40020c00: General-purpose I/Os

161/161 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	MODER	MODER[15]		MODER[14]		MODER[13]		MODER[12]		MODER[11]		MODER[10]		MODER[9]		MODER[8]		MODER[7]		MODER[6]		MODER[5]		MODER[4]		MODER[3]		MODER[2]		MODER[1]		MODER[0]
0x4	OTYPER																	OT[15]	OT[14]	OT[13]	OT[12]	OT[11]	OT[10]	OT[9]	OT[8]	OT[7]	OT[6]	OT[5]	OT[4]	OT[3]	OT[2]	OT[1]	OT[0]
0x8	OSPEEDR	OSPEEDR[15]		OSPEEDR[14]		OSPEEDR[13]		OSPEEDR[12]		OSPEEDR[11]		OSPEEDR[10]		OSPEEDR[9]		OSPEEDR[8]		OSPEEDR[7]		OSPEEDR[6]		OSPEEDR[5]		OSPEEDR[4]		OSPEEDR[3]		OSPEEDR[2]		OSPEEDR[1]		OSPEEDR[0]
0xc	PUPDR	PUPDR[15]		PUPDR[14]		PUPDR[13]		PUPDR[12]		PUPDR[11]		PUPDR[10]		PUPDR[9]		PUPDR[8]		PUPDR[7]		PUPDR[6]		PUPDR[5]		PUPDR[4]		PUPDR[3]		PUPDR[2]		PUPDR[1]		PUPDR[0]
0x10	IDR																	IDR[15]	IDR[14]	IDR[13]	IDR[12]	IDR[11]	IDR[10]	IDR[9]	IDR[8]	IDR[7]	IDR[6]	IDR[5]	IDR[4]	IDR[3]	IDR[2]	IDR[1]	IDR[0]
0x14	ODR																	ODR[15]	ODR[14]	ODR[13]	ODR[12]	ODR[11]	ODR[10]	ODR[9]	ODR[8]	ODR[7]	ODR[6]	ODR[5]	ODR[4]	ODR[3]	ODR[2]	ODR[1]	ODR[0]
0x18	BSRR	BR[15]	BR[14]	BR[13]	BR[12]	BR[11]	BR[10]	BR[9]	BR[8]	BR[7]	BR[6]	BR[5]	BR[4]	BR[3]	BR[2]	BR[1]	BR[0]	BS[15]	BS[14]	BS[13]	BS[12]	BS[11]	BS[10]	BS[9]	BS[8]	BS[7]	BS[6]	BS[5]	BS[4]	BS[3]	BS[2]	BS[1]	BS[0]
0x1c	LCKR																LCKK	LCK[15]	LCK[14]	LCK[13]	LCK[12]	LCK[11]	LCK[10]	LCK[9]	LCK[8]	LCK[7]	LCK[6]	LCK[5]	LCK[4]	LCK[3]	LCK[2]	LCK[1]	LCK[0]
0x20	AFRL	AFR[L7]				AFR[L6]				AFR[L5]				AFR[L4]				AFR[L3]				AFR[L2]				AFR[L1]				AFR[L0]
0x24	AFRH	AFR[H15]				AFR[H14]				AFR[H13]				AFR[H12]				AFR[H11]				AFR[H10]				AFR[H9]				AFR[H8]

Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODER[15] rw		MODER[14] rw		MODER[13] rw		MODER[12] rw		MODER[11] rw		MODER[10] rw		MODER[9] rw		MODER[8] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODER[7] rw		MODER[6] rw		MODER[5] rw		MODER[4] rw		MODER[3] rw		MODER[2] rw		MODER[1] rw		MODER[0] rw

Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT[15] rw	OT[14] rw	OT[13] rw	OT[12] rw	OT[11] rw	OT[10] rw	OT[9] rw	OT[8] rw	OT[7] rw	OT[6] rw	OT[5] rw	OT[4] rw	OT[3] rw	OT[2] rw	OT[1] rw	OT[0] rw

Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEEDR[15] rw		OSPEEDR[14] rw		OSPEEDR[13] rw		OSPEEDR[12] rw		OSPEEDR[11] rw		OSPEEDR[10] rw		OSPEEDR[9] rw		OSPEEDR[8] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEEDR[7] rw		OSPEEDR[6] rw		OSPEEDR[5] rw		OSPEEDR[4] rw		OSPEEDR[3] rw		OSPEEDR[2] rw		OSPEEDR[1] rw		OSPEEDR[0] rw

Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPDR[15] rw		PUPDR[14] rw		PUPDR[13] rw		PUPDR[12] rw		PUPDR[11] rw		PUPDR[10] rw		PUPDR[9] rw		PUPDR[8] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPDR[7] rw		PUPDR[6] rw		PUPDR[5] rw		PUPDR[4] rw		PUPDR[3] rw		PUPDR[2] rw		PUPDR[1] rw		PUPDR[0] rw

Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IDR[15] r	IDR[14] r	IDR[13] r	IDR[12] r	IDR[11] r	IDR[10] r	IDR[9] r	IDR[8] r	IDR[7] r	IDR[6] r	IDR[5] r	IDR[4] r	IDR[3] r	IDR[2] r	IDR[1] r	IDR[0] r

Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ODR[15] rw	ODR[14] rw	ODR[13] rw	ODR[12] rw	ODR[11] rw	ODR[10] rw	ODR[9] rw	ODR[8] rw	ODR[7] rw	ODR[6] rw	ODR[5] rw	ODR[4] rw	ODR[3] rw	ODR[2] rw	ODR[1] rw	ODR[0] rw

Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR[15] w	BR[14] w	BR[13] w	BR[12] w	BR[11] w	BR[10] w	BR[9] w	BR[8] w	BR[7] w	BR[6] w	BR[5] w	BR[4] w	BR[3] w	BR[2] w	BR[1] w	BR[0] w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS[15] w	BS[14] w	BS[13] w	BS[12] w	BS[11] w	BS[10] w	BS[9] w	BS[8] w	BS[7] w	BS[6] w	BS[5] w	BS[4] w	BS[3] w	BS[2] w	BS[1] w	BS[0] w

Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK[15] rw	LCK[14] rw	LCK[13] rw	LCK[12] rw	LCK[11] rw	LCK[10] rw	LCK[9] rw	LCK[8] rw	LCK[7] rw	LCK[6] rw	LCK[5] rw	LCK[4] rw	LCK[3] rw	LCK[2] rw	LCK[1] rw	LCK[0] rw

Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFR[L7] rw				AFR[L6] rw				AFR[L5] rw				AFR[L4] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFR[L3] rw				AFR[L2] rw				AFR[L1] rw				AFR[L0] rw

Toggle fields

AFR[L0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFR[H15] rw				AFR[H14] rw				AFR[H13] rw				AFR[H12] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFR[H11] rw				AFR[H10] rw				AFR[H9] rw				AFR[H8] rw

Toggle fields

AFR[H8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

GPIOE

0x40021000: General-purpose I/Os

161/161 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	MODER	MODER[15]		MODER[14]		MODER[13]		MODER[12]		MODER[11]		MODER[10]		MODER[9]		MODER[8]		MODER[7]		MODER[6]		MODER[5]		MODER[4]		MODER[3]		MODER[2]		MODER[1]		MODER[0]
0x4	OTYPER																	OT[15]	OT[14]	OT[13]	OT[12]	OT[11]	OT[10]	OT[9]	OT[8]	OT[7]	OT[6]	OT[5]	OT[4]	OT[3]	OT[2]	OT[1]	OT[0]
0x8	OSPEEDR	OSPEEDR[15]		OSPEEDR[14]		OSPEEDR[13]		OSPEEDR[12]		OSPEEDR[11]		OSPEEDR[10]		OSPEEDR[9]		OSPEEDR[8]		OSPEEDR[7]		OSPEEDR[6]		OSPEEDR[5]		OSPEEDR[4]		OSPEEDR[3]		OSPEEDR[2]		OSPEEDR[1]		OSPEEDR[0]
0xc	PUPDR	PUPDR[15]		PUPDR[14]		PUPDR[13]		PUPDR[12]		PUPDR[11]		PUPDR[10]		PUPDR[9]		PUPDR[8]		PUPDR[7]		PUPDR[6]		PUPDR[5]		PUPDR[4]		PUPDR[3]		PUPDR[2]		PUPDR[1]		PUPDR[0]
0x10	IDR																	IDR[15]	IDR[14]	IDR[13]	IDR[12]	IDR[11]	IDR[10]	IDR[9]	IDR[8]	IDR[7]	IDR[6]	IDR[5]	IDR[4]	IDR[3]	IDR[2]	IDR[1]	IDR[0]
0x14	ODR																	ODR[15]	ODR[14]	ODR[13]	ODR[12]	ODR[11]	ODR[10]	ODR[9]	ODR[8]	ODR[7]	ODR[6]	ODR[5]	ODR[4]	ODR[3]	ODR[2]	ODR[1]	ODR[0]
0x18	BSRR	BR[15]	BR[14]	BR[13]	BR[12]	BR[11]	BR[10]	BR[9]	BR[8]	BR[7]	BR[6]	BR[5]	BR[4]	BR[3]	BR[2]	BR[1]	BR[0]	BS[15]	BS[14]	BS[13]	BS[12]	BS[11]	BS[10]	BS[9]	BS[8]	BS[7]	BS[6]	BS[5]	BS[4]	BS[3]	BS[2]	BS[1]	BS[0]
0x1c	LCKR																LCKK	LCK[15]	LCK[14]	LCK[13]	LCK[12]	LCK[11]	LCK[10]	LCK[9]	LCK[8]	LCK[7]	LCK[6]	LCK[5]	LCK[4]	LCK[3]	LCK[2]	LCK[1]	LCK[0]
0x20	AFRL	AFR[L7]				AFR[L6]				AFR[L5]				AFR[L4]				AFR[L3]				AFR[L2]				AFR[L1]				AFR[L0]
0x24	AFRH	AFR[H15]				AFR[H14]				AFR[H13]				AFR[H12]				AFR[H11]				AFR[H10]				AFR[H9]				AFR[H8]

Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODER[15] rw		MODER[14] rw		MODER[13] rw		MODER[12] rw		MODER[11] rw		MODER[10] rw		MODER[9] rw		MODER[8] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODER[7] rw		MODER[6] rw		MODER[5] rw		MODER[4] rw		MODER[3] rw		MODER[2] rw		MODER[1] rw		MODER[0] rw

Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT[15] rw	OT[14] rw	OT[13] rw	OT[12] rw	OT[11] rw	OT[10] rw	OT[9] rw	OT[8] rw	OT[7] rw	OT[6] rw	OT[5] rw	OT[4] rw	OT[3] rw	OT[2] rw	OT[1] rw	OT[0] rw

Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEEDR[15] rw		OSPEEDR[14] rw		OSPEEDR[13] rw		OSPEEDR[12] rw		OSPEEDR[11] rw		OSPEEDR[10] rw		OSPEEDR[9] rw		OSPEEDR[8] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEEDR[7] rw		OSPEEDR[6] rw		OSPEEDR[5] rw		OSPEEDR[4] rw		OSPEEDR[3] rw		OSPEEDR[2] rw		OSPEEDR[1] rw		OSPEEDR[0] rw

Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPDR[15] rw		PUPDR[14] rw		PUPDR[13] rw		PUPDR[12] rw		PUPDR[11] rw		PUPDR[10] rw		PUPDR[9] rw		PUPDR[8] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPDR[7] rw		PUPDR[6] rw		PUPDR[5] rw		PUPDR[4] rw		PUPDR[3] rw		PUPDR[2] rw		PUPDR[1] rw		PUPDR[0] rw

Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IDR[15] r	IDR[14] r	IDR[13] r	IDR[12] r	IDR[11] r	IDR[10] r	IDR[9] r	IDR[8] r	IDR[7] r	IDR[6] r	IDR[5] r	IDR[4] r	IDR[3] r	IDR[2] r	IDR[1] r	IDR[0] r

Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ODR[15] rw	ODR[14] rw	ODR[13] rw	ODR[12] rw	ODR[11] rw	ODR[10] rw	ODR[9] rw	ODR[8] rw	ODR[7] rw	ODR[6] rw	ODR[5] rw	ODR[4] rw	ODR[3] rw	ODR[2] rw	ODR[1] rw	ODR[0] rw

Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR[15] w	BR[14] w	BR[13] w	BR[12] w	BR[11] w	BR[10] w	BR[9] w	BR[8] w	BR[7] w	BR[6] w	BR[5] w	BR[4] w	BR[3] w	BR[2] w	BR[1] w	BR[0] w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS[15] w	BS[14] w	BS[13] w	BS[12] w	BS[11] w	BS[10] w	BS[9] w	BS[8] w	BS[7] w	BS[6] w	BS[5] w	BS[4] w	BS[3] w	BS[2] w	BS[1] w	BS[0] w

Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK[15] rw	LCK[14] rw	LCK[13] rw	LCK[12] rw	LCK[11] rw	LCK[10] rw	LCK[9] rw	LCK[8] rw	LCK[7] rw	LCK[6] rw	LCK[5] rw	LCK[4] rw	LCK[3] rw	LCK[2] rw	LCK[1] rw	LCK[0] rw

Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFR[L7] rw				AFR[L6] rw				AFR[L5] rw				AFR[L4] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFR[L3] rw				AFR[L2] rw				AFR[L1] rw				AFR[L0] rw

Toggle fields

AFR[L0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFR[H15] rw				AFR[H14] rw				AFR[H13] rw				AFR[H12] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFR[H11] rw				AFR[H10] rw				AFR[H9] rw				AFR[H8] rw

Toggle fields

AFR[H8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

GPIOH

0x40021c00: General-purpose I/Os

161/161 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	MODER	MODER[15]		MODER[14]		MODER[13]		MODER[12]		MODER[11]		MODER[10]		MODER[9]		MODER[8]		MODER[7]		MODER[6]		MODER[5]		MODER[4]		MODER[3]		MODER[2]		MODER[1]		MODER[0]
0x4	OTYPER																	OT[15]	OT[14]	OT[13]	OT[12]	OT[11]	OT[10]	OT[9]	OT[8]	OT[7]	OT[6]	OT[5]	OT[4]	OT[3]	OT[2]	OT[1]	OT[0]
0x8	OSPEEDR	OSPEEDR[15]		OSPEEDR[14]		OSPEEDR[13]		OSPEEDR[12]		OSPEEDR[11]		OSPEEDR[10]		OSPEEDR[9]		OSPEEDR[8]		OSPEEDR[7]		OSPEEDR[6]		OSPEEDR[5]		OSPEEDR[4]		OSPEEDR[3]		OSPEEDR[2]		OSPEEDR[1]		OSPEEDR[0]
0xc	PUPDR	PUPDR[15]		PUPDR[14]		PUPDR[13]		PUPDR[12]		PUPDR[11]		PUPDR[10]		PUPDR[9]		PUPDR[8]		PUPDR[7]		PUPDR[6]		PUPDR[5]		PUPDR[4]		PUPDR[3]		PUPDR[2]		PUPDR[1]		PUPDR[0]
0x10	IDR																	IDR[15]	IDR[14]	IDR[13]	IDR[12]	IDR[11]	IDR[10]	IDR[9]	IDR[8]	IDR[7]	IDR[6]	IDR[5]	IDR[4]	IDR[3]	IDR[2]	IDR[1]	IDR[0]
0x14	ODR																	ODR[15]	ODR[14]	ODR[13]	ODR[12]	ODR[11]	ODR[10]	ODR[9]	ODR[8]	ODR[7]	ODR[6]	ODR[5]	ODR[4]	ODR[3]	ODR[2]	ODR[1]	ODR[0]
0x18	BSRR	BR[15]	BR[14]	BR[13]	BR[12]	BR[11]	BR[10]	BR[9]	BR[8]	BR[7]	BR[6]	BR[5]	BR[4]	BR[3]	BR[2]	BR[1]	BR[0]	BS[15]	BS[14]	BS[13]	BS[12]	BS[11]	BS[10]	BS[9]	BS[8]	BS[7]	BS[6]	BS[5]	BS[4]	BS[3]	BS[2]	BS[1]	BS[0]
0x1c	LCKR																LCKK	LCK[15]	LCK[14]	LCK[13]	LCK[12]	LCK[11]	LCK[10]	LCK[9]	LCK[8]	LCK[7]	LCK[6]	LCK[5]	LCK[4]	LCK[3]	LCK[2]	LCK[1]	LCK[0]
0x20	AFRL	AFR[L7]				AFR[L6]				AFR[L5]				AFR[L4]				AFR[L3]				AFR[L2]				AFR[L1]				AFR[L0]
0x24	AFRH	AFR[H15]				AFR[H14]				AFR[H13]				AFR[H12]				AFR[H11]				AFR[H10]				AFR[H9]				AFR[H8]

Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODER[15] rw		MODER[14] rw		MODER[13] rw		MODER[12] rw		MODER[11] rw		MODER[10] rw		MODER[9] rw		MODER[8] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODER[7] rw		MODER[6] rw		MODER[5] rw		MODER[4] rw		MODER[3] rw		MODER[2] rw		MODER[1] rw		MODER[0] rw

Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT[15] rw	OT[14] rw	OT[13] rw	OT[12] rw	OT[11] rw	OT[10] rw	OT[9] rw	OT[8] rw	OT[7] rw	OT[6] rw	OT[5] rw	OT[4] rw	OT[3] rw	OT[2] rw	OT[1] rw	OT[0] rw

Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEEDR[15] rw		OSPEEDR[14] rw		OSPEEDR[13] rw		OSPEEDR[12] rw		OSPEEDR[11] rw		OSPEEDR[10] rw		OSPEEDR[9] rw		OSPEEDR[8] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEEDR[7] rw		OSPEEDR[6] rw		OSPEEDR[5] rw		OSPEEDR[4] rw		OSPEEDR[3] rw		OSPEEDR[2] rw		OSPEEDR[1] rw		OSPEEDR[0] rw

Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPDR[15] rw		PUPDR[14] rw		PUPDR[13] rw		PUPDR[12] rw		PUPDR[11] rw		PUPDR[10] rw		PUPDR[9] rw		PUPDR[8] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPDR[7] rw		PUPDR[6] rw		PUPDR[5] rw		PUPDR[4] rw		PUPDR[3] rw		PUPDR[2] rw		PUPDR[1] rw		PUPDR[0] rw

Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IDR[15] r	IDR[14] r	IDR[13] r	IDR[12] r	IDR[11] r	IDR[10] r	IDR[9] r	IDR[8] r	IDR[7] r	IDR[6] r	IDR[5] r	IDR[4] r	IDR[3] r	IDR[2] r	IDR[1] r	IDR[0] r

Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ODR[15] rw	ODR[14] rw	ODR[13] rw	ODR[12] rw	ODR[11] rw	ODR[10] rw	ODR[9] rw	ODR[8] rw	ODR[7] rw	ODR[6] rw	ODR[5] rw	ODR[4] rw	ODR[3] rw	ODR[2] rw	ODR[1] rw	ODR[0] rw

Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR[15] w	BR[14] w	BR[13] w	BR[12] w	BR[11] w	BR[10] w	BR[9] w	BR[8] w	BR[7] w	BR[6] w	BR[5] w	BR[4] w	BR[3] w	BR[2] w	BR[1] w	BR[0] w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS[15] w	BS[14] w	BS[13] w	BS[12] w	BS[11] w	BS[10] w	BS[9] w	BS[8] w	BS[7] w	BS[6] w	BS[5] w	BS[4] w	BS[3] w	BS[2] w	BS[1] w	BS[0] w

Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK[15] rw	LCK[14] rw	LCK[13] rw	LCK[12] rw	LCK[11] rw	LCK[10] rw	LCK[9] rw	LCK[8] rw	LCK[7] rw	LCK[6] rw	LCK[5] rw	LCK[4] rw	LCK[3] rw	LCK[2] rw	LCK[1] rw	LCK[0] rw

Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFR[L7] rw				AFR[L6] rw				AFR[L5] rw				AFR[L4] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFR[L3] rw				AFR[L2] rw				AFR[L1] rw				AFR[L0] rw

Toggle fields

AFR[L0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFR[H15] rw				AFR[H14] rw				AFR[H13] rw				AFR[H12] rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFR[H11] rw				AFR[H10] rw				AFR[H9] rw				AFR[H8] rw

Toggle fields

AFR[H8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

I2C1

0x40005400: Inter-integrated circuit

53/53 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1	SWRST		ALERT	PEC	POS	ACK	STOP	START	NOSTRETCH	ENGC	ENPEC	ENARP	SMBTYPE		SMBUS	PE
0x4	CR2				LAST	DMAEN	ITBUFEN	ITEVTEN	ITERREN			FREQ
0x8	OAR1	ADDMODE						ADD
0xc	OAR2									ADD2							ENDUAL
0x10	DR									DR
0x14	SR1	SMBALERT	TIMEOUT		PECERR	OVR	AF	ARLO	BERR	TxE	RxNE		STOPF	ADD10	BTF	ADDR	SB
0x18	SR2	PEC								DUALF	SMBHOST	SMBDEFAULT	GENCALL		TRA	BUSY	MSL
0x1c	CCR	F_S	DUTY			CCR
0x20	TRISE											TRISE
0x24	FLTR												ANOFF	DNF

Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWRST rw		ALERT rw	PEC rw	POS rw	ACK rw	STOP rw	START rw	NOSTRETCH rw	ENGC rw	ENPEC rw	ENARP rw	SMBTYPE rw		SMBUS rw	PE rw

Toggle fields

PE

Bit 0: Peripheral enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

SMBUS

Bit 1: SMBus mode.

Allowed values:
0: I2C: I2C Mode
1: SMBus: SMBus

SMBTYPE

Bit 3: SMBus type.

Allowed values:
0: Device: SMBus Device
1: Host: SMBus Host

ENARP

Bit 4: ARP enable.

Allowed values:
0: Disabled: ARP disabled
1: Enabled: ARP enabled

ENPEC

Bit 5: PEC enable.

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

ENGC

Bit 6: General call enable.

Allowed values:
0: Disabled: General call disabled
1: Enabled: General call enabled

NOSTRETCH

Bit 7: Clock stretching disable (Slave mode).

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

START

Bit 8: Start generation.

Allowed values:
0: NoStart: No Start generation
1: Start: In master mode: repeated start generation, in slave mode: start generation when bus is free

STOP

Bit 9: Stop generation.

Allowed values:
0: NoStop: No Stop generation
1: Stop: In master mode: stop generation after current byte/start, in slave mode: release SCL and SDA after current byte

ACK

Bit 10: Acknowledge enable.

Allowed values:
0: NAK: No acknowledge returned
1: ACK: Acknowledge returned after a byte is received

POS

Bit 11: Acknowledge/PEC Position (for data reception).

Allowed values:
0: Current: ACK bit controls the (N)ACK of the current byte being received
1: Next: ACK bit controls the (N)ACK of the next byte to be received

PEC

Bit 12: Packet error checking.

Allowed values:
0: Disabled: No PEC transfer
1: Enabled: PEC transfer

ALERT

Bit 13: SMBus alert.

Allowed values:
0: Release: SMBA pin released high
1: Drive: SMBA pin driven low

SWRST

Bit 15: Software reset.

Allowed values:
0: NotReset: I2C peripheral not under reset
1: Reset: I2C peripheral under reset

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			LAST rw	DMAEN rw	ITBUFEN rw	ITEVTEN rw	ITERREN rw			FREQ rw

Toggle fields

FREQ

Bits 0-5: Peripheral clock frequency.

Allowed values: 0x2-0x32

ITERREN

Bit 8: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

ITEVTEN

Bit 9: Event interrupt enable.

Allowed values:
0: Disabled: Event interrupt disabled
1: Enabled: Event interrupt enabled

ITBUFEN

Bit 10: Buffer interrupt enable.

Allowed values:
0: Disabled: TxE=1 or RxNE=1 does not generate any interrupt
1: Enabled: TxE=1 or RxNE=1 generates Event interrupt

DMAEN

Bit 11: DMA requests enable.

Allowed values:
0: Disabled: DMA requests disabled
1: Enabled: DMA request enabled when TxE=1 or RxNE=1

LAST

Bit 12: DMA last transfer.

Allowed values:
0: NotLast: Next DMA EOT is not the last transfer
1: Last: Next DMA EOT is the last transfer

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDMODE rw						ADD rw

Toggle fields

ADD

Bits 0-9: Interface address.

Allowed values: 0x0-0x3ff

ADDMODE

Bit 15: Addressing mode (slave mode).

Allowed values:
0: ADD7: 7-bit slave address
1: ADD10: 10-bit slave address

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								ADD2 rw							ENDUAL rw

Toggle fields

ENDUAL

Bit 0: Dual addressing mode enable.

Allowed values:
0: Single: Single addressing mode
1: Dual: Dual addressing mode

ADD2

Bits 1-7: Interface address.

Allowed values: 0x0-0x7f

DR

Data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								DR rw

Toggle fields

DR

Bits 0-7: 8-bit data register.

Allowed values: 0x0-0xff

SR1

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

14/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SMBALERT rw	TIMEOUT rw		PECERR rw	OVR rw	AF rw	ARLO rw	BERR rw	TxE r	RxNE r		STOPF r	ADD10 r	BTF r	ADDR r	SB r

Toggle fields

SB

Bit 0: Start bit (Master mode).

Allowed values:
0: NoStart: No Start condition
1: Start: Start condition generated

ADDR

Bit 1: Address sent (master mode)/matched (slave mode).

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

BTF

Bit 2: Byte transfer finished.

Allowed values:
0: NotFinished: Data byte transfer not done
1: Finished: Data byte transfer successful

ADD10

Bit 3: 10-bit header sent (Master mode).

STOPF

Bit 4: Stop detection (slave mode).

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

RxNE

Bit 6: Data register not empty (receivers).

Allowed values:
0: Empty: Data register empty
1: NotEmpty: Data register not empty

TxE

Bit 7: Data register empty (transmitters).

Allowed values:
0: NotEmpty: Data register not empty
1: Empty: Data register empty

BERR

Bit 8: Bus error.

Allowed values:
0: NoError: No misplaced Start or Stop condition
1: Error: Misplaced Start or Stop condition

ARLO

Bit 9: Arbitration lost (master mode).

Allowed values:
0: NoLost: No Arbitration Lost detected
1: Lost: Arbitration Lost detected

AF

Bit 10: Acknowledge failure.

Allowed values:
0: NoFailure: No acknowledge failure
1: Failure: Acknowledge failure

OVR

Bit 11: Overrun/Underrun.

Allowed values:
0: NoOverrun: No overrun/underrun occured
1: Overrun: Overrun/underrun occured

PECERR

Bit 12: PEC Error in reception.

Allowed values:
0: NoError: no PEC error: receiver returns ACK after PEC reception (if ACK=1)
1: Error: PEC error: receiver returns NACK after PEC reception (whatever ACK)

TIMEOUT

Bit 14: Timeout or Tlow error.

Allowed values:
0: NoTimeout: No Timeout error
1: Timeout: SCL remained LOW for 25 ms

SMBALERT

Bit 15: SMBus alert.

Allowed values:
0: NoAlert: No SMBALERT occured
1: Alert: SMBALERT occurred

SR2

Status register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PEC r								DUALF r	SMBHOST r	SMBDEFAULT r	GENCALL r		TRA r	BUSY r	MSL r

Toggle fields

MSL

Bit 0: Master/slave.

BUSY

Bit 1: Bus busy.

TRA

Bit 2: Transmitter/receiver.

GENCALL

Bit 4: General call address (Slave mode).

SMBDEFAULT

Bit 5: SMBus device default address (Slave mode).

SMBHOST

Bit 6: SMBus host header (Slave mode).

DUALF

Bit 7: Dual flag (Slave mode).

PEC

Bits 8-15: acket error checking register.

CCR

Clock control register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
F_S rw	DUTY rw			CCR rw

Toggle fields

CCR

Bits 0-11: Clock control register in Fast/Standard mode (Master mode).

Allowed values: 0x1-0xfff

DUTY

Bit 14: Fast mode duty cycle.

Allowed values:
0: Duty2_1: Duty cycle t_low/t_high = 2/1
1: Duty16_9: Duty cycle t_low/t_high = 16/9

F_S

Bit 15: I2C master mode selection.

Allowed values:
0: Standard: Standard mode I2C
1: Fast: Fast mode I2C

TRISE

TRISE register

Offset: 0x20, size: 32, reset: 0x00000002, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										TRISE rw

Toggle fields

TRISE

Bits 0-5: Maximum rise time in Fast/Standard mode (Master mode).

Allowed values: 0x0-0x3f

FLTR

FLTR register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											ANOFF rw	DNF rw

Toggle fields

DNF

Bits 0-3: Digital noise filter.

Allowed values:
0: NoFilter: Digital filter disabled
1: Filter1: Digital filter enabled and filtering capability up to 1 tI2CCLK
2: Filter2: Digital filter enabled and filtering capability up to 2 tI2CCLK
3: Filter3: Digital filter enabled and filtering capability up to 3 tI2CCLK
4: Filter4: Digital filter enabled and filtering capability up to 4 tI2CCLK
5: Filter5: Digital filter enabled and filtering capability up to 5 tI2CCLK
6: Filter6: Digital filter enabled and filtering capability up to 6 tI2CCLK
7: Filter7: Digital filter enabled and filtering capability up to 7 tI2CCLK
8: Filter8: Digital filter enabled and filtering capability up to 8 tI2CCLK
9: Filter9: Digital filter enabled and filtering capability up to 9 tI2CCLK
10: Filter10: Digital filter enabled and filtering capability up to 10 tI2CCLK
11: Filter11: Digital filter enabled and filtering capability up to 11 tI2CCLK
12: Filter12: Digital filter enabled and filtering capability up to 12 tI2CCLK
13: Filter13: Digital filter enabled and filtering capability up to 13 tI2CCLK
14: Filter14: Digital filter enabled and filtering capability up to 14 tI2CCLK
15: Filter15: Digital filter enabled and filtering capability up to 15 tI2CCLK

ANOFF

Bit 4: Analog noise filter.

Allowed values:
0: Enabled: Analog noise filter enabled
1: Disabled: Analog noise filter disabled

I2C2

0x40005800: Inter-integrated circuit

53/53 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1	SWRST		ALERT	PEC	POS	ACK	STOP	START	NOSTRETCH	ENGC	ENPEC	ENARP	SMBTYPE		SMBUS	PE
0x4	CR2				LAST	DMAEN	ITBUFEN	ITEVTEN	ITERREN			FREQ
0x8	OAR1	ADDMODE						ADD
0xc	OAR2									ADD2							ENDUAL
0x10	DR									DR
0x14	SR1	SMBALERT	TIMEOUT		PECERR	OVR	AF	ARLO	BERR	TxE	RxNE		STOPF	ADD10	BTF	ADDR	SB
0x18	SR2	PEC								DUALF	SMBHOST	SMBDEFAULT	GENCALL		TRA	BUSY	MSL
0x1c	CCR	F_S	DUTY			CCR
0x20	TRISE											TRISE
0x24	FLTR												ANOFF	DNF

Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWRST rw		ALERT rw	PEC rw	POS rw	ACK rw	STOP rw	START rw	NOSTRETCH rw	ENGC rw	ENPEC rw	ENARP rw	SMBTYPE rw		SMBUS rw	PE rw

Toggle fields

PE

Bit 0: Peripheral enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

SMBUS

Bit 1: SMBus mode.

Allowed values:
0: I2C: I2C Mode
1: SMBus: SMBus

SMBTYPE

Bit 3: SMBus type.

Allowed values:
0: Device: SMBus Device
1: Host: SMBus Host

ENARP

Bit 4: ARP enable.

Allowed values:
0: Disabled: ARP disabled
1: Enabled: ARP enabled

ENPEC

Bit 5: PEC enable.

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

ENGC

Bit 6: General call enable.

Allowed values:
0: Disabled: General call disabled
1: Enabled: General call enabled

NOSTRETCH

Bit 7: Clock stretching disable (Slave mode).

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

START

Bit 8: Start generation.

Allowed values:
0: NoStart: No Start generation
1: Start: In master mode: repeated start generation, in slave mode: start generation when bus is free

STOP

Bit 9: Stop generation.

Allowed values:
0: NoStop: No Stop generation
1: Stop: In master mode: stop generation after current byte/start, in slave mode: release SCL and SDA after current byte

ACK

Bit 10: Acknowledge enable.

Allowed values:
0: NAK: No acknowledge returned
1: ACK: Acknowledge returned after a byte is received

POS

Bit 11: Acknowledge/PEC Position (for data reception).

Allowed values:
0: Current: ACK bit controls the (N)ACK of the current byte being received
1: Next: ACK bit controls the (N)ACK of the next byte to be received

PEC

Bit 12: Packet error checking.

Allowed values:
0: Disabled: No PEC transfer
1: Enabled: PEC transfer

ALERT

Bit 13: SMBus alert.

Allowed values:
0: Release: SMBA pin released high
1: Drive: SMBA pin driven low

SWRST

Bit 15: Software reset.

Allowed values:
0: NotReset: I2C peripheral not under reset
1: Reset: I2C peripheral under reset

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			LAST rw	DMAEN rw	ITBUFEN rw	ITEVTEN rw	ITERREN rw			FREQ rw

Toggle fields

FREQ

Bits 0-5: Peripheral clock frequency.

Allowed values: 0x2-0x32

ITERREN

Bit 8: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

ITEVTEN

Bit 9: Event interrupt enable.

Allowed values:
0: Disabled: Event interrupt disabled
1: Enabled: Event interrupt enabled

ITBUFEN

Bit 10: Buffer interrupt enable.

Allowed values:
0: Disabled: TxE=1 or RxNE=1 does not generate any interrupt
1: Enabled: TxE=1 or RxNE=1 generates Event interrupt

DMAEN

Bit 11: DMA requests enable.

Allowed values:
0: Disabled: DMA requests disabled
1: Enabled: DMA request enabled when TxE=1 or RxNE=1

LAST

Bit 12: DMA last transfer.

Allowed values:
0: NotLast: Next DMA EOT is not the last transfer
1: Last: Next DMA EOT is the last transfer

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDMODE rw						ADD rw

Toggle fields

ADD

Bits 0-9: Interface address.

Allowed values: 0x0-0x3ff

ADDMODE

Bit 15: Addressing mode (slave mode).

Allowed values:
0: ADD7: 7-bit slave address
1: ADD10: 10-bit slave address

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								ADD2 rw							ENDUAL rw

Toggle fields

ENDUAL

Bit 0: Dual addressing mode enable.

Allowed values:
0: Single: Single addressing mode
1: Dual: Dual addressing mode

ADD2

Bits 1-7: Interface address.

Allowed values: 0x0-0x7f

DR

Data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								DR rw

Toggle fields

DR

Bits 0-7: 8-bit data register.

Allowed values: 0x0-0xff

SR1

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

14/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SMBALERT rw	TIMEOUT rw		PECERR rw	OVR rw	AF rw	ARLO rw	BERR rw	TxE r	RxNE r		STOPF r	ADD10 r	BTF r	ADDR r	SB r

Toggle fields

SB

Bit 0: Start bit (Master mode).

Allowed values:
0: NoStart: No Start condition
1: Start: Start condition generated

ADDR

Bit 1: Address sent (master mode)/matched (slave mode).

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

BTF

Bit 2: Byte transfer finished.

Allowed values:
0: NotFinished: Data byte transfer not done
1: Finished: Data byte transfer successful

ADD10

Bit 3: 10-bit header sent (Master mode).

STOPF

Bit 4: Stop detection (slave mode).

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

RxNE

Bit 6: Data register not empty (receivers).

Allowed values:
0: Empty: Data register empty
1: NotEmpty: Data register not empty

TxE

Bit 7: Data register empty (transmitters).

Allowed values:
0: NotEmpty: Data register not empty
1: Empty: Data register empty

BERR

Bit 8: Bus error.

Allowed values:
0: NoError: No misplaced Start or Stop condition
1: Error: Misplaced Start or Stop condition

ARLO

Bit 9: Arbitration lost (master mode).

Allowed values:
0: NoLost: No Arbitration Lost detected
1: Lost: Arbitration Lost detected

AF

Bit 10: Acknowledge failure.

Allowed values:
0: NoFailure: No acknowledge failure
1: Failure: Acknowledge failure

OVR

Bit 11: Overrun/Underrun.

Allowed values:
0: NoOverrun: No overrun/underrun occured
1: Overrun: Overrun/underrun occured

PECERR

Bit 12: PEC Error in reception.

Allowed values:
0: NoError: no PEC error: receiver returns ACK after PEC reception (if ACK=1)
1: Error: PEC error: receiver returns NACK after PEC reception (whatever ACK)

TIMEOUT

Bit 14: Timeout or Tlow error.

Allowed values:
0: NoTimeout: No Timeout error
1: Timeout: SCL remained LOW for 25 ms

SMBALERT

Bit 15: SMBus alert.

Allowed values:
0: NoAlert: No SMBALERT occured
1: Alert: SMBALERT occurred

SR2

Status register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PEC r								DUALF r	SMBHOST r	SMBDEFAULT r	GENCALL r		TRA r	BUSY r	MSL r

Toggle fields

MSL

Bit 0: Master/slave.

BUSY

Bit 1: Bus busy.

TRA

Bit 2: Transmitter/receiver.

GENCALL

Bit 4: General call address (Slave mode).

SMBDEFAULT

Bit 5: SMBus device default address (Slave mode).

SMBHOST

Bit 6: SMBus host header (Slave mode).

DUALF

Bit 7: Dual flag (Slave mode).

PEC

Bits 8-15: acket error checking register.

CCR

Clock control register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
F_S rw	DUTY rw			CCR rw

Toggle fields

CCR

Bits 0-11: Clock control register in Fast/Standard mode (Master mode).

Allowed values: 0x1-0xfff

DUTY

Bit 14: Fast mode duty cycle.

Allowed values:
0: Duty2_1: Duty cycle t_low/t_high = 2/1
1: Duty16_9: Duty cycle t_low/t_high = 16/9

F_S

Bit 15: I2C master mode selection.

Allowed values:
0: Standard: Standard mode I2C
1: Fast: Fast mode I2C

TRISE

TRISE register

Offset: 0x20, size: 32, reset: 0x00000002, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										TRISE rw

Toggle fields

TRISE

Bits 0-5: Maximum rise time in Fast/Standard mode (Master mode).

Allowed values: 0x0-0x3f

FLTR

FLTR register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											ANOFF rw	DNF rw

Toggle fields

DNF

Bits 0-3: Digital noise filter.

Allowed values:
0: NoFilter: Digital filter disabled
1: Filter1: Digital filter enabled and filtering capability up to 1 tI2CCLK
2: Filter2: Digital filter enabled and filtering capability up to 2 tI2CCLK
3: Filter3: Digital filter enabled and filtering capability up to 3 tI2CCLK
4: Filter4: Digital filter enabled and filtering capability up to 4 tI2CCLK
5: Filter5: Digital filter enabled and filtering capability up to 5 tI2CCLK
6: Filter6: Digital filter enabled and filtering capability up to 6 tI2CCLK
7: Filter7: Digital filter enabled and filtering capability up to 7 tI2CCLK
8: Filter8: Digital filter enabled and filtering capability up to 8 tI2CCLK
9: Filter9: Digital filter enabled and filtering capability up to 9 tI2CCLK
10: Filter10: Digital filter enabled and filtering capability up to 10 tI2CCLK
11: Filter11: Digital filter enabled and filtering capability up to 11 tI2CCLK
12: Filter12: Digital filter enabled and filtering capability up to 12 tI2CCLK
13: Filter13: Digital filter enabled and filtering capability up to 13 tI2CCLK
14: Filter14: Digital filter enabled and filtering capability up to 14 tI2CCLK
15: Filter15: Digital filter enabled and filtering capability up to 15 tI2CCLK

ANOFF

Bit 4: Analog noise filter.

Allowed values:
0: Enabled: Analog noise filter enabled
1: Disabled: Analog noise filter disabled

I2C3

0x40005c00: Inter-integrated circuit

53/53 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1	SWRST		ALERT	PEC	POS	ACK	STOP	START	NOSTRETCH	ENGC	ENPEC	ENARP	SMBTYPE		SMBUS	PE
0x4	CR2				LAST	DMAEN	ITBUFEN	ITEVTEN	ITERREN			FREQ
0x8	OAR1	ADDMODE						ADD
0xc	OAR2									ADD2							ENDUAL
0x10	DR									DR
0x14	SR1	SMBALERT	TIMEOUT		PECERR	OVR	AF	ARLO	BERR	TxE	RxNE		STOPF	ADD10	BTF	ADDR	SB
0x18	SR2	PEC								DUALF	SMBHOST	SMBDEFAULT	GENCALL		TRA	BUSY	MSL
0x1c	CCR	F_S	DUTY			CCR
0x20	TRISE											TRISE
0x24	FLTR												ANOFF	DNF

Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWRST rw		ALERT rw	PEC rw	POS rw	ACK rw	STOP rw	START rw	NOSTRETCH rw	ENGC rw	ENPEC rw	ENARP rw	SMBTYPE rw		SMBUS rw	PE rw

Toggle fields

PE

Bit 0: Peripheral enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

SMBUS

Bit 1: SMBus mode.

Allowed values:
0: I2C: I2C Mode
1: SMBus: SMBus

SMBTYPE

Bit 3: SMBus type.

Allowed values:
0: Device: SMBus Device
1: Host: SMBus Host

ENARP

Bit 4: ARP enable.

Allowed values:
0: Disabled: ARP disabled
1: Enabled: ARP enabled

ENPEC

Bit 5: PEC enable.

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

ENGC

Bit 6: General call enable.

Allowed values:
0: Disabled: General call disabled
1: Enabled: General call enabled

NOSTRETCH

Bit 7: Clock stretching disable (Slave mode).

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

START

Bit 8: Start generation.

Allowed values:
0: NoStart: No Start generation
1: Start: In master mode: repeated start generation, in slave mode: start generation when bus is free

STOP

Bit 9: Stop generation.

Allowed values:
0: NoStop: No Stop generation
1: Stop: In master mode: stop generation after current byte/start, in slave mode: release SCL and SDA after current byte

ACK

Bit 10: Acknowledge enable.

Allowed values:
0: NAK: No acknowledge returned
1: ACK: Acknowledge returned after a byte is received

POS

Bit 11: Acknowledge/PEC Position (for data reception).

Allowed values:
0: Current: ACK bit controls the (N)ACK of the current byte being received
1: Next: ACK bit controls the (N)ACK of the next byte to be received

PEC

Bit 12: Packet error checking.

Allowed values:
0: Disabled: No PEC transfer
1: Enabled: PEC transfer

ALERT

Bit 13: SMBus alert.

Allowed values:
0: Release: SMBA pin released high
1: Drive: SMBA pin driven low

SWRST

Bit 15: Software reset.

Allowed values:
0: NotReset: I2C peripheral not under reset
1: Reset: I2C peripheral under reset

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			LAST rw	DMAEN rw	ITBUFEN rw	ITEVTEN rw	ITERREN rw			FREQ rw

Toggle fields

FREQ

Bits 0-5: Peripheral clock frequency.

Allowed values: 0x2-0x32

ITERREN

Bit 8: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

ITEVTEN

Bit 9: Event interrupt enable.

Allowed values:
0: Disabled: Event interrupt disabled
1: Enabled: Event interrupt enabled

ITBUFEN

Bit 10: Buffer interrupt enable.

Allowed values:
0: Disabled: TxE=1 or RxNE=1 does not generate any interrupt
1: Enabled: TxE=1 or RxNE=1 generates Event interrupt

DMAEN

Bit 11: DMA requests enable.

Allowed values:
0: Disabled: DMA requests disabled
1: Enabled: DMA request enabled when TxE=1 or RxNE=1

LAST

Bit 12: DMA last transfer.

Allowed values:
0: NotLast: Next DMA EOT is not the last transfer
1: Last: Next DMA EOT is the last transfer

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDMODE rw						ADD rw

Toggle fields

ADD

Bits 0-9: Interface address.

Allowed values: 0x0-0x3ff

ADDMODE

Bit 15: Addressing mode (slave mode).

Allowed values:
0: ADD7: 7-bit slave address
1: ADD10: 10-bit slave address

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								ADD2 rw							ENDUAL rw

Toggle fields

ENDUAL

Bit 0: Dual addressing mode enable.

Allowed values:
0: Single: Single addressing mode
1: Dual: Dual addressing mode

ADD2

Bits 1-7: Interface address.

Allowed values: 0x0-0x7f

DR

Data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								DR rw

Toggle fields

DR

Bits 0-7: 8-bit data register.

Allowed values: 0x0-0xff

SR1

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

14/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SMBALERT rw	TIMEOUT rw		PECERR rw	OVR rw	AF rw	ARLO rw	BERR rw	TxE r	RxNE r		STOPF r	ADD10 r	BTF r	ADDR r	SB r

Toggle fields

SB

Bit 0: Start bit (Master mode).

Allowed values:
0: NoStart: No Start condition
1: Start: Start condition generated

ADDR

Bit 1: Address sent (master mode)/matched (slave mode).

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

BTF

Bit 2: Byte transfer finished.

Allowed values:
0: NotFinished: Data byte transfer not done
1: Finished: Data byte transfer successful

ADD10

Bit 3: 10-bit header sent (Master mode).

STOPF

Bit 4: Stop detection (slave mode).

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

RxNE

Bit 6: Data register not empty (receivers).

Allowed values:
0: Empty: Data register empty
1: NotEmpty: Data register not empty

TxE

Bit 7: Data register empty (transmitters).

Allowed values:
0: NotEmpty: Data register not empty
1: Empty: Data register empty

BERR

Bit 8: Bus error.

Allowed values:
0: NoError: No misplaced Start or Stop condition
1: Error: Misplaced Start or Stop condition

ARLO

Bit 9: Arbitration lost (master mode).

Allowed values:
0: NoLost: No Arbitration Lost detected
1: Lost: Arbitration Lost detected

AF

Bit 10: Acknowledge failure.

Allowed values:
0: NoFailure: No acknowledge failure
1: Failure: Acknowledge failure

OVR

Bit 11: Overrun/Underrun.

Allowed values:
0: NoOverrun: No overrun/underrun occured
1: Overrun: Overrun/underrun occured

PECERR

Bit 12: PEC Error in reception.

Allowed values:
0: NoError: no PEC error: receiver returns ACK after PEC reception (if ACK=1)
1: Error: PEC error: receiver returns NACK after PEC reception (whatever ACK)

TIMEOUT

Bit 14: Timeout or Tlow error.

Allowed values:
0: NoTimeout: No Timeout error
1: Timeout: SCL remained LOW for 25 ms

SMBALERT

Bit 15: SMBus alert.

Allowed values:
0: NoAlert: No SMBALERT occured
1: Alert: SMBALERT occurred

SR2

Status register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PEC r								DUALF r	SMBHOST r	SMBDEFAULT r	GENCALL r		TRA r	BUSY r	MSL r

Toggle fields

MSL

Bit 0: Master/slave.

BUSY

Bit 1: Bus busy.

TRA

Bit 2: Transmitter/receiver.

GENCALL

Bit 4: General call address (Slave mode).

SMBDEFAULT

Bit 5: SMBus device default address (Slave mode).

SMBHOST

Bit 6: SMBus host header (Slave mode).

DUALF

Bit 7: Dual flag (Slave mode).

PEC

Bits 8-15: acket error checking register.

CCR

Clock control register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
F_S rw	DUTY rw			CCR rw

Toggle fields

CCR

Bits 0-11: Clock control register in Fast/Standard mode (Master mode).

Allowed values: 0x1-0xfff

DUTY

Bit 14: Fast mode duty cycle.

Allowed values:
0: Duty2_1: Duty cycle t_low/t_high = 2/1
1: Duty16_9: Duty cycle t_low/t_high = 16/9

F_S

Bit 15: I2C master mode selection.

Allowed values:
0: Standard: Standard mode I2C
1: Fast: Fast mode I2C

TRISE

TRISE register

Offset: 0x20, size: 32, reset: 0x00000002, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										TRISE rw

Toggle fields

TRISE

Bits 0-5: Maximum rise time in Fast/Standard mode (Master mode).

Allowed values: 0x0-0x3f

FLTR

FLTR register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											ANOFF rw	DNF rw

Toggle fields

DNF

Bits 0-3: Digital noise filter.

Allowed values:
0: NoFilter: Digital filter disabled
1: Filter1: Digital filter enabled and filtering capability up to 1 tI2CCLK
2: Filter2: Digital filter enabled and filtering capability up to 2 tI2CCLK
3: Filter3: Digital filter enabled and filtering capability up to 3 tI2CCLK
4: Filter4: Digital filter enabled and filtering capability up to 4 tI2CCLK
5: Filter5: Digital filter enabled and filtering capability up to 5 tI2CCLK
6: Filter6: Digital filter enabled and filtering capability up to 6 tI2CCLK
7: Filter7: Digital filter enabled and filtering capability up to 7 tI2CCLK
8: Filter8: Digital filter enabled and filtering capability up to 8 tI2CCLK
9: Filter9: Digital filter enabled and filtering capability up to 9 tI2CCLK
10: Filter10: Digital filter enabled and filtering capability up to 10 tI2CCLK
11: Filter11: Digital filter enabled and filtering capability up to 11 tI2CCLK
12: Filter12: Digital filter enabled and filtering capability up to 12 tI2CCLK
13: Filter13: Digital filter enabled and filtering capability up to 13 tI2CCLK
14: Filter14: Digital filter enabled and filtering capability up to 14 tI2CCLK
15: Filter15: Digital filter enabled and filtering capability up to 15 tI2CCLK

ANOFF

Bit 4: Analog noise filter.

Allowed values:
0: Enabled: Analog noise filter enabled
1: Disabled: Analog noise filter disabled

I2S2ext

0x40003400: Serial peripheral interface

46/46 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0 (16-bit)	CR1	BIDIMODE	BIDIOE	CRCEN	CRCNEXT	DFF	RXONLY	SSM	SSI	LSBFIRST	SPE	BR			MSTR	CPOL	CPHA
0x4 (16-bit)	CR2									TXEIE	RXNEIE	ERRIE	FRF		SSOE	TXDMAEN	RXDMAEN
0x8 (16-bit)	SR								FRE	BSY	OVR	MODF	CRCERR	UDR	CHSIDE	TXE	RXNE
0xc (16-bit)	DR	DR
0xc (8-bit)	DR8									DR
0x10 (16-bit)	CRCPR	CRCPOLY
0x14 (16-bit)	RXCRCR	RxCRC
0x18 (16-bit)	TXCRCR	TxCRC
0x1c (16-bit)	I2SCFGR					I2SMOD	I2SE	I2SCFG		PCMSYNC		I2SSTD		CKPOL	DATLEN		CHLEN
0x20 (16-bit)	I2SPR							MCKOE	ODD	I2SDIV

Toggle registers

CR1

control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

14/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIDIMODE rw	BIDIOE rw	CRCEN rw	CRCNEXT rw	DFF rw	RXONLY rw	SSM rw	SSI rw	LSBFIRST rw	SPE rw	BR rw			MSTR rw	CPOL rw	CPHA rw

Toggle fields

CPHA

Bit 0: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 1: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

MSTR

Bit 2: Master selection.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

BR

Bits 3-5: Baud rate control.

Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256

SPE

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LSBFIRST

Bit 7: Frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SSI

Bit 8: Internal slave select.

Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored

SSM

Bit 9: Software slave management.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

RXONLY

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)

DFF

Bit 11: Data frame format.

Allowed values:
0: EightBit: 8-bit data frame format is selected for transmission/reception
1: SixteenBit: 16-bit data frame format is selected for transmission/reception

CRCNEXT

Bit 12: CRC transfer next.

Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register

CRCEN

Bit 13: Hardware CRC calculation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BIDIOE

Bit 14: Output enable in bidirectional mode.

Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)

BIDIMODE

Bit 15: Bidirectional data mode enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CR2

control register 2

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TXEIE rw	RXNEIE rw	ERRIE rw	FRF rw		SSOE rw	TXDMAEN rw	RXDMAEN rw

Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 1: Tx buffer DMA enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

SSOE

Bit 2: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

FRF

Bit 4: Frame format.

Allowed values:
0: Motorola: SPI Motorola mode
1: TI: SPI TI mode

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked

TXEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked

SR

status register

Offset: 0x8, size: 16, reset: 0x00000002, access: Unspecified

9/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							FRE r	BSY r	OVR r	MODF r	CRCERR rw	UDR r	CHSIDE r	TXE r	RXNE r

Toggle fields

RXNE

Bit 0: Receive buffer not empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXE

Bit 1: Transmit buffer empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

CHSIDE

Bit 2: Channel side.

Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received

UDR

Bit 3: Underrun flag.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

CRCERR

Bit 4: CRC error flag.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

MODF

Bit 5: Mode fault.

Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred

OVR

Bit 6: Overrun flag.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

BSY

Bit 7: Busy flag.

Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy

FRE

Bit 8: TI frame format error.

Allowed values:
0: NoError: No frame format error
1: Error: A frame format error occurred

DR

data register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR rw

Toggle fields

DR

Bits 0-15: Data register.

Allowed values: 0x0-0xffff

DR8

Direct 8-bit access to data register

Offset: 0xc, size: 8, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								DR rw

Toggle fields

DR

Bits 0-7: Data register.

Allowed values: 0x0-0xff

CRCPR

CRC polynomial register

Offset: 0x10, size: 16, reset: 0x00000007, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRCPOLY rw

Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0x0-0xffff

RXCRCR

RX CRC register

Offset: 0x14, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RxCRC r

Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

Allowed values: 0x0-0xffff

TXCRCR

TX CRC register

Offset: 0x18, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TxCRC r

Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

Allowed values: 0x0-0xffff

I2SCFGR

I2S configuration register

Offset: 0x1c, size: 16, reset: 0x00000000, access: read-write

8/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				I2SMOD rw	I2SE rw	I2SCFG rw		PCMSYNC rw		I2SSTD rw		CKPOL rw	DATLEN rw		CHLEN rw

Toggle fields

CHLEN

Bit 0: Channel length (number of bits per audio channel).

Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide

DATLEN

Bits 1-2: Data length to be transferred.

Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length

CKPOL

Bit 3: Steady state clock polarity.

Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level

I2SSTD

Bits 4-5: I2S standard selection.

Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard

PCMSYNC

Bit 7: PCM frame synchronization.

Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation

I2SCFG

Bits 8-9: I2S configuration mode.

Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive

I2SE

Bit 10: I2S Enable.

Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled

I2SMOD

Bit 11: I2S mode selection.

Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected

I2SPR

I2S prescaler register

Offset: 0x20, size: 16, reset: 0x0000000A, access: read-write

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						MCKOE rw	ODD rw	I2SDIV rw

Toggle fields

I2SDIV

Bits 0-7: I2S Linear prescaler.

Allowed values: 0x2-0xff

ODD

Bit 8: Odd factor for the prescaler.

Allowed values:
0: Even: Real divider value is I2SDIV * 2
1: Odd: Real divider value is (I2SDIV * 2) + 1

MCKOE

Bit 9: Master clock output enable.

Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled

I2S3ext

0x40004000: Serial peripheral interface

46/46 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0 (16-bit)	CR1	BIDIMODE	BIDIOE	CRCEN	CRCNEXT	DFF	RXONLY	SSM	SSI	LSBFIRST	SPE	BR			MSTR	CPOL	CPHA
0x4 (16-bit)	CR2									TXEIE	RXNEIE	ERRIE	FRF		SSOE	TXDMAEN	RXDMAEN
0x8 (16-bit)	SR								FRE	BSY	OVR	MODF	CRCERR	UDR	CHSIDE	TXE	RXNE
0xc (16-bit)	DR	DR
0xc (8-bit)	DR8									DR
0x10 (16-bit)	CRCPR	CRCPOLY
0x14 (16-bit)	RXCRCR	RxCRC
0x18 (16-bit)	TXCRCR	TxCRC
0x1c (16-bit)	I2SCFGR					I2SMOD	I2SE	I2SCFG		PCMSYNC		I2SSTD		CKPOL	DATLEN		CHLEN
0x20 (16-bit)	I2SPR							MCKOE	ODD	I2SDIV

Toggle registers

CR1

control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

14/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIDIMODE rw	BIDIOE rw	CRCEN rw	CRCNEXT rw	DFF rw	RXONLY rw	SSM rw	SSI rw	LSBFIRST rw	SPE rw	BR rw			MSTR rw	CPOL rw	CPHA rw

Toggle fields

CPHA

Bit 0: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 1: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

MSTR

Bit 2: Master selection.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

BR

Bits 3-5: Baud rate control.

Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256

SPE

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LSBFIRST

Bit 7: Frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SSI

Bit 8: Internal slave select.

Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored

SSM

Bit 9: Software slave management.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

RXONLY

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)

DFF

Bit 11: Data frame format.

Allowed values:
0: EightBit: 8-bit data frame format is selected for transmission/reception
1: SixteenBit: 16-bit data frame format is selected for transmission/reception

CRCNEXT

Bit 12: CRC transfer next.

Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register

CRCEN

Bit 13: Hardware CRC calculation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BIDIOE

Bit 14: Output enable in bidirectional mode.

Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)

BIDIMODE

Bit 15: Bidirectional data mode enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CR2

control register 2

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TXEIE rw	RXNEIE rw	ERRIE rw	FRF rw		SSOE rw	TXDMAEN rw	RXDMAEN rw

Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 1: Tx buffer DMA enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

SSOE

Bit 2: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

FRF

Bit 4: Frame format.

Allowed values:
0: Motorola: SPI Motorola mode
1: TI: SPI TI mode

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked

TXEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked

SR

status register

Offset: 0x8, size: 16, reset: 0x00000002, access: Unspecified

9/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							FRE r	BSY r	OVR r	MODF r	CRCERR rw	UDR r	CHSIDE r	TXE r	RXNE r

Toggle fields

RXNE

Bit 0: Receive buffer not empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXE

Bit 1: Transmit buffer empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

CHSIDE

Bit 2: Channel side.

Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received

UDR

Bit 3: Underrun flag.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

CRCERR

Bit 4: CRC error flag.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

MODF

Bit 5: Mode fault.

Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred

OVR

Bit 6: Overrun flag.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

BSY

Bit 7: Busy flag.

Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy

FRE

Bit 8: TI frame format error.

Allowed values:
0: NoError: No frame format error
1: Error: A frame format error occurred

DR

data register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR rw

Toggle fields

DR

Bits 0-15: Data register.

Allowed values: 0x0-0xffff

DR8

Direct 8-bit access to data register

Offset: 0xc, size: 8, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								DR rw

Toggle fields

DR

Bits 0-7: Data register.

Allowed values: 0x0-0xff

CRCPR

CRC polynomial register

Offset: 0x10, size: 16, reset: 0x00000007, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRCPOLY rw

Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0x0-0xffff

RXCRCR

RX CRC register

Offset: 0x14, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RxCRC r

Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

Allowed values: 0x0-0xffff

TXCRCR

TX CRC register

Offset: 0x18, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TxCRC r

Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

Allowed values: 0x0-0xffff

I2SCFGR

I2S configuration register

Offset: 0x1c, size: 16, reset: 0x00000000, access: read-write

8/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				I2SMOD rw	I2SE rw	I2SCFG rw		PCMSYNC rw		I2SSTD rw		CKPOL rw	DATLEN rw		CHLEN rw

Toggle fields

CHLEN

Bit 0: Channel length (number of bits per audio channel).

Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide

DATLEN

Bits 1-2: Data length to be transferred.

Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length

CKPOL

Bit 3: Steady state clock polarity.

Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level

I2SSTD

Bits 4-5: I2S standard selection.

Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard

PCMSYNC

Bit 7: PCM frame synchronization.

Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation

I2SCFG

Bits 8-9: I2S configuration mode.

Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive

I2SE

Bit 10: I2S Enable.

Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled

I2SMOD

Bit 11: I2S mode selection.

Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected

I2SPR

I2S prescaler register

Offset: 0x20, size: 16, reset: 0x0000000A, access: read-write

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						MCKOE rw	ODD rw	I2SDIV rw

Toggle fields

I2SDIV

Bits 0-7: I2S Linear prescaler.

Allowed values: 0x2-0xff

ODD

Bit 8: Odd factor for the prescaler.

Allowed values:
0: Even: Real divider value is I2SDIV * 2
1: Odd: Real divider value is (I2SDIV * 2) + 1

MCKOE

Bit 9: Master clock output enable.

Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled

IWDG

0x40003000: Independent watchdog

5/5 fields covered.

Toggle register map

Offset	Name	15	11	2	1	0
0x0	KR	KEY
0x4	PR			PR
0x8	RLR		RL
0xc	SR				RVU	PVU

Toggle registers

KR

Key register

Offset: 0x0, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY w

Toggle fields

KEY

Bits 0-15: Key value.

Allowed values:
21845: Unlock: Enable access to PR, RLR and WINR registers
43690: Feed: Feed watchdog with RLR register value
52428: Start: Start the watchdog

PR

Prescaler register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													PR rw

Toggle fields

PR

Bits 0-2: Prescaler divider.

Allowed values:
0: DivideBy4: Divider /4
1: DivideBy8: Divider /8
2: DivideBy16: Divider /16
3: DivideBy32: Divider /32
4: DivideBy64: Divider /64
5: DivideBy128: Divider /128
6: DivideBy256: Divider /256

RLR

Reload register

Offset: 0x8, size: 32, reset: 0x00000FFF, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				RL rw

Toggle fields

RL

Bits 0-11: Watchdog counter reload value.

Allowed values: 0x0-0xfff

SR

Status register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														RVU r	PVU r

Toggle fields

PVU

Bit 0: Watchdog prescaler value update.

RVU

Bit 1: Watchdog counter reload value update.

MPU

0xe000ed90: Memory protection unit

6/19 fields covered.

Toggle register map

Offset	Name	31	28	26	23	21	18	17	16	15	7	5	4	3	2	1	0
0x0	TYPER				IREGION					DREGION							SEPARATE
0x4	CTRL														PRIVDEFENA	HFNMIENA	ENABLE
0x8	RNR										REGION
0xc	RBAR	ADDR								ADDR			VALID	REGION
0x10	RASR		XN	AP		TEX	S	C	B	SRD		SIZE					ENABLE

Toggle registers

TYPER

MPU type register

Offset: 0x0, size: 32, reset: 0x00000800, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								IREGION r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DREGION r															SEPARATE r

Toggle fields

SEPARATE

Bit 0: Separate flag.

DREGION

Bits 8-15: Number of MPU data regions.

IREGION

Bits 16-23: Number of MPU instruction regions.

CTRL

MPU control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													PRIVDEFENA r	HFNMIENA r	ENABLE r

Toggle fields

ENABLE

Bit 0: Enables the MPU.

HFNMIENA

Bit 1: Enables the operation of MPU during hard fault.

PRIVDEFENA

Bit 2: Enable priviliged software access to default memory map.

RNR

MPU region number register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REGION rw

Toggle fields

REGION

Bits 0-7: MPU region.

RBAR

MPU region base address register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADDR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDR rw											VALID rw	REGION rw

Toggle fields

REGION

Bits 0-3: MPU region field.

VALID

Bit 4: MPU region number valid.

ADDR

Bits 5-31: Region base address field.

RASR

MPU region attribute and size register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			XN rw		AP rw					TEX rw			S rw	C rw	B rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SRD rw										SIZE rw					ENABLE rw

Toggle fields

ENABLE

Bit 0: Region enable bit..

SIZE

Bits 1-5: Size of the MPU protection region.

SRD

Bits 8-15: Subregion disable bits.

B

Bit 16: memory attribute.

C

Bit 17: memory attribute.

S

Bit 18: Shareable memory attribute.

TEX

Bits 19-21: memory attribute.

AP

Bits 24-26: Access permission.

XN

Bit 28: Instruction access disable bit.

NVIC

0xe000e100: Nested Vectored Interrupt Controller

3/95 fields covered.

Toggle register map

Offset	Name	31	23	15	7
0x0	ISER0	SETENA		SETENA
0x4	ISER1	SETENA		SETENA
0x8	ISER2	SETENA		SETENA
0x80	ICER0	CLRENA		CLRENA
0x84	ICER1	CLRENA		CLRENA
0x88	ICER2	CLRENA		CLRENA
0x100	ISPR0	SETPEND		SETPEND
0x104	ISPR1	SETPEND		SETPEND
0x108	ISPR2	SETPEND		SETPEND
0x180	ICPR0	CLRPEND		CLRPEND
0x184	ICPR1	CLRPEND		CLRPEND
0x188	ICPR2	CLRPEND		CLRPEND
0x200	IABR0	ACTIVE		ACTIVE
0x204	IABR1	ACTIVE		ACTIVE
0x208	IABR2	ACTIVE		ACTIVE
0x300	IPR0	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x304	IPR1	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x308	IPR2	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x30c	IPR3	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x310	IPR4	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x314	IPR5	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x318	IPR6	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x31c	IPR7	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x320	IPR8	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x324	IPR9	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x328	IPR10	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x32c	IPR11	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x330	IPR12	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x334	IPR13	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x338	IPR14	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x33c	IPR15	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x340	IPR16	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x344	IPR17	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x348	IPR18	IPR_N3	IPR_N2	IPR_N1	IPR_N0
0x34c	IPR19	IPR_N3	IPR_N2	IPR_N1	IPR_N0

Toggle registers

ISER0

Interrupt Set-Enable Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SETENA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SETENA rw

Toggle fields

SETENA

Bits 0-31: SETENA.

ISER1

Interrupt Set-Enable Register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SETENA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SETENA rw

Toggle fields

SETENA

Bits 0-31: SETENA.

ISER2

Interrupt Set-Enable Register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SETENA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SETENA rw

Toggle fields

SETENA

Bits 0-31: SETENA.

ICER0

Interrupt Clear-Enable Register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLRENA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLRENA rw

Toggle fields

CLRENA

Bits 0-31: CLRENA.

ICER1

Interrupt Clear-Enable Register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLRENA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLRENA rw

Toggle fields

CLRENA

Bits 0-31: CLRENA.

ICER2

Interrupt Clear-Enable Register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLRENA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLRENA rw

Toggle fields

CLRENA

Bits 0-31: CLRENA.

ISPR0

Interrupt Set-Pending Register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SETPEND rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SETPEND rw

Toggle fields

SETPEND

Bits 0-31: SETPEND.

ISPR1

Interrupt Set-Pending Register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SETPEND rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SETPEND rw

Toggle fields

SETPEND

Bits 0-31: SETPEND.

ISPR2

Interrupt Set-Pending Register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SETPEND rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SETPEND rw

Toggle fields

SETPEND

Bits 0-31: SETPEND.

ICPR0

Interrupt Clear-Pending Register

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLRPEND rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLRPEND rw

Toggle fields

CLRPEND

Bits 0-31: CLRPEND.

ICPR1

Interrupt Clear-Pending Register

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLRPEND rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLRPEND rw

Toggle fields

CLRPEND

Bits 0-31: CLRPEND.

ICPR2

Interrupt Clear-Pending Register

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLRPEND rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLRPEND rw

Toggle fields

CLRPEND

Bits 0-31: CLRPEND.

IABR0

Interrupt Active Bit Register

Offset: 0x200, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ACTIVE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ACTIVE r

Toggle fields

ACTIVE

Bits 0-31: ACTIVE.

IABR1

Interrupt Active Bit Register

Offset: 0x204, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ACTIVE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ACTIVE r

Toggle fields

ACTIVE

Bits 0-31: ACTIVE.

IABR2

Interrupt Active Bit Register

Offset: 0x208, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ACTIVE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ACTIVE r

Toggle fields

ACTIVE

Bits 0-31: ACTIVE.

IPR0

Interrupt Priority Register

Offset: 0x300, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR1

Interrupt Priority Register

Offset: 0x304, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR2

Interrupt Priority Register

Offset: 0x308, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR3

Interrupt Priority Register

Offset: 0x30c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR4

Interrupt Priority Register

Offset: 0x310, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR5

Interrupt Priority Register

Offset: 0x314, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR6

Interrupt Priority Register

Offset: 0x318, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR7

Interrupt Priority Register

Offset: 0x31c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR8

Interrupt Priority Register

Offset: 0x320, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR9

Interrupt Priority Register

Offset: 0x324, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR10

Interrupt Priority Register

Offset: 0x328, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR11

Interrupt Priority Register

Offset: 0x32c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR12

Interrupt Priority Register

Offset: 0x330, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR13

Interrupt Priority Register

Offset: 0x334, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR14

Interrupt Priority Register

Offset: 0x338, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR15

Interrupt Priority Register

Offset: 0x33c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR16

Interrupt Priority Register

Offset: 0x340, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR17

Interrupt Priority Register

Offset: 0x344, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR18

Interrupt Priority Register

Offset: 0x348, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR19

Interrupt Priority Register

Offset: 0x34c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

NVIC_STIR

0xe000ef00: Nested vectored interrupt controller

0/1 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	STIR																								INTID

Toggle registers

STIR

Software trigger interrupt register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							INTID rw

Toggle fields

INTID

Bits 0-8: Software generated interrupt ID.

OTG_FS_DEVICE

0x50000800: USB on the go full speed

37/204 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	21	20	19	18	17	16	15	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	DCFG															PFIVL		DAD								NZLSOHSK	DSPD
0x4	DCTL																POPRGDNE	CGONAK	SGONAK	CGINAK	SGINAK	TCTL			GONSTS	GINSTS	SDIS	RWUSIG
0x8	DSTS								FNSOF						FNSOF										EERR	ENUMSPD		SUSPSTS
0x10	DIEPMSK																					INEPNEM	INEPNMM	ITTXFEMSK	TOM		EPDM	XFRCM
0x14	DOEPMSK																							OTEPDM	STUPM		EPDM	XFRCM
0x18	DAINT	OEPINT													IEPINT
0x1c	DAINTMSK	OEPM													IEPM
0x28	DVBUSDIS														VBUSDT
0x2c	DVBUSPULSE																DVBUSP
0x34	DIEPEMPMSK														INEPTXFEM
0x100	CTL [0]	EPENA	EPDIS			SNAK	CNAK	TXFNUM	STALL		EPTYP		NAKSTS		USBAEP												MPSIZ
0x108	INT [0]																				TXFE	INEPNE		ITTXFE	TOC		EPDISD	XFRC
0x110	TSIZ [0]									PKTCNT												XFRSIZ
0x118	TXFSTS [0]														INEPTFSAV
0x120	CTL [1]	EPENA	EPDIS	SODDFRM_SD1PID	SD0PID_SEVNFRM	SNAK	CNAK	TXFNUM	STALL		EPTYP		NAKSTS	EONUM_DPID	USBAEP			MPSIZ
0x128	INT [1]																				TXFE	INEPNE		ITTXFE	TOC		EPDISD	XFRC
0x130	TSIZ [1]		MCNT		PKTCNT							XFRSIZ			XFRSIZ
0x138	TXFSTS [1]														INEPTFSAV
0x140	CTL [2]	EPENA	EPDIS	SODDFRM_SD1PID	SD0PID_SEVNFRM	SNAK	CNAK	TXFNUM	STALL		EPTYP		NAKSTS	EONUM_DPID	USBAEP			MPSIZ
0x148	INT [2]																				TXFE	INEPNE		ITTXFE	TOC		EPDISD	XFRC
0x150	TSIZ [2]		MCNT		PKTCNT							XFRSIZ			XFRSIZ
0x158	TXFSTS [2]														INEPTFSAV
0x160	CTL [3]	EPENA	EPDIS	SODDFRM_SD1PID	SD0PID_SEVNFRM	SNAK	CNAK	TXFNUM	STALL		EPTYP		NAKSTS	EONUM_DPID	USBAEP			MPSIZ
0x168	INT [3]																				TXFE	INEPNE		ITTXFE	TOC		EPDISD	XFRC
0x170	TSIZ [3]		MCNT		PKTCNT							XFRSIZ			XFRSIZ
0x178	TXFSTS [3]														INEPTFSAV
0x300	CTL [0]	EPENA	EPDIS			SNAK	CNAK		STALL	SNPM	EPTYP		NAKSTS		USBAEP												MPSIZ
0x308	INT [0]																					B2BSTUP		OTEPDIS	STUP		EPDISD	XFRC
0x310	TSIZ [0]		STUPCNT								PKTCNT											XFRSIZ
0x320	CTL [1]	EPENA	EPDIS	SODDFRM	SD0PID_SEVNFRM	SNAK	CNAK		STALL	SNPM	EPTYP		NAKSTS	EONUM_DPID	USBAEP			MPSIZ
0x328	INT [1]																					B2BSTUP		OTEPDIS	STUP		EPDISD	XFRC
0x330	TSIZ [1]		RXDPID_STUPCNT		PKTCNT							XFRSIZ			XFRSIZ
0x340	CTL [2]	EPENA	EPDIS	SODDFRM	SD0PID_SEVNFRM	SNAK	CNAK		STALL	SNPM	EPTYP		NAKSTS	EONUM_DPID	USBAEP			MPSIZ
0x348	INT [2]																					B2BSTUP		OTEPDIS	STUP		EPDISD	XFRC
0x350	TSIZ [2]		RXDPID_STUPCNT		PKTCNT							XFRSIZ			XFRSIZ
0x360	CTL [3]	EPENA	EPDIS	SODDFRM	SD0PID_SEVNFRM	SNAK	CNAK		STALL	SNPM	EPTYP		NAKSTS	EONUM_DPID	USBAEP			MPSIZ
0x368	INT [3]																					B2BSTUP		OTEPDIS	STUP		EPDISD	XFRC
0x370	TSIZ [3]		RXDPID_STUPCNT		PKTCNT							XFRSIZ			XFRSIZ

Toggle registers

DCFG

OTG_FS device configuration register (OTG_FS_DCFG)

Offset: 0x0, size: 32, reset: 0x02200000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			PFIVL rw		DAD rw								NZLSOHSK rw	DSPD rw

Toggle fields

DSPD

Bits 0-1: Device speed.

NZLSOHSK

Bit 2: Non-zero-length status OUT handshake.

DAD

Bits 4-10: Device address.

PFIVL

Bits 11-12: Periodic frame interval.

DCTL

OTG_FS device control register (OTG_FS_DCTL)

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

2/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				POPRGDNE rw	CGONAK rw	SGONAK rw	CGINAK rw	SGINAK rw	TCTL rw			GONSTS r	GINSTS r	SDIS rw	RWUSIG rw

Toggle fields

RWUSIG

Bit 0: Remote wakeup signaling.

SDIS

Bit 1: Soft disconnect.

GINSTS

Bit 2: Global IN NAK status.

GONSTS

Bit 3: Global OUT NAK status.

TCTL

Bits 4-6: Test control.

SGINAK

Bit 7: Set global IN NAK.

CGINAK

Bit 8: Clear global IN NAK.

SGONAK

Bit 9: Set global OUT NAK.

CGONAK

Bit 10: Clear global OUT NAK.

POPRGDNE

Bit 11: Power-on programming done.

DSTS

OTG_FS device status register (OTG_FS_DSTS)

Offset: 0x8, size: 32, reset: 0x00000010, access: read-only

4/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										FNSOF r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FNSOF r												EERR r	ENUMSPD r		SUSPSTS r

Toggle fields

SUSPSTS

Bit 0: Suspend status.

ENUMSPD

Bits 1-2: Enumerated speed.

EERR

Bit 3: Erratic error.

FNSOF

Bits 8-21: Frame number of the received SOF.

DIEPMSK

OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									INEPNEM rw	INEPNMM rw	ITTXFEMSK rw	TOM rw		EPDM rw	XFRCM rw

Toggle fields

XFRCM

Bit 0: Transfer completed interrupt mask.

EPDM

Bit 1: Endpoint disabled interrupt mask.

TOM

Bit 3: Timeout condition mask (Non-isochronous endpoints).

ITTXFEMSK

Bit 4: IN token received when TxFIFO empty mask.

INEPNMM

Bit 5: IN token received with EP mismatch mask.

INEPNEM

Bit 6: IN endpoint NAK effective mask.

DOEPMSK

OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											OTEPDM rw	STUPM rw		EPDM rw	XFRCM rw

Toggle fields

XFRCM

Bit 0: Transfer completed interrupt mask.

EPDM

Bit 1: Endpoint disabled interrupt mask.

STUPM

Bit 3: SETUP phase done mask.

OTEPDM

Bit 4: OUT token received when endpoint disabled mask.

DAINT

OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OEPINT r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IEPINT r

Toggle fields

IEPINT

Bits 0-15: IN endpoint interrupt bits.

OEPINT

Bits 16-31: OUT endpoint interrupt bits.

DAINTMSK

OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OEPM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IEPM rw

Toggle fields

IEPM

Bits 0-15: IN EP interrupt mask bits.

OEPM

Bits 16-31: OUT EP interrupt mask bits.

DVBUSDIS

OTG_FS device VBUS discharge time register

Offset: 0x28, size: 32, reset: 0x000017D7, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VBUSDT rw

Toggle fields

VBUSDT

Bits 0-15: Device VBUS discharge time.

DVBUSPULSE

OTG_FS device VBUS pulsing time register

Offset: 0x2c, size: 32, reset: 0x000005B8, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				DVBUSP rw

Toggle fields

DVBUSP

Bits 0-11: Device VBUS pulsing time.

DIEPEMPMSK

OTG_FS device IN endpoint FIFO empty interrupt mask register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
INEPTXFEM rw

Toggle fields

INEPTXFEM

Bits 0-15: IN EP Tx FIFO empty interrupt mask bits.

CTL [0]

OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)

Offset: 0x100, size: 32, reset: 0x00000000, access: Unspecified

4/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EPENA rw	EPDIS r			SNAK w	CNAK w	TXFNUM rw				STALL rw		EPTYP r		NAKSTS r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
USBAEP r														MPSIZ rw

Toggle fields

MPSIZ

Bits 0-1: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

STALL

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TxFIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

INT [0]

device endpoint-x interrupt register

Offset: 0x108, size: 32, reset: 0x00000080, access: Unspecified

1/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TXFE r	INEPNE rw		ITTXFE rw	TOC rw		EPDISD rw	XFRC rw

Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

ITTXFE

Bit 4: ITTXFE.

INEPNE

Bit 6: INEPNE.

TXFE

Bit 7: TXFE.

TSIZ [0]

device endpoint-0 transfer size register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											PKTCNT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									XFRSIZ rw

Toggle fields

XFRSIZ

Bits 0-6: Transfer size.

PKTCNT

Bits 19-20: Packet count.

TXFSTS [0]

OTG_FS device IN endpoint transmit FIFO status register

Offset: 0x118, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
INEPTFSAV r

Toggle fields

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space available.

CTL [1]

OTG device endpoint-1 control register

Offset: 0x120, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EPENA rw	EPDIS rw	SODDFRM_SD1PID w	SD0PID_SEVNFRM w	SNAK w	CNAK w	TXFNUM rw				STALL rw		EPTYP rw		NAKSTS r	EONUM_DPID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
USBAEP rw					MPSIZ rw

Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPID

Bit 16: EONUM/DPID.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

STALL

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TXFNUM.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID/SEVNFRM.

SODDFRM_SD1PID

Bit 29: SODDFRM/SD1PID.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

INT [1]

device endpoint-1 interrupt register

Offset: 0x128, size: 32, reset: 0x00000080, access: Unspecified

1/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TXFE r	INEPNE rw		ITTXFE rw	TOC rw		EPDISD rw	XFRC rw

Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

ITTXFE

Bit 4: ITTXFE.

INEPNE

Bit 6: INEPNE.

TXFE

Bit 7: TXFE.

TSIZ [1]

device endpoint-1 transfer size register

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	MCNT rw		PKTCNT rw										XFRSIZ rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
XFRSIZ rw

Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

TXFSTS [1]

OTG_FS device IN endpoint transmit FIFO status register

Offset: 0x138, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
INEPTFSAV r

Toggle fields

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space available.

CTL [2]

OTG device endpoint-1 control register

Offset: 0x140, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EPENA rw	EPDIS rw	SODDFRM_SD1PID w	SD0PID_SEVNFRM w	SNAK w	CNAK w	TXFNUM rw				STALL rw		EPTYP rw		NAKSTS r	EONUM_DPID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
USBAEP rw					MPSIZ rw

Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPID

Bit 16: EONUM/DPID.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

STALL

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TXFNUM.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID/SEVNFRM.

SODDFRM_SD1PID

Bit 29: SODDFRM/SD1PID.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

INT [2]

device endpoint-1 interrupt register

Offset: 0x148, size: 32, reset: 0x00000080, access: Unspecified

1/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TXFE r	INEPNE rw		ITTXFE rw	TOC rw		EPDISD rw	XFRC rw

Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

ITTXFE

Bit 4: ITTXFE.

INEPNE

Bit 6: INEPNE.

TXFE

Bit 7: TXFE.

TSIZ [2]

device endpoint-1 transfer size register

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	MCNT rw		PKTCNT rw										XFRSIZ rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
XFRSIZ rw

Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

TXFSTS [2]

OTG_FS device IN endpoint transmit FIFO status register

Offset: 0x158, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
INEPTFSAV r

Toggle fields

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space available.

CTL [3]

OTG device endpoint-1 control register

Offset: 0x160, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EPENA rw	EPDIS rw	SODDFRM_SD1PID w	SD0PID_SEVNFRM w	SNAK w	CNAK w	TXFNUM rw				STALL rw		EPTYP rw		NAKSTS r	EONUM_DPID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
USBAEP rw					MPSIZ rw

Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPID

Bit 16: EONUM/DPID.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

STALL

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TXFNUM.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID/SEVNFRM.

SODDFRM_SD1PID

Bit 29: SODDFRM/SD1PID.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

INT [3]

device endpoint-1 interrupt register

Offset: 0x168, size: 32, reset: 0x00000080, access: Unspecified

1/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TXFE r	INEPNE rw		ITTXFE rw	TOC rw		EPDISD rw	XFRC rw

Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

ITTXFE

Bit 4: ITTXFE.

INEPNE

Bit 6: INEPNE.

TXFE

Bit 7: TXFE.

TSIZ [3]

device endpoint-1 transfer size register

Offset: 0x170, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	MCNT rw		PKTCNT rw										XFRSIZ rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
XFRSIZ rw

Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

TXFSTS [3]

OTG_FS device IN endpoint transmit FIFO status register

Offset: 0x178, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
INEPTFSAV r

Toggle fields

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space available.

CTL [0]

device endpoint-0 control register

Offset: 0x300, size: 32, reset: 0x00008000, access: Unspecified

5/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EPENA rw	EPDIS r			SNAK w	CNAK w					STALL rw	SNPM rw	EPTYP r		NAKSTS r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
USBAEP r														MPSIZ r

Toggle fields

MPSIZ

Bits 0-1: MPSIZ.

USBAEP

Bit 15: USBAEP.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

SNPM

Bit 20: SNPM.

STALL

Bit 21: STALL handshake.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

INT [0]

device endpoint-0 interrupt register

Offset: 0x308, size: 32, reset: 0x00000080, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									B2BSTUP rw		OTEPDIS rw	STUP rw		EPDISD rw	XFRC rw

Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

STUP

Bit 3: STUP.

OTEPDIS

Bit 4: OTEPDIS.

B2BSTUP

Bit 6: B2BSTUP.

TSIZ [0]

device OUT endpoint-0 transfer size register

Offset: 0x310, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	STUPCNT rw											PKTCNT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									XFRSIZ rw

Toggle fields

XFRSIZ

Bits 0-6: Transfer size.

PKTCNT

Bit 19: Packet count.

STUPCNT

Bits 29-30: SETUP packet count.

CTL [1]

device endpoint-1 control register

Offset: 0x320, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EPENA rw	EPDIS rw	SODDFRM w	SD0PID_SEVNFRM w	SNAK w	CNAK w					STALL rw	SNPM rw	EPTYP rw		NAKSTS r	EONUM_DPID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
USBAEP rw					MPSIZ rw

Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPID

Bit 16: EONUM/DPID.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

SNPM

Bit 20: SNPM.

STALL

Bit 21: STALL handshake.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID/SEVNFRM.

SODDFRM

Bit 29: SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

INT [1]

device endpoint-1 interrupt register

Offset: 0x328, size: 32, reset: 0x00000080, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									B2BSTUP rw		OTEPDIS rw	STUP rw		EPDISD rw	XFRC rw

Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

STUP

Bit 3: STUP.

OTEPDIS

Bit 4: OTEPDIS.

B2BSTUP

Bit 6: B2BSTUP.

TSIZ [1]

device OUT endpoint-1 transfer size register

Offset: 0x330, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	RXDPID_STUPCNT rw		PKTCNT rw										XFRSIZ rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
XFRSIZ rw

Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

RXDPID_STUPCNT

Bits 29-30: Received data PID/SETUP packet count.

CTL [2]

device endpoint-1 control register

Offset: 0x340, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EPENA rw	EPDIS rw	SODDFRM w	SD0PID_SEVNFRM w	SNAK w	CNAK w					STALL rw	SNPM rw	EPTYP rw		NAKSTS r	EONUM_DPID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
USBAEP rw					MPSIZ rw

Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPID

Bit 16: EONUM/DPID.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

SNPM

Bit 20: SNPM.

STALL

Bit 21: STALL handshake.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID/SEVNFRM.

SODDFRM

Bit 29: SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

INT [2]

device endpoint-1 interrupt register

Offset: 0x348, size: 32, reset: 0x00000080, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									B2BSTUP rw		OTEPDIS rw	STUP rw		EPDISD rw	XFRC rw

Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

STUP

Bit 3: STUP.

OTEPDIS

Bit 4: OTEPDIS.

B2BSTUP

Bit 6: B2BSTUP.

TSIZ [2]

device OUT endpoint-1 transfer size register

Offset: 0x350, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	RXDPID_STUPCNT rw		PKTCNT rw										XFRSIZ rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
XFRSIZ rw

Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

RXDPID_STUPCNT

Bits 29-30: Received data PID/SETUP packet count.

CTL [3]

device endpoint-1 control register

Offset: 0x360, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EPENA rw	EPDIS rw	SODDFRM w	SD0PID_SEVNFRM w	SNAK w	CNAK w					STALL rw	SNPM rw	EPTYP rw		NAKSTS r	EONUM_DPID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
USBAEP rw					MPSIZ rw

Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPID

Bit 16: EONUM/DPID.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

SNPM

Bit 20: SNPM.

STALL

Bit 21: STALL handshake.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID/SEVNFRM.

SODDFRM

Bit 29: SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

INT [3]

device endpoint-1 interrupt register

Offset: 0x368, size: 32, reset: 0x00000080, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									B2BSTUP rw		OTEPDIS rw	STUP rw		EPDISD rw	XFRC rw

Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

STUP

Bit 3: STUP.

OTEPDIS

Bit 4: OTEPDIS.

B2BSTUP

Bit 6: B2BSTUP.

TSIZ [3]

device OUT endpoint-1 transfer size register

Offset: 0x370, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	RXDPID_STUPCNT rw		PKTCNT rw										XFRSIZ rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
XFRSIZ rw

Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

RXDPID_STUPCNT

Bits 29-30: Received data PID/SETUP packet count.

OTG_FS_GLOBAL

0x50000000: USB on the go full speed

39/124 fields covered.

Toggle register map

Offset	Name	31	30	29	28	26	25	24	23	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	GOTGCTL											BSVLD	ASVLD	DBCT	CIDSTS					DHNPEN	HSHNPEN	HNPRQ	HNGSCS							SRQ	SRQSCS
0x4	GOTGINT											DBCDNE	ADTOCHG	HNGDET								HNSSCHG	SRSSCHG						SEDET
0x8	GAHBCFG																						PTXFELVL	TXFELVL							GINT
0xc	GUSBCFG	CTXPKT	FDMOD	FHMOD														TRDT				HNPCAP	SRPCAP		PHYSEL				TOCAL
0x10	GRSTCTL	AHBIDL																			TXFNUM					TXFFLSH	RXFFLSH		FCRST	HSRST	CSRST
0x14	GINTSTS	WKUPINT	SRQINT	DISCINT	CIDSCHG	PTXFE	HCINT	HPRTINT		IPXFR_INCOMPISOOUT	IISOIXFR	OEPINT	IEPINT			EOPF	ISOODRP	ENUMDNE	USBRST	USBSUSP	ESUSP			GOUTNAKEFF	GINAKEFF	NPTXFE	RXFLVL	SOF	OTGINT	MMIS	CMOD
0x18	GINTMSK	WUIM	SRQIM	DISCINT	CIDSCHGM	PTXFEM	HCIM	PRTIM		IPXFRM_IISOOXFRM	IISOIXFRM	OEPINT	IEPINT	EPMISM		EOPFM	ISOODRPM	ENUMDNEM	USBRST	USBSUSPM	ESUSPM			GONAKEFFM	GINAKEFFM	NPTXFEM	RXFLVLM	SOFM	OTGINT	MMISM
0x1c	GRXSTSR_Device							FRMNUM			PKTSTS				DPID	DPID	BCNT											EPNUM
0x1c	GRXSTSR_Host										PKTSTS				DPID	DPID	BCNT											CHNUM
0x20	GRXSTSP_Device							FRMNUM			PKTSTS				DPID	DPID	BCNT											EPNUM
0x20	GRXSTSP_Host										PKTSTS				DPID	DPID	BCNT											CHNUM
0x24	GRXFSIZ															RXFD
0x28	DIEPTXF0	TX0FD														TX0FSA
0x28	HNPTXFSIZ	NPTXFD														NPTXFSA
0x2c	GNPTXSTS		NPTXQTOP						NPTQXSAV							NPTXFSAV
0x38	GCCFG									NOVBUSSENS	SOFOUTEN	VBUSBSEN	VBUSASEN		PWRDWN
0x3c	CID	PRODUCT_ID														PRODUCT_ID
0x100	HPTXFSIZ	PTXFSIZ														PTXSA
0x104	DIEPTXF[1]	INEPTXFD														INEPTXSA
0x108	DIEPTXF[2]	INEPTXFD														INEPTXSA
0x10c	DIEPTXF[3]	INEPTXFD														INEPTXSA

Toggle registers

GOTGCTL

OTG_FS control and status register (OTG_FS_GOTGCTL)

Offset: 0x0, size: 32, reset: 0x00000800, access: Unspecified

6/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												BSVLD r	ASVLD r	DBCT r	CIDSTS r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				DHNPEN rw	HSHNPEN rw	HNPRQ rw	HNGSCS r							SRQ rw	SRQSCS r

Toggle fields

SRQSCS

Bit 0: Session request success.

SRQ

Bit 1: Session request.

HNGSCS

Bit 8: Host negotiation success.

HNPRQ

Bit 9: HNP request.

HSHNPEN

Bit 10: Host set HNP enable.

DHNPEN

Bit 11: Device HNP enabled.

CIDSTS

Bit 16: Connector ID status.

DBCT

Bit 17: Long/short debounce time.

ASVLD

Bit 18: A-session valid.

BSVLD

Bit 19: B-session valid.

GOTGINT

OTG_FS interrupt register (OTG_FS_GOTGINT)

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												DBCDNE rw	ADTOCHG rw	HNGDET rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						HNSSCHG rw	SRSSCHG rw						SEDET rw

Toggle fields

SEDET

Bit 2: Session end detected.

SRSSCHG

Bit 8: Session request success status change.

HNSSCHG

Bit 9: Host negotiation success status change.

HNGDET

Bit 17: Host negotiation detected.

ADTOCHG

Bit 18: A-device timeout change.

DBCDNE

Bit 19: Debounce done.

GAHBCFG

OTG_FS AHB configuration register (OTG_FS_GAHBCFG)

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							PTXFELVL rw	TXFELVL rw							GINT rw

Toggle fields

GINT

Bit 0: Global interrupt mask.

TXFELVL

Bit 7: TxFIFO empty level.

PTXFELVL

Bit 8: Periodic TxFIFO empty level.

GUSBCFG

OTG_FS USB configuration register (OTG_FS_GUSBCFG)

Offset: 0xc, size: 32, reset: 0x00000A00, access: Unspecified

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CTXPKT rw	FDMOD rw	FHMOD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		TRDT rw				HNPCAP rw	SRPCAP rw		PHYSEL w				TOCAL rw

Toggle fields

TOCAL

Bits 0-2: FS timeout calibration.

PHYSEL

Bit 6: Full Speed serial transceiver select.

SRPCAP

Bit 8: SRP-capable.

HNPCAP

Bit 9: HNP-capable.

TRDT

Bits 10-13: USB turnaround time.

FHMOD

Bit 29: Force host mode.

FDMOD

Bit 30: Force device mode.

CTXPKT

Bit 31: Corrupt Tx packet.

GRSTCTL

OTG_FS reset register (OTG_FS_GRSTCTL)

Offset: 0x10, size: 32, reset: 0x20000000, access: Unspecified

1/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AHBIDL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					TXFNUM rw					TXFFLSH rw	RXFFLSH rw		FCRST rw	HSRST rw	CSRST rw

Toggle fields

CSRST

Bit 0: Core soft reset.

HSRST

Bit 1: HCLK soft reset.

FCRST

Bit 2: Host frame counter reset.

RXFFLSH

Bit 4: RxFIFO flush.

TXFFLSH

Bit 5: TxFIFO flush.

TXFNUM

Bits 6-10: TxFIFO number.

AHBIDL

Bit 31: AHB master idle.

GINTSTS

OTG_FS core interrupt register (OTG_FS_GINTSTS)

Offset: 0x14, size: 32, reset: 0x04000020, access: Unspecified

11/25 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
WKUPINT rw	SRQINT rw	DISCINT rw	CIDSCHG rw		PTXFE r	HCINT r	HPRTINT r			IPXFR_INCOMPISOOUT rw	IISOIXFR rw	OEPINT r	IEPINT r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EOPF rw	ISOODRP rw	ENUMDNE rw	USBRST rw	USBSUSP rw	ESUSP rw			GOUTNAKEFF r	GINAKEFF r	NPTXFE r	RXFLVL r	SOF rw	OTGINT r	MMIS rw	CMOD r

Toggle fields

CMOD

Bit 0: Current mode of operation.

MMIS

Bit 1: Mode mismatch interrupt.

OTGINT

Bit 2: OTG interrupt.

SOF

Bit 3: Start of frame.

RXFLVL

Bit 4: RxFIFO non-empty.

NPTXFE

Bit 5: Non-periodic TxFIFO empty.

GINAKEFF

Bit 6: Global IN non-periodic NAK effective.

GOUTNAKEFF

Bit 7: Global OUT NAK effective.

ESUSP

Bit 10: Early suspend.

USBSUSP

Bit 11: USB suspend.

USBRST

Bit 12: USB reset.

ENUMDNE

Bit 13: Enumeration done.

ISOODRP

Bit 14: Isochronous OUT packet dropped interrupt.

EOPF

Bit 15: End of periodic frame interrupt.

IEPINT

Bit 18: IN endpoint interrupt.

OEPINT

Bit 19: OUT endpoint interrupt.

IISOIXFR

Bit 20: Incomplete isochronous IN transfer.

IPXFR_INCOMPISOOUT

Bit 21: Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode).

HPRTINT

Bit 24: Host port interrupt.

HCINT

Bit 25: Host channels interrupt.

PTXFE

Bit 26: Periodic TxFIFO empty.

CIDSCHG

Bit 28: Connector ID status change.

DISCINT

Bit 29: Disconnect detected interrupt.

SRQINT

Bit 30: Session request/new session detected interrupt.

WKUPINT

Bit 31: Resume/remote wakeup detected interrupt.

GINTMSK

OTG_FS interrupt mask register (OTG_FS_GINTMSK)

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/25 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
WUIM rw	SRQIM rw	DISCINT rw	CIDSCHGM rw		PTXFEM rw	HCIM rw	PRTIM rw			IPXFRM_IISOOXFRM rw	IISOIXFRM rw	OEPINT rw	IEPINT rw	EPMISM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EOPFM rw	ISOODRPM rw	ENUMDNEM rw	USBRST rw	USBSUSPM rw	ESUSPM rw			GONAKEFFM rw	GINAKEFFM rw	NPTXFEM rw	RXFLVLM rw	SOFM rw	OTGINT rw	MMISM rw

Toggle fields

MMISM

Bit 1: Mode mismatch interrupt mask.

OTGINT

Bit 2: OTG interrupt mask.

SOFM

Bit 3: Start of frame mask.

RXFLVLM

Bit 4: Receive FIFO non-empty mask.

NPTXFEM

Bit 5: Non-periodic TxFIFO empty mask.

GINAKEFFM

Bit 6: Global non-periodic IN NAK effective mask.

GONAKEFFM

Bit 7: Global OUT NAK effective mask.

ESUSPM

Bit 10: Early suspend mask.

USBSUSPM

Bit 11: USB suspend mask.

USBRST

Bit 12: USB reset mask.

ENUMDNEM

Bit 13: Enumeration done mask.

ISOODRPM

Bit 14: Isochronous OUT packet dropped interrupt mask.

EOPFM

Bit 15: End of periodic frame interrupt mask.

EPMISM

Bit 17: Endpoint mismatch interrupt mask.

IEPINT

Bit 18: IN endpoints interrupt mask.

OEPINT

Bit 19: OUT endpoints interrupt mask.

IISOIXFRM

Bit 20: Incomplete isochronous IN transfer mask.

IPXFRM_IISOOXFRM

Bit 21: Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode).

PRTIM

Bit 24: Host port interrupt mask.

HCIM

Bit 25: Host channels interrupt mask.

PTXFEM

Bit 26: Periodic TxFIFO empty mask.

CIDSCHGM

Bit 28: Connector ID status change mask.

DISCINT

Bit 29: Disconnect detected interrupt mask.

SRQIM

Bit 30: Session request/new session detected interrupt mask.

WUIM

Bit 31: Resume/remote wakeup detected interrupt mask.

GRXSTSR_Device

OTG_FS Receive status debug read(Device mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							FRMNUM r				PKTSTS r				DPID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DPID r	BCNT r											EPNUM r

Toggle fields

EPNUM

Bits 0-3: Endpoint number.

BCNT

Bits 4-14: Byte count.

DPID

Bits 15-16: Data PID.

PKTSTS

Bits 17-20: Packet status.

FRMNUM

Bits 21-24: Frame number.

GRXSTSR_Host

OTG status debug read (host mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											PKTSTS r				DPID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DPID r	BCNT r											CHNUM r

Toggle fields

CHNUM

Bits 0-3: Channel number.

BCNT

Bits 4-14: Byte count.

DPID

Bits 15-16: Data PID.

PKTSTS

Bits 17-20: Packet status.

GRXSTSP_Device

OTG status read and pop (device mode)

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							FRMNUM r				PKTSTS r				DPID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DPID r	BCNT r											EPNUM r

Toggle fields

EPNUM

Bits 0-3: Endpoint number.

BCNT

Bits 4-14: Byte count.

DPID

Bits 15-16: Data PID.

PKTSTS

Bits 17-20: Packet status.

FRMNUM

Bits 21-24: Frame number.

GRXSTSP_Host

OTG status read and pop (host mode)

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											PKTSTS r				DPID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DPID r	BCNT r											CHNUM r

Toggle fields

CHNUM

Bits 0-3: Channel number.

BCNT

Bits 4-14: Byte count.

DPID

Bits 15-16: Data PID.

PKTSTS

Bits 17-20: Packet status.

GRXFSIZ

OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)

Offset: 0x24, size: 32, reset: 0x00000200, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXFD rw

Toggle fields

RXFD

Bits 0-15: RxFIFO depth.

DIEPTXF0

OTG_FS non-periodic transmit FIFO size register (Device mode)

Offset: 0x28, size: 32, reset: 0x00000200, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TX0FD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TX0FSA rw

Toggle fields

TX0FSA

Bits 0-15: Endpoint 0 transmit RAM start address.

TX0FD

Bits 16-31: Endpoint 0 TxFIFO depth.

HNPTXFSIZ

OTG_FS non-periodic transmit FIFO size register (Host mode)

Offset: 0x28, size: 32, reset: 0x00000200, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
NPTXFD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NPTXFSA rw

Toggle fields

NPTXFSA

Bits 0-15: Non-periodic transmit RAM start address.

NPTXFD

Bits 16-31: Non-periodic TxFIFO depth.

GNPTXSTS

OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)

Offset: 0x2c, size: 32, reset: 0x00080200, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	NPTXQTOP r							NPTQXSAV r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NPTXFSAV r

Toggle fields

NPTXFSAV

Bits 0-15: Non-periodic TxFIFO space available.

NPTQXSAV

Bits 16-23: Non-periodic transmit request queue space available.

NPTXQTOP

Bits 24-30: Top of the non-periodic transmit request queue.

GCCFG

OTG_FS general core configuration register (OTG_FS_GCCFG)

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										NOVBUSSENS rw	SOFOUTEN rw	VBUSBSEN rw	VBUSASEN rw		PWRDWN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

PWRDWN

Bit 16: Power down.

VBUSASEN

Bit 18: Enable the VBUS sensing device.

VBUSBSEN

Bit 19: Enable the VBUS sensing device.

SOFOUTEN

Bit 20: SOF output enable.

NOVBUSSENS

Bit 21: Vbus sensing disable option.

CID

core ID register

Offset: 0x3c, size: 32, reset: 0x00001000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRODUCT_ID rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRODUCT_ID rw

Toggle fields

PRODUCT_ID

Bits 0-31: Product ID field.

HPTXFSIZ

OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)

Offset: 0x100, size: 32, reset: 0x02000600, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PTXFSIZ rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PTXSA rw

Toggle fields

PTXSA

Bits 0-15: Host periodic TxFIFO start address.

PTXFSIZ

Bits 16-31: Host periodic TxFIFO depth.

DIEPTXF[1]

OTF_FS device IN endpoint transmit FIFO size register

Offset: 0x104, size: 32, reset: 0x02000400, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
INEPTXFD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
INEPTXSA rw

Toggle fields

INEPTXSA

Bits 0-15: IN endpoint FIFO2 transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

DIEPTXF[2]

OTF_FS device IN endpoint transmit FIFO size register

Offset: 0x108, size: 32, reset: 0x02000400, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
INEPTXFD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
INEPTXSA rw

Toggle fields

INEPTXSA

Bits 0-15: IN endpoint FIFO2 transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

DIEPTXF[3]

OTF_FS device IN endpoint transmit FIFO size register

Offset: 0x10c, size: 32, reset: 0x02000400, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
INEPTXFD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
INEPTXSA rw

Toggle fields

INEPTXSA

Bits 0-15: IN endpoint FIFO2 transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

OTG_FS_HOST

0x50000400: USB on the go full speed

9/279 fields covered.

Toggle register map

Offset	Name	31	30	29	28	23	21	19	18	17	16	15	14	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	HCFG																							FSLSS	FSLSPCS
0x4	HFIR											FRIVL
0x8	HFNUM	FTREM										FRNUM
0x10	HPTXSTS	PTXQTOP				PTXQSAV						PTXFSAVL
0x14	HAINT											HAINT
0x18	HAINTMSK											HAINTM
0x40	HPRT								PSPD		PTCTL	PTCTL		PPWR	PLSTS			PRST	PSUSP	PRES	POCCHNG	POCA	PENCHNG	PENA	PCDET	PCSTS
0x100	CHAR [0]	CHENA	CHDIS	ODDFRM	DAD		MCNT	EPTYP		LSDEV		EPDIR	EPNUM			MPSIZ
0x108	INT [0]															DTERR	FRMOR	BBERR	TXERR		ACK	NAK	STALL		CHH	XFRC
0x10c	INTMSK [0]															DTERRM	FRMORM	BBERRM	TXERRM	NYET	ACKM	NAKM	STALLM		CHHM	XFRCM
0x110	TSIZ [0]		DPID		PKTCNT				XFRSIZ			XFRSIZ
0x120	CHAR [1]	CHENA	CHDIS	ODDFRM	DAD		MCNT	EPTYP		LSDEV		EPDIR	EPNUM			MPSIZ
0x128	INT [1]															DTERR	FRMOR	BBERR	TXERR		ACK	NAK	STALL		CHH	XFRC
0x12c	INTMSK [1]															DTERRM	FRMORM	BBERRM	TXERRM	NYET	ACKM	NAKM	STALLM		CHHM	XFRCM
0x130	TSIZ [1]		DPID		PKTCNT				XFRSIZ			XFRSIZ
0x140	CHAR [2]	CHENA	CHDIS	ODDFRM	DAD		MCNT	EPTYP		LSDEV		EPDIR	EPNUM			MPSIZ
0x148	INT [2]															DTERR	FRMOR	BBERR	TXERR		ACK	NAK	STALL		CHH	XFRC
0x14c	INTMSK [2]															DTERRM	FRMORM	BBERRM	TXERRM	NYET	ACKM	NAKM	STALLM		CHHM	XFRCM
0x150	TSIZ [2]		DPID		PKTCNT				XFRSIZ			XFRSIZ
0x160	CHAR [3]	CHENA	CHDIS	ODDFRM	DAD		MCNT	EPTYP		LSDEV		EPDIR	EPNUM			MPSIZ
0x168	INT [3]															DTERR	FRMOR	BBERR	TXERR		ACK	NAK	STALL		CHH	XFRC
0x16c	INTMSK [3]															DTERRM	FRMORM	BBERRM	TXERRM	NYET	ACKM	NAKM	STALLM		CHHM	XFRCM
0x170	TSIZ [3]		DPID		PKTCNT				XFRSIZ			XFRSIZ
0x180	CHAR [4]	CHENA	CHDIS	ODDFRM	DAD		MCNT	EPTYP		LSDEV		EPDIR	EPNUM			MPSIZ
0x188	INT [4]															DTERR	FRMOR	BBERR	TXERR		ACK	NAK	STALL		CHH	XFRC
0x18c	INTMSK [4]															DTERRM	FRMORM	BBERRM	TXERRM	NYET	ACKM	NAKM	STALLM		CHHM	XFRCM
0x190	TSIZ [4]		DPID		PKTCNT				XFRSIZ			XFRSIZ
0x1a0	CHAR [5]	CHENA	CHDIS	ODDFRM	DAD		MCNT	EPTYP		LSDEV		EPDIR	EPNUM			MPSIZ
0x1a8	INT [5]															DTERR	FRMOR	BBERR	TXERR		ACK	NAK	STALL		CHH	XFRC
0x1ac	INTMSK [5]															DTERRM	FRMORM	BBERRM	TXERRM	NYET	ACKM	NAKM	STALLM		CHHM	XFRCM
0x1b0	TSIZ [5]		DPID		PKTCNT				XFRSIZ			XFRSIZ
0x1c0	CHAR [6]	CHENA	CHDIS	ODDFRM	DAD		MCNT	EPTYP		LSDEV		EPDIR	EPNUM			MPSIZ
0x1c8	INT [6]															DTERR	FRMOR	BBERR	TXERR		ACK	NAK	STALL		CHH	XFRC
0x1cc	INTMSK [6]															DTERRM	FRMORM	BBERRM	TXERRM	NYET	ACKM	NAKM	STALLM		CHHM	XFRCM
0x1d0	TSIZ [6]		DPID		PKTCNT				XFRSIZ			XFRSIZ
0x1e0	CHAR [7]	CHENA	CHDIS	ODDFRM	DAD		MCNT	EPTYP		LSDEV		EPDIR	EPNUM			MPSIZ
0x1e8	INT [7]															DTERR	FRMOR	BBERR	TXERR		ACK	NAK	STALL		CHH	XFRC
0x1ec	INTMSK [7]															DTERRM	FRMORM	BBERRM	TXERRM	NYET	ACKM	NAKM	STALLM		CHHM	XFRCM
0x1f0	TSIZ [7]		DPID		PKTCNT				XFRSIZ			XFRSIZ

Toggle registers

HCFG

OTG_FS host configuration register (OTG_FS_HCFG)

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													FSLSS rw	FSLSPCS rw

Toggle fields

FSLSPCS

Bits 0-1: FS/LS PHY clock select.

FSLSS

Bit 2: FS- and LS-only support.

HFIR

OTG_FS Host frame interval register

Offset: 0x4, size: 32, reset: 0x0000EA60, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FRIVL rw

Toggle fields

FRIVL

Bits 0-15: Frame interval.

HFNUM

OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)

Offset: 0x8, size: 32, reset: 0x00003FFF, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
FTREM r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FRNUM r

Toggle fields

FRNUM

Bits 0-15: Frame number.

FTREM

Bits 16-31: Frame time remaining.

HPTXSTS

OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)

Offset: 0x10, size: 32, reset: 0x00080100, access: Unspecified

2/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PTXQTOP r								PTXQSAV r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PTXFSAVL rw

Toggle fields

PTXFSAVL

Bits 0-15: Periodic transmit data FIFO space available.

PTXQSAV

Bits 16-23: Periodic transmit request queue space available.

PTXQTOP

Bits 24-31: Top of the periodic transmit request queue.

HAINT

OTG_FS Host all channels interrupt register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
HAINT r

Toggle fields

HAINT

Bits 0-15: Channel interrupts.

HAINTMSK

OTG_FS host all channels interrupt mask register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
HAINTM rw

Toggle fields

HAINTM

Bits 0-15: Channel interrupt mask.

HPRT

OTG_FS host port control and status register (OTG_FS_HPRT)

Offset: 0x40, size: 32, reset: 0x00000000, access: Unspecified

4/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													PSPD r		PTCTL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PTCTL rw			PPWR rw	PLSTS r			PRST rw	PSUSP rw	PRES rw	POCCHNG rw	POCA r	PENCHNG rw	PENA rw	PCDET rw	PCSTS r

Toggle fields

PCSTS

Bit 0: Port connect status.

PCDET

Bit 1: Port connect detected.

PENA

Bit 2: Port enable.

PENCHNG

Bit 3: Port enable/disable change.

POCA

Bit 4: Port overcurrent active.

POCCHNG

Bit 5: Port overcurrent change.

PRES

Bit 6: Port resume.

PSUSP

Bit 7: Port suspend.

PRST

Bit 8: Port reset.

PLSTS

Bits 10-11: Port line status.

PPWR

Bit 12: Port power.

PTCTL

Bits 13-16: Port test control.

PSPD

Bits 17-18: Port speed.

CHAR [0]

OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CHENA rw	CHDIS rw	ODDFRM rw	DAD rw							MCNT rw		EPTYP rw		LSDEV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EPDIR rw	EPNUM rw				MPSIZ rw

Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

INT [0]

OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					DTERR rw	FRMOR rw	BBERR rw	TXERR rw		ACK rw	NAK rw	STALL rw		CHH rw	XFRC rw

Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

INTMSK [0]

OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					DTERRM rw	FRMORM rw	BBERRM rw	TXERRM rw	NYET rw	ACKM rw	NAKM rw	STALLM rw		CHHM rw	XFRCM rw

Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

TSIZ [0]

OTG_FS host channel-0 transfer size register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	DPID rw		PKTCNT rw										XFRSIZ rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
XFRSIZ rw

Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

CHAR [1]

OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CHENA rw	CHDIS rw	ODDFRM rw	DAD rw							MCNT rw		EPTYP rw		LSDEV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EPDIR rw	EPNUM rw				MPSIZ rw

Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

INT [1]

OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)

Offset: 0x128, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					DTERR rw	FRMOR rw	BBERR rw	TXERR rw		ACK rw	NAK rw	STALL rw		CHH rw	XFRC rw

Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

INTMSK [1]

OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					DTERRM rw	FRMORM rw	BBERRM rw	TXERRM rw	NYET rw	ACKM rw	NAKM rw	STALLM rw		CHHM rw	XFRCM rw

Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

TSIZ [1]

OTG_FS host channel-0 transfer size register

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	DPID rw		PKTCNT rw										XFRSIZ rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
XFRSIZ rw

Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

CHAR [2]

OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CHENA rw	CHDIS rw	ODDFRM rw	DAD rw							MCNT rw		EPTYP rw		LSDEV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EPDIR rw	EPNUM rw				MPSIZ rw

Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

INT [2]

OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)

Offset: 0x148, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					DTERR rw	FRMOR rw	BBERR rw	TXERR rw		ACK rw	NAK rw	STALL rw		CHH rw	XFRC rw

Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

INTMSK [2]

OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)

Offset: 0x14c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					DTERRM rw	FRMORM rw	BBERRM rw	TXERRM rw	NYET rw	ACKM rw	NAKM rw	STALLM rw		CHHM rw	XFRCM rw

Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

TSIZ [2]

OTG_FS host channel-0 transfer size register

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	DPID rw		PKTCNT rw										XFRSIZ rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
XFRSIZ rw

Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

CHAR [3]

OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CHENA rw	CHDIS rw	ODDFRM rw	DAD rw							MCNT rw		EPTYP rw		LSDEV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EPDIR rw	EPNUM rw				MPSIZ rw

Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

INT [3]

OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)

Offset: 0x168, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					DTERR rw	FRMOR rw	BBERR rw	TXERR rw		ACK rw	NAK rw	STALL rw		CHH rw	XFRC rw

Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

INTMSK [3]

OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)

Offset: 0x16c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					DTERRM rw	FRMORM rw	BBERRM rw	TXERRM rw	NYET rw	ACKM rw	NAKM rw	STALLM rw		CHHM rw	XFRCM rw

Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

TSIZ [3]

OTG_FS host channel-0 transfer size register

Offset: 0x170, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	DPID rw		PKTCNT rw										XFRSIZ rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
XFRSIZ rw

Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

CHAR [4]

OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CHENA rw	CHDIS rw	ODDFRM rw	DAD rw							MCNT rw		EPTYP rw		LSDEV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EPDIR rw	EPNUM rw				MPSIZ rw

Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

INT [4]

OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					DTERR rw	FRMOR rw	BBERR rw	TXERR rw		ACK rw	NAK rw	STALL rw		CHH rw	XFRC rw

Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

INTMSK [4]

OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					DTERRM rw	FRMORM rw	BBERRM rw	TXERRM rw	NYET rw	ACKM rw	NAKM rw	STALLM rw		CHHM rw	XFRCM rw

Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

TSIZ [4]

OTG_FS host channel-0 transfer size register

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	DPID rw		PKTCNT rw										XFRSIZ rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
XFRSIZ rw

Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

CHAR [5]

OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CHENA rw	CHDIS rw	ODDFRM rw	DAD rw							MCNT rw		EPTYP rw		LSDEV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EPDIR rw	EPNUM rw				MPSIZ rw

Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

INT [5]

OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)

Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					DTERR rw	FRMOR rw	BBERR rw	TXERR rw		ACK rw	NAK rw	STALL rw		CHH rw	XFRC rw

Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

INTMSK [5]

OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					DTERRM rw	FRMORM rw	BBERRM rw	TXERRM rw	NYET rw	ACKM rw	NAKM rw	STALLM rw		CHHM rw	XFRCM rw

Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

TSIZ [5]

OTG_FS host channel-0 transfer size register

Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	DPID rw		PKTCNT rw										XFRSIZ rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
XFRSIZ rw

Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

CHAR [6]

OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)

Offset: 0x1c0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CHENA rw	CHDIS rw	ODDFRM rw	DAD rw							MCNT rw		EPTYP rw		LSDEV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EPDIR rw	EPNUM rw				MPSIZ rw

Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

INT [6]

OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)

Offset: 0x1c8, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					DTERR rw	FRMOR rw	BBERR rw	TXERR rw		ACK rw	NAK rw	STALL rw		CHH rw	XFRC rw

Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

INTMSK [6]

OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)

Offset: 0x1cc, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					DTERRM rw	FRMORM rw	BBERRM rw	TXERRM rw	NYET rw	ACKM rw	NAKM rw	STALLM rw		CHHM rw	XFRCM rw

Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

TSIZ [6]

OTG_FS host channel-0 transfer size register

Offset: 0x1d0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	DPID rw		PKTCNT rw										XFRSIZ rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
XFRSIZ rw

Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

CHAR [7]

OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)

Offset: 0x1e0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CHENA rw	CHDIS rw	ODDFRM rw	DAD rw							MCNT rw		EPTYP rw		LSDEV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EPDIR rw	EPNUM rw				MPSIZ rw

Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

INT [7]

OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)

Offset: 0x1e8, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					DTERR rw	FRMOR rw	BBERR rw	TXERR rw		ACK rw	NAK rw	STALL rw		CHH rw	XFRC rw

Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

INTMSK [7]

OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)

Offset: 0x1ec, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					DTERRM rw	FRMORM rw	BBERRM rw	TXERRM rw	NYET rw	ACKM rw	NAKM rw	STALLM rw		CHHM rw	XFRCM rw

Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

TSIZ [7]

OTG_FS host channel-0 transfer size register

Offset: 0x1f0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	DPID rw		PKTCNT rw										XFRSIZ rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
XFRSIZ rw

Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

OTG_FS_PWRCLK

0x50000e00: USB on the go full speed

0/3 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	PCGCCTL																												PHYSUSP			GATEHCLK	STPPCLK

Toggle registers

PCGCCTL

OTG_FS power and clock gating control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											PHYSUSP rw			GATEHCLK rw	STPPCLK rw

Toggle fields

STPPCLK

Bit 0: Stop PHY clock.

GATEHCLK

Bit 1: Gate HCLK.

PHYSUSP

Bit 4: PHY Suspended.

PWR

0x40007000: Power control

21/21 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR											FISSR	FMSSR					VOS		ADCDC1		MRLVDS	LPLVDS	FPDS	DBP	PLS			PVDE	CSBF	CWUF	PDDS	LPDS
0x4	CSR																		VOSRDY					BRE	EWUP					BRR	PVDO	SBF	WUF

Toggle registers

CR

power control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										FISSR rw	FMSSR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VOS rw		ADCDC1 rw		MRLVDS rw	LPLVDS rw	FPDS rw	DBP rw	PLS rw			PVDE rw	CSBF rw	CWUF rw	PDDS rw	LPDS rw

Toggle fields

LPDS

Bit 0: Low-power deep sleep.

Allowed values:
0: Main: Main voltage regulator ON during Stop mode
1: LowPower: Low-power voltage regulator ON during Stop mode

PDDS

Bit 1: Power down deepsleep.

Allowed values:
0: EnterStop: Enter Stop mode when the CPU enters deepsleep. The regulator status depends on the LPDS bit
1: EnterStandby: Enter Standby mode when the CPU enters deepsleep

CWUF

Bit 2: Clear wakeup flag.

Allowed values:
0: Zero: This bit is always read as 0

CSBF

Bit 3: Clear standby flag.

Allowed values:
0: Zero: This bit is always read as 0

PVDE

Bit 4: Power voltage detector enable.

Allowed values:
0: Disabled: PVD disabled
1: Enabled: PVD enabled

PLS

Bits 5-7: PVD level selection.

Allowed values: 0x0-0x7

DBP

Bit 8: Disable backup domain write protection.

Allowed values:
0: Protected: Access to RTC and RTC Backup registers and backup SRAM disabled
1: Writable: Access to RTC and RTC Backup registers and backup SRAM enabled

FPDS

Bit 9: Flash power down in Stop mode.

Allowed values:
0: Idle: Flash memory not in power-down when the device is in Stop mode
1: PowerDown: Flash memory in power-down when the device is in Stop mode

LPLVDS

Bit 10: Main regulator Low Voltage in Deep Sleep.

Allowed values:
0: On: Low-power regulator on if LPDS bit is set when the device is in Stop mode
1: UnderDrive: Low-power regulator in Low Voltage and Flash memory in Deep Sleep mode if LPDS bit is set when device is in Stop mode

MRLVDS

Bit 11: Main regulator Low Voltage in Deep Sleep.

Allowed values:
0: Scale3: Main regulator in Voltage scale 3 when the device is in Stop mode
1: LowVoltage: Main regulator in Low Voltage and Flash memory in Deep Sleep mode when the device is in Stop mode

ADCDC1

Bit 13: ADCDC1.

Allowed values: 0x0-0x1

VOS

Bits 14-15: Regulator voltage scaling output selection.

Allowed values:
1: Scale3: Scale 3 mode <= 64 MHz
2: Scale2: Scale 2 mode (reset value) <= 84 MHz
3: Scale1: Scale 1 mode <= 100 MHz

FMSSR

Bit 20: Flash Memory Sleep System Run.

Allowed values:
0: Standard: Flash standard mode (Default value)
1: Forced: Flash forced to be in STOP or DeepPower Down mode (depending of FPDS value bit) by hardware

FISSR

Bit 21: Flash Interface Stop while System Run.

Allowed values:
0: Run: Flash Interface clock run (Default value)
1: Off: Flash Interface clock off

CSR

power control/status register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	VOSRDY r					BRE rw	EWUP rw					BRR r	PVDO r	SBF r	WUF r

Toggle fields

WUF

Bit 0: Wakeup flag.

Allowed values:
0: NotOccurred: No wakeup event occurred
1: Occurred: A wakeup event was received from the WKUP pin or from the RTC alarm (Alarm A or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup)

SBF

Bit 1: Standby flag.

Allowed values:
0: InStandby: Device has not been in Standby mode
1: NotInStandby: Device has been in Standby mode

PVDO

Bit 2: PVD output.

Allowed values:
0: Higher: Vdd is higher than the PVD threshold selected with the PLS[2:0] bits
1: Lower: Vdd is lower than the PVD threshold selected with the PLS[2:0] bits

BRR

Bit 3: Backup regulator ready.

Allowed values:
0: NotReady: Backup Regulator not ready
1: Ready: Backup Regulator ready

EWUP

Bit 8: Enable WKUP pin.

Allowed values:
0: GPIO: WKUP1 pin is used for general purpose I/O. An event on the WKUP1 pin does not wakeup the device from Standby mode
1: WakeUp: WKUP1 pin is used for wakeup from Standby mode and forced in input pull down configuration (rising edge or falling on WKUP pin wakes-up the system from Standby mode)

BRE

Bit 9: Backup regulator enable.

Allowed values:
0: Disabled: Backup regulator disabled
1: Enabled: Backup regulator enabled

VOSRDY

Bit 14: Regulator voltage scaling output selection ready bit.

Allowed values:
0: NotReady: Not ready
1: Ready: Ready

RCC

0x40023800: Reset and clock control

177/177 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	5	4	3	2	1	0
0x0	CR					PLLI2SRDY	PLLI2SON	PLLRDY	PLLON					CSSON	HSEBYP	HSERDY	HSEON	HSICAL								HSITRIM					HSIRDY	HSION
0x4	PLLCFGR					PLLQ					PLLSRC					PLLP			PLLN								PLLM
0x8	CFGR	MCO2		MCO2PRE			MCO1PRE			I2SSRC	MCO1		RTCPRE					PPRE2			PPRE1					HPRE			SWS		SW
0xc	CIR									CSSC		PLLI2SRDYC	PLLRDYC	HSERDYC	HSIRDYC	LSERDYC	LSIRDYC			PLLI2SRDYIE	PLLRDYIE	HSERDYIE	HSIRDYIE	LSERDYIE	LSIRDYIE	CSSF	PLLI2SRDYF	PLLRDYF	HSERDYF	HSIRDYF	LSERDYF	LSIRDYF
0x10	AHB1RSTR										DMA2RST	DMA1RST									CRCRST					GPIOHRST		GPIOERST	GPIODRST	GPIOCRST	GPIOBRST	GPIOARST
0x14	AHB2RSTR																									OTGFSRST
0x20	APB1RSTR				PWRRST					I2C3RST	I2C2RST	I2C1RST				USART2RST		SPI3RST	SPI2RST			WWDGRST							TIM5RST	TIM4RST	TIM3RST	TIM2RST
0x24	APB2RSTR												SPI5RST		TIM11RST	TIM10RST	TIM9RST		SYSCFGRST	SPI4RST	SPI1RST	SDIORST			ADCRST		USART6RST	USART1RST				TIM1RST
0x30	AHB1ENR										DMA2EN	DMA1EN									CRCEN					GPIOHEN		GPIOEEN	GPIODEN	GPIOCEN	GPIOBEN	GPIOAEN
0x34	AHB2ENR																									OTGFSEN
0x40	APB1ENR				PWREN					I2C3EN	I2C2EN	I2C1EN				USART2EN		SPI3EN	SPI2EN			WWDGEN							TIM5EN	TIM4EN	TIM3EN	TIM2EN
0x44	APB2ENR												SPI5EN		TIM11EN	TIM10EN	TIM9EN		SYSCFGEN	SPI4EN	SPI1EN	SDIOEN			ADC1EN		USART6EN	USART1EN				TIM1EN
0x50	AHB1LPENR										DMA2LPEN	DMA1LPEN					SRAM1LPEN	FLITFLPEN			CRCLPEN					GPIOHLPEN		GPIOELPEN	GPIODLPEN	GPIOCLPEN	GPIOBLPEN	GPIOALPEN
0x54	AHB2LPENR																									OTGFSLPEN
0x60	APB1LPENR				PWRLPEN					I2C3LPEN	I2C2LPEN	I2C1LPEN				USART2LPEN		SPI3LPEN	SPI2LPEN			WWDGLPEN							TIM5LPEN	TIM4LPEN	TIM3LPEN	TIM2LPEN
0x64	APB2LPENR												SPI5LPEN		TIM11LPEN	TIM10LPEN	TIM9LPEN		SYSCFGLPEN	SPI4LPEN	SPI1LPEN	SDIOLPEN			ADC1LPEN		USART6LPEN	USART1LPEN				TIM1LPEN
0x70	BDCR																BDRST	RTCEN						RTCSEL					LSEMOD	LSEBYP	LSERDY	LSEON
0x74	CSR	LPWRRSTF	WWDGRSTF	WDGRSTF	SFTRSTF	PORRSTF	PADRSTF	BORRSTF	RMVF																						LSIRDY	LSION
0x80	SSCGR	SSCGEN	SPREADSEL			INCSTEP												INCSTEP			MODPER
0x84	PLLI2SCFGR		PLLI2SR																PLLI2SN								PLLI2SM
0x8c	DCKCFGR								TIMPRE

Toggle registers

CR

clock control register

Offset: 0x0, size: 32, reset: 0x00000083, access: Unspecified

12/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				PLLI2SRDY r	PLLI2SON rw	PLLRDY r	PLLON rw					CSSON rw	HSEBYP rw	HSERDY r	HSEON rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
HSICAL r								HSITRIM rw						HSIRDY r	HSION rw

Toggle fields

HSION

Bit 0: Internal high-speed clock enable.

Allowed values:
0: Off: Clock Off
1: On: Clock On

HSIRDY

Bit 1: Internal high-speed clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

HSITRIM

Bits 3-7: Internal high-speed clock trimming.

Allowed values: 0x0-0x1f

HSICAL

Bits 8-15: Internal high-speed clock calibration.

Allowed values: 0x0-0xff

HSEON

Bit 16: HSE clock enable.

Allowed values:
0: Off: Clock Off
1: On: Clock On

HSERDY

Bit 17: HSE clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

HSEBYP

Bit 18: HSE clock bypass.

Allowed values:
0: NotBypassed: HSE crystal oscillator not bypassed
1: Bypassed: HSE crystal oscillator bypassed with external clock

CSSON

Bit 19: Clock security system enable.

Allowed values:
0: Off: Clock security system disabled (clock detector OFF)
1: On: Clock security system enable (clock detector ON if the HSE is ready, OFF if not)

PLLON

Bit 24: Main PLL (PLL) enable.

Allowed values:
0: Off: Clock Off
1: On: Clock On

PLLRDY

Bit 25: Main PLL (PLL) clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

PLLI2SON

Bit 26: PLLI2S enable.

Allowed values:
0: Off: Clock Off
1: On: Clock On

PLLI2SRDY

Bit 27: PLLI2S clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

PLLCFGR

PLL configuration register

Offset: 0x4, size: 32, reset: 0x24003010, access: read-write

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				PLLQ rw					PLLSRC rw					PLLP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	PLLN rw									PLLM rw

Toggle fields

PLLM

Bits 0-5: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock.

Allowed values: 0x2-0x3f

PLLN

Bits 6-14: Main PLL (PLL) multiplication factor for VCO.

Allowed values: 0x32-0x1b0

PLLP

Bits 16-17: Main PLL (PLL) division factor for main system clock.

Allowed values:
0: Div2: PLLP=2
1: Div4: PLLP=4
2: Div6: PLLP=6
3: Div8: PLLP=8

PLLSRC

Bit 22: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source.

Allowed values:
0: HSI: HSI clock selected as PLL and PLLI2S clock entry
1: HSE: HSE oscillator clock selected as PLL and PLLI2S clock entry

PLLQ

Bits 24-27: Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks.

Allowed values: 0x2-0xf

CFGR

clock configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

11/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MCO2 rw		MCO2PRE rw			MCO1PRE rw			I2SSRC rw	MCO1 rw		RTCPRE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PPRE2 rw			PPRE1 rw					HPRE rw				SWS N/A		SW N/A

Toggle fields

SW

Bits 0-1: System clock switch.

Allowed values:
0: HSI: HSI selected as system clock
1: HSE: HSE selected as system clock
2: PLL: PLL selected as system clock

SWS

Bits 2-3: System clock switch status.

Allowed values:
0: HSI: HSI oscillator used as system clock
1: HSE: HSE oscillator used as system clock
2: PLL: PLL used as system clock

HPRE

Bits 4-7: AHB prescaler.

Allowed values:
8: Div2: SYSCLK divided by 2
9: Div4: SYSCLK divided by 4
10: Div8: SYSCLK divided by 8
11: Div16: SYSCLK divided by 16
12: Div64: SYSCLK divided by 64
13: Div128: SYSCLK divided by 128
14: Div256: SYSCLK divided by 256
15: Div512: SYSCLK divided by 512
0 (+): Div1: SYSCLK not divided

PPRE1

Bits 10-12: APB Low speed prescaler (APB1).

Allowed values:
4: Div2: HCLK divided by 2
5: Div4: HCLK divided by 4
6: Div8: HCLK divided by 8
7: Div16: HCLK divided by 16
0 (+): Div1: HCLK not divided

PPRE2

Bits 13-15: APB high-speed prescaler (APB2).

Allowed values:
4: Div2: HCLK divided by 2
5: Div4: HCLK divided by 4
6: Div8: HCLK divided by 8
7: Div16: HCLK divided by 16
0 (+): Div1: HCLK not divided

RTCPRE

Bits 16-20: HSE division factor for RTC clock.

Allowed values: 0x0-0x1f

MCO1

Bits 21-22: Microcontroller clock output 1.

Allowed values:
0: HSI: HSI clock selected
1: LSE: LSE oscillator selected
2: HSE: HSE oscillator clock selected
3: PLL: PLL clock selected

I2SSRC

Bit 23: I2S clock selection.

Allowed values:
0: PLLI2S: PLLI2S clock used as I2S clock source
1: CKIN: External clock mapped on the I2S_CKIN pin used as I2S clock source

MCO1PRE

Bits 24-26: MCO1 prescaler.

Allowed values:
4: Div2: Division by 2
5: Div3: Division by 3
6: Div4: Division by 4
7: Div5: Division by 5
0 (+): Div1: No division

MCO2PRE

Bits 27-29: MCO2 prescaler.

Allowed values:
4: Div2: Division by 2
5: Div3: Division by 3
6: Div4: Division by 4
7: Div5: Division by 5
0 (+): Div1: No division

MCO2

Bits 30-31: Microcontroller clock output 2.

Allowed values:
0: SYSCLK: System clock (SYSCLK) selected
1: PLLI2S: PLLI2S clock selected
2: HSE: HSE oscillator clock selected
3: PLL: PLL clock selected

CIR

clock interrupt register

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

20/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								CSSC w		PLLI2SRDYC w	PLLRDYC w	HSERDYC w	HSIRDYC w	LSERDYC w	LSIRDYC w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		PLLI2SRDYIE rw	PLLRDYIE rw	HSERDYIE rw	HSIRDYIE rw	LSERDYIE rw	LSIRDYIE rw	CSSF r		PLLI2SRDYF r	PLLRDYF r	HSERDYF r	HSIRDYF r	LSERDYF r	LSIRDYF r

Toggle fields

LSIRDYF

Bit 0: LSI ready interrupt flag.

Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt

LSERDYF

Bit 1: LSE ready interrupt flag.

Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt

HSIRDYF

Bit 2: HSI ready interrupt flag.

Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt

HSERDYF

Bit 3: HSE ready interrupt flag.

Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt

PLLRDYF

Bit 4: Main PLL (PLL) ready interrupt flag.

Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt

PLLI2SRDYF

Bit 5: PLLI2S ready interrupt flag.

Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt

CSSF

Bit 7: Clock security system interrupt flag.

Allowed values:
0: NotInterrupted: No clock security interrupt caused by HSE clock failure
1: Interrupted: Clock security interrupt caused by HSE clock failure

LSIRDYIE

Bit 8: LSI ready interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

LSERDYIE

Bit 9: LSE ready interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

HSIRDYIE

Bit 10: HSI ready interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

HSERDYIE

Bit 11: HSE ready interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

PLLRDYIE

Bit 12: Main PLL (PLL) ready interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

PLLI2SRDYIE

Bit 13: PLLI2S ready interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

LSIRDYC

Bit 16: LSI ready interrupt clear.

Allowed values:
1: Clear: Clear interrupt flag

LSERDYC

Bit 17: LSE ready interrupt clear.

Allowed values:
1: Clear: Clear interrupt flag

HSIRDYC

Bit 18: HSI ready interrupt clear.

Allowed values:
1: Clear: Clear interrupt flag

HSERDYC

Bit 19: HSE ready interrupt clear.

Allowed values:
1: Clear: Clear interrupt flag

PLLRDYC

Bit 20: Main PLL(PLL) ready interrupt clear.

Allowed values:
1: Clear: Clear interrupt flag

PLLI2SRDYC

Bit 21: PLLI2S ready interrupt clear.

Allowed values:
1: Clear: Clear interrupt flag

CSSC

Bit 23: Clock security system interrupt clear.

Allowed values:
1: Clear: Clear CSSF flag

AHB1RSTR

AHB1 peripheral reset register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									DMA2RST rw	DMA1RST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CRCRST rw					GPIOHRST rw			GPIOERST rw	GPIODRST rw	GPIOCRST rw	GPIOBRST rw	GPIOARST rw

Toggle fields

GPIOARST

Bit 0: IO port A reset.

Allowed values:
1: Reset: Reset the selected module

GPIOBRST

Bit 1: IO port B reset.

Allowed values:
1: Reset: Reset the selected module

GPIOCRST

Bit 2: IO port C reset.

Allowed values:
1: Reset: Reset the selected module

GPIODRST

Bit 3: IO port D reset.

Allowed values:
1: Reset: Reset the selected module

GPIOERST

Bit 4: IO port E reset.

Allowed values:
1: Reset: Reset the selected module

GPIOHRST

Bit 7: IO port H reset.

Allowed values:
1: Reset: Reset the selected module

CRCRST

Bit 12: CRC reset.

Allowed values:
1: Reset: Reset the selected module

DMA1RST

Bit 21: DMA2 reset.

Allowed values:
1: Reset: Reset the selected module

DMA2RST

Bit 22: DMA2 reset.

Allowed values:
1: Reset: Reset the selected module

AHB2RSTR

AHB2 peripheral reset register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								OTGFSRST rw

Toggle fields

OTGFSRST

Bit 7: USB OTG FS module reset.

Allowed values:
1: Reset: Reset the selected module

APB1RSTR

APB1 peripheral reset register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			PWRRST rw					I2C3RST rw	I2C2RST rw	I2C1RST rw				USART2RST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SPI3RST rw	SPI2RST rw			WWDGRST rw								TIM5RST rw	TIM4RST rw	TIM3RST rw	TIM2RST rw

Toggle fields

TIM2RST

Bit 0: TIM2 reset.

Allowed values:
1: Reset: Reset the selected module

TIM3RST

Bit 1: TIM3 reset.

Allowed values:
1: Reset: Reset the selected module

TIM4RST

Bit 2: TIM4 reset.

Allowed values:
1: Reset: Reset the selected module

TIM5RST

Bit 3: TIM5 reset.

Allowed values:
1: Reset: Reset the selected module

WWDGRST

Bit 11: Window watchdog reset.

Allowed values:
1: Reset: Reset the selected module

SPI2RST

Bit 14: SPI 2 reset.

Allowed values:
1: Reset: Reset the selected module

SPI3RST

Bit 15: SPI 3 reset.

Allowed values:
1: Reset: Reset the selected module

USART2RST

Bit 17: USART 2 reset.

Allowed values:
1: Reset: Reset the selected module

I2C1RST

Bit 21: I2C 1 reset.

Allowed values:
1: Reset: Reset the selected module

I2C2RST

Bit 22: I2C 2 reset.

Allowed values:
1: Reset: Reset the selected module

I2C3RST

Bit 23: I2C3 reset.

Allowed values:
1: Reset: Reset the selected module

PWRRST

Bit 28: Power interface reset.

Allowed values:
1: Reset: Reset the selected module

APB2RSTR

APB2 peripheral reset register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											SPI5RST rw		TIM11RST rw	TIM10RST rw	TIM9RST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SYSCFGRST rw	SPI4RST rw	SPI1RST rw	SDIORST rw			ADCRST rw			USART6RST rw	USART1RST rw				TIM1RST rw

Toggle fields

TIM1RST

Bit 0: TIM1 reset.

Allowed values:
1: Reset: Reset the selected module

USART1RST

Bit 4: USART1 reset.

Allowed values:
1: Reset: Reset the selected module

USART6RST

Bit 5: USART6 reset.

Allowed values:
1: Reset: Reset the selected module

ADCRST

Bit 8: ADC interface reset (common to all ADCs).

Allowed values:
1: Reset: Reset the selected module

SDIORST

Bit 11: SDIO reset.

Allowed values:
1: Reset: Reset the selected module

SPI1RST

Bit 12: SPI 1 reset.

Allowed values:
1: Reset: Reset the selected module

SPI4RST

Bit 13: SPI4 reset.

Allowed values:
1: Reset: Reset the selected module

SYSCFGRST

Bit 14: System configuration controller reset.

Allowed values:
1: Reset: Reset the selected module

TIM9RST

Bit 16: TIM9 reset.

Allowed values:
1: Reset: Reset the selected module

TIM10RST

Bit 17: TIM10 reset.

Allowed values:
1: Reset: Reset the selected module

TIM11RST

Bit 18: TIM11 reset.

Allowed values:
1: Reset: Reset the selected module

SPI5RST

Bit 20: SPI5 reset.

Allowed values:
1: Reset: Reset the selected module

AHB1ENR

AHB1 peripheral clock register

Offset: 0x30, size: 32, reset: 0x00100000, access: read-write

9/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									DMA2EN rw	DMA1EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CRCEN rw					GPIOHEN rw			GPIOEEN rw	GPIODEN rw	GPIOCEN rw	GPIOBEN rw	GPIOAEN rw

Toggle fields

GPIOAEN

Bit 0: IO port A clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOBEN

Bit 1: IO port B clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOCEN

Bit 2: IO port C clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIODEN

Bit 3: IO port D clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOEEN

Bit 4: IO port E clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOHEN

Bit 7: IO port H clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

CRCEN

Bit 12: CRC clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

DMA1EN

Bit 21: DMA1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

DMA2EN

Bit 22: DMA2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

AHB2ENR

AHB2 peripheral clock enable register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								OTGFSEN rw

Toggle fields

OTGFSEN

Bit 7: USB OTG FS clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

APB1ENR

APB1 peripheral clock enable register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			PWREN rw					I2C3EN rw	I2C2EN rw	I2C1EN rw				USART2EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SPI3EN rw	SPI2EN rw			WWDGEN rw								TIM5EN rw	TIM4EN rw	TIM3EN rw	TIM2EN rw

Toggle fields

TIM2EN

Bit 0: TIM2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM3EN

Bit 1: TIM3 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM4EN

Bit 2: TIM4 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM5EN

Bit 3: TIM5 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

WWDGEN

Bit 11: Window watchdog clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SPI2EN

Bit 14: SPI2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SPI3EN

Bit 15: SPI3 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USART2EN

Bit 17: USART 2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

I2C1EN

Bit 21: I2C1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

I2C2EN

Bit 22: I2C2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

I2C3EN

Bit 23: I2C3 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

PWREN

Bit 28: Power interface clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

APB2ENR

APB2 peripheral clock enable register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											SPI5EN rw		TIM11EN rw	TIM10EN rw	TIM9EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SYSCFGEN rw	SPI4EN rw	SPI1EN rw	SDIOEN rw			ADC1EN rw			USART6EN rw	USART1EN rw				TIM1EN rw

Toggle fields

TIM1EN

Bit 0: TIM1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USART1EN

Bit 4: USART1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USART6EN

Bit 5: USART6 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

ADC1EN

Bit 8: ADC1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SDIOEN

Bit 11: SDIO clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SPI1EN

Bit 12: SPI1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SPI4EN

Bit 13: SPI4 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SYSCFGEN

Bit 14: System configuration controller clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM9EN

Bit 16: TIM9 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM10EN

Bit 17: TIM10 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM11EN

Bit 18: TIM11 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SPI5EN

Bit 20: SPI5 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

AHB1LPENR

AHB1 peripheral clock enable in low power mode register

Offset: 0x50, size: 32, reset: 0x7E6791FF, access: read-write

11/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									DMA2LPEN rw	DMA1LPEN rw					SRAM1LPEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FLITFLPEN rw			CRCLPEN rw					GPIOHLPEN rw			GPIOELPEN rw	GPIODLPEN rw	GPIOCLPEN rw	GPIOBLPEN rw	GPIOALPEN rw

Toggle fields

GPIOALPEN

Bit 0: IO port A clock enable during sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

GPIOBLPEN

Bit 1: IO port B clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

GPIOCLPEN

Bit 2: IO port C clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

GPIODLPEN

Bit 3: IO port D clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

GPIOELPEN

Bit 4: IO port E clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

GPIOHLPEN

Bit 7: IO port H clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

CRCLPEN

Bit 12: CRC clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

FLITFLPEN

Bit 15: Flash interface clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

SRAM1LPEN

Bit 16: SRAM 1interface clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

DMA1LPEN

Bit 21: DMA1 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

DMA2LPEN

Bit 22: DMA2 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

AHB2LPENR

AHB2 peripheral clock enable in low power mode register

Offset: 0x54, size: 32, reset: 0x000000F1, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								OTGFSLPEN rw

Toggle fields

OTGFSLPEN

Bit 7: USB OTG FS clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

APB1LPENR

APB1 peripheral clock enable in low power mode register

Offset: 0x60, size: 32, reset: 0x36FEC9FF, access: read-write

12/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			PWRLPEN rw					I2C3LPEN rw	I2C2LPEN rw	I2C1LPEN rw				USART2LPEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SPI3LPEN rw	SPI2LPEN rw			WWDGLPEN rw								TIM5LPEN rw	TIM4LPEN rw	TIM3LPEN rw	TIM2LPEN rw

Toggle fields

TIM2LPEN

Bit 0: TIM2 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

TIM3LPEN

Bit 1: TIM3 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

TIM4LPEN

Bit 2: TIM4 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

TIM5LPEN

Bit 3: TIM5 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

WWDGLPEN

Bit 11: Window watchdog clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

SPI2LPEN

Bit 14: SPI2 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

SPI3LPEN

Bit 15: SPI3 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

USART2LPEN

Bit 17: USART2 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

I2C1LPEN

Bit 21: I2C1 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

I2C2LPEN

Bit 22: I2C2 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

I2C3LPEN

Bit 23: I2C3 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

PWRLPEN

Bit 28: Power interface clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

APB2LPENR

APB2 peripheral clock enabled in low power mode register

Offset: 0x64, size: 32, reset: 0x00075F33, access: read-write

12/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											SPI5LPEN rw		TIM11LPEN rw	TIM10LPEN rw	TIM9LPEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SYSCFGLPEN rw	SPI4LPEN rw	SPI1LPEN rw	SDIOLPEN rw			ADC1LPEN rw			USART6LPEN rw	USART1LPEN rw				TIM1LPEN rw

Toggle fields

TIM1LPEN

Bit 0: TIM1 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

USART1LPEN

Bit 4: USART1 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

USART6LPEN

Bit 5: USART6 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

ADC1LPEN

Bit 8: ADC1 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

SDIOLPEN

Bit 11: SDIO clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

SPI1LPEN

Bit 12: SPI 1 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

SPI4LPEN

Bit 13: SPI4 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

SYSCFGLPEN

Bit 14: System configuration controller clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

TIM9LPEN

Bit 16: TIM9 clock enable during sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

TIM10LPEN

Bit 17: TIM10 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

TIM11LPEN

Bit 18: TIM11 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

SPI5LPEN

Bit 20: SPI5 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

BDCR

Backup domain control register

Offset: 0x70, size: 32, reset: 0x00000000, access: Unspecified

7/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															BDRST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RTCEN rw						RTCSEL N/A						LSEMOD N/A	LSEBYP rw	LSERDY r	LSEON rw

Toggle fields

LSEON

Bit 0: External low-speed oscillator enable.

Allowed values:
0: Off: LSE oscillator Off
1: On: LSE oscillator On

LSERDY

Bit 1: External low-speed oscillator ready.

Allowed values:
0: NotReady: LSE oscillator not ready
1: Ready: LSE oscillator ready

LSEBYP

Bit 2: External low-speed oscillator bypass.

Allowed values:
0: NotBypassed: LSE crystal oscillator not bypassed
1: Bypassed: LSE crystal oscillator bypassed with external clock

LSEMOD

Bit 3: External low speed oscillator.

Allowed values:
0: Low: LSE oscillator low power mode selection
1: High: LSE oscillator high drive mode selection

RTCSEL

Bits 8-9: RTC clock source selection.

Allowed values:
0: NoClock: No clock
1: LSE: LSE oscillator clock used as RTC clock
2: LSI: LSI oscillator clock used as RTC clock
3: HSE: HSE oscillator clock divided by a prescaler used as RTC clock

RTCEN

Bit 15: RTC clock enable.

Allowed values:
0: Disabled: RTC clock disabled
1: Enabled: RTC clock enabled

BDRST

Bit 16: Backup domain software reset.

Allowed values:
0: Disabled: Reset not activated
1: Enabled: Reset the entire RTC domain

CSR

clock control & status register

Offset: 0x74, size: 32, reset: 0x0E000000, access: Unspecified

10/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LPWRRSTF rw	WWDGRSTF rw	WDGRSTF rw	SFTRSTF rw	PORRSTF rw	PADRSTF rw	BORRSTF rw	RMVF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														LSIRDY r	LSION rw

Toggle fields

LSION

Bit 0: Internal low-speed oscillator enable.

Allowed values:
0: Off: LSI oscillator Off
1: On: LSI oscillator On

LSIRDY

Bit 1: Internal low-speed oscillator ready.

Allowed values:
0: NotReady: LSI oscillator not ready
1: Ready: LSI oscillator ready

RMVF

Bit 24: Remove reset flag.

Allowed values:
1: Clear: Clears the reset flag

BORRSTF

Bit 25: BOR reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

PADRSTF

Bit 26: PIN reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

PORRSTF

Bit 27: POR/PDR reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

SFTRSTF

Bit 28: Software reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

WDGRSTF

Bit 29: Independent watchdog reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

WWDGRSTF

Bit 30: Window watchdog reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

LPWRRSTF

Bit 31: Low-power reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

SSCGR

spread spectrum clock generation register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SSCGEN rw	SPREADSEL rw			INCSTEP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
INCSTEP rw			MODPER rw

Toggle fields

MODPER

Bits 0-12: Modulation period.

Allowed values: 0x0-0x1fff

INCSTEP

Bits 13-27: Incrementation step.

Allowed values: 0x0-0x7fff

SPREADSEL

Bit 30: Spread Select.

Allowed values:
0: Center: Center spread
1: Down: Down spread

SSCGEN

Bit 31: Spread spectrum modulation enable.

Allowed values:
0: Disabled: Spread spectrum modulation disabled
1: Enabled: Spread spectrum modulation enabled

PLLI2SCFGR

PLLI2S configuration register

Offset: 0x84, size: 32, reset: 0x20003000, access: read-write

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	PLLI2SR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	PLLI2SN rw									PLLI2SM rw

Toggle fields

PLLI2SM

Bits 0-5: Division factor for the audio PLL (PLLI2S) input clock.

Allowed values: 0x2-0x3f

PLLI2SN

Bits 6-14: PLLI2S multiplication factor for VCO.

Allowed values: 0x32-0x1b0

PLLI2SR

Bits 28-30: PLLI2S division factor for I2S clocks.

Allowed values: 0x2-0x7

DCKCFGR

RCC Dedicated Clock Configuration Register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							TIMPRE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

TIMPRE

Bit 24: Timers clocks prescalers selection.

Allowed values:
0: Mul1Or2: If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx
1: Mul1Or4: If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx

RTC

0x40002800: Real-time clock

128/144 fields covered.

Toggle register map

Offset	Name	31	30	29	27	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	TR						PM	HT		HU					MNT			MNU					ST			SU
0x4	DR					YT				YU				WDU			MT	MU						DT		DU
0x8	CR					COE	OSEL		POL	COSEL	BKP	SUB1H	ADD1H	TSIE	WUTIE	ALRBIE	ALRAIE	TSE	WUTE	ALRBE	ALRAE	DCE	FMT	BYPSHAD	REFCKON	TSEDGE	WUCKSEL
0xc	ISR												RECALPF		TAMP2F	TAMP1F	TSOVF	TSF	WUTF	ALRBF	ALRAF	INIT	INITF	RSF	INITS	SHPF	WUTWF	ALRBWF	ALRAWF
0x10	PRER						PREDIV_A								PREDIV_S
0x14	WUTR													WUT
0x18	CALIBR																					DCS			DC
0x1c	ALRM[A]R	MSK4	WDSEL	DT	DU	MSK3	PM	HT		HU				MSK2	MNT			MNU				MSK1	ST			SU
0x20	ALRM[B]R	MSK4	WDSEL	DT	DU	MSK3	PM	HT		HU				MSK2	MNT			MNU				MSK1	ST			SU
0x24	WPR																					KEY
0x28	SSR													SS
0x2c	SHIFTR	ADD1S													SUBFS
0x30	TSTR						PM	HT		HU					MNT			MNU					ST			SU
0x34	TSDR					YT				YU				WDU			MT	MU						DT		DU
0x38	TSSSR													SS
0x3c	CALR													CALP	CALW8	CALW16					CALM
0x40	TAFCR										ALARMOUTTYPE	TSINSEL	TAMP1INSEL	TAMPPUDIS	TAMPPRCH		TAMPFLT		TAMPFREQ			TAMPTS			TAMP2TRG	TAMP2E	TAMPIE	TAMP1TRG	TAMP1E
0x44	ALRM[A]SSR				MASKSS										SS
0x48	ALRM[B]SSR				MASKSS										SS
0x50	BKP[0]R	BKP												BKP
0x54	BKP[1]R	BKP												BKP
0x58	BKP[2]R	BKP												BKP
0x5c	BKP[3]R	BKP												BKP
0x60	BKP[4]R	BKP												BKP
0x64	BKP[5]R	BKP												BKP
0x68	BKP[6]R	BKP												BKP
0x6c	BKP[7]R	BKP												BKP
0x70	BKP[8]R	BKP												BKP
0x74	BKP[9]R	BKP												BKP
0x78	BKP[10]R	BKP												BKP
0x7c	BKP[11]R	BKP												BKP
0x80	BKP[12]R	BKP												BKP
0x84	BKP[13]R	BKP												BKP
0x88	BKP[14]R	BKP												BKP
0x8c	BKP[15]R	BKP												BKP
0x90	BKP[16]R	BKP												BKP
0x94	BKP[17]R	BKP												BKP
0x98	BKP[18]R	BKP												BKP
0x9c	BKP[19]R	BKP												BKP

Toggle registers

TR

time register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									PM rw	HT rw		HU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MNT rw			MNU rw					ST rw			SU rw

Toggle fields

SU

Bits 0-3: Second units in BCD format.

Allowed values: 0x0-0xf

ST

Bits 4-6: Second tens in BCD format.

Allowed values: 0x0-0x7

MNU

Bits 8-11: Minute units in BCD format.

Allowed values: 0x0-0xf

MNT

Bits 12-14: Minute tens in BCD format.

Allowed values: 0x0-0x7

HU

Bits 16-19: Hour units in BCD format.

Allowed values: 0x0-0xf

HT

Bits 20-21: Hour tens in BCD format.

Allowed values: 0x0-0x3

PM

Bit 22: AM/PM notation.

Allowed values:
0: AM: AM or 24-hour format
1: PM: PM

DR

date register

Offset: 0x4, size: 32, reset: 0x00002101, access: read-write

7/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								YT rw				YU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WDU rw			MT rw	MU rw						DT rw		DU rw

Toggle fields

DU

Bits 0-3: Date units in BCD format.

Allowed values: 0x0-0xf

DT

Bits 4-5: Date tens in BCD format.

Allowed values: 0x0-0x3

MU

Bits 8-11: Month units in BCD format.

Allowed values: 0x0-0xf

MT

Bit 12: Month tens in BCD format.

Allowed values:
0: Zero: Month tens is 0
1: One: Month tens is 1

WDU

Bits 13-15: Week day units.

Allowed values: 0x1-0x7

YU

Bits 16-19: Year units in BCD format.

Allowed values: 0x0-0xf

YT

Bits 20-23: Year tens in BCD format.

Allowed values: 0x0-0xf

CR

control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

20/21 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								COE rw	OSEL rw		POL rw	COSEL rw	BKP rw	SUB1H rw	ADD1H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TSIE rw	WUTIE rw	ALRBIE rw	ALRAIE rw	TSE rw	WUTE rw	ALRBE rw	ALRAE rw	DCE rw	FMT rw	BYPSHAD rw	REFCKON rw	TSEDGE rw	WUCKSEL rw

Toggle fields

WUCKSEL

Bits 0-2: Wakeup clock selection.

Allowed values:
0: Div16: RTC/16 clock is selected
1: Div8: RTC/8 clock is selected
2: Div4: RTC/4 clock is selected
3: Div2: RTC/2 clock is selected
4: ClockSpare: ck_spre (usually 1 Hz) clock is selected
6: ClockSpareWithOffset: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value

TSEDGE

Bit 3: Time-stamp event active edge.

Allowed values:
0: RisingEdge: RTC_TS input rising edge generates a time-stamp event
1: FallingEdge: RTC_TS input falling edge generates a time-stamp event

REFCKON

Bit 4: Reference clock detection enable (50 or 60 Hz).

Allowed values:
0: Disabled: RTC_REFIN detection disabled
1: Enabled: RTC_REFIN detection enabled

BYPSHAD

Bit 5: Bypass the shadow registers.

Allowed values:
0: ShadowReg: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles
1: BypassShadowReg: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters

FMT

Bit 6: Hour format.

Allowed values:
0: Twenty_Four_Hour: 24 hour/day format
1: AM_PM: AM/PM hour format

DCE

Bit 7: Coarse digital calibration enable.

ALRAE

Bit 8: Alarm A enable.

Allowed values:
0: Disabled: Alarm A disabled
1: Enabled: Alarm A enabled

ALRBE

Bit 9: Alarm B enable.

Allowed values:
0: Disabled: Alarm B disabled
1: Enabled: Alarm B enabled

WUTE

Bit 10: Wakeup timer enable.

Allowed values:
0: Disabled: Wakeup timer disabled
1: Enabled: Wakeup timer enabled

TSE

Bit 11: Time stamp enable.

Allowed values:
0: Disabled: Timestamp disabled
1: Enabled: Timestamp enabled

ALRAIE

Bit 12: Alarm A interrupt enable.

Allowed values:
0: Disabled: Alarm A interrupt disabled
1: Enabled: Alarm A interrupt enabled

ALRBIE

Bit 13: Alarm B interrupt enable.

Allowed values:
0: Disabled: Alarm B Interrupt disabled
1: Enabled: Alarm B Interrupt enabled

WUTIE

Bit 14: Wakeup timer interrupt enable.

Allowed values:
0: Disabled: Wakeup timer interrupt disabled
1: Enabled: Wakeup timer interrupt enabled

TSIE

Bit 15: Time-stamp interrupt enable.

Allowed values:
0: Disabled: Time-stamp Interrupt disabled
1: Enabled: Time-stamp Interrupt enabled

ADD1H

Bit 16: Add 1 hour (summer time change).

Allowed values:
1: Add1: Adds 1 hour to the current time. This can be used for summer time change outside initialization mode

SUB1H

Bit 17: Subtract 1 hour (winter time change).

Allowed values:
1: Sub1: Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode

BKP

Bit 18: Backup.

Allowed values:
0: DST_Not_Changed: Daylight Saving Time change has not been performed
1: DST_Changed: Daylight Saving Time change has been performed

COSEL

Bit 19: Calibration Output selection.

Allowed values:
0: CalFreq_512Hz: Calibration output is 512 Hz (with default prescaler setting)
1: CalFreq_1Hz: Calibration output is 1 Hz (with default prescaler setting)

POL

Bit 20: Output polarity.

Allowed values:
0: High: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])
1: Low: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])

OSEL

Bits 21-22: Output selection.

Allowed values:
0: Disabled: Output disabled
1: AlarmA: Alarm A output enabled
2: AlarmB: Alarm B output enabled
3: Wakeup: Wakeup output enabled

COE

Bit 23: Calibration output enable.

Allowed values:
0: Disabled: Calibration output disabled
1: Enabled: Calibration output enabled

ISR

initialization and status register

Offset: 0xc, size: 32, reset: 0x00000007, access: Unspecified

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															RECALPF r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TAMP2F rw	TAMP1F rw	TSOVF rw	TSF rw	WUTF rw	ALRBF rw	ALRAF rw	INIT rw	INITF r	RSF rw	INITS r	SHPF rw	WUTWF r	ALRBWF r	ALRAWF r

Toggle fields

ALRAWF

Bit 0: Alarm A write flag.

Allowed values:
0: UpdateNotAllowed: Alarm update not allowed
1: UpdateAllowed: Alarm update allowed

ALRBWF

Bit 1: Alarm B write flag.

Allowed values:
0: UpdateNotAllowed: Alarm update not allowed
1: UpdateAllowed: Alarm update allowed

WUTWF

Bit 2: Wakeup timer write flag.

Allowed values:
0: UpdateNotAllowed: Wakeup timer configuration update not allowed
1: UpdateAllowed: Wakeup timer configuration update allowed

SHPF

Bit 3: Shift operation pending.

Allowed values:
0: NoShiftPending: No shift operation is pending
1: ShiftPending: A shift operation is pending

INITS

Bit 4: Initialization status flag.

Allowed values:
0: NotInitalized: Calendar has not been initialized
1: Initalized: Calendar has been initialized

RSF

Bit 5: Registers synchronization flag.

Allowed values:
0: NotSynced: Calendar shadow registers not yet synchronized
1: Synced: Calendar shadow registers synchronized

INITF

Bit 6: Initialization flag.

Allowed values:
0: NotAllowed: Calendar registers update is not allowed
1: Allowed: Calendar registers update is allowed

INIT

Bit 7: Initialization mode.

Allowed values:
0: FreeRunningMode: Free running mode
1: InitMode: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.

ALRAF

Bit 8: Alarm A flag.

Allowed values:
1: Match: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR)

ALRBF

Bit 9: Alarm B flag.

Allowed values:
1: Match: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR)

WUTF

Bit 10: Wakeup timer flag.

Allowed values:
1: Zero: This flag is set by hardware when the wakeup auto-reload counter reaches 0

TSF

Bit 11: Time-stamp flag.

Allowed values:
1: TimestampEvent: This flag is set by hardware when a time-stamp event occurs

TSOVF

Bit 12: Time-stamp overflow flag.

Allowed values:
1: Overflow: This flag is set by hardware when a time-stamp event occurs while TSF is already set

TAMP1F

Bit 13: Tamper detection flag.

Allowed values:
1: Tampered: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input

TAMP2F

Bit 14: TAMPER2 detection flag.

Allowed values:
1: Tampered: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input

RECALPF

Bit 16: Recalibration pending Flag.

Allowed values:
1: Pending: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0

PRER

prescaler register

Offset: 0x10, size: 32, reset: 0x007F00FF, access: read-write

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									PREDIV_A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	PREDIV_S rw

Toggle fields

PREDIV_S

Bits 0-14: Synchronous prescaler factor.

Allowed values: 0x0-0x7fff

PREDIV_A

Bits 16-22: Asynchronous prescaler factor.

Allowed values: 0x0-0x7f

WUTR

wakeup timer register

Offset: 0x14, size: 32, reset: 0x0000FFFF, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WUT rw

Toggle fields

WUT

Bits 0-15: Wakeup auto-reload value bits.

Allowed values: 0x0-0xffff

CALIBR

calibration register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								DCS rw			DC rw

Toggle fields

DC

Bits 0-4: Digital calibration.

DCS

Bit 7: Digital calibration sign.

ALRM[A]R

Alarm A register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MSK4 rw	WDSEL rw	DT rw		DU rw				MSK3 rw	PM rw	HT rw		HU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MSK2 rw	MNT rw			MNU rw				MSK1 rw	ST rw			SU rw

Toggle fields

SU

Bits 0-3: Second units in BCD format.

Allowed values: 0x0-0xf

ST

Bits 4-6: Second tens in BCD format.

Allowed values: 0x0-0x7

MSK1

Bit 7: Alarm seconds mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

MNU

Bits 8-11: Minute units in BCD format.

Allowed values: 0x0-0xf

MNT

Bits 12-14: Minute tens in BCD format.

Allowed values: 0x0-0x7

MSK2

Bit 15: Alarm minutes mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

HU

Bits 16-19: Hour units in BCD format.

Allowed values: 0x0-0xf

HT

Bits 20-21: Hour tens in BCD format.

Allowed values: 0x0-0x3

PM

Bit 22: AM/PM notation.

Allowed values:
0: AM: AM or 24-hour format
1: PM: PM

MSK3

Bit 23: Alarm hours mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

DU

Bits 24-27: Date units or day in BCD format.

Allowed values: 0x0-0xf

DT

Bits 28-29: Date tens in BCD format.

Allowed values: 0x0-0x3

WDSEL

Bit 30: Week day selection.

Allowed values:
0: DateUnits: DU[3:0] represents the date units
1: WeekDay: DU[3:0] represents the week day. DT[1:0] is don’t care.

MSK4

Bit 31: Alarm date mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

ALRM[B]R

Alarm B register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MSK4 rw	WDSEL rw	DT rw		DU rw				MSK3 rw	PM rw	HT rw		HU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MSK2 rw	MNT rw			MNU rw				MSK1 rw	ST rw			SU rw

Toggle fields

SU

Bits 0-3: Second units in BCD format.

Allowed values: 0x0-0xf

ST

Bits 4-6: Second tens in BCD format.

Allowed values: 0x0-0x7

MSK1

Bit 7: Alarm seconds mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

MNU

Bits 8-11: Minute units in BCD format.

Allowed values: 0x0-0xf

MNT

Bits 12-14: Minute tens in BCD format.

Allowed values: 0x0-0x7

MSK2

Bit 15: Alarm minutes mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

HU

Bits 16-19: Hour units in BCD format.

Allowed values: 0x0-0xf

HT

Bits 20-21: Hour tens in BCD format.

Allowed values: 0x0-0x3

PM

Bit 22: AM/PM notation.

Allowed values:
0: AM: AM or 24-hour format
1: PM: PM

MSK3

Bit 23: Alarm hours mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

DU

Bits 24-27: Date units or day in BCD format.

Allowed values: 0x0-0xf

DT

Bits 28-29: Date tens in BCD format.

Allowed values: 0x0-0x3

WDSEL

Bit 30: Week day selection.

Allowed values:
0: DateUnits: DU[3:0] represents the date units
1: WeekDay: DU[3:0] represents the week day. DT[1:0] is don’t care.

MSK4

Bit 31: Alarm date mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

WPR

write protection register

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								KEY w

Toggle fields

KEY

Bits 0-7: Write protection key.

Allowed values: 0x0-0xff

SSR

sub second register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SS r

Toggle fields

SS

Bits 0-15: Sub second value.

Allowed values: 0x0-0xffff

SHIFTR

shift control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: write-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD1S w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SUBFS w

Toggle fields

SUBFS

Bits 0-14: Subtract a fraction of a second.

Allowed values: 0x0-0x7fff

ADD1S

Bit 31: Add one second.

Allowed values:
1: Add1: Add one second to the clock/calendar

TSTR

time stamp time register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									PM rw	HT rw		HU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MNT rw			MNU rw					ST rw			SU rw

Toggle fields

SU

Bits 0-3: Second units in BCD format.

Allowed values: 0x0-0xf

ST

Bits 4-6: Second tens in BCD format.

Allowed values: 0x0-0x7

MNU

Bits 8-11: Minute units in BCD format.

Allowed values: 0x0-0xf

MNT

Bits 12-14: Minute tens in BCD format.

Allowed values: 0x0-0x7

HU

Bits 16-19: Hour units in BCD format.

Allowed values: 0x0-0xf

HT

Bits 20-21: Hour tens in BCD format.

Allowed values: 0x0-0x3

PM

Bit 22: AM/PM notation.

Allowed values:
0: AM: AM or 24-hour format
1: PM: PM

TSDR

time stamp date register

Offset: 0x34, size: 32, reset: 0x00002101, access: read-write

7/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								YT rw				YU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WDU rw			MT rw	MU rw						DT rw		DU rw

Toggle fields

DU

Bits 0-3: Date units in BCD format.

Allowed values: 0x0-0xf

DT

Bits 4-5: Date tens in BCD format.

Allowed values: 0x0-0x3

MU

Bits 8-11: Month units in BCD format.

Allowed values: 0x0-0xf

MT

Bit 12: Month tens in BCD format.

Allowed values:
0: Zero: Month tens is 0
1: One: Month tens is 1

WDU

Bits 13-15: Week day units.

Allowed values: 0x1-0x7

YU

Bits 16-19: Year units in BCD format.

Allowed values: 0x0-0xf

YT

Bits 20-23: Year tens in BCD format.

Allowed values: 0x0-0xf

TSSSR

timestamp sub second register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SS r

Toggle fields

SS

Bits 0-15: Sub second value.

Allowed values: 0x0-0xffff

CALR

calibration register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CALP rw	CALW8 rw	CALW16 rw					CALM rw

Toggle fields

CALM

Bits 0-8: Calibration minus.

Allowed values: 0x0-0x1ff

CALW16

Bit 13: Use a 16-second calibration cycle period.

Allowed values:
1: Sixteen_Second: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1

CALW8

Bit 14: Use an 8-second calibration cycle period.

Allowed values:
1: Eight_Second: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected

CALP

Bit 15: Increase frequency of RTC by 488.5 ppm.

Allowed values:
0: NoChange: No RTCCLK pulses are added
1: IncreaseFreq: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm)

TAFCR

tamper and alternate function configuration register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													ALARMOUTTYPE rw	TSINSEL rw	TAMP1INSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TAMPPUDIS rw	TAMPPRCH rw		TAMPFLT rw		TAMPFREQ rw			TAMPTS rw			TAMP2TRG rw	TAMP2E rw	TAMPIE rw	TAMP1TRG rw	TAMP1E rw

Toggle fields

TAMP1E

Bit 0: Tamper 1 detection enable.

TAMP1TRG

Bit 1: Active level for tamper 1.

TAMPIE

Bit 2: Tamper interrupt enable.

TAMP2E

Bit 3: Tamper 2 detection enable.

TAMP2TRG

Bit 4: Active level for tamper 2.

TAMPTS

Bit 7: Activate timestamp on tamper detection event.

TAMPFREQ

Bits 8-10: Tamper sampling frequency.

TAMPFLT

Bits 11-12: Tamper filter count.

TAMPPRCH

Bits 13-14: Tamper precharge duration.

TAMPPUDIS

Bit 15: TAMPER pull-up disable.

TAMP1INSEL

Bit 16: TAMPER1 mapping.

TSINSEL

Bit 17: TIMESTAMP mapping.

ALARMOUTTYPE

Bit 18: AFO_ALARM output type.

ALRM[A]SSR

Alarm A sub-second register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				MASKSS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SS rw

Toggle fields

SS

Bits 0-14: Sub seconds value.

Allowed values: 0x0-0x7fff

MASKSS

Bits 24-27: Mask the most-significant bits starting at this bit.

Allowed values: 0x0-0xf

ALRM[B]SSR

Alarm B sub-second register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				MASKSS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SS rw

Toggle fields

SS

Bits 0-14: Sub seconds value.

Allowed values: 0x0-0x7fff

MASKSS

Bits 24-27: Mask the most-significant bits starting at this bit.

Allowed values: 0x0-0xf

BKP[0]R

backup register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[1]R

backup register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[2]R

backup register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[3]R

backup register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[4]R

backup register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[5]R

backup register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[6]R

backup register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[7]R

backup register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[8]R

backup register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[9]R

backup register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[10]R

backup register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[11]R

backup register

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[12]R

backup register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[13]R

backup register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[14]R

backup register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[15]R

backup register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[16]R

backup register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[17]R

backup register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[18]R

backup register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

BKP[19]R

backup register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle fields

BKP

Bits 0-31: BKP.

Allowed values: 0x0-0xffffffff

SCB

0xe000ed00: System control block

5/74 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	19	18	17	16	15	14	13	12	11	10	9	8	7	5	4	3	2	1	0
0x0	CPUID	Implementer								Variant		Constant				PartNo											Revision
0x4	ICSR	NMIPENDSET			PENDSVSET	PENDSVCLR	PENDSTSET	PENDSTCLR			ISRPENDING		VECTPENDING			VECTPENDING				RETTOBASE			VECTACTIVE
0x8	VTOR			TBLOFF												TBLOFF
0xc	AIRCR	VECTKEYSTAT														ENDIANESS					PRIGROUP							SYSRESETREQ	VECTCLRACTIVE	VECTRESET
0x10	SCR																									SEVEONPEND		SLEEPDEEP	SLEEPONEXIT
0x14	CCR																					STKALIGN	BFHFNMIGN			DIV_0_TRP	UNALIGN__TRP		USERSETMPEND	NONBASETHRDENA
0x18	SHPR1									PRI_6						PRI_5								PRI_4
0x1c	SHPR2	PRI_11
0x20	SHPR3	PRI_15								PRI_14
0x24	SHCRS												USGFAULTENA	BUSFAULTENA	MEMFAULTENA	SVCALLPENDED	BUSFAULTPENDED	MEMFAULTPENDED	USGFAULTPENDED	SYSTICKACT	PENDSVACT		MONITORACT	SVCALLACT			USGFAULTACT		BUSFAULTACT	MEMFAULTACT
0x28	CFSR_UFSR_BFSR_MMFSR							DIVBYZERO	UNALIGNED			NOCP	INVPC	INVSTATE	UNDEFINSTR	BFARVALID		LSPERR	STKERR	UNSTKERR	IMPRECISERR	PRECISERR	IBUSERR	MMARVALID	MLSPERR	MSTKERR	MUNSTKERR		IACCVIOL
0x2c	HFSR	DEBUG_VT	FORCED																										VECTTBL
0x34	MMFAR	MMFAR														MMFAR
0x38	BFAR	BFAR														BFAR
0x3c	AFSR	IMPDEF														IMPDEF

Toggle registers

CPUID

CPUID base register

Offset: 0x0, size: 32, reset: 0x410FC241, access: read-only

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Implementer r								Variant r				Constant r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PartNo r												Revision r

Toggle fields

Revision

Bits 0-3: Revision number.

PartNo

Bits 4-15: Part number of the processor.

Constant

Bits 16-19: Reads as 0xF.

Variant

Bits 20-23: Variant number.

Implementer

Bits 24-31: Implementer code.

ICSR

Interrupt control and state register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
NMIPENDSET rw			PENDSVSET rw	PENDSVCLR rw	PENDSTSET rw	PENDSTCLR rw			ISRPENDING rw				VECTPENDING rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VECTPENDING rw				RETTOBASE rw			VECTACTIVE rw

Toggle fields

VECTACTIVE

Bits 0-8: Active vector.

RETTOBASE

Bit 11: Return to base level.

VECTPENDING

Bits 12-18: Pending vector.

ISRPENDING

Bit 22: Interrupt pending flag.

PENDSTCLR

Bit 25: SysTick exception clear-pending bit.

PENDSTSET

Bit 26: SysTick exception set-pending bit.

PENDSVCLR

Bit 27: PendSV clear-pending bit.

PENDSVSET

Bit 28: PendSV set-pending bit.

NMIPENDSET

Bit 31: NMI set-pending bit..

VTOR

Vector table offset register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		TBLOFF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TBLOFF rw

Toggle fields

TBLOFF

Bits 9-29: Vector table base offset field.

AIRCR

Application interrupt and reset control register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
VECTKEYSTAT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ENDIANESS rw					PRIGROUP rw								SYSRESETREQ rw	VECTCLRACTIVE rw	VECTRESET rw

Toggle fields

VECTRESET

Bit 0: VECTRESET.

VECTCLRACTIVE

Bit 1: VECTCLRACTIVE.

SYSRESETREQ

Bit 2: SYSRESETREQ.

PRIGROUP

Bits 8-10: PRIGROUP.

ENDIANESS

Bit 15: ENDIANESS.

VECTKEYSTAT

Bits 16-31: Register key.

SCR

System control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											SEVEONPEND rw		SLEEPDEEP rw	SLEEPONEXIT rw

Toggle fields

SLEEPONEXIT

Bit 1: SLEEPONEXIT.

SLEEPDEEP

Bit 2: SLEEPDEEP.

SEVEONPEND

Bit 4: Send Event on Pending bit.

CCR

Configuration and control register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						STKALIGN rw	BFHFNMIGN rw				DIV_0_TRP rw	UNALIGN__TRP rw		USERSETMPEND rw	NONBASETHRDENA rw

Toggle fields

NONBASETHRDENA

Bit 0: Configures how the processor enters Thread mode.

USERSETMPEND

Bit 1: USERSETMPEND.

UNALIGN__TRP

Bit 3: UNALIGN_ TRP.

DIV_0_TRP

Bit 4: DIV_0_TRP.

BFHFNMIGN

Bit 8: BFHFNMIGN.

STKALIGN

Bit 9: STKALIGN.

SHPR1

System handler priority registers

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRI_6 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRI_5 rw								PRI_4 rw

Toggle fields

PRI_4

Bits 0-7: Priority of system handler 4.

PRI_5

Bits 8-15: Priority of system handler 5.

PRI_6

Bits 16-23: Priority of system handler 6.

SHPR2

System handler priority registers

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRI_11 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

PRI_11

Bits 24-31: Priority of system handler 11.

SHPR3

System handler priority registers

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRI_15 rw								PRI_14 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

PRI_14

Bits 16-23: Priority of system handler 14.

PRI_15

Bits 24-31: Priority of system handler 15.

SHCRS

System handler control and state register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													USGFAULTENA rw	BUSFAULTENA rw	MEMFAULTENA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SVCALLPENDED rw	BUSFAULTPENDED rw	MEMFAULTPENDED rw	USGFAULTPENDED rw	SYSTICKACT rw	PENDSVACT rw		MONITORACT rw	SVCALLACT rw				USGFAULTACT rw		BUSFAULTACT rw	MEMFAULTACT rw

Toggle fields

MEMFAULTACT

Bit 0: Memory management fault exception active bit.

BUSFAULTACT

Bit 1: Bus fault exception active bit.

USGFAULTACT

Bit 3: Usage fault exception active bit.

SVCALLACT

Bit 7: SVC call active bit.

MONITORACT

Bit 8: Debug monitor active bit.

PENDSVACT

Bit 10: PendSV exception active bit.

SYSTICKACT

Bit 11: SysTick exception active bit.

USGFAULTPENDED

Bit 12: Usage fault exception pending bit.

MEMFAULTPENDED

Bit 13: Memory management fault exception pending bit.

BUSFAULTPENDED

Bit 14: Bus fault exception pending bit.

SVCALLPENDED

Bit 15: SVC call pending bit.

MEMFAULTENA

Bit 16: Memory management fault enable bit.

BUSFAULTENA

Bit 17: Bus fault enable bit.

USGFAULTENA

Bit 18: Usage fault enable bit.

CFSR_UFSR_BFSR_MMFSR

Configurable fault status register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						DIVBYZERO rw	UNALIGNED rw					NOCP rw	INVPC rw	INVSTATE rw	UNDEFINSTR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BFARVALID rw		LSPERR rw	STKERR rw	UNSTKERR rw	IMPRECISERR rw	PRECISERR rw	IBUSERR rw	MMARVALID rw		MLSPERR rw	MSTKERR rw	MUNSTKERR rw		IACCVIOL rw

Toggle fields

IACCVIOL

Bit 1: Instruction access violation flag.

MUNSTKERR

Bit 3: Memory manager fault on unstacking for a return from exception.

MSTKERR

Bit 4: Memory manager fault on stacking for exception entry..

MLSPERR

Bit 5: MLSPERR.

MMARVALID

Bit 7: Memory Management Fault Address Register (MMAR) valid flag.

IBUSERR

Bit 8: Instruction bus error.

PRECISERR

Bit 9: Precise data bus error.

IMPRECISERR

Bit 10: Imprecise data bus error.

UNSTKERR

Bit 11: Bus fault on unstacking for a return from exception.

STKERR

Bit 12: Bus fault on stacking for exception entry.

LSPERR

Bit 13: Bus fault on floating-point lazy state preservation.

BFARVALID

Bit 15: Bus Fault Address Register (BFAR) valid flag.

UNDEFINSTR

Bit 16: Undefined instruction usage fault.

INVSTATE

Bit 17: Invalid state usage fault.

INVPC

Bit 18: Invalid PC load usage fault.

NOCP

Bit 19: No coprocessor usage fault..

UNALIGNED

Bit 24: Unaligned access usage fault.

DIVBYZERO

Bit 25: Divide by zero usage fault.

HFSR

Hard fault status register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DEBUG_VT rw	FORCED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														VECTTBL rw

Toggle fields

VECTTBL

Bit 1: Vector table hard fault.

FORCED

Bit 30: Forced hard fault.

DEBUG_VT

Bit 31: Reserved for Debug use.

MMFAR

Memory management fault address register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MMFAR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MMFAR rw

Toggle fields

MMFAR

Bits 0-31: Memory management fault address.

BFAR

Bus fault address register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BFAR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BFAR rw

Toggle fields

BFAR

Bits 0-31: Bus fault address.

AFSR

Auxiliary fault status register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IMPDEF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IMPDEF rw

Toggle fields

IMPDEF

Bits 0-31: Implementation defined.

SCB_ACTRL

0xe000e008: System control block ACTLR

0/5 fields covered.

Toggle register map

Offset	Name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	ACTRL																							DISOOFP	DISFPCA						DISFOLD	DISDEFWBUF	DISMCYCINT

Toggle registers

ACTRL

Auxiliary control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						DISOOFP rw	DISFPCA rw						DISFOLD rw	DISDEFWBUF rw	DISMCYCINT rw

Toggle fields

DISMCYCINT

Bit 0: DISMCYCINT.

DISDEFWBUF

Bit 1: DISDEFWBUF.

DISFOLD

Bit 2: DISFOLD.

DISFPCA

Bit 8: DISFPCA.

DISOOFP

Bit 9: DISOOFP.

SDIO

0x40012c00: Secure digital input/output interface

98/98 fields covered.

Toggle register map

Offset	Name	31	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	POWER																									PWRCTRL
0x4	CLKCR												HWFC_EN	NEGEDGE	WIDBUS		BYPASS	PWRSAV	CLKEN	CLKDIV
0x8	ARG	CMDARG										CMDARG
0xc	CMD												CE_ATACMD	nIEN	ENCMDcompl	SDIOSuspend	CPSMEN	WAITPEND	WAITINT	WAITRESP		CMDINDEX
0x10	RESPCMD																					RESPCMD
0x14	RESP[1]	CARDSTATUS										CARDSTATUS
0x18	RESP[2]	CARDSTATUS										CARDSTATUS
0x1c	RESP[3]	CARDSTATUS										CARDSTATUS
0x20	RESP[4]	CARDSTATUS										CARDSTATUS
0x24	DTIMER	DATATIME										DATATIME
0x28	DLEN		DATALENGTH									DATALENGTH
0x2c	DCTRL															SDIOEN	RWMOD	RWSTOP	RWSTART	DBLOCKSIZE				DMAEN	DTMODE	DTDIR	DTEN
0x30	DCOUNT		DATACOUNT									DATACOUNT
0x34	STA			CEATAEND	SDIOIT	RXDAVL	TXDAVL	RXFIFOE	TXFIFOE	RXFIFOF	TXFIFOF	RXFIFOHF	TXFIFOHE	RXACT	TXACT	CMDACT	DBCKEND	STBITERR	DATAEND	CMDSENT	CMDREND	RXOVERR	TXUNDERR	DTIMEOUT	CTIMEOUT	DCRCFAIL	CCRCFAIL
0x38	ICR			CEATAENDC	SDIOITC												DBCKENDC	STBITERRC	DATAENDC	CMDSENTC	CMDRENDC	RXOVERRC	TXUNDERRC	DTIMEOUTC	CTIMEOUTC	DCRCFAILC	CCRCFAILC
0x3c	MASK			CEATAENDIE	SDIOITIE	RXDAVLIE	TXDAVLIE	RXFIFOEIE	TXFIFOEIE	RXFIFOFIE	TXFIFOFIE	RXFIFOHFIE	TXFIFOHEIE	RXACTIE	TXACTIE	CMDACTIE	DBCKENDIE	STBITERRIE	DATAENDIE	CMDSENTIE	CMDRENDIE	RXOVERRIE	TXUNDERRIE	DTIMEOUTIE	CTIMEOUTIE	DCRCFAILIE	CCRCFAILIE
0x48	FIFOCNT			FIFOCOUNT								FIFOCOUNT
0x80	FIFO	FIFOData										FIFOData

Toggle registers

POWER

power control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														PWRCTRL rw

Toggle fields

PWRCTRL

Bits 0-1: PWRCTRL.

Allowed values:
0: PowerOff: Power off
3: PowerOn: Power on

CLKCR

SDI clock control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	HWFC_EN rw	NEGEDGE rw	WIDBUS rw		BYPASS rw	PWRSAV rw	CLKEN rw	CLKDIV rw

Toggle fields

CLKDIV

Bits 0-7: Clock divide factor.

Allowed values: 0x0-0xff

CLKEN

Bit 8: Clock enable bit.

Allowed values:
0: Disabled: Disable clock
1: Enabled: Enable clock

PWRSAV

Bit 9: Power saving configuration bit.

Allowed values:
0: Enabled: SDIO_CK clock is always enabled
1: Disabled: SDIO_CK is only enabled when the bus is active

BYPASS

Bit 10: Clock divider bypass enable bit.

Allowed values:
0: Disabled: SDIOCLK is divided according to the CLKDIV value before driving the SDIO_CK output signal.
1: Enabled: SDIOCLK directly drives the SDIO_CK output signal

WIDBUS

Bits 11-12: Wide bus mode enable bit.

Allowed values:
0: BusWidth1: 1 lane wide bus
1: BusWidth4: 4 lane wide bus
2: BusWidth8: 8 lane wide bus

NEGEDGE

Bit 13: SDIO_CK dephasing selection bit.

Allowed values:
0: Rising: SDIO_CK generated on the rising edge
1: Falling: SDIO_CK generated on the falling edge

HWFC_EN

Bit 14: HW Flow Control enable.

Allowed values:
0: Disabled: HW Flow Control is disabled
1: Enabled: HW Flow Control is enabled

ARG

argument register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CMDARG rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CMDARG rw

Toggle fields

CMDARG

Bits 0-31: Command argument.

Allowed values: 0x0-0xffffffff

CMD

command register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	CE_ATACMD rw	nIEN rw	ENCMDcompl rw	SDIOSuspend rw	CPSMEN rw	WAITPEND rw	WAITINT rw	WAITRESP rw		CMDINDEX rw

Toggle fields

CMDINDEX

Bits 0-5: Command index.

Allowed values: 0x0-0x3f

WAITRESP

Bits 6-7: Wait for response bits.

Allowed values:
0: NoResponse: No response
1: ShortResponse: Short response
2: NoResponse2: No reponse
3: LongResponse: Long reponse

WAITINT

Bit 8: CPSM waits for interrupt request.

Allowed values:
0: Disabled: Don't wait for interrupt request
1: Enabled: Wait for interrupt request

WAITPEND

Bit 9: CPSM Waits for ends of data transfer (CmdPend internal signal)..

Allowed values:
0: Disabled: Don't wait for data end
1: Enabled: Wait for end of data transfer signal before sending command

CPSMEN

Bit 10: Command path state machine (CPSM) Enable bit.

Allowed values:
0: Disabled: Command path state machine disabled
1: Enabled: Command path state machine enabled

SDIOSuspend

Bit 11: SD I/O suspend command.

Allowed values:
0: Disabled: Next command is not a SDIO suspend command
1: Enabled: Next command send is a SDIO suspend command

ENCMDcompl

Bit 12: Enable CMD completion.

Allowed values:
0: Disabled: Command complete signal disabled
1: Enabled: Command complete signal enabled

nIEN

Bit 13: not Interrupt Enable.

Allowed values:
0: Disabled: Interrupts to the CE-ATA not disabled
1: Enabled: Interrupt to the CE-ATA are disabled

CE_ATACMD

Bit 14: CE-ATA command.

Allowed values:
0: Disabled: CE-ATA command disabled
1: Enabled: CE-ATA command enabled

RESPCMD

command response register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										RESPCMD r

Toggle fields

RESPCMD

Bits 0-5: Response command index.

Allowed values: 0x0-0x3f

RESP[1]

SDIO response 1 register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CARDSTATUS r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CARDSTATUS r

Toggle fields

CARDSTATUS

Bits 0-31: Status of a card, which is part of the received response.

Allowed values: 0x0-0xffffffff

RESP[2]

SDIO response 2 register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CARDSTATUS r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CARDSTATUS r

Toggle fields

CARDSTATUS

Bits 0-31: Status of a card, which is part of the received response.

Allowed values: 0x0-0xffffffff

RESP[3]

SDIO response 3 register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CARDSTATUS r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CARDSTATUS r

Toggle fields

CARDSTATUS

Bits 0-31: Status of a card, which is part of the received response.

Allowed values: 0x0-0xffffffff

RESP[4]

SDIO response 4 register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CARDSTATUS r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CARDSTATUS r

Toggle fields

CARDSTATUS

Bits 0-31: Status of a card, which is part of the received response.

Allowed values: 0x0-0xffffffff

DTIMER

data timer register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DATATIME rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATATIME rw

Toggle fields

DATATIME

Bits 0-31: Data timeout period.

Allowed values: 0x0-0xffffffff

DLEN

data length register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							DATALENGTH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATALENGTH rw

Toggle fields

DATALENGTH

Bits 0-24: Data length value.

Allowed values: 0x0-0x1ffffff

DCTRL

data control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				SDIOEN rw	RWMOD rw	RWSTOP rw	RWSTART rw	DBLOCKSIZE rw				DMAEN rw	DTMODE rw	DTDIR rw	DTEN rw

Toggle fields

DTEN

Bit 0: DTEN.

Allowed values:
0: Disabled: Disabled
1: Enabled: Start transfer

DTDIR

Bit 1: Data transfer direction selection.

Allowed values:
0: ControllerToCard: From controller to card
1: CardToController: From card to controller

DTMODE

Bit 2: Data transfer mode selection 1: Stream or SDIO multibyte data transfer..

Allowed values:
0: BlockMode: Bloack data transfer
1: StreamMode: Stream or SDIO multibyte data transfer

DMAEN

Bit 3: DMA enable bit.

Allowed values:
0: Disabled: Dma disabled
1: Enabled: Dma enabled

DBLOCKSIZE

Bits 4-7: Data block size.

Allowed values: 0x0-0xf

RWSTART

Bit 8: Read wait start.

Allowed values:
0: Disabled: Don't start read wait operation
1: Enabled: Read wait operation starts

RWSTOP

Bit 9: Read wait stop.

Allowed values:
0: Disabled: Read wait in progress if RWSTART is enabled
1: Enabled: Enable for read wait stop if RWSTART is enabled

RWMOD

Bit 10: Read wait mode.

Allowed values:
0: D2: Read wait control stopping using SDIO_D2
1: Ck: Read wait control using SDIO_CK

SDIOEN

Bit 11: SD I/O enable functions.

Allowed values:
0: Disabled: SDIO operations disabled
1: Enabled: SDIO operations enabled

DCOUNT

data counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							DATACOUNT r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATACOUNT r

Toggle fields

DATACOUNT

Bits 0-24: Data count value.

Allowed values: 0x0-0x1ffffff

STA

status register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

24/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								CEATAEND r	SDIOIT r	RXDAVL r	TXDAVL r	RXFIFOE r	TXFIFOE r	RXFIFOF r	TXFIFOF r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXFIFOHF r	TXFIFOHE r	RXACT r	TXACT r	CMDACT r	DBCKEND r	STBITERR r	DATAEND r	CMDSENT r	CMDREND r	RXOVERR r	TXUNDERR r	DTIMEOUT r	CTIMEOUT r	DCRCFAIL r	CCRCFAIL r

Toggle fields

CCRCFAIL

Bit 0: Command response received (CRC check failed).

Allowed values:
0: NotFailed: Command response received, crc check passed
1: Failed: Command response received, crc check failed

DCRCFAIL

Bit 1: Data block sent/received (CRC check failed).

Allowed values:
0: NotFailed: No Data block sent/received crc check fail
1: Failed: Data block sent/received crc failed

CTIMEOUT

Bit 2: Command response timeout.

Allowed values:
0: NoTimeout: No Command timeout
1: Timeout: Command timeout

DTIMEOUT

Bit 3: Data timeout.

Allowed values:
0: NoTimeout: No data timeout
1: Timeout: Data timeout

TXUNDERR

Bit 4: Transmit FIFO underrun error.

Allowed values:
0: NoUnderrun: No transmit FIFO underrun error
1: Underrun: Transmit FIFO underrun error

RXOVERR

Bit 5: Received FIFO overrun error.

Allowed values:
0: NoOverrun: No FIFO overrun error
1: Overrun: Receive FIFO overrun error

CMDREND

Bit 6: Command response received (CRC check passed).

Allowed values:
0: NotDone: Command not done
1: Done: Command response received (CRC check passed)

CMDSENT

Bit 7: Command sent (no response required).

Allowed values:
0: NotSent: Command not sent
1: Sent: Command sent (no response required)

DATAEND

Bit 8: Data end (data counter, SDIDCOUNT, is zero).

Allowed values:
0: NotDone: Not done
1: Done: Data end (DCOUNT, is zero)

STBITERR

Bit 9: Start bit not detected on all data signals in wide bus mode.

Allowed values:
0: Detected: No start bit detected error
1: NotDetected: Start bit not detected error

DBCKEND

Bit 10: Data block sent/received (CRC check passed).

Allowed values:
0: NotTransferred: Data block not sent/received (CRC check failed)
1: Transferred: Data block sent/received (CRC check passed)

CMDACT

Bit 11: Command transfer in progress.

Allowed values:
0: NotInProgress: Command transfer not in progress
1: InProgress: Command tranfer in progress

TXACT

Bit 12: Data transmit in progress.

Allowed values:
0: NotInProgress: Data transmit is not in progress
1: InProgress: Data transmit in progress

RXACT

Bit 13: Data receive in progress.

Allowed values:
0: NotInProgress: Data receive not in progress
1: InProgress: Data receive in progress

TXFIFOHE

Bit 14: Transmit FIFO half empty: at least 8 words can be written into the FIFO.

Allowed values:
0: NotHalfEmpty: Transmit FIFO not half empty
1: HalfEmpty: Transmit FIFO half empty. At least 8 words can be written into the FIFO

RXFIFOHF

Bit 15: Receive FIFO half full: there are at least 8 words in the FIFO.

Allowed values:
0: NotHalfFull: Receive FIFO not half full
1: HalfFull: Receive FIFO half full. At least 8 words in the FIFO

TXFIFOF

Bit 16: Transmit FIFO full.

Allowed values:
0: NotFull: Transmit FIFO not full
1: Full: Transmit FIFO full

RXFIFOF

Bit 17: Receive FIFO full.

Allowed values:
0: NotFull: Transmit FIFO not full
1: Full: Receive FIFO full. When HW Flow Control is enabled, RXFIFOF signals becomes activated 2 words before the FIFO is full.

TXFIFOE

Bit 18: Transmit FIFO empty.

Allowed values:
0: NotEmpty: Transmit FIFO not empty
1: Empty: Transmit FIFO empty. When HW Flow Control is enabled, TXFIFOE signals becomes activated when the FIFO contains 2 words.

RXFIFOE

Bit 19: Receive FIFO empty.

Allowed values:
0: NotEmpty: Receive FIFO not empty
1: Empty: Receive FIFO empty

TXDAVL

Bit 20: Data available in transmit FIFO.

Allowed values:
0: NotAvailable: Data not available in transmit FIFO
1: Available: Data available in transmit FIFO

RXDAVL

Bit 21: Data available in receive FIFO.

Allowed values:
0: NotAvailable: Data not available in receive FIFO
1: Available: Data available in receive FIFO

SDIOIT

Bit 22: SDIO interrupt received.

Allowed values:
0: NotReceived: SDIO interrupt not receieved
1: Received: SDIO interrupt received

CEATAEND

Bit 23: CE-ATA command completion signal received for CMD61.

Allowed values:
0: NotReceived: Completion signal not received
1: Received: CE-ATA command completion signal received for CMD61

ICR

interrupt clear register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

13/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								CEATAENDC rw	SDIOITC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					DBCKENDC rw	STBITERRC rw	DATAENDC rw	CMDSENTC rw	CMDRENDC rw	RXOVERRC rw	TXUNDERRC rw	DTIMEOUTC rw	CTIMEOUTC rw	DCRCFAILC rw	CCRCFAILC rw

Toggle fields

CCRCFAILC

Bit 0: CCRCFAIL flag clear bit.

Allowed values:
1: Clear: Clear flag

DCRCFAILC

Bit 1: DCRCFAIL flag clear bit.

Allowed values:
1: Clear: Clear flag

CTIMEOUTC

Bit 2: CTIMEOUT flag clear bit.

Allowed values:
1: Clear: Clear flag

DTIMEOUTC

Bit 3: DTIMEOUT flag clear bit.

Allowed values:
1: Clear: Clear flag

TXUNDERRC

Bit 4: TXUNDERR flag clear bit.

Allowed values:
1: Clear: Clear flag

RXOVERRC

Bit 5: RXOVERR flag clear bit.

Allowed values:
1: Clear: Clear flag

CMDRENDC

Bit 6: CMDREND flag clear bit.

Allowed values:
1: Clear: Clear flag

CMDSENTC

Bit 7: CMDSENT flag clear bit.

Allowed values:
1: Clear: Clear flag

DATAENDC

Bit 8: DATAEND flag clear bit.

Allowed values:
1: Clear: Clear flag

STBITERRC

Bit 9: STBITERR flag clear bit.

Allowed values:
1: Clear: Clear flag

DBCKENDC

Bit 10: DBCKEND flag clear bit.

Allowed values:
1: Clear: Clear flag

SDIOITC

Bit 22: SDIOIT flag clear bit.

Allowed values:
1: Clear: Clear flag

CEATAENDC

Bit 23: CEATAEND flag clear bit.

Allowed values:
1: Clear: Clear flag

MASK

mask register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								CEATAENDIE rw	SDIOITIE rw	RXDAVLIE rw	TXDAVLIE rw	RXFIFOEIE rw	TXFIFOEIE rw	RXFIFOFIE rw	TXFIFOFIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXFIFOHFIE rw	TXFIFOHEIE rw	RXACTIE rw	TXACTIE rw	CMDACTIE rw	DBCKENDIE rw	STBITERRIE rw	DATAENDIE rw	CMDSENTIE rw	CMDRENDIE rw	RXOVERRIE rw	TXUNDERRIE rw	DTIMEOUTIE rw	CTIMEOUTIE rw	DCRCFAILIE rw	CCRCFAILIE rw

Toggle fields

CCRCFAILIE

Bit 0: Command CRC fail interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

DCRCFAILIE

Bit 1: Data CRC fail interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CTIMEOUTIE

Bit 2: Command timeout interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

DTIMEOUTIE

Bit 3: Data timeout interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TXUNDERRIE

Bit 4: Tx FIFO underrun error interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

RXOVERRIE

Bit 5: Rx FIFO overrun error interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CMDRENDIE

Bit 6: Command response received interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CMDSENTIE

Bit 7: Command sent interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

DATAENDIE

Bit 8: Data end interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

STBITERRIE

Bit 9: Start bit error interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

DBCKENDIE

Bit 10: Data block end interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CMDACTIE

Bit 11: Command acting interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TXACTIE

Bit 12: Data transmit acting interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

RXACTIE

Bit 13: Data receive acting interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TXFIFOHEIE

Bit 14: Tx FIFO half empty interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

RXFIFOHFIE

Bit 15: Rx FIFO half full interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TXFIFOFIE

Bit 16: Tx FIFO full interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

RXFIFOFIE

Bit 17: Rx FIFO full interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TXFIFOEIE

Bit 18: Tx FIFO empty interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

RXFIFOEIE

Bit 19: Rx FIFO empty interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TXDAVLIE

Bit 20: Data available in Tx FIFO interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

RXDAVLIE

Bit 21: Data available in Rx FIFO interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

SDIOITIE

Bit 22: SDIO mode interrupt received interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CEATAENDIE

Bit 23: CE-ATA command completion signal received interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

FIFOCNT

FIFO counter register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								FIFOCOUNT r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FIFOCOUNT r

Toggle fields

FIFOCOUNT

Bits 0-23: Remaining number of words to be written to or read from the FIFO..

Allowed values: 0x0-0xffffff

FIFO

data FIFO register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
FIFOData rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FIFOData rw

Toggle fields

FIFOData

Bits 0-31: Receive and transmit FIFO data.

Allowed values: 0x0-0xffffffff

SPI1

0x40013000: Serial peripheral interface

46/46 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0 (16-bit)	CR1	BIDIMODE	BIDIOE	CRCEN	CRCNEXT	DFF	RXONLY	SSM	SSI	LSBFIRST	SPE	BR			MSTR	CPOL	CPHA
0x4 (16-bit)	CR2									TXEIE	RXNEIE	ERRIE	FRF		SSOE	TXDMAEN	RXDMAEN
0x8 (16-bit)	SR								FRE	BSY	OVR	MODF	CRCERR	UDR	CHSIDE	TXE	RXNE
0xc (16-bit)	DR	DR
0xc (8-bit)	DR8									DR
0x10 (16-bit)	CRCPR	CRCPOLY
0x14 (16-bit)	RXCRCR	RxCRC
0x18 (16-bit)	TXCRCR	TxCRC
0x1c (16-bit)	I2SCFGR					I2SMOD	I2SE	I2SCFG		PCMSYNC		I2SSTD		CKPOL	DATLEN		CHLEN
0x20 (16-bit)	I2SPR							MCKOE	ODD	I2SDIV

Toggle registers

CR1

control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

14/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIDIMODE rw	BIDIOE rw	CRCEN rw	CRCNEXT rw	DFF rw	RXONLY rw	SSM rw	SSI rw	LSBFIRST rw	SPE rw	BR rw			MSTR rw	CPOL rw	CPHA rw

Toggle fields

CPHA

Bit 0: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 1: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

MSTR

Bit 2: Master selection.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

BR

Bits 3-5: Baud rate control.

Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256

SPE

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LSBFIRST

Bit 7: Frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SSI

Bit 8: Internal slave select.

Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored

SSM

Bit 9: Software slave management.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

RXONLY

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)

DFF

Bit 11: Data frame format.

Allowed values:
0: EightBit: 8-bit data frame format is selected for transmission/reception
1: SixteenBit: 16-bit data frame format is selected for transmission/reception

CRCNEXT

Bit 12: CRC transfer next.

Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register

CRCEN

Bit 13: Hardware CRC calculation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BIDIOE

Bit 14: Output enable in bidirectional mode.

Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)

BIDIMODE

Bit 15: Bidirectional data mode enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CR2

control register 2

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TXEIE rw	RXNEIE rw	ERRIE rw	FRF rw		SSOE rw	TXDMAEN rw	RXDMAEN rw

Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 1: Tx buffer DMA enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

SSOE

Bit 2: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

FRF

Bit 4: Frame format.

Allowed values:
0: Motorola: SPI Motorola mode
1: TI: SPI TI mode

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked

TXEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked

SR

status register

Offset: 0x8, size: 16, reset: 0x00000002, access: Unspecified

9/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							FRE r	BSY r	OVR r	MODF r	CRCERR rw	UDR r	CHSIDE r	TXE r	RXNE r

Toggle fields

RXNE

Bit 0: Receive buffer not empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXE

Bit 1: Transmit buffer empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

CHSIDE

Bit 2: Channel side.

Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received

UDR

Bit 3: Underrun flag.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

CRCERR

Bit 4: CRC error flag.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

MODF

Bit 5: Mode fault.

Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred

OVR

Bit 6: Overrun flag.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

BSY

Bit 7: Busy flag.

Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy

FRE

Bit 8: TI frame format error.

Allowed values:
0: NoError: No frame format error
1: Error: A frame format error occurred

DR

data register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR rw

Toggle fields

DR

Bits 0-15: Data register.

Allowed values: 0x0-0xffff

DR8

Direct 8-bit access to data register

Offset: 0xc, size: 8, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								DR rw

Toggle fields

DR

Bits 0-7: Data register.

Allowed values: 0x0-0xff

CRCPR

CRC polynomial register

Offset: 0x10, size: 16, reset: 0x00000007, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRCPOLY rw

Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0x0-0xffff

RXCRCR

RX CRC register

Offset: 0x14, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RxCRC r

Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

Allowed values: 0x0-0xffff

TXCRCR

TX CRC register

Offset: 0x18, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TxCRC r

Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

Allowed values: 0x0-0xffff

I2SCFGR

I2S configuration register

Offset: 0x1c, size: 16, reset: 0x00000000, access: read-write

8/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				I2SMOD rw	I2SE rw	I2SCFG rw		PCMSYNC rw		I2SSTD rw		CKPOL rw	DATLEN rw		CHLEN rw

Toggle fields

CHLEN

Bit 0: Channel length (number of bits per audio channel).

Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide

DATLEN

Bits 1-2: Data length to be transferred.

Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length

CKPOL

Bit 3: Steady state clock polarity.

Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level

I2SSTD

Bits 4-5: I2S standard selection.

Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard

PCMSYNC

Bit 7: PCM frame synchronization.

Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation

I2SCFG

Bits 8-9: I2S configuration mode.

Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive

I2SE

Bit 10: I2S Enable.

Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled

I2SMOD

Bit 11: I2S mode selection.

Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected

I2SPR

I2S prescaler register

Offset: 0x20, size: 16, reset: 0x0000000A, access: read-write

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						MCKOE rw	ODD rw	I2SDIV rw

Toggle fields

I2SDIV

Bits 0-7: I2S Linear prescaler.

Allowed values: 0x2-0xff

ODD

Bit 8: Odd factor for the prescaler.

Allowed values:
0: Even: Real divider value is I2SDIV * 2
1: Odd: Real divider value is (I2SDIV * 2) + 1

MCKOE

Bit 9: Master clock output enable.

Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled

SPI2

0x40003800: Serial peripheral interface

46/46 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0 (16-bit)	CR1	BIDIMODE	BIDIOE	CRCEN	CRCNEXT	DFF	RXONLY	SSM	SSI	LSBFIRST	SPE	BR			MSTR	CPOL	CPHA
0x4 (16-bit)	CR2									TXEIE	RXNEIE	ERRIE	FRF		SSOE	TXDMAEN	RXDMAEN
0x8 (16-bit)	SR								FRE	BSY	OVR	MODF	CRCERR	UDR	CHSIDE	TXE	RXNE
0xc (16-bit)	DR	DR
0xc (8-bit)	DR8									DR
0x10 (16-bit)	CRCPR	CRCPOLY
0x14 (16-bit)	RXCRCR	RxCRC
0x18 (16-bit)	TXCRCR	TxCRC
0x1c (16-bit)	I2SCFGR					I2SMOD	I2SE	I2SCFG		PCMSYNC		I2SSTD		CKPOL	DATLEN		CHLEN
0x20 (16-bit)	I2SPR							MCKOE	ODD	I2SDIV

Toggle registers

CR1

control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

14/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIDIMODE rw	BIDIOE rw	CRCEN rw	CRCNEXT rw	DFF rw	RXONLY rw	SSM rw	SSI rw	LSBFIRST rw	SPE rw	BR rw			MSTR rw	CPOL rw	CPHA rw

Toggle fields

CPHA

Bit 0: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 1: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

MSTR

Bit 2: Master selection.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

BR

Bits 3-5: Baud rate control.

Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256

SPE

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LSBFIRST

Bit 7: Frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SSI

Bit 8: Internal slave select.

Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored

SSM

Bit 9: Software slave management.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

RXONLY

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)

DFF

Bit 11: Data frame format.

Allowed values:
0: EightBit: 8-bit data frame format is selected for transmission/reception
1: SixteenBit: 16-bit data frame format is selected for transmission/reception

CRCNEXT

Bit 12: CRC transfer next.

Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register

CRCEN

Bit 13: Hardware CRC calculation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BIDIOE

Bit 14: Output enable in bidirectional mode.

Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)

BIDIMODE

Bit 15: Bidirectional data mode enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CR2

control register 2

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TXEIE rw	RXNEIE rw	ERRIE rw	FRF rw		SSOE rw	TXDMAEN rw	RXDMAEN rw

Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 1: Tx buffer DMA enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

SSOE

Bit 2: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

FRF

Bit 4: Frame format.

Allowed values:
0: Motorola: SPI Motorola mode
1: TI: SPI TI mode

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked

TXEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked

SR

status register

Offset: 0x8, size: 16, reset: 0x00000002, access: Unspecified

9/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							FRE r	BSY r	OVR r	MODF r	CRCERR rw	UDR r	CHSIDE r	TXE r	RXNE r

Toggle fields

RXNE

Bit 0: Receive buffer not empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXE

Bit 1: Transmit buffer empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

CHSIDE

Bit 2: Channel side.

Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received

UDR

Bit 3: Underrun flag.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

CRCERR

Bit 4: CRC error flag.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

MODF

Bit 5: Mode fault.

Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred

OVR

Bit 6: Overrun flag.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

BSY

Bit 7: Busy flag.

Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy

FRE

Bit 8: TI frame format error.

Allowed values:
0: NoError: No frame format error
1: Error: A frame format error occurred

DR

data register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR rw

Toggle fields

DR

Bits 0-15: Data register.

Allowed values: 0x0-0xffff

DR8

Direct 8-bit access to data register

Offset: 0xc, size: 8, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								DR rw

Toggle fields

DR

Bits 0-7: Data register.

Allowed values: 0x0-0xff

CRCPR

CRC polynomial register

Offset: 0x10, size: 16, reset: 0x00000007, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRCPOLY rw

Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0x0-0xffff

RXCRCR

RX CRC register

Offset: 0x14, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RxCRC r

Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

Allowed values: 0x0-0xffff

TXCRCR

TX CRC register

Offset: 0x18, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TxCRC r

Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

Allowed values: 0x0-0xffff

I2SCFGR

I2S configuration register

Offset: 0x1c, size: 16, reset: 0x00000000, access: read-write

8/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				I2SMOD rw	I2SE rw	I2SCFG rw		PCMSYNC rw		I2SSTD rw		CKPOL rw	DATLEN rw		CHLEN rw

Toggle fields

CHLEN

Bit 0: Channel length (number of bits per audio channel).

Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide

DATLEN

Bits 1-2: Data length to be transferred.

Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length

CKPOL

Bit 3: Steady state clock polarity.

Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level

I2SSTD

Bits 4-5: I2S standard selection.

Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard

PCMSYNC

Bit 7: PCM frame synchronization.

Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation

I2SCFG

Bits 8-9: I2S configuration mode.

Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive

I2SE

Bit 10: I2S Enable.

Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled

I2SMOD

Bit 11: I2S mode selection.

Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected

I2SPR

I2S prescaler register

Offset: 0x20, size: 16, reset: 0x0000000A, access: read-write

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						MCKOE rw	ODD rw	I2SDIV rw

Toggle fields

I2SDIV

Bits 0-7: I2S Linear prescaler.

Allowed values: 0x2-0xff

ODD

Bit 8: Odd factor for the prescaler.

Allowed values:
0: Even: Real divider value is I2SDIV * 2
1: Odd: Real divider value is (I2SDIV * 2) + 1

MCKOE

Bit 9: Master clock output enable.

Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled

SPI3

0x40003c00: Serial peripheral interface

46/46 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0 (16-bit)	CR1	BIDIMODE	BIDIOE	CRCEN	CRCNEXT	DFF	RXONLY	SSM	SSI	LSBFIRST	SPE	BR			MSTR	CPOL	CPHA
0x4 (16-bit)	CR2									TXEIE	RXNEIE	ERRIE	FRF		SSOE	TXDMAEN	RXDMAEN
0x8 (16-bit)	SR								FRE	BSY	OVR	MODF	CRCERR	UDR	CHSIDE	TXE	RXNE
0xc (16-bit)	DR	DR
0xc (8-bit)	DR8									DR
0x10 (16-bit)	CRCPR	CRCPOLY
0x14 (16-bit)	RXCRCR	RxCRC
0x18 (16-bit)	TXCRCR	TxCRC
0x1c (16-bit)	I2SCFGR					I2SMOD	I2SE	I2SCFG		PCMSYNC		I2SSTD		CKPOL	DATLEN		CHLEN
0x20 (16-bit)	I2SPR							MCKOE	ODD	I2SDIV

Toggle registers

CR1

control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

14/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIDIMODE rw	BIDIOE rw	CRCEN rw	CRCNEXT rw	DFF rw	RXONLY rw	SSM rw	SSI rw	LSBFIRST rw	SPE rw	BR rw			MSTR rw	CPOL rw	CPHA rw

Toggle fields

CPHA

Bit 0: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 1: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

MSTR

Bit 2: Master selection.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

BR

Bits 3-5: Baud rate control.

Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256

SPE

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LSBFIRST

Bit 7: Frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SSI

Bit 8: Internal slave select.

Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored

SSM

Bit 9: Software slave management.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

RXONLY

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)

DFF

Bit 11: Data frame format.

Allowed values:
0: EightBit: 8-bit data frame format is selected for transmission/reception
1: SixteenBit: 16-bit data frame format is selected for transmission/reception

CRCNEXT

Bit 12: CRC transfer next.

Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register

CRCEN

Bit 13: Hardware CRC calculation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BIDIOE

Bit 14: Output enable in bidirectional mode.

Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)

BIDIMODE

Bit 15: Bidirectional data mode enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CR2

control register 2

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TXEIE rw	RXNEIE rw	ERRIE rw	FRF rw		SSOE rw	TXDMAEN rw	RXDMAEN rw

Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 1: Tx buffer DMA enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

SSOE

Bit 2: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

FRF

Bit 4: Frame format.

Allowed values:
0: Motorola: SPI Motorola mode
1: TI: SPI TI mode

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked

TXEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked

SR

status register

Offset: 0x8, size: 16, reset: 0x00000002, access: Unspecified

9/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							FRE r	BSY r	OVR r	MODF r	CRCERR rw	UDR r	CHSIDE r	TXE r	RXNE r

Toggle fields

RXNE

Bit 0: Receive buffer not empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXE

Bit 1: Transmit buffer empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

CHSIDE

Bit 2: Channel side.

Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received

UDR

Bit 3: Underrun flag.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

CRCERR

Bit 4: CRC error flag.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

MODF

Bit 5: Mode fault.

Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred

OVR

Bit 6: Overrun flag.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

BSY

Bit 7: Busy flag.

Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy

FRE

Bit 8: TI frame format error.

Allowed values:
0: NoError: No frame format error
1: Error: A frame format error occurred

DR

data register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR rw

Toggle fields

DR

Bits 0-15: Data register.

Allowed values: 0x0-0xffff

DR8

Direct 8-bit access to data register

Offset: 0xc, size: 8, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								DR rw

Toggle fields

DR

Bits 0-7: Data register.

Allowed values: 0x0-0xff

CRCPR

CRC polynomial register

Offset: 0x10, size: 16, reset: 0x00000007, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRCPOLY rw

Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0x0-0xffff

RXCRCR

RX CRC register

Offset: 0x14, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RxCRC r

Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

Allowed values: 0x0-0xffff

TXCRCR

TX CRC register

Offset: 0x18, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TxCRC r

Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

Allowed values: 0x0-0xffff

I2SCFGR

I2S configuration register

Offset: 0x1c, size: 16, reset: 0x00000000, access: read-write

8/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				I2SMOD rw	I2SE rw	I2SCFG rw		PCMSYNC rw		I2SSTD rw		CKPOL rw	DATLEN rw		CHLEN rw

Toggle fields

CHLEN

Bit 0: Channel length (number of bits per audio channel).

Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide

DATLEN

Bits 1-2: Data length to be transferred.

Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length

CKPOL

Bit 3: Steady state clock polarity.

Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level

I2SSTD

Bits 4-5: I2S standard selection.

Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard

PCMSYNC

Bit 7: PCM frame synchronization.

Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation

I2SCFG

Bits 8-9: I2S configuration mode.

Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive

I2SE

Bit 10: I2S Enable.

Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled

I2SMOD

Bit 11: I2S mode selection.

Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected

I2SPR

I2S prescaler register

Offset: 0x20, size: 16, reset: 0x0000000A, access: read-write

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						MCKOE rw	ODD rw	I2SDIV rw

Toggle fields

I2SDIV

Bits 0-7: I2S Linear prescaler.

Allowed values: 0x2-0xff

ODD

Bit 8: Odd factor for the prescaler.

Allowed values:
0: Even: Real divider value is I2SDIV * 2
1: Odd: Real divider value is (I2SDIV * 2) + 1

MCKOE

Bit 9: Master clock output enable.

Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled

SPI4

0x40013400: Serial peripheral interface

46/46 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0 (16-bit)	CR1	BIDIMODE	BIDIOE	CRCEN	CRCNEXT	DFF	RXONLY	SSM	SSI	LSBFIRST	SPE	BR			MSTR	CPOL	CPHA
0x4 (16-bit)	CR2									TXEIE	RXNEIE	ERRIE	FRF		SSOE	TXDMAEN	RXDMAEN
0x8 (16-bit)	SR								FRE	BSY	OVR	MODF	CRCERR	UDR	CHSIDE	TXE	RXNE
0xc (16-bit)	DR	DR
0xc (8-bit)	DR8									DR
0x10 (16-bit)	CRCPR	CRCPOLY
0x14 (16-bit)	RXCRCR	RxCRC
0x18 (16-bit)	TXCRCR	TxCRC
0x1c (16-bit)	I2SCFGR					I2SMOD	I2SE	I2SCFG		PCMSYNC		I2SSTD		CKPOL	DATLEN		CHLEN
0x20 (16-bit)	I2SPR							MCKOE	ODD	I2SDIV

Toggle registers

CR1

control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

14/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIDIMODE rw	BIDIOE rw	CRCEN rw	CRCNEXT rw	DFF rw	RXONLY rw	SSM rw	SSI rw	LSBFIRST rw	SPE rw	BR rw			MSTR rw	CPOL rw	CPHA rw

Toggle fields

CPHA

Bit 0: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 1: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

MSTR

Bit 2: Master selection.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

BR

Bits 3-5: Baud rate control.

Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256

SPE

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LSBFIRST

Bit 7: Frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SSI

Bit 8: Internal slave select.

Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored

SSM

Bit 9: Software slave management.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

RXONLY

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)

DFF

Bit 11: Data frame format.

Allowed values:
0: EightBit: 8-bit data frame format is selected for transmission/reception
1: SixteenBit: 16-bit data frame format is selected for transmission/reception

CRCNEXT

Bit 12: CRC transfer next.

Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register

CRCEN

Bit 13: Hardware CRC calculation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BIDIOE

Bit 14: Output enable in bidirectional mode.

Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)

BIDIMODE

Bit 15: Bidirectional data mode enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CR2

control register 2

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TXEIE rw	RXNEIE rw	ERRIE rw	FRF rw		SSOE rw	TXDMAEN rw	RXDMAEN rw

Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 1: Tx buffer DMA enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

SSOE

Bit 2: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

FRF

Bit 4: Frame format.

Allowed values:
0: Motorola: SPI Motorola mode
1: TI: SPI TI mode

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked

TXEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked

SR

status register

Offset: 0x8, size: 16, reset: 0x00000002, access: Unspecified

9/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							FRE r	BSY r	OVR r	MODF r	CRCERR rw	UDR r	CHSIDE r	TXE r	RXNE r

Toggle fields

RXNE

Bit 0: Receive buffer not empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXE

Bit 1: Transmit buffer empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

CHSIDE

Bit 2: Channel side.

Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received

UDR

Bit 3: Underrun flag.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

CRCERR

Bit 4: CRC error flag.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

MODF

Bit 5: Mode fault.

Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred

OVR

Bit 6: Overrun flag.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

BSY

Bit 7: Busy flag.

Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy

FRE

Bit 8: TI frame format error.

Allowed values:
0: NoError: No frame format error
1: Error: A frame format error occurred

DR

data register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR rw

Toggle fields

DR

Bits 0-15: Data register.

Allowed values: 0x0-0xffff

DR8

Direct 8-bit access to data register

Offset: 0xc, size: 8, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								DR rw

Toggle fields

DR

Bits 0-7: Data register.

Allowed values: 0x0-0xff

CRCPR

CRC polynomial register

Offset: 0x10, size: 16, reset: 0x00000007, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRCPOLY rw

Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0x0-0xffff

RXCRCR

RX CRC register

Offset: 0x14, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RxCRC r

Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

Allowed values: 0x0-0xffff

TXCRCR

TX CRC register

Offset: 0x18, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TxCRC r

Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

Allowed values: 0x0-0xffff

I2SCFGR

I2S configuration register

Offset: 0x1c, size: 16, reset: 0x00000000, access: read-write

8/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				I2SMOD rw	I2SE rw	I2SCFG rw		PCMSYNC rw		I2SSTD rw		CKPOL rw	DATLEN rw		CHLEN rw

Toggle fields

CHLEN

Bit 0: Channel length (number of bits per audio channel).

Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide

DATLEN

Bits 1-2: Data length to be transferred.

Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length

CKPOL

Bit 3: Steady state clock polarity.

Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level

I2SSTD

Bits 4-5: I2S standard selection.

Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard

PCMSYNC

Bit 7: PCM frame synchronization.

Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation

I2SCFG

Bits 8-9: I2S configuration mode.

Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive

I2SE

Bit 10: I2S Enable.

Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled

I2SMOD

Bit 11: I2S mode selection.

Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected

I2SPR

I2S prescaler register

Offset: 0x20, size: 16, reset: 0x0000000A, access: read-write

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						MCKOE rw	ODD rw	I2SDIV rw

Toggle fields

I2SDIV

Bits 0-7: I2S Linear prescaler.

Allowed values: 0x2-0xff

ODD

Bit 8: Odd factor for the prescaler.

Allowed values:
0: Even: Real divider value is I2SDIV * 2
1: Odd: Real divider value is (I2SDIV * 2) + 1

MCKOE

Bit 9: Master clock output enable.

Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled

SPI5

0x40015000: Serial peripheral interface

46/46 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0 (16-bit)	CR1	BIDIMODE	BIDIOE	CRCEN	CRCNEXT	DFF	RXONLY	SSM	SSI	LSBFIRST	SPE	BR			MSTR	CPOL	CPHA
0x4 (16-bit)	CR2									TXEIE	RXNEIE	ERRIE	FRF		SSOE	TXDMAEN	RXDMAEN
0x8 (16-bit)	SR								FRE	BSY	OVR	MODF	CRCERR	UDR	CHSIDE	TXE	RXNE
0xc (16-bit)	DR	DR
0xc (8-bit)	DR8									DR
0x10 (16-bit)	CRCPR	CRCPOLY
0x14 (16-bit)	RXCRCR	RxCRC
0x18 (16-bit)	TXCRCR	TxCRC
0x1c (16-bit)	I2SCFGR					I2SMOD	I2SE	I2SCFG		PCMSYNC		I2SSTD		CKPOL	DATLEN		CHLEN
0x20 (16-bit)	I2SPR							MCKOE	ODD	I2SDIV

Toggle registers

CR1

control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

14/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIDIMODE rw	BIDIOE rw	CRCEN rw	CRCNEXT rw	DFF rw	RXONLY rw	SSM rw	SSI rw	LSBFIRST rw	SPE rw	BR rw			MSTR rw	CPOL rw	CPHA rw

Toggle fields

CPHA

Bit 0: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 1: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

MSTR

Bit 2: Master selection.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

BR

Bits 3-5: Baud rate control.

Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256

SPE

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LSBFIRST

Bit 7: Frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SSI

Bit 8: Internal slave select.

Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored

SSM

Bit 9: Software slave management.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

RXONLY

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)

DFF

Bit 11: Data frame format.

Allowed values:
0: EightBit: 8-bit data frame format is selected for transmission/reception
1: SixteenBit: 16-bit data frame format is selected for transmission/reception

CRCNEXT

Bit 12: CRC transfer next.

Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register

CRCEN

Bit 13: Hardware CRC calculation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BIDIOE

Bit 14: Output enable in bidirectional mode.

Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)

BIDIMODE

Bit 15: Bidirectional data mode enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CR2

control register 2

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TXEIE rw	RXNEIE rw	ERRIE rw	FRF rw		SSOE rw	TXDMAEN rw	RXDMAEN rw

Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 1: Tx buffer DMA enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

SSOE

Bit 2: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

FRF

Bit 4: Frame format.

Allowed values:
0: Motorola: SPI Motorola mode
1: TI: SPI TI mode

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked

TXEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked

SR

status register

Offset: 0x8, size: 16, reset: 0x00000002, access: Unspecified

9/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							FRE r	BSY r	OVR r	MODF r	CRCERR rw	UDR r	CHSIDE r	TXE r	RXNE r

Toggle fields

RXNE

Bit 0: Receive buffer not empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXE

Bit 1: Transmit buffer empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

CHSIDE

Bit 2: Channel side.

Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received

UDR

Bit 3: Underrun flag.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

CRCERR

Bit 4: CRC error flag.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

MODF

Bit 5: Mode fault.

Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred

OVR

Bit 6: Overrun flag.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

BSY

Bit 7: Busy flag.

Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy

FRE

Bit 8: TI frame format error.

Allowed values:
0: NoError: No frame format error
1: Error: A frame format error occurred

DR

data register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR rw

Toggle fields

DR

Bits 0-15: Data register.

Allowed values: 0x0-0xffff

DR8

Direct 8-bit access to data register

Offset: 0xc, size: 8, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								DR rw

Toggle fields

DR

Bits 0-7: Data register.

Allowed values: 0x0-0xff

CRCPR

CRC polynomial register

Offset: 0x10, size: 16, reset: 0x00000007, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRCPOLY rw

Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0x0-0xffff

RXCRCR

RX CRC register

Offset: 0x14, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RxCRC r

Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

Allowed values: 0x0-0xffff

TXCRCR

TX CRC register

Offset: 0x18, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TxCRC r

Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

Allowed values: 0x0-0xffff

I2SCFGR

I2S configuration register

Offset: 0x1c, size: 16, reset: 0x00000000, access: read-write

8/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				I2SMOD rw	I2SE rw	I2SCFG rw		PCMSYNC rw		I2SSTD rw		CKPOL rw	DATLEN rw		CHLEN rw

Toggle fields

CHLEN

Bit 0: Channel length (number of bits per audio channel).

Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide

DATLEN

Bits 1-2: Data length to be transferred.

Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length

CKPOL

Bit 3: Steady state clock polarity.

Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level

I2SSTD

Bits 4-5: I2S standard selection.

Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard

PCMSYNC

Bit 7: PCM frame synchronization.

Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation

I2SCFG

Bits 8-9: I2S configuration mode.

Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive

I2SE

Bit 10: I2S Enable.

Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled

I2SMOD

Bit 11: I2S mode selection.

Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected

I2SPR

I2S prescaler register

Offset: 0x20, size: 16, reset: 0x0000000A, access: read-write

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						MCKOE rw	ODD rw	I2SDIV rw

Toggle fields

I2SDIV

Bits 0-7: I2S Linear prescaler.

Allowed values: 0x2-0xff

ODD

Bit 8: Odd factor for the prescaler.

Allowed values:
0: Even: Real divider value is I2SDIV * 2
1: Odd: Real divider value is (I2SDIV * 2) + 1

MCKOE

Bit 9: Master clock output enable.

Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled

STK

0xe000e010: SysTick timer

0/9 fields covered.

Toggle register map

Offset	Name	31	30	23	16	15	2	1	0
0x0	CTRL				COUNTFLAG		CLKSOURCE	TICKINT	ENABLE
0x4	LOAD			RELOAD		RELOAD
0x8	VAL			CURRENT		CURRENT
0xc	CALIB	NOREF	SKEW	TENMS		TENMS

Toggle registers

CTRL

SysTick control and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															COUNTFLAG rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													CLKSOURCE rw	TICKINT rw	ENABLE rw

Toggle fields

ENABLE

Bit 0: Counter enable.

TICKINT

Bit 1: SysTick exception request enable.

CLKSOURCE

Bit 2: Clock source selection.

COUNTFLAG

Bit 16: COUNTFLAG.

LOAD

SysTick reload value register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								RELOAD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RELOAD rw

Toggle fields

RELOAD

Bits 0-23: RELOAD value.

VAL

SysTick current value register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								CURRENT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CURRENT rw

Toggle fields

CURRENT

Bits 0-23: Current counter value.

CALIB

SysTick calibration value register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
NOREF rw	SKEW rw							TENMS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TENMS rw

Toggle fields

TENMS

Bits 0-23: Calibration value.

SKEW

Bit 30: SKEW flag: Indicates whether the TENMS value is exact.

NOREF

Bit 31: NOREF flag. Reads as zero.

SYSCFG

0x40013800: System configuration controller

2/20 fields covered.

Toggle register map

Offset	Name	16	15	11	8	7	3	1	0
0x0	MEMRM							MEM_MODE
0x4	PMC	ADC1DC2
0x8	EXTICR1		EXTI3	EXTI2		EXTI1	EXTI0
0xc	EXTICR2		EXTI7	EXTI6		EXTI5	EXTI4
0x10	EXTICR3		EXTI11	EXTI10		EXTI9	EXTI8
0x14	EXTICR4		EXTI15	EXTI14		EXTI13	EXTI12
0x20	CMPCR				READY				CMP_PD

Toggle registers

MEMRM

memory remap register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														MEM_MODE rw

Toggle fields

MEM_MODE

Bits 0-1: MEM_MODE.

PMC

peripheral mode configuration register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															ADC1DC2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle fields

ADC1DC2

Bit 16: ADC1DC2.

EXTICR1

external interrupt configuration register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EXTI3 rw				EXTI2 rw				EXTI1 rw				EXTI0 rw

Toggle fields

EXTI0

Bits 0-3: EXTI x configuration (x = 0 to 3).

EXTI1

Bits 4-7: EXTI x configuration (x = 0 to 3).

EXTI2

Bits 8-11: EXTI x configuration (x = 0 to 3).

EXTI3

Bits 12-15: EXTI x configuration (x = 0 to 3).

EXTICR2

external interrupt configuration register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EXTI7 rw				EXTI6 rw				EXTI5 rw				EXTI4 rw

Toggle fields

EXTI4

Bits 0-3: EXTI x configuration (x = 4 to 7).

EXTI5

Bits 4-7: EXTI x configuration (x = 4 to 7).

EXTI6

Bits 8-11: EXTI x configuration (x = 4 to 7).

EXTI7

Bits 12-15: EXTI x configuration (x = 4 to 7).

EXTICR3

external interrupt configuration register 3

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EXTI11 rw				EXTI10 rw				EXTI9 rw				EXTI8 rw

Toggle fields

EXTI8

Bits 0-3: EXTI x configuration (x = 8 to 11).

EXTI9

Bits 4-7: EXTI x configuration (x = 8 to 11).

EXTI10

Bits 8-11: EXTI10.

EXTI11

Bits 12-15: EXTI x configuration (x = 8 to 11).

EXTICR4

external interrupt configuration register 4

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EXTI15 rw				EXTI14 rw				EXTI13 rw				EXTI12 rw

Toggle fields

EXTI12

Bits 0-3: EXTI x configuration (x = 12 to 15).

EXTI13

Bits 4-7: EXTI x configuration (x = 12 to 15).

EXTI14

Bits 8-11: EXTI x configuration (x = 12 to 15).

EXTI15

Bits 12-15: EXTI x configuration (x = 12 to 15).

CMPCR

Compensation cell control register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							READY r								CMP_PD r

Toggle fields

CMP_PD

Bit 0: Compensation cell power-down.

READY

Bit 8: READY.

TIM1

0x40010000: Advanced-timers

92/127 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1							CKD		ARPE	CMS		DIR	OPM	URS	UDIS	CEN
0x4	CR2		OIS[4]	OIS[3]N	OIS[3]	OIS[2]N	OIS[2]	OIS[1]N	OIS[1]	TI1S	MMS			CCDS	CCUS		CCPC
0x8	SMCR	ETP	ECE	ETPS		ETF				MSM	TS				SMS
0xc	DIER		TDE	COMDE	CC[4]DE	CC[3]DE	CC[2]DE	CC[1]DE	UDE	BIE	TIE	COMIE	CC[4]IE	CC[3]IE	CC[2]IE	CC[1]IE	UIE
0x10	SR				CC[4]OF	CC[3]OF	CC[2]OF	CC[1]OF		BIF	TIF	COMIF	CC[4]IF	CC[3]IF	CC[2]IF	CC[1]IF	UIF
0x14	EGR									BG	TG	COMG	CC[4]G	CC[3]G	CC[2]G	CC[1]G	UG
0x18	CCMR1_Input	IC[2]F				IC[2]PSC		CC[2]S		IC[1]F				IC[1]PSC		CC[1]S
0x18	CCMR1_Output	OC[2]CE	OC[2]M			OC[2]PE	OC[2]FE	CC[2]S		OC[1]CE	OC[1]M			OC[1]PE	OC[1]FE	CC[1]S
0x1c	CCMR2_Input	IC[4]F				IC[4]PSC		CC[4]S		IC[3]F				IC[3]PSC		CC[3]S
0x1c	CCMR2_Output	OC[4]CE	OC[4]M			OC[4]PE	OC[4]FE	CC[4]S		OC[3]CE	OC[3]M			OC[3]PE	OC[3]FE	CC[3]S
0x20	CCER			CC[4]P	CC[4]E	CC[3]NP	CC[3]NE	CC[3]P	CC[3]E	CC[2]NP	CC[2]NE	CC[2]P	CC[2]E	CC[1]NP	CC[1]NE	CC[1]P	CC[1]E
0x24	CNT	CNT
0x28	PSC	PSC
0x2c	ARR	ARR
0x30	RCR									REP
0x34	CCR[1]	CCR
0x38	CCR[2]	CCR
0x3c	CCR[3]	CCR
0x40	CCR[4]	CCR
0x44	BDTR	MOE	AOE	BKP	BKE	OSSR	OSSI	LOCK		DTG
0x48	DCR				DBL								DBA
0x4c	DMAR	DMAB

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CKD rw		ARPE rw	CMS rw		DIR rw	OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

10/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	OIS[4] rw	OIS[3]N rw	OIS[3] rw	OIS[2]N rw	OIS[2] rw	OIS[1]N rw	OIS[1] rw	TI1S rw	MMS rw			CCDS rw	CCUS rw		CCPC rw

Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

OIS[1]

Bit 8: Output Idle state (OC1 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[1]N

Bit 9: Output Idle state (OC1N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[2]

Bit 10: Output Idle state (OC2 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[2]N

Bit 11: Output Idle state (OC2N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[3]

Bit 12: Output Idle state (OC3 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[3]N

Bit 13: Output Idle state (OC3N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[4]

Bit 14: Output Idle state (OC4 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETP rw	ECE rw	ETPS rw		ETF rw				MSM rw	TS rw				SMS rw

Toggle fields

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

12/15 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDE rw	COMDE rw	CC[4]DE rw	CC[3]DE rw	CC[2]DE rw	CC[1]DE rw	UDE rw	BIE rw	TIE rw	COMIE rw	CC[4]IE rw	CC[3]IE rw	CC[2]IE rw	CC[1]IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

COMIE

Bit 5: COM interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CC[4]OF rw	CC[3]OF rw	CC[2]OF rw	CC[1]OF rw		BIF rw	TIF rw	COMIF rw	CC[4]IF rw	CC[3]IF rw	CC[2]IF rw	CC[1]IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

BIF

Bit 7: Break interrupt flag.

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

6/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								BG w	TG w	COMG w	CC[4]G w	CC[3]G w	CC[2]G w	CC[1]G w	UG w

Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC[2]F rw				IC[2]PSC rw		CC[2]S rw		IC[1]F rw				IC[1]PSC rw		CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC[2]CE rw	OC[2]M rw			OC[2]PE rw	OC[2]FE rw	CC[2]S rw		OC[1]CE rw	OC[1]M rw			OC[1]PE rw	OC[1]FE rw	CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC[4]F rw				IC[4]PSC rw		CC[4]S rw		IC[3]F rw				IC[3]PSC rw		CC[3]S rw

Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0x0-0x3

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values: 0x0-0xf

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0x0-0x3

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values: 0x0-0xf

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC[4]CE rw	OC[4]M rw			OC[4]PE rw	OC[4]FE rw	CC[4]S rw		OC[3]CE rw	OC[3]M rw			OC[3]PE rw	OC[3]FE rw	CC[3]S rw

Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CC[4]P rw	CC[4]E rw	CC[3]NP rw	CC[3]NE rw	CC[3]P rw	CC[3]E rw	CC[2]NP rw	CC[2]NE rw	CC[2]P rw	CC[2]E rw	CC[1]NP rw	CC[1]NE rw	CC[1]P rw	CC[1]E rw

Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[1]NE

Bit 2: Capture/Compare 1 complementary output enable.

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

CC[2]NE

Bit 6: Capture/Compare 2 complementary output enable.

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CC[3]E

Bit 8: Capture/Compare 3 output enable.

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

CC[3]NE

Bit 10: Capture/Compare 3 complementary output enable.

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

CC[4]E

Bit 12: Capture/Compare 4 output enable.

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle fields

CNT

Bits 0-15: counter value.

Allowed values: 0x0-0xffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REP rw

Toggle fields

REP

Bits 0-7: Repetition counter value.

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MOE rw	AOE rw	BKP rw	BKE rw	OSSR rw	OSSI rw	LOCK rw		DTG rw

Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

Allowed values: 0x0-0xff

LOCK

Bits 8-9: Lock configuration.

Allowed values:
0: Off: No bit is write protected
1: Level1: Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
2: Level2: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
3: Level3: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written

OSSI

Bit 10: Off-state selection for Idle mode.

Allowed values:
0: Disabled: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are forced to idle level

OSSR

Bit 11: Off-state selection for Run mode.

Allowed values:
0: Disabled: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are enabled with their inactive level

BKE

Bit 12: Break enable.

Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x disabled

BKP

Bit 13: Break polarity.

Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high

AOE

Bit 14: Automatic output enable.

Allowed values:
0: Manual: MOE can be set only by software
1: Automatic: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)

MOE

Bit 15: Main output enable.

Allowed values:
0: DisabledIdle: OC/OCN are disabled or forced idle depending on OSSI
1: Enabled: OC/OCN are enabled if CCxE/CCxNE are set

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

TIM10

0x40014400: General-purpose-timers

11/27 fields covered.

Toggle register map

Offset	Name	15	9	7	6	3	2	1	0
0x0	CR1		CKD	ARPE		OPM	URS	UDIS	CEN
0xc	DIER							CC[1]IE	UIE
0x10	SR		CC[1]OF					CC[1]IF	UIF
0x14	EGR							CC[1]G	UG
0x18	CCMR1_Input			IC[1]F		IC[1]PSC		CC[1]S
0x18	CCMR1_Output				OC[1]M	OC[1]PE	OC[1]FE	CC[1]S
0x20	CCER					CC[1]NP		CC[1]P	CC[1]E
0x24	CNT	CNT
0x28	PSC	PSC
0x2c	ARR	ARR
0x34	CCR[1]	CCR

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CKD rw		ARPE rw				OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CC[1]IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC[1]OF rw								CC[1]IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

1/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CC[1]G w	UG w

Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IC[1]F rw				IC[1]PSC rw		CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OC[1]M rw			OC[1]PE rw	OC[1]FE rw	CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												CC[1]NP rw		CC[1]P rw	CC[1]E rw

Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle fields

CNT

Bits 0-15: counter value.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-15: Auto-reload value.

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

TIM11

0x40014800: General-purpose-timers

11/28 fields covered.

Toggle register map

Offset	Name	15	9	7	6	3	2	1	0
0x0	CR1		CKD	ARPE		OPM	URS	UDIS	CEN
0xc	DIER							CC[1]IE	UIE
0x10	SR		CC[1]OF					CC[1]IF	UIF
0x14	EGR							CC[1]G	UG
0x18	CCMR1_Input			IC[1]F		IC[1]PSC		CC[1]S
0x18	CCMR1_Output				OC[1]M	OC[1]PE	OC[1]FE	CC[1]S
0x20	CCER					CC[1]NP		CC[1]P	CC[1]E
0x24	CNT	CNT
0x28	PSC	PSC
0x2c	ARR	ARR
0x34	CCR[1]	CCR
0x50	OR							RMP

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CKD rw		ARPE rw				OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CC[1]IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC[1]OF rw								CC[1]IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

1/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														CC[1]G w	UG w

Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IC[1]F rw				IC[1]PSC rw		CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OC[1]M rw			OC[1]PE rw	OC[1]FE rw	CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												CC[1]NP rw		CC[1]P rw	CC[1]E rw

Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle fields

CNT

Bits 0-15: counter value.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-15: Auto-reload value.

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

OR

option register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														RMP rw

Toggle fields

RMP

Bits 0-1: Input 1 remapping capability.

TIM2

0x40000000: General purpose timers

77/101 fields covered.

Toggle register map

Offset	Name	31	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1								CKD		ARPE	CMS		DIR	OPM	URS	UDIS	CEN
0x4	CR2										TI1S	MMS			CCDS
0x8	SMCR		ETP	ECE	ETPS		ETF				MSM	TS				SMS
0xc	DIER			TDE		CC[4]DE	CC[3]DE	CC[2]DE	CC[1]DE	UDE		TIE		CC[4]IE	CC[3]IE	CC[2]IE	CC[1]IE	UIE
0x10	SR					CC[4]OF	CC[3]OF	CC[2]OF	CC[1]OF			TIF		CC[4]IF	CC[3]IF	CC[2]IF	CC[1]IF	UIF
0x14	EGR											TG		CC[4]G	CC[3]G	CC[2]G	CC[1]G	UG
0x18	CCMR1_Input		IC[2]F				IC[2]PSC		CC[2]S		IC[1]F				IC[1]PSC		CC[1]S
0x18	CCMR1_Output		OC[2]CE	OC[2]M			OC[2]PE	OC[2]FE	CC[2]S		OC[1]CE	OC[1]M			OC[1]PE	OC[1]FE	CC[1]S
0x1c	CCMR2_Input		IC[4]F				IC[4]PSC		CC[4]S		IC[3]F				IC[3]PSC		CC[3]S
0x1c	CCMR2_Output		OC[4]CE	OC[4]M			OC[4]PE	OC[4]FE	CC[4]S		OC[3]CE	OC[3]M			OC[3]PE	OC[3]FE	CC[3]S
0x20	CCER		CC[4]NP		CC[4]P	CC[4]E	CC[3]NP		CC[3]P	CC[3]E	CC[2]NP		CC[2]P	CC[2]E	CC[1]NP		CC[1]P	CC[1]E
0x24	CNT	CNT	CNT
0x28	PSC		PSC
0x2c	ARR	ARR	ARR
0x34	CCR[1]	CCR	CCR
0x38	CCR[2]	CCR	CCR
0x3c	CCR[3]	CCR	CCR
0x40	CCR[4]	CCR	CCR
0x48	DCR					DBL								DBA
0x4c	DMAR		DMAB
0x50	OR						ITR1_RMP

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CKD rw		ARPE rw	CMS rw		DIR rw	OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TI1S rw	MMS rw			CCDS rw

Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETP rw	ECE rw	ETPS rw		ETF rw				MSM rw	TS rw				SMS rw

Toggle fields

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDE rw		CC[4]DE rw	CC[3]DE rw	CC[2]DE rw	CC[1]DE rw	UDE rw		TIE rw		CC[4]IE rw	CC[3]IE rw	CC[2]IE rw	CC[1]IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CC[4]OF rw	CC[3]OF rw	CC[2]OF rw	CC[1]OF rw			TIF rw		CC[4]IF rw	CC[3]IF rw	CC[2]IF rw	CC[1]IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									TG w		CC[4]G w	CC[3]G w	CC[2]G w	CC[1]G w	UG w

Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC[2]F rw				IC[2]PSC rw		CC[2]S rw		IC[1]F rw				IC[1]PSC rw		CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC[2]CE rw	OC[2]M rw			OC[2]PE rw	OC[2]FE rw	CC[2]S rw		OC[1]CE rw	OC[1]M rw			OC[1]PE rw	OC[1]FE rw	CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC[4]F rw				IC[4]PSC rw		CC[4]S rw		IC[3]F rw				IC[3]PSC rw		CC[3]S rw

Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0x0-0x3

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values: 0x0-0xf

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0x0-0x3

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values: 0x0-0xf

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC[4]CE rw	OC[4]M rw			OC[4]PE rw	OC[4]FE rw	CC[4]S rw		OC[3]CE rw	OC[3]M rw			OC[3]PE rw	OC[3]FE rw	CC[3]S rw

Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CC[4]NP rw		CC[4]P rw	CC[4]E rw	CC[3]NP rw		CC[3]P rw	CC[3]E rw	CC[2]NP rw		CC[2]P rw	CC[2]E rw	CC[1]NP rw		CC[1]P rw	CC[1]E rw

Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CC[3]E

Bit 8: Capture/Compare 3 output enable.

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

CC[4]E

Bit 12: Capture/Compare 4 output enable.

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

CC[4]NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CNT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle fields

CNT

Bits 0-31: Counter value.

Allowed values: 0x0-0xffffffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ARR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-31: Auto-reload value.

Allowed values: 0x0-0xffffffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

OR

TIM5 option register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				ITR1_RMP rw

Toggle fields

ITR1_RMP

Bits 10-11: Timer Input 4 remap.

TIM3

0x40000400: General purpose timers

77/100 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1							CKD		ARPE	CMS		DIR	OPM	URS	UDIS	CEN
0x4	CR2									TI1S	MMS			CCDS
0x8	SMCR	ETP	ECE	ETPS		ETF				MSM	TS				SMS
0xc	DIER		TDE		CC[4]DE	CC[3]DE	CC[2]DE	CC[1]DE	UDE		TIE		CC[4]IE	CC[3]IE	CC[2]IE	CC[1]IE	UIE
0x10	SR				CC[4]OF	CC[3]OF	CC[2]OF	CC[1]OF			TIF		CC[4]IF	CC[3]IF	CC[2]IF	CC[1]IF	UIF
0x14	EGR										TG		CC[4]G	CC[3]G	CC[2]G	CC[1]G	UG
0x18	CCMR1_Input	IC[2]F				IC[2]PSC		CC[2]S		IC[1]F				IC[1]PSC		CC[1]S
0x18	CCMR1_Output	OC[2]CE	OC[2]M			OC[2]PE	OC[2]FE	CC[2]S		OC[1]CE	OC[1]M			OC[1]PE	OC[1]FE	CC[1]S
0x1c	CCMR2_Input	IC[4]F				IC[4]PSC		CC[4]S		IC[3]F				IC[3]PSC		CC[3]S
0x1c	CCMR2_Output	OC[4]CE	OC[4]M			OC[4]PE	OC[4]FE	CC[4]S		OC[3]CE	OC[3]M			OC[3]PE	OC[3]FE	CC[3]S
0x20	CCER	CC[4]NP		CC[4]P	CC[4]E	CC[3]NP		CC[3]P	CC[3]E	CC[2]NP		CC[2]P	CC[2]E	CC[1]NP		CC[1]P	CC[1]E
0x24	CNT	CNT
0x28	PSC	PSC
0x2c	ARR	ARR
0x34	CCR[1]	CCR
0x38	CCR[2]	CCR
0x3c	CCR[3]	CCR
0x40	CCR[4]	CCR
0x48	DCR				DBL								DBA
0x4c	DMAR	DMAB

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CKD rw		ARPE rw	CMS rw		DIR rw	OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TI1S rw	MMS rw			CCDS rw

Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETP rw	ECE rw	ETPS rw		ETF rw				MSM rw	TS rw				SMS rw

Toggle fields

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDE rw		CC[4]DE rw	CC[3]DE rw	CC[2]DE rw	CC[1]DE rw	UDE rw		TIE rw		CC[4]IE rw	CC[3]IE rw	CC[2]IE rw	CC[1]IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CC[4]OF rw	CC[3]OF rw	CC[2]OF rw	CC[1]OF rw			TIF rw		CC[4]IF rw	CC[3]IF rw	CC[2]IF rw	CC[1]IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									TG w		CC[4]G w	CC[3]G w	CC[2]G w	CC[1]G w	UG w

Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC[2]F rw				IC[2]PSC rw		CC[2]S rw		IC[1]F rw				IC[1]PSC rw		CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC[2]CE rw	OC[2]M rw			OC[2]PE rw	OC[2]FE rw	CC[2]S rw		OC[1]CE rw	OC[1]M rw			OC[1]PE rw	OC[1]FE rw	CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC[4]F rw				IC[4]PSC rw		CC[4]S rw		IC[3]F rw				IC[3]PSC rw		CC[3]S rw

Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0x0-0x3

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values: 0x0-0xf

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0x0-0x3

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values: 0x0-0xf

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC[4]CE rw	OC[4]M rw			OC[4]PE rw	OC[4]FE rw	CC[4]S rw		OC[3]CE rw	OC[3]M rw			OC[3]PE rw	OC[3]FE rw	CC[3]S rw

Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CC[4]NP rw		CC[4]P rw	CC[4]E rw	CC[3]NP rw		CC[3]P rw	CC[3]E rw	CC[2]NP rw		CC[2]P rw	CC[2]E rw	CC[1]NP rw		CC[1]P rw	CC[1]E rw

Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CC[3]E

Bit 8: Capture/Compare 3 output enable.

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

CC[4]E

Bit 12: Capture/Compare 4 output enable.

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

CC[4]NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle fields

CNT

Bits 0-15: Counter value.

Allowed values: 0x0-0xffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

TIM4

0x40000800: General purpose timers

77/100 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1							CKD		ARPE	CMS		DIR	OPM	URS	UDIS	CEN
0x4	CR2									TI1S	MMS			CCDS
0x8	SMCR	ETP	ECE	ETPS		ETF				MSM	TS				SMS
0xc	DIER		TDE		CC[4]DE	CC[3]DE	CC[2]DE	CC[1]DE	UDE		TIE		CC[4]IE	CC[3]IE	CC[2]IE	CC[1]IE	UIE
0x10	SR				CC[4]OF	CC[3]OF	CC[2]OF	CC[1]OF			TIF		CC[4]IF	CC[3]IF	CC[2]IF	CC[1]IF	UIF
0x14	EGR										TG		CC[4]G	CC[3]G	CC[2]G	CC[1]G	UG
0x18	CCMR1_Input	IC[2]F				IC[2]PSC		CC[2]S		IC[1]F				IC[1]PSC		CC[1]S
0x18	CCMR1_Output	OC[2]CE	OC[2]M			OC[2]PE	OC[2]FE	CC[2]S		OC[1]CE	OC[1]M			OC[1]PE	OC[1]FE	CC[1]S
0x1c	CCMR2_Input	IC[4]F				IC[4]PSC		CC[4]S		IC[3]F				IC[3]PSC		CC[3]S
0x1c	CCMR2_Output	OC[4]CE	OC[4]M			OC[4]PE	OC[4]FE	CC[4]S		OC[3]CE	OC[3]M			OC[3]PE	OC[3]FE	CC[3]S
0x20	CCER	CC[4]NP		CC[4]P	CC[4]E	CC[3]NP		CC[3]P	CC[3]E	CC[2]NP		CC[2]P	CC[2]E	CC[1]NP		CC[1]P	CC[1]E
0x24	CNT	CNT
0x28	PSC	PSC
0x2c	ARR	ARR
0x34	CCR[1]	CCR
0x38	CCR[2]	CCR
0x3c	CCR[3]	CCR
0x40	CCR[4]	CCR
0x48	DCR				DBL								DBA
0x4c	DMAR	DMAB

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CKD rw		ARPE rw	CMS rw		DIR rw	OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TI1S rw	MMS rw			CCDS rw

Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETP rw	ECE rw	ETPS rw		ETF rw				MSM rw	TS rw				SMS rw

Toggle fields

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDE rw		CC[4]DE rw	CC[3]DE rw	CC[2]DE rw	CC[1]DE rw	UDE rw		TIE rw		CC[4]IE rw	CC[3]IE rw	CC[2]IE rw	CC[1]IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CC[4]OF rw	CC[3]OF rw	CC[2]OF rw	CC[1]OF rw			TIF rw		CC[4]IF rw	CC[3]IF rw	CC[2]IF rw	CC[1]IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									TG w		CC[4]G w	CC[3]G w	CC[2]G w	CC[1]G w	UG w

Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC[2]F rw				IC[2]PSC rw		CC[2]S rw		IC[1]F rw				IC[1]PSC rw		CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC[2]CE rw	OC[2]M rw			OC[2]PE rw	OC[2]FE rw	CC[2]S rw		OC[1]CE rw	OC[1]M rw			OC[1]PE rw	OC[1]FE rw	CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC[4]F rw				IC[4]PSC rw		CC[4]S rw		IC[3]F rw				IC[3]PSC rw		CC[3]S rw

Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0x0-0x3

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values: 0x0-0xf

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0x0-0x3

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values: 0x0-0xf

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC[4]CE rw	OC[4]M rw			OC[4]PE rw	OC[4]FE rw	CC[4]S rw		OC[3]CE rw	OC[3]M rw			OC[3]PE rw	OC[3]FE rw	CC[3]S rw

Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CC[4]NP rw		CC[4]P rw	CC[4]E rw	CC[3]NP rw		CC[3]P rw	CC[3]E rw	CC[2]NP rw		CC[2]P rw	CC[2]E rw	CC[1]NP rw		CC[1]P rw	CC[1]E rw

Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CC[3]E

Bit 8: Capture/Compare 3 output enable.

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

CC[4]E

Bit 12: Capture/Compare 4 output enable.

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

CC[4]NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle fields

CNT

Bits 0-15: Counter value.

Allowed values: 0x0-0xffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

TIM5

0x40000c00: General-purpose-timers

77/101 fields covered.

Toggle register map

Offset	Name	31	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1								CKD		ARPE	CMS		DIR	OPM	URS	UDIS	CEN
0x4	CR2										TI1S	MMS			CCDS
0x8	SMCR		ETP	ECE	ETPS		ETF				MSM	TS				SMS
0xc	DIER			TDE		CC[4]DE	CC[3]DE	CC[2]DE	CC[1]DE	UDE		TIE		CC[4]IE	CC[3]IE	CC[2]IE	CC[1]IE	UIE
0x10	SR					CC[4]OF	CC[3]OF	CC[2]OF	CC[1]OF			TIF		CC[4]IF	CC[3]IF	CC[2]IF	CC[1]IF	UIF
0x14	EGR											TG		CC[4]G	CC[3]G	CC[2]G	CC[1]G	UG
0x18	CCMR1_Input		IC[2]F				IC[2]PSC		CC[2]S		IC[1]F				IC[1]PSC		CC[1]S
0x18	CCMR1_Output		OC[2]CE	OC[2]M			OC[2]PE	OC[2]FE	CC[2]S		OC[1]CE	OC[1]M			OC[1]PE	OC[1]FE	CC[1]S
0x1c	CCMR2_Input		IC[4]F				IC[4]PSC		CC[4]S		IC[3]F				IC[3]PSC		CC[3]S
0x1c	CCMR2_Output		OC[4]CE	OC[4]M			OC[4]PE	OC[4]FE	CC[4]S		OC[3]CE	OC[3]M			OC[3]PE	OC[3]FE	CC[3]S
0x20	CCER		CC[4]NP		CC[4]P	CC[4]E	CC[3]NP		CC[3]P	CC[3]E	CC[2]NP		CC[2]P	CC[2]E	CC[1]NP		CC[1]P	CC[1]E
0x24	CNT	CNT	CNT
0x28	PSC		PSC
0x2c	ARR	ARR	ARR
0x34	CCR[1]	CCR	CCR
0x38	CCR[2]	CCR	CCR
0x3c	CCR[3]	CCR	CCR
0x40	CCR[4]	CCR	CCR
0x48	DCR					DBL								DBA
0x4c	DMAR		DMAB
0x50	OR										IT4_RMP

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CKD rw		ARPE rw	CMS rw		DIR rw	OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TI1S rw	MMS rw			CCDS rw

Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETP rw	ECE rw	ETPS rw		ETF rw				MSM rw	TS rw				SMS rw

Toggle fields

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDE rw		CC[4]DE rw	CC[3]DE rw	CC[2]DE rw	CC[1]DE rw	UDE rw		TIE rw		CC[4]IE rw	CC[3]IE rw	CC[2]IE rw	CC[1]IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CC[4]OF rw	CC[3]OF rw	CC[2]OF rw	CC[1]OF rw			TIF rw		CC[4]IF rw	CC[3]IF rw	CC[2]IF rw	CC[1]IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									TG w		CC[4]G w	CC[3]G w	CC[2]G w	CC[1]G w	UG w

Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC[2]F rw				IC[2]PSC rw		CC[2]S rw		IC[1]F rw				IC[1]PSC rw		CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC[2]CE rw	OC[2]M rw			OC[2]PE rw	OC[2]FE rw	CC[2]S rw		OC[1]CE rw	OC[1]M rw			OC[1]PE rw	OC[1]FE rw	CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC[4]F rw				IC[4]PSC rw		CC[4]S rw		IC[3]F rw				IC[3]PSC rw		CC[3]S rw

Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0x0-0x3

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values: 0x0-0xf

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0x0-0x3

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values: 0x0-0xf

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC[4]CE rw	OC[4]M rw			OC[4]PE rw	OC[4]FE rw	CC[4]S rw		OC[3]CE rw	OC[3]M rw			OC[3]PE rw	OC[3]FE rw	CC[3]S rw

Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CC[4]NP rw		CC[4]P rw	CC[4]E rw	CC[3]NP rw		CC[3]P rw	CC[3]E rw	CC[2]NP rw		CC[2]P rw	CC[2]E rw	CC[1]NP rw		CC[1]P rw	CC[1]E rw

Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CC[3]E

Bit 8: Capture/Compare 3 output enable.

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

CC[4]E

Bit 12: Capture/Compare 4 output enable.

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

CC[4]NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CNT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle fields

CNT

Bits 0-31: Counter value.

Allowed values: 0x0-0xffffffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ARR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-31: Auto-reload value.

Allowed values: 0x0-0xffffffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

OR

TIM5 option register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IT4_RMP rw

Toggle fields

IT4_RMP

Bits 6-7: Timer Input 4 remap.

TIM8

0x40010400: Advanced-timers

92/127 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	CR1							CKD		ARPE	CMS		DIR	OPM	URS	UDIS	CEN
0x4	CR2		OIS[4]	OIS[3]N	OIS[3]	OIS[2]N	OIS[2]	OIS[1]N	OIS[1]	TI1S	MMS			CCDS	CCUS		CCPC
0x8	SMCR	ETP	ECE	ETPS		ETF				MSM	TS				SMS
0xc	DIER		TDE	COMDE	CC[4]DE	CC[3]DE	CC[2]DE	CC[1]DE	UDE	BIE	TIE	COMIE	CC[4]IE	CC[3]IE	CC[2]IE	CC[1]IE	UIE
0x10	SR				CC[4]OF	CC[3]OF	CC[2]OF	CC[1]OF		BIF	TIF	COMIF	CC[4]IF	CC[3]IF	CC[2]IF	CC[1]IF	UIF
0x14	EGR									BG	TG	COMG	CC[4]G	CC[3]G	CC[2]G	CC[1]G	UG
0x18	CCMR1_Input	IC[2]F				IC[2]PSC		CC[2]S		IC[1]F				IC[1]PSC		CC[1]S
0x18	CCMR1_Output	OC[2]CE	OC[2]M			OC[2]PE	OC[2]FE	CC[2]S		OC[1]CE	OC[1]M			OC[1]PE	OC[1]FE	CC[1]S
0x1c	CCMR2_Input	IC[4]F				IC[4]PSC		CC[4]S		IC[3]F				IC[3]PSC		CC[3]S
0x1c	CCMR2_Output	OC[4]CE	OC[4]M			OC[4]PE	OC[4]FE	CC[4]S		OC[3]CE	OC[3]M			OC[3]PE	OC[3]FE	CC[3]S
0x20	CCER			CC[4]P	CC[4]E	CC[3]NP	CC[3]NE	CC[3]P	CC[3]E	CC[2]NP	CC[2]NE	CC[2]P	CC[2]E	CC[1]NP	CC[1]NE	CC[1]P	CC[1]E
0x24	CNT	CNT
0x28	PSC	PSC
0x2c	ARR	ARR
0x30	RCR									REP
0x34	CCR[1]	CCR
0x38	CCR[2]	CCR
0x3c	CCR[3]	CCR
0x40	CCR[4]	CCR
0x44	BDTR	MOE	AOE	BKP	BKE	OSSR	OSSI	LOCK		DTG
0x48	DCR				DBL								DBA
0x4c	DMAR	DMAB

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CKD rw		ARPE rw	CMS rw		DIR rw	OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

10/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	OIS[4] rw	OIS[3]N rw	OIS[3] rw	OIS[2]N rw	OIS[2] rw	OIS[1]N rw	OIS[1] rw	TI1S rw	MMS rw			CCDS rw	CCUS rw		CCPC rw

Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

OIS[1]

Bit 8: Output Idle state (OC1 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[1]N

Bit 9: Output Idle state (OC1N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[2]

Bit 10: Output Idle state (OC2 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[2]N

Bit 11: Output Idle state (OC2N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[3]

Bit 12: Output Idle state (OC3 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[3]N

Bit 13: Output Idle state (OC3N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[4]

Bit 14: Output Idle state (OC4 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETP rw	ECE rw	ETPS rw		ETF rw				MSM rw	TS rw				SMS rw

Toggle fields

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

12/15 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDE rw	COMDE rw	CC[4]DE rw	CC[3]DE rw	CC[2]DE rw	CC[1]DE rw	UDE rw	BIE rw	TIE rw	COMIE rw	CC[4]IE rw	CC[3]IE rw	CC[2]IE rw	CC[1]IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

COMIE

Bit 5: COM interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CC[4]OF rw	CC[3]OF rw	CC[2]OF rw	CC[1]OF rw		BIF rw	TIF rw	COMIF rw	CC[4]IF rw	CC[3]IF rw	CC[2]IF rw	CC[1]IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

BIF

Bit 7: Break interrupt flag.

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

6/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								BG w	TG w	COMG w	CC[4]G w	CC[3]G w	CC[2]G w	CC[1]G w	UG w

Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC[2]F rw				IC[2]PSC rw		CC[2]S rw		IC[1]F rw				IC[1]PSC rw		CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC[2]CE rw	OC[2]M rw			OC[2]PE rw	OC[2]FE rw	CC[2]S rw		OC[1]CE rw	OC[1]M rw			OC[1]PE rw	OC[1]FE rw	CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC[4]F rw				IC[4]PSC rw		CC[4]S rw		IC[3]F rw				IC[3]PSC rw		CC[3]S rw

Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0x0-0x3

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values: 0x0-0xf

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0x0-0x3

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values: 0x0-0xf

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC[4]CE rw	OC[4]M rw			OC[4]PE rw	OC[4]FE rw	CC[4]S rw		OC[3]CE rw	OC[3]M rw			OC[3]PE rw	OC[3]FE rw	CC[3]S rw

Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CC[4]P rw	CC[4]E rw	CC[3]NP rw	CC[3]NE rw	CC[3]P rw	CC[3]E rw	CC[2]NP rw	CC[2]NE rw	CC[2]P rw	CC[2]E rw	CC[1]NP rw	CC[1]NE rw	CC[1]P rw	CC[1]E rw

Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[1]NE

Bit 2: Capture/Compare 1 complementary output enable.

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

CC[2]NE

Bit 6: Capture/Compare 2 complementary output enable.

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CC[3]E

Bit 8: Capture/Compare 3 output enable.

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

CC[3]NE

Bit 10: Capture/Compare 3 complementary output enable.

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

CC[4]E

Bit 12: Capture/Compare 4 output enable.

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle fields

CNT

Bits 0-15: counter value.

Allowed values: 0x0-0xffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REP rw

Toggle fields

REP

Bits 0-7: Repetition counter value.

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MOE rw	AOE rw	BKP rw	BKE rw	OSSR rw	OSSI rw	LOCK rw		DTG rw

Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

Allowed values: 0x0-0xff

LOCK

Bits 8-9: Lock configuration.

Allowed values:
0: Off: No bit is write protected
1: Level1: Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
2: Level2: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
3: Level3: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written

OSSI

Bit 10: Off-state selection for Idle mode.

Allowed values:
0: Disabled: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are forced to idle level

OSSR

Bit 11: Off-state selection for Run mode.

Allowed values:
0: Disabled: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are enabled with their inactive level

BKE

Bit 12: Break enable.

Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x disabled

BKP

Bit 13: Break polarity.

Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high

AOE

Bit 14: Automatic output enable.

Allowed values:
0: Manual: MOE can be set only by software
1: Automatic: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)

MOE

Bit 15: Main output enable.

Allowed values:
0: DisabledIdle: OC/OCN are disabled or forced idle depending on OSSI
1: Enabled: OC/OCN are enabled if CCxE/CCxNE are set

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

TIM9

0x40014000: General purpose timers

12/49 fields covered.

Toggle register map

Offset	Name	15	14	11	10	9	7	6	5	4	3	2	1	0
0x0	CR1					CKD	ARPE				OPM	URS	UDIS	CEN
0x4	CR2							MMS
0x8	SMCR						MSM	TS				SMS
0xc	DIER							TIE				CC[2]IE	CC[1]IE	UIE
0x10	SR				CC[2]OF	CC[1]OF		TIF				CC[2]IF	CC[1]IF	UIF
0x14	EGR							TG				CC[2]G	CC[1]G	UG
0x18	CCMR1_Input		IC[2]F	IC[2]PSC		CC[2]S		IC[1]F			IC[1]PSC		CC[1]S
0x18	CCMR1_Output		OC[2]M	OC[2]PE	OC[2]FE	CC[2]S		OC[1]M			OC[1]PE	OC[1]FE	CC[1]S
0x20	CCER						CC[2]NP		CC[2]P	CC[2]E	CC[1]NP		CC[1]P	CC[1]E
0x24	CNT	CNT
0x28	PSC	PSC
0x2c	ARR	ARR
0x34	CCR[1]	CCR
0x38	CCR[2]	CCR

Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CKD rw		ARPE rw				OPM rw	URS rw	UDIS rw	CEN rw

Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									MMS rw

Toggle fields

MMS

Bits 4-6: Master mode selection.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								MSM rw	TS rw				SMS rw

Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									TIE rw				CC[2]IE rw	CC[1]IE rw	UIE rw

Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					CC[2]OF rw	CC[1]OF rw			TIF rw				CC[2]IF rw	CC[1]IF rw	UIF rw

Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

1/4 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									TG w				CC[2]G w	CC[1]G w	UG w

Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

CC[2]G

Bit 2: Capture/compare 2 generation.

TG

Bit 6: Trigger generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	IC[2]F rw			IC[2]PSC rw		CC[2]S rw			IC[1]F rw			IC[1]PSC rw		CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-6: Input capture 1 filter.

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

IC[2]F

Bits 12-14: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

2/8 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	OC[2]M rw			OC[2]PE rw	OC[2]FE rw	CC[2]S rw			OC[1]M rw			OC[1]PE rw	OC[1]FE rw	CC[1]S rw

Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

OC[2]FE

Bit 10: Output compare 2 fast enable.

OC[2]PE

Bit 11: Output compare 2 preload enable.

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								CC[2]NP rw		CC[2]P rw	CC[2]E rw	CC[1]NP rw		CC[1]P rw	CC[1]E rw

Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle fields

CNT

Bits 0-15: counter value.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle fields

ARR

Bits 0-15: Auto-reload value.

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR rw

Toggle fields

CCR

Bits 0-15: Capture/Compare value.

USART1

0x40011000: Universal synchronous asynchronous receiver transmitter

44/51 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	SR							CTS	LBD	TXE	TC	RXNE	IDLE	ORE	NF	FE	PE
0x4	DR								DR
0x8	BRR	DIV_Mantissa												DIV_Fraction
0xc	CR1	OVER8		UE	M	WAKE	PCE	PS	PEIE	TXEIE	TCIE	RXNEIE	IDLEIE	TE	RE	RWU	SBK
0x10	CR2		LINEN	STOP		CLKEN	CPOL	CPHA	LBCL		LBDIE	LBDL		ADD
0x14	CR3					ONEBIT	CTSIE	CTSE	RTSE	DMAT	DMAR	SCEN	NACK	HDSEL	IRLP	IREN	EIE
0x18	GTPR	GT								PSC

Toggle registers

SR

Status register

Offset: 0x0, size: 32, reset: 0x00C00000, access: Unspecified

6/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CTS rw	LBD rw	TXE r	TC rw	RXNE rw	IDLE r	ORE r	NF r	FE r	PE r

Toggle fields

PE

Bit 0: Parity error.

FE

Bit 1: Framing error.

NF

Bit 2: Noise detected flag.

ORE

Bit 3: Overrun error.

IDLE

Bit 4: IDLE line detected.

RXNE

Bit 5: Read data register not empty.

TC

Bit 6: Transmission complete.

TXE

Bit 7: Transmit data register empty.

LBD

Bit 8: LIN break detection flag.

CTS

Bit 9: CTS flag.

DR

Data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							DR rw

Toggle fields

DR

Bits 0-8: Data value.

Allowed values: 0x0-0x1ff

BRR

Baud rate register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DIV_Mantissa rw												DIV_Fraction rw

Toggle fields

DIV_Fraction

Bits 0-3: fraction of USARTDIV.

Allowed values: 0x0-0xf

DIV_Mantissa

Bits 4-15: mantissa of USARTDIV.

Allowed values: 0x0-0xfff

CR1

Control register 1

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVER8 rw		UE rw	M rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXEIE rw	TCIE rw	RXNEIE rw	IDLEIE rw	TE rw	RE rw	RWU rw	SBK rw

Toggle fields

SBK

Bit 0: Send break.

Allowed values:
0: NoBreak: No break character is transmitted
1: Break: Break character transmitted

RWU

Bit 1: Receiver wakeup.

Allowed values:
0: Active: Receiver in active mode
1: Mute: Receiver in mute mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver disabled
1: Enabled: Receiver enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter disabled
1: Enabled: Transmitter enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: IDLE interrupt disabled
1: Enabled: IDLE interrupt enabled

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: RXNE interrupt disabled
1: Enabled: RXNE interrupt enabled

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

TXEIE

Bit 7: TXE interrupt enable.

Allowed values:
0: Disabled: TXE interrupt disabled
1: Enabled: TXE interrupt enabled

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: PE interrupt disabled
1: Enabled: PE interrupt enabled

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Wakeup method.

Allowed values:
0: IdleLine: USART wakeup on idle line
1: AddressMark: USART wakeup on address mark

M

Bit 12: Word length.

Allowed values:
0: M8: 8 data bits
1: M9: 9 data bits

UE

Bit 13: USART enable.

Allowed values:
0: Disabled: USART prescaler and outputs disabled
1: Enabled: USART enabled

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversample16: Oversampling by 16
1: Oversample8: Oversampling by 8

CR2

Control register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

8/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	LINEN rw	STOP rw		CLKEN rw	CPOL rw	CPHA rw	LBCL rw		LBDIE rw	LBDL rw		ADD rw

Toggle fields

ADD

Bits 0-3: Address of the USART node.

Allowed values: 0x0-0xf

LBDL

Bit 5: lin break detection length.

Allowed values:
0: LBDL10: 10-bit break detection
1: LBDL11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: LIN break detection interrupt disabled
1: Enabled: LIN break detection interrupt enabled

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bits
2: Stop2: 2 stop bits
3: Stop1p5: 1.5 stop bits

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

CR3

Control register 3

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				ONEBIT rw	CTSIE rw	CTSE rw	RTSE rw	DMAT rw	DMAR rw	SCEN rw	NACK rw	HDSEL rw	IRLP rw	IREN rw	EIE rw

Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

IREN

Bit 1: IrDA mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: IrDA low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: FullDuplex: Half duplex mode is not selected
1: HalfDuplex: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard mode disabled
1: Enabled: Smartcard mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS hardware flow control enabled

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS hardware flow control enabled

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: CTS interrupt disabled
1: Enabled: CTS interrupt enabled

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

GTPR

Guard time and prescaler register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
GT rw								PSC rw

Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

USART2

0x40004400: Universal synchronous asynchronous receiver transmitter

44/51 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	SR							CTS	LBD	TXE	TC	RXNE	IDLE	ORE	NF	FE	PE
0x4	DR								DR
0x8	BRR	DIV_Mantissa												DIV_Fraction
0xc	CR1	OVER8		UE	M	WAKE	PCE	PS	PEIE	TXEIE	TCIE	RXNEIE	IDLEIE	TE	RE	RWU	SBK
0x10	CR2		LINEN	STOP		CLKEN	CPOL	CPHA	LBCL		LBDIE	LBDL		ADD
0x14	CR3					ONEBIT	CTSIE	CTSE	RTSE	DMAT	DMAR	SCEN	NACK	HDSEL	IRLP	IREN	EIE
0x18	GTPR	GT								PSC

Toggle registers

SR

Status register

Offset: 0x0, size: 32, reset: 0x00C00000, access: Unspecified

6/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CTS rw	LBD rw	TXE r	TC rw	RXNE rw	IDLE r	ORE r	NF r	FE r	PE r

Toggle fields

PE

Bit 0: Parity error.

FE

Bit 1: Framing error.

NF

Bit 2: Noise detected flag.

ORE

Bit 3: Overrun error.

IDLE

Bit 4: IDLE line detected.

RXNE

Bit 5: Read data register not empty.

TC

Bit 6: Transmission complete.

TXE

Bit 7: Transmit data register empty.

LBD

Bit 8: LIN break detection flag.

CTS

Bit 9: CTS flag.

DR

Data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							DR rw

Toggle fields

DR

Bits 0-8: Data value.

Allowed values: 0x0-0x1ff

BRR

Baud rate register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DIV_Mantissa rw												DIV_Fraction rw

Toggle fields

DIV_Fraction

Bits 0-3: fraction of USARTDIV.

Allowed values: 0x0-0xf

DIV_Mantissa

Bits 4-15: mantissa of USARTDIV.

Allowed values: 0x0-0xfff

CR1

Control register 1

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVER8 rw		UE rw	M rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXEIE rw	TCIE rw	RXNEIE rw	IDLEIE rw	TE rw	RE rw	RWU rw	SBK rw

Toggle fields

SBK

Bit 0: Send break.

Allowed values:
0: NoBreak: No break character is transmitted
1: Break: Break character transmitted

RWU

Bit 1: Receiver wakeup.

Allowed values:
0: Active: Receiver in active mode
1: Mute: Receiver in mute mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver disabled
1: Enabled: Receiver enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter disabled
1: Enabled: Transmitter enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: IDLE interrupt disabled
1: Enabled: IDLE interrupt enabled

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: RXNE interrupt disabled
1: Enabled: RXNE interrupt enabled

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

TXEIE

Bit 7: TXE interrupt enable.

Allowed values:
0: Disabled: TXE interrupt disabled
1: Enabled: TXE interrupt enabled

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: PE interrupt disabled
1: Enabled: PE interrupt enabled

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Wakeup method.

Allowed values:
0: IdleLine: USART wakeup on idle line
1: AddressMark: USART wakeup on address mark

M

Bit 12: Word length.

Allowed values:
0: M8: 8 data bits
1: M9: 9 data bits

UE

Bit 13: USART enable.

Allowed values:
0: Disabled: USART prescaler and outputs disabled
1: Enabled: USART enabled

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversample16: Oversampling by 16
1: Oversample8: Oversampling by 8

CR2

Control register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

8/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	LINEN rw	STOP rw		CLKEN rw	CPOL rw	CPHA rw	LBCL rw		LBDIE rw	LBDL rw		ADD rw

Toggle fields

ADD

Bits 0-3: Address of the USART node.

Allowed values: 0x0-0xf

LBDL

Bit 5: lin break detection length.

Allowed values:
0: LBDL10: 10-bit break detection
1: LBDL11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: LIN break detection interrupt disabled
1: Enabled: LIN break detection interrupt enabled

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bits
2: Stop2: 2 stop bits
3: Stop1p5: 1.5 stop bits

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

CR3

Control register 3

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				ONEBIT rw	CTSIE rw	CTSE rw	RTSE rw	DMAT rw	DMAR rw	SCEN rw	NACK rw	HDSEL rw	IRLP rw	IREN rw	EIE rw

Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

IREN

Bit 1: IrDA mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: IrDA low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: FullDuplex: Half duplex mode is not selected
1: HalfDuplex: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard mode disabled
1: Enabled: Smartcard mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS hardware flow control enabled

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS hardware flow control enabled

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: CTS interrupt disabled
1: Enabled: CTS interrupt enabled

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

GTPR

Guard time and prescaler register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
GT rw								PSC rw

Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

USART6

0x40011400: Universal synchronous asynchronous receiver transmitter

44/51 fields covered.

Toggle register map

Offset	Name	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0	SR							CTS	LBD	TXE	TC	RXNE	IDLE	ORE	NF	FE	PE
0x4	DR								DR
0x8	BRR	DIV_Mantissa												DIV_Fraction
0xc	CR1	OVER8		UE	M	WAKE	PCE	PS	PEIE	TXEIE	TCIE	RXNEIE	IDLEIE	TE	RE	RWU	SBK
0x10	CR2		LINEN	STOP		CLKEN	CPOL	CPHA	LBCL		LBDIE	LBDL		ADD
0x14	CR3					ONEBIT	CTSIE	CTSE	RTSE	DMAT	DMAR	SCEN	NACK	HDSEL	IRLP	IREN	EIE
0x18	GTPR	GT								PSC

Toggle registers

SR

Status register

Offset: 0x0, size: 32, reset: 0x00C00000, access: Unspecified

6/10 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CTS rw	LBD rw	TXE r	TC rw	RXNE rw	IDLE r	ORE r	NF r	FE r	PE r

Toggle fields

PE

Bit 0: Parity error.

FE

Bit 1: Framing error.

NF

Bit 2: Noise detected flag.

ORE

Bit 3: Overrun error.

IDLE

Bit 4: IDLE line detected.

RXNE

Bit 5: Read data register not empty.

TC

Bit 6: Transmission complete.

TXE

Bit 7: Transmit data register empty.

LBD

Bit 8: LIN break detection flag.

CTS

Bit 9: CTS flag.

DR

Data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							DR rw

Toggle fields

DR

Bits 0-8: Data value.

Allowed values: 0x0-0x1ff

BRR

Baud rate register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DIV_Mantissa rw												DIV_Fraction rw

Toggle fields

DIV_Fraction

Bits 0-3: fraction of USARTDIV.

Allowed values: 0x0-0xf

DIV_Mantissa

Bits 4-15: mantissa of USARTDIV.

Allowed values: 0x0-0xfff

CR1

Control register 1

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVER8 rw		UE rw	M rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXEIE rw	TCIE rw	RXNEIE rw	IDLEIE rw	TE rw	RE rw	RWU rw	SBK rw

Toggle fields

SBK

Bit 0: Send break.

Allowed values:
0: NoBreak: No break character is transmitted
1: Break: Break character transmitted

RWU

Bit 1: Receiver wakeup.

Allowed values:
0: Active: Receiver in active mode
1: Mute: Receiver in mute mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver disabled
1: Enabled: Receiver enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter disabled
1: Enabled: Transmitter enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: IDLE interrupt disabled
1: Enabled: IDLE interrupt enabled

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: RXNE interrupt disabled
1: Enabled: RXNE interrupt enabled

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

TXEIE

Bit 7: TXE interrupt enable.

Allowed values:
0: Disabled: TXE interrupt disabled
1: Enabled: TXE interrupt enabled

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: PE interrupt disabled
1: Enabled: PE interrupt enabled

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Wakeup method.

Allowed values:
0: IdleLine: USART wakeup on idle line
1: AddressMark: USART wakeup on address mark

M

Bit 12: Word length.

Allowed values:
0: M8: 8 data bits
1: M9: 9 data bits

UE

Bit 13: USART enable.

Allowed values:
0: Disabled: USART prescaler and outputs disabled
1: Enabled: USART enabled

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversample16: Oversampling by 16
1: Oversample8: Oversampling by 8

CR2

Control register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

8/9 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	LINEN rw	STOP rw		CLKEN rw	CPOL rw	CPHA rw	LBCL rw		LBDIE rw	LBDL rw		ADD rw

Toggle fields

ADD

Bits 0-3: Address of the USART node.

Allowed values: 0x0-0xf

LBDL

Bit 5: lin break detection length.

Allowed values:
0: LBDL10: 10-bit break detection
1: LBDL11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: LIN break detection interrupt disabled
1: Enabled: LIN break detection interrupt enabled

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bits
2: Stop2: 2 stop bits
3: Stop1p5: 1.5 stop bits

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

CR3

Control register 3

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				ONEBIT rw	CTSIE rw	CTSE rw	RTSE rw	DMAT rw	DMAR rw	SCEN rw	NACK rw	HDSEL rw	IRLP rw	IREN rw	EIE rw

Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

IREN

Bit 1: IrDA mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: IrDA low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: FullDuplex: Half duplex mode is not selected
1: HalfDuplex: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard mode disabled
1: Enabled: Smartcard mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS hardware flow control enabled

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS hardware flow control enabled

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: CTS interrupt disabled
1: Enabled: CTS interrupt enabled

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

GTPR

Guard time and prescaler register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
GT rw								PSC rw

Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

WWDG

0x40002c00: Window watchdog

6/6 fields covered.

Toggle register map

Offset	Name	9	8	7	6	0
0x0	CR			WDGA	T
0x4	CFR	EWI	WDGTB		W
0x8	SR					EWIF

Toggle registers

CR

Control register

Offset: 0x0, size: 32, reset: 0x0000007F, access: read-write

2/2 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								WDGA rw	T rw

Toggle fields

T

Bits 0-6: 7-bit counter (MSB to LSB).

Allowed values: 0x0-0x7f

WDGA

Bit 7: Activation bit.

Allowed values:
0: Disabled: Watchdog disabled
1: Enabled: Watchdog enabled

CFR

Configuration register

Offset: 0x4, size: 32, reset: 0x0000007F, access: read-write

3/3 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EWI rw	WDGTB rw		W rw

Toggle fields

W

Bits 0-6: 7-bit window value.

Allowed values: 0x0-0x7f

WDGTB

Bits 7-8: Timer base.

Allowed values:
0: Div1: Counter clock (PCLK1 div 4096) div 1
1: Div2: Counter clock (PCLK1 div 4096) div 2
2: Div4: Counter clock (PCLK1 div 4096) div 4
3: Div8: Counter clock (PCLK1 div 4096) div 8

EWI

Bit 9: Early wakeup interrupt.

Allowed values:
1: Enable: interrupt occurs whenever the counter reaches the value 0x40

SR

Status register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EWIF rw

Toggle fields

EWIF

Bit 0: Early wakeup interrupt flag.

Allowed values:
0: Finished: The EWI Interrupt Service Routine has been serviced
1: Pending: The EWI Interrupt Service Routine has been triggered