Overall: 962/12297 fields covered

ADC1

0x40012000: Analog-to-digital converter

5/67 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 SR
0x4 CR1
0x8 CR2
0xc SMPR1
0x10 SMPR2
0x14 JOFR1
0x18 JOFR2
0x1c JOFR3
0x20 JOFR4
0x24 HTR
0x28 LTR
0x2c SQR1
0x30 SQR2
0x34 SQR3
0x38 JSQR
0x3c JDR1
0x40 JDR2
0x44 JDR3
0x48 JDR4
0x4c DR
Toggle registers

SR

status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVR
rw 		STRT
rw 		JSTRT
rw 		JEOC
rw 		EOC
rw 		AWD
rw
Toggle fields

AWD

Bit 0: Analog watchdog flag.

EOC

Bit 1: Regular channel end of conversion.

JEOC

Bit 2: Injected channel end of conversion.

JSTRT

Bit 3: Injected channel start flag.

STRT

Bit 4: Regular channel start flag.

OVR

Bit 5: Overrun.

CR1

control register 1

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OVRIE
rw 		RES
rw 		AWDEN
rw 		JAWDEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISCNUM
rw 		JDISCEN
rw 		DISCEN
rw 		JAUTO
rw 		AWDSGL
rw 		SCAN
rw 		JEOCIE
rw 		AWDIE
rw 		EOCIE
rw 		AWDCH
rw
Toggle fields

AWDCH

Bits 0-4: Analog watchdog channel select bits.

EOCIE

Bit 5: Interrupt enable for EOC.

AWDIE

Bit 6: Analog watchdog interrupt enable.

JEOCIE

Bit 7: Interrupt enable for injected channels.

SCAN

Bit 8: Scan mode.

AWDSGL

Bit 9: Enable the watchdog on a single channel in scan mode.

JAUTO

Bit 10: Automatic injected group conversion.

DISCEN

Bit 11: Discontinuous mode on regular channels.

JDISCEN

Bit 12: Discontinuous mode on injected channels.

DISCNUM

Bits 13-15: Discontinuous mode channel count.

JAWDEN

Bit 22: Analog watchdog enable on injected channels.

AWDEN

Bit 23: Analog watchdog enable on regular channels.

RES

Bits 24-25: Resolution.

OVRIE

Bit 26: Overrun interrupt enable.

CR2

control register 2

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWSTART
rw 		EXTEN
rw 		EXTSEL
rw 		JSWSTART
rw 		JEXTEN
rw 		JEXTSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALIGN
rw 		EOCS
rw 		DDS
rw 		DMA
rw 		CONT
rw 		ADON
rw
Toggle fields

ADON

Bit 0: A/D Converter ON / OFF.

CONT

Bit 1: Continuous conversion.

DMA

Bit 8: Direct memory access mode (for single ADC mode).

DDS

Bit 9: DMA disable selection (for single ADC mode).

EOCS

Bit 10: End of conversion selection.

ALIGN

Bit 11: Data alignment.

JEXTSEL

Bits 16-19: External event select for injected group.

JEXTEN

Bits 20-21: External trigger enable for injected channels.

JSWSTART

Bit 22: Start conversion of injected channels.

EXTSEL

Bits 24-27: External event select for regular group.

EXTEN

Bits 28-29: External trigger enable for regular channels.

SWSTART

Bit 30: Start conversion of regular channels.

SMPR1

sample time register 1

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMPx_x
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMPx_x
rw
Toggle fields

SMPx_x

Bits 0-31: Sample time bits.

SMPR2

sample time register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMPx_x
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMPx_x
rw
Toggle fields

SMPx_x

Bits 0-31: Sample time bits.

JOFR1

injected channel data offset register x

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JOFFSET1
rw
Toggle fields

JOFFSET1

Bits 0-11: Data offset for injected channel x.

JOFR2

injected channel data offset register x

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JOFFSET2
rw
Toggle fields

JOFFSET2

Bits 0-11: Data offset for injected channel x.

JOFR3

injected channel data offset register x

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JOFFSET3
rw
Toggle fields

JOFFSET3

Bits 0-11: Data offset for injected channel x.

JOFR4

injected channel data offset register x

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JOFFSET4
rw
Toggle fields

JOFFSET4

Bits 0-11: Data offset for injected channel x.

HTR

watchdog higher threshold register

Offset: 0x24, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HT
rw
Toggle fields

HT

Bits 0-11: Analog watchdog higher threshold.

LTR

watchdog lower threshold register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT
rw
Toggle fields

LT

Bits 0-11: Analog watchdog lower threshold.

SQR1

regular sequence register 1

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
L
rw 		SQ16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ16
rw 		SQ15
rw 		SQ14
rw 		SQ13
rw
Toggle fields

SQ13

Bits 0-4: 13th conversion in regular sequence.

SQ14

Bits 5-9: 14th conversion in regular sequence.

SQ15

Bits 10-14: 15th conversion in regular sequence.

SQ16

Bits 15-19: 16th conversion in regular sequence.

L

Bits 20-23: Regular channel sequence length.

SQR2

regular sequence register 2

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ12
rw 		SQ11
rw 		SQ10
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ10
rw 		SQ9
rw 		SQ8
rw 		SQ7
rw
Toggle fields

SQ7

Bits 0-4: 7th conversion in regular sequence.

SQ8

Bits 5-9: 8th conversion in regular sequence.

SQ9

Bits 10-14: 9th conversion in regular sequence.

SQ10

Bits 15-19: 10th conversion in regular sequence.

SQ11

Bits 20-24: 11th conversion in regular sequence.

SQ12

Bits 25-29: 12th conversion in regular sequence.

SQR3

regular sequence register 3

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ6
rw 		SQ5
rw 		SQ4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ4
rw 		SQ3
rw 		SQ2
rw 		SQ1
rw
Toggle fields

SQ1

Bits 0-4: 1st conversion in regular sequence.

SQ2

Bits 5-9: 2nd conversion in regular sequence.

SQ3

Bits 10-14: 3rd conversion in regular sequence.

SQ4

Bits 15-19: 4th conversion in regular sequence.

SQ5

Bits 20-24: 5th conversion in regular sequence.

SQ6

Bits 25-29: 6th conversion in regular sequence.

JSQR

injected sequence register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JL
rw 		JSQ4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JSQ4
rw 		JSQ3
rw 		JSQ2
rw 		JSQ1
rw
Toggle fields

JSQ1

Bits 0-4: 1st conversion in injected sequence.

JSQ2

Bits 5-9: 2nd conversion in injected sequence.

JSQ3

Bits 10-14: 3rd conversion in injected sequence.

JSQ4

Bits 15-19: 4th conversion in injected sequence.

JL

Bits 20-21: Injected sequence length.

JDR1

injected data register x

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: Injected data.

JDR2

injected data register x

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: Injected data.

JDR3

injected data register x

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: Injected data.

JDR4

injected data register x

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: Injected data.

DR

regular data register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
r
Toggle fields

DATA

Bits 0-15: Regular data.

ADC2

0x40012100: Analog-to-digital converter

5/67 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 SR
0x4 CR1
0x8 CR2
0xc SMPR1
0x10 SMPR2
0x14 JOFR1
0x18 JOFR2
0x1c JOFR3
0x20 JOFR4
0x24 HTR
0x28 LTR
0x2c SQR1
0x30 SQR2
0x34 SQR3
0x38 JSQR
0x3c JDR1
0x40 JDR2
0x44 JDR3
0x48 JDR4
0x4c DR
Toggle registers

SR

status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVR
rw 		STRT
rw 		JSTRT
rw 		JEOC
rw 		EOC
rw 		AWD
rw
Toggle fields

AWD

Bit 0: Analog watchdog flag.

EOC

Bit 1: Regular channel end of conversion.

JEOC

Bit 2: Injected channel end of conversion.

JSTRT

Bit 3: Injected channel start flag.

STRT

Bit 4: Regular channel start flag.

OVR

Bit 5: Overrun.

CR1

control register 1

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OVRIE
rw 		RES
rw 		AWDEN
rw 		JAWDEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISCNUM
rw 		JDISCEN
rw 		DISCEN
rw 		JAUTO
rw 		AWDSGL
rw 		SCAN
rw 		JEOCIE
rw 		AWDIE
rw 		EOCIE
rw 		AWDCH
rw
Toggle fields

AWDCH

Bits 0-4: Analog watchdog channel select bits.

EOCIE

Bit 5: Interrupt enable for EOC.

AWDIE

Bit 6: Analog watchdog interrupt enable.

JEOCIE

Bit 7: Interrupt enable for injected channels.

SCAN

Bit 8: Scan mode.

AWDSGL

Bit 9: Enable the watchdog on a single channel in scan mode.

JAUTO

Bit 10: Automatic injected group conversion.

DISCEN

Bit 11: Discontinuous mode on regular channels.

JDISCEN

Bit 12: Discontinuous mode on injected channels.

DISCNUM

Bits 13-15: Discontinuous mode channel count.

JAWDEN

Bit 22: Analog watchdog enable on injected channels.

AWDEN

Bit 23: Analog watchdog enable on regular channels.

RES

Bits 24-25: Resolution.

OVRIE

Bit 26: Overrun interrupt enable.

CR2

control register 2

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWSTART
rw 		EXTEN
rw 		EXTSEL
rw 		JSWSTART
rw 		JEXTEN
rw 		JEXTSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALIGN
rw 		EOCS
rw 		DDS
rw 		DMA
rw 		CONT
rw 		ADON
rw
Toggle fields

ADON

Bit 0: A/D Converter ON / OFF.

CONT

Bit 1: Continuous conversion.

DMA

Bit 8: Direct memory access mode (for single ADC mode).

DDS

Bit 9: DMA disable selection (for single ADC mode).

EOCS

Bit 10: End of conversion selection.

ALIGN

Bit 11: Data alignment.

JEXTSEL

Bits 16-19: External event select for injected group.

JEXTEN

Bits 20-21: External trigger enable for injected channels.

JSWSTART

Bit 22: Start conversion of injected channels.

EXTSEL

Bits 24-27: External event select for regular group.

EXTEN

Bits 28-29: External trigger enable for regular channels.

SWSTART

Bit 30: Start conversion of regular channels.

SMPR1

sample time register 1

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMPx_x
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMPx_x
rw
Toggle fields

SMPx_x

Bits 0-31: Sample time bits.

SMPR2

sample time register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMPx_x
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMPx_x
rw
Toggle fields

SMPx_x

Bits 0-31: Sample time bits.

JOFR1

injected channel data offset register x

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JOFFSET1
rw
Toggle fields

JOFFSET1

Bits 0-11: Data offset for injected channel x.

JOFR2

injected channel data offset register x

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JOFFSET2
rw
Toggle fields

JOFFSET2

Bits 0-11: Data offset for injected channel x.

JOFR3

injected channel data offset register x

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JOFFSET3
rw
Toggle fields

JOFFSET3

Bits 0-11: Data offset for injected channel x.

JOFR4

injected channel data offset register x

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JOFFSET4
rw
Toggle fields

JOFFSET4

Bits 0-11: Data offset for injected channel x.

HTR

watchdog higher threshold register

Offset: 0x24, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HT
rw
Toggle fields

HT

Bits 0-11: Analog watchdog higher threshold.

LTR

watchdog lower threshold register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT
rw
Toggle fields

LT

Bits 0-11: Analog watchdog lower threshold.

SQR1

regular sequence register 1

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
L
rw 		SQ16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ16
rw 		SQ15
rw 		SQ14
rw 		SQ13
rw
Toggle fields

SQ13

Bits 0-4: 13th conversion in regular sequence.

SQ14

Bits 5-9: 14th conversion in regular sequence.

SQ15

Bits 10-14: 15th conversion in regular sequence.

SQ16

Bits 15-19: 16th conversion in regular sequence.

L

Bits 20-23: Regular channel sequence length.

SQR2

regular sequence register 2

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ12
rw 		SQ11
rw 		SQ10
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ10
rw 		SQ9
rw 		SQ8
rw 		SQ7
rw
Toggle fields

SQ7

Bits 0-4: 7th conversion in regular sequence.

SQ8

Bits 5-9: 8th conversion in regular sequence.

SQ9

Bits 10-14: 9th conversion in regular sequence.

SQ10

Bits 15-19: 10th conversion in regular sequence.

SQ11

Bits 20-24: 11th conversion in regular sequence.

SQ12

Bits 25-29: 12th conversion in regular sequence.

SQR3

regular sequence register 3

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ6
rw 		SQ5
rw 		SQ4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ4
rw 		SQ3
rw 		SQ2
rw 		SQ1
rw
Toggle fields

SQ1

Bits 0-4: 1st conversion in regular sequence.

SQ2

Bits 5-9: 2nd conversion in regular sequence.

SQ3

Bits 10-14: 3rd conversion in regular sequence.

SQ4

Bits 15-19: 4th conversion in regular sequence.

SQ5

Bits 20-24: 5th conversion in regular sequence.

SQ6

Bits 25-29: 6th conversion in regular sequence.

JSQR

injected sequence register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JL
rw 		JSQ4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JSQ4
rw 		JSQ3
rw 		JSQ2
rw 		JSQ1
rw
Toggle fields

JSQ1

Bits 0-4: 1st conversion in injected sequence.

JSQ2

Bits 5-9: 2nd conversion in injected sequence.

JSQ3

Bits 10-14: 3rd conversion in injected sequence.

JSQ4

Bits 15-19: 4th conversion in injected sequence.

JL

Bits 20-21: Injected sequence length.

JDR1

injected data register x

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: Injected data.

JDR2

injected data register x

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: Injected data.

JDR3

injected data register x

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: Injected data.

JDR4

injected data register x

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: Injected data.

DR

regular data register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
r
Toggle fields

DATA

Bits 0-15: Regular data.

ADC3

0x40012200: Analog-to-digital converter

5/67 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 SR
0x4 CR1
0x8 CR2
0xc SMPR1
0x10 SMPR2
0x14 JOFR1
0x18 JOFR2
0x1c JOFR3
0x20 JOFR4
0x24 HTR
0x28 LTR
0x2c SQR1
0x30 SQR2
0x34 SQR3
0x38 JSQR
0x3c JDR1
0x40 JDR2
0x44 JDR3
0x48 JDR4
0x4c DR
Toggle registers

SR

status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVR
rw 		STRT
rw 		JSTRT
rw 		JEOC
rw 		EOC
rw 		AWD
rw
Toggle fields

AWD

Bit 0: Analog watchdog flag.

EOC

Bit 1: Regular channel end of conversion.

JEOC

Bit 2: Injected channel end of conversion.

JSTRT

Bit 3: Injected channel start flag.

STRT

Bit 4: Regular channel start flag.

OVR

Bit 5: Overrun.

CR1

control register 1

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OVRIE
rw 		RES
rw 		AWDEN
rw 		JAWDEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISCNUM
rw 		JDISCEN
rw 		DISCEN
rw 		JAUTO
rw 		AWDSGL
rw 		SCAN
rw 		JEOCIE
rw 		AWDIE
rw 		EOCIE
rw 		AWDCH
rw
Toggle fields

AWDCH

Bits 0-4: Analog watchdog channel select bits.

EOCIE

Bit 5: Interrupt enable for EOC.

AWDIE

Bit 6: Analog watchdog interrupt enable.

JEOCIE

Bit 7: Interrupt enable for injected channels.

SCAN

Bit 8: Scan mode.

AWDSGL

Bit 9: Enable the watchdog on a single channel in scan mode.

JAUTO

Bit 10: Automatic injected group conversion.

DISCEN

Bit 11: Discontinuous mode on regular channels.

JDISCEN

Bit 12: Discontinuous mode on injected channels.

DISCNUM

Bits 13-15: Discontinuous mode channel count.

JAWDEN

Bit 22: Analog watchdog enable on injected channels.

AWDEN

Bit 23: Analog watchdog enable on regular channels.

RES

Bits 24-25: Resolution.

OVRIE

Bit 26: Overrun interrupt enable.

CR2

control register 2

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWSTART
rw 		EXTEN
rw 		EXTSEL
rw 		JSWSTART
rw 		JEXTEN
rw 		JEXTSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALIGN
rw 		EOCS
rw 		DDS
rw 		DMA
rw 		CONT
rw 		ADON
rw
Toggle fields

ADON

Bit 0: A/D Converter ON / OFF.

CONT

Bit 1: Continuous conversion.

DMA

Bit 8: Direct memory access mode (for single ADC mode).

DDS

Bit 9: DMA disable selection (for single ADC mode).

EOCS

Bit 10: End of conversion selection.

ALIGN

Bit 11: Data alignment.

JEXTSEL

Bits 16-19: External event select for injected group.

JEXTEN

Bits 20-21: External trigger enable for injected channels.

JSWSTART

Bit 22: Start conversion of injected channels.

EXTSEL

Bits 24-27: External event select for regular group.

EXTEN

Bits 28-29: External trigger enable for regular channels.

SWSTART

Bit 30: Start conversion of regular channels.

SMPR1

sample time register 1

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMPx_x
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMPx_x
rw
Toggle fields

SMPx_x

Bits 0-31: Sample time bits.

SMPR2

sample time register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMPx_x
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMPx_x
rw
Toggle fields

SMPx_x

Bits 0-31: Sample time bits.

JOFR1

injected channel data offset register x

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JOFFSET1
rw
Toggle fields

JOFFSET1

Bits 0-11: Data offset for injected channel x.

JOFR2

injected channel data offset register x

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JOFFSET2
rw
Toggle fields

JOFFSET2

Bits 0-11: Data offset for injected channel x.

JOFR3

injected channel data offset register x

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JOFFSET3
rw
Toggle fields

JOFFSET3

Bits 0-11: Data offset for injected channel x.

JOFR4

injected channel data offset register x

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JOFFSET4
rw
Toggle fields

JOFFSET4

Bits 0-11: Data offset for injected channel x.

HTR

watchdog higher threshold register

Offset: 0x24, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HT
rw
Toggle fields

HT

Bits 0-11: Analog watchdog higher threshold.

LTR

watchdog lower threshold register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT
rw
Toggle fields

LT

Bits 0-11: Analog watchdog lower threshold.

SQR1

regular sequence register 1

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
L
rw 		SQ16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ16
rw 		SQ15
rw 		SQ14
rw 		SQ13
rw
Toggle fields

SQ13

Bits 0-4: 13th conversion in regular sequence.

SQ14

Bits 5-9: 14th conversion in regular sequence.

SQ15

Bits 10-14: 15th conversion in regular sequence.

SQ16

Bits 15-19: 16th conversion in regular sequence.

L

Bits 20-23: Regular channel sequence length.

SQR2

regular sequence register 2

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ12
rw 		SQ11
rw 		SQ10
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ10
rw 		SQ9
rw 		SQ8
rw 		SQ7
rw
Toggle fields

SQ7

Bits 0-4: 7th conversion in regular sequence.

SQ8

Bits 5-9: 8th conversion in regular sequence.

SQ9

Bits 10-14: 9th conversion in regular sequence.

SQ10

Bits 15-19: 10th conversion in regular sequence.

SQ11

Bits 20-24: 11th conversion in regular sequence.

SQ12

Bits 25-29: 12th conversion in regular sequence.

SQR3

regular sequence register 3

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ6
rw 		SQ5
rw 		SQ4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ4
rw 		SQ3
rw 		SQ2
rw 		SQ1
rw
Toggle fields

SQ1

Bits 0-4: 1st conversion in regular sequence.

SQ2

Bits 5-9: 2nd conversion in regular sequence.

SQ3

Bits 10-14: 3rd conversion in regular sequence.

SQ4

Bits 15-19: 4th conversion in regular sequence.

SQ5

Bits 20-24: 5th conversion in regular sequence.

SQ6

Bits 25-29: 6th conversion in regular sequence.

JSQR

injected sequence register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JL
rw 		JSQ4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JSQ4
rw 		JSQ3
rw 		JSQ2
rw 		JSQ1
rw
Toggle fields

JSQ1

Bits 0-4: 1st conversion in injected sequence.

JSQ2

Bits 5-9: 2nd conversion in injected sequence.

JSQ3

Bits 10-14: 3rd conversion in injected sequence.

JSQ4

Bits 15-19: 4th conversion in injected sequence.

JL

Bits 20-21: Injected sequence length.

JDR1

injected data register x

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: Injected data.

JDR2

injected data register x

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: Injected data.

JDR3

injected data register x

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: Injected data.

JDR4

injected data register x

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: Injected data.

DR

regular data register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
r
Toggle fields

DATA

Bits 0-15: Regular data.

C_ADC

0x40012300: Common ADC registers

20/27 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CSR
0x4 CCR
0x8 CDR
Toggle registers

CSR

ADC Common status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OVR3
r 		STRT3
r 		JSTRT3
r 		JEOC3
r 		EOC3
r 		AWD3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVR2
r 		STRT2
r 		JSTRT2
r 		JEOC2
r 		EOC2
r 		AWD2
r 		OVR1
r 		STRT1
r 		JSTRT1
r 		JEOC1
r 		EOC1
r 		AWD1
r
Toggle fields

AWD1

Bit 0: Analog watchdog flag of ADC 1.

EOC1

Bit 1: End of conversion of ADC 1.

JEOC1

Bit 2: Injected channel end of conversion of ADC 1.

JSTRT1

Bit 3: Injected channel Start flag of ADC 1.

STRT1

Bit 4: Regular channel Start flag of ADC 1.

OVR1

Bit 5: Overrun flag of ADC 1.

AWD2

Bit 8: Analog watchdog flag of ADC 2.

EOC2

Bit 9: End of conversion of ADC 2.

JEOC2

Bit 10: Injected channel end of conversion of ADC 2.

JSTRT2

Bit 11: Injected channel Start flag of ADC 2.

STRT2

Bit 12: Regular channel Start flag of ADC 2.

OVR2

Bit 13: Overrun flag of ADC 2.

AWD3

Bit 16: Analog watchdog flag of ADC 3.

EOC3

Bit 17: End of conversion of ADC 3.

JEOC3

Bit 18: Injected channel end of conversion of ADC 3.

JSTRT3

Bit 19: Injected channel Start flag of ADC 3.

STRT3

Bit 20: Regular channel Start flag of ADC 3.

OVR3

Bit 21: Overrun flag of ADC3.

CCR

ADC common control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSVREFE
rw 		VBATE
rw 		ADCPRE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMA
rw 		DDS
rw 		DELAY
rw 		MULT
rw
Toggle fields

MULT

Bits 0-4: Multi ADC mode selection.

DELAY

Bits 8-11: Delay between 2 sampling phases.

DDS

Bit 13: DMA disable selection for multi-ADC mode.

DMA

Bits 14-15: Direct memory access mode for multi ADC mode.

ADCPRE

Bits 16-17: ADC prescaler.

VBATE

Bit 22: VBAT enable.

TSVREFE

Bit 23: Temperature sensor and VREFINT enable.

CDR

ADC common regular data register for dual and triple modes

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA1
r
Toggle fields

DATA1

Bits 0-15: 1st data item of a pair of regular conversions.

DATA2

Bits 16-31: 2nd data item of a pair of regular conversions.

CAN1

0x40006400: Controller area network

50/2059 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MCR
0x4 MSR
0x8 TSR
0xc RF0R
0x10 RF1R
0x14 IER
0x18 ESR
0x1c BTR
0x180 TI0R
0x184 TDT0R
0x188 TDL0R
0x18c TDH0R
0x190 TI1R
0x194 TDT1R
0x198 TDL1R
0x19c TDH1R
0x1a0 TI2R
0x1a4 TDT2R
0x1a8 TDL2R
0x1ac TDH2R
0x1b0 RI0R
0x1b4 RDT0R
0x1b8 RDL0R
0x1bc RDH0R
0x1c0 RI1R
0x1c4 RDT1R
0x1c8 RDL1R
0x1cc RDH1R
0x200 FMR
0x204 FM1R
0x20c FS1R
0x214 FFA1R
0x21c FA1R
0x240 F0R1
0x244 F0R2
0x248 F1R1
0x24c F1R2
0x250 F2R1
0x254 F2R2
0x258 F3R1
0x25c F3R2
0x260 F4R1
0x264 F4R2
0x268 F5R1
0x26c F5R2
0x270 F6R1
0x274 F6R2
0x278 F7R1
0x27c F7R2
0x280 F8R1
0x284 F8R2
0x288 F9R1
0x28c F9R2
0x290 F10R1
0x294 F10R2
0x298 F11R1
0x29c F11R2
0x2a0 F12R1
0x2a4 F12R2
0x2a8 F13R1
0x2ac F13R2
0x2b0 F14R1
0x2b4 F14R2
0x2b8 F15R1
0x2bc F15R2
0x2c0 F16R1
0x2c4 F16R2
0x2c8 F17R1
0x2cc F17R2
0x2d0 F18R1
0x2d4 F18R2
0x2d8 F19R1
0x2dc F19R2
0x2e0 F20R1
0x2e4 F20R2
0x2e8 F21R1
0x2ec F21R2
0x2f0 F22R1
0x2f4 F22R2
0x2f8 F23R1
0x2fc F23R2
0x300 F24R1
0x304 F24R2
0x308 F25R1
0x30c F25R2
0x310 F26R1
0x314 F26R2
0x318 F27R1
0x31c F27R2
Toggle registers

MCR

master control register

Offset: 0x0, size: 32, reset: 0x00010002, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET
rw 		TTCM
rw 		ABOM
rw 		AWUM
rw 		NART
rw 		RFLM
rw 		TXFP
rw 		SLEEP
rw 		INRQ
rw
Toggle fields

INRQ

Bit 0: INRQ.

SLEEP

Bit 1: SLEEP.

TXFP

Bit 2: TXFP.

RFLM

Bit 3: RFLM.

NART

Bit 4: NART.

AWUM

Bit 5: AWUM.

ABOM

Bit 6: ABOM.

TTCM

Bit 7: TTCM.

RESET

Bit 15: RESET.

DBF

Bit 16: DBF.

MSR

master status register

Offset: 0x4, size: 32, reset: 0x00000C02, access: Unspecified

6/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX
r 		SAMP
r 		RXM
r 		TXM
r 		SLAKI
rw 		WKUI
rw 		ERRI
rw 		SLAK
r 		INAK
r
Toggle fields

INAK

Bit 0: INAK.

SLAK

Bit 1: SLAK.

ERRI

Bit 2: ERRI.

WKUI

Bit 3: WKUI.

SLAKI

Bit 4: SLAKI.

TXM

Bit 8: TXM.

RXM

Bit 9: RXM.

SAMP

Bit 10: SAMP.

RX

Bit 11: RX.

TSR

transmit status register

Offset: 0x8, size: 32, reset: 0x1C000000, access: Unspecified

7/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOW2
r 		LOW1
r 		LOW0
r 		TME2
r 		TME1
r 		TME0
r 		CODE
r 		ABRQ2
rw 		TERR2
rw 		ALST2
rw 		TXOK2
rw 		RQCP2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRQ1
rw 		TERR1
rw 		ALST1
rw 		TXOK1
rw 		RQCP1
rw 		ABRQ0
rw 		TERR0
rw 		ALST0
rw 		TXOK0
rw 		RQCP0
rw
Toggle fields

RQCP0

Bit 0: RQCP0.

TXOK0

Bit 1: TXOK0.

ALST0

Bit 2: ALST0.

TERR0

Bit 3: TERR0.

ABRQ0

Bit 7: ABRQ0.

RQCP1

Bit 8: RQCP1.

TXOK1

Bit 9: TXOK1.

ALST1

Bit 10: ALST1.

TERR1

Bit 11: TERR1.

ABRQ1

Bit 15: ABRQ1.

RQCP2

Bit 16: RQCP2.

TXOK2

Bit 17: TXOK2.

ALST2

Bit 18: ALST2.

TERR2

Bit 19: TERR2.

ABRQ2

Bit 23: ABRQ2.

CODE

Bits 24-25: CODE.

TME0

Bit 26: Lowest priority flag for mailbox 0.

TME1

Bit 27: Lowest priority flag for mailbox 1.

TME2

Bit 28: Lowest priority flag for mailbox 2.

LOW0

Bit 29: Lowest priority flag for mailbox 0.

LOW1

Bit 30: Lowest priority flag for mailbox 1.

LOW2

Bit 31: Lowest priority flag for mailbox 2.

RF0R

receive FIFO 0 register

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFOM0
rw 		FOVR0
rw 		FULL0
rw 		FMP0
r
Toggle fields

FMP0

Bits 0-1: FMP0.

FULL0

Bit 3: FULL0.

FOVR0

Bit 4: FOVR0.

RFOM0

Bit 5: RFOM0.

RF1R

receive FIFO 1 register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFOM1
rw 		FOVR1
rw 		FULL1
rw 		FMP1
r
Toggle fields

FMP1

Bits 0-1: FMP1.

FULL1

Bit 3: FULL1.

FOVR1

Bit 4: FOVR1.

RFOM1

Bit 5: RFOM1.

IER

interrupt enable register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLKIE
rw 		WKUIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRIE
rw 		LECIE
rw 		BOFIE
rw 		EPVIE
rw 		EWGIE
rw 		FOVIE1
rw 		FFIE1
rw 		FMPIE1
rw 		FOVIE0
rw 		FFIE0
rw 		FMPIE0
rw 		TMEIE
rw
Toggle fields

TMEIE

Bit 0: TMEIE.

FMPIE0

Bit 1: FMPIE0.

FFIE0

Bit 2: FFIE0.

FOVIE0

Bit 3: FOVIE0.

FMPIE1

Bit 4: FMPIE1.

FFIE1

Bit 5: FFIE1.

FOVIE1

Bit 6: FOVIE1.

EWGIE

Bit 8: EWGIE.

EPVIE

Bit 9: EPVIE.

BOFIE

Bit 10: BOFIE.

LECIE

Bit 11: LECIE.

ERRIE

Bit 15: ERRIE.

WKUIE

Bit 16: WKUIE.

SLKIE

Bit 17: SLKIE.

ESR

interrupt enable register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

5/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REC
r 		TEC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LEC
rw 		BOFF
r 		EPVF
r 		EWGF
r
Toggle fields

EWGF

Bit 0: EWGF.

EPVF

Bit 1: EPVF.

BOFF

Bit 2: BOFF.

LEC

Bits 4-6: LEC.

TEC

Bits 16-23: TEC.

REC

Bits 24-31: REC.

BTR

bit timing register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SILM
rw 		LBKM
rw 		SJW
rw 		TS2
rw 		TS1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRP
rw
Toggle fields

BRP

Bits 0-9: BRP.

TS1

Bits 16-19: TS1.

TS2

Bits 20-22: TS2.

SJW

Bits 24-25: SJW.

LBKM

Bit 30: LBKM.

SILM

Bit 31: SILM.

TI0R

TX mailbox identifier register

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STID
rw 		EXID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXID
rw 		IDE
rw 		RTR
rw 		TXRQ
rw
Toggle fields

TXRQ

Bit 0: TXRQ.

RTR

Bit 1: RTR.

IDE

Bit 2: IDE.

EXID

Bits 3-20: EXID.

STID

Bits 21-31: STID.

TDT0R

mailbox data length control and time stamp register

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TGT
rw 		DLC
rw
Toggle fields

DLC

Bits 0-3: DLC.

TGT

Bit 8: TGT.

TIME

Bits 16-31: TIME.

TDL0R

mailbox data low register

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA3
rw 		DATA2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA1
rw 		DATA0
rw
Toggle fields

DATA0

Bits 0-7: DATA0.

DATA1

Bits 8-15: DATA1.

DATA2

Bits 16-23: DATA2.

DATA3

Bits 24-31: DATA3.

TDH0R

mailbox data high register

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA7
rw 		DATA6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA5
rw 		DATA4
rw
Toggle fields

DATA4

Bits 0-7: DATA4.

DATA5

Bits 8-15: DATA5.

DATA6

Bits 16-23: DATA6.

DATA7

Bits 24-31: DATA7.

TI1R

mailbox identifier register

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STID
rw 		EXID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXID
rw 		IDE
rw 		RTR
rw 		TXRQ
rw
Toggle fields

TXRQ

Bit 0: TXRQ.

RTR

Bit 1: RTR.

IDE

Bit 2: IDE.

EXID

Bits 3-20: EXID.

STID

Bits 21-31: STID.

TDT1R

mailbox data length control and time stamp register

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TGT
rw 		DLC
rw
Toggle fields

DLC

Bits 0-3: DLC.

TGT

Bit 8: TGT.

TIME

Bits 16-31: TIME.

TDL1R

mailbox data low register

Offset: 0x198, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA3
rw 		DATA2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA1
rw 		DATA0
rw
Toggle fields

DATA0

Bits 0-7: DATA0.

DATA1

Bits 8-15: DATA1.

DATA2

Bits 16-23: DATA2.

DATA3

Bits 24-31: DATA3.

TDH1R

mailbox data high register

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA7
rw 		DATA6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA5
rw 		DATA4
rw
Toggle fields

DATA4

Bits 0-7: DATA4.

DATA5

Bits 8-15: DATA5.

DATA6

Bits 16-23: DATA6.

DATA7

Bits 24-31: DATA7.

TI2R

mailbox identifier register

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STID
rw 		EXID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXID
rw 		IDE
rw 		RTR
rw 		TXRQ
rw
Toggle fields

TXRQ

Bit 0: TXRQ.

RTR

Bit 1: RTR.

IDE

Bit 2: IDE.

EXID

Bits 3-20: EXID.

STID

Bits 21-31: STID.

TDT2R

mailbox data length control and time stamp register

Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TGT
rw 		DLC
rw
Toggle fields

DLC

Bits 0-3: DLC.

TGT

Bit 8: TGT.

TIME

Bits 16-31: TIME.

TDL2R

mailbox data low register

Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA3
rw 		DATA2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA1
rw 		DATA0
rw
Toggle fields

DATA0

Bits 0-7: DATA0.

DATA1

Bits 8-15: DATA1.

DATA2

Bits 16-23: DATA2.

DATA3

Bits 24-31: DATA3.

TDH2R

mailbox data high register

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA7
rw 		DATA6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA5
rw 		DATA4
rw
Toggle fields

DATA4

Bits 0-7: DATA4.

DATA5

Bits 8-15: DATA5.

DATA6

Bits 16-23: DATA6.

DATA7

Bits 24-31: DATA7.

RI0R

receive FIFO mailbox identifier register

Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STID
r 		EXID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXID
r 		IDE
r 		RTR
r
Toggle fields

RTR

Bit 1: RTR.

IDE

Bit 2: IDE.

EXID

Bits 3-20: EXID.

STID

Bits 21-31: STID.

RDT0R

mailbox data high register

Offset: 0x1b4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIME
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMI
r 		DLC
r
Toggle fields

DLC

Bits 0-3: DLC.

FMI

Bits 8-15: FMI.

TIME

Bits 16-31: TIME.

RDL0R

mailbox data high register

Offset: 0x1b8, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA3
r 		DATA2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA1
r 		DATA0
r
Toggle fields

DATA0

Bits 0-7: DATA0.

DATA1

Bits 8-15: DATA1.

DATA2

Bits 16-23: DATA2.

DATA3

Bits 24-31: DATA3.

RDH0R

receive FIFO mailbox data high register

Offset: 0x1bc, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA7
r 		DATA6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA5
r 		DATA4
r
Toggle fields

DATA4

Bits 0-7: DATA4.

DATA5

Bits 8-15: DATA5.

DATA6

Bits 16-23: DATA6.

DATA7

Bits 24-31: DATA7.

RI1R

mailbox data high register

Offset: 0x1c0, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STID
r 		EXID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXID
r 		IDE
r 		RTR
r
Toggle fields

RTR

Bit 1: RTR.

IDE

Bit 2: IDE.

EXID

Bits 3-20: EXID.

STID

Bits 21-31: STID.

RDT1R

mailbox data high register

Offset: 0x1c4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIME
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMI
r 		DLC
r
Toggle fields

DLC

Bits 0-3: DLC.

FMI

Bits 8-15: FMI.

TIME

Bits 16-31: TIME.

RDL1R

mailbox data high register

Offset: 0x1c8, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA3
r 		DATA2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA1
r 		DATA0
r
Toggle fields

DATA0

Bits 0-7: DATA0.

DATA1

Bits 8-15: DATA1.

DATA2

Bits 16-23: DATA2.

DATA3

Bits 24-31: DATA3.

RDH1R

mailbox data high register

Offset: 0x1cc, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA7
r 		DATA6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA5
r 		DATA4
r
Toggle fields

DATA4

Bits 0-7: DATA4.

DATA5

Bits 8-15: DATA5.

DATA6

Bits 16-23: DATA6.

DATA7

Bits 24-31: DATA7.

FMR

filter master register

Offset: 0x200, size: 32, reset: 0x2A1C0E01, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAN2SB
rw 		FINIT
rw
Toggle fields

FINIT

Bit 0: FINIT.

CAN2SB

Bits 8-13: CAN2SB.

FM1R

filter mode register

Offset: 0x204, size: 32, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FBM27
rw 		FBM26
rw 		FBM25
rw 		FBM24
rw 		FBM23
rw 		FBM22
rw 		FBM21
rw 		FBM20
rw 		FBM19
rw 		FBM18
rw 		FBM17
rw 		FBM16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FBM15
rw 		FBM14
rw 		FBM13
rw 		FBM12
rw 		FBM11
rw 		FBM10
rw 		FBM9
rw 		FBM8
rw 		FBM7
rw 		FBM6
rw 		FBM5
rw 		FBM4
rw 		FBM3
rw 		FBM2
rw 		FBM1
rw 		FBM0
rw
Toggle fields

FBM0

Bit 0: Filter mode.

FBM1

Bit 1: Filter mode.

FBM2

Bit 2: Filter mode.

FBM3

Bit 3: Filter mode.

FBM4

Bit 4: Filter mode.

FBM5

Bit 5: Filter mode.

FBM6

Bit 6: Filter mode.

FBM7

Bit 7: Filter mode.

FBM8

Bit 8: Filter mode.

FBM9

Bit 9: Filter mode.

FBM10

Bit 10: Filter mode.

FBM11

Bit 11: Filter mode.

FBM12

Bit 12: Filter mode.

FBM13

Bit 13: Filter mode.

FBM14

Bit 14: Filter mode.

FBM15

Bit 15: Filter mode.

FBM16

Bit 16: Filter mode.

FBM17

Bit 17: Filter mode.

FBM18

Bit 18: Filter mode.

FBM19

Bit 19: Filter mode.

FBM20

Bit 20: Filter mode.

FBM21

Bit 21: Filter mode.

FBM22

Bit 22: Filter mode.

FBM23

Bit 23: Filter mode.

FBM24

Bit 24: Filter mode.

FBM25

Bit 25: Filter mode.

FBM26

Bit 26: Filter mode.

FBM27

Bit 27: Filter mode.

FS1R

filter scale register

Offset: 0x20c, size: 32, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSC27
rw 		FSC26
rw 		FSC25
rw 		FSC24
rw 		FSC23
rw 		FSC22
rw 		FSC21
rw 		FSC20
rw 		FSC19
rw 		FSC18
rw 		FSC17
rw 		FSC16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSC15
rw 		FSC14
rw 		FSC13
rw 		FSC12
rw 		FSC11
rw 		FSC10
rw 		FSC9
rw 		FSC8
rw 		FSC7
rw 		FSC6
rw 		FSC5
rw 		FSC4
rw 		FSC3
rw 		FSC2
rw 		FSC1
rw 		FSC0
rw
Toggle fields

FSC0

Bit 0: Filter scale configuration.

FSC1

Bit 1: Filter scale configuration.

FSC2

Bit 2: Filter scale configuration.

FSC3

Bit 3: Filter scale configuration.

FSC4

Bit 4: Filter scale configuration.

FSC5

Bit 5: Filter scale configuration.

FSC6

Bit 6: Filter scale configuration.

FSC7

Bit 7: Filter scale configuration.

FSC8

Bit 8: Filter scale configuration.

FSC9

Bit 9: Filter scale configuration.

FSC10

Bit 10: Filter scale configuration.

FSC11

Bit 11: Filter scale configuration.

FSC12

Bit 12: Filter scale configuration.

FSC13

Bit 13: Filter scale configuration.

FSC14

Bit 14: Filter scale configuration.

FSC15

Bit 15: Filter scale configuration.

FSC16

Bit 16: Filter scale configuration.

FSC17

Bit 17: Filter scale configuration.

FSC18

Bit 18: Filter scale configuration.

FSC19

Bit 19: Filter scale configuration.

FSC20

Bit 20: Filter scale configuration.

FSC21

Bit 21: Filter scale configuration.

FSC22

Bit 22: Filter scale configuration.

FSC23

Bit 23: Filter scale configuration.

FSC24

Bit 24: Filter scale configuration.

FSC25

Bit 25: Filter scale configuration.

FSC26

Bit 26: Filter scale configuration.

FSC27

Bit 27: Filter scale configuration.

FFA1R

filter FIFO assignment register

Offset: 0x214, size: 32, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FFA27
rw 		FFA26
rw 		FFA25
rw 		FFA24
rw 		FFA23
rw 		FFA22
rw 		FFA21
rw 		FFA20
rw 		FFA19
rw 		FFA18
rw 		FFA17
rw 		FFA16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FFA15
rw 		FFA14
rw 		FFA13
rw 		FFA12
rw 		FFA11
rw 		FFA10
rw 		FFA9
rw 		FFA8
rw 		FFA7
rw 		FFA6
rw 		FFA5
rw 		FFA4
rw 		FFA3
rw 		FFA2
rw 		FFA1
rw 		FFA0
rw
Toggle fields

FFA0

Bit 0: Filter FIFO assignment for filter 0.

FFA1

Bit 1: Filter FIFO assignment for filter 1.

FFA2

Bit 2: Filter FIFO assignment for filter 2.

FFA3

Bit 3: Filter FIFO assignment for filter 3.

FFA4

Bit 4: Filter FIFO assignment for filter 4.

FFA5

Bit 5: Filter FIFO assignment for filter 5.

FFA6

Bit 6: Filter FIFO assignment for filter 6.

FFA7

Bit 7: Filter FIFO assignment for filter 7.

FFA8

Bit 8: Filter FIFO assignment for filter 8.

FFA9

Bit 9: Filter FIFO assignment for filter 9.

FFA10

Bit 10: Filter FIFO assignment for filter 10.

FFA11

Bit 11: Filter FIFO assignment for filter 11.

FFA12

Bit 12: Filter FIFO assignment for filter 12.

FFA13

Bit 13: Filter FIFO assignment for filter 13.

FFA14

Bit 14: Filter FIFO assignment for filter 14.

FFA15

Bit 15: Filter FIFO assignment for filter 15.

FFA16

Bit 16: Filter FIFO assignment for filter 16.

FFA17

Bit 17: Filter FIFO assignment for filter 17.

FFA18

Bit 18: Filter FIFO assignment for filter 18.

FFA19

Bit 19: Filter FIFO assignment for filter 19.

FFA20

Bit 20: Filter FIFO assignment for filter 20.

FFA21

Bit 21: Filter FIFO assignment for filter 21.

FFA22

Bit 22: Filter FIFO assignment for filter 22.

FFA23

Bit 23: Filter FIFO assignment for filter 23.

FFA24

Bit 24: Filter FIFO assignment for filter 24.

FFA25

Bit 25: Filter FIFO assignment for filter 25.

FFA26

Bit 26: Filter FIFO assignment for filter 26.

FFA27

Bit 27: Filter FIFO assignment for filter 27.

FA1R

filter activation register

Offset: 0x21c, size: 32, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FACT27
rw 		FACT26
rw 		FACT25
rw 		FACT24
rw 		FACT23
rw 		FACT22
rw 		FACT21
rw 		FACT20
rw 		FACT19
rw 		FACT18
rw 		FACT17
rw 		FACT16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FACT15
rw 		FACT14
rw 		FACT13
rw 		FACT12
rw 		FACT11
rw 		FACT10
rw 		FACT9
rw 		FACT8
rw 		FACT7
rw 		FACT6
rw 		FACT5
rw 		FACT4
rw 		FACT3
rw 		FACT2
rw 		FACT1
rw 		FACT0
rw
Toggle fields

FACT0

Bit 0: Filter active.

FACT1

Bit 1: Filter active.

FACT2

Bit 2: Filter active.

FACT3

Bit 3: Filter active.

FACT4

Bit 4: Filter active.

FACT5

Bit 5: Filter active.

FACT6

Bit 6: Filter active.

FACT7

Bit 7: Filter active.

FACT8

Bit 8: Filter active.

FACT9

Bit 9: Filter active.

FACT10

Bit 10: Filter active.

FACT11

Bit 11: Filter active.

FACT12

Bit 12: Filter active.

FACT13

Bit 13: Filter active.

FACT14

Bit 14: Filter active.

FACT15

Bit 15: Filter active.

FACT16

Bit 16: Filter active.

FACT17

Bit 17: Filter active.

FACT18

Bit 18: Filter active.

FACT19

Bit 19: Filter active.

FACT20

Bit 20: Filter active.

FACT21

Bit 21: Filter active.

FACT22

Bit 22: Filter active.

FACT23

Bit 23: Filter active.

FACT24

Bit 24: Filter active.

FACT25

Bit 25: Filter active.

FACT26

Bit 26: Filter active.

FACT27

Bit 27: Filter active.

F0R1

Filter bank 0 register 1

Offset: 0x240, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F0R2

Filter bank 0 register 2

Offset: 0x244, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F1R1

Filter bank 1 register 1

Offset: 0x248, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F1R2

Filter bank 1 register 2

Offset: 0x24c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F2R1

Filter bank 2 register 1

Offset: 0x250, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F2R2

Filter bank 2 register 2

Offset: 0x254, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F3R1

Filter bank 3 register 1

Offset: 0x258, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F3R2

Filter bank 3 register 2

Offset: 0x25c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F4R1

Filter bank 4 register 1

Offset: 0x260, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F4R2

Filter bank 4 register 2

Offset: 0x264, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F5R1

Filter bank 5 register 1

Offset: 0x268, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F5R2

Filter bank 5 register 2

Offset: 0x26c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F6R1

Filter bank 6 register 1

Offset: 0x270, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F6R2

Filter bank 6 register 2

Offset: 0x274, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F7R1

Filter bank 7 register 1

Offset: 0x278, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F7R2

Filter bank 7 register 2

Offset: 0x27c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F8R1

Filter bank 8 register 1

Offset: 0x280, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F8R2

Filter bank 8 register 2

Offset: 0x284, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F9R1

Filter bank 9 register 1

Offset: 0x288, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F9R2

Filter bank 9 register 2

Offset: 0x28c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F10R1

Filter bank 10 register 1

Offset: 0x290, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F10R2

Filter bank 10 register 2

Offset: 0x294, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F11R1

Filter bank 11 register 1

Offset: 0x298, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F11R2

Filter bank 11 register 2

Offset: 0x29c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F12R1

Filter bank 4 register 1

Offset: 0x2a0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F12R2

Filter bank 12 register 2

Offset: 0x2a4, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F13R1

Filter bank 13 register 1

Offset: 0x2a8, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F13R2

Filter bank 13 register 2

Offset: 0x2ac, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F14R1

Filter bank 14 register 1

Offset: 0x2b0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F14R2

Filter bank 14 register 2

Offset: 0x2b4, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F15R1

Filter bank 15 register 1

Offset: 0x2b8, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F15R2

Filter bank 15 register 2

Offset: 0x2bc, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F16R1

Filter bank 16 register 1

Offset: 0x2c0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F16R2

Filter bank 16 register 2

Offset: 0x2c4, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F17R1

Filter bank 17 register 1

Offset: 0x2c8, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F17R2

Filter bank 17 register 2

Offset: 0x2cc, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F18R1

Filter bank 18 register 1

Offset: 0x2d0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F18R2

Filter bank 18 register 2

Offset: 0x2d4, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F19R1

Filter bank 19 register 1

Offset: 0x2d8, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F19R2

Filter bank 19 register 2

Offset: 0x2dc, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F20R1

Filter bank 20 register 1

Offset: 0x2e0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F20R2

Filter bank 20 register 2

Offset: 0x2e4, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F21R1

Filter bank 21 register 1

Offset: 0x2e8, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F21R2

Filter bank 21 register 2

Offset: 0x2ec, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F22R1

Filter bank 22 register 1

Offset: 0x2f0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F22R2

Filter bank 22 register 2

Offset: 0x2f4, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F23R1

Filter bank 23 register 1

Offset: 0x2f8, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F23R2

Filter bank 23 register 2

Offset: 0x2fc, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F24R1

Filter bank 24 register 1

Offset: 0x300, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F24R2

Filter bank 24 register 2

Offset: 0x304, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F25R1

Filter bank 25 register 1

Offset: 0x308, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F25R2

Filter bank 25 register 2

Offset: 0x30c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F26R1

Filter bank 26 register 1

Offset: 0x310, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F26R2

Filter bank 26 register 2

Offset: 0x314, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F27R1

Filter bank 27 register 1

Offset: 0x318, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F27R2

Filter bank 27 register 2

Offset: 0x31c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

CAN2

0x40006800: Controller area network

50/2059 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MCR
0x4 MSR
0x8 TSR
0xc RF0R
0x10 RF1R
0x14 IER
0x18 ESR
0x1c BTR
0x180 TI0R
0x184 TDT0R
0x188 TDL0R
0x18c TDH0R
0x190 TI1R
0x194 TDT1R
0x198 TDL1R
0x19c TDH1R
0x1a0 TI2R
0x1a4 TDT2R
0x1a8 TDL2R
0x1ac TDH2R
0x1b0 RI0R
0x1b4 RDT0R
0x1b8 RDL0R
0x1bc RDH0R
0x1c0 RI1R
0x1c4 RDT1R
0x1c8 RDL1R
0x1cc RDH1R
0x200 FMR
0x204 FM1R
0x20c FS1R
0x214 FFA1R
0x21c FA1R
0x240 F0R1
0x244 F0R2
0x248 F1R1
0x24c F1R2
0x250 F2R1
0x254 F2R2
0x258 F3R1
0x25c F3R2
0x260 F4R1
0x264 F4R2
0x268 F5R1
0x26c F5R2
0x270 F6R1
0x274 F6R2
0x278 F7R1
0x27c F7R2
0x280 F8R1
0x284 F8R2
0x288 F9R1
0x28c F9R2
0x290 F10R1
0x294 F10R2
0x298 F11R1
0x29c F11R2
0x2a0 F12R1
0x2a4 F12R2
0x2a8 F13R1
0x2ac F13R2
0x2b0 F14R1
0x2b4 F14R2
0x2b8 F15R1
0x2bc F15R2
0x2c0 F16R1
0x2c4 F16R2
0x2c8 F17R1
0x2cc F17R2
0x2d0 F18R1
0x2d4 F18R2
0x2d8 F19R1
0x2dc F19R2
0x2e0 F20R1
0x2e4 F20R2
0x2e8 F21R1
0x2ec F21R2
0x2f0 F22R1
0x2f4 F22R2
0x2f8 F23R1
0x2fc F23R2
0x300 F24R1
0x304 F24R2
0x308 F25R1
0x30c F25R2
0x310 F26R1
0x314 F26R2
0x318 F27R1
0x31c F27R2
Toggle registers

MCR

master control register

Offset: 0x0, size: 32, reset: 0x00010002, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET
rw 		TTCM
rw 		ABOM
rw 		AWUM
rw 		NART
rw 		RFLM
rw 		TXFP
rw 		SLEEP
rw 		INRQ
rw
Toggle fields

INRQ

Bit 0: INRQ.

SLEEP

Bit 1: SLEEP.

TXFP

Bit 2: TXFP.

RFLM

Bit 3: RFLM.

NART

Bit 4: NART.

AWUM

Bit 5: AWUM.

ABOM

Bit 6: ABOM.

TTCM

Bit 7: TTCM.

RESET

Bit 15: RESET.

DBF

Bit 16: DBF.

MSR

master status register

Offset: 0x4, size: 32, reset: 0x00000C02, access: Unspecified

6/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX
r 		SAMP
r 		RXM
r 		TXM
r 		SLAKI
rw 		WKUI
rw 		ERRI
rw 		SLAK
r 		INAK
r
Toggle fields

INAK

Bit 0: INAK.

SLAK

Bit 1: SLAK.

ERRI

Bit 2: ERRI.

WKUI

Bit 3: WKUI.

SLAKI

Bit 4: SLAKI.

TXM

Bit 8: TXM.

RXM

Bit 9: RXM.

SAMP

Bit 10: SAMP.

RX

Bit 11: RX.

TSR

transmit status register

Offset: 0x8, size: 32, reset: 0x1C000000, access: Unspecified

7/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOW2
r 		LOW1
r 		LOW0
r 		TME2
r 		TME1
r 		TME0
r 		CODE
r 		ABRQ2
rw 		TERR2
rw 		ALST2
rw 		TXOK2
rw 		RQCP2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRQ1
rw 		TERR1
rw 		ALST1
rw 		TXOK1
rw 		RQCP1
rw 		ABRQ0
rw 		TERR0
rw 		ALST0
rw 		TXOK0
rw 		RQCP0
rw
Toggle fields

RQCP0

Bit 0: RQCP0.

TXOK0

Bit 1: TXOK0.

ALST0

Bit 2: ALST0.

TERR0

Bit 3: TERR0.

ABRQ0

Bit 7: ABRQ0.

RQCP1

Bit 8: RQCP1.

TXOK1

Bit 9: TXOK1.

ALST1

Bit 10: ALST1.

TERR1

Bit 11: TERR1.

ABRQ1

Bit 15: ABRQ1.

RQCP2

Bit 16: RQCP2.

TXOK2

Bit 17: TXOK2.

ALST2

Bit 18: ALST2.

TERR2

Bit 19: TERR2.

ABRQ2

Bit 23: ABRQ2.

CODE

Bits 24-25: CODE.

TME0

Bit 26: Lowest priority flag for mailbox 0.

TME1

Bit 27: Lowest priority flag for mailbox 1.

TME2

Bit 28: Lowest priority flag for mailbox 2.

LOW0

Bit 29: Lowest priority flag for mailbox 0.

LOW1

Bit 30: Lowest priority flag for mailbox 1.

LOW2

Bit 31: Lowest priority flag for mailbox 2.

RF0R

receive FIFO 0 register

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFOM0
rw 		FOVR0
rw 		FULL0
rw 		FMP0
r
Toggle fields

FMP0

Bits 0-1: FMP0.

FULL0

Bit 3: FULL0.

FOVR0

Bit 4: FOVR0.

RFOM0

Bit 5: RFOM0.

RF1R

receive FIFO 1 register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFOM1
rw 		FOVR1
rw 		FULL1
rw 		FMP1
r
Toggle fields

FMP1

Bits 0-1: FMP1.

FULL1

Bit 3: FULL1.

FOVR1

Bit 4: FOVR1.

RFOM1

Bit 5: RFOM1.

IER

interrupt enable register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLKIE
rw 		WKUIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRIE
rw 		LECIE
rw 		BOFIE
rw 		EPVIE
rw 		EWGIE
rw 		FOVIE1
rw 		FFIE1
rw 		FMPIE1
rw 		FOVIE0
rw 		FFIE0
rw 		FMPIE0
rw 		TMEIE
rw
Toggle fields

TMEIE

Bit 0: TMEIE.

FMPIE0

Bit 1: FMPIE0.

FFIE0

Bit 2: FFIE0.

FOVIE0

Bit 3: FOVIE0.

FMPIE1

Bit 4: FMPIE1.

FFIE1

Bit 5: FFIE1.

FOVIE1

Bit 6: FOVIE1.

EWGIE

Bit 8: EWGIE.

EPVIE

Bit 9: EPVIE.

BOFIE

Bit 10: BOFIE.

LECIE

Bit 11: LECIE.

ERRIE

Bit 15: ERRIE.

WKUIE

Bit 16: WKUIE.

SLKIE

Bit 17: SLKIE.

ESR

interrupt enable register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

5/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REC
r 		TEC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LEC
rw 		BOFF
r 		EPVF
r 		EWGF
r
Toggle fields

EWGF

Bit 0: EWGF.

EPVF

Bit 1: EPVF.

BOFF

Bit 2: BOFF.

LEC

Bits 4-6: LEC.

TEC

Bits 16-23: TEC.

REC

Bits 24-31: REC.

BTR

bit timing register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SILM
rw 		LBKM
rw 		SJW
rw 		TS2
rw 		TS1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRP
rw
Toggle fields

BRP

Bits 0-9: BRP.

TS1

Bits 16-19: TS1.

TS2

Bits 20-22: TS2.

SJW

Bits 24-25: SJW.

LBKM

Bit 30: LBKM.

SILM

Bit 31: SILM.

TI0R

TX mailbox identifier register

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STID
rw 		EXID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXID
rw 		IDE
rw 		RTR
rw 		TXRQ
rw
Toggle fields

TXRQ

Bit 0: TXRQ.

RTR

Bit 1: RTR.

IDE

Bit 2: IDE.

EXID

Bits 3-20: EXID.

STID

Bits 21-31: STID.

TDT0R

mailbox data length control and time stamp register

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TGT
rw 		DLC
rw
Toggle fields

DLC

Bits 0-3: DLC.

TGT

Bit 8: TGT.

TIME

Bits 16-31: TIME.

TDL0R

mailbox data low register

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA3
rw 		DATA2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA1
rw 		DATA0
rw
Toggle fields

DATA0

Bits 0-7: DATA0.

DATA1

Bits 8-15: DATA1.

DATA2

Bits 16-23: DATA2.

DATA3

Bits 24-31: DATA3.

TDH0R

mailbox data high register

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA7
rw 		DATA6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA5
rw 		DATA4
rw
Toggle fields

DATA4

Bits 0-7: DATA4.

DATA5

Bits 8-15: DATA5.

DATA6

Bits 16-23: DATA6.

DATA7

Bits 24-31: DATA7.

TI1R

mailbox identifier register

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STID
rw 		EXID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXID
rw 		IDE
rw 		RTR
rw 		TXRQ
rw
Toggle fields

TXRQ

Bit 0: TXRQ.

RTR

Bit 1: RTR.

IDE

Bit 2: IDE.

EXID

Bits 3-20: EXID.

STID

Bits 21-31: STID.

TDT1R

mailbox data length control and time stamp register

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TGT
rw 		DLC
rw
Toggle fields

DLC

Bits 0-3: DLC.

TGT

Bit 8: TGT.

TIME

Bits 16-31: TIME.

TDL1R

mailbox data low register

Offset: 0x198, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA3
rw 		DATA2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA1
rw 		DATA0
rw
Toggle fields

DATA0

Bits 0-7: DATA0.

DATA1

Bits 8-15: DATA1.

DATA2

Bits 16-23: DATA2.

DATA3

Bits 24-31: DATA3.

TDH1R

mailbox data high register

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA7
rw 		DATA6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA5
rw 		DATA4
rw
Toggle fields

DATA4

Bits 0-7: DATA4.

DATA5

Bits 8-15: DATA5.

DATA6

Bits 16-23: DATA6.

DATA7

Bits 24-31: DATA7.

TI2R

mailbox identifier register

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STID
rw 		EXID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXID
rw 		IDE
rw 		RTR
rw 		TXRQ
rw
Toggle fields

TXRQ

Bit 0: TXRQ.

RTR

Bit 1: RTR.

IDE

Bit 2: IDE.

EXID

Bits 3-20: EXID.

STID

Bits 21-31: STID.

TDT2R

mailbox data length control and time stamp register

Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TGT
rw 		DLC
rw
Toggle fields

DLC

Bits 0-3: DLC.

TGT

Bit 8: TGT.

TIME

Bits 16-31: TIME.

TDL2R

mailbox data low register

Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA3
rw 		DATA2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA1
rw 		DATA0
rw
Toggle fields

DATA0

Bits 0-7: DATA0.

DATA1

Bits 8-15: DATA1.

DATA2

Bits 16-23: DATA2.

DATA3

Bits 24-31: DATA3.

TDH2R

mailbox data high register

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA7
rw 		DATA6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA5
rw 		DATA4
rw
Toggle fields

DATA4

Bits 0-7: DATA4.

DATA5

Bits 8-15: DATA5.

DATA6

Bits 16-23: DATA6.

DATA7

Bits 24-31: DATA7.

RI0R

receive FIFO mailbox identifier register

Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STID
r 		EXID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXID
r 		IDE
r 		RTR
r
Toggle fields

RTR

Bit 1: RTR.

IDE

Bit 2: IDE.

EXID

Bits 3-20: EXID.

STID

Bits 21-31: STID.

RDT0R

mailbox data high register

Offset: 0x1b4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIME
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMI
r 		DLC
r
Toggle fields

DLC

Bits 0-3: DLC.

FMI

Bits 8-15: FMI.

TIME

Bits 16-31: TIME.

RDL0R

mailbox data high register

Offset: 0x1b8, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA3
r 		DATA2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA1
r 		DATA0
r
Toggle fields

DATA0

Bits 0-7: DATA0.

DATA1

Bits 8-15: DATA1.

DATA2

Bits 16-23: DATA2.

DATA3

Bits 24-31: DATA3.

RDH0R

receive FIFO mailbox data high register

Offset: 0x1bc, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA7
r 		DATA6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA5
r 		DATA4
r
Toggle fields

DATA4

Bits 0-7: DATA4.

DATA5

Bits 8-15: DATA5.

DATA6

Bits 16-23: DATA6.

DATA7

Bits 24-31: DATA7.

RI1R

mailbox data high register

Offset: 0x1c0, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STID
r 		EXID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXID
r 		IDE
r 		RTR
r
Toggle fields

RTR

Bit 1: RTR.

IDE

Bit 2: IDE.

EXID

Bits 3-20: EXID.

STID

Bits 21-31: STID.

RDT1R

mailbox data high register

Offset: 0x1c4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIME
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMI
r 		DLC
r
Toggle fields

DLC

Bits 0-3: DLC.

FMI

Bits 8-15: FMI.

TIME

Bits 16-31: TIME.

RDL1R

mailbox data high register

Offset: 0x1c8, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA3
r 		DATA2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA1
r 		DATA0
r
Toggle fields

DATA0

Bits 0-7: DATA0.

DATA1

Bits 8-15: DATA1.

DATA2

Bits 16-23: DATA2.

DATA3

Bits 24-31: DATA3.

RDH1R

mailbox data high register

Offset: 0x1cc, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA7
r 		DATA6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA5
r 		DATA4
r
Toggle fields

DATA4

Bits 0-7: DATA4.

DATA5

Bits 8-15: DATA5.

DATA6

Bits 16-23: DATA6.

DATA7

Bits 24-31: DATA7.

FMR

filter master register

Offset: 0x200, size: 32, reset: 0x2A1C0E01, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAN2SB
rw 		FINIT
rw
Toggle fields

FINIT

Bit 0: FINIT.

CAN2SB

Bits 8-13: CAN2SB.

FM1R

filter mode register

Offset: 0x204, size: 32, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FBM27
rw 		FBM26
rw 		FBM25
rw 		FBM24
rw 		FBM23
rw 		FBM22
rw 		FBM21
rw 		FBM20
rw 		FBM19
rw 		FBM18
rw 		FBM17
rw 		FBM16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FBM15
rw 		FBM14
rw 		FBM13
rw 		FBM12
rw 		FBM11
rw 		FBM10
rw 		FBM9
rw 		FBM8
rw 		FBM7
rw 		FBM6
rw 		FBM5
rw 		FBM4
rw 		FBM3
rw 		FBM2
rw 		FBM1
rw 		FBM0
rw
Toggle fields

FBM0

Bit 0: Filter mode.

FBM1

Bit 1: Filter mode.

FBM2

Bit 2: Filter mode.

FBM3

Bit 3: Filter mode.

FBM4

Bit 4: Filter mode.

FBM5

Bit 5: Filter mode.

FBM6

Bit 6: Filter mode.

FBM7

Bit 7: Filter mode.

FBM8

Bit 8: Filter mode.

FBM9

Bit 9: Filter mode.

FBM10

Bit 10: Filter mode.

FBM11

Bit 11: Filter mode.

FBM12

Bit 12: Filter mode.

FBM13

Bit 13: Filter mode.

FBM14

Bit 14: Filter mode.

FBM15

Bit 15: Filter mode.

FBM16

Bit 16: Filter mode.

FBM17

Bit 17: Filter mode.

FBM18

Bit 18: Filter mode.

FBM19

Bit 19: Filter mode.

FBM20

Bit 20: Filter mode.

FBM21

Bit 21: Filter mode.

FBM22

Bit 22: Filter mode.

FBM23

Bit 23: Filter mode.

FBM24

Bit 24: Filter mode.

FBM25

Bit 25: Filter mode.

FBM26

Bit 26: Filter mode.

FBM27

Bit 27: Filter mode.

FS1R

filter scale register

Offset: 0x20c, size: 32, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSC27
rw 		FSC26
rw 		FSC25
rw 		FSC24
rw 		FSC23
rw 		FSC22
rw 		FSC21
rw 		FSC20
rw 		FSC19
rw 		FSC18
rw 		FSC17
rw 		FSC16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSC15
rw 		FSC14
rw 		FSC13
rw 		FSC12
rw 		FSC11
rw 		FSC10
rw 		FSC9
rw 		FSC8
rw 		FSC7
rw 		FSC6
rw 		FSC5
rw 		FSC4
rw 		FSC3
rw 		FSC2
rw 		FSC1
rw 		FSC0
rw
Toggle fields

FSC0

Bit 0: Filter scale configuration.

FSC1

Bit 1: Filter scale configuration.

FSC2

Bit 2: Filter scale configuration.

FSC3

Bit 3: Filter scale configuration.

FSC4

Bit 4: Filter scale configuration.

FSC5

Bit 5: Filter scale configuration.

FSC6

Bit 6: Filter scale configuration.

FSC7

Bit 7: Filter scale configuration.

FSC8

Bit 8: Filter scale configuration.

FSC9

Bit 9: Filter scale configuration.

FSC10

Bit 10: Filter scale configuration.

FSC11

Bit 11: Filter scale configuration.

FSC12

Bit 12: Filter scale configuration.

FSC13

Bit 13: Filter scale configuration.

FSC14

Bit 14: Filter scale configuration.

FSC15

Bit 15: Filter scale configuration.

FSC16

Bit 16: Filter scale configuration.

FSC17

Bit 17: Filter scale configuration.

FSC18

Bit 18: Filter scale configuration.

FSC19

Bit 19: Filter scale configuration.

FSC20

Bit 20: Filter scale configuration.

FSC21

Bit 21: Filter scale configuration.

FSC22

Bit 22: Filter scale configuration.

FSC23

Bit 23: Filter scale configuration.

FSC24

Bit 24: Filter scale configuration.

FSC25

Bit 25: Filter scale configuration.

FSC26

Bit 26: Filter scale configuration.

FSC27

Bit 27: Filter scale configuration.

FFA1R

filter FIFO assignment register

Offset: 0x214, size: 32, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FFA27
rw 		FFA26
rw 		FFA25
rw 		FFA24
rw 		FFA23
rw 		FFA22
rw 		FFA21
rw 		FFA20
rw 		FFA19
rw 		FFA18
rw 		FFA17
rw 		FFA16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FFA15
rw 		FFA14
rw 		FFA13
rw 		FFA12
rw 		FFA11
rw 		FFA10
rw 		FFA9
rw 		FFA8
rw 		FFA7
rw 		FFA6
rw 		FFA5
rw 		FFA4
rw 		FFA3
rw 		FFA2
rw 		FFA1
rw 		FFA0
rw
Toggle fields

FFA0

Bit 0: Filter FIFO assignment for filter 0.

FFA1

Bit 1: Filter FIFO assignment for filter 1.

FFA2

Bit 2: Filter FIFO assignment for filter 2.

FFA3

Bit 3: Filter FIFO assignment for filter 3.

FFA4

Bit 4: Filter FIFO assignment for filter 4.

FFA5

Bit 5: Filter FIFO assignment for filter 5.

FFA6

Bit 6: Filter FIFO assignment for filter 6.

FFA7

Bit 7: Filter FIFO assignment for filter 7.

FFA8

Bit 8: Filter FIFO assignment for filter 8.

FFA9

Bit 9: Filter FIFO assignment for filter 9.

FFA10

Bit 10: Filter FIFO assignment for filter 10.

FFA11

Bit 11: Filter FIFO assignment for filter 11.

FFA12

Bit 12: Filter FIFO assignment for filter 12.

FFA13

Bit 13: Filter FIFO assignment for filter 13.

FFA14

Bit 14: Filter FIFO assignment for filter 14.

FFA15

Bit 15: Filter FIFO assignment for filter 15.

FFA16

Bit 16: Filter FIFO assignment for filter 16.

FFA17

Bit 17: Filter FIFO assignment for filter 17.

FFA18

Bit 18: Filter FIFO assignment for filter 18.

FFA19

Bit 19: Filter FIFO assignment for filter 19.

FFA20

Bit 20: Filter FIFO assignment for filter 20.

FFA21

Bit 21: Filter FIFO assignment for filter 21.

FFA22

Bit 22: Filter FIFO assignment for filter 22.

FFA23

Bit 23: Filter FIFO assignment for filter 23.

FFA24

Bit 24: Filter FIFO assignment for filter 24.

FFA25

Bit 25: Filter FIFO assignment for filter 25.

FFA26

Bit 26: Filter FIFO assignment for filter 26.

FFA27

Bit 27: Filter FIFO assignment for filter 27.

FA1R

filter activation register

Offset: 0x21c, size: 32, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FACT27
rw 		FACT26
rw 		FACT25
rw 		FACT24
rw 		FACT23
rw 		FACT22
rw 		FACT21
rw 		FACT20
rw 		FACT19
rw 		FACT18
rw 		FACT17
rw 		FACT16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FACT15
rw 		FACT14
rw 		FACT13
rw 		FACT12
rw 		FACT11
rw 		FACT10
rw 		FACT9
rw 		FACT8
rw 		FACT7
rw 		FACT6
rw 		FACT5
rw 		FACT4
rw 		FACT3
rw 		FACT2
rw 		FACT1
rw 		FACT0
rw
Toggle fields

FACT0

Bit 0: Filter active.

FACT1

Bit 1: Filter active.

FACT2

Bit 2: Filter active.

FACT3

Bit 3: Filter active.

FACT4

Bit 4: Filter active.

FACT5

Bit 5: Filter active.

FACT6

Bit 6: Filter active.

FACT7

Bit 7: Filter active.

FACT8

Bit 8: Filter active.

FACT9

Bit 9: Filter active.

FACT10

Bit 10: Filter active.

FACT11

Bit 11: Filter active.

FACT12

Bit 12: Filter active.

FACT13

Bit 13: Filter active.

FACT14

Bit 14: Filter active.

FACT15

Bit 15: Filter active.

FACT16

Bit 16: Filter active.

FACT17

Bit 17: Filter active.

FACT18

Bit 18: Filter active.

FACT19

Bit 19: Filter active.

FACT20

Bit 20: Filter active.

FACT21

Bit 21: Filter active.

FACT22

Bit 22: Filter active.

FACT23

Bit 23: Filter active.

FACT24

Bit 24: Filter active.

FACT25

Bit 25: Filter active.

FACT26

Bit 26: Filter active.

FACT27

Bit 27: Filter active.

F0R1

Filter bank 0 register 1

Offset: 0x240, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F0R2

Filter bank 0 register 2

Offset: 0x244, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F1R1

Filter bank 1 register 1

Offset: 0x248, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F1R2

Filter bank 1 register 2

Offset: 0x24c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F2R1

Filter bank 2 register 1

Offset: 0x250, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F2R2

Filter bank 2 register 2

Offset: 0x254, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F3R1

Filter bank 3 register 1

Offset: 0x258, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F3R2

Filter bank 3 register 2

Offset: 0x25c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F4R1

Filter bank 4 register 1

Offset: 0x260, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F4R2

Filter bank 4 register 2

Offset: 0x264, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F5R1

Filter bank 5 register 1

Offset: 0x268, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F5R2

Filter bank 5 register 2

Offset: 0x26c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F6R1

Filter bank 6 register 1

Offset: 0x270, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F6R2

Filter bank 6 register 2

Offset: 0x274, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F7R1

Filter bank 7 register 1

Offset: 0x278, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F7R2

Filter bank 7 register 2

Offset: 0x27c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F8R1

Filter bank 8 register 1

Offset: 0x280, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F8R2

Filter bank 8 register 2

Offset: 0x284, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F9R1

Filter bank 9 register 1

Offset: 0x288, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F9R2

Filter bank 9 register 2

Offset: 0x28c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F10R1

Filter bank 10 register 1

Offset: 0x290, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F10R2

Filter bank 10 register 2

Offset: 0x294, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F11R1

Filter bank 11 register 1

Offset: 0x298, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F11R2

Filter bank 11 register 2

Offset: 0x29c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F12R1

Filter bank 4 register 1

Offset: 0x2a0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F12R2

Filter bank 12 register 2

Offset: 0x2a4, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F13R1

Filter bank 13 register 1

Offset: 0x2a8, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F13R2

Filter bank 13 register 2

Offset: 0x2ac, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F14R1

Filter bank 14 register 1

Offset: 0x2b0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F14R2

Filter bank 14 register 2

Offset: 0x2b4, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F15R1

Filter bank 15 register 1

Offset: 0x2b8, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F15R2

Filter bank 15 register 2

Offset: 0x2bc, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F16R1

Filter bank 16 register 1

Offset: 0x2c0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F16R2

Filter bank 16 register 2

Offset: 0x2c4, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F17R1

Filter bank 17 register 1

Offset: 0x2c8, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F17R2

Filter bank 17 register 2

Offset: 0x2cc, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F18R1

Filter bank 18 register 1

Offset: 0x2d0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F18R2

Filter bank 18 register 2

Offset: 0x2d4, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F19R1

Filter bank 19 register 1

Offset: 0x2d8, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F19R2

Filter bank 19 register 2

Offset: 0x2dc, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F20R1

Filter bank 20 register 1

Offset: 0x2e0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F20R2

Filter bank 20 register 2

Offset: 0x2e4, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F21R1

Filter bank 21 register 1

Offset: 0x2e8, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F21R2

Filter bank 21 register 2

Offset: 0x2ec, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F22R1

Filter bank 22 register 1

Offset: 0x2f0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F22R2

Filter bank 22 register 2

Offset: 0x2f4, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F23R1

Filter bank 23 register 1

Offset: 0x2f8, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F23R2

Filter bank 23 register 2

Offset: 0x2fc, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F24R1

Filter bank 24 register 1

Offset: 0x300, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F24R2

Filter bank 24 register 2

Offset: 0x304, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F25R1

Filter bank 25 register 1

Offset: 0x308, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F25R2

Filter bank 25 register 2

Offset: 0x30c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F26R1

Filter bank 26 register 1

Offset: 0x310, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F26R2

Filter bank 26 register 2

Offset: 0x314, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F27R1

Filter bank 27 register 1

Offset: 0x318, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

F27R2

Filter bank 27 register 2

Offset: 0x31c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB31
rw 		FB30
rw 		FB29
rw 		FB28
rw 		FB27
rw 		FB26
rw 		FB25
rw 		FB24
rw 		FB23
rw 		FB22
rw 		FB21
rw 		FB20
rw 		FB19
rw 		FB18
rw 		FB17
rw 		FB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB15
rw 		FB14
rw 		FB13
rw 		FB12
rw 		FB11
rw 		FB10
rw 		FB9
rw 		FB8
rw 		FB7
rw 		FB6
rw 		FB5
rw 		FB4
rw 		FB3
rw 		FB2
rw 		FB1
rw 		FB0
rw
Toggle fields

FB0

Bit 0: Filter bits.

FB1

Bit 1: Filter bits.

FB2

Bit 2: Filter bits.

FB3

Bit 3: Filter bits.

FB4

Bit 4: Filter bits.

FB5

Bit 5: Filter bits.

FB6

Bit 6: Filter bits.

FB7

Bit 7: Filter bits.

FB8

Bit 8: Filter bits.

FB9

Bit 9: Filter bits.

FB10

Bit 10: Filter bits.

FB11

Bit 11: Filter bits.

FB12

Bit 12: Filter bits.

FB13

Bit 13: Filter bits.

FB14

Bit 14: Filter bits.

FB15

Bit 15: Filter bits.

FB16

Bit 16: Filter bits.

FB17

Bit 17: Filter bits.

FB18

Bit 18: Filter bits.

FB19

Bit 19: Filter bits.

FB20

Bit 20: Filter bits.

FB21

Bit 21: Filter bits.

FB22

Bit 22: Filter bits.

FB23

Bit 23: Filter bits.

FB24

Bit 24: Filter bits.

FB25

Bit 25: Filter bits.

FB26

Bit 26: Filter bits.

FB27

Bit 27: Filter bits.

FB28

Bit 28: Filter bits.

FB29

Bit 29: Filter bits.

FB30

Bit 30: Filter bits.

FB31

Bit 31: Filter bits.

CRC

0x40023000: Cryptographic processor

0/3 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 DR
0x4 IDR
0x8 CR
Toggle registers

DR

Data register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-31: Data Register.

IDR

Independent Data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR
rw
Toggle fields

IDR

Bits 0-7: Independent Data register.

CR

Control register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR
w
Toggle fields

CR

Bit 0: Control regidter.

CRYP

0x50060000: Cryptographic processor

10/423 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SR
0x8 DIN
0xc DOUT
0x10 DMACR
0x14 IMSCR
0x18 RISR
0x1c MISR
0x20 K0LR
0x24 K0RR
0x28 K1LR
0x2c K1RR
0x30 K2LR
0x34 K2RR
0x38 K3LR
0x3c K3RR
0x40 IV0LR
0x44 IV0RR
0x48 IV1LR
0x4c IV1RR
0x50 CSGCMCCM0R
0x54 CSGCMCCM1R
0x58 CSGCMCCM2R
0x5c CSGCMCCM3R
0x60 CSGCMCCM4R
0x64 CSGCMCCM5R
0x68 CSGCMCCM6R
0x6c CSGCMCCM7R
0x70 CSGCM0R
0x74 CSGCM1R
0x78 CSGCM2R
0x7c CSGCM3R
0x80 CSGCM4R
0x84 CSGCM5R
0x88 CSGCM6R
0x8c CSGCM7R
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALGOMODE3
rw 		GCM_CCMPH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRYPEN
rw 		FFLUSH
w 		KEYSIZE
rw 		DATATYPE
rw 		ALGOMODE0
rw 		ALGODIR
rw
Toggle fields

ALGODIR

Bit 2: Algorithm direction.

ALGOMODE0

Bits 3-5: Algorithm mode.

DATATYPE

Bits 6-7: Data type selection.

KEYSIZE

Bits 8-9: Key size selection (AES mode only).

FFLUSH

Bit 14: FIFO flush.

CRYPEN

Bit 15: Cryptographic processor enable.

GCM_CCMPH

Bits 16-17: GCM_CCMPH.

ALGOMODE3

Bit 19: ALGOMODE.

SR

status register

Offset: 0x4, size: 32, reset: 0x00000003, access: read-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		OFFU
r 		OFNE
r 		IFNF
r 		IFEM
r
Toggle fields

IFEM

Bit 0: Input FIFO empty.

IFNF

Bit 1: Input FIFO not full.

OFNE

Bit 2: Output FIFO not empty.

OFFU

Bit 3: Output FIFO full.

BUSY

Bit 4: Busy bit.

DIN

data input register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAIN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAIN
rw
Toggle fields

DATAIN

Bits 0-31: Data input.

DOUT

data output register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAOUT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAOUT
r
Toggle fields

DATAOUT

Bits 0-31: Data output.

DMACR

DMA control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOEN
rw 		DIEN
rw
Toggle fields

DIEN

Bit 0: DMA input enable.

DOEN

Bit 1: DMA output enable.

IMSCR

interrupt mask set/clear register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTIM
rw 		INIM
rw
Toggle fields

INIM

Bit 0: Input FIFO service interrupt mask.

OUTIM

Bit 1: Output FIFO service interrupt mask.

RISR

raw interrupt status register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTRIS
r 		INRIS
r
Toggle fields

INRIS

Bit 0: Input FIFO service raw interrupt status.

OUTRIS

Bit 1: Output FIFO service raw interrupt status.

MISR

masked interrupt status register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTMIS
r 		INMIS
r
Toggle fields

INMIS

Bit 0: Input FIFO service masked interrupt status.

OUTMIS

Bit 1: Output FIFO service masked interrupt status.

K0LR

key registers

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
b255
w 		b254
w 		b253
w 		b252
w 		b251
w 		b250
w 		b249
w 		b248
w 		b247
w 		b246
w 		b245
w 		b244
w 		b243
w 		b242
w 		b241
w 		b240
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
b239
w 		b238
w 		b237
w 		b236
w 		b235
w 		b234
w 		b233
w 		b232
w 		b231
w 		b230
w 		b229
w 		b228
w 		b227
w 		b226
w 		b225
w 		b224
w
Toggle fields

b224

Bit 0: b224.

b225

Bit 1: b225.

b226

Bit 2: b226.

b227

Bit 3: b227.

b228

Bit 4: b228.

b229

Bit 5: b229.

b230

Bit 6: b230.

b231

Bit 7: b231.

b232

Bit 8: b232.

b233

Bit 9: b233.

b234

Bit 10: b234.

b235

Bit 11: b235.

b236

Bit 12: b236.

b237

Bit 13: b237.

b238

Bit 14: b238.

b239

Bit 15: b239.

b240

Bit 16: b240.

b241

Bit 17: b241.

b242

Bit 18: b242.

b243

Bit 19: b243.

b244

Bit 20: b244.

b245

Bit 21: b245.

b246

Bit 22: b246.

b247

Bit 23: b247.

b248

Bit 24: b248.

b249

Bit 25: b249.

b250

Bit 26: b250.

b251

Bit 27: b251.

b252

Bit 28: b252.

b253

Bit 29: b253.

b254

Bit 30: b254.

b255

Bit 31: b255.

K0RR

key registers

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
b223
w 		b222
w 		b221
w 		b220
w 		b219
w 		b218
w 		b217
w 		b216
w 		b215
w 		b214
w 		b213
w 		b212
w 		b211
w 		b210
w 		b209
w 		b208
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
b207
w 		b206
w 		b205
w 		b204
w 		b203
w 		b202
w 		b201
w 		b200
w 		b199
w 		b198
w 		b197
w 		b196
w 		b195
w 		b194
w 		b193
w 		b192
w
Toggle fields

b192

Bit 0: b192.

b193

Bit 1: b193.

b194

Bit 2: b194.

b195

Bit 3: b195.

b196

Bit 4: b196.

b197

Bit 5: b197.

b198

Bit 6: b198.

b199

Bit 7: b199.

b200

Bit 8: b200.

b201

Bit 9: b201.

b202

Bit 10: b202.

b203

Bit 11: b203.

b204

Bit 12: b204.

b205

Bit 13: b205.

b206

Bit 14: b206.

b207

Bit 15: b207.

b208

Bit 16: b208.

b209

Bit 17: b209.

b210

Bit 18: b210.

b211

Bit 19: b211.

b212

Bit 20: b212.

b213

Bit 21: b213.

b214

Bit 22: b214.

b215

Bit 23: b215.

b216

Bit 24: b216.

b217

Bit 25: b217.

b218

Bit 26: b218.

b219

Bit 27: b219.

b220

Bit 28: b220.

b221

Bit 29: b221.

b222

Bit 30: b222.

b223

Bit 31: b223.

K1LR

key registers

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
b191
w 		b190
w 		b189
w 		b188
w 		b187
w 		b186
w 		b185
w 		b184
w 		b183
w 		b182
w 		b181
w 		b180
w 		b179
w 		b178
w 		b177
w 		b176
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
b175
w 		b174
w 		b173
w 		b172
w 		b171
w 		b170
w 		b169
w 		b168
w 		b167
w 		b166
w 		b165
w 		b164
w 		b163
w 		b162
w 		b161
w 		b160
w
Toggle fields

b160

Bit 0: b160.

b161

Bit 1: b161.

b162

Bit 2: b162.

b163

Bit 3: b163.

b164

Bit 4: b164.

b165

Bit 5: b165.

b166

Bit 6: b166.

b167

Bit 7: b167.

b168

Bit 8: b168.

b169

Bit 9: b169.

b170

Bit 10: b170.

b171

Bit 11: b171.

b172

Bit 12: b172.

b173

Bit 13: b173.

b174

Bit 14: b174.

b175

Bit 15: b175.

b176

Bit 16: b176.

b177

Bit 17: b177.

b178

Bit 18: b178.

b179

Bit 19: b179.

b180

Bit 20: b180.

b181

Bit 21: b181.

b182

Bit 22: b182.

b183

Bit 23: b183.

b184

Bit 24: b184.

b185

Bit 25: b185.

b186

Bit 26: b186.

b187

Bit 27: b187.

b188

Bit 28: b188.

b189

Bit 29: b189.

b190

Bit 30: b190.

b191

Bit 31: b191.

K1RR

key registers

Offset: 0x2c, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
b159
w 		b158
w 		b157
w 		b156
w 		b155
w 		b154
w 		b153
w 		b152
w 		b151
w 		b150
w 		b149
w 		b148
w 		b147
w 		b146
w 		b145
w 		b144
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
b143
w 		b142
w 		b141
w 		b140
w 		b139
w 		b138
w 		b137
w 		b136
w 		b135
w 		b134
w 		b133
w 		b132
w 		b131
w 		b130
w 		b129
w 		b128
w
Toggle fields

b128

Bit 0: b128.

b129

Bit 1: b129.

b130

Bit 2: b130.

b131

Bit 3: b131.

b132

Bit 4: b132.

b133

Bit 5: b133.

b134

Bit 6: b134.

b135

Bit 7: b135.

b136

Bit 8: b136.

b137

Bit 9: b137.

b138

Bit 10: b138.

b139

Bit 11: b139.

b140

Bit 12: b140.

b141

Bit 13: b141.

b142

Bit 14: b142.

b143

Bit 15: b143.

b144

Bit 16: b144.

b145

Bit 17: b145.

b146

Bit 18: b146.

b147

Bit 19: b147.

b148

Bit 20: b148.

b149

Bit 21: b149.

b150

Bit 22: b150.

b151

Bit 23: b151.

b152

Bit 24: b152.

b153

Bit 25: b153.

b154

Bit 26: b154.

b155

Bit 27: b155.

b156

Bit 28: b156.

b157

Bit 29: b157.

b158

Bit 30: b158.

b159

Bit 31: b159.

K2LR

key registers

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
b127
w 		b126
w 		b125
w 		b124
w 		b123
w 		b122
w 		b121
w 		b120
w 		b119
w 		b118
w 		b117
w 		b116
w 		b115
w 		b114
w 		b113
w 		b112
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
b111
w 		b110
w 		b109
w 		b108
w 		b107
w 		b106
w 		b105
w 		b104
w 		b103
w 		b102
w 		b101
w 		b100
w 		b99
w 		b98
w 		b97
w 		b96
w
Toggle fields

b96

Bit 0: b96.

b97

Bit 1: b97.

b98

Bit 2: b98.

b99

Bit 3: b99.

b100

Bit 4: b100.

b101

Bit 5: b101.

b102

Bit 6: b102.

b103

Bit 7: b103.

b104

Bit 8: b104.

b105

Bit 9: b105.

b106

Bit 10: b106.

b107

Bit 11: b107.

b108

Bit 12: b108.

b109

Bit 13: b109.

b110

Bit 14: b110.

b111

Bit 15: b111.

b112

Bit 16: b112.

b113

Bit 17: b113.

b114

Bit 18: b114.

b115

Bit 19: b115.

b116

Bit 20: b116.

b117

Bit 21: b117.

b118

Bit 22: b118.

b119

Bit 23: b119.

b120

Bit 24: b120.

b121

Bit 25: b121.

b122

Bit 26: b122.

b123

Bit 27: b123.

b124

Bit 28: b124.

b125

Bit 29: b125.

b126

Bit 30: b126.

b127

Bit 31: b127.

K2RR

key registers

Offset: 0x34, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
b95
w 		b94
w 		b93
w 		b92
w 		b91
w 		b90
w 		b89
w 		b88
w 		b87
w 		b86
w 		b85
w 		b84
w 		b83
w 		b82
w 		b81
w 		b80
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
b79
w 		b78
w 		b77
w 		b76
w 		b75
w 		b74
w 		b73
w 		b72
w 		b71
w 		b70
w 		b69
w 		b68
w 		b67
w 		b66
w 		b65
w 		b64
w
Toggle fields

b64

Bit 0: b64.

b65

Bit 1: b65.

b66

Bit 2: b66.

b67

Bit 3: b67.

b68

Bit 4: b68.

b69

Bit 5: b69.

b70

Bit 6: b70.

b71

Bit 7: b71.

b72

Bit 8: b72.

b73

Bit 9: b73.

b74

Bit 10: b74.

b75

Bit 11: b75.

b76

Bit 12: b76.

b77

Bit 13: b77.

b78

Bit 14: b78.

b79

Bit 15: b79.

b80

Bit 16: b80.

b81

Bit 17: b81.

b82

Bit 18: b82.

b83

Bit 19: b83.

b84

Bit 20: b84.

b85

Bit 21: b85.

b86

Bit 22: b86.

b87

Bit 23: b87.

b88

Bit 24: b88.

b89

Bit 25: b89.

b90

Bit 26: b90.

b91

Bit 27: b91.

b92

Bit 28: b92.

b93

Bit 29: b93.

b94

Bit 30: b94.

b95

Bit 31: b95.

K3LR

key registers

Offset: 0x38, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
b63
w 		b62
w 		b61
w 		b60
w 		b59
w 		b58
w 		b57
w 		b56
w 		b55
w 		b54
w 		b53
w 		b52
w 		b51
w 		b50
w 		b49
w 		b48
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
b47
w 		b46
w 		b45
w 		b44
w 		b43
w 		b42
w 		b41
w 		b40
w 		b39
w 		b38
w 		b37
w 		b36
w 		b35
w 		b34
w 		b33
w 		b32
w
Toggle fields

b32

Bit 0: b32.

b33

Bit 1: b33.

b34

Bit 2: b34.

b35

Bit 3: b35.

b36

Bit 4: b36.

b37

Bit 5: b37.

b38

Bit 6: b38.

b39

Bit 7: b39.

b40

Bit 8: b40.

b41

Bit 9: b41.

b42

Bit 10: b42.

b43

Bit 11: b43.

b44

Bit 12: b44.

b45

Bit 13: b45.

b46

Bit 14: b46.

b47

Bit 15: b47.

b48

Bit 16: b48.

b49

Bit 17: b49.

b50

Bit 18: b50.

b51

Bit 19: b51.

b52

Bit 20: b52.

b53

Bit 21: b53.

b54

Bit 22: b54.

b55

Bit 23: b55.

b56

Bit 24: b56.

b57

Bit 25: b57.

b58

Bit 26: b58.

b59

Bit 27: b59.

b60

Bit 28: b60.

b61

Bit 29: b61.

b62

Bit 30: b62.

b63

Bit 31: b63.

K3RR

key registers

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
b31
w 		b30
w 		b29
w 		b28
w 		b27
w 		b26
w 		b25
w 		b24
w 		b23
w 		b22
w 		b21
w 		b20
w 		b19
w 		b18
w 		b17
w 		b16
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
b15
w 		b14
w 		b13
w 		b12
w 		b11
w 		b10
w 		b9
w 		b8
w 		b7
w 		b6
w 		b5
w 		b4
w 		b3
w 		b2
w 		b1
w 		b0
w
Toggle fields

b0

Bit 0: b0.

b1

Bit 1: b1.

b2

Bit 2: b2.

b3

Bit 3: b3.

b4

Bit 4: b4.

b5

Bit 5: b5.

b6

Bit 6: b6.

b7

Bit 7: b7.

b8

Bit 8: b8.

b9

Bit 9: b9.

b10

Bit 10: b10.

b11

Bit 11: b11.

b12

Bit 12: b12.

b13

Bit 13: b13.

b14

Bit 14: b14.

b15

Bit 15: b15.

b16

Bit 16: b16.

b17

Bit 17: b17.

b18

Bit 18: b18.

b19

Bit 19: b19.

b20

Bit 20: b20.

b21

Bit 21: b21.

b22

Bit 22: b22.

b23

Bit 23: b23.

b24

Bit 24: b24.

b25

Bit 25: b25.

b26

Bit 26: b26.

b27

Bit 27: b27.

b28

Bit 28: b28.

b29

Bit 29: b29.

b30

Bit 30: b30.

b31

Bit 31: b31.

IV0LR

initialization vector registers

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IV0
rw 		IV1
rw 		IV2
rw 		IV3
rw 		IV4
rw 		IV5
rw 		IV6
rw 		IV7
rw 		IV8
rw 		IV9
rw 		IV10
rw 		IV11
rw 		IV12
rw 		IV13
rw 		IV14
rw 		IV15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IV16
rw 		IV17
rw 		IV18
rw 		IV19
rw 		IV20
rw 		IV21
rw 		IV22
rw 		IV23
rw 		IV24
rw 		IV25
rw 		IV26
rw 		IV27
rw 		IV28
rw 		IV29
rw 		IV30
rw 		IV31
rw
Toggle fields

IV31

Bit 0: IV31.

IV30

Bit 1: IV30.

IV29

Bit 2: IV29.

IV28

Bit 3: IV28.

IV27

Bit 4: IV27.

IV26

Bit 5: IV26.

IV25

Bit 6: IV25.

IV24

Bit 7: IV24.

IV23

Bit 8: IV23.

IV22

Bit 9: IV22.

IV21

Bit 10: IV21.

IV20

Bit 11: IV20.

IV19

Bit 12: IV19.

IV18

Bit 13: IV18.

IV17

Bit 14: IV17.

IV16

Bit 15: IV16.

IV15

Bit 16: IV15.

IV14

Bit 17: IV14.

IV13

Bit 18: IV13.

IV12

Bit 19: IV12.

IV11

Bit 20: IV11.

IV10

Bit 21: IV10.

IV9

Bit 22: IV9.

IV8

Bit 23: IV8.

IV7

Bit 24: IV7.

IV6

Bit 25: IV6.

IV5

Bit 26: IV5.

IV4

Bit 27: IV4.

IV3

Bit 28: IV3.

IV2

Bit 29: IV2.

IV1

Bit 30: IV1.

IV0

Bit 31: IV0.

IV0RR

initialization vector registers

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IV32
rw 		IV33
rw 		IV34
rw 		IV35
rw 		IV36
rw 		IV37
rw 		IV38
rw 		IV39
rw 		IV40
rw 		IV41
rw 		IV42
rw 		IV43
rw 		IV44
rw 		IV45
rw 		IV46
rw 		IV47
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IV48
rw 		IV49
rw 		IV50
rw 		IV51
rw 		IV52
rw 		IV53
rw 		IV54
rw 		IV55
rw 		IV56
rw 		IV57
rw 		IV58
rw 		IV59
rw 		IV60
rw 		IV61
rw 		IV62
rw 		IV63
rw
Toggle fields

IV63

Bit 0: IV63.

IV62

Bit 1: IV62.

IV61

Bit 2: IV61.

IV60

Bit 3: IV60.

IV59

Bit 4: IV59.

IV58

Bit 5: IV58.

IV57

Bit 6: IV57.

IV56

Bit 7: IV56.

IV55

Bit 8: IV55.

IV54

Bit 9: IV54.

IV53

Bit 10: IV53.

IV52

Bit 11: IV52.

IV51

Bit 12: IV51.

IV50

Bit 13: IV50.

IV49

Bit 14: IV49.

IV48

Bit 15: IV48.

IV47

Bit 16: IV47.

IV46

Bit 17: IV46.

IV45

Bit 18: IV45.

IV44

Bit 19: IV44.

IV43

Bit 20: IV43.

IV42

Bit 21: IV42.

IV41

Bit 22: IV41.

IV40

Bit 23: IV40.

IV39

Bit 24: IV39.

IV38

Bit 25: IV38.

IV37

Bit 26: IV37.

IV36

Bit 27: IV36.

IV35

Bit 28: IV35.

IV34

Bit 29: IV34.

IV33

Bit 30: IV33.

IV32

Bit 31: IV32.

IV1LR

initialization vector registers

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IV64
rw 		IV65
rw 		IV66
rw 		IV67
rw 		IV68
rw 		IV69
rw 		IV70
rw 		IV71
rw 		IV72
rw 		IV73
rw 		IV74
rw 		IV75
rw 		IV76
rw 		IV77
rw 		IV78
rw 		IV79
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IV80
rw 		IV81
rw 		IV82
rw 		IV83
rw 		IV84
rw 		IV85
rw 		IV86
rw 		IV87
rw 		IV88
rw 		IV89
rw 		IV90
rw 		IV91
rw 		IV92
rw 		IV93
rw 		IV94
rw 		IV95
rw
Toggle fields

IV95

Bit 0: IV95.

IV94

Bit 1: IV94.

IV93

Bit 2: IV93.

IV92

Bit 3: IV92.

IV91

Bit 4: IV91.

IV90

Bit 5: IV90.

IV89

Bit 6: IV89.

IV88

Bit 7: IV88.

IV87

Bit 8: IV87.

IV86

Bit 9: IV86.

IV85

Bit 10: IV85.

IV84

Bit 11: IV84.

IV83

Bit 12: IV83.

IV82

Bit 13: IV82.

IV81

Bit 14: IV81.

IV80

Bit 15: IV80.

IV79

Bit 16: IV79.

IV78

Bit 17: IV78.

IV77

Bit 18: IV77.

IV76

Bit 19: IV76.

IV75

Bit 20: IV75.

IV74

Bit 21: IV74.

IV73

Bit 22: IV73.

IV72

Bit 23: IV72.

IV71

Bit 24: IV71.

IV70

Bit 25: IV70.

IV69

Bit 26: IV69.

IV68

Bit 27: IV68.

IV67

Bit 28: IV67.

IV66

Bit 29: IV66.

IV65

Bit 30: IV65.

IV64

Bit 31: IV64.

IV1RR

initialization vector registers

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IV96
rw 		IV97
rw 		IV98
rw 		IV99
rw 		IV100
rw 		IV101
rw 		IV102
rw 		IV103
rw 		IV104
rw 		IV105
rw 		IV106
rw 		IV107
rw 		IV108
rw 		IV109
rw 		IV110
rw 		IV111
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IV112
rw 		IV113
rw 		IV114
rw 		IV115
rw 		IV116
rw 		IV117
rw 		IV118
rw 		IV119
rw 		IV120
rw 		IV121
rw 		IV122
rw 		IV123
rw 		IV124
rw 		IV125
rw 		IV126
rw 		IV127
rw
Toggle fields

IV127

Bit 0: IV127.

IV126

Bit 1: IV126.

IV125

Bit 2: IV125.

IV124

Bit 3: IV124.

IV123

Bit 4: IV123.

IV122

Bit 5: IV122.

IV121

Bit 6: IV121.

IV120

Bit 7: IV120.

IV119

Bit 8: IV119.

IV118

Bit 9: IV118.

IV117

Bit 10: IV117.

IV116

Bit 11: IV116.

IV115

Bit 12: IV115.

IV114

Bit 13: IV114.

IV113

Bit 14: IV113.

IV112

Bit 15: IV112.

IV111

Bit 16: IV111.

IV110

Bit 17: IV110.

IV109

Bit 18: IV109.

IV108

Bit 19: IV108.

IV107

Bit 20: IV107.

IV106

Bit 21: IV106.

IV105

Bit 22: IV105.

IV104

Bit 23: IV104.

IV103

Bit 24: IV103.

IV102

Bit 25: IV102.

IV101

Bit 26: IV101.

IV100

Bit 27: IV100.

IV99

Bit 28: IV99.

IV98

Bit 29: IV98.

IV97

Bit 30: IV97.

IV96

Bit 31: IV96.

CSGCMCCM0R

context swap register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCMCCM0R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCMCCM0R
rw
Toggle fields

CSGCMCCM0R

Bits 0-31: CSGCMCCM0R.

CSGCMCCM1R

context swap register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCMCCM1R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCMCCM1R
rw
Toggle fields

CSGCMCCM1R

Bits 0-31: CSGCMCCM1R.

CSGCMCCM2R

context swap register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCMCCM2R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCMCCM2R
rw
Toggle fields

CSGCMCCM2R

Bits 0-31: CSGCMCCM2R.

CSGCMCCM3R

context swap register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCMCCM3R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCMCCM3R
rw
Toggle fields

CSGCMCCM3R

Bits 0-31: CSGCMCCM3R.

CSGCMCCM4R

context swap register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCMCCM4R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCMCCM4R
rw
Toggle fields

CSGCMCCM4R

Bits 0-31: CSGCMCCM4R.

CSGCMCCM5R

context swap register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCMCCM5R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCMCCM5R
rw
Toggle fields

CSGCMCCM5R

Bits 0-31: CSGCMCCM5R.

CSGCMCCM6R

context swap register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCMCCM6R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCMCCM6R
rw
Toggle fields

CSGCMCCM6R

Bits 0-31: CSGCMCCM6R.

CSGCMCCM7R

context swap register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCMCCM7R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCMCCM7R
rw
Toggle fields

CSGCMCCM7R

Bits 0-31: CSGCMCCM7R.

CSGCM0R

context swap register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCM0R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCM0R
rw
Toggle fields

CSGCM0R

Bits 0-31: CSGCM0R.

CSGCM1R

context swap register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCM1R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCM1R
rw
Toggle fields

CSGCM1R

Bits 0-31: CSGCM1R.

CSGCM2R

context swap register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCM2R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCM2R
rw
Toggle fields

CSGCM2R

Bits 0-31: CSGCM2R.

CSGCM3R

context swap register

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCM3R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCM3R
rw
Toggle fields

CSGCM3R

Bits 0-31: CSGCM3R.

CSGCM4R

context swap register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCM4R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCM4R
rw
Toggle fields

CSGCM4R

Bits 0-31: CSGCM4R.

CSGCM5R

context swap register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCM5R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCM5R
rw
Toggle fields

CSGCM5R

Bits 0-31: CSGCM5R.

CSGCM6R

context swap register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCM6R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCM6R
rw
Toggle fields

CSGCM6R

Bits 0-31: CSGCM6R.

CSGCM7R

context swap register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCM7R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCM7R
rw
Toggle fields

CSGCM7R

Bits 0-31: CSGCM7R.

DAC

0x40007400: Digital-to-analog converter

2/34 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SWTRIGR
0x8 DHR12R1
0xc DHR12L1
0x10 DHR8R1
0x14 DHR12R2
0x18 DHR12L2
0x1c DHR8R2
0x20 DHR12RD
0x24 DHR12LD
0x28 DHR8RD
0x2c DOR1
0x30 DOR2
0x34 SR
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAUDRIE2
rw 		DMAEN2
rw 		MAMP2
rw 		WAVE2
rw 		TSEL2
rw 		TEN2
rw 		BOFF2
rw 		EN2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAUDRIE1
rw 		DMAEN1
rw 		MAMP1
rw 		WAVE1
rw 		TSEL1
rw 		TEN1
rw 		BOFF1
rw 		EN1
rw
Toggle fields

EN1

Bit 0: DAC channel1 enable.

BOFF1

Bit 1: DAC channel1 output buffer disable.

TEN1

Bit 2: DAC channel1 trigger enable.

TSEL1

Bits 3-5: DAC channel1 trigger selection.

WAVE1

Bits 6-7: DAC channel1 noise/triangle wave generation enable.

MAMP1

Bits 8-11: DAC channel1 mask/amplitude selector.

DMAEN1

Bit 12: DAC channel1 DMA enable.

DMAUDRIE1

Bit 13: DAC channel1 DMA Underrun Interrupt enable.

EN2

Bit 16: DAC channel2 enable.

BOFF2

Bit 17: DAC channel2 output buffer disable.

TEN2

Bit 18: DAC channel2 trigger enable.

TSEL2

Bits 19-21: DAC channel2 trigger selection.

WAVE2

Bits 22-23: DAC channel2 noise/triangle wave generation enable.

MAMP2

Bits 24-27: DAC channel2 mask/amplitude selector.

DMAEN2

Bit 28: DAC channel2 DMA enable.

DMAUDRIE2

Bit 29: DAC channel2 DMA underrun interrupt enable.

SWTRIGR

software trigger register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWTRIG2
w 		SWTRIG1
w
Toggle fields

SWTRIG1

Bit 0: DAC channel1 software trigger.

SWTRIG2

Bit 1: DAC channel2 software trigger.

DHR12R1

channel1 12-bit right-aligned data holding register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 0-11: DAC channel1 12-bit right-aligned data.

DHR12L1

channel1 12-bit left aligned data holding register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 4-15: DAC channel1 12-bit left-aligned data.

DHR8R1

channel1 8-bit right aligned data holding register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 0-7: DAC channel1 8-bit right-aligned data.

DHR12R2

channel2 12-bit right aligned data holding register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
Toggle fields

DACC2DHR

Bits 0-11: DAC channel2 12-bit right-aligned data.

DHR12L2

channel2 12-bit left aligned data holding register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
Toggle fields

DACC2DHR

Bits 4-15: DAC channel2 12-bit left-aligned data.

DHR8R2

channel2 8-bit right-aligned data holding register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
Toggle fields

DACC2DHR

Bits 0-7: DAC channel2 8-bit right-aligned data.

DHR12RD

Dual DAC 12-bit right-aligned data holding register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACC2DHR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 0-11: DAC channel1 12-bit right-aligned data.

DACC2DHR

Bits 16-27: DAC channel2 12-bit right-aligned data.

DHR12LD

DUAL DAC 12-bit left aligned data holding register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACC2DHR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 4-15: DAC channel1 12-bit left-aligned data.

DACC2DHR

Bits 20-31: DAC channel2 12-bit left-aligned data.

DHR8RD

DUAL DAC 8-bit right aligned data holding register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw 		DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 0-7: DAC channel1 8-bit right-aligned data.

DACC2DHR

Bits 8-15: DAC channel2 8-bit right-aligned data.

DOR1

channel1 data output register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DOR
r
Toggle fields

DACC1DOR

Bits 0-11: DAC channel1 data output.

DOR2

channel2 data output register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DOR
r
Toggle fields

DACC2DOR

Bits 0-11: DAC channel2 data output.

SR

status register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAUDR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAUDR1
rw
Toggle fields

DMAUDR1

Bit 13: DAC channel1 DMA underrun flag.

DMAUDR2

Bit 29: DAC channel2 DMA underrun flag.

DBG

0xe0042000: Debug support

2/28 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 DBGMCU_IDCODE
0x4 DBGMCU_CR
0x8 DBGMCU_APB1_FZ
0xc DBGMCU_APB2_FZ
Toggle registers

DBGMCU_IDCODE

IDCODE

Offset: 0x0, size: 32, reset: 0x10006411, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REV_ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEV_ID
r
Toggle fields

DEV_ID

Bits 0-11: DEV_ID.

REV_ID

Bits 16-31: REV_ID.

DBGMCU_CR

Control Register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRACE_MODE
rw 		TRACE_IOEN
rw 		DBG_STANDBY
rw 		DBG_STOP
rw 		DBG_SLEEP
rw
Toggle fields

DBG_SLEEP

Bit 0: DBG_SLEEP.

DBG_STOP

Bit 1: DBG_STOP.

DBG_STANDBY

Bit 2: DBG_STANDBY.

TRACE_IOEN

Bit 5: TRACE_IOEN.

TRACE_MODE

Bits 6-7: TRACE_MODE.

DBGMCU_APB1_FZ

Debug MCU APB1 Freeze registe

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBG_CAN2_STOP
rw 		DBG_CAN1_STOP
rw 		DBG_J2C3SMBUS_TIMEOUT
rw 		DBG_J2C2_SMBUS_TIMEOUT
rw 		DBG_J2C1_SMBUS_TIMEOUT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_IWDEG_STOP
rw 		DBG_WWDG_STOP
rw 		DBG_TIM14_STOP
rw 		DBG_TIM13_STOP
rw 		DBG_TIM12_STOP
rw 		DBG_TIM7_STOP
rw 		DBG_TIM6_STOP
rw 		DBG_TIM5_STOP
rw 		DBG_TIM4_STOP
rw 		DBG_TIM3_STOP
rw 		DBG_TIM2_STOP
rw
Toggle fields

DBG_TIM2_STOP

Bit 0: DBG_TIM2_STOP.

DBG_TIM3_STOP

Bit 1: DBG_TIM3 _STOP.

DBG_TIM4_STOP

Bit 2: DBG_TIM4_STOP.

DBG_TIM5_STOP

Bit 3: DBG_TIM5_STOP.

DBG_TIM6_STOP

Bit 4: DBG_TIM6_STOP.

DBG_TIM7_STOP

Bit 5: DBG_TIM7_STOP.

DBG_TIM12_STOP

Bit 6: DBG_TIM12_STOP.

DBG_TIM13_STOP

Bit 7: DBG_TIM13_STOP.

DBG_TIM14_STOP

Bit 8: DBG_TIM14_STOP.

DBG_WWDG_STOP

Bit 11: DBG_WWDG_STOP.

DBG_IWDEG_STOP

Bit 12: DBG_IWDEG_STOP.

DBG_J2C1_SMBUS_TIMEOUT

Bit 21: DBG_J2C1_SMBUS_TIMEOUT.

DBG_J2C2_SMBUS_TIMEOUT

Bit 22: DBG_J2C2_SMBUS_TIMEOUT.

DBG_J2C3SMBUS_TIMEOUT

Bit 23: DBG_J2C3SMBUS_TIMEOUT.

DBG_CAN1_STOP

Bit 25: DBG_CAN1_STOP.

DBG_CAN2_STOP

Bit 26: DBG_CAN2_STOP.

DBGMCU_APB2_FZ

Debug MCU APB2 Freeze registe

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBG_TIM11_STOP
rw 		DBG_TIM10_STOP
rw 		DBG_TIM9_STOP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_TIM8_STOP
rw 		DBG_TIM1_STOP
rw
Toggle fields

DBG_TIM1_STOP

Bit 0: TIM1 counter stopped when core is halted.

DBG_TIM8_STOP

Bit 1: TIM8 counter stopped when core is halted.

DBG_TIM9_STOP

Bit 16: TIM9 counter stopped when core is halted.

DBG_TIM10_STOP

Bit 17: TIM10 counter stopped when core is halted.

DBG_TIM11_STOP

Bit 18: TIM11 counter stopped when core is halted.

DCMI

0x50050000: Digital camera interface

17/50 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SR
0x8 RIS
0xc IER
0x10 MIS
0x14 ICR
0x18 ESCR
0x1c ESUR
0x20 CWSTRT
0x24 CWSIZE
0x28 DR
Toggle registers

CR

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENABLE
rw 		EDM
rw 		FCRC
rw 		VSPOL
rw 		HSPOL
rw 		PCKPOL
rw 		ESS
rw 		JPEG
rw 		CROP
rw 		CM
rw 		CAPTURE
rw
Toggle fields

CAPTURE

Bit 0: Capture enable.

CM

Bit 1: Capture mode.

CROP

Bit 2: Crop feature.

JPEG

Bit 3: JPEG format.

ESS

Bit 4: Embedded synchronization select.

PCKPOL

Bit 5: Pixel clock polarity.

HSPOL

Bit 6: Horizontal synchronization polarity.

VSPOL

Bit 7: Vertical synchronization polarity.

FCRC

Bits 8-9: Frame capture rate control.

EDM

Bits 10-11: Extended data mode.

ENABLE

Bit 14: DCMI enable.

SR

status register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FNE
r 		VSYNC
r 		HSYNC
r
Toggle fields

HSYNC

Bit 0: HSYNC.

VSYNC

Bit 1: VSYNC.

FNE

Bit 2: FIFO not empty.

RIS

raw interrupt status register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINE_RIS
r 		VSYNC_RIS
r 		ERR_RIS
r 		OVR_RIS
r 		FRAME_RIS
r
Toggle fields

FRAME_RIS

Bit 0: Capture complete raw interrupt status.

OVR_RIS

Bit 1: Overrun raw interrupt status.

ERR_RIS

Bit 2: Synchronization error raw interrupt status.

VSYNC_RIS

Bit 3: VSYNC raw interrupt status.

LINE_RIS

Bit 4: Line raw interrupt status.

IER

interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINE_IE
rw 		VSYNC_IE
rw 		ERR_IE
rw 		OVR_IE
rw 		FRAME_IE
rw
Toggle fields

FRAME_IE

Bit 0: Capture complete interrupt enable.

OVR_IE

Bit 1: Overrun interrupt enable.

ERR_IE

Bit 2: Synchronization error interrupt enable.

VSYNC_IE

Bit 3: VSYNC interrupt enable.

LINE_IE

Bit 4: Line interrupt enable.

MIS

masked interrupt status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINE_MIS
r 		VSYNC_MIS
r 		ERR_MIS
r 		OVR_MIS
r 		FRAME_MIS
r
Toggle fields

FRAME_MIS

Bit 0: Capture complete masked interrupt status.

OVR_MIS

Bit 1: Overrun masked interrupt status.

ERR_MIS

Bit 2: Synchronization error masked interrupt status.

VSYNC_MIS

Bit 3: VSYNC masked interrupt status.

LINE_MIS

Bit 4: Line masked interrupt status.

ICR

interrupt clear register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINE_ISC
w 		VSYNC_ISC
w 		ERR_ISC
w 		OVR_ISC
w 		FRAME_ISC
w
Toggle fields

FRAME_ISC

Bit 0: Capture complete interrupt status clear.

OVR_ISC

Bit 1: Overrun interrupt status clear.

ERR_ISC

Bit 2: Synchronization error interrupt status clear.

VSYNC_ISC

Bit 3: Vertical synch interrupt status clear.

LINE_ISC

Bit 4: line interrupt status clear.

ESCR

embedded synchronization code register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FEC
rw 		LEC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSC
rw 		FSC
rw
Toggle fields

FSC

Bits 0-7: Frame start delimiter code.

LSC

Bits 8-15: Line start delimiter code.

LEC

Bits 16-23: Line end delimiter code.

FEC

Bits 24-31: Frame end delimiter code.

ESUR

embedded synchronization unmask register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FEU
rw 		LEU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSU
rw 		FSU
rw
Toggle fields

FSU

Bits 0-7: Frame start delimiter unmask.

LSU

Bits 8-15: Line start delimiter unmask.

LEU

Bits 16-23: Line end delimiter unmask.

FEU

Bits 24-31: Frame end delimiter unmask.

CWSTRT

crop window start

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HOFFCNT
rw
Toggle fields

HOFFCNT

Bits 0-13: Horizontal offset count.

VST

Bits 16-28: Vertical start line count.

CWSIZE

crop window size

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VLINE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAPCNT
rw
Toggle fields

CAPCNT

Bits 0-13: Capture count.

VLINE

Bits 16-29: Vertical line count.

DR

data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Byte3
r 		Byte2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Byte1
r 		Byte0
r
Toggle fields

Byte0

Bits 0-7: Data byte 0.

Byte1

Bits 8-15: Data byte 1.

Byte2

Bits 16-23: Data byte 2.

Byte3

Bits 24-31: Data byte 3.

DMA1

0x40026000: DMA controller

48/303 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 LISR
0x4 HISR
0x8 LIFCR
0xc HIFCR
0x10 S0CR
0x14 S0NDTR
0x18 S0PAR
0x1c S0M0AR
0x20 S0M1AR
0x24 S0FCR
0x28 S1CR
0x2c S1NDTR
0x30 S1PAR
0x34 S1M0AR
0x38 S1M1AR
0x3c S1FCR
0x40 S2CR
0x44 S2NDTR
0x48 S2PAR
0x4c S2M0AR
0x50 S2M1AR
0x54 S2FCR
0x58 S3CR
0x5c S3NDTR
0x60 S3PAR
0x64 S3M0AR
0x68 S3M1AR
0x6c S3FCR
0x70 S4CR
0x74 S4NDTR
0x78 S4PAR
0x7c S4M0AR
0x80 S4M1AR
0x84 S4FCR
0x88 S5CR
0x8c S5NDTR
0x90 S5PAR
0x94 S5M0AR
0x98 S5M1AR
0x9c S5FCR
0xa0 S6CR
0xa4 S6NDTR
0xa8 S6PAR
0xac S6M0AR
0xb0 S6M1AR
0xb4 S6FCR
0xb8 S7CR
0xbc S7NDTR
0xc0 S7PAR
0xc4 S7M0AR
0xc8 S7M1AR
0xcc S7FCR
Toggle registers

LISR

low interrupt status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCIF3
r 		HTIF3
r 		TEIF3
r 		DMEIF3
r 		FEIF3
r 		TCIF2
r 		HTIF2
r 		TEIF2
r 		DMEIF2
r 		FEIF2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF1
r 		HTIF1
r 		TEIF1
r 		DMEIF1
r 		FEIF1
r 		TCIF0
r 		HTIF0
r 		TEIF0
r 		DMEIF0
r 		FEIF0
r
Toggle fields

FEIF0

Bit 0: Stream x FIFO error interrupt flag (x=3..0).

DMEIF0

Bit 2: Stream x direct mode error interrupt flag (x=3..0).

TEIF0

Bit 3: Stream x transfer error interrupt flag (x=3..0).

HTIF0

Bit 4: Stream x half transfer interrupt flag (x=3..0).

TCIF0

Bit 5: Stream x transfer complete interrupt flag (x = 3..0).

FEIF1

Bit 6: Stream x FIFO error interrupt flag (x=3..0).

DMEIF1

Bit 8: Stream x direct mode error interrupt flag (x=3..0).

TEIF1

Bit 9: Stream x transfer error interrupt flag (x=3..0).

HTIF1

Bit 10: Stream x half transfer interrupt flag (x=3..0).

TCIF1

Bit 11: Stream x transfer complete interrupt flag (x = 3..0).

FEIF2

Bit 16: Stream x FIFO error interrupt flag (x=3..0).

DMEIF2

Bit 18: Stream x direct mode error interrupt flag (x=3..0).

TEIF2

Bit 19: Stream x transfer error interrupt flag (x=3..0).

HTIF2

Bit 20: Stream x half transfer interrupt flag (x=3..0).

TCIF2

Bit 21: Stream x transfer complete interrupt flag (x = 3..0).

FEIF3

Bit 22: Stream x FIFO error interrupt flag (x=3..0).

DMEIF3

Bit 24: Stream x direct mode error interrupt flag (x=3..0).

TEIF3

Bit 25: Stream x transfer error interrupt flag (x=3..0).

HTIF3

Bit 26: Stream x half transfer interrupt flag (x=3..0).

TCIF3

Bit 27: Stream x transfer complete interrupt flag (x = 3..0).

HISR

high interrupt status register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCIF7
r 		HTIF7
r 		TEIF7
r 		DMEIF7
r 		FEIF7
r 		TCIF6
r 		HTIF6
r 		TEIF6
r 		DMEIF6
r 		FEIF6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF5
r 		HTIF5
r 		TEIF5
r 		DMEIF5
r 		FEIF5
r 		TCIF4
r 		HTIF4
r 		TEIF4
r 		DMEIF4
r 		FEIF4
r
Toggle fields

FEIF4

Bit 0: Stream x FIFO error interrupt flag (x=7..4).

DMEIF4

Bit 2: Stream x direct mode error interrupt flag (x=7..4).

TEIF4

Bit 3: Stream x transfer error interrupt flag (x=7..4).

HTIF4

Bit 4: Stream x half transfer interrupt flag (x=7..4).

TCIF4

Bit 5: Stream x transfer complete interrupt flag (x=7..4).

FEIF5

Bit 6: Stream x FIFO error interrupt flag (x=7..4).

DMEIF5

Bit 8: Stream x direct mode error interrupt flag (x=7..4).

TEIF5

Bit 9: Stream x transfer error interrupt flag (x=7..4).

HTIF5

Bit 10: Stream x half transfer interrupt flag (x=7..4).

TCIF5

Bit 11: Stream x transfer complete interrupt flag (x=7..4).

FEIF6

Bit 16: Stream x FIFO error interrupt flag (x=7..4).

DMEIF6

Bit 18: Stream x direct mode error interrupt flag (x=7..4).

TEIF6

Bit 19: Stream x transfer error interrupt flag (x=7..4).

HTIF6

Bit 20: Stream x half transfer interrupt flag (x=7..4).

TCIF6

Bit 21: Stream x transfer complete interrupt flag (x=7..4).

FEIF7

Bit 22: Stream x FIFO error interrupt flag (x=7..4).

DMEIF7

Bit 24: Stream x direct mode error interrupt flag (x=7..4).

TEIF7

Bit 25: Stream x transfer error interrupt flag (x=7..4).

HTIF7

Bit 26: Stream x half transfer interrupt flag (x=7..4).

TCIF7

Bit 27: Stream x transfer complete interrupt flag (x=7..4).

LIFCR

low interrupt flag clear register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTCIF3
rw 		CHTIF3
rw 		CTEIF3
rw 		CDMEIF3
rw 		CFEIF3
rw 		CTCIF2
rw 		CHTIF2
rw 		CTEIF2
rw 		CDMEIF2
rw 		CFEIF2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTCIF1
rw 		CHTIF1
rw 		CTEIF1
rw 		CDMEIF1
rw 		CFEIF1
rw 		CTCIF0
rw 		CHTIF0
rw 		CTEIF0
rw 		CDMEIF0
rw 		CFEIF0
rw
Toggle fields

CFEIF0

Bit 0: Stream x clear FIFO error interrupt flag (x = 3..0).

CDMEIF0

Bit 2: Stream x clear direct mode error interrupt flag (x = 3..0).

CTEIF0

Bit 3: Stream x clear transfer error interrupt flag (x = 3..0).

CHTIF0

Bit 4: Stream x clear half transfer interrupt flag (x = 3..0).

CTCIF0

Bit 5: Stream x clear transfer complete interrupt flag (x = 3..0).

CFEIF1

Bit 6: Stream x clear FIFO error interrupt flag (x = 3..0).

CDMEIF1

Bit 8: Stream x clear direct mode error interrupt flag (x = 3..0).

CTEIF1

Bit 9: Stream x clear transfer error interrupt flag (x = 3..0).

CHTIF1

Bit 10: Stream x clear half transfer interrupt flag (x = 3..0).

CTCIF1

Bit 11: Stream x clear transfer complete interrupt flag (x = 3..0).

CFEIF2

Bit 16: Stream x clear FIFO error interrupt flag (x = 3..0).

CDMEIF2

Bit 18: Stream x clear direct mode error interrupt flag (x = 3..0).

CTEIF2

Bit 19: Stream x clear transfer error interrupt flag (x = 3..0).

CHTIF2

Bit 20: Stream x clear half transfer interrupt flag (x = 3..0).

CTCIF2

Bit 21: Stream x clear transfer complete interrupt flag (x = 3..0).

CFEIF3

Bit 22: Stream x clear FIFO error interrupt flag (x = 3..0).

CDMEIF3

Bit 24: Stream x clear direct mode error interrupt flag (x = 3..0).

CTEIF3

Bit 25: Stream x clear transfer error interrupt flag (x = 3..0).

CHTIF3

Bit 26: Stream x clear half transfer interrupt flag (x = 3..0).

CTCIF3

Bit 27: Stream x clear transfer complete interrupt flag (x = 3..0).

HIFCR

high interrupt flag clear register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTCIF7
rw 		CHTIF7
rw 		CTEIF7
rw 		CDMEIF7
rw 		CFEIF7
rw 		CTCIF6
rw 		CHTIF6
rw 		CTEIF6
rw 		CDMEIF6
rw 		CFEIF6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTCIF5
rw 		CHTIF5
rw 		CTEIF5
rw 		CDMEIF5
rw 		CFEIF5
rw 		CTCIF4
rw 		CHTIF4
rw 		CTEIF4
rw 		CDMEIF4
rw 		CFEIF4
rw
Toggle fields

CFEIF4

Bit 0: Stream x clear FIFO error interrupt flag (x = 7..4).

CDMEIF4

Bit 2: Stream x clear direct mode error interrupt flag (x = 7..4).

CTEIF4

Bit 3: Stream x clear transfer error interrupt flag (x = 7..4).

CHTIF4

Bit 4: Stream x clear half transfer interrupt flag (x = 7..4).

CTCIF4

Bit 5: Stream x clear transfer complete interrupt flag (x = 7..4).

CFEIF5

Bit 6: Stream x clear FIFO error interrupt flag (x = 7..4).

CDMEIF5

Bit 8: Stream x clear direct mode error interrupt flag (x = 7..4).

CTEIF5

Bit 9: Stream x clear transfer error interrupt flag (x = 7..4).

CHTIF5

Bit 10: Stream x clear half transfer interrupt flag (x = 7..4).

CTCIF5

Bit 11: Stream x clear transfer complete interrupt flag (x = 7..4).

CFEIF6

Bit 16: Stream x clear FIFO error interrupt flag (x = 7..4).

CDMEIF6

Bit 18: Stream x clear direct mode error interrupt flag (x = 7..4).

CTEIF6

Bit 19: Stream x clear transfer error interrupt flag (x = 7..4).

CHTIF6

Bit 20: Stream x clear half transfer interrupt flag (x = 7..4).

CTCIF6

Bit 21: Stream x clear transfer complete interrupt flag (x = 7..4).

CFEIF7

Bit 22: Stream x clear FIFO error interrupt flag (x = 7..4).

CDMEIF7

Bit 24: Stream x clear direct mode error interrupt flag (x = 7..4).

CTEIF7

Bit 25: Stream x clear transfer error interrupt flag (x = 7..4).

CHTIF7

Bit 26: Stream x clear half transfer interrupt flag (x = 7..4).

CTCIF7

Bit 27: Stream x clear transfer complete interrupt flag (x = 7..4).

S0CR

stream x configuration register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHSEL
rw 		MBURST
rw 		PBURST
rw 		CT
rw 		DBM
rw 		PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		PFCTRL
rw 		TCIE
rw 		HTIE
rw 		TEIE
rw 		DMEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

DMEIE

Bit 1: Direct mode error interrupt enable.

TEIE

Bit 2: Transfer error interrupt enable.

HTIE

Bit 3: Half transfer interrupt enable.

TCIE

Bit 4: Transfer complete interrupt enable.

PFCTRL

Bit 5: Peripheral flow controller.

DIR

Bits 6-7: Data transfer direction.

CIRC

Bit 8: Circular mode.

PINC

Bit 9: Peripheral increment mode.

MINC

Bit 10: Memory increment mode.

PSIZE

Bits 11-12: Peripheral data size.

MSIZE

Bits 13-14: Memory data size.

PINCOS

Bit 15: Peripheral increment offset size.

PL

Bits 16-17: Priority level.

DBM

Bit 18: Double buffer mode.

CT

Bit 19: Current target (only in double buffer mode).

PBURST

Bits 21-22: Peripheral burst transfer configuration.

MBURST

Bits 23-24: Memory burst transfer configuration.

CHSEL

Bits 25-27: Channel selection.

S0NDTR

stream x number of data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

S0PAR

stream x peripheral address register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

S0M0AR

stream x memory 0 address register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: Memory 0 address.

S0M1AR

stream x memory 1 address register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

S0FCR

stream x FIFO control register

Offset: 0x24, size: 32, reset: 0x00000021, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw 		FS
r 		DMDIS
rw 		FTH
rw
Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

DMDIS

Bit 2: Direct mode disable.

FS

Bits 3-5: FIFO status.

FEIE

Bit 7: FIFO error interrupt enable.

S1CR

stream x configuration register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHSEL
rw 		MBURST
rw 		PBURST
rw 		ACK
rw 		CT
rw 		DBM
rw 		PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		PFCTRL
rw 		TCIE
rw 		HTIE
rw 		TEIE
rw 		DMEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

DMEIE

Bit 1: Direct mode error interrupt enable.

TEIE

Bit 2: Transfer error interrupt enable.

HTIE

Bit 3: Half transfer interrupt enable.

TCIE

Bit 4: Transfer complete interrupt enable.

PFCTRL

Bit 5: Peripheral flow controller.

DIR

Bits 6-7: Data transfer direction.

CIRC

Bit 8: Circular mode.

PINC

Bit 9: Peripheral increment mode.

MINC

Bit 10: Memory increment mode.

PSIZE

Bits 11-12: Peripheral data size.

MSIZE

Bits 13-14: Memory data size.

PINCOS

Bit 15: Peripheral increment offset size.

PL

Bits 16-17: Priority level.

DBM

Bit 18: Double buffer mode.

CT

Bit 19: Current target (only in double buffer mode).

ACK

Bit 20: ACK.

PBURST

Bits 21-22: Peripheral burst transfer configuration.

MBURST

Bits 23-24: Memory burst transfer configuration.

CHSEL

Bits 25-27: Channel selection.

S1NDTR

stream x number of data register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

S1PAR

stream x peripheral address register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

S1M0AR

stream x memory 0 address register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: Memory 0 address.

S1M1AR

stream x memory 1 address register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

S1FCR

stream x FIFO control register

Offset: 0x3c, size: 32, reset: 0x00000021, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw 		FS
r 		DMDIS
rw 		FTH
rw
Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

DMDIS

Bit 2: Direct mode disable.

FS

Bits 3-5: FIFO status.

FEIE

Bit 7: FIFO error interrupt enable.

S2CR

stream x configuration register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHSEL
rw 		MBURST
rw 		PBURST
rw 		ACK
rw 		CT
rw 		DBM
rw 		PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		PFCTRL
rw 		TCIE
rw 		HTIE
rw 		TEIE
rw 		DMEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

DMEIE

Bit 1: Direct mode error interrupt enable.

TEIE

Bit 2: Transfer error interrupt enable.

HTIE

Bit 3: Half transfer interrupt enable.

TCIE

Bit 4: Transfer complete interrupt enable.

PFCTRL

Bit 5: Peripheral flow controller.

DIR

Bits 6-7: Data transfer direction.

CIRC

Bit 8: Circular mode.

PINC

Bit 9: Peripheral increment mode.

MINC

Bit 10: Memory increment mode.

PSIZE

Bits 11-12: Peripheral data size.

MSIZE

Bits 13-14: Memory data size.

PINCOS

Bit 15: Peripheral increment offset size.

PL

Bits 16-17: Priority level.

DBM

Bit 18: Double buffer mode.

CT

Bit 19: Current target (only in double buffer mode).

ACK

Bit 20: ACK.

PBURST

Bits 21-22: Peripheral burst transfer configuration.

MBURST

Bits 23-24: Memory burst transfer configuration.

CHSEL

Bits 25-27: Channel selection.

S2NDTR

stream x number of data register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

S2PAR

stream x peripheral address register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

S2M0AR

stream x memory 0 address register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: Memory 0 address.

S2M1AR

stream x memory 1 address register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

S2FCR

stream x FIFO control register

Offset: 0x54, size: 32, reset: 0x00000021, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw 		FS
r 		DMDIS
rw 		FTH
rw
Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

DMDIS

Bit 2: Direct mode disable.

FS

Bits 3-5: FIFO status.

FEIE

Bit 7: FIFO error interrupt enable.

S3CR

stream x configuration register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHSEL
rw 		MBURST
rw 		PBURST
rw 		ACK
rw 		CT
rw 		DBM
rw 		PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		PFCTRL
rw 		TCIE
rw 		HTIE
rw 		TEIE
rw 		DMEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

DMEIE

Bit 1: Direct mode error interrupt enable.

TEIE

Bit 2: Transfer error interrupt enable.

HTIE

Bit 3: Half transfer interrupt enable.

TCIE

Bit 4: Transfer complete interrupt enable.

PFCTRL

Bit 5: Peripheral flow controller.

DIR

Bits 6-7: Data transfer direction.

CIRC

Bit 8: Circular mode.

PINC

Bit 9: Peripheral increment mode.

MINC

Bit 10: Memory increment mode.

PSIZE

Bits 11-12: Peripheral data size.

MSIZE

Bits 13-14: Memory data size.

PINCOS

Bit 15: Peripheral increment offset size.

PL

Bits 16-17: Priority level.

DBM

Bit 18: Double buffer mode.

CT

Bit 19: Current target (only in double buffer mode).

ACK

Bit 20: ACK.

PBURST

Bits 21-22: Peripheral burst transfer configuration.

MBURST

Bits 23-24: Memory burst transfer configuration.

CHSEL

Bits 25-27: Channel selection.

S3NDTR

stream x number of data register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

S3PAR

stream x peripheral address register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

S3M0AR

stream x memory 0 address register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: Memory 0 address.

S3M1AR

stream x memory 1 address register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

S3FCR

stream x FIFO control register

Offset: 0x6c, size: 32, reset: 0x00000021, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw 		FS
r 		DMDIS
rw 		FTH
rw
Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

DMDIS

Bit 2: Direct mode disable.

FS

Bits 3-5: FIFO status.

FEIE

Bit 7: FIFO error interrupt enable.

S4CR

stream x configuration register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHSEL
rw 		MBURST
rw 		PBURST
rw 		ACK
rw 		CT
rw 		DBM
rw 		PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		PFCTRL
rw 		TCIE
rw 		HTIE
rw 		TEIE
rw 		DMEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

DMEIE

Bit 1: Direct mode error interrupt enable.

TEIE

Bit 2: Transfer error interrupt enable.

HTIE

Bit 3: Half transfer interrupt enable.

TCIE

Bit 4: Transfer complete interrupt enable.

PFCTRL

Bit 5: Peripheral flow controller.

DIR

Bits 6-7: Data transfer direction.

CIRC

Bit 8: Circular mode.

PINC

Bit 9: Peripheral increment mode.

MINC

Bit 10: Memory increment mode.

PSIZE

Bits 11-12: Peripheral data size.

MSIZE

Bits 13-14: Memory data size.

PINCOS

Bit 15: Peripheral increment offset size.

PL

Bits 16-17: Priority level.

DBM

Bit 18: Double buffer mode.

CT

Bit 19: Current target (only in double buffer mode).

ACK

Bit 20: ACK.

PBURST

Bits 21-22: Peripheral burst transfer configuration.

MBURST

Bits 23-24: Memory burst transfer configuration.

CHSEL

Bits 25-27: Channel selection.

S4NDTR

stream x number of data register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

S4PAR

stream x peripheral address register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

S4M0AR

stream x memory 0 address register

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: Memory 0 address.

S4M1AR

stream x memory 1 address register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

S4FCR

stream x FIFO control register

Offset: 0x84, size: 32, reset: 0x00000021, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw 		FS
r 		DMDIS
rw 		FTH
rw
Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

DMDIS

Bit 2: Direct mode disable.

FS

Bits 3-5: FIFO status.

FEIE

Bit 7: FIFO error interrupt enable.

S5CR

stream x configuration register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHSEL
rw 		MBURST
rw 		PBURST
rw 		ACK
rw 		CT
rw 		DBM
rw 		PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		PFCTRL
rw 		TCIE
rw 		HTIE
rw 		TEIE
rw 		DMEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

DMEIE

Bit 1: Direct mode error interrupt enable.

TEIE

Bit 2: Transfer error interrupt enable.

HTIE

Bit 3: Half transfer interrupt enable.

TCIE

Bit 4: Transfer complete interrupt enable.

PFCTRL

Bit 5: Peripheral flow controller.

DIR

Bits 6-7: Data transfer direction.

CIRC

Bit 8: Circular mode.

PINC

Bit 9: Peripheral increment mode.

MINC

Bit 10: Memory increment mode.

PSIZE

Bits 11-12: Peripheral data size.

MSIZE

Bits 13-14: Memory data size.

PINCOS

Bit 15: Peripheral increment offset size.

PL

Bits 16-17: Priority level.

DBM

Bit 18: Double buffer mode.

CT

Bit 19: Current target (only in double buffer mode).

ACK

Bit 20: ACK.

PBURST

Bits 21-22: Peripheral burst transfer configuration.

MBURST

Bits 23-24: Memory burst transfer configuration.

CHSEL

Bits 25-27: Channel selection.

S5NDTR

stream x number of data register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

S5PAR

stream x peripheral address register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

S5M0AR

stream x memory 0 address register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: Memory 0 address.

S5M1AR

stream x memory 1 address register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

S5FCR

stream x FIFO control register

Offset: 0x9c, size: 32, reset: 0x00000021, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw 		FS
r 		DMDIS
rw 		FTH
rw
Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

DMDIS

Bit 2: Direct mode disable.

FS

Bits 3-5: FIFO status.

FEIE

Bit 7: FIFO error interrupt enable.

S6CR

stream x configuration register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHSEL
rw 		MBURST
rw 		PBURST
rw 		ACK
rw 		CT
rw 		DBM
rw 		PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		PFCTRL
rw 		TCIE
rw 		HTIE
rw 		TEIE
rw 		DMEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

DMEIE

Bit 1: Direct mode error interrupt enable.

TEIE

Bit 2: Transfer error interrupt enable.

HTIE

Bit 3: Half transfer interrupt enable.

TCIE

Bit 4: Transfer complete interrupt enable.

PFCTRL

Bit 5: Peripheral flow controller.

DIR

Bits 6-7: Data transfer direction.

CIRC

Bit 8: Circular mode.

PINC

Bit 9: Peripheral increment mode.

MINC

Bit 10: Memory increment mode.

PSIZE

Bits 11-12: Peripheral data size.

MSIZE

Bits 13-14: Memory data size.

PINCOS

Bit 15: Peripheral increment offset size.

PL

Bits 16-17: Priority level.

DBM

Bit 18: Double buffer mode.

CT

Bit 19: Current target (only in double buffer mode).

ACK

Bit 20: ACK.

PBURST

Bits 21-22: Peripheral burst transfer configuration.

MBURST

Bits 23-24: Memory burst transfer configuration.

CHSEL

Bits 25-27: Channel selection.

S6NDTR

stream x number of data register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

S6PAR

stream x peripheral address register

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

S6M0AR

stream x memory 0 address register

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: Memory 0 address.

S6M1AR

stream x memory 1 address register

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

S6FCR

stream x FIFO control register

Offset: 0xb4, size: 32, reset: 0x00000021, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw 		FS
r 		DMDIS
rw 		FTH
rw
Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

DMDIS

Bit 2: Direct mode disable.

FS

Bits 3-5: FIFO status.

FEIE

Bit 7: FIFO error interrupt enable.

S7CR

stream x configuration register

Offset: 0xb8, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHSEL
rw 		MBURST
rw 		PBURST
rw 		ACK
rw 		CT
rw 		DBM
rw 		PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		PFCTRL
rw 		TCIE
rw 		HTIE
rw 		TEIE
rw 		DMEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

DMEIE

Bit 1: Direct mode error interrupt enable.

TEIE

Bit 2: Transfer error interrupt enable.

HTIE

Bit 3: Half transfer interrupt enable.

TCIE

Bit 4: Transfer complete interrupt enable.

PFCTRL

Bit 5: Peripheral flow controller.

DIR

Bits 6-7: Data transfer direction.

CIRC

Bit 8: Circular mode.

PINC

Bit 9: Peripheral increment mode.

MINC

Bit 10: Memory increment mode.

PSIZE

Bits 11-12: Peripheral data size.

MSIZE

Bits 13-14: Memory data size.

PINCOS

Bit 15: Peripheral increment offset size.

PL

Bits 16-17: Priority level.

DBM

Bit 18: Double buffer mode.

CT

Bit 19: Current target (only in double buffer mode).

ACK

Bit 20: ACK.

PBURST

Bits 21-22: Peripheral burst transfer configuration.

MBURST

Bits 23-24: Memory burst transfer configuration.

CHSEL

Bits 25-27: Channel selection.

S7NDTR

stream x number of data register

Offset: 0xbc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

S7PAR

stream x peripheral address register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

S7M0AR

stream x memory 0 address register

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: Memory 0 address.

S7M1AR

stream x memory 1 address register

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

S7FCR

stream x FIFO control register

Offset: 0xcc, size: 32, reset: 0x00000021, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw 		FS
r 		DMDIS
rw 		FTH
rw
Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

DMDIS

Bit 2: Direct mode disable.

FS

Bits 3-5: FIFO status.

FEIE

Bit 7: FIFO error interrupt enable.

DMA2

0x40026400: DMA controller

48/303 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 LISR
0x4 HISR
0x8 LIFCR
0xc HIFCR
0x10 S0CR
0x14 S0NDTR
0x18 S0PAR
0x1c S0M0AR
0x20 S0M1AR
0x24 S0FCR
0x28 S1CR
0x2c S1NDTR
0x30 S1PAR
0x34 S1M0AR
0x38 S1M1AR
0x3c S1FCR
0x40 S2CR
0x44 S2NDTR
0x48 S2PAR
0x4c S2M0AR
0x50 S2M1AR
0x54 S2FCR
0x58 S3CR
0x5c S3NDTR
0x60 S3PAR
0x64 S3M0AR
0x68 S3M1AR
0x6c S3FCR
0x70 S4CR
0x74 S4NDTR
0x78 S4PAR
0x7c S4M0AR
0x80 S4M1AR
0x84 S4FCR
0x88 S5CR
0x8c S5NDTR
0x90 S5PAR
0x94 S5M0AR
0x98 S5M1AR
0x9c S5FCR
0xa0 S6CR
0xa4 S6NDTR
0xa8 S6PAR
0xac S6M0AR
0xb0 S6M1AR
0xb4 S6FCR
0xb8 S7CR
0xbc S7NDTR
0xc0 S7PAR
0xc4 S7M0AR
0xc8 S7M1AR
0xcc S7FCR
Toggle registers

LISR

low interrupt status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCIF3
r 		HTIF3
r 		TEIF3
r 		DMEIF3
r 		FEIF3
r 		TCIF2
r 		HTIF2
r 		TEIF2
r 		DMEIF2
r 		FEIF2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF1
r 		HTIF1
r 		TEIF1
r 		DMEIF1
r 		FEIF1
r 		TCIF0
r 		HTIF0
r 		TEIF0
r 		DMEIF0
r 		FEIF0
r
Toggle fields

FEIF0

Bit 0: Stream x FIFO error interrupt flag (x=3..0).

DMEIF0

Bit 2: Stream x direct mode error interrupt flag (x=3..0).

TEIF0

Bit 3: Stream x transfer error interrupt flag (x=3..0).

HTIF0

Bit 4: Stream x half transfer interrupt flag (x=3..0).

TCIF0

Bit 5: Stream x transfer complete interrupt flag (x = 3..0).

FEIF1

Bit 6: Stream x FIFO error interrupt flag (x=3..0).

DMEIF1

Bit 8: Stream x direct mode error interrupt flag (x=3..0).

TEIF1

Bit 9: Stream x transfer error interrupt flag (x=3..0).

HTIF1

Bit 10: Stream x half transfer interrupt flag (x=3..0).

TCIF1

Bit 11: Stream x transfer complete interrupt flag (x = 3..0).

FEIF2

Bit 16: Stream x FIFO error interrupt flag (x=3..0).

DMEIF2

Bit 18: Stream x direct mode error interrupt flag (x=3..0).

TEIF2

Bit 19: Stream x transfer error interrupt flag (x=3..0).

HTIF2

Bit 20: Stream x half transfer interrupt flag (x=3..0).

TCIF2

Bit 21: Stream x transfer complete interrupt flag (x = 3..0).

FEIF3

Bit 22: Stream x FIFO error interrupt flag (x=3..0).

DMEIF3

Bit 24: Stream x direct mode error interrupt flag (x=3..0).

TEIF3

Bit 25: Stream x transfer error interrupt flag (x=3..0).

HTIF3

Bit 26: Stream x half transfer interrupt flag (x=3..0).

TCIF3

Bit 27: Stream x transfer complete interrupt flag (x = 3..0).

HISR

high interrupt status register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCIF7
r 		HTIF7
r 		TEIF7
r 		DMEIF7
r 		FEIF7
r 		TCIF6
r 		HTIF6
r 		TEIF6
r 		DMEIF6
r 		FEIF6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF5
r 		HTIF5
r 		TEIF5
r 		DMEIF5
r 		FEIF5
r 		TCIF4
r 		HTIF4
r 		TEIF4
r 		DMEIF4
r 		FEIF4
r
Toggle fields

FEIF4

Bit 0: Stream x FIFO error interrupt flag (x=7..4).

DMEIF4

Bit 2: Stream x direct mode error interrupt flag (x=7..4).

TEIF4

Bit 3: Stream x transfer error interrupt flag (x=7..4).

HTIF4

Bit 4: Stream x half transfer interrupt flag (x=7..4).

TCIF4

Bit 5: Stream x transfer complete interrupt flag (x=7..4).

FEIF5

Bit 6: Stream x FIFO error interrupt flag (x=7..4).

DMEIF5

Bit 8: Stream x direct mode error interrupt flag (x=7..4).

TEIF5

Bit 9: Stream x transfer error interrupt flag (x=7..4).

HTIF5

Bit 10: Stream x half transfer interrupt flag (x=7..4).

TCIF5

Bit 11: Stream x transfer complete interrupt flag (x=7..4).

FEIF6

Bit 16: Stream x FIFO error interrupt flag (x=7..4).

DMEIF6

Bit 18: Stream x direct mode error interrupt flag (x=7..4).

TEIF6

Bit 19: Stream x transfer error interrupt flag (x=7..4).

HTIF6

Bit 20: Stream x half transfer interrupt flag (x=7..4).

TCIF6

Bit 21: Stream x transfer complete interrupt flag (x=7..4).

FEIF7

Bit 22: Stream x FIFO error interrupt flag (x=7..4).

DMEIF7

Bit 24: Stream x direct mode error interrupt flag (x=7..4).

TEIF7

Bit 25: Stream x transfer error interrupt flag (x=7..4).

HTIF7

Bit 26: Stream x half transfer interrupt flag (x=7..4).

TCIF7

Bit 27: Stream x transfer complete interrupt flag (x=7..4).

LIFCR

low interrupt flag clear register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTCIF3
rw 		CHTIF3
rw 		CTEIF3
rw 		CDMEIF3
rw 		CFEIF3
rw 		CTCIF2
rw 		CHTIF2
rw 		CTEIF2
rw 		CDMEIF2
rw 		CFEIF2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTCIF1
rw 		CHTIF1
rw 		CTEIF1
rw 		CDMEIF1
rw 		CFEIF1
rw 		CTCIF0
rw 		CHTIF0
rw 		CTEIF0
rw 		CDMEIF0
rw 		CFEIF0
rw
Toggle fields

CFEIF0

Bit 0: Stream x clear FIFO error interrupt flag (x = 3..0).

CDMEIF0

Bit 2: Stream x clear direct mode error interrupt flag (x = 3..0).

CTEIF0

Bit 3: Stream x clear transfer error interrupt flag (x = 3..0).

CHTIF0

Bit 4: Stream x clear half transfer interrupt flag (x = 3..0).

CTCIF0

Bit 5: Stream x clear transfer complete interrupt flag (x = 3..0).

CFEIF1

Bit 6: Stream x clear FIFO error interrupt flag (x = 3..0).

CDMEIF1

Bit 8: Stream x clear direct mode error interrupt flag (x = 3..0).

CTEIF1

Bit 9: Stream x clear transfer error interrupt flag (x = 3..0).

CHTIF1

Bit 10: Stream x clear half transfer interrupt flag (x = 3..0).

CTCIF1

Bit 11: Stream x clear transfer complete interrupt flag (x = 3..0).

CFEIF2

Bit 16: Stream x clear FIFO error interrupt flag (x = 3..0).

CDMEIF2

Bit 18: Stream x clear direct mode error interrupt flag (x = 3..0).

CTEIF2

Bit 19: Stream x clear transfer error interrupt flag (x = 3..0).

CHTIF2

Bit 20: Stream x clear half transfer interrupt flag (x = 3..0).

CTCIF2

Bit 21: Stream x clear transfer complete interrupt flag (x = 3..0).

CFEIF3

Bit 22: Stream x clear FIFO error interrupt flag (x = 3..0).

CDMEIF3

Bit 24: Stream x clear direct mode error interrupt flag (x = 3..0).

CTEIF3

Bit 25: Stream x clear transfer error interrupt flag (x = 3..0).

CHTIF3

Bit 26: Stream x clear half transfer interrupt flag (x = 3..0).

CTCIF3

Bit 27: Stream x clear transfer complete interrupt flag (x = 3..0).

HIFCR

high interrupt flag clear register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTCIF7
rw 		CHTIF7
rw 		CTEIF7
rw 		CDMEIF7
rw 		CFEIF7
rw 		CTCIF6
rw 		CHTIF6
rw 		CTEIF6
rw 		CDMEIF6
rw 		CFEIF6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTCIF5
rw 		CHTIF5
rw 		CTEIF5
rw 		CDMEIF5
rw 		CFEIF5
rw 		CTCIF4
rw 		CHTIF4
rw 		CTEIF4
rw 		CDMEIF4
rw 		CFEIF4
rw
Toggle fields

CFEIF4

Bit 0: Stream x clear FIFO error interrupt flag (x = 7..4).

CDMEIF4

Bit 2: Stream x clear direct mode error interrupt flag (x = 7..4).

CTEIF4

Bit 3: Stream x clear transfer error interrupt flag (x = 7..4).

CHTIF4

Bit 4: Stream x clear half transfer interrupt flag (x = 7..4).

CTCIF4

Bit 5: Stream x clear transfer complete interrupt flag (x = 7..4).

CFEIF5

Bit 6: Stream x clear FIFO error interrupt flag (x = 7..4).

CDMEIF5

Bit 8: Stream x clear direct mode error interrupt flag (x = 7..4).

CTEIF5

Bit 9: Stream x clear transfer error interrupt flag (x = 7..4).

CHTIF5

Bit 10: Stream x clear half transfer interrupt flag (x = 7..4).

CTCIF5

Bit 11: Stream x clear transfer complete interrupt flag (x = 7..4).

CFEIF6

Bit 16: Stream x clear FIFO error interrupt flag (x = 7..4).

CDMEIF6

Bit 18: Stream x clear direct mode error interrupt flag (x = 7..4).

CTEIF6

Bit 19: Stream x clear transfer error interrupt flag (x = 7..4).

CHTIF6

Bit 20: Stream x clear half transfer interrupt flag (x = 7..4).

CTCIF6

Bit 21: Stream x clear transfer complete interrupt flag (x = 7..4).

CFEIF7

Bit 22: Stream x clear FIFO error interrupt flag (x = 7..4).

CDMEIF7

Bit 24: Stream x clear direct mode error interrupt flag (x = 7..4).

CTEIF7

Bit 25: Stream x clear transfer error interrupt flag (x = 7..4).

CHTIF7

Bit 26: Stream x clear half transfer interrupt flag (x = 7..4).

CTCIF7

Bit 27: Stream x clear transfer complete interrupt flag (x = 7..4).

S0CR

stream x configuration register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHSEL
rw 		MBURST
rw 		PBURST
rw 		CT
rw 		DBM
rw 		PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		PFCTRL
rw 		TCIE
rw 		HTIE
rw 		TEIE
rw 		DMEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

DMEIE

Bit 1: Direct mode error interrupt enable.

TEIE

Bit 2: Transfer error interrupt enable.

HTIE

Bit 3: Half transfer interrupt enable.

TCIE

Bit 4: Transfer complete interrupt enable.

PFCTRL

Bit 5: Peripheral flow controller.

DIR

Bits 6-7: Data transfer direction.

CIRC

Bit 8: Circular mode.

PINC

Bit 9: Peripheral increment mode.

MINC

Bit 10: Memory increment mode.

PSIZE

Bits 11-12: Peripheral data size.

MSIZE

Bits 13-14: Memory data size.

PINCOS

Bit 15: Peripheral increment offset size.

PL

Bits 16-17: Priority level.

DBM

Bit 18: Double buffer mode.

CT

Bit 19: Current target (only in double buffer mode).

PBURST

Bits 21-22: Peripheral burst transfer configuration.

MBURST

Bits 23-24: Memory burst transfer configuration.

CHSEL

Bits 25-27: Channel selection.

S0NDTR

stream x number of data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

S0PAR

stream x peripheral address register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

S0M0AR

stream x memory 0 address register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: Memory 0 address.

S0M1AR

stream x memory 1 address register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

S0FCR

stream x FIFO control register

Offset: 0x24, size: 32, reset: 0x00000021, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw 		FS
r 		DMDIS
rw 		FTH
rw
Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

DMDIS

Bit 2: Direct mode disable.

FS

Bits 3-5: FIFO status.

FEIE

Bit 7: FIFO error interrupt enable.

S1CR

stream x configuration register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHSEL
rw 		MBURST
rw 		PBURST
rw 		ACK
rw 		CT
rw 		DBM
rw 		PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		PFCTRL
rw 		TCIE
rw 		HTIE
rw 		TEIE
rw 		DMEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

DMEIE

Bit 1: Direct mode error interrupt enable.

TEIE

Bit 2: Transfer error interrupt enable.

HTIE

Bit 3: Half transfer interrupt enable.

TCIE

Bit 4: Transfer complete interrupt enable.

PFCTRL

Bit 5: Peripheral flow controller.

DIR

Bits 6-7: Data transfer direction.

CIRC

Bit 8: Circular mode.

PINC

Bit 9: Peripheral increment mode.

MINC

Bit 10: Memory increment mode.

PSIZE

Bits 11-12: Peripheral data size.

MSIZE

Bits 13-14: Memory data size.

PINCOS

Bit 15: Peripheral increment offset size.

PL

Bits 16-17: Priority level.

DBM

Bit 18: Double buffer mode.

CT

Bit 19: Current target (only in double buffer mode).

ACK

Bit 20: ACK.

PBURST

Bits 21-22: Peripheral burst transfer configuration.

MBURST

Bits 23-24: Memory burst transfer configuration.

CHSEL

Bits 25-27: Channel selection.

S1NDTR

stream x number of data register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

S1PAR

stream x peripheral address register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

S1M0AR

stream x memory 0 address register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: Memory 0 address.

S1M1AR

stream x memory 1 address register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

S1FCR

stream x FIFO control register

Offset: 0x3c, size: 32, reset: 0x00000021, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw 		FS
r 		DMDIS
rw 		FTH
rw
Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

DMDIS

Bit 2: Direct mode disable.

FS

Bits 3-5: FIFO status.

FEIE

Bit 7: FIFO error interrupt enable.

S2CR

stream x configuration register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHSEL
rw 		MBURST
rw 		PBURST
rw 		ACK
rw 		CT
rw 		DBM
rw 		PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		PFCTRL
rw 		TCIE
rw 		HTIE
rw 		TEIE
rw 		DMEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

DMEIE

Bit 1: Direct mode error interrupt enable.

TEIE

Bit 2: Transfer error interrupt enable.

HTIE

Bit 3: Half transfer interrupt enable.

TCIE

Bit 4: Transfer complete interrupt enable.

PFCTRL

Bit 5: Peripheral flow controller.

DIR

Bits 6-7: Data transfer direction.

CIRC

Bit 8: Circular mode.

PINC

Bit 9: Peripheral increment mode.

MINC

Bit 10: Memory increment mode.

PSIZE

Bits 11-12: Peripheral data size.

MSIZE

Bits 13-14: Memory data size.

PINCOS

Bit 15: Peripheral increment offset size.

PL

Bits 16-17: Priority level.

DBM

Bit 18: Double buffer mode.

CT

Bit 19: Current target (only in double buffer mode).

ACK

Bit 20: ACK.

PBURST

Bits 21-22: Peripheral burst transfer configuration.

MBURST

Bits 23-24: Memory burst transfer configuration.

CHSEL

Bits 25-27: Channel selection.

S2NDTR

stream x number of data register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

S2PAR

stream x peripheral address register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

S2M0AR

stream x memory 0 address register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: Memory 0 address.

S2M1AR

stream x memory 1 address register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

S2FCR

stream x FIFO control register

Offset: 0x54, size: 32, reset: 0x00000021, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw 		FS
r 		DMDIS
rw 		FTH
rw
Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

DMDIS

Bit 2: Direct mode disable.

FS

Bits 3-5: FIFO status.

FEIE

Bit 7: FIFO error interrupt enable.

S3CR

stream x configuration register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHSEL
rw 		MBURST
rw 		PBURST
rw 		ACK
rw 		CT
rw 		DBM
rw 		PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		PFCTRL
rw 		TCIE
rw 		HTIE
rw 		TEIE
rw 		DMEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

DMEIE

Bit 1: Direct mode error interrupt enable.

TEIE

Bit 2: Transfer error interrupt enable.

HTIE

Bit 3: Half transfer interrupt enable.

TCIE

Bit 4: Transfer complete interrupt enable.

PFCTRL

Bit 5: Peripheral flow controller.

DIR

Bits 6-7: Data transfer direction.

CIRC

Bit 8: Circular mode.

PINC

Bit 9: Peripheral increment mode.

MINC

Bit 10: Memory increment mode.

PSIZE

Bits 11-12: Peripheral data size.

MSIZE

Bits 13-14: Memory data size.

PINCOS

Bit 15: Peripheral increment offset size.

PL

Bits 16-17: Priority level.

DBM

Bit 18: Double buffer mode.

CT

Bit 19: Current target (only in double buffer mode).

ACK

Bit 20: ACK.

PBURST

Bits 21-22: Peripheral burst transfer configuration.

MBURST

Bits 23-24: Memory burst transfer configuration.

CHSEL

Bits 25-27: Channel selection.

S3NDTR

stream x number of data register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

S3PAR

stream x peripheral address register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

S3M0AR

stream x memory 0 address register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: Memory 0 address.

S3M1AR

stream x memory 1 address register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

S3FCR

stream x FIFO control register

Offset: 0x6c, size: 32, reset: 0x00000021, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw 		FS
r 		DMDIS
rw 		FTH
rw
Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

DMDIS

Bit 2: Direct mode disable.

FS

Bits 3-5: FIFO status.

FEIE

Bit 7: FIFO error interrupt enable.

S4CR

stream x configuration register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHSEL
rw 		MBURST
rw 		PBURST
rw 		ACK
rw 		CT
rw 		DBM
rw 		PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		PFCTRL
rw 		TCIE
rw 		HTIE
rw 		TEIE
rw 		DMEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

DMEIE

Bit 1: Direct mode error interrupt enable.

TEIE

Bit 2: Transfer error interrupt enable.

HTIE

Bit 3: Half transfer interrupt enable.

TCIE

Bit 4: Transfer complete interrupt enable.

PFCTRL

Bit 5: Peripheral flow controller.

DIR

Bits 6-7: Data transfer direction.

CIRC

Bit 8: Circular mode.

PINC

Bit 9: Peripheral increment mode.

MINC

Bit 10: Memory increment mode.

PSIZE

Bits 11-12: Peripheral data size.

MSIZE

Bits 13-14: Memory data size.

PINCOS

Bit 15: Peripheral increment offset size.

PL

Bits 16-17: Priority level.

DBM

Bit 18: Double buffer mode.

CT

Bit 19: Current target (only in double buffer mode).

ACK

Bit 20: ACK.

PBURST

Bits 21-22: Peripheral burst transfer configuration.

MBURST

Bits 23-24: Memory burst transfer configuration.

CHSEL

Bits 25-27: Channel selection.

S4NDTR

stream x number of data register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

S4PAR

stream x peripheral address register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

S4M0AR

stream x memory 0 address register

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: Memory 0 address.

S4M1AR

stream x memory 1 address register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

S4FCR

stream x FIFO control register

Offset: 0x84, size: 32, reset: 0x00000021, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw 		FS
r 		DMDIS
rw 		FTH
rw
Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

DMDIS

Bit 2: Direct mode disable.

FS

Bits 3-5: FIFO status.

FEIE

Bit 7: FIFO error interrupt enable.

S5CR

stream x configuration register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHSEL
rw 		MBURST
rw 		PBURST
rw 		ACK
rw 		CT
rw 		DBM
rw 		PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		PFCTRL
rw 		TCIE
rw 		HTIE
rw 		TEIE
rw 		DMEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

DMEIE

Bit 1: Direct mode error interrupt enable.

TEIE

Bit 2: Transfer error interrupt enable.

HTIE

Bit 3: Half transfer interrupt enable.

TCIE

Bit 4: Transfer complete interrupt enable.

PFCTRL

Bit 5: Peripheral flow controller.

DIR

Bits 6-7: Data transfer direction.

CIRC

Bit 8: Circular mode.

PINC

Bit 9: Peripheral increment mode.

MINC

Bit 10: Memory increment mode.

PSIZE

Bits 11-12: Peripheral data size.

MSIZE

Bits 13-14: Memory data size.

PINCOS

Bit 15: Peripheral increment offset size.

PL

Bits 16-17: Priority level.

DBM

Bit 18: Double buffer mode.

CT

Bit 19: Current target (only in double buffer mode).

ACK

Bit 20: ACK.

PBURST

Bits 21-22: Peripheral burst transfer configuration.

MBURST

Bits 23-24: Memory burst transfer configuration.

CHSEL

Bits 25-27: Channel selection.

S5NDTR

stream x number of data register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

S5PAR

stream x peripheral address register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

S5M0AR

stream x memory 0 address register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: Memory 0 address.

S5M1AR

stream x memory 1 address register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

S5FCR

stream x FIFO control register

Offset: 0x9c, size: 32, reset: 0x00000021, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw 		FS
r 		DMDIS
rw 		FTH
rw
Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

DMDIS

Bit 2: Direct mode disable.

FS

Bits 3-5: FIFO status.

FEIE

Bit 7: FIFO error interrupt enable.

S6CR

stream x configuration register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHSEL
rw 		MBURST
rw 		PBURST
rw 		ACK
rw 		CT
rw 		DBM
rw 		PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		PFCTRL
rw 		TCIE
rw 		HTIE
rw 		TEIE
rw 		DMEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

DMEIE

Bit 1: Direct mode error interrupt enable.

TEIE

Bit 2: Transfer error interrupt enable.

HTIE

Bit 3: Half transfer interrupt enable.

TCIE

Bit 4: Transfer complete interrupt enable.

PFCTRL

Bit 5: Peripheral flow controller.

DIR

Bits 6-7: Data transfer direction.

CIRC

Bit 8: Circular mode.

PINC

Bit 9: Peripheral increment mode.

MINC

Bit 10: Memory increment mode.

PSIZE

Bits 11-12: Peripheral data size.

MSIZE

Bits 13-14: Memory data size.

PINCOS

Bit 15: Peripheral increment offset size.

PL

Bits 16-17: Priority level.

DBM

Bit 18: Double buffer mode.

CT

Bit 19: Current target (only in double buffer mode).

ACK

Bit 20: ACK.

PBURST

Bits 21-22: Peripheral burst transfer configuration.

MBURST

Bits 23-24: Memory burst transfer configuration.

CHSEL

Bits 25-27: Channel selection.

S6NDTR

stream x number of data register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

S6PAR

stream x peripheral address register

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

S6M0AR

stream x memory 0 address register

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: Memory 0 address.

S6M1AR

stream x memory 1 address register

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

S6FCR

stream x FIFO control register

Offset: 0xb4, size: 32, reset: 0x00000021, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw 		FS
r 		DMDIS
rw 		FTH
rw
Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

DMDIS

Bit 2: Direct mode disable.

FS

Bits 3-5: FIFO status.

FEIE

Bit 7: FIFO error interrupt enable.

S7CR

stream x configuration register

Offset: 0xb8, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHSEL
rw 		MBURST
rw 		PBURST
rw 		ACK
rw 		CT
rw 		DBM
rw 		PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		PFCTRL
rw 		TCIE
rw 		HTIE
rw 		TEIE
rw 		DMEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

DMEIE

Bit 1: Direct mode error interrupt enable.

TEIE

Bit 2: Transfer error interrupt enable.

HTIE

Bit 3: Half transfer interrupt enable.

TCIE

Bit 4: Transfer complete interrupt enable.

PFCTRL

Bit 5: Peripheral flow controller.

DIR

Bits 6-7: Data transfer direction.

CIRC

Bit 8: Circular mode.

PINC

Bit 9: Peripheral increment mode.

MINC

Bit 10: Memory increment mode.

PSIZE

Bits 11-12: Peripheral data size.

MSIZE

Bits 13-14: Memory data size.

PINCOS

Bit 15: Peripheral increment offset size.

PL

Bits 16-17: Priority level.

DBM

Bit 18: Double buffer mode.

CT

Bit 19: Current target (only in double buffer mode).

ACK

Bit 20: ACK.

PBURST

Bits 21-22: Peripheral burst transfer configuration.

MBURST

Bits 23-24: Memory burst transfer configuration.

CHSEL

Bits 25-27: Channel selection.

S7NDTR

stream x number of data register

Offset: 0xbc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

S7PAR

stream x peripheral address register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

S7M0AR

stream x memory 0 address register

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: Memory 0 address.

S7M1AR

stream x memory 1 address register

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

S7FCR

stream x FIFO control register

Offset: 0xcc, size: 32, reset: 0x00000021, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw 		FS
r 		DMDIS
rw 		FTH
rw
Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

DMDIS

Bit 2: Direct mode disable.

FS

Bits 3-5: FIFO status.

FEIE

Bit 7: FIFO error interrupt enable.

DMA2D

0x4002b000: DMA2D controller

6/66 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 ISR
0x8 IFCR
0xc FGMAR
0x10 FGOR
0x14 BGMAR
0x18 BGOR
0x1c FGPFCCR
0x20 FGCOLR
0x24 BGPFCCR
0x28 BGCOLR
0x2c FGCMAR
0x30 BGCMAR
0x34 OPFCCR
0x38 OCOLR
0x3c OMAR
0x40 OOR
0x44 NLR
0x48 LWR
0x4c AMTCR
0x400 FGCLUT
0x800 BGCLUT
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CEIE
rw 		CTCIE
rw 		CAEIE
rw 		TWIE
rw 		TCIE
rw 		TEIE
rw 		ABORT
rw 		SUSP
rw 		START
rw
Toggle fields

START

Bit 0: Start.

SUSP

Bit 1: Suspend.

ABORT

Bit 2: Abort.

TEIE

Bit 8: Transfer error interrupt enable.

TCIE

Bit 9: Transfer complete interrupt enable.

TWIE

Bit 10: Transfer watermark interrupt enable.

CAEIE

Bit 11: CLUT access error interrupt enable.

CTCIE

Bit 12: CLUT transfer complete interrupt enable.

CEIE

Bit 13: Configuration Error Interrupt Enable.

MODE

Bits 16-17: DMA2D mode.

ISR

Interrupt Status Register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CEIF
r 		CTCIF
r 		CAEIF
r 		TWIF
r 		TCIF
r 		TEIF
r
Toggle fields

TEIF

Bit 0: Transfer error interrupt flag.

TCIF

Bit 1: Transfer complete interrupt flag.

TWIF

Bit 2: Transfer watermark interrupt flag.

CAEIF

Bit 3: CLUT access error interrupt flag.

CTCIF

Bit 4: CLUT transfer complete interrupt flag.

CEIF

Bit 5: Configuration error interrupt flag.

IFCR

interrupt flag clear register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCEIF
rw 		CCTCIF
rw 		CAECIF
rw 		CTWIF
rw 		CTCIF
rw 		CTEIF
rw
Toggle fields

CTEIF

Bit 0: Clear Transfer error interrupt flag.

CTCIF

Bit 1: Clear transfer complete interrupt flag.

CTWIF

Bit 2: Clear transfer watermark interrupt flag.

CAECIF

Bit 3: Clear CLUT access error interrupt flag.

CCTCIF

Bit 4: Clear CLUT transfer complete interrupt flag.

CCEIF

Bit 5: Clear configuration error interrupt flag.

FGMAR

foreground memory address register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

FGOR

foreground offset register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 0-13: Line offset.

BGMAR

background memory address register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

BGOR

background offset register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 0-13: Line offset.

FGPFCCR

foreground PFC control register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALPHA
rw 		AM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS
rw 		START
rw 		CCM
rw 		CM
rw
Toggle fields

CM

Bits 0-3: Color mode.

CCM

Bit 4: CLUT color mode.

START

Bit 5: Start.

CS

Bits 8-15: CLUT size.

AM

Bits 16-17: Alpha mode.

ALPHA

Bits 24-31: Alpha value.

FGCOLR

foreground color register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GREEN
rw 		BLUE
rw
Toggle fields

BLUE

Bits 0-7: Blue Value.

GREEN

Bits 8-15: Green Value.

RED

Bits 16-23: Red Value.

BGPFCCR

background PFC control register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALPHA
rw 		AM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS
rw 		START
rw 		CCM
rw 		CM
rw
Toggle fields

CM

Bits 0-3: Color mode.

CCM

Bit 4: CLUT Color mode.

START

Bit 5: Start.

CS

Bits 8-15: CLUT size.

AM

Bits 16-17: Alpha mode.

ALPHA

Bits 24-31: Alpha value.

BGCOLR

background color register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GREEN
rw 		BLUE
rw
Toggle fields

BLUE

Bits 0-7: Blue Value.

GREEN

Bits 8-15: Green Value.

RED

Bits 16-23: Red Value.

FGCMAR

foreground CLUT memory address register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory Address.

BGCMAR

background CLUT memory address register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

OPFCCR

output PFC control register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CM
rw
Toggle fields

CM

Bits 0-2: Color mode.

OCOLR

output color register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
APLHA
rw 		RED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GREEN
rw 		BLUE
rw
Toggle fields

BLUE

Bits 0-7: Blue Value.

GREEN

Bits 8-15: Green Value.

RED

Bits 16-23: Red Value.

APLHA

Bits 24-31: Alpha Channel Value.

OMAR

output memory address register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory Address.

OOR

output offset register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 0-13: Line Offset.

NLR

number of line register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NL
rw
Toggle fields

NL

Bits 0-15: Number of lines.

PL

Bits 16-29: Pixel per lines.

LWR

line watermark register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LW
rw
Toggle fields

LW

Bits 0-15: Line watermark.

AMTCR

AHB master timer configuration register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DT
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

DT

Bits 8-15: Dead Time.

FGCLUT

FGCLUT

Offset: 0x400, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
APLHA
rw 		RED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GREEN
rw 		BLUE
rw
Toggle fields

BLUE

Bits 0-7: BLUE.

GREEN

Bits 8-15: GREEN.

RED

Bits 16-23: RED.

APLHA

Bits 24-31: APLHA.

BGCLUT

BGCLUT

Offset: 0x800, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
APLHA
rw 		RED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GREEN
rw 		BLUE
rw
Toggle fields

BLUE

Bits 0-7: BLUE.

GREEN

Bits 8-15: GREEN.

RED

Bits 16-23: RED.

APLHA

Bits 24-31: APLHA.

Ethernet_DMA

0x40029000: Ethernet: DMA controller operation

10/73 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 DMABMR
0x4 DMATPDR
0x8 DMARPDR
0xc DMARDLAR
0x10 DMATDLAR
0x14 DMASR
0x18 DMAOMR
0x1c DMAIER
0x20 DMAMFBOCR
0x24 DMARSWTR
0x48 DMACHTDR
0x4c DMACHRDR
0x50 DMACHTBAR
0x54 DMACHRBAR
Toggle registers

DMABMR

Ethernet DMA bus mode register

Offset: 0x0, size: 32, reset: 0x00002101, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MB
rw 		AAB
rw 		FPM
rw 		USP
rw 		RDP
rw 		FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTPR
rw 		PBL
rw 		EDFE
rw 		DSL
rw 		DA
rw 		SR
rw
Toggle fields

SR

Bit 0: SR.

DA

Bit 1: DA.

DSL

Bits 2-6: DSL.

EDFE

Bit 7: EDFE.

PBL

Bits 8-13: PBL.

RTPR

Bits 14-15: RTPR.

FB

Bit 16: FB.

RDP

Bits 17-22: RDP.

USP

Bit 23: USP.

FPM

Bit 24: FPM.

AAB

Bit 25: AAB.

MB

Bit 26: MB.

DMATPDR

Ethernet DMA transmit poll demand register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TPD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TPD
rw
Toggle fields

TPD

Bits 0-31: TPD.

DMARPDR

EHERNET DMA receive poll demand register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RPD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RPD
rw
Toggle fields

RPD

Bits 0-31: RPD.

DMARDLAR

Ethernet DMA receive descriptor list address register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRL
rw
Toggle fields

SRL

Bits 0-31: SRL.

DMATDLAR

Ethernet DMA transmit descriptor list address register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STL
rw
Toggle fields

STL

Bits 0-31: STL.

DMASR

Ethernet DMA status register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

6/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSTS
r 		PMTS
r 		MMCS
r 		EBS
r 		TPS
r 		RPS
r 		NIS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AIS
rw 		ERS
rw 		FBES
rw 		ETS
rw 		PWTS
rw 		RPSS
rw 		RBUS
rw 		RS
rw 		TUS
rw 		ROS
rw 		TJTS
rw 		TBUS
rw 		TPSS
rw 		TS
rw
Toggle fields

TS

Bit 0: TS.

TPSS

Bit 1: TPSS.

TBUS

Bit 2: TBUS.

TJTS

Bit 3: TJTS.

ROS

Bit 4: ROS.

TUS

Bit 5: TUS.

RS

Bit 6: RS.

RBUS

Bit 7: RBUS.

RPSS

Bit 8: RPSS.

PWTS

Bit 9: PWTS.

ETS

Bit 10: ETS.

FBES

Bit 13: FBES.

ERS

Bit 14: ERS.

AIS

Bit 15: AIS.

NIS

Bit 16: NIS.

RPS

Bits 17-19: RPS.

TPS

Bits 20-22: TPS.

EBS

Bits 23-25: EBS.

MMCS

Bit 27: MMCS.

PMTS

Bit 28: PMTS.

TSTS

Bit 29: TSTS.

DMAOMR

Ethernet DMA operation mode register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTCEFD
rw 		RSF
rw 		DFRF
rw 		TSF
rw 		FTF
rw 		TTC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TTC
rw 		ST
rw 		FEF
rw 		FUGF
rw 		RTC
rw 		OSF
rw 		SR
rw
Toggle fields

SR

Bit 1: SR.

OSF

Bit 2: OSF.

RTC

Bits 3-4: RTC.

FUGF

Bit 6: FUGF.

FEF

Bit 7: FEF.

ST

Bit 13: ST.

TTC

Bits 14-16: TTC.

FTF

Bit 20: FTF.

TSF

Bit 21: TSF.

DFRF

Bit 24: DFRF.

RSF

Bit 25: RSF.

DTCEFD

Bit 26: DTCEFD.

DMAIER

Ethernet DMA interrupt enable register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NISE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AISE
rw 		ERIE
rw 		FBEIE
rw 		ETIE
rw 		RWTIE
rw 		RPSIE
rw 		RBUIE
rw 		RIE
rw 		TUIE
rw 		ROIE
rw 		TJTIE
rw 		TBUIE
rw 		TPSIE
rw 		TIE
rw
Toggle fields

TIE

Bit 0: TIE.

TPSIE

Bit 1: TPSIE.

TBUIE

Bit 2: TBUIE.

TJTIE

Bit 3: TJTIE.

ROIE

Bit 4: ROIE.

TUIE

Bit 5: TUIE.

RIE

Bit 6: RIE.

RBUIE

Bit 7: RBUIE.

RPSIE

Bit 8: RPSIE.

RWTIE

Bit 9: RWTIE.

ETIE

Bit 10: ETIE.

FBEIE

Bit 13: FBEIE.

ERIE

Bit 14: ERIE.

AISE

Bit 15: AISE.

NISE

Bit 16: NISE.

DMAMFBOCR

Ethernet DMA missed frame and buffer overflow counter register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFOC
rw 		MFA
rw 		OMFC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MFC
rw
Toggle fields

MFC

Bits 0-15: MFC.

OMFC

Bit 16: OMFC.

MFA

Bits 17-27: MFA.

OFOC

Bit 28: OFOC.

DMARSWTR

Ethernet DMA receive status watchdog timer register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSWTC
rw
Toggle fields

RSWTC

Bits 0-7: RSWTC.

DMACHTDR

Ethernet DMA current host transmit descriptor register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HTDAP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HTDAP
r
Toggle fields

HTDAP

Bits 0-31: HTDAP.

DMACHRDR

Ethernet DMA current host receive descriptor register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HRDAP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HRDAP
r
Toggle fields

HRDAP

Bits 0-31: HRDAP.

DMACHTBAR

Ethernet DMA current host transmit buffer address register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HTBAP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HTBAP
r
Toggle fields

HTBAP

Bits 0-31: HTBAP.

DMACHRBAR

Ethernet DMA current host receive buffer address register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HRBAP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HRBAP
r
Toggle fields

HRBAP

Bits 0-31: HRBAP.

Ethernet_MAC

0x40028000: Ethernet: media access control (MAC)

11/82 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MACCR
0x4 MACFFR
0x8 MACHTHR
0xc MACHTLR
0x10 MACMIIAR
0x14 MACMIIDR
0x18 MACFCR
0x1c MACVLANTR
0x2c MACPMTCSR
0x34 MACDBGR
0x38 MACSR
0x3c MACIMR
0x40 MACA0HR
0x44 MACA0LR
0x48 MACA1HR
0x4c MACA1LR
0x50 MACA2HR
0x54 MACA2LR
0x58 MACA3HR
0x5c MACA3LR
Toggle registers

MACCR

Ethernet MAC configuration register

Offset: 0x0, size: 32, reset: 0x00008000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSTF
rw 		WD
rw 		JD
rw 		IFG
rw 		CSD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FES
rw 		ROD
rw 		LM
rw 		DM
rw 		IPCO
rw 		RD
rw 		APCS
rw 		BL
rw 		DC
rw 		TE
rw 		RE
rw
Toggle fields

RE

Bit 2: RE.

TE

Bit 3: TE.

DC

Bit 4: DC.

BL

Bits 5-6: BL.

APCS

Bit 7: APCS.

RD

Bit 9: RD.

IPCO

Bit 10: IPCO.

DM

Bit 11: DM.

LM

Bit 12: LM.

ROD

Bit 13: ROD.

FES

Bit 14: FES.

CSD

Bit 16: CSD.

IFG

Bits 17-19: IFG.

JD

Bit 22: JD.

WD

Bit 23: WD.

CSTF

Bit 25: CSTF.

MACFFR

Ethernet MAC frame filter register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HPF
rw 		SAF
rw 		SAIF
rw 		PCF
rw 		BFD
rw 		RAM
rw 		DAIF
rw 		HM
rw 		HU
rw 		PM
rw
Toggle fields

PM

Bit 0: PM.

HU

Bit 1: HU.

HM

Bit 2: HM.

DAIF

Bit 3: DAIF.

RAM

Bit 4: RAM.

BFD

Bit 5: BFD.

PCF

Bit 6: PCF.

SAIF

Bit 7: SAIF.

SAF

Bit 8: SAF.

HPF

Bit 9: HPF.

RA

Bit 31: RA.

MACHTHR

Ethernet MAC hash table high register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HTH
rw
Toggle fields

HTH

Bits 0-31: HTH.

MACHTLR

Ethernet MAC hash table low register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HTL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HTL
rw
Toggle fields

HTL

Bits 0-31: HTL.

MACMIIAR

Ethernet MAC MII address register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw 		MR
rw 		CR
rw 		MW
rw 		MB
rw
Toggle fields

MB

Bit 0: MB.

MW

Bit 1: MW.

CR

Bits 2-4: CR.

MR

Bits 6-10: MR.

PA

Bits 11-15: PA.

MACMIIDR

Ethernet MAC MII data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TD
rw
Toggle fields

TD

Bits 0-15: TD.

MACFCR

Ethernet MAC flow control register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ZQPD
rw 		PLT
rw 		UPFD
rw 		RFCE
rw 		TFCE
rw 		FCB
rw
Toggle fields

FCB

Bit 0: FCB.

TFCE

Bit 1: TFCE.

RFCE

Bit 2: RFCE.

UPFD

Bit 3: UPFD.

PLT

Bits 4-5: PLT.

ZQPD

Bit 7: ZQPD.

PT

Bits 16-31: PT.

MACVLANTR

Ethernet MAC VLAN tag register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VLANTC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VLANTI
rw
Toggle fields

VLANTI

Bits 0-15: VLANTI.

VLANTC

Bit 16: VLANTC.

MACPMTCSR

Ethernet MAC PMT control and status register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WFFRPR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GU
rw 		WFR
rw 		MPR
rw 		WFE
rw 		MPE
rw 		PD
rw
Toggle fields

PD

Bit 0: PD.

MPE

Bit 1: MPE.

WFE

Bit 2: WFE.

MPR

Bit 5: MPR.

WFR

Bit 6: WFR.

GU

Bit 9: GU.

WFFRPR

Bit 31: WFFRPR.

MACDBGR

Ethernet MAC debug register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCFHP
r 		MCP
r 		MCF
r 		ROR
r 		CSR
r 		CR
r
Toggle fields

CR

Bit 0: CR.

CSR

Bit 1: CSR.

ROR

Bit 2: ROR.

MCF

Bit 3: MCF.

MCP

Bit 4: MCP.

MCFHP

Bit 5: MCFHP.

MACSR

Ethernet MAC interrupt status register

Offset: 0x38, size: 32, reset: 0x00000000, access: Unspecified

4/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSTS
rw 		MMCTS
r 		MMCRS
r 		MMCS
r 		PMTS
r
Toggle fields

PMTS

Bit 3: PMTS.

MMCS

Bit 4: MMCS.

MMCRS

Bit 5: MMCRS.

MMCTS

Bit 6: MMCTS.

TSTS

Bit 9: TSTS.

MACIMR

Ethernet MAC interrupt mask register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSTIM
rw 		PMTIM
rw
Toggle fields

PMTIM

Bit 3: PMTIM.

TSTIM

Bit 9: TSTIM.

MACA0HR

Ethernet MAC address 0 high register

Offset: 0x40, size: 32, reset: 0x0010FFFF, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MO
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MACA0H
rw
Toggle fields

MACA0H

Bits 0-15: MAC address0 high.

MO

Bit 31: Always 1.

MACA0LR

Ethernet MAC address 0 low register

Offset: 0x44, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MACA0L
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MACA0L
rw
Toggle fields

MACA0L

Bits 0-31: 0.

MACA1HR

Ethernet MAC address 1 high register

Offset: 0x48, size: 32, reset: 0x0000FFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AE
rw 		SA
rw 		MBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MACA1H
rw
Toggle fields

MACA1H

Bits 0-15: MACA1H.

MBC

Bits 24-29: MBC.

SA

Bit 30: SA.

AE

Bit 31: AE.

MACA1LR

Ethernet MAC address1 low register

Offset: 0x4c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MACA1LR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MACA1LR
rw
Toggle fields

MACA1LR

Bits 0-31: MACA1LR.

MACA2HR

Ethernet MAC address 2 high register

Offset: 0x50, size: 32, reset: 0x0000FFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AE
rw 		SA
rw 		MBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAC2AH
rw
Toggle fields

MAC2AH

Bits 0-15: MAC2AH.

MBC

Bits 24-29: MBC.

SA

Bit 30: SA.

AE

Bit 31: AE.

MACA2LR

Ethernet MAC address 2 low register

Offset: 0x54, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MACA2L
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MACA2L
rw
Toggle fields

MACA2L

Bits 0-30: MACA2L.

MACA3HR

Ethernet MAC address 3 high register

Offset: 0x58, size: 32, reset: 0x0000FFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AE
rw 		SA
rw 		MBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MACA3H
rw
Toggle fields

MACA3H

Bits 0-15: MACA3H.

MBC

Bits 24-29: MBC.

SA

Bit 30: SA.

AE

Bit 31: AE.

MACA3LR

Ethernet MAC address 3 low register

Offset: 0x5c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBCA3L
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MBCA3L
rw
Toggle fields

MBCA3L

Bits 0-31: MBCA3L.

Ethernet_MMC

0x40028100: Ethernet: MAC management counters

9/24 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MMCCR
0x4 MMCRIR
0x8 MMCTIR
0xc MMCRIMR
0x10 MMCTIMR
0x4c MMCTGFSCCR
0x50 MMCTGFMSCCR
0x68 MMCTGFCR
0x94 MMCRFCECR
0x98 MMCRFAECR
0xc4 MMCRGUFCR
Toggle registers

MMCCR

Ethernet MMC control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCFHP
rw 		MCP
rw 		MCF
rw 		ROR
rw 		CSR
rw 		CR
rw
Toggle fields

CR

Bit 0: CR.

CSR

Bit 1: CSR.

ROR

Bit 2: ROR.

MCF

Bit 3: MCF.

MCP

Bit 4: MCP.

MCFHP

Bit 5: MCFHP.

MMCRIR

Ethernet MMC receive interrupt register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RGUFS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFAES
rw 		RFCES
rw
Toggle fields

RFCES

Bit 5: RFCES.

RFAES

Bit 6: RFAES.

RGUFS

Bit 17: RGUFS.

MMCTIR

Ethernet MMC transmit interrupt register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TGFS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TGFMSCS
r 		TGFSCS
r
Toggle fields

TGFSCS

Bit 14: TGFSCS.

TGFMSCS

Bit 15: TGFMSCS.

TGFS

Bit 21: TGFS.

MMCRIMR

Ethernet MMC receive interrupt mask register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RGUFM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFAEM
rw 		RFCEM
rw
Toggle fields

RFCEM

Bit 5: RFCEM.

RFAEM

Bit 6: RFAEM.

RGUFM

Bit 17: RGUFM.

MMCTIMR

Ethernet MMC transmit interrupt mask register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TGFM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TGFMSCM
rw 		TGFSCM
rw
Toggle fields

TGFSCM

Bit 14: TGFSCM.

TGFMSCM

Bit 15: TGFMSCM.

TGFM

Bit 16: TGFM.

MMCTGFSCCR

Ethernet MMC transmitted good frames after a single collision counter

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TGFSCC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TGFSCC
r
Toggle fields

TGFSCC

Bits 0-31: TGFSCC.

MMCTGFMSCCR

Ethernet MMC transmitted good frames after more than a single collision

Offset: 0x50, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TGFMSCC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TGFMSCC
r
Toggle fields

TGFMSCC

Bits 0-31: TGFMSCC.

MMCTGFCR

Ethernet MMC transmitted good frames counter register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TGFC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TGFC
r
Toggle fields

TGFC

Bits 0-31: HTL.

MMCRFCECR

Ethernet MMC received frames with CRC error counter register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RFCFC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFCFC
r
Toggle fields

RFCFC

Bits 0-31: RFCFC.

MMCRFAECR

Ethernet MMC received frames with alignment error counter register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RFAEC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFAEC
r
Toggle fields

RFAEC

Bits 0-31: RFAEC.

MMCRGUFCR

MMC received good unicast frames counter register

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RGUFC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RGUFC
r
Toggle fields

RGUFC

Bits 0-31: RGUFC.

Ethernet_PTP

0x40028700: Ethernet: Precision time protocol

7/30 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 PTPTSCR
0x4 PTPSSIR
0x8 PTPTSHR
0xc PTPTSLR
0x10 PTPTSHUR
0x14 PTPTSLUR
0x18 PTPTSAR
0x1c PTPTTHR
0x20 PTPTTLR
0x28 PTPTSSR
0x2c PTPPPSCR
Toggle registers

PTPTSCR

Ethernet PTP time stamp control register

Offset: 0x0, size: 32, reset: 0x00002000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSPFFMAE
rw 		TSCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSSMRME
rw 		TSSEME
rw 		TSSIPV4FE
rw 		TSSIPV6FE
rw 		TSSPTPOEFE
rw 		TSPTPPSV2E
rw 		TSSSR
rw 		TSSARFE
rw 		TTSARU
rw 		TSITE
rw 		TSSTU
rw 		TSSTI
rw 		TSFCU
rw 		TSE
rw
Toggle fields

TSE

Bit 0: TSE.

TSFCU

Bit 1: TSFCU.

TSSTI

Bit 2: TSSTI.

TSSTU

Bit 3: TSSTU.

TSITE

Bit 4: TSITE.

TTSARU

Bit 5: TTSARU.

TSSARFE

Bit 8: TSSARFE.

TSSSR

Bit 9: TSSSR.

TSPTPPSV2E

Bit 10: TSPTPPSV2E.

TSSPTPOEFE

Bit 11: TSSPTPOEFE.

TSSIPV6FE

Bit 12: TSSIPV6FE.

TSSIPV4FE

Bit 13: TSSIPV4FE.

TSSEME

Bit 14: TSSEME.

TSSMRME

Bit 15: TSSMRME.

TSCNT

Bits 16-17: TSCNT.

TSPFFMAE

Bit 18: TSPFFMAE.

PTPSSIR

Ethernet PTP subsecond increment register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STSSI
rw
Toggle fields

STSSI

Bits 0-7: STSSI.

PTPTSHR

Ethernet PTP time stamp high register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STS
r
Toggle fields

STS

Bits 0-31: STS.

PTPTSLR

Ethernet PTP time stamp low register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STPNS
r 		STSS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STSS
r
Toggle fields

STSS

Bits 0-30: STSS.

STPNS

Bit 31: STPNS.

PTPTSHUR

Ethernet PTP time stamp high update register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSUS
rw
Toggle fields

TSUS

Bits 0-31: TSUS.

PTPTSLUR

Ethernet PTP time stamp low update register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSUPNS
rw 		TSUSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSUSS
rw
Toggle fields

TSUSS

Bits 0-30: TSUSS.

TSUPNS

Bit 31: TSUPNS.

PTPTSAR

Ethernet PTP time stamp addend register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSA
rw
Toggle fields

TSA

Bits 0-31: TSA.

PTPTTHR

Ethernet PTP target time high register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TTSH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TTSH
rw
Toggle fields

TTSH

Bits 0-31: 0.

PTPTTLR

Ethernet PTP target time low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TTSL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TTSL
rw
Toggle fields

TTSL

Bits 0-31: TTSL.

PTPTSSR

Ethernet PTP time stamp status register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSTTR
r 		TSSO
r
Toggle fields

TSSO

Bit 0: TSSO.

TSTTR

Bit 1: TSTTR.

PTPPPSCR

Ethernet PTP PPS control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSTTR
r 		TSSO
r
Toggle fields

TSSO

Bit 0: TSSO.

TSTTR

Bit 1: TSTTR.

EXTI

0x40013c00: External interrupt/event controller

0/138 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 IMR
0x4 EMR
0x8 RTSR
0xc FTSR
0x10 SWIER
0x14 PR
Toggle registers

IMR

Interrupt mask register (EXTI_IMR)

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MR22
rw 		MR21
rw 		MR20
rw 		MR19
rw 		MR18
rw 		MR17
rw 		MR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR15
rw 		MR14
rw 		MR13
rw 		MR12
rw 		MR11
rw 		MR10
rw 		MR9
rw 		MR8
rw 		MR7
rw 		MR6
rw 		MR5
rw 		MR4
rw 		MR3
rw 		MR2
rw 		MR1
rw 		MR0
rw
Toggle fields

MR0

Bit 0: Interrupt Mask on line 0.

MR1

Bit 1: Interrupt Mask on line 1.

MR2

Bit 2: Interrupt Mask on line 2.

MR3

Bit 3: Interrupt Mask on line 3.

MR4

Bit 4: Interrupt Mask on line 4.

MR5

Bit 5: Interrupt Mask on line 5.

MR6

Bit 6: Interrupt Mask on line 6.

MR7

Bit 7: Interrupt Mask on line 7.

MR8

Bit 8: Interrupt Mask on line 8.

MR9

Bit 9: Interrupt Mask on line 9.

MR10

Bit 10: Interrupt Mask on line 10.

MR11

Bit 11: Interrupt Mask on line 11.

MR12

Bit 12: Interrupt Mask on line 12.

MR13

Bit 13: Interrupt Mask on line 13.

MR14

Bit 14: Interrupt Mask on line 14.

MR15

Bit 15: Interrupt Mask on line 15.

MR16

Bit 16: Interrupt Mask on line 16.

MR17

Bit 17: Interrupt Mask on line 17.

MR18

Bit 18: Interrupt Mask on line 18.

MR19

Bit 19: Interrupt Mask on line 19.

MR20

Bit 20: Interrupt Mask on line 20.

MR21

Bit 21: Interrupt Mask on line 21.

MR22

Bit 22: Interrupt Mask on line 22.

EMR

Event mask register (EXTI_EMR)

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MR22
rw 		MR21
rw 		MR20
rw 		MR19
rw 		MR18
rw 		MR17
rw 		MR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR15
rw 		MR14
rw 		MR13
rw 		MR12
rw 		MR11
rw 		MR10
rw 		MR9
rw 		MR8
rw 		MR7
rw 		MR6
rw 		MR5
rw 		MR4
rw 		MR3
rw 		MR2
rw 		MR1
rw 		MR0
rw
Toggle fields

MR0

Bit 0: Event Mask on line 0.

MR1

Bit 1: Event Mask on line 1.

MR2

Bit 2: Event Mask on line 2.

MR3

Bit 3: Event Mask on line 3.

MR4

Bit 4: Event Mask on line 4.

MR5

Bit 5: Event Mask on line 5.

MR6

Bit 6: Event Mask on line 6.

MR7

Bit 7: Event Mask on line 7.

MR8

Bit 8: Event Mask on line 8.

MR9

Bit 9: Event Mask on line 9.

MR10

Bit 10: Event Mask on line 10.

MR11

Bit 11: Event Mask on line 11.

MR12

Bit 12: Event Mask on line 12.

MR13

Bit 13: Event Mask on line 13.

MR14

Bit 14: Event Mask on line 14.

MR15

Bit 15: Event Mask on line 15.

MR16

Bit 16: Event Mask on line 16.

MR17

Bit 17: Event Mask on line 17.

MR18

Bit 18: Event Mask on line 18.

MR19

Bit 19: Event Mask on line 19.

MR20

Bit 20: Event Mask on line 20.

MR21

Bit 21: Event Mask on line 21.

MR22

Bit 22: Event Mask on line 22.

RTSR

Rising Trigger selection register (EXTI_RTSR)

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TR22
rw 		TR21
rw 		TR20
rw 		TR19
rw 		TR18
rw 		TR17
rw 		TR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TR15
rw 		TR14
rw 		TR13
rw 		TR12
rw 		TR11
rw 		TR10
rw 		TR9
rw 		TR8
rw 		TR7
rw 		TR6
rw 		TR5
rw 		TR4
rw 		TR3
rw 		TR2
rw 		TR1
rw 		TR0
rw
Toggle fields

TR0

Bit 0: Rising trigger event configuration of line 0.

TR1

Bit 1: Rising trigger event configuration of line 1.

TR2

Bit 2: Rising trigger event configuration of line 2.

TR3

Bit 3: Rising trigger event configuration of line 3.

TR4

Bit 4: Rising trigger event configuration of line 4.

TR5

Bit 5: Rising trigger event configuration of line 5.

TR6

Bit 6: Rising trigger event configuration of line 6.

TR7

Bit 7: Rising trigger event configuration of line 7.

TR8

Bit 8: Rising trigger event configuration of line 8.

TR9

Bit 9: Rising trigger event configuration of line 9.

TR10

Bit 10: Rising trigger event configuration of line 10.

TR11

Bit 11: Rising trigger event configuration of line 11.

TR12

Bit 12: Rising trigger event configuration of line 12.

TR13

Bit 13: Rising trigger event configuration of line 13.

TR14

Bit 14: Rising trigger event configuration of line 14.

TR15

Bit 15: Rising trigger event configuration of line 15.

TR16

Bit 16: Rising trigger event configuration of line 16.

TR17

Bit 17: Rising trigger event configuration of line 17.

TR18

Bit 18: Rising trigger event configuration of line 18.

TR19

Bit 19: Rising trigger event configuration of line 19.

TR20

Bit 20: Rising trigger event configuration of line 20.

TR21

Bit 21: Rising trigger event configuration of line 21.

TR22

Bit 22: Rising trigger event configuration of line 22.

FTSR

Falling Trigger selection register (EXTI_FTSR)

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TR22
rw 		TR21
rw 		TR20
rw 		TR19
rw 		TR18
rw 		TR17
rw 		TR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TR15
rw 		TR14
rw 		TR13
rw 		TR12
rw 		TR11
rw 		TR10
rw 		TR9
rw 		TR8
rw 		TR7
rw 		TR6
rw 		TR5
rw 		TR4
rw 		TR3
rw 		TR2
rw 		TR1
rw 		TR0
rw
Toggle fields

TR0

Bit 0: Falling trigger event configuration of line 0.

TR1

Bit 1: Falling trigger event configuration of line 1.

TR2

Bit 2: Falling trigger event configuration of line 2.

TR3

Bit 3: Falling trigger event configuration of line 3.

TR4

Bit 4: Falling trigger event configuration of line 4.

TR5

Bit 5: Falling trigger event configuration of line 5.

TR6

Bit 6: Falling trigger event configuration of line 6.

TR7

Bit 7: Falling trigger event configuration of line 7.

TR8

Bit 8: Falling trigger event configuration of line 8.

TR9

Bit 9: Falling trigger event configuration of line 9.

TR10

Bit 10: Falling trigger event configuration of line 10.

TR11

Bit 11: Falling trigger event configuration of line 11.

TR12

Bit 12: Falling trigger event configuration of line 12.

TR13

Bit 13: Falling trigger event configuration of line 13.

TR14

Bit 14: Falling trigger event configuration of line 14.

TR15

Bit 15: Falling trigger event configuration of line 15.

TR16

Bit 16: Falling trigger event configuration of line 16.

TR17

Bit 17: Falling trigger event configuration of line 17.

TR18

Bit 18: Falling trigger event configuration of line 18.

TR19

Bit 19: Falling trigger event configuration of line 19.

TR20

Bit 20: Falling trigger event configuration of line 20.

TR21

Bit 21: Falling trigger event configuration of line 21.

TR22

Bit 22: Falling trigger event configuration of line 22.

SWIER

Software interrupt event register (EXTI_SWIER)

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWIER22
rw 		SWIER21
rw 		SWIER20
rw 		SWIER19
rw 		SWIER18
rw 		SWIER17
rw 		SWIER16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWIER15
rw 		SWIER14
rw 		SWIER13
rw 		SWIER12
rw 		SWIER11
rw 		SWIER10
rw 		SWIER9
rw 		SWIER8
rw 		SWIER7
rw 		SWIER6
rw 		SWIER5
rw 		SWIER4
rw 		SWIER3
rw 		SWIER2
rw 		SWIER1
rw 		SWIER0
rw
Toggle fields

SWIER0

Bit 0: Software Interrupt on line 0.

SWIER1

Bit 1: Software Interrupt on line 1.

SWIER2

Bit 2: Software Interrupt on line 2.

SWIER3

Bit 3: Software Interrupt on line 3.

SWIER4

Bit 4: Software Interrupt on line 4.

SWIER5

Bit 5: Software Interrupt on line 5.

SWIER6

Bit 6: Software Interrupt on line 6.

SWIER7

Bit 7: Software Interrupt on line 7.

SWIER8

Bit 8: Software Interrupt on line 8.

SWIER9

Bit 9: Software Interrupt on line 9.

SWIER10

Bit 10: Software Interrupt on line 10.

SWIER11

Bit 11: Software Interrupt on line 11.

SWIER12

Bit 12: Software Interrupt on line 12.

SWIER13

Bit 13: Software Interrupt on line 13.

SWIER14

Bit 14: Software Interrupt on line 14.

SWIER15

Bit 15: Software Interrupt on line 15.

SWIER16

Bit 16: Software Interrupt on line 16.

SWIER17

Bit 17: Software Interrupt on line 17.

SWIER18

Bit 18: Software Interrupt on line 18.

SWIER19

Bit 19: Software Interrupt on line 19.

SWIER20

Bit 20: Software Interrupt on line 20.

SWIER21

Bit 21: Software Interrupt on line 21.

SWIER22

Bit 22: Software Interrupt on line 22.

PR

Pending register (EXTI_PR)

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PR22
rw 		PR21
rw 		PR20
rw 		PR19
rw 		PR18
rw 		PR17
rw 		PR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PR15
rw 		PR14
rw 		PR13
rw 		PR12
rw 		PR11
rw 		PR10
rw 		PR9
rw 		PR8
rw 		PR7
rw 		PR6
rw 		PR5
rw 		PR4
rw 		PR3
rw 		PR2
rw 		PR1
rw 		PR0
rw
Toggle fields

PR0

Bit 0: Pending bit 0.

PR1

Bit 1: Pending bit 1.

PR2

Bit 2: Pending bit 2.

PR3

Bit 3: Pending bit 3.

PR4

Bit 4: Pending bit 4.

PR5

Bit 5: Pending bit 5.

PR6

Bit 6: Pending bit 6.

PR7

Bit 7: Pending bit 7.

PR8

Bit 8: Pending bit 8.

PR9

Bit 9: Pending bit 9.

PR10

Bit 10: Pending bit 10.

PR11

Bit 11: Pending bit 11.

PR12

Bit 12: Pending bit 12.

PR13

Bit 13: Pending bit 13.

PR14

Bit 14: Pending bit 14.

PR15

Bit 15: Pending bit 15.

PR16

Bit 16: Pending bit 16.

PR17

Bit 17: Pending bit 17.

PR18

Bit 18: Pending bit 18.

PR19

Bit 19: Pending bit 19.

PR20

Bit 20: Pending bit 20.

PR21

Bit 21: Pending bit 21.

PR22

Bit 22: Pending bit 22.

FLASH

0x40023c00: FLASH

1/37 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ACR
0x4 KEYR
0x8 OPTKEYR
0xc SR
0x10 CR
0x14 OPTCR
0x18 OPTCR1
Toggle registers

ACR

Flash access control register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCRST
rw 		ICRST
w 		DCEN
rw 		ICEN
rw 		PRFTEN
rw 		LATENCY
rw
Toggle fields

LATENCY

Bits 0-2: Latency.

PRFTEN

Bit 8: Prefetch enable.

ICEN

Bit 9: Instruction cache enable.

DCEN

Bit 10: Data cache enable.

ICRST

Bit 11: Instruction cache reset.

DCRST

Bit 12: Data cache reset.

KEYR

Flash key register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-31: FPEC key.

OPTKEYR

Flash option key register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPTKEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPTKEY
w
Toggle fields

OPTKEY

Bits 0-31: Option byte key.

SR

Status register

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

1/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PGSERR
rw 		PGPERR
rw 		PGAERR
rw 		WRPERR
rw 		OPERR
rw 		EOP
rw
Toggle fields

EOP

Bit 0: End of operation.

OPERR

Bit 1: Operation error.

WRPERR

Bit 4: Write protection error.

PGAERR

Bit 5: Programming alignment error.

PGPERR

Bit 6: Programming parallelism error.

PGSERR

Bit 7: Programming sequence error.

BSY

Bit 16: Busy.

CR

Control register

Offset: 0x10, size: 32, reset: 0x80000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw 		ERRIE
rw 		EOPIE
rw 		STRT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MER1
rw 		PSIZE
rw 		SNB
rw 		MER
rw 		SER
rw 		PG
rw
Toggle fields

PG

Bit 0: Programming.

SER

Bit 1: Sector Erase.

MER

Bit 2: Mass Erase of sectors 0 to 11.

SNB

Bits 3-7: Sector number.

PSIZE

Bits 8-9: Program size.

MER1

Bit 15: Mass Erase of sectors 12 to 23.

STRT

Bit 16: Start.

EOPIE

Bit 24: End of operation interrupt enable.

ERRIE

Bit 25: Error interrupt enable.

LOCK

Bit 31: Lock.

OPTCR

Flash option control register

Offset: 0x14, size: 32, reset: 0x0FFFAAED, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPRMOD
rw 		DB1M
rw 		nWRP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDP
rw 		nRST_STDBY
rw 		nRST_STOP
rw 		WDG_SW
rw 		BFB2
rw 		BOR_LEV
rw 		OPTSTRT
rw 		OPTLOCK
rw
Toggle fields

OPTLOCK

Bit 0: Option lock.

OPTSTRT

Bit 1: Option start.

BOR_LEV

Bits 2-3: BOR reset Level.

BFB2

Bit 4: Dual-bank Boot option byte.

WDG_SW

Bit 5: WDG_SW User option bytes.

nRST_STOP

Bit 6: nRST_STOP User option bytes.

nRST_STDBY

Bit 7: nRST_STDBY User option bytes.

RDP

Bits 8-15: Read protect.

nWRP

Bits 16-27: Not write protect.

DB1M

Bit 30: Dual-bank on 1 Mbyte Flash memory devices.

SPRMOD

Bit 31: Selection of protection mode for nWPRi bits.

OPTCR1

Flash option control register 1

Offset: 0x18, size: 32, reset: 0x0FFF0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
nWRP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

nWRP

Bits 16-27: Not write protect.

FMC

0xa0000000: Flexible memory controller

9/226 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 BCR1
0x4 BTR1
0x8 BCR2
0xc BTR2
0x10 BCR3
0x14 BTR3
0x18 BCR4
0x1c BTR4
0x60 PCR2
0x64 SR2
0x68 PMEM2
0x6c PATT2
0x74 ECCR2
0x80 PCR3
0x84 SR3
0x88 PMEM3
0x8c PATT3
0x94 ECCR3
0xa0 PCR4
0xa4 SR4
0xa8 PMEM4
0xac PATT4
0xb0 PIO4
0x104 BWTR1
0x104 BWTR3
0x10c BWTR2
0x10c BWTR4
0x140 SDCR1
0x144 SDCR2
0x148 SDTR1
0x14c SDTR2
0x150 SDCMR
0x154 SDRTR
0x158 SDSR
Toggle registers

BCR1

SRAM/NOR-Flash chip-select control register 1

Offset: 0x0, size: 32, reset: 0x000030DB, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCLKEN
rw 		CBURSTRW
rw 		CPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXTMOD
rw 		WAITEN
rw 		WREN
rw 		WAITCFG
rw 		WRAPMOD
rw 		WAITPOL
rw 		BURSTEN
rw 		FACCEN
rw 		MWID
rw 		MTYP
rw 		MUXEN
rw 		MBKEN
rw
Toggle fields

MBKEN

Bit 0: MBKEN.

MUXEN

Bit 1: MUXEN.

MTYP

Bits 2-3: MTYP.

MWID

Bits 4-5: MWID.

FACCEN

Bit 6: FACCEN.

BURSTEN

Bit 8: BURSTEN.

WAITPOL

Bit 9: WAITPOL.

WRAPMOD

Bit 10: WRAPMOD.

WAITCFG

Bit 11: WAITCFG.

WREN

Bit 12: WREN.

WAITEN

Bit 13: WAITEN.

EXTMOD

Bit 14: EXTMOD.

ASYNCWAIT

Bit 15: ASYNCWAIT.

CPSIZE

Bits 16-18: CPSIZE.

CBURSTRW

Bit 19: CBURSTRW.

CCLKEN

Bit 20: CCLKEN.

BTR1

SRAM/NOR-Flash chip-select timing register 1

Offset: 0x4, size: 32, reset: 0x0FFFFFFF, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw 		DATLAT
rw 		CLKDIV
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: ADDSET.

ADDHLD

Bits 4-7: ADDHLD.

DATAST

Bits 8-15: DATAST.

BUSTURN

Bits 16-19: BUSTURN.

CLKDIV

Bits 20-23: CLKDIV.

DATLAT

Bits 24-27: DATLAT.

ACCMOD

Bits 28-29: ACCMOD.

BCR2

SRAM/NOR-Flash chip-select control register 2

Offset: 0x8, size: 32, reset: 0x000030D2, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CBURSTRW
rw 		CPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXTMOD
rw 		WAITEN
rw 		WREN
rw 		WAITCFG
rw 		WRAPMOD
rw 		WAITPOL
rw 		BURSTEN
rw 		FACCEN
rw 		MWID
rw 		MTYP
rw 		MUXEN
rw 		MBKEN
rw
Toggle fields

MBKEN

Bit 0: MBKEN.

MUXEN

Bit 1: MUXEN.

MTYP

Bits 2-3: MTYP.

MWID

Bits 4-5: MWID.

FACCEN

Bit 6: FACCEN.

BURSTEN

Bit 8: BURSTEN.

WAITPOL

Bit 9: WAITPOL.

WRAPMOD

Bit 10: WRAPMOD.

WAITCFG

Bit 11: WAITCFG.

WREN

Bit 12: WREN.

WAITEN

Bit 13: WAITEN.

EXTMOD

Bit 14: EXTMOD.

ASYNCWAIT

Bit 15: ASYNCWAIT.

CPSIZE

Bits 16-18: CPSIZE.

CBURSTRW

Bit 19: CBURSTRW.

BTR2

SRAM/NOR-Flash chip-select timing register 2

Offset: 0xc, size: 32, reset: 0x0FFFFFFF, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw 		DATLAT
rw 		CLKDIV
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: ADDSET.

ADDHLD

Bits 4-7: ADDHLD.

DATAST

Bits 8-15: DATAST.

BUSTURN

Bits 16-19: BUSTURN.

CLKDIV

Bits 20-23: CLKDIV.

DATLAT

Bits 24-27: DATLAT.

ACCMOD

Bits 28-29: ACCMOD.

BCR3

SRAM/NOR-Flash chip-select control register 3

Offset: 0x10, size: 32, reset: 0x000030D2, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CBURSTRW
rw 		CPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXTMOD
rw 		WAITEN
rw 		WREN
rw 		WAITCFG
rw 		WRAPMOD
rw 		WAITPOL
rw 		BURSTEN
rw 		FACCEN
rw 		MWID
rw 		MTYP
rw 		MUXEN
rw 		MBKEN
rw
Toggle fields

MBKEN

Bit 0: MBKEN.

MUXEN

Bit 1: MUXEN.

MTYP

Bits 2-3: MTYP.

MWID

Bits 4-5: MWID.

FACCEN

Bit 6: FACCEN.

BURSTEN

Bit 8: BURSTEN.

WAITPOL

Bit 9: WAITPOL.

WRAPMOD

Bit 10: WRAPMOD.

WAITCFG

Bit 11: WAITCFG.

WREN

Bit 12: WREN.

WAITEN

Bit 13: WAITEN.

EXTMOD

Bit 14: EXTMOD.

ASYNCWAIT

Bit 15: ASYNCWAIT.

CPSIZE

Bits 16-18: CPSIZE.

CBURSTRW

Bit 19: CBURSTRW.

BTR3

SRAM/NOR-Flash chip-select timing register 3

Offset: 0x14, size: 32, reset: 0x0FFFFFFF, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw 		DATLAT
rw 		CLKDIV
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: ADDSET.

ADDHLD

Bits 4-7: ADDHLD.

DATAST

Bits 8-15: DATAST.

BUSTURN

Bits 16-19: BUSTURN.

CLKDIV

Bits 20-23: CLKDIV.

DATLAT

Bits 24-27: DATLAT.

ACCMOD

Bits 28-29: ACCMOD.

BCR4

SRAM/NOR-Flash chip-select control register 4

Offset: 0x18, size: 32, reset: 0x000030D2, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CBURSTRW
rw 		CPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXTMOD
rw 		WAITEN
rw 		WREN
rw 		WAITCFG
rw 		WRAPMOD
rw 		WAITPOL
rw 		BURSTEN
rw 		FACCEN
rw 		MWID
rw 		MTYP
rw 		MUXEN
rw 		MBKEN
rw
Toggle fields

MBKEN

Bit 0: MBKEN.

MUXEN

Bit 1: MUXEN.

MTYP

Bits 2-3: MTYP.

MWID

Bits 4-5: MWID.

FACCEN

Bit 6: FACCEN.

BURSTEN

Bit 8: BURSTEN.

WAITPOL

Bit 9: WAITPOL.

WRAPMOD

Bit 10: WRAPMOD.

WAITCFG

Bit 11: WAITCFG.

WREN

Bit 12: WREN.

WAITEN

Bit 13: WAITEN.

EXTMOD

Bit 14: EXTMOD.

ASYNCWAIT

Bit 15: ASYNCWAIT.

CPSIZE

Bits 16-18: CPSIZE.

CBURSTRW

Bit 19: CBURSTRW.

BTR4

SRAM/NOR-Flash chip-select timing register 4

Offset: 0x1c, size: 32, reset: 0x0FFFFFFF, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw 		DATLAT
rw 		CLKDIV
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: ADDSET.

ADDHLD

Bits 4-7: ADDHLD.

DATAST

Bits 8-15: DATAST.

BUSTURN

Bits 16-19: BUSTURN.

CLKDIV

Bits 20-23: CLKDIV.

DATLAT

Bits 24-27: DATLAT.

ACCMOD

Bits 28-29: ACCMOD.

PCR2

PC Card/NAND Flash control register 2

Offset: 0x60, size: 32, reset: 0x00000018, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCPS
rw 		TAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAR
rw 		TCLR
rw 		ECCEN
rw 		PWID
rw 		PTYP
rw 		PBKEN
rw 		PWAITEN
rw
Toggle fields

PWAITEN

Bit 1: PWAITEN.

PBKEN

Bit 2: PBKEN.

PTYP

Bit 3: PTYP.

PWID

Bits 4-5: PWID.

ECCEN

Bit 6: ECCEN.

TCLR

Bits 9-12: TCLR.

TAR

Bits 13-16: TAR.

ECCPS

Bits 17-19: ECCPS.

SR2

FIFO status and interrupt register 2

Offset: 0x64, size: 32, reset: 0x00000040, access: Unspecified

1/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEMPT
r 		IFEN
rw 		ILEN
rw 		IREN
rw 		IFS
rw 		ILS
rw 		IRS
rw
Toggle fields

IRS

Bit 0: IRS.

ILS

Bit 1: ILS.

IFS

Bit 2: IFS.

IREN

Bit 3: IREN.

ILEN

Bit 4: ILEN.

IFEN

Bit 5: IFEN.

FEMPT

Bit 6: FEMPT.

PMEM2

Common memory space timing register 2

Offset: 0x68, size: 32, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MEMHIZx
rw 		MEMHOLDx
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEMWAITx
rw 		MEMSETx
rw
Toggle fields

MEMSETx

Bits 0-7: MEMSETx.

MEMWAITx

Bits 8-15: MEMWAITx.

MEMHOLDx

Bits 16-23: MEMHOLDx.

MEMHIZx

Bits 24-31: MEMHIZx.

PATT2

Attribute memory space timing register 2

Offset: 0x6c, size: 32, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATTHIZx
rw 		ATTHOLDx
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATTWAITx
rw 		ATTSETx
rw
Toggle fields

ATTSETx

Bits 0-7: ATTSETx.

ATTWAITx

Bits 8-15: ATTWAITx.

ATTHOLDx

Bits 16-23: ATTHOLDx.

ATTHIZx

Bits 24-31: ATTHIZx.

ECCR2

ECC result register 2

Offset: 0x74, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCx
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECCx
r
Toggle fields

ECCx

Bits 0-31: ECCx.

PCR3

PC Card/NAND Flash control register 3

Offset: 0x80, size: 32, reset: 0x00000018, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCPS
rw 		TAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAR
rw 		TCLR
rw 		ECCEN
rw 		PWID
rw 		PTYP
rw 		PBKEN
rw 		PWAITEN
rw
Toggle fields

PWAITEN

Bit 1: PWAITEN.

PBKEN

Bit 2: PBKEN.

PTYP

Bit 3: PTYP.

PWID

Bits 4-5: PWID.

ECCEN

Bit 6: ECCEN.

TCLR

Bits 9-12: TCLR.

TAR

Bits 13-16: TAR.

ECCPS

Bits 17-19: ECCPS.

SR3

FIFO status and interrupt register 3

Offset: 0x84, size: 32, reset: 0x00000040, access: Unspecified

1/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEMPT
r 		IFEN
rw 		ILEN
rw 		IREN
rw 		IFS
rw 		ILS
rw 		IRS
rw
Toggle fields

IRS

Bit 0: IRS.

ILS

Bit 1: ILS.

IFS

Bit 2: IFS.

IREN

Bit 3: IREN.

ILEN

Bit 4: ILEN.

IFEN

Bit 5: IFEN.

FEMPT

Bit 6: FEMPT.

PMEM3

Common memory space timing register 3

Offset: 0x88, size: 32, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MEMHIZx
rw 		MEMHOLDx
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEMWAITx
rw 		MEMSETx
rw
Toggle fields

MEMSETx

Bits 0-7: MEMSETx.

MEMWAITx

Bits 8-15: MEMWAITx.

MEMHOLDx

Bits 16-23: MEMHOLDx.

MEMHIZx

Bits 24-31: MEMHIZx.

PATT3

Attribute memory space timing register 3

Offset: 0x8c, size: 32, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATTHIZx
rw 		ATTHOLDx
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATTWAITx
rw 		ATTSETx
rw
Toggle fields

ATTSETx

Bits 0-7: ATTSETx.

ATTWAITx

Bits 8-15: ATTWAITx.

ATTHOLDx

Bits 16-23: ATTHOLDx.

ATTHIZx

Bits 24-31: ATTHIZx.

ECCR3

ECC result register 3

Offset: 0x94, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCx
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECCx
r
Toggle fields

ECCx

Bits 0-31: ECCx.

PCR4

PC Card/NAND Flash control register 4

Offset: 0xa0, size: 32, reset: 0x00000018, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCPS
rw 		TAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAR
rw 		TCLR
rw 		ECCEN
rw 		PWID
rw 		PTYP
rw 		PBKEN
rw 		PWAITEN
rw
Toggle fields

PWAITEN

Bit 1: PWAITEN.

PBKEN

Bit 2: PBKEN.

PTYP

Bit 3: PTYP.

PWID

Bits 4-5: PWID.

ECCEN

Bit 6: ECCEN.

TCLR

Bits 9-12: TCLR.

TAR

Bits 13-16: TAR.

ECCPS

Bits 17-19: ECCPS.

SR4

FIFO status and interrupt register 4

Offset: 0xa4, size: 32, reset: 0x00000040, access: Unspecified

1/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEMPT
r 		IFEN
rw 		ILEN
rw 		IREN
rw 		IFS
rw 		ILS
rw 		IRS
rw
Toggle fields

IRS

Bit 0: IRS.

ILS

Bit 1: ILS.

IFS

Bit 2: IFS.

IREN

Bit 3: IREN.

ILEN

Bit 4: ILEN.

IFEN

Bit 5: IFEN.

FEMPT

Bit 6: FEMPT.

PMEM4

Common memory space timing register 4

Offset: 0xa8, size: 32, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MEMHIZx
rw 		MEMHOLDx
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEMWAITx
rw 		MEMSETx
rw
Toggle fields

MEMSETx

Bits 0-7: MEMSETx.

MEMWAITx

Bits 8-15: MEMWAITx.

MEMHOLDx

Bits 16-23: MEMHOLDx.

MEMHIZx

Bits 24-31: MEMHIZx.

PATT4

Attribute memory space timing register 4

Offset: 0xac, size: 32, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATTHIZx
rw 		ATTHOLDx
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATTWAITx
rw 		ATTSETx
rw
Toggle fields

ATTSETx

Bits 0-7: ATTSETx.

ATTWAITx

Bits 8-15: ATTWAITx.

ATTHOLDx

Bits 16-23: ATTHOLDx.

ATTHIZx

Bits 24-31: ATTHIZx.

PIO4

I/O space timing register 4

Offset: 0xb0, size: 32, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IOHIZx
rw 		IOHOLDx
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOWAITx
rw 		IOSETx
rw
Toggle fields

IOSETx

Bits 0-7: IOSETx.

IOWAITx

Bits 8-15: IOWAITx.

IOHOLDx

Bits 16-23: IOHOLDx.

IOHIZx

Bits 24-31: IOHIZx.

BWTR1

SRAM/NOR-Flash write timing registers 1

Offset: 0x104, size: 32, reset: 0x0FFFFFFF, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: ADDSET.

ADDHLD

Bits 4-7: ADDHLD.

DATAST

Bits 8-15: DATAST.

BUSTURN

Bits 16-19: BUSTURN.

ACCMOD

Bits 28-29: ACCMOD.

BWTR3

SRAM/NOR-Flash write timing registers 3

Offset: 0x104, size: 32, reset: 0x0FFFFFFF, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: ADDSET.

ADDHLD

Bits 4-7: ADDHLD.

DATAST

Bits 8-15: DATAST.

BUSTURN

Bits 16-19: BUSTURN.

ACCMOD

Bits 28-29: ACCMOD.

BWTR2

SRAM/NOR-Flash write timing registers 2

Offset: 0x10c, size: 32, reset: 0x0FFFFFFF, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: ADDSET.

ADDHLD

Bits 4-7: ADDHLD.

DATAST

Bits 8-15: DATAST.

BUSTURN

Bits 16-19: BUSTURN.

ACCMOD

Bits 28-29: ACCMOD.

BWTR4

SRAM/NOR-Flash write timing registers 4

Offset: 0x10c, size: 32, reset: 0x0FFFFFFF, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: ADDSET.

ADDHLD

Bits 4-7: ADDHLD.

DATAST

Bits 8-15: DATAST.

BUSTURN

Bits 16-19: BUSTURN.

ACCMOD

Bits 28-29: ACCMOD.

SDCR1

SDRAM Control Register 1

Offset: 0x140, size: 32, reset: 0x000002D0, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RPIPE
rw 		RBURST
rw 		SDCLK
rw 		WP
rw 		CAS
rw 		NB
rw 		MWID
rw 		NR
rw 		NC
rw
Toggle fields

NC

Bits 0-1: Number of column address bits.

NR

Bits 2-3: Number of row address bits.

MWID

Bits 4-5: Memory data bus width.

NB

Bit 6: Number of internal banks.

CAS

Bits 7-8: CAS latency.

WP

Bit 9: Write protection.

SDCLK

Bits 10-11: SDRAM clock configuration.

RBURST

Bit 12: Burst read.

RPIPE

Bits 13-14: Read pipe.

SDCR2

SDRAM Control Register 2

Offset: 0x144, size: 32, reset: 0x000002D0, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLK
rw 		WP
rw 		CAS
rw 		NB
rw 		MWID
rw 		NR
rw 		NC
rw
Toggle fields

NC

Bits 0-1: Number of column address bits.

NR

Bits 2-3: Number of row address bits.

MWID

Bits 4-5: Memory data bus width.

NB

Bit 6: Number of internal banks.

CAS

Bits 7-8: CAS latency.

WP

Bit 9: Write protection.

CLK

Bits 10-11: SDRAM clock configuration.

SDTR1

SDRAM Timing register 1

Offset: 0x148, size: 32, reset: 0x0FFFFFFF, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TRCD
rw 		TRP
rw 		TWR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRC
rw 		TRAS
rw 		TXSR
rw 		TMRD
rw
Toggle fields

TMRD

Bits 0-3: Load Mode Register to Active.

TXSR

Bits 4-7: Exit self-refresh delay.

TRAS

Bits 8-11: Self refresh time.

TRC

Bits 12-15: Row cycle delay.

TWR

Bits 16-19: Recovery delay.

TRP

Bits 20-23: Row precharge delay.

TRCD

Bits 24-27: Row to column delay.

SDTR2

SDRAM Timing register 2

Offset: 0x14c, size: 32, reset: 0x0FFFFFFF, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TRCD
rw 		TRP
rw 		TWR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRC
rw 		TRAS
rw 		TXSR
rw 		TMRD
rw
Toggle fields

TMRD

Bits 0-3: Load Mode Register to Active.

TXSR

Bits 4-7: Exit self-refresh delay.

TRAS

Bits 8-11: Self refresh time.

TRC

Bits 12-15: Row cycle delay.

TWR

Bits 16-19: Recovery delay.

TRP

Bits 20-23: Row precharge delay.

TRCD

Bits 24-27: Row to column delay.

SDCMR

SDRAM Command Mode register

Offset: 0x150, size: 32, reset: 0x00000000, access: Unspecified

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MRD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MRD
rw 		NRFS
rw 		CTB1
w 		CTB2
w 		MODE
w
Toggle fields

MODE

Bits 0-2: Command mode.

CTB2

Bit 3: Command target bank 2.

CTB1

Bit 4: Command target bank 1.

NRFS

Bits 5-8: Number of Auto-refresh.

MRD

Bits 9-21: Mode Register definition.

SDRTR

SDRAM Refresh Timer register

Offset: 0x154, size: 32, reset: 0x00000000, access: Unspecified

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REIE
rw 		COUNT
rw 		CRE
w
Toggle fields

CRE

Bit 0: Clear Refresh error flag.

COUNT

Bits 1-13: Refresh Timer Count.

REIE

Bit 14: RES Interrupt Enable.

SDSR

SDRAM Status register

Offset: 0x158, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		MODES2
r 		MODES1
r 		RE
r
Toggle fields

RE

Bit 0: Refresh error flag.

MODES1

Bits 1-2: Status Mode for Bank 1.

MODES2

Bits 3-4: Status Mode for Bank 2.

BUSY

Bit 5: Busy status.

GPIOA

0x40020000: General-purpose I/Os

16/161 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xA8000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

OT1

Bit 1: Port x configuration bits (y = 0..15).

OT2

Bit 2: Port x configuration bits (y = 0..15).

OT3

Bit 3: Port x configuration bits (y = 0..15).

OT4

Bit 4: Port x configuration bits (y = 0..15).

OT5

Bit 5: Port x configuration bits (y = 0..15).

OT6

Bit 6: Port x configuration bits (y = 0..15).

OT7

Bit 7: Port x configuration bits (y = 0..15).

OT8

Bit 8: Port x configuration bits (y = 0..15).

OT9

Bit 9: Port x configuration bits (y = 0..15).

OT10

Bit 10: Port x configuration bits (y = 0..15).

OT11

Bit 11: Port x configuration bits (y = 0..15).

OT12

Bit 12: Port x configuration bits (y = 0..15).

OT13

Bit 13: Port x configuration bits (y = 0..15).

OT14

Bit 14: Port x configuration bits (y = 0..15).

OT15

Bit 15: Port x configuration bits (y = 0..15).

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x64000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: Port input data (y = 0..15).

IDR1

Bit 1: Port input data (y = 0..15).

IDR2

Bit 2: Port input data (y = 0..15).

IDR3

Bit 3: Port input data (y = 0..15).

IDR4

Bit 4: Port input data (y = 0..15).

IDR5

Bit 5: Port input data (y = 0..15).

IDR6

Bit 6: Port input data (y = 0..15).

IDR7

Bit 7: Port input data (y = 0..15).

IDR8

Bit 8: Port input data (y = 0..15).

IDR9

Bit 9: Port input data (y = 0..15).

IDR10

Bit 10: Port input data (y = 0..15).

IDR11

Bit 11: Port input data (y = 0..15).

IDR12

Bit 12: Port input data (y = 0..15).

IDR13

Bit 13: Port input data (y = 0..15).

IDR14

Bit 14: Port input data (y = 0..15).

IDR15

Bit 15: Port input data (y = 0..15).

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: Port output data (y = 0..15).

ODR1

Bit 1: Port output data (y = 0..15).

ODR2

Bit 2: Port output data (y = 0..15).

ODR3

Bit 3: Port output data (y = 0..15).

ODR4

Bit 4: Port output data (y = 0..15).

ODR5

Bit 5: Port output data (y = 0..15).

ODR6

Bit 6: Port output data (y = 0..15).

ODR7

Bit 7: Port output data (y = 0..15).

ODR8

Bit 8: Port output data (y = 0..15).

ODR9

Bit 9: Port output data (y = 0..15).

ODR10

Bit 10: Port output data (y = 0..15).

ODR11

Bit 11: Port output data (y = 0..15).

ODR12

Bit 12: Port output data (y = 0..15).

ODR13

Bit 13: Port output data (y = 0..15).

ODR14

Bit 14: Port output data (y = 0..15).

ODR15

Bit 15: Port output data (y = 0..15).

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: Port x set bit y (y= 0..15).

BS1

Bit 1: Port x set bit y (y= 0..15).

BS2

Bit 2: Port x set bit y (y= 0..15).

BS3

Bit 3: Port x set bit y (y= 0..15).

BS4

Bit 4: Port x set bit y (y= 0..15).

BS5

Bit 5: Port x set bit y (y= 0..15).

BS6

Bit 6: Port x set bit y (y= 0..15).

BS7

Bit 7: Port x set bit y (y= 0..15).

BS8

Bit 8: Port x set bit y (y= 0..15).

BS9

Bit 9: Port x set bit y (y= 0..15).

BS10

Bit 10: Port x set bit y (y= 0..15).

BS11

Bit 11: Port x set bit y (y= 0..15).

BS12

Bit 12: Port x set bit y (y= 0..15).

BS13

Bit 13: Port x set bit y (y= 0..15).

BS14

Bit 14: Port x set bit y (y= 0..15).

BS15

Bit 15: Port x set bit y (y= 0..15).

BR0

Bit 16: Port x set bit y (y= 0..15).

BR1

Bit 17: Port x reset bit y (y = 0..15).

BR2

Bit 18: Port x reset bit y (y = 0..15).

BR3

Bit 19: Port x reset bit y (y = 0..15).

BR4

Bit 20: Port x reset bit y (y = 0..15).

BR5

Bit 21: Port x reset bit y (y = 0..15).

BR6

Bit 22: Port x reset bit y (y = 0..15).

BR7

Bit 23: Port x reset bit y (y = 0..15).

BR8

Bit 24: Port x reset bit y (y = 0..15).

BR9

Bit 25: Port x reset bit y (y = 0..15).

BR10

Bit 26: Port x reset bit y (y = 0..15).

BR11

Bit 27: Port x reset bit y (y = 0..15).

BR12

Bit 28: Port x reset bit y (y = 0..15).

BR13

Bit 29: Port x reset bit y (y = 0..15).

BR14

Bit 30: Port x reset bit y (y = 0..15).

BR15

Bit 31: Port x reset bit y (y = 0..15).

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

LCK1

Bit 1: Port x lock bit y (y= 0..15).

LCK2

Bit 2: Port x lock bit y (y= 0..15).

LCK3

Bit 3: Port x lock bit y (y= 0..15).

LCK4

Bit 4: Port x lock bit y (y= 0..15).

LCK5

Bit 5: Port x lock bit y (y= 0..15).

LCK6

Bit 6: Port x lock bit y (y= 0..15).

LCK7

Bit 7: Port x lock bit y (y= 0..15).

LCK8

Bit 8: Port x lock bit y (y= 0..15).

LCK9

Bit 9: Port x lock bit y (y= 0..15).

LCK10

Bit 10: Port x lock bit y (y= 0..15).

LCK11

Bit 11: Port x lock bit y (y= 0..15).

LCK12

Bit 12: Port x lock bit y (y= 0..15).

LCK13

Bit 13: Port x lock bit y (y= 0..15).

LCK14

Bit 14: Port x lock bit y (y= 0..15).

LCK15

Bit 15: Port x lock bit y (y= 0..15).

LCKK

Bit 16: Port x lock bit y (y= 0..15).

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL7
rw 		AFRL6
rw 		AFRL5
rw 		AFRL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL3
rw 		AFRL2
rw 		AFRL1
rw 		AFRL0
rw
Toggle fields

AFRL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

AFRL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

AFRL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

AFRL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

AFRL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

AFRL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

AFRL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

AFRL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH15
rw 		AFRH14
rw 		AFRH13
rw 		AFRH12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH11
rw 		AFRH10
rw 		AFRH9
rw 		AFRH8
rw
Toggle fields

AFRH8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

AFRH9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

AFRH10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

AFRH11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

AFRH12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

AFRH13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

AFRH14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

AFRH15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

GPIOB

0x40020400: General-purpose I/Os

16/161 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0x00000280, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

OT1

Bit 1: Port x configuration bits (y = 0..15).

OT2

Bit 2: Port x configuration bits (y = 0..15).

OT3

Bit 3: Port x configuration bits (y = 0..15).

OT4

Bit 4: Port x configuration bits (y = 0..15).

OT5

Bit 5: Port x configuration bits (y = 0..15).

OT6

Bit 6: Port x configuration bits (y = 0..15).

OT7

Bit 7: Port x configuration bits (y = 0..15).

OT8

Bit 8: Port x configuration bits (y = 0..15).

OT9

Bit 9: Port x configuration bits (y = 0..15).

OT10

Bit 10: Port x configuration bits (y = 0..15).

OT11

Bit 11: Port x configuration bits (y = 0..15).

OT12

Bit 12: Port x configuration bits (y = 0..15).

OT13

Bit 13: Port x configuration bits (y = 0..15).

OT14

Bit 14: Port x configuration bits (y = 0..15).

OT15

Bit 15: Port x configuration bits (y = 0..15).

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x000000C0, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000100, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: Port input data (y = 0..15).

IDR1

Bit 1: Port input data (y = 0..15).

IDR2

Bit 2: Port input data (y = 0..15).

IDR3

Bit 3: Port input data (y = 0..15).

IDR4

Bit 4: Port input data (y = 0..15).

IDR5

Bit 5: Port input data (y = 0..15).

IDR6

Bit 6: Port input data (y = 0..15).

IDR7

Bit 7: Port input data (y = 0..15).

IDR8

Bit 8: Port input data (y = 0..15).

IDR9

Bit 9: Port input data (y = 0..15).

IDR10

Bit 10: Port input data (y = 0..15).

IDR11

Bit 11: Port input data (y = 0..15).

IDR12

Bit 12: Port input data (y = 0..15).

IDR13

Bit 13: Port input data (y = 0..15).

IDR14

Bit 14: Port input data (y = 0..15).

IDR15

Bit 15: Port input data (y = 0..15).

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: Port output data (y = 0..15).

ODR1

Bit 1: Port output data (y = 0..15).

ODR2

Bit 2: Port output data (y = 0..15).

ODR3

Bit 3: Port output data (y = 0..15).

ODR4

Bit 4: Port output data (y = 0..15).

ODR5

Bit 5: Port output data (y = 0..15).

ODR6

Bit 6: Port output data (y = 0..15).

ODR7

Bit 7: Port output data (y = 0..15).

ODR8

Bit 8: Port output data (y = 0..15).

ODR9

Bit 9: Port output data (y = 0..15).

ODR10

Bit 10: Port output data (y = 0..15).

ODR11

Bit 11: Port output data (y = 0..15).

ODR12

Bit 12: Port output data (y = 0..15).

ODR13

Bit 13: Port output data (y = 0..15).

ODR14

Bit 14: Port output data (y = 0..15).

ODR15

Bit 15: Port output data (y = 0..15).

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: Port x set bit y (y= 0..15).

BS1

Bit 1: Port x set bit y (y= 0..15).

BS2

Bit 2: Port x set bit y (y= 0..15).

BS3

Bit 3: Port x set bit y (y= 0..15).

BS4

Bit 4: Port x set bit y (y= 0..15).

BS5

Bit 5: Port x set bit y (y= 0..15).

BS6

Bit 6: Port x set bit y (y= 0..15).

BS7

Bit 7: Port x set bit y (y= 0..15).

BS8

Bit 8: Port x set bit y (y= 0..15).

BS9

Bit 9: Port x set bit y (y= 0..15).

BS10

Bit 10: Port x set bit y (y= 0..15).

BS11

Bit 11: Port x set bit y (y= 0..15).

BS12

Bit 12: Port x set bit y (y= 0..15).

BS13

Bit 13: Port x set bit y (y= 0..15).

BS14

Bit 14: Port x set bit y (y= 0..15).

BS15

Bit 15: Port x set bit y (y= 0..15).

BR0

Bit 16: Port x set bit y (y= 0..15).

BR1

Bit 17: Port x reset bit y (y = 0..15).

BR2

Bit 18: Port x reset bit y (y = 0..15).

BR3

Bit 19: Port x reset bit y (y = 0..15).

BR4

Bit 20: Port x reset bit y (y = 0..15).

BR5

Bit 21: Port x reset bit y (y = 0..15).

BR6

Bit 22: Port x reset bit y (y = 0..15).

BR7

Bit 23: Port x reset bit y (y = 0..15).

BR8

Bit 24: Port x reset bit y (y = 0..15).

BR9

Bit 25: Port x reset bit y (y = 0..15).

BR10

Bit 26: Port x reset bit y (y = 0..15).

BR11

Bit 27: Port x reset bit y (y = 0..15).

BR12

Bit 28: Port x reset bit y (y = 0..15).

BR13

Bit 29: Port x reset bit y (y = 0..15).

BR14

Bit 30: Port x reset bit y (y = 0..15).

BR15

Bit 31: Port x reset bit y (y = 0..15).

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

LCK1

Bit 1: Port x lock bit y (y= 0..15).

LCK2

Bit 2: Port x lock bit y (y= 0..15).

LCK3

Bit 3: Port x lock bit y (y= 0..15).

LCK4

Bit 4: Port x lock bit y (y= 0..15).

LCK5

Bit 5: Port x lock bit y (y= 0..15).

LCK6

Bit 6: Port x lock bit y (y= 0..15).

LCK7

Bit 7: Port x lock bit y (y= 0..15).

LCK8

Bit 8: Port x lock bit y (y= 0..15).

LCK9

Bit 9: Port x lock bit y (y= 0..15).

LCK10

Bit 10: Port x lock bit y (y= 0..15).

LCK11

Bit 11: Port x lock bit y (y= 0..15).

LCK12

Bit 12: Port x lock bit y (y= 0..15).

LCK13

Bit 13: Port x lock bit y (y= 0..15).

LCK14

Bit 14: Port x lock bit y (y= 0..15).

LCK15

Bit 15: Port x lock bit y (y= 0..15).

LCKK

Bit 16: Port x lock bit y (y= 0..15).

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL7
rw 		AFRL6
rw 		AFRL5
rw 		AFRL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL3
rw 		AFRL2
rw 		AFRL1
rw 		AFRL0
rw
Toggle fields

AFRL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

AFRL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

AFRL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

AFRL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

AFRL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

AFRL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

AFRL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

AFRL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH15
rw 		AFRH14
rw 		AFRH13
rw 		AFRH12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH11
rw 		AFRH10
rw 		AFRH9
rw 		AFRH8
rw
Toggle fields

AFRH8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

AFRH9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

AFRH10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

AFRH11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

AFRH12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

AFRH13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

AFRH14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

AFRH15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

GPIOC

0x40020800: General-purpose I/Os

16/161 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

OT1

Bit 1: Port x configuration bits (y = 0..15).

OT2

Bit 2: Port x configuration bits (y = 0..15).

OT3

Bit 3: Port x configuration bits (y = 0..15).

OT4

Bit 4: Port x configuration bits (y = 0..15).

OT5

Bit 5: Port x configuration bits (y = 0..15).

OT6

Bit 6: Port x configuration bits (y = 0..15).

OT7

Bit 7: Port x configuration bits (y = 0..15).

OT8

Bit 8: Port x configuration bits (y = 0..15).

OT9

Bit 9: Port x configuration bits (y = 0..15).

OT10

Bit 10: Port x configuration bits (y = 0..15).

OT11

Bit 11: Port x configuration bits (y = 0..15).

OT12

Bit 12: Port x configuration bits (y = 0..15).

OT13

Bit 13: Port x configuration bits (y = 0..15).

OT14

Bit 14: Port x configuration bits (y = 0..15).

OT15

Bit 15: Port x configuration bits (y = 0..15).

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: Port input data (y = 0..15).

IDR1

Bit 1: Port input data (y = 0..15).

IDR2

Bit 2: Port input data (y = 0..15).

IDR3

Bit 3: Port input data (y = 0..15).

IDR4

Bit 4: Port input data (y = 0..15).

IDR5

Bit 5: Port input data (y = 0..15).

IDR6

Bit 6: Port input data (y = 0..15).

IDR7

Bit 7: Port input data (y = 0..15).

IDR8

Bit 8: Port input data (y = 0..15).

IDR9

Bit 9: Port input data (y = 0..15).

IDR10

Bit 10: Port input data (y = 0..15).

IDR11

Bit 11: Port input data (y = 0..15).

IDR12

Bit 12: Port input data (y = 0..15).

IDR13

Bit 13: Port input data (y = 0..15).

IDR14

Bit 14: Port input data (y = 0..15).

IDR15

Bit 15: Port input data (y = 0..15).

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: Port output data (y = 0..15).

ODR1

Bit 1: Port output data (y = 0..15).

ODR2

Bit 2: Port output data (y = 0..15).

ODR3

Bit 3: Port output data (y = 0..15).

ODR4

Bit 4: Port output data (y = 0..15).

ODR5

Bit 5: Port output data (y = 0..15).

ODR6

Bit 6: Port output data (y = 0..15).

ODR7

Bit 7: Port output data (y = 0..15).

ODR8

Bit 8: Port output data (y = 0..15).

ODR9

Bit 9: Port output data (y = 0..15).

ODR10

Bit 10: Port output data (y = 0..15).

ODR11

Bit 11: Port output data (y = 0..15).

ODR12

Bit 12: Port output data (y = 0..15).

ODR13

Bit 13: Port output data (y = 0..15).

ODR14

Bit 14: Port output data (y = 0..15).

ODR15

Bit 15: Port output data (y = 0..15).

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: Port x set bit y (y= 0..15).

BS1

Bit 1: Port x set bit y (y= 0..15).

BS2

Bit 2: Port x set bit y (y= 0..15).

BS3

Bit 3: Port x set bit y (y= 0..15).

BS4

Bit 4: Port x set bit y (y= 0..15).

BS5

Bit 5: Port x set bit y (y= 0..15).

BS6

Bit 6: Port x set bit y (y= 0..15).

BS7

Bit 7: Port x set bit y (y= 0..15).

BS8

Bit 8: Port x set bit y (y= 0..15).

BS9

Bit 9: Port x set bit y (y= 0..15).

BS10

Bit 10: Port x set bit y (y= 0..15).

BS11

Bit 11: Port x set bit y (y= 0..15).

BS12

Bit 12: Port x set bit y (y= 0..15).

BS13

Bit 13: Port x set bit y (y= 0..15).

BS14

Bit 14: Port x set bit y (y= 0..15).

BS15

Bit 15: Port x set bit y (y= 0..15).

BR0

Bit 16: Port x set bit y (y= 0..15).

BR1

Bit 17: Port x reset bit y (y = 0..15).

BR2

Bit 18: Port x reset bit y (y = 0..15).

BR3

Bit 19: Port x reset bit y (y = 0..15).

BR4

Bit 20: Port x reset bit y (y = 0..15).

BR5

Bit 21: Port x reset bit y (y = 0..15).

BR6

Bit 22: Port x reset bit y (y = 0..15).

BR7

Bit 23: Port x reset bit y (y = 0..15).

BR8

Bit 24: Port x reset bit y (y = 0..15).

BR9

Bit 25: Port x reset bit y (y = 0..15).

BR10

Bit 26: Port x reset bit y (y = 0..15).

BR11

Bit 27: Port x reset bit y (y = 0..15).

BR12

Bit 28: Port x reset bit y (y = 0..15).

BR13

Bit 29: Port x reset bit y (y = 0..15).

BR14

Bit 30: Port x reset bit y (y = 0..15).

BR15

Bit 31: Port x reset bit y (y = 0..15).

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

LCK1

Bit 1: Port x lock bit y (y= 0..15).

LCK2

Bit 2: Port x lock bit y (y= 0..15).

LCK3

Bit 3: Port x lock bit y (y= 0..15).

LCK4

Bit 4: Port x lock bit y (y= 0..15).

LCK5

Bit 5: Port x lock bit y (y= 0..15).

LCK6

Bit 6: Port x lock bit y (y= 0..15).

LCK7

Bit 7: Port x lock bit y (y= 0..15).

LCK8

Bit 8: Port x lock bit y (y= 0..15).

LCK9

Bit 9: Port x lock bit y (y= 0..15).

LCK10

Bit 10: Port x lock bit y (y= 0..15).

LCK11

Bit 11: Port x lock bit y (y= 0..15).

LCK12

Bit 12: Port x lock bit y (y= 0..15).

LCK13

Bit 13: Port x lock bit y (y= 0..15).

LCK14

Bit 14: Port x lock bit y (y= 0..15).

LCK15

Bit 15: Port x lock bit y (y= 0..15).

LCKK

Bit 16: Port x lock bit y (y= 0..15).

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL7
rw 		AFRL6
rw 		AFRL5
rw 		AFRL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL3
rw 		AFRL2
rw 		AFRL1
rw 		AFRL0
rw
Toggle fields

AFRL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

AFRL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

AFRL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

AFRL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

AFRL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

AFRL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

AFRL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

AFRL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH15
rw 		AFRH14
rw 		AFRH13
rw 		AFRH12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH11
rw 		AFRH10
rw 		AFRH9
rw 		AFRH8
rw
Toggle fields

AFRH8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

AFRH9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

AFRH10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

AFRH11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

AFRH12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

AFRH13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

AFRH14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

AFRH15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

GPIOD

0x40020c00: General-purpose I/Os

16/161 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

OT1

Bit 1: Port x configuration bits (y = 0..15).

OT2

Bit 2: Port x configuration bits (y = 0..15).

OT3

Bit 3: Port x configuration bits (y = 0..15).

OT4

Bit 4: Port x configuration bits (y = 0..15).

OT5

Bit 5: Port x configuration bits (y = 0..15).

OT6

Bit 6: Port x configuration bits (y = 0..15).

OT7

Bit 7: Port x configuration bits (y = 0..15).

OT8

Bit 8: Port x configuration bits (y = 0..15).

OT9

Bit 9: Port x configuration bits (y = 0..15).

OT10

Bit 10: Port x configuration bits (y = 0..15).

OT11

Bit 11: Port x configuration bits (y = 0..15).

OT12

Bit 12: Port x configuration bits (y = 0..15).

OT13

Bit 13: Port x configuration bits (y = 0..15).

OT14

Bit 14: Port x configuration bits (y = 0..15).

OT15

Bit 15: Port x configuration bits (y = 0..15).

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: Port input data (y = 0..15).

IDR1

Bit 1: Port input data (y = 0..15).

IDR2

Bit 2: Port input data (y = 0..15).

IDR3

Bit 3: Port input data (y = 0..15).

IDR4

Bit 4: Port input data (y = 0..15).

IDR5

Bit 5: Port input data (y = 0..15).

IDR6

Bit 6: Port input data (y = 0..15).

IDR7

Bit 7: Port input data (y = 0..15).

IDR8

Bit 8: Port input data (y = 0..15).

IDR9

Bit 9: Port input data (y = 0..15).

IDR10

Bit 10: Port input data (y = 0..15).

IDR11

Bit 11: Port input data (y = 0..15).

IDR12

Bit 12: Port input data (y = 0..15).

IDR13

Bit 13: Port input data (y = 0..15).

IDR14

Bit 14: Port input data (y = 0..15).

IDR15

Bit 15: Port input data (y = 0..15).

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: Port output data (y = 0..15).

ODR1

Bit 1: Port output data (y = 0..15).

ODR2

Bit 2: Port output data (y = 0..15).

ODR3

Bit 3: Port output data (y = 0..15).

ODR4

Bit 4: Port output data (y = 0..15).

ODR5

Bit 5: Port output data (y = 0..15).

ODR6

Bit 6: Port output data (y = 0..15).

ODR7

Bit 7: Port output data (y = 0..15).

ODR8

Bit 8: Port output data (y = 0..15).

ODR9

Bit 9: Port output data (y = 0..15).

ODR10

Bit 10: Port output data (y = 0..15).

ODR11

Bit 11: Port output data (y = 0..15).

ODR12

Bit 12: Port output data (y = 0..15).

ODR13

Bit 13: Port output data (y = 0..15).

ODR14

Bit 14: Port output data (y = 0..15).

ODR15

Bit 15: Port output data (y = 0..15).

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: Port x set bit y (y= 0..15).

BS1

Bit 1: Port x set bit y (y= 0..15).

BS2

Bit 2: Port x set bit y (y= 0..15).

BS3

Bit 3: Port x set bit y (y= 0..15).

BS4

Bit 4: Port x set bit y (y= 0..15).

BS5

Bit 5: Port x set bit y (y= 0..15).

BS6

Bit 6: Port x set bit y (y= 0..15).

BS7

Bit 7: Port x set bit y (y= 0..15).

BS8

Bit 8: Port x set bit y (y= 0..15).

BS9

Bit 9: Port x set bit y (y= 0..15).

BS10

Bit 10: Port x set bit y (y= 0..15).

BS11

Bit 11: Port x set bit y (y= 0..15).

BS12

Bit 12: Port x set bit y (y= 0..15).

BS13

Bit 13: Port x set bit y (y= 0..15).

BS14

Bit 14: Port x set bit y (y= 0..15).

BS15

Bit 15: Port x set bit y (y= 0..15).

BR0

Bit 16: Port x set bit y (y= 0..15).

BR1

Bit 17: Port x reset bit y (y = 0..15).

BR2

Bit 18: Port x reset bit y (y = 0..15).

BR3

Bit 19: Port x reset bit y (y = 0..15).

BR4

Bit 20: Port x reset bit y (y = 0..15).

BR5

Bit 21: Port x reset bit y (y = 0..15).

BR6

Bit 22: Port x reset bit y (y = 0..15).

BR7

Bit 23: Port x reset bit y (y = 0..15).

BR8

Bit 24: Port x reset bit y (y = 0..15).

BR9

Bit 25: Port x reset bit y (y = 0..15).

BR10

Bit 26: Port x reset bit y (y = 0..15).

BR11

Bit 27: Port x reset bit y (y = 0..15).

BR12

Bit 28: Port x reset bit y (y = 0..15).

BR13

Bit 29: Port x reset bit y (y = 0..15).

BR14

Bit 30: Port x reset bit y (y = 0..15).

BR15

Bit 31: Port x reset bit y (y = 0..15).

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

LCK1

Bit 1: Port x lock bit y (y= 0..15).

LCK2

Bit 2: Port x lock bit y (y= 0..15).

LCK3

Bit 3: Port x lock bit y (y= 0..15).

LCK4

Bit 4: Port x lock bit y (y= 0..15).

LCK5

Bit 5: Port x lock bit y (y= 0..15).

LCK6

Bit 6: Port x lock bit y (y= 0..15).

LCK7

Bit 7: Port x lock bit y (y= 0..15).

LCK8

Bit 8: Port x lock bit y (y= 0..15).

LCK9

Bit 9: Port x lock bit y (y= 0..15).

LCK10

Bit 10: Port x lock bit y (y= 0..15).

LCK11

Bit 11: Port x lock bit y (y= 0..15).

LCK12

Bit 12: Port x lock bit y (y= 0..15).

LCK13

Bit 13: Port x lock bit y (y= 0..15).

LCK14

Bit 14: Port x lock bit y (y= 0..15).

LCK15

Bit 15: Port x lock bit y (y= 0..15).

LCKK

Bit 16: Port x lock bit y (y= 0..15).

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL7
rw 		AFRL6
rw 		AFRL5
rw 		AFRL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL3
rw 		AFRL2
rw 		AFRL1
rw 		AFRL0
rw
Toggle fields

AFRL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

AFRL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

AFRL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

AFRL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

AFRL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

AFRL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

AFRL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

AFRL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH15
rw 		AFRH14
rw 		AFRH13
rw 		AFRH12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH11
rw 		AFRH10
rw 		AFRH9
rw 		AFRH8
rw
Toggle fields

AFRH8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

AFRH9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

AFRH10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

AFRH11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

AFRH12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

AFRH13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

AFRH14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

AFRH15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

GPIOE

0x40021000: General-purpose I/Os

16/161 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

OT1

Bit 1: Port x configuration bits (y = 0..15).

OT2

Bit 2: Port x configuration bits (y = 0..15).

OT3

Bit 3: Port x configuration bits (y = 0..15).

OT4

Bit 4: Port x configuration bits (y = 0..15).

OT5

Bit 5: Port x configuration bits (y = 0..15).

OT6

Bit 6: Port x configuration bits (y = 0..15).

OT7

Bit 7: Port x configuration bits (y = 0..15).

OT8

Bit 8: Port x configuration bits (y = 0..15).

OT9

Bit 9: Port x configuration bits (y = 0..15).

OT10

Bit 10: Port x configuration bits (y = 0..15).

OT11

Bit 11: Port x configuration bits (y = 0..15).

OT12

Bit 12: Port x configuration bits (y = 0..15).

OT13

Bit 13: Port x configuration bits (y = 0..15).

OT14

Bit 14: Port x configuration bits (y = 0..15).

OT15

Bit 15: Port x configuration bits (y = 0..15).

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: Port input data (y = 0..15).

IDR1

Bit 1: Port input data (y = 0..15).

IDR2

Bit 2: Port input data (y = 0..15).

IDR3

Bit 3: Port input data (y = 0..15).

IDR4

Bit 4: Port input data (y = 0..15).

IDR5

Bit 5: Port input data (y = 0..15).

IDR6

Bit 6: Port input data (y = 0..15).

IDR7

Bit 7: Port input data (y = 0..15).

IDR8

Bit 8: Port input data (y = 0..15).

IDR9

Bit 9: Port input data (y = 0..15).

IDR10

Bit 10: Port input data (y = 0..15).

IDR11

Bit 11: Port input data (y = 0..15).

IDR12

Bit 12: Port input data (y = 0..15).

IDR13

Bit 13: Port input data (y = 0..15).

IDR14

Bit 14: Port input data (y = 0..15).

IDR15

Bit 15: Port input data (y = 0..15).

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: Port output data (y = 0..15).

ODR1

Bit 1: Port output data (y = 0..15).

ODR2

Bit 2: Port output data (y = 0..15).

ODR3

Bit 3: Port output data (y = 0..15).

ODR4

Bit 4: Port output data (y = 0..15).

ODR5

Bit 5: Port output data (y = 0..15).

ODR6

Bit 6: Port output data (y = 0..15).

ODR7

Bit 7: Port output data (y = 0..15).

ODR8

Bit 8: Port output data (y = 0..15).

ODR9

Bit 9: Port output data (y = 0..15).

ODR10

Bit 10: Port output data (y = 0..15).

ODR11

Bit 11: Port output data (y = 0..15).

ODR12

Bit 12: Port output data (y = 0..15).

ODR13

Bit 13: Port output data (y = 0..15).

ODR14

Bit 14: Port output data (y = 0..15).

ODR15

Bit 15: Port output data (y = 0..15).

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: Port x set bit y (y= 0..15).

BS1

Bit 1: Port x set bit y (y= 0..15).

BS2

Bit 2: Port x set bit y (y= 0..15).

BS3

Bit 3: Port x set bit y (y= 0..15).

BS4

Bit 4: Port x set bit y (y= 0..15).

BS5

Bit 5: Port x set bit y (y= 0..15).

BS6

Bit 6: Port x set bit y (y= 0..15).

BS7

Bit 7: Port x set bit y (y= 0..15).

BS8

Bit 8: Port x set bit y (y= 0..15).

BS9

Bit 9: Port x set bit y (y= 0..15).

BS10

Bit 10: Port x set bit y (y= 0..15).

BS11

Bit 11: Port x set bit y (y= 0..15).

BS12

Bit 12: Port x set bit y (y= 0..15).

BS13

Bit 13: Port x set bit y (y= 0..15).

BS14

Bit 14: Port x set bit y (y= 0..15).

BS15

Bit 15: Port x set bit y (y= 0..15).

BR0

Bit 16: Port x set bit y (y= 0..15).

BR1

Bit 17: Port x reset bit y (y = 0..15).

BR2

Bit 18: Port x reset bit y (y = 0..15).

BR3

Bit 19: Port x reset bit y (y = 0..15).

BR4

Bit 20: Port x reset bit y (y = 0..15).

BR5

Bit 21: Port x reset bit y (y = 0..15).

BR6

Bit 22: Port x reset bit y (y = 0..15).

BR7

Bit 23: Port x reset bit y (y = 0..15).

BR8

Bit 24: Port x reset bit y (y = 0..15).

BR9

Bit 25: Port x reset bit y (y = 0..15).

BR10

Bit 26: Port x reset bit y (y = 0..15).

BR11

Bit 27: Port x reset bit y (y = 0..15).

BR12

Bit 28: Port x reset bit y (y = 0..15).

BR13

Bit 29: Port x reset bit y (y = 0..15).

BR14

Bit 30: Port x reset bit y (y = 0..15).

BR15

Bit 31: Port x reset bit y (y = 0..15).

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

LCK1

Bit 1: Port x lock bit y (y= 0..15).

LCK2

Bit 2: Port x lock bit y (y= 0..15).

LCK3

Bit 3: Port x lock bit y (y= 0..15).

LCK4

Bit 4: Port x lock bit y (y= 0..15).

LCK5

Bit 5: Port x lock bit y (y= 0..15).

LCK6

Bit 6: Port x lock bit y (y= 0..15).

LCK7

Bit 7: Port x lock bit y (y= 0..15).

LCK8

Bit 8: Port x lock bit y (y= 0..15).

LCK9

Bit 9: Port x lock bit y (y= 0..15).

LCK10

Bit 10: Port x lock bit y (y= 0..15).

LCK11

Bit 11: Port x lock bit y (y= 0..15).

LCK12

Bit 12: Port x lock bit y (y= 0..15).

LCK13

Bit 13: Port x lock bit y (y= 0..15).

LCK14

Bit 14: Port x lock bit y (y= 0..15).

LCK15

Bit 15: Port x lock bit y (y= 0..15).

LCKK

Bit 16: Port x lock bit y (y= 0..15).

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL7
rw 		AFRL6
rw 		AFRL5
rw 		AFRL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL3
rw 		AFRL2
rw 		AFRL1
rw 		AFRL0
rw
Toggle fields

AFRL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

AFRL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

AFRL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

AFRL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

AFRL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

AFRL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

AFRL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

AFRL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH15
rw 		AFRH14
rw 		AFRH13
rw 		AFRH12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH11
rw 		AFRH10
rw 		AFRH9
rw 		AFRH8
rw
Toggle fields

AFRH8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

AFRH9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

AFRH10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

AFRH11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

AFRH12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

AFRH13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

AFRH14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

AFRH15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

GPIOF

0x40021400: General-purpose I/Os

16/161 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

OT1

Bit 1: Port x configuration bits (y = 0..15).

OT2

Bit 2: Port x configuration bits (y = 0..15).

OT3

Bit 3: Port x configuration bits (y = 0..15).

OT4

Bit 4: Port x configuration bits (y = 0..15).

OT5

Bit 5: Port x configuration bits (y = 0..15).

OT6

Bit 6: Port x configuration bits (y = 0..15).

OT7

Bit 7: Port x configuration bits (y = 0..15).

OT8

Bit 8: Port x configuration bits (y = 0..15).

OT9

Bit 9: Port x configuration bits (y = 0..15).

OT10

Bit 10: Port x configuration bits (y = 0..15).

OT11

Bit 11: Port x configuration bits (y = 0..15).

OT12

Bit 12: Port x configuration bits (y = 0..15).

OT13

Bit 13: Port x configuration bits (y = 0..15).

OT14

Bit 14: Port x configuration bits (y = 0..15).

OT15

Bit 15: Port x configuration bits (y = 0..15).

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: Port input data (y = 0..15).

IDR1

Bit 1: Port input data (y = 0..15).

IDR2

Bit 2: Port input data (y = 0..15).

IDR3

Bit 3: Port input data (y = 0..15).

IDR4

Bit 4: Port input data (y = 0..15).

IDR5

Bit 5: Port input data (y = 0..15).

IDR6

Bit 6: Port input data (y = 0..15).

IDR7

Bit 7: Port input data (y = 0..15).

IDR8

Bit 8: Port input data (y = 0..15).

IDR9

Bit 9: Port input data (y = 0..15).

IDR10

Bit 10: Port input data (y = 0..15).

IDR11

Bit 11: Port input data (y = 0..15).

IDR12

Bit 12: Port input data (y = 0..15).

IDR13

Bit 13: Port input data (y = 0..15).

IDR14

Bit 14: Port input data (y = 0..15).

IDR15

Bit 15: Port input data (y = 0..15).

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: Port output data (y = 0..15).

ODR1

Bit 1: Port output data (y = 0..15).

ODR2

Bit 2: Port output data (y = 0..15).

ODR3

Bit 3: Port output data (y = 0..15).

ODR4

Bit 4: Port output data (y = 0..15).

ODR5

Bit 5: Port output data (y = 0..15).

ODR6

Bit 6: Port output data (y = 0..15).

ODR7

Bit 7: Port output data (y = 0..15).

ODR8

Bit 8: Port output data (y = 0..15).

ODR9

Bit 9: Port output data (y = 0..15).

ODR10

Bit 10: Port output data (y = 0..15).

ODR11

Bit 11: Port output data (y = 0..15).

ODR12

Bit 12: Port output data (y = 0..15).

ODR13

Bit 13: Port output data (y = 0..15).

ODR14

Bit 14: Port output data (y = 0..15).

ODR15

Bit 15: Port output data (y = 0..15).

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: Port x set bit y (y= 0..15).

BS1

Bit 1: Port x set bit y (y= 0..15).

BS2

Bit 2: Port x set bit y (y= 0..15).

BS3

Bit 3: Port x set bit y (y= 0..15).

BS4

Bit 4: Port x set bit y (y= 0..15).

BS5

Bit 5: Port x set bit y (y= 0..15).

BS6

Bit 6: Port x set bit y (y= 0..15).

BS7

Bit 7: Port x set bit y (y= 0..15).

BS8

Bit 8: Port x set bit y (y= 0..15).

BS9

Bit 9: Port x set bit y (y= 0..15).

BS10

Bit 10: Port x set bit y (y= 0..15).

BS11

Bit 11: Port x set bit y (y= 0..15).

BS12

Bit 12: Port x set bit y (y= 0..15).

BS13

Bit 13: Port x set bit y (y= 0..15).

BS14

Bit 14: Port x set bit y (y= 0..15).

BS15

Bit 15: Port x set bit y (y= 0..15).

BR0

Bit 16: Port x set bit y (y= 0..15).

BR1

Bit 17: Port x reset bit y (y = 0..15).

BR2

Bit 18: Port x reset bit y (y = 0..15).

BR3

Bit 19: Port x reset bit y (y = 0..15).

BR4

Bit 20: Port x reset bit y (y = 0..15).

BR5

Bit 21: Port x reset bit y (y = 0..15).

BR6

Bit 22: Port x reset bit y (y = 0..15).

BR7

Bit 23: Port x reset bit y (y = 0..15).

BR8

Bit 24: Port x reset bit y (y = 0..15).

BR9

Bit 25: Port x reset bit y (y = 0..15).

BR10

Bit 26: Port x reset bit y (y = 0..15).

BR11

Bit 27: Port x reset bit y (y = 0..15).

BR12

Bit 28: Port x reset bit y (y = 0..15).

BR13

Bit 29: Port x reset bit y (y = 0..15).

BR14

Bit 30: Port x reset bit y (y = 0..15).

BR15

Bit 31: Port x reset bit y (y = 0..15).

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

LCK1

Bit 1: Port x lock bit y (y= 0..15).

LCK2

Bit 2: Port x lock bit y (y= 0..15).

LCK3

Bit 3: Port x lock bit y (y= 0..15).

LCK4

Bit 4: Port x lock bit y (y= 0..15).

LCK5

Bit 5: Port x lock bit y (y= 0..15).

LCK6

Bit 6: Port x lock bit y (y= 0..15).

LCK7

Bit 7: Port x lock bit y (y= 0..15).

LCK8

Bit 8: Port x lock bit y (y= 0..15).

LCK9

Bit 9: Port x lock bit y (y= 0..15).

LCK10

Bit 10: Port x lock bit y (y= 0..15).

LCK11

Bit 11: Port x lock bit y (y= 0..15).

LCK12

Bit 12: Port x lock bit y (y= 0..15).

LCK13

Bit 13: Port x lock bit y (y= 0..15).

LCK14

Bit 14: Port x lock bit y (y= 0..15).

LCK15

Bit 15: Port x lock bit y (y= 0..15).

LCKK

Bit 16: Port x lock bit y (y= 0..15).

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL7
rw 		AFRL6
rw 		AFRL5
rw 		AFRL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL3
rw 		AFRL2
rw 		AFRL1
rw 		AFRL0
rw
Toggle fields

AFRL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

AFRL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

AFRL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

AFRL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

AFRL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

AFRL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

AFRL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

AFRL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH15
rw 		AFRH14
rw 		AFRH13
rw 		AFRH12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH11
rw 		AFRH10
rw 		AFRH9
rw 		AFRH8
rw
Toggle fields

AFRH8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

AFRH9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

AFRH10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

AFRH11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

AFRH12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

AFRH13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

AFRH14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

AFRH15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

GPIOG

0x40021800: General-purpose I/Os

16/161 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

OT1

Bit 1: Port x configuration bits (y = 0..15).

OT2

Bit 2: Port x configuration bits (y = 0..15).

OT3

Bit 3: Port x configuration bits (y = 0..15).

OT4

Bit 4: Port x configuration bits (y = 0..15).

OT5

Bit 5: Port x configuration bits (y = 0..15).

OT6

Bit 6: Port x configuration bits (y = 0..15).

OT7

Bit 7: Port x configuration bits (y = 0..15).

OT8

Bit 8: Port x configuration bits (y = 0..15).

OT9

Bit 9: Port x configuration bits (y = 0..15).

OT10

Bit 10: Port x configuration bits (y = 0..15).

OT11

Bit 11: Port x configuration bits (y = 0..15).

OT12

Bit 12: Port x configuration bits (y = 0..15).

OT13

Bit 13: Port x configuration bits (y = 0..15).

OT14

Bit 14: Port x configuration bits (y = 0..15).

OT15

Bit 15: Port x configuration bits (y = 0..15).

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: Port input data (y = 0..15).

IDR1

Bit 1: Port input data (y = 0..15).

IDR2

Bit 2: Port input data (y = 0..15).

IDR3

Bit 3: Port input data (y = 0..15).

IDR4

Bit 4: Port input data (y = 0..15).

IDR5

Bit 5: Port input data (y = 0..15).

IDR6

Bit 6: Port input data (y = 0..15).

IDR7

Bit 7: Port input data (y = 0..15).

IDR8

Bit 8: Port input data (y = 0..15).

IDR9

Bit 9: Port input data (y = 0..15).

IDR10

Bit 10: Port input data (y = 0..15).

IDR11

Bit 11: Port input data (y = 0..15).

IDR12

Bit 12: Port input data (y = 0..15).

IDR13

Bit 13: Port input data (y = 0..15).

IDR14

Bit 14: Port input data (y = 0..15).

IDR15

Bit 15: Port input data (y = 0..15).

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: Port output data (y = 0..15).

ODR1

Bit 1: Port output data (y = 0..15).

ODR2

Bit 2: Port output data (y = 0..15).

ODR3

Bit 3: Port output data (y = 0..15).

ODR4

Bit 4: Port output data (y = 0..15).

ODR5

Bit 5: Port output data (y = 0..15).

ODR6

Bit 6: Port output data (y = 0..15).

ODR7

Bit 7: Port output data (y = 0..15).

ODR8

Bit 8: Port output data (y = 0..15).

ODR9

Bit 9: Port output data (y = 0..15).

ODR10

Bit 10: Port output data (y = 0..15).

ODR11

Bit 11: Port output data (y = 0..15).

ODR12

Bit 12: Port output data (y = 0..15).

ODR13

Bit 13: Port output data (y = 0..15).

ODR14

Bit 14: Port output data (y = 0..15).

ODR15

Bit 15: Port output data (y = 0..15).

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: Port x set bit y (y= 0..15).

BS1

Bit 1: Port x set bit y (y= 0..15).

BS2

Bit 2: Port x set bit y (y= 0..15).

BS3

Bit 3: Port x set bit y (y= 0..15).

BS4

Bit 4: Port x set bit y (y= 0..15).

BS5

Bit 5: Port x set bit y (y= 0..15).

BS6

Bit 6: Port x set bit y (y= 0..15).

BS7

Bit 7: Port x set bit y (y= 0..15).

BS8

Bit 8: Port x set bit y (y= 0..15).

BS9

Bit 9: Port x set bit y (y= 0..15).

BS10

Bit 10: Port x set bit y (y= 0..15).

BS11

Bit 11: Port x set bit y (y= 0..15).

BS12

Bit 12: Port x set bit y (y= 0..15).

BS13

Bit 13: Port x set bit y (y= 0..15).

BS14

Bit 14: Port x set bit y (y= 0..15).

BS15

Bit 15: Port x set bit y (y= 0..15).

BR0

Bit 16: Port x set bit y (y= 0..15).

BR1

Bit 17: Port x reset bit y (y = 0..15).

BR2

Bit 18: Port x reset bit y (y = 0..15).

BR3

Bit 19: Port x reset bit y (y = 0..15).

BR4

Bit 20: Port x reset bit y (y = 0..15).

BR5

Bit 21: Port x reset bit y (y = 0..15).

BR6

Bit 22: Port x reset bit y (y = 0..15).

BR7

Bit 23: Port x reset bit y (y = 0..15).

BR8

Bit 24: Port x reset bit y (y = 0..15).

BR9

Bit 25: Port x reset bit y (y = 0..15).

BR10

Bit 26: Port x reset bit y (y = 0..15).

BR11

Bit 27: Port x reset bit y (y = 0..15).

BR12

Bit 28: Port x reset bit y (y = 0..15).

BR13

Bit 29: Port x reset bit y (y = 0..15).

BR14

Bit 30: Port x reset bit y (y = 0..15).

BR15

Bit 31: Port x reset bit y (y = 0..15).

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

LCK1

Bit 1: Port x lock bit y (y= 0..15).

LCK2

Bit 2: Port x lock bit y (y= 0..15).

LCK3

Bit 3: Port x lock bit y (y= 0..15).

LCK4

Bit 4: Port x lock bit y (y= 0..15).

LCK5

Bit 5: Port x lock bit y (y= 0..15).

LCK6

Bit 6: Port x lock bit y (y= 0..15).

LCK7

Bit 7: Port x lock bit y (y= 0..15).

LCK8

Bit 8: Port x lock bit y (y= 0..15).

LCK9

Bit 9: Port x lock bit y (y= 0..15).

LCK10

Bit 10: Port x lock bit y (y= 0..15).

LCK11

Bit 11: Port x lock bit y (y= 0..15).

LCK12

Bit 12: Port x lock bit y (y= 0..15).

LCK13

Bit 13: Port x lock bit y (y= 0..15).

LCK14

Bit 14: Port x lock bit y (y= 0..15).

LCK15

Bit 15: Port x lock bit y (y= 0..15).

LCKK

Bit 16: Port x lock bit y (y= 0..15).

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL7
rw 		AFRL6
rw 		AFRL5
rw 		AFRL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL3
rw 		AFRL2
rw 		AFRL1
rw 		AFRL0
rw
Toggle fields

AFRL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

AFRL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

AFRL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

AFRL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

AFRL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

AFRL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

AFRL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

AFRL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH15
rw 		AFRH14
rw 		AFRH13
rw 		AFRH12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH11
rw 		AFRH10
rw 		AFRH9
rw 		AFRH8
rw
Toggle fields

AFRH8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

AFRH9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

AFRH10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

AFRH11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

AFRH12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

AFRH13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

AFRH14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

AFRH15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

GPIOH

0x40021c00: General-purpose I/Os

16/161 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

OT1

Bit 1: Port x configuration bits (y = 0..15).

OT2

Bit 2: Port x configuration bits (y = 0..15).

OT3

Bit 3: Port x configuration bits (y = 0..15).

OT4

Bit 4: Port x configuration bits (y = 0..15).

OT5

Bit 5: Port x configuration bits (y = 0..15).

OT6

Bit 6: Port x configuration bits (y = 0..15).

OT7

Bit 7: Port x configuration bits (y = 0..15).

OT8

Bit 8: Port x configuration bits (y = 0..15).

OT9

Bit 9: Port x configuration bits (y = 0..15).

OT10

Bit 10: Port x configuration bits (y = 0..15).

OT11

Bit 11: Port x configuration bits (y = 0..15).

OT12

Bit 12: Port x configuration bits (y = 0..15).

OT13

Bit 13: Port x configuration bits (y = 0..15).

OT14

Bit 14: Port x configuration bits (y = 0..15).

OT15

Bit 15: Port x configuration bits (y = 0..15).

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: Port input data (y = 0..15).

IDR1

Bit 1: Port input data (y = 0..15).

IDR2

Bit 2: Port input data (y = 0..15).

IDR3

Bit 3: Port input data (y = 0..15).

IDR4

Bit 4: Port input data (y = 0..15).

IDR5

Bit 5: Port input data (y = 0..15).

IDR6

Bit 6: Port input data (y = 0..15).

IDR7

Bit 7: Port input data (y = 0..15).

IDR8

Bit 8: Port input data (y = 0..15).

IDR9

Bit 9: Port input data (y = 0..15).

IDR10

Bit 10: Port input data (y = 0..15).

IDR11

Bit 11: Port input data (y = 0..15).

IDR12

Bit 12: Port input data (y = 0..15).

IDR13

Bit 13: Port input data (y = 0..15).

IDR14

Bit 14: Port input data (y = 0..15).

IDR15

Bit 15: Port input data (y = 0..15).

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: Port output data (y = 0..15).

ODR1

Bit 1: Port output data (y = 0..15).

ODR2

Bit 2: Port output data (y = 0..15).

ODR3

Bit 3: Port output data (y = 0..15).

ODR4

Bit 4: Port output data (y = 0..15).

ODR5

Bit 5: Port output data (y = 0..15).

ODR6

Bit 6: Port output data (y = 0..15).

ODR7

Bit 7: Port output data (y = 0..15).

ODR8

Bit 8: Port output data (y = 0..15).

ODR9

Bit 9: Port output data (y = 0..15).

ODR10

Bit 10: Port output data (y = 0..15).

ODR11

Bit 11: Port output data (y = 0..15).

ODR12

Bit 12: Port output data (y = 0..15).

ODR13

Bit 13: Port output data (y = 0..15).

ODR14

Bit 14: Port output data (y = 0..15).

ODR15

Bit 15: Port output data (y = 0..15).

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: Port x set bit y (y= 0..15).

BS1

Bit 1: Port x set bit y (y= 0..15).

BS2

Bit 2: Port x set bit y (y= 0..15).

BS3

Bit 3: Port x set bit y (y= 0..15).

BS4

Bit 4: Port x set bit y (y= 0..15).

BS5

Bit 5: Port x set bit y (y= 0..15).

BS6

Bit 6: Port x set bit y (y= 0..15).

BS7

Bit 7: Port x set bit y (y= 0..15).

BS8

Bit 8: Port x set bit y (y= 0..15).

BS9

Bit 9: Port x set bit y (y= 0..15).

BS10

Bit 10: Port x set bit y (y= 0..15).

BS11

Bit 11: Port x set bit y (y= 0..15).

BS12

Bit 12: Port x set bit y (y= 0..15).

BS13

Bit 13: Port x set bit y (y= 0..15).

BS14

Bit 14: Port x set bit y (y= 0..15).

BS15

Bit 15: Port x set bit y (y= 0..15).

BR0

Bit 16: Port x set bit y (y= 0..15).

BR1

Bit 17: Port x reset bit y (y = 0..15).

BR2

Bit 18: Port x reset bit y (y = 0..15).

BR3

Bit 19: Port x reset bit y (y = 0..15).

BR4

Bit 20: Port x reset bit y (y = 0..15).

BR5

Bit 21: Port x reset bit y (y = 0..15).

BR6

Bit 22: Port x reset bit y (y = 0..15).

BR7

Bit 23: Port x reset bit y (y = 0..15).

BR8

Bit 24: Port x reset bit y (y = 0..15).

BR9

Bit 25: Port x reset bit y (y = 0..15).

BR10

Bit 26: Port x reset bit y (y = 0..15).

BR11

Bit 27: Port x reset bit y (y = 0..15).

BR12

Bit 28: Port x reset bit y (y = 0..15).

BR13

Bit 29: Port x reset bit y (y = 0..15).

BR14

Bit 30: Port x reset bit y (y = 0..15).

BR15

Bit 31: Port x reset bit y (y = 0..15).

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

LCK1

Bit 1: Port x lock bit y (y= 0..15).

LCK2

Bit 2: Port x lock bit y (y= 0..15).

LCK3

Bit 3: Port x lock bit y (y= 0..15).

LCK4

Bit 4: Port x lock bit y (y= 0..15).

LCK5

Bit 5: Port x lock bit y (y= 0..15).

LCK6

Bit 6: Port x lock bit y (y= 0..15).

LCK7

Bit 7: Port x lock bit y (y= 0..15).

LCK8

Bit 8: Port x lock bit y (y= 0..15).

LCK9

Bit 9: Port x lock bit y (y= 0..15).

LCK10

Bit 10: Port x lock bit y (y= 0..15).

LCK11

Bit 11: Port x lock bit y (y= 0..15).

LCK12

Bit 12: Port x lock bit y (y= 0..15).

LCK13

Bit 13: Port x lock bit y (y= 0..15).

LCK14

Bit 14: Port x lock bit y (y= 0..15).

LCK15

Bit 15: Port x lock bit y (y= 0..15).

LCKK

Bit 16: Port x lock bit y (y= 0..15).

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL7
rw 		AFRL6
rw 		AFRL5
rw 		AFRL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL3
rw 		AFRL2
rw 		AFRL1
rw 		AFRL0
rw
Toggle fields

AFRL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

AFRL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

AFRL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

AFRL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

AFRL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

AFRL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

AFRL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

AFRL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH15
rw 		AFRH14
rw 		AFRH13
rw 		AFRH12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH11
rw 		AFRH10
rw 		AFRH9
rw 		AFRH8
rw
Toggle fields

AFRH8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

AFRH9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

AFRH10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

AFRH11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

AFRH12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

AFRH13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

AFRH14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

AFRH15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

GPIOI

0x40022000: General-purpose I/Os

16/161 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

OT1

Bit 1: Port x configuration bits (y = 0..15).

OT2

Bit 2: Port x configuration bits (y = 0..15).

OT3

Bit 3: Port x configuration bits (y = 0..15).

OT4

Bit 4: Port x configuration bits (y = 0..15).

OT5

Bit 5: Port x configuration bits (y = 0..15).

OT6

Bit 6: Port x configuration bits (y = 0..15).

OT7

Bit 7: Port x configuration bits (y = 0..15).

OT8

Bit 8: Port x configuration bits (y = 0..15).

OT9

Bit 9: Port x configuration bits (y = 0..15).

OT10

Bit 10: Port x configuration bits (y = 0..15).

OT11

Bit 11: Port x configuration bits (y = 0..15).

OT12

Bit 12: Port x configuration bits (y = 0..15).

OT13

Bit 13: Port x configuration bits (y = 0..15).

OT14

Bit 14: Port x configuration bits (y = 0..15).

OT15

Bit 15: Port x configuration bits (y = 0..15).

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: Port input data (y = 0..15).

IDR1

Bit 1: Port input data (y = 0..15).

IDR2

Bit 2: Port input data (y = 0..15).

IDR3

Bit 3: Port input data (y = 0..15).

IDR4

Bit 4: Port input data (y = 0..15).

IDR5

Bit 5: Port input data (y = 0..15).

IDR6

Bit 6: Port input data (y = 0..15).

IDR7

Bit 7: Port input data (y = 0..15).

IDR8

Bit 8: Port input data (y = 0..15).

IDR9

Bit 9: Port input data (y = 0..15).

IDR10

Bit 10: Port input data (y = 0..15).

IDR11

Bit 11: Port input data (y = 0..15).

IDR12

Bit 12: Port input data (y = 0..15).

IDR13

Bit 13: Port input data (y = 0..15).

IDR14

Bit 14: Port input data (y = 0..15).

IDR15

Bit 15: Port input data (y = 0..15).

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: Port output data (y = 0..15).

ODR1

Bit 1: Port output data (y = 0..15).

ODR2

Bit 2: Port output data (y = 0..15).

ODR3

Bit 3: Port output data (y = 0..15).

ODR4

Bit 4: Port output data (y = 0..15).

ODR5

Bit 5: Port output data (y = 0..15).

ODR6

Bit 6: Port output data (y = 0..15).

ODR7

Bit 7: Port output data (y = 0..15).

ODR8

Bit 8: Port output data (y = 0..15).

ODR9

Bit 9: Port output data (y = 0..15).

ODR10

Bit 10: Port output data (y = 0..15).

ODR11

Bit 11: Port output data (y = 0..15).

ODR12

Bit 12: Port output data (y = 0..15).

ODR13

Bit 13: Port output data (y = 0..15).

ODR14

Bit 14: Port output data (y = 0..15).

ODR15

Bit 15: Port output data (y = 0..15).

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: Port x set bit y (y= 0..15).

BS1

Bit 1: Port x set bit y (y= 0..15).

BS2

Bit 2: Port x set bit y (y= 0..15).

BS3

Bit 3: Port x set bit y (y= 0..15).

BS4

Bit 4: Port x set bit y (y= 0..15).

BS5

Bit 5: Port x set bit y (y= 0..15).

BS6

Bit 6: Port x set bit y (y= 0..15).

BS7

Bit 7: Port x set bit y (y= 0..15).

BS8

Bit 8: Port x set bit y (y= 0..15).

BS9

Bit 9: Port x set bit y (y= 0..15).

BS10

Bit 10: Port x set bit y (y= 0..15).

BS11

Bit 11: Port x set bit y (y= 0..15).

BS12

Bit 12: Port x set bit y (y= 0..15).

BS13

Bit 13: Port x set bit y (y= 0..15).

BS14

Bit 14: Port x set bit y (y= 0..15).

BS15

Bit 15: Port x set bit y (y= 0..15).

BR0

Bit 16: Port x set bit y (y= 0..15).

BR1

Bit 17: Port x reset bit y (y = 0..15).

BR2

Bit 18: Port x reset bit y (y = 0..15).

BR3

Bit 19: Port x reset bit y (y = 0..15).

BR4

Bit 20: Port x reset bit y (y = 0..15).

BR5

Bit 21: Port x reset bit y (y = 0..15).

BR6

Bit 22: Port x reset bit y (y = 0..15).

BR7

Bit 23: Port x reset bit y (y = 0..15).

BR8

Bit 24: Port x reset bit y (y = 0..15).

BR9

Bit 25: Port x reset bit y (y = 0..15).

BR10

Bit 26: Port x reset bit y (y = 0..15).

BR11

Bit 27: Port x reset bit y (y = 0..15).

BR12

Bit 28: Port x reset bit y (y = 0..15).

BR13

Bit 29: Port x reset bit y (y = 0..15).

BR14

Bit 30: Port x reset bit y (y = 0..15).

BR15

Bit 31: Port x reset bit y (y = 0..15).

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

LCK1

Bit 1: Port x lock bit y (y= 0..15).

LCK2

Bit 2: Port x lock bit y (y= 0..15).

LCK3

Bit 3: Port x lock bit y (y= 0..15).

LCK4

Bit 4: Port x lock bit y (y= 0..15).

LCK5

Bit 5: Port x lock bit y (y= 0..15).

LCK6

Bit 6: Port x lock bit y (y= 0..15).

LCK7

Bit 7: Port x lock bit y (y= 0..15).

LCK8

Bit 8: Port x lock bit y (y= 0..15).

LCK9

Bit 9: Port x lock bit y (y= 0..15).

LCK10

Bit 10: Port x lock bit y (y= 0..15).

LCK11

Bit 11: Port x lock bit y (y= 0..15).

LCK12

Bit 12: Port x lock bit y (y= 0..15).

LCK13

Bit 13: Port x lock bit y (y= 0..15).

LCK14

Bit 14: Port x lock bit y (y= 0..15).

LCK15

Bit 15: Port x lock bit y (y= 0..15).

LCKK

Bit 16: Port x lock bit y (y= 0..15).

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL7
rw 		AFRL6
rw 		AFRL5
rw 		AFRL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL3
rw 		AFRL2
rw 		AFRL1
rw 		AFRL0
rw
Toggle fields

AFRL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

AFRL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

AFRL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

AFRL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

AFRL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

AFRL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

AFRL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

AFRL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH15
rw 		AFRH14
rw 		AFRH13
rw 		AFRH12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH11
rw 		AFRH10
rw 		AFRH9
rw 		AFRH8
rw
Toggle fields

AFRH8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

AFRH9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

AFRH10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

AFRH11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

AFRH12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

AFRH13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

AFRH14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

AFRH15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

GPIOJ

0x40022400: General-purpose I/Os

16/161 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

OT1

Bit 1: Port x configuration bits (y = 0..15).

OT2

Bit 2: Port x configuration bits (y = 0..15).

OT3

Bit 3: Port x configuration bits (y = 0..15).

OT4

Bit 4: Port x configuration bits (y = 0..15).

OT5

Bit 5: Port x configuration bits (y = 0..15).

OT6

Bit 6: Port x configuration bits (y = 0..15).

OT7

Bit 7: Port x configuration bits (y = 0..15).

OT8

Bit 8: Port x configuration bits (y = 0..15).

OT9

Bit 9: Port x configuration bits (y = 0..15).

OT10

Bit 10: Port x configuration bits (y = 0..15).

OT11

Bit 11: Port x configuration bits (y = 0..15).

OT12

Bit 12: Port x configuration bits (y = 0..15).

OT13

Bit 13: Port x configuration bits (y = 0..15).

OT14

Bit 14: Port x configuration bits (y = 0..15).

OT15

Bit 15: Port x configuration bits (y = 0..15).

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: Port input data (y = 0..15).

IDR1

Bit 1: Port input data (y = 0..15).

IDR2

Bit 2: Port input data (y = 0..15).

IDR3

Bit 3: Port input data (y = 0..15).

IDR4

Bit 4: Port input data (y = 0..15).

IDR5

Bit 5: Port input data (y = 0..15).

IDR6

Bit 6: Port input data (y = 0..15).

IDR7

Bit 7: Port input data (y = 0..15).

IDR8

Bit 8: Port input data (y = 0..15).

IDR9

Bit 9: Port input data (y = 0..15).

IDR10

Bit 10: Port input data (y = 0..15).

IDR11

Bit 11: Port input data (y = 0..15).

IDR12

Bit 12: Port input data (y = 0..15).

IDR13

Bit 13: Port input data (y = 0..15).

IDR14

Bit 14: Port input data (y = 0..15).

IDR15

Bit 15: Port input data (y = 0..15).

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: Port output data (y = 0..15).

ODR1

Bit 1: Port output data (y = 0..15).

ODR2

Bit 2: Port output data (y = 0..15).

ODR3

Bit 3: Port output data (y = 0..15).

ODR4

Bit 4: Port output data (y = 0..15).

ODR5

Bit 5: Port output data (y = 0..15).

ODR6

Bit 6: Port output data (y = 0..15).

ODR7

Bit 7: Port output data (y = 0..15).

ODR8

Bit 8: Port output data (y = 0..15).

ODR9

Bit 9: Port output data (y = 0..15).

ODR10

Bit 10: Port output data (y = 0..15).

ODR11

Bit 11: Port output data (y = 0..15).

ODR12

Bit 12: Port output data (y = 0..15).

ODR13

Bit 13: Port output data (y = 0..15).

ODR14

Bit 14: Port output data (y = 0..15).

ODR15

Bit 15: Port output data (y = 0..15).

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: Port x set bit y (y= 0..15).

BS1

Bit 1: Port x set bit y (y= 0..15).

BS2

Bit 2: Port x set bit y (y= 0..15).

BS3

Bit 3: Port x set bit y (y= 0..15).

BS4

Bit 4: Port x set bit y (y= 0..15).

BS5

Bit 5: Port x set bit y (y= 0..15).

BS6

Bit 6: Port x set bit y (y= 0..15).

BS7

Bit 7: Port x set bit y (y= 0..15).

BS8

Bit 8: Port x set bit y (y= 0..15).

BS9

Bit 9: Port x set bit y (y= 0..15).

BS10

Bit 10: Port x set bit y (y= 0..15).

BS11

Bit 11: Port x set bit y (y= 0..15).

BS12

Bit 12: Port x set bit y (y= 0..15).

BS13

Bit 13: Port x set bit y (y= 0..15).

BS14

Bit 14: Port x set bit y (y= 0..15).

BS15

Bit 15: Port x set bit y (y= 0..15).

BR0

Bit 16: Port x set bit y (y= 0..15).

BR1

Bit 17: Port x reset bit y (y = 0..15).

BR2

Bit 18: Port x reset bit y (y = 0..15).

BR3

Bit 19: Port x reset bit y (y = 0..15).

BR4

Bit 20: Port x reset bit y (y = 0..15).

BR5

Bit 21: Port x reset bit y (y = 0..15).

BR6

Bit 22: Port x reset bit y (y = 0..15).

BR7

Bit 23: Port x reset bit y (y = 0..15).

BR8

Bit 24: Port x reset bit y (y = 0..15).

BR9

Bit 25: Port x reset bit y (y = 0..15).

BR10

Bit 26: Port x reset bit y (y = 0..15).

BR11

Bit 27: Port x reset bit y (y = 0..15).

BR12

Bit 28: Port x reset bit y (y = 0..15).

BR13

Bit 29: Port x reset bit y (y = 0..15).

BR14

Bit 30: Port x reset bit y (y = 0..15).

BR15

Bit 31: Port x reset bit y (y = 0..15).

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

LCK1

Bit 1: Port x lock bit y (y= 0..15).

LCK2

Bit 2: Port x lock bit y (y= 0..15).

LCK3

Bit 3: Port x lock bit y (y= 0..15).

LCK4

Bit 4: Port x lock bit y (y= 0..15).

LCK5

Bit 5: Port x lock bit y (y= 0..15).

LCK6

Bit 6: Port x lock bit y (y= 0..15).

LCK7

Bit 7: Port x lock bit y (y= 0..15).

LCK8

Bit 8: Port x lock bit y (y= 0..15).

LCK9

Bit 9: Port x lock bit y (y= 0..15).

LCK10

Bit 10: Port x lock bit y (y= 0..15).

LCK11

Bit 11: Port x lock bit y (y= 0..15).

LCK12

Bit 12: Port x lock bit y (y= 0..15).

LCK13

Bit 13: Port x lock bit y (y= 0..15).

LCK14

Bit 14: Port x lock bit y (y= 0..15).

LCK15

Bit 15: Port x lock bit y (y= 0..15).

LCKK

Bit 16: Port x lock bit y (y= 0..15).

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL7
rw 		AFRL6
rw 		AFRL5
rw 		AFRL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL3
rw 		AFRL2
rw 		AFRL1
rw 		AFRL0
rw
Toggle fields

AFRL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

AFRL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

AFRL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

AFRL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

AFRL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

AFRL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

AFRL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

AFRL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH15
rw 		AFRH14
rw 		AFRH13
rw 		AFRH12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH11
rw 		AFRH10
rw 		AFRH9
rw 		AFRH8
rw
Toggle fields

AFRH8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

AFRH9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

AFRH10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

AFRH11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

AFRH12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

AFRH13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

AFRH14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

AFRH15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

GPIOK

0x40022800: General-purpose I/Os

16/161 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

OT1

Bit 1: Port x configuration bits (y = 0..15).

OT2

Bit 2: Port x configuration bits (y = 0..15).

OT3

Bit 3: Port x configuration bits (y = 0..15).

OT4

Bit 4: Port x configuration bits (y = 0..15).

OT5

Bit 5: Port x configuration bits (y = 0..15).

OT6

Bit 6: Port x configuration bits (y = 0..15).

OT7

Bit 7: Port x configuration bits (y = 0..15).

OT8

Bit 8: Port x configuration bits (y = 0..15).

OT9

Bit 9: Port x configuration bits (y = 0..15).

OT10

Bit 10: Port x configuration bits (y = 0..15).

OT11

Bit 11: Port x configuration bits (y = 0..15).

OT12

Bit 12: Port x configuration bits (y = 0..15).

OT13

Bit 13: Port x configuration bits (y = 0..15).

OT14

Bit 14: Port x configuration bits (y = 0..15).

OT15

Bit 15: Port x configuration bits (y = 0..15).

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: Port input data (y = 0..15).

IDR1

Bit 1: Port input data (y = 0..15).

IDR2

Bit 2: Port input data (y = 0..15).

IDR3

Bit 3: Port input data (y = 0..15).

IDR4

Bit 4: Port input data (y = 0..15).

IDR5

Bit 5: Port input data (y = 0..15).

IDR6

Bit 6: Port input data (y = 0..15).

IDR7

Bit 7: Port input data (y = 0..15).

IDR8

Bit 8: Port input data (y = 0..15).

IDR9

Bit 9: Port input data (y = 0..15).

IDR10

Bit 10: Port input data (y = 0..15).

IDR11

Bit 11: Port input data (y = 0..15).

IDR12

Bit 12: Port input data (y = 0..15).

IDR13

Bit 13: Port input data (y = 0..15).

IDR14

Bit 14: Port input data (y = 0..15).

IDR15

Bit 15: Port input data (y = 0..15).

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: Port output data (y = 0..15).

ODR1

Bit 1: Port output data (y = 0..15).

ODR2

Bit 2: Port output data (y = 0..15).

ODR3

Bit 3: Port output data (y = 0..15).

ODR4

Bit 4: Port output data (y = 0..15).

ODR5

Bit 5: Port output data (y = 0..15).

ODR6

Bit 6: Port output data (y = 0..15).

ODR7

Bit 7: Port output data (y = 0..15).

ODR8

Bit 8: Port output data (y = 0..15).

ODR9

Bit 9: Port output data (y = 0..15).

ODR10

Bit 10: Port output data (y = 0..15).

ODR11

Bit 11: Port output data (y = 0..15).

ODR12

Bit 12: Port output data (y = 0..15).

ODR13

Bit 13: Port output data (y = 0..15).

ODR14

Bit 14: Port output data (y = 0..15).

ODR15

Bit 15: Port output data (y = 0..15).

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: Port x set bit y (y= 0..15).

BS1

Bit 1: Port x set bit y (y= 0..15).

BS2

Bit 2: Port x set bit y (y= 0..15).

BS3

Bit 3: Port x set bit y (y= 0..15).

BS4

Bit 4: Port x set bit y (y= 0..15).

BS5

Bit 5: Port x set bit y (y= 0..15).

BS6

Bit 6: Port x set bit y (y= 0..15).

BS7

Bit 7: Port x set bit y (y= 0..15).

BS8

Bit 8: Port x set bit y (y= 0..15).

BS9

Bit 9: Port x set bit y (y= 0..15).

BS10

Bit 10: Port x set bit y (y= 0..15).

BS11

Bit 11: Port x set bit y (y= 0..15).

BS12

Bit 12: Port x set bit y (y= 0..15).

BS13

Bit 13: Port x set bit y (y= 0..15).

BS14

Bit 14: Port x set bit y (y= 0..15).

BS15

Bit 15: Port x set bit y (y= 0..15).

BR0

Bit 16: Port x set bit y (y= 0..15).

BR1

Bit 17: Port x reset bit y (y = 0..15).

BR2

Bit 18: Port x reset bit y (y = 0..15).

BR3

Bit 19: Port x reset bit y (y = 0..15).

BR4

Bit 20: Port x reset bit y (y = 0..15).

BR5

Bit 21: Port x reset bit y (y = 0..15).

BR6

Bit 22: Port x reset bit y (y = 0..15).

BR7

Bit 23: Port x reset bit y (y = 0..15).

BR8

Bit 24: Port x reset bit y (y = 0..15).

BR9

Bit 25: Port x reset bit y (y = 0..15).

BR10

Bit 26: Port x reset bit y (y = 0..15).

BR11

Bit 27: Port x reset bit y (y = 0..15).

BR12

Bit 28: Port x reset bit y (y = 0..15).

BR13

Bit 29: Port x reset bit y (y = 0..15).

BR14

Bit 30: Port x reset bit y (y = 0..15).

BR15

Bit 31: Port x reset bit y (y = 0..15).

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

LCK1

Bit 1: Port x lock bit y (y= 0..15).

LCK2

Bit 2: Port x lock bit y (y= 0..15).

LCK3

Bit 3: Port x lock bit y (y= 0..15).

LCK4

Bit 4: Port x lock bit y (y= 0..15).

LCK5

Bit 5: Port x lock bit y (y= 0..15).

LCK6

Bit 6: Port x lock bit y (y= 0..15).

LCK7

Bit 7: Port x lock bit y (y= 0..15).

LCK8

Bit 8: Port x lock bit y (y= 0..15).

LCK9

Bit 9: Port x lock bit y (y= 0..15).

LCK10

Bit 10: Port x lock bit y (y= 0..15).

LCK11

Bit 11: Port x lock bit y (y= 0..15).

LCK12

Bit 12: Port x lock bit y (y= 0..15).

LCK13

Bit 13: Port x lock bit y (y= 0..15).

LCK14

Bit 14: Port x lock bit y (y= 0..15).

LCK15

Bit 15: Port x lock bit y (y= 0..15).

LCKK

Bit 16: Port x lock bit y (y= 0..15).

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL7
rw 		AFRL6
rw 		AFRL5
rw 		AFRL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL3
rw 		AFRL2
rw 		AFRL1
rw 		AFRL0
rw
Toggle fields

AFRL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

AFRL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

AFRL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

AFRL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

AFRL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

AFRL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

AFRL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

AFRL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH15
rw 		AFRH14
rw 		AFRH13
rw 		AFRH12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH11
rw 		AFRH10
rw 		AFRH9
rw 		AFRH8
rw
Toggle fields

AFRH8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

AFRH9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

AFRH10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

AFRH11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

AFRH12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

AFRH13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

AFRH14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

AFRH15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

HASH

0x50060400: Hash processor

17/86 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 DIN
0x8 STR
0xc HR0
0x10 HR1
0x14 HR2
0x18 HR3
0x1c HR4
0x20 IMR
0x24 SR
0xf8 CSR0
0xfc CSR1
0x100 CSR2
0x104 CSR3
0x108 CSR4
0x10c CSR5
0x110 CSR6
0x114 CSR7
0x118 CSR8
0x11c CSR9
0x120 CSR10
0x124 CSR11
0x128 CSR12
0x12c CSR13
0x130 CSR14
0x134 CSR15
0x138 CSR16
0x13c CSR17
0x140 CSR18
0x144 CSR19
0x148 CSR20
0x14c CSR21
0x150 CSR22
0x154 CSR23
0x158 CSR24
0x15c CSR25
0x160 CSR26
0x164 CSR27
0x168 CSR28
0x16c CSR29
0x170 CSR30
0x174 CSR31
0x178 CSR32
0x17c CSR33
0x180 CSR34
0x184 CSR35
0x188 CSR36
0x18c CSR37
0x190 CSR38
0x194 CSR39
0x198 CSR40
0x19c CSR41
0x1a0 CSR42
0x1a4 CSR43
0x1a8 CSR44
0x1ac CSR45
0x1b0 CSR46
0x1b4 CSR47
0x1b8 CSR48
0x1bc CSR49
0x1c0 CSR50
0x1c4 CSR51
0x1c8 CSR52
0x1cc CSR53
0x310 HASH_HR0
0x314 HASH_HR1
0x318 HASH_HR2
0x31c HASH_HR3
0x320 HASH_HR4
0x324 HASH_HR5
0x328 HASH_HR6
0x32c HASH_HR7
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

2/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALGO1
rw 		LKEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDMAT
rw 		DINNE
r 		NBW
r 		ALGO0
rw 		MODE
rw 		DATATYPE
rw 		DMAE
rw 		INIT
w
Toggle fields

INIT

Bit 2: Initialize message digest calculation.

DMAE

Bit 3: DMA enable.

DATATYPE

Bits 4-5: Data type selection.

MODE

Bit 6: Mode selection.

ALGO0

Bit 7: Algorithm selection.

NBW

Bits 8-11: Number of words already pushed.

DINNE

Bit 12: DIN not empty.

MDMAT

Bit 13: Multiple DMA Transfers.

LKEY

Bit 16: Long key selection.

ALGO1

Bit 18: ALGO.

DIN

data input register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAIN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAIN
rw
Toggle fields

DATAIN

Bits 0-31: Data input.

STR

start register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCAL
w 		NBLW
rw
Toggle fields

NBLW

Bits 0-4: Number of valid bits in the last word of the message.

DCAL

Bit 8: Digest calculation.

HR0

digest registers

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H0
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H0
r
Toggle fields

H0

Bits 0-31: H0.

HR1

digest registers

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H1
r
Toggle fields

H1

Bits 0-31: H1.

HR2

digest registers

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H2
r
Toggle fields

H2

Bits 0-31: H2.

HR3

digest registers

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H3
r
Toggle fields

H3

Bits 0-31: H3.

HR4

digest registers

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H4
r
Toggle fields

H4

Bits 0-31: H4.

IMR

interrupt enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCIE
rw 		DINIE
rw
Toggle fields

DINIE

Bit 0: Data input interrupt enable.

DCIE

Bit 1: Digest calculation completion interrupt enable.

SR

status register

Offset: 0x24, size: 32, reset: 0x00000001, access: Unspecified

2/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		DMAS
r 		DCIS
rw 		DINIS
rw
Toggle fields

DINIS

Bit 0: Data input interrupt status.

DCIS

Bit 1: Digest calculation completion interrupt status.

DMAS

Bit 2: DMA Status.

BUSY

Bit 3: Busy bit.

CSR0

context swap registers

Offset: 0xf8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR0
rw
Toggle fields

CSR0

Bits 0-31: CSR0.

CSR1

context swap registers

Offset: 0xfc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR1
rw
Toggle fields

CSR1

Bits 0-31: CSR1.

CSR2

context swap registers

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR2
rw
Toggle fields

CSR2

Bits 0-31: CSR2.

CSR3

context swap registers

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR3
rw
Toggle fields

CSR3

Bits 0-31: CSR3.

CSR4

context swap registers

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR4
rw
Toggle fields

CSR4

Bits 0-31: CSR4.

CSR5

context swap registers

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR5
rw
Toggle fields

CSR5

Bits 0-31: CSR5.

CSR6

context swap registers

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR6
rw
Toggle fields

CSR6

Bits 0-31: CSR6.

CSR7

context swap registers

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR7
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR7
rw
Toggle fields

CSR7

Bits 0-31: CSR7.

CSR8

context swap registers

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR8
rw
Toggle fields

CSR8

Bits 0-31: CSR8.

CSR9

context swap registers

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR9
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR9
rw
Toggle fields

CSR9

Bits 0-31: CSR9.

CSR10

context swap registers

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR10
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR10
rw
Toggle fields

CSR10

Bits 0-31: CSR10.

CSR11

context swap registers

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR11
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR11
rw
Toggle fields

CSR11

Bits 0-31: CSR11.

CSR12

context swap registers

Offset: 0x128, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR12
rw
Toggle fields

CSR12

Bits 0-31: CSR12.

CSR13

context swap registers

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR13
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR13
rw
Toggle fields

CSR13

Bits 0-31: CSR13.

CSR14

context swap registers

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR14
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR14
rw
Toggle fields

CSR14

Bits 0-31: CSR14.

CSR15

context swap registers

Offset: 0x134, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR15
rw
Toggle fields

CSR15

Bits 0-31: CSR15.

CSR16

context swap registers

Offset: 0x138, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR16
rw
Toggle fields

CSR16

Bits 0-31: CSR16.

CSR17

context swap registers

Offset: 0x13c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR17
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR17
rw
Toggle fields

CSR17

Bits 0-31: CSR17.

CSR18

context swap registers

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR18
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR18
rw
Toggle fields

CSR18

Bits 0-31: CSR18.

CSR19

context swap registers

Offset: 0x144, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR19
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR19
rw
Toggle fields

CSR19

Bits 0-31: CSR19.

CSR20

context swap registers

Offset: 0x148, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR20
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR20
rw
Toggle fields

CSR20

Bits 0-31: CSR20.

CSR21

context swap registers

Offset: 0x14c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR21
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR21
rw
Toggle fields

CSR21

Bits 0-31: CSR21.

CSR22

context swap registers

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR22
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR22
rw
Toggle fields

CSR22

Bits 0-31: CSR22.

CSR23

context swap registers

Offset: 0x154, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR23
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR23
rw
Toggle fields

CSR23

Bits 0-31: CSR23.

CSR24

context swap registers

Offset: 0x158, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR24
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR24
rw
Toggle fields

CSR24

Bits 0-31: CSR24.

CSR25

context swap registers

Offset: 0x15c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR25
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR25
rw
Toggle fields

CSR25

Bits 0-31: CSR25.

CSR26

context swap registers

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR26
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR26
rw
Toggle fields

CSR26

Bits 0-31: CSR26.

CSR27

context swap registers

Offset: 0x164, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR27
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR27
rw
Toggle fields

CSR27

Bits 0-31: CSR27.

CSR28

context swap registers

Offset: 0x168, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR28
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR28
rw
Toggle fields

CSR28

Bits 0-31: CSR28.

CSR29

context swap registers

Offset: 0x16c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR29
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR29
rw
Toggle fields

CSR29

Bits 0-31: CSR29.

CSR30

context swap registers

Offset: 0x170, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR30
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR30
rw
Toggle fields

CSR30

Bits 0-31: CSR30.

CSR31

context swap registers

Offset: 0x174, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR31
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR31
rw
Toggle fields

CSR31

Bits 0-31: CSR31.

CSR32

context swap registers

Offset: 0x178, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR32
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR32
rw
Toggle fields

CSR32

Bits 0-31: CSR32.

CSR33

context swap registers

Offset: 0x17c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR33
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR33
rw
Toggle fields

CSR33

Bits 0-31: CSR33.

CSR34

context swap registers

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR34
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR34
rw
Toggle fields

CSR34

Bits 0-31: CSR34.

CSR35

context swap registers

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR35
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR35
rw
Toggle fields

CSR35

Bits 0-31: CSR35.

CSR36

context swap registers

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR36
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR36
rw
Toggle fields

CSR36

Bits 0-31: CSR36.

CSR37

context swap registers

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR37
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR37
rw
Toggle fields

CSR37

Bits 0-31: CSR37.

CSR38

context swap registers

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR38
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR38
rw
Toggle fields

CSR38

Bits 0-31: CSR38.

CSR39

context swap registers

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR39
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR39
rw
Toggle fields

CSR39

Bits 0-31: CSR39.

CSR40

context swap registers

Offset: 0x198, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR40
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR40
rw
Toggle fields

CSR40

Bits 0-31: CSR40.

CSR41

context swap registers

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR41
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR41
rw
Toggle fields

CSR41

Bits 0-31: CSR41.

CSR42

context swap registers

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR42
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR42
rw
Toggle fields

CSR42

Bits 0-31: CSR42.

CSR43

context swap registers

Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR43
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR43
rw
Toggle fields

CSR43

Bits 0-31: CSR43.

CSR44

context swap registers

Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR44
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR44
rw
Toggle fields

CSR44

Bits 0-31: CSR44.

CSR45

context swap registers

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR45
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR45
rw
Toggle fields

CSR45

Bits 0-31: CSR45.

CSR46

context swap registers

Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR46
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR46
rw
Toggle fields

CSR46

Bits 0-31: CSR46.

CSR47

context swap registers

Offset: 0x1b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR47
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR47
rw
Toggle fields

CSR47

Bits 0-31: CSR47.

CSR48

context swap registers

Offset: 0x1b8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR48
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR48
rw
Toggle fields

CSR48

Bits 0-31: CSR48.

CSR49

context swap registers

Offset: 0x1bc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR49
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR49
rw
Toggle fields

CSR49

Bits 0-31: CSR49.

CSR50

context swap registers

Offset: 0x1c0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR50
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR50
rw
Toggle fields

CSR50

Bits 0-31: CSR50.

CSR51

context swap registers

Offset: 0x1c4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR51
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR51
rw
Toggle fields

CSR51

Bits 0-31: CSR51.

CSR52

context swap registers

Offset: 0x1c8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR52
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR52
rw
Toggle fields

CSR52

Bits 0-31: CSR52.

CSR53

context swap registers

Offset: 0x1cc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR53
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR53
rw
Toggle fields

CSR53

Bits 0-31: CSR53.

HASH_HR0

HASH digest register

Offset: 0x310, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H0
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H0
r
Toggle fields

H0

Bits 0-31: H0.

HASH_HR1

read-only

Offset: 0x314, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H1
r
Toggle fields

H1

Bits 0-31: H1.

HASH_HR2

read-only

Offset: 0x318, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H2
r
Toggle fields

H2

Bits 0-31: H2.

HASH_HR3

read-only

Offset: 0x31c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H3
r
Toggle fields

H3

Bits 0-31: H3.

HASH_HR4

read-only

Offset: 0x320, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H4
r
Toggle fields

H4

Bits 0-31: H4.

HASH_HR5

read-only

Offset: 0x324, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H5
r
Toggle fields

H5

Bits 0-31: H5.

HASH_HR6

read-only

Offset: 0x328, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H6
r
Toggle fields

H6

Bits 0-31: H6.

HASH_HR7

read-only

Offset: 0x32c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H7
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H7
r
Toggle fields

H7

Bits 0-31: H7.

I2C1

0x40005400: Inter-integrated circuit

15/55 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 DR
0x14 SR1
0x18 SR2
0x1c CCR
0x20 TRISE
0x24 FLTR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWRST
rw 		ALERT
rw 		PEC
rw 		POS
rw 		ACK
rw 		STOP
rw 		START
rw 		NOSTRETCH
rw 		ENGC
rw 		ENPEC
rw 		ENARP
rw 		SMBTYPE
rw 		SMBUS
rw 		PE
rw
Toggle fields

PE

Bit 0: Peripheral enable.

SMBUS

Bit 1: SMBus mode.

SMBTYPE

Bit 3: SMBus type.

ENARP

Bit 4: ARP enable.

ENPEC

Bit 5: PEC enable.

ENGC

Bit 6: General call enable.

NOSTRETCH

Bit 7: Clock stretching disable (Slave mode).

START

Bit 8: Start generation.

STOP

Bit 9: Stop generation.

ACK

Bit 10: Acknowledge enable.

POS

Bit 11: Acknowledge/PEC Position (for data reception).

PEC

Bit 12: Packet error checking.

ALERT

Bit 13: SMBus alert.

SWRST

Bit 15: Software reset.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAST
rw 		DMAEN
rw 		ITBUFEN
rw 		ITEVTEN
rw 		ITERREN
rw 		FREQ
rw
Toggle fields

FREQ

Bits 0-5: Peripheral clock frequency.

ITERREN

Bit 8: Error interrupt enable.

ITEVTEN

Bit 9: Event interrupt enable.

ITBUFEN

Bit 10: Buffer interrupt enable.

DMAEN

Bit 11: DMA requests enable.

LAST

Bit 12: DMA last transfer.

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDMODE
rw 		ADD10
rw 		ADD7
rw 		ADD0
rw
Toggle fields

ADD0

Bit 0: Interface address.

ADD7

Bits 1-7: Interface address.

ADD10

Bits 8-9: Interface address.

ADDMODE

Bit 15: Addressing mode (slave mode).

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADD2
rw 		ENDUAL
rw
Toggle fields

ENDUAL

Bit 0: Dual addressing mode enable.

ADD2

Bits 1-7: Interface address.

DR

Data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-7: 8-bit data register.

SR1

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

7/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMBALERT
rw 		TIMEOUT
rw 		PECERR
rw 		OVR
rw 		AF
rw 		ARLO
rw 		BERR
rw 		TxE
r 		RxNE
r 		STOPF
r 		ADD10
r 		BTF
r 		ADDR
r 		SB
r
Toggle fields

SB

Bit 0: Start bit (Master mode).

ADDR

Bit 1: Address sent (master mode)/matched (slave mode).

BTF

Bit 2: Byte transfer finished.

ADD10

Bit 3: 10-bit header sent (Master mode).

STOPF

Bit 4: Stop detection (slave mode).

RxNE

Bit 6: Data register not empty (receivers).

TxE

Bit 7: Data register empty (transmitters).

BERR

Bit 8: Bus error.

ARLO

Bit 9: Arbitration lost (master mode).

AF

Bit 10: Acknowledge failure.

OVR

Bit 11: Overrun/Underrun.

PECERR

Bit 12: PEC Error in reception.

TIMEOUT

Bit 14: Timeout or Tlow error.

SMBALERT

Bit 15: SMBus alert.

SR2

Status register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r 		DUALF
r 		SMBHOST
r 		SMBDEFAULT
r 		GENCALL
r 		TRA
r 		BUSY
r 		MSL
r
Toggle fields

MSL

Bit 0: Master/slave.

BUSY

Bit 1: Bus busy.

TRA

Bit 2: Transmitter/receiver.

GENCALL

Bit 4: General call address (Slave mode).

SMBDEFAULT

Bit 5: SMBus device default address (Slave mode).

SMBHOST

Bit 6: SMBus host header (Slave mode).

DUALF

Bit 7: Dual flag (Slave mode).

PEC

Bits 8-15: acket error checking register.

CCR

Clock control register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F_S
rw 		DUTY
rw 		CCR
rw
Toggle fields

CCR

Bits 0-11: Clock control register in Fast/Standard mode (Master mode).

DUTY

Bit 14: Fast mode duty cycle.

F_S

Bit 15: I2C master mode selection.

TRISE

TRISE register

Offset: 0x20, size: 32, reset: 0x00000002, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRISE
rw
Toggle fields

TRISE

Bits 0-5: Maximum rise time in Fast/Standard mode (Master mode).

FLTR

I2C FLTR register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ANOFF
rw 		DNF
rw
Toggle fields

DNF

Bits 0-3: Digital noise filter.

ANOFF

Bit 4: Analog noise filter OFF.

I2C2

0x40005800: Inter-integrated circuit

15/55 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 DR
0x14 SR1
0x18 SR2
0x1c CCR
0x20 TRISE
0x24 FLTR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWRST
rw 		ALERT
rw 		PEC
rw 		POS
rw 		ACK
rw 		STOP
rw 		START
rw 		NOSTRETCH
rw 		ENGC
rw 		ENPEC
rw 		ENARP
rw 		SMBTYPE
rw 		SMBUS
rw 		PE
rw
Toggle fields

PE

Bit 0: Peripheral enable.

SMBUS

Bit 1: SMBus mode.

SMBTYPE

Bit 3: SMBus type.

ENARP

Bit 4: ARP enable.

ENPEC

Bit 5: PEC enable.

ENGC

Bit 6: General call enable.

NOSTRETCH

Bit 7: Clock stretching disable (Slave mode).

START

Bit 8: Start generation.

STOP

Bit 9: Stop generation.

ACK

Bit 10: Acknowledge enable.

POS

Bit 11: Acknowledge/PEC Position (for data reception).

PEC

Bit 12: Packet error checking.

ALERT

Bit 13: SMBus alert.

SWRST

Bit 15: Software reset.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAST
rw 		DMAEN
rw 		ITBUFEN
rw 		ITEVTEN
rw 		ITERREN
rw 		FREQ
rw
Toggle fields

FREQ

Bits 0-5: Peripheral clock frequency.

ITERREN

Bit 8: Error interrupt enable.

ITEVTEN

Bit 9: Event interrupt enable.

ITBUFEN

Bit 10: Buffer interrupt enable.

DMAEN

Bit 11: DMA requests enable.

LAST

Bit 12: DMA last transfer.

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDMODE
rw 		ADD10
rw 		ADD7
rw 		ADD0
rw
Toggle fields

ADD0

Bit 0: Interface address.

ADD7

Bits 1-7: Interface address.

ADD10

Bits 8-9: Interface address.

ADDMODE

Bit 15: Addressing mode (slave mode).

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADD2
rw 		ENDUAL
rw
Toggle fields

ENDUAL

Bit 0: Dual addressing mode enable.

ADD2

Bits 1-7: Interface address.

DR

Data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-7: 8-bit data register.

SR1

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

7/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMBALERT
rw 		TIMEOUT
rw 		PECERR
rw 		OVR
rw 		AF
rw 		ARLO
rw 		BERR
rw 		TxE
r 		RxNE
r 		STOPF
r 		ADD10
r 		BTF
r 		ADDR
r 		SB
r
Toggle fields

SB

Bit 0: Start bit (Master mode).

ADDR

Bit 1: Address sent (master mode)/matched (slave mode).

BTF

Bit 2: Byte transfer finished.

ADD10

Bit 3: 10-bit header sent (Master mode).

STOPF

Bit 4: Stop detection (slave mode).

RxNE

Bit 6: Data register not empty (receivers).

TxE

Bit 7: Data register empty (transmitters).

BERR

Bit 8: Bus error.

ARLO

Bit 9: Arbitration lost (master mode).

AF

Bit 10: Acknowledge failure.

OVR

Bit 11: Overrun/Underrun.

PECERR

Bit 12: PEC Error in reception.

TIMEOUT

Bit 14: Timeout or Tlow error.

SMBALERT

Bit 15: SMBus alert.

SR2

Status register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r 		DUALF
r 		SMBHOST
r 		SMBDEFAULT
r 		GENCALL
r 		TRA
r 		BUSY
r 		MSL
r
Toggle fields

MSL

Bit 0: Master/slave.

BUSY

Bit 1: Bus busy.

TRA

Bit 2: Transmitter/receiver.

GENCALL

Bit 4: General call address (Slave mode).

SMBDEFAULT

Bit 5: SMBus device default address (Slave mode).

SMBHOST

Bit 6: SMBus host header (Slave mode).

DUALF

Bit 7: Dual flag (Slave mode).

PEC

Bits 8-15: acket error checking register.

CCR

Clock control register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F_S
rw 		DUTY
rw 		CCR
rw
Toggle fields

CCR

Bits 0-11: Clock control register in Fast/Standard mode (Master mode).

DUTY

Bit 14: Fast mode duty cycle.

F_S

Bit 15: I2C master mode selection.

TRISE

TRISE register

Offset: 0x20, size: 32, reset: 0x00000002, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRISE
rw
Toggle fields

TRISE

Bits 0-5: Maximum rise time in Fast/Standard mode (Master mode).

FLTR

I2C FLTR register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ANOFF
rw 		DNF
rw
Toggle fields

DNF

Bits 0-3: Digital noise filter.

ANOFF

Bit 4: Analog noise filter OFF.

I2C3

0x40005c00: Inter-integrated circuit

15/55 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 DR
0x14 SR1
0x18 SR2
0x1c CCR
0x20 TRISE
0x24 FLTR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWRST
rw 		ALERT
rw 		PEC
rw 		POS
rw 		ACK
rw 		STOP
rw 		START
rw 		NOSTRETCH
rw 		ENGC
rw 		ENPEC
rw 		ENARP
rw 		SMBTYPE
rw 		SMBUS
rw 		PE
rw
Toggle fields

PE

Bit 0: Peripheral enable.

SMBUS

Bit 1: SMBus mode.

SMBTYPE

Bit 3: SMBus type.

ENARP

Bit 4: ARP enable.

ENPEC

Bit 5: PEC enable.

ENGC

Bit 6: General call enable.

NOSTRETCH

Bit 7: Clock stretching disable (Slave mode).

START

Bit 8: Start generation.

STOP

Bit 9: Stop generation.

ACK

Bit 10: Acknowledge enable.

POS

Bit 11: Acknowledge/PEC Position (for data reception).

PEC

Bit 12: Packet error checking.

ALERT

Bit 13: SMBus alert.

SWRST

Bit 15: Software reset.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAST
rw 		DMAEN
rw 		ITBUFEN
rw 		ITEVTEN
rw 		ITERREN
rw 		FREQ
rw
Toggle fields

FREQ

Bits 0-5: Peripheral clock frequency.

ITERREN

Bit 8: Error interrupt enable.

ITEVTEN

Bit 9: Event interrupt enable.

ITBUFEN

Bit 10: Buffer interrupt enable.

DMAEN

Bit 11: DMA requests enable.

LAST

Bit 12: DMA last transfer.

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDMODE
rw 		ADD10
rw 		ADD7
rw 		ADD0
rw
Toggle fields

ADD0

Bit 0: Interface address.

ADD7

Bits 1-7: Interface address.

ADD10

Bits 8-9: Interface address.

ADDMODE

Bit 15: Addressing mode (slave mode).

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADD2
rw 		ENDUAL
rw
Toggle fields

ENDUAL

Bit 0: Dual addressing mode enable.

ADD2

Bits 1-7: Interface address.

DR

Data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-7: 8-bit data register.

SR1

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

7/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMBALERT
rw 		TIMEOUT
rw 		PECERR
rw 		OVR
rw 		AF
rw 		ARLO
rw 		BERR
rw 		TxE
r 		RxNE
r 		STOPF
r 		ADD10
r 		BTF
r 		ADDR
r 		SB
r
Toggle fields

SB

Bit 0: Start bit (Master mode).

ADDR

Bit 1: Address sent (master mode)/matched (slave mode).

BTF

Bit 2: Byte transfer finished.

ADD10

Bit 3: 10-bit header sent (Master mode).

STOPF

Bit 4: Stop detection (slave mode).

RxNE

Bit 6: Data register not empty (receivers).

TxE

Bit 7: Data register empty (transmitters).

BERR

Bit 8: Bus error.

ARLO

Bit 9: Arbitration lost (master mode).

AF

Bit 10: Acknowledge failure.

OVR

Bit 11: Overrun/Underrun.

PECERR

Bit 12: PEC Error in reception.

TIMEOUT

Bit 14: Timeout or Tlow error.

SMBALERT

Bit 15: SMBus alert.

SR2

Status register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r 		DUALF
r 		SMBHOST
r 		SMBDEFAULT
r 		GENCALL
r 		TRA
r 		BUSY
r 		MSL
r
Toggle fields

MSL

Bit 0: Master/slave.

BUSY

Bit 1: Bus busy.

TRA

Bit 2: Transmitter/receiver.

GENCALL

Bit 4: General call address (Slave mode).

SMBDEFAULT

Bit 5: SMBus device default address (Slave mode).

SMBHOST

Bit 6: SMBus host header (Slave mode).

DUALF

Bit 7: Dual flag (Slave mode).

PEC

Bits 8-15: acket error checking register.

CCR

Clock control register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F_S
rw 		DUTY
rw 		CCR
rw
Toggle fields

CCR

Bits 0-11: Clock control register in Fast/Standard mode (Master mode).

DUTY

Bit 14: Fast mode duty cycle.

F_S

Bit 15: I2C master mode selection.

TRISE

TRISE register

Offset: 0x20, size: 32, reset: 0x00000002, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRISE
rw
Toggle fields

TRISE

Bits 0-5: Maximum rise time in Fast/Standard mode (Master mode).

FLTR

I2C FLTR register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ANOFF
rw 		DNF
rw
Toggle fields

DNF

Bits 0-3: Digital noise filter.

ANOFF

Bit 4: Analog noise filter OFF.

I2S2ext

0x40003400: Serial peripheral interface

10/45 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SR
0xc DR
0x10 CRCPR
0x14 RXCRCR
0x18 TXCRCR
0x1c I2SCFGR
0x20 I2SPR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw 		BIDIOE
rw 		CRCEN
rw 		CRCNEXT
rw 		DFF
rw 		RXONLY
rw 		SSM
rw 		SSI
rw 		LSBFIRST
rw 		SPE
rw 		BR
rw 		MSTR
rw 		CPOL
rw 		CPHA
rw
Toggle fields

CPHA

Bit 0: Clock phase.

CPOL

Bit 1: Clock polarity.

MSTR

Bit 2: Master selection.

BR

Bits 3-5: Baud rate control.

SPE

Bit 6: SPI enable.

LSBFIRST

Bit 7: Frame format.

SSI

Bit 8: Internal slave select.

SSM

Bit 9: Software slave management.

RXONLY

Bit 10: Receive only.

DFF

Bit 11: Data frame format.

CRCNEXT

Bit 12: CRC transfer next.

CRCEN

Bit 13: Hardware CRC calculation enable.

BIDIOE

Bit 14: Output enable in bidirectional mode.

BIDIMODE

Bit 15: Bidirectional data mode enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXEIE
rw 		RXNEIE
rw 		ERRIE
rw 		FRF
rw 		SSOE
rw 		TXDMAEN
rw 		RXDMAEN
rw
Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

TXDMAEN

Bit 1: Tx buffer DMA enable.

SSOE

Bit 2: SS output enable.

FRF

Bit 4: Frame format.

ERRIE

Bit 5: Error interrupt enable.

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

TXEIE

Bit 7: Tx buffer empty interrupt enable.

SR

status register

Offset: 0x8, size: 32, reset: 0x00000002, access: Unspecified

8/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIFRFE
r 		BSY
r 		OVR
r 		MODF
r 		CRCERR
rw 		UDR
r 		CHSIDE
r 		TXE
r 		RXNE
r
Toggle fields

RXNE

Bit 0: Receive buffer not empty.

TXE

Bit 1: Transmit buffer empty.

CHSIDE

Bit 2: Channel side.

UDR

Bit 3: Underrun flag.

CRCERR

Bit 4: CRC error flag.

MODF

Bit 5: Mode fault.

OVR

Bit 6: Overrun flag.

BSY

Bit 7: Busy flag.

TIFRFE

Bit 8: TI frame format error.

DR

data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-15: Data register.

CRCPR

CRC polynomial register

Offset: 0x10, size: 32, reset: 0x00000007, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

RXCRCR

RX CRC register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

TXCRCR

TX CRC register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

I2SCFGR

I2S configuration register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SMOD
rw 		I2SE
rw 		I2SCFG
rw 		PCMSYNC
rw 		I2SSTD
rw 		CKPOL
rw 		DATLEN
rw 		CHLEN
rw
Toggle fields

CHLEN

Bit 0: Channel length (number of bits per audio channel).

DATLEN

Bits 1-2: Data length to be transferred.

CKPOL

Bit 3: Steady state clock polarity.

I2SSTD

Bits 4-5: I2S standard selection.

PCMSYNC

Bit 7: PCM frame synchronization.

I2SCFG

Bits 8-9: I2S configuration mode.

I2SE

Bit 10: I2S Enable.

I2SMOD

Bit 11: I2S mode selection.

I2SPR

I2S prescaler register

Offset: 0x20, size: 32, reset: 0x0000000A, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOE
rw 		ODD
rw 		I2SDIV
rw
Toggle fields

I2SDIV

Bits 0-7: I2S Linear prescaler.

ODD

Bit 8: Odd factor for the prescaler.

MCKOE

Bit 9: Master clock output enable.

I2S3ext

0x40004000: Serial peripheral interface

10/45 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SR
0xc DR
0x10 CRCPR
0x14 RXCRCR
0x18 TXCRCR
0x1c I2SCFGR
0x20 I2SPR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw 		BIDIOE
rw 		CRCEN
rw 		CRCNEXT
rw 		DFF
rw 		RXONLY
rw 		SSM
rw 		SSI
rw 		LSBFIRST
rw 		SPE
rw 		BR
rw 		MSTR
rw 		CPOL
rw 		CPHA
rw
Toggle fields

CPHA

Bit 0: Clock phase.

CPOL

Bit 1: Clock polarity.

MSTR

Bit 2: Master selection.

BR

Bits 3-5: Baud rate control.

SPE

Bit 6: SPI enable.

LSBFIRST

Bit 7: Frame format.

SSI

Bit 8: Internal slave select.

SSM

Bit 9: Software slave management.

RXONLY

Bit 10: Receive only.

DFF

Bit 11: Data frame format.

CRCNEXT

Bit 12: CRC transfer next.

CRCEN

Bit 13: Hardware CRC calculation enable.

BIDIOE

Bit 14: Output enable in bidirectional mode.

BIDIMODE

Bit 15: Bidirectional data mode enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXEIE
rw 		RXNEIE
rw 		ERRIE
rw 		FRF
rw 		SSOE
rw 		TXDMAEN
rw 		RXDMAEN
rw
Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

TXDMAEN

Bit 1: Tx buffer DMA enable.

SSOE

Bit 2: SS output enable.

FRF

Bit 4: Frame format.

ERRIE

Bit 5: Error interrupt enable.

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

TXEIE

Bit 7: Tx buffer empty interrupt enable.

SR

status register

Offset: 0x8, size: 32, reset: 0x00000002, access: Unspecified

8/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIFRFE
r 		BSY
r 		OVR
r 		MODF
r 		CRCERR
rw 		UDR
r 		CHSIDE
r 		TXE
r 		RXNE
r
Toggle fields

RXNE

Bit 0: Receive buffer not empty.

TXE

Bit 1: Transmit buffer empty.

CHSIDE

Bit 2: Channel side.

UDR

Bit 3: Underrun flag.

CRCERR

Bit 4: CRC error flag.

MODF

Bit 5: Mode fault.

OVR

Bit 6: Overrun flag.

BSY

Bit 7: Busy flag.

TIFRFE

Bit 8: TI frame format error.

DR

data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-15: Data register.

CRCPR

CRC polynomial register

Offset: 0x10, size: 32, reset: 0x00000007, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

RXCRCR

RX CRC register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

TXCRCR

TX CRC register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

I2SCFGR

I2S configuration register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SMOD
rw 		I2SE
rw 		I2SCFG
rw 		PCMSYNC
rw 		I2SSTD
rw 		CKPOL
rw 		DATLEN
rw 		CHLEN
rw
Toggle fields

CHLEN

Bit 0: Channel length (number of bits per audio channel).

DATLEN

Bits 1-2: Data length to be transferred.

CKPOL

Bit 3: Steady state clock polarity.

I2SSTD

Bits 4-5: I2S standard selection.

PCMSYNC

Bit 7: PCM frame synchronization.

I2SCFG

Bits 8-9: I2S configuration mode.

I2SE

Bit 10: I2S Enable.

I2SMOD

Bit 11: I2S mode selection.

I2SPR

I2S prescaler register

Offset: 0x20, size: 32, reset: 0x0000000A, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOE
rw 		ODD
rw 		I2SDIV
rw
Toggle fields

I2SDIV

Bits 0-7: I2S Linear prescaler.

ODD

Bit 8: Odd factor for the prescaler.

MCKOE

Bit 9: Master clock output enable.

IWDG

0x40003000: Independent watchdog

2/5 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 KR
0x4 PR
0x8 RLR
0xc SR
Toggle registers

KR

Key register

Offset: 0x0, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-15: Key value (write only, read 0000h).

PR

Prescaler register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PR
rw
Toggle fields

PR

Bits 0-2: Prescaler divider.

RLR

Reload register

Offset: 0x8, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RL
rw
Toggle fields

RL

Bits 0-11: Watchdog counter reload value.

SR

Status register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RVU
r 		PVU
r
Toggle fields

PVU

Bit 0: Watchdog prescaler value update.

RVU

Bit 1: Watchdog counter reload value update.

LTDC

0x40016800: LCD-TFT Controller

13/91 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x8 SSCR
0xc BPCR
0x10 AWCR
0x14 TWCR
0x18 GCR
0x24 SRCR
0x2c BCCR
0x34 IER
0x38 ISR
0x3c ICR
0x40 LIPCR
0x44 CPSR
0x48 CDSR
0x84 L1CR
0x88 L1WHPCR
0x8c L1WVPCR
0x90 L1CKCR
0x94 L1PFCR
0x98 L1CACR
0x9c L1DCCR
0xa0 L1BFCR
0xac L1CFBAR
0xb0 L1CFBLR
0xb4 L1CFBLNR
0xc4 L1CLUTWR
0x104 L2CR
0x108 L2WHPCR
0x10c L2WVPCR
0x110 L2CKCR
0x114 L2PFCR
0x118 L2CACR
0x11c L2DCCR
0x120 L2BFCR
0x12c L2CFBAR
0x130 L2CFBLR
0x134 L2CFBLNR
0x144 L2CLUTWR
Toggle registers

SSCR

Synchronization Size Configuration Register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HSW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VSH
rw
Toggle fields

VSH

Bits 0-10: Vertical Synchronization Height (in units of horizontal scan line).

HSW

Bits 16-27: Horizontal Synchronization Width (in units of pixel clock period).

BPCR

Back Porch Configuration Register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AHBP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AVBP
rw
Toggle fields

AVBP

Bits 0-10: Accumulated Vertical back porch (in units of horizontal scan line).

AHBP

Bits 16-27: Accumulated Horizontal back porch (in units of pixel clock period).

AWCR

Active Width Configuration Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AAW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AAH
rw
Toggle fields

AAH

Bits 0-10: Accumulated Active Height (in units of horizontal scan line).

AAW

Bits 16-27: AAW.

TWCR

Total Width Configuration Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TOTALW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOTALH
rw
Toggle fields

TOTALH

Bits 0-10: Total Height (in units of horizontal scan line).

TOTALW

Bits 16-27: Total Width (in units of pixel clock period).

GCR

Global Control Register

Offset: 0x18, size: 32, reset: 0x00002220, access: Unspecified

3/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HSPOL
rw 		VSPOL
rw 		DEPOL
rw 		PCPOL
rw 		DEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DRW
r 		DGW
r 		DBW
r 		LTDCEN
rw
Toggle fields

LTDCEN

Bit 0: LCD-TFT controller enable bit.

DBW

Bits 4-6: Dither Blue Width.

DGW

Bits 8-10: Dither Green Width.

DRW

Bits 12-14: Dither Red Width.

DEN

Bit 16: Dither Enable.

PCPOL

Bit 28: Pixel Clock Polarity.

DEPOL

Bit 29: Data Enable Polarity.

VSPOL

Bit 30: Vertical Synchronization Polarity.

HSPOL

Bit 31: Horizontal Synchronization Polarity.

SRCR

Shadow Reload Configuration Register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VBR
rw 		IMR
rw
Toggle fields

IMR

Bit 0: Immediate Reload.

VBR

Bit 1: Vertical Blanking Reload.

BCCR

Background Color Configuration Register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BC
rw
Toggle fields

BC

Bits 0-23: Background Color Red value.

IER

Interrupt Enable Register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RRIE
rw 		TERRIE
rw 		FUIE
rw 		LIE
rw
Toggle fields

LIE

Bit 0: Line Interrupt Enable.

FUIE

Bit 1: FIFO Underrun Interrupt Enable.

TERRIE

Bit 2: Transfer Error Interrupt Enable.

RRIE

Bit 3: Register Reload interrupt enable.

ISR

Interrupt Status Register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RRIF
r 		TERRIF
r 		FUIF
r 		LIF
r
Toggle fields

LIF

Bit 0: Line Interrupt flag.

FUIF

Bit 1: FIFO Underrun Interrupt flag.

TERRIF

Bit 2: Transfer Error interrupt flag.

RRIF

Bit 3: Register Reload Interrupt Flag.

ICR

Interrupt Clear Register

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRRIF
w 		CTERRIF
w 		CFUIF
w 		CLIF
w
Toggle fields

CLIF

Bit 0: Clears the Line Interrupt Flag.

CFUIF

Bit 1: Clears the FIFO Underrun Interrupt flag.

CTERRIF

Bit 2: Clears the Transfer Error Interrupt Flag.

CRRIF

Bit 3: Clears Register Reload Interrupt Flag.

LIPCR

Line Interrupt Position Configuration Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LIPOS
rw
Toggle fields

LIPOS

Bits 0-10: Line Interrupt Position.

CPSR

Current Position Status Register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CXPOS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CYPOS
r
Toggle fields

CYPOS

Bits 0-15: Current Y Position.

CXPOS

Bits 16-31: Current X Position.

CDSR

Current Display Status Register

Offset: 0x48, size: 32, reset: 0x0000000F, access: read-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSYNCS
r 		VSYNCS
r 		HDES
r 		VDES
r
Toggle fields

VDES

Bit 0: Vertical Data Enable display Status.

HDES

Bit 1: Horizontal Data Enable display Status.

VSYNCS

Bit 2: Vertical Synchronization display Status.

HSYNCS

Bit 3: Horizontal Synchronization display Status.

L1CR

Layerx Control Register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLUTEN
rw 		COLKEN
rw 		LEN
rw
Toggle fields

LEN

Bit 0: Layer Enable.

COLKEN

Bit 1: Color Keying Enable.

CLUTEN

Bit 4: Color Look-Up Table Enable.

L1WHPCR

Layerx Window Horizontal Position Configuration Register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WHSPPOS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WHSTPOS
rw
Toggle fields

WHSTPOS

Bits 0-11: Window Horizontal Start Position.

WHSPPOS

Bits 16-27: Window Horizontal Stop Position.

L1WVPCR

Layerx Window Vertical Position Configuration Register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WVSPPOS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WVSTPOS
rw
Toggle fields

WVSTPOS

Bits 0-10: Window Vertical Start Position.

WVSPPOS

Bits 16-26: Window Vertical Stop Position.

L1CKCR

Layerx Color Keying Configuration Register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CKRED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKGREEN
rw 		CKBLUE
rw
Toggle fields

CKBLUE

Bits 0-7: Color Key Blue value.

CKGREEN

Bits 8-15: Color Key Green value.

CKRED

Bits 16-23: Color Key Red value.

L1PFCR

Layerx Pixel Format Configuration Register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PF
rw
Toggle fields

PF

Bits 0-2: Pixel Format.

L1CACR

Layerx Constant Alpha Configuration Register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CONSTA
rw
Toggle fields

CONSTA

Bits 0-7: Constant Alpha.

L1DCCR

Layerx Default Color Configuration Register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DCALPHA
rw 		DCRED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCGREEN
rw 		DCBLUE
rw
Toggle fields

DCBLUE

Bits 0-7: Default Color Blue.

DCGREEN

Bits 8-15: Default Color Green.

DCRED

Bits 16-23: Default Color Red.

DCALPHA

Bits 24-31: Default Color Alpha.

L1BFCR

Layerx Blending Factors Configuration Register

Offset: 0xa0, size: 32, reset: 0x00000607, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BF1
rw 		BF2
rw
Toggle fields

BF2

Bits 0-2: Blending Factor 2.

BF1

Bits 8-10: Blending Factor 1.

L1CFBAR

Layerx Color Frame Buffer Address Register

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CFBADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFBADD
rw
Toggle fields

CFBADD

Bits 0-31: Color Frame Buffer Start Address.

L1CFBLR

Layerx Color Frame Buffer Length Register

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CFBP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFBLL
rw
Toggle fields

CFBLL

Bits 0-12: Color Frame Buffer Line Length.

CFBP

Bits 16-28: Color Frame Buffer Pitch in bytes.

L1CFBLNR

Layerx ColorFrame Buffer Line Number Register

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFBLNBR
rw
Toggle fields

CFBLNBR

Bits 0-10: Frame Buffer Line Number.

L1CLUTWR

Layerx CLUT Write Register

Offset: 0xc4, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLUTADD
w 		RED
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GREEN
w 		BLUE
w
Toggle fields

BLUE

Bits 0-7: Blue value.

GREEN

Bits 8-15: Green value.

RED

Bits 16-23: Red value.

CLUTADD

Bits 24-31: CLUT Address.

L2CR

Layerx Control Register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLUTEN
rw 		COLKEN
rw 		LEN
rw
Toggle fields

LEN

Bit 0: Layer Enable.

COLKEN

Bit 1: Color Keying Enable.

CLUTEN

Bit 4: Color Look-Up Table Enable.

L2WHPCR

Layerx Window Horizontal Position Configuration Register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WHSPPOS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WHSTPOS
rw
Toggle fields

WHSTPOS

Bits 0-11: Window Horizontal Start Position.

WHSPPOS

Bits 16-27: Window Horizontal Stop Position.

L2WVPCR

Layerx Window Vertical Position Configuration Register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WVSPPOS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WVSTPOS
rw
Toggle fields

WVSTPOS

Bits 0-10: Window Vertical Start Position.

WVSPPOS

Bits 16-26: Window Vertical Stop Position.

L2CKCR

Layerx Color Keying Configuration Register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CKRED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKRED
rw 		CKGREEN
rw 		CKBLUE
rw
Toggle fields

CKBLUE

Bits 0-7: Color Key Blue value.

CKGREEN

Bits 8-14: Color Key Green value.

CKRED

Bits 15-23: Color Key Red value.

L2PFCR

Layerx Pixel Format Configuration Register

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PF
rw
Toggle fields

PF

Bits 0-2: Pixel Format.

L2CACR

Layerx Constant Alpha Configuration Register

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CONSTA
rw
Toggle fields

CONSTA

Bits 0-7: Constant Alpha.

L2DCCR

Layerx Default Color Configuration Register

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DCALPHA
rw 		DCRED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCGREEN
rw 		DCBLUE
rw
Toggle fields

DCBLUE

Bits 0-7: Default Color Blue.

DCGREEN

Bits 8-15: Default Color Green.

DCRED

Bits 16-23: Default Color Red.

DCALPHA

Bits 24-31: Default Color Alpha.

L2BFCR

Layerx Blending Factors Configuration Register

Offset: 0x120, size: 32, reset: 0x00000607, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BF1
rw 		BF2
rw
Toggle fields

BF2

Bits 0-2: Blending Factor 2.

BF1

Bits 8-10: Blending Factor 1.

L2CFBAR

Layerx Color Frame Buffer Address Register

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CFBADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFBADD
rw
Toggle fields

CFBADD

Bits 0-31: Color Frame Buffer Start Address.

L2CFBLR

Layerx Color Frame Buffer Length Register

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CFBP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFBLL
rw
Toggle fields

CFBLL

Bits 0-12: Color Frame Buffer Line Length.

CFBP

Bits 16-28: Color Frame Buffer Pitch in bytes.

L2CFBLNR

Layerx ColorFrame Buffer Line Number Register

Offset: 0x134, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFBLNBR
rw
Toggle fields

CFBLNBR

Bits 0-10: Frame Buffer Line Number.

L2CLUTWR

Layerx CLUT Write Register

Offset: 0x144, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLUTADD
w 		RED
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GREEN
w 		BLUE
w
Toggle fields

BLUE

Bits 0-7: Blue value.

GREEN

Bits 8-15: Green value.

RED

Bits 16-23: Red value.

CLUTADD

Bits 24-31: CLUT Address.

OTG_FS_DEVICE

0x50000800: USB on the go full speed

38/204 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 FS_DCFG
0x4 FS_DCTL
0x8 FS_DSTS
0x10 FS_DIEPMSK
0x14 FS_DOEPMSK
0x18 FS_DAINT
0x1c FS_DAINTMSK
0x28 DVBUSDIS
0x2c DVBUSPULSE
0x34 DIEPEMPMSK
0x100 FS_DIEPCTL0
0x108 DIEPINT0
0x110 DIEPTSIZ0
0x118 DTXFSTS0
0x120 DIEPCTL1
0x128 DIEPINT1
0x130 DIEPTSIZ1
0x138 DTXFSTS1
0x140 DIEPCTL2
0x148 DIEPINT2
0x150 DIEPTSIZ2
0x158 DTXFSTS2
0x160 DIEPCTL3
0x168 DIEPINT3
0x170 DIEPTSIZ3
0x178 DTXFSTS3
0x300 DOEPCTL0
0x308 DOEPINT0
0x310 DOEPTSIZ0
0x320 DOEPCTL1
0x328 DOEPINT1
0x330 DOEPTSIZ1
0x340 DOEPCTL2
0x348 DOEPINT2
0x350 DOEPTSIZ2
0x360 DOEPCTL3
0x368 DOEPINT3
0x370 DOEPTSIZ3
Toggle registers

FS_DCFG

OTG_FS device configuration register (OTG_FS_DCFG)

Offset: 0x0, size: 32, reset: 0x02200000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PFIVL
rw 		DAD
rw 		NZLSOHSK
rw 		DSPD
rw
Toggle fields

DSPD

Bits 0-1: Device speed.

NZLSOHSK

Bit 2: Non-zero-length status OUT handshake.

DAD

Bits 4-10: Device address.

PFIVL

Bits 11-12: Periodic frame interval.

FS_DCTL

OTG_FS device control register (OTG_FS_DCTL)

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

2/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POPRGDNE
rw 		CGONAK
rw 		SGONAK
rw 		CGINAK
rw 		SGINAK
rw 		TCTL
rw 		GONSTS
r 		GINSTS
r 		SDIS
rw 		RWUSIG
rw
Toggle fields

RWUSIG

Bit 0: Remote wakeup signaling.

SDIS

Bit 1: Soft disconnect.

GINSTS

Bit 2: Global IN NAK status.

GONSTS

Bit 3: Global OUT NAK status.

TCTL

Bits 4-6: Test control.

SGINAK

Bit 7: Set global IN NAK.

CGINAK

Bit 8: Clear global IN NAK.

SGONAK

Bit 9: Set global OUT NAK.

CGONAK

Bit 10: Clear global OUT NAK.

POPRGDNE

Bit 11: Power-on programming done.

FS_DSTS

OTG_FS device status register (OTG_FS_DSTS)

Offset: 0x8, size: 32, reset: 0x00000010, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FNSOF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FNSOF
r 		EERR
r 		ENUMSPD
r 		SUSPSTS
r
Toggle fields

SUSPSTS

Bit 0: Suspend status.

ENUMSPD

Bits 1-2: Enumerated speed.

EERR

Bit 3: Erratic error.

FNSOF

Bits 8-21: Frame number of the received SOF.

FS_DIEPMSK

OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPNEM
rw 		INEPNMM
rw 		ITTXFEMSK
rw 		TOM
rw 		EPDM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed interrupt mask.

EPDM

Bit 1: Endpoint disabled interrupt mask.

TOM

Bit 3: Timeout condition mask (Non-isochronous endpoints).

ITTXFEMSK

Bit 4: IN token received when TxFIFO empty mask.

INEPNMM

Bit 5: IN token received with EP mismatch mask.

INEPNEM

Bit 6: IN endpoint NAK effective mask.

FS_DOEPMSK

OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OTEPDM
rw 		STUPM
rw 		EPDM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed interrupt mask.

EPDM

Bit 1: Endpoint disabled interrupt mask.

STUPM

Bit 3: SETUP phase done mask.

OTEPDM

Bit 4: OUT token received when endpoint disabled mask.

FS_DAINT

OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OEPINT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPINT
r
Toggle fields

IEPINT

Bits 0-15: IN endpoint interrupt bits.

OEPINT

Bits 16-31: OUT endpoint interrupt bits.

FS_DAINTMSK

OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OEPINT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPM
rw
Toggle fields

IEPM

Bits 0-15: IN EP interrupt mask bits.

OEPINT

Bits 16-31: OUT endpoint interrupt bits.

DVBUSDIS

OTG_FS device VBUS discharge time register

Offset: 0x28, size: 32, reset: 0x000017D7, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VBUSDT
rw
Toggle fields

VBUSDT

Bits 0-15: Device VBUS discharge time.

DVBUSPULSE

OTG_FS device VBUS pulsing time register

Offset: 0x2c, size: 32, reset: 0x000005B8, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DVBUSP
rw
Toggle fields

DVBUSP

Bits 0-11: Device VBUS pulsing time.

DIEPEMPMSK

OTG_FS device IN endpoint FIFO empty interrupt mask register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXFEM
rw
Toggle fields

INEPTXFEM

Bits 0-15: IN EP Tx FIFO empty interrupt mask bits.

FS_DIEPCTL0

OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)

Offset: 0x100, size: 32, reset: 0x00000000, access: Unspecified

5/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
r 		EPDIS
r 		SNAK
w 		CNAK
w 		TXFNUM
rw 		STALL
rw 		EPTYP
r 		NAKSTS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
r 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-1: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

STALL

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TxFIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

DIEPINT0

device endpoint-x interrupt register

Offset: 0x108, size: 32, reset: 0x00000080, access: Unspecified

1/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFE
r 		INEPNE
rw 		ITTXFE
rw 		TOC
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

TOC

Bit 3: TOC.

ITTXFE

Bit 4: ITTXFE.

INEPNE

Bit 6: INEPNE.

TXFE

Bit 7: TXFE.

DIEPTSIZ0

device endpoint-0 transfer size register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PKTCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-6: Transfer size.

PKTCNT

Bits 19-20: Packet count.

DTXFSTS0

OTG_FS device IN endpoint transmit FIFO status register

Offset: 0x118, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle fields

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space available.

DIEPCTL1

OTG device endpoint-1 control register

Offset: 0x120, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SODDFRM_SD1PID
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		TXFNUM
rw 		Stall
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPID

Bit 16: EONUM/DPID.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

Stall

Bit 21: Stall.

TXFNUM

Bits 22-25: TXFNUM.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID/SEVNFRM.

SODDFRM_SD1PID

Bit 29: SODDFRM/SD1PID.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DIEPINT1

device endpoint-1 interrupt register

Offset: 0x128, size: 32, reset: 0x00000080, access: Unspecified

1/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFE
r 		INEPNE
rw 		ITTXFE
rw 		TOC
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

TOC

Bit 3: TOC.

ITTXFE

Bit 4: ITTXFE.

INEPNE

Bit 6: INEPNE.

TXFE

Bit 7: TXFE.

DIEPTSIZ1

device endpoint-1 transfer size register

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

DTXFSTS1

OTG_FS device IN endpoint transmit FIFO status register

Offset: 0x138, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle fields

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space available.

DIEPCTL2

OTG device endpoint-2 control register

Offset: 0x140, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SODDFRM
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		TXFNUM
rw 		Stall
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPID

Bit 16: EONUM/DPID.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

Stall

Bit 21: Stall.

TXFNUM

Bits 22-25: TXFNUM.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID/SEVNFRM.

SODDFRM

Bit 29: SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DIEPINT2

device endpoint-2 interrupt register

Offset: 0x148, size: 32, reset: 0x00000080, access: Unspecified

1/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFE
r 		INEPNE
rw 		ITTXFE
rw 		TOC
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

TOC

Bit 3: TOC.

ITTXFE

Bit 4: ITTXFE.

INEPNE

Bit 6: INEPNE.

TXFE

Bit 7: TXFE.

DIEPTSIZ2

device endpoint-2 transfer size register

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

DTXFSTS2

OTG_FS device IN endpoint transmit FIFO status register

Offset: 0x158, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle fields

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space available.

DIEPCTL3

OTG device endpoint-3 control register

Offset: 0x160, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SODDFRM
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		TXFNUM
rw 		Stall
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPID

Bit 16: EONUM/DPID.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

Stall

Bit 21: Stall.

TXFNUM

Bits 22-25: TXFNUM.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID/SEVNFRM.

SODDFRM

Bit 29: SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DIEPINT3

device endpoint-3 interrupt register

Offset: 0x168, size: 32, reset: 0x00000080, access: Unspecified

1/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFE
r 		INEPNE
rw 		ITTXFE
rw 		TOC
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

TOC

Bit 3: TOC.

ITTXFE

Bit 4: ITTXFE.

INEPNE

Bit 6: INEPNE.

TXFE

Bit 7: TXFE.

DIEPTSIZ3

device endpoint-3 transfer size register

Offset: 0x170, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

DTXFSTS3

OTG_FS device IN endpoint transmit FIFO status register

Offset: 0x178, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle fields

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space available.

DOEPCTL0

device endpoint-0 control register

Offset: 0x300, size: 32, reset: 0x00008000, access: Unspecified

5/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
w 		EPDIS
r 		SNAK
w 		CNAK
w 		Stall
rw 		SNPM
rw 		EPTYP
r 		NAKSTS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
r 		MPSIZ
r
Toggle fields

MPSIZ

Bits 0-1: MPSIZ.

USBAEP

Bit 15: USBAEP.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

SNPM

Bit 20: SNPM.

Stall

Bit 21: Stall.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DOEPINT0

device endpoint-0 interrupt register

Offset: 0x308, size: 32, reset: 0x00000080, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2BSTUP
rw 		OTEPDIS
rw 		STUP
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

STUP

Bit 3: STUP.

OTEPDIS

Bit 4: OTEPDIS.

B2BSTUP

Bit 6: B2BSTUP.

DOEPTSIZ0

device OUT endpoint-0 transfer size register

Offset: 0x310, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STUPCNT
rw 		PKTCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-6: Transfer size.

PKTCNT

Bit 19: Packet count.

STUPCNT

Bits 29-30: SETUP packet count.

DOEPCTL1

device endpoint-1 control register

Offset: 0x320, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SODDFRM
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		Stall
rw 		SNPM
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPID

Bit 16: EONUM/DPID.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

SNPM

Bit 20: SNPM.

Stall

Bit 21: Stall.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID/SEVNFRM.

SODDFRM

Bit 29: SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DOEPINT1

device endpoint-1 interrupt register

Offset: 0x328, size: 32, reset: 0x00000080, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2BSTUP
rw 		OTEPDIS
rw 		STUP
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

STUP

Bit 3: STUP.

OTEPDIS

Bit 4: OTEPDIS.

B2BSTUP

Bit 6: B2BSTUP.

DOEPTSIZ1

device OUT endpoint-1 transfer size register

Offset: 0x330, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDPID_STUPCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

RXDPID_STUPCNT

Bits 29-30: Received data PID/SETUP packet count.

DOEPCTL2

device endpoint-2 control register

Offset: 0x340, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SODDFRM
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		Stall
rw 		SNPM
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPID

Bit 16: EONUM/DPID.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

SNPM

Bit 20: SNPM.

Stall

Bit 21: Stall.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID/SEVNFRM.

SODDFRM

Bit 29: SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DOEPINT2

device endpoint-2 interrupt register

Offset: 0x348, size: 32, reset: 0x00000080, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2BSTUP
rw 		OTEPDIS
rw 		STUP
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

STUP

Bit 3: STUP.

OTEPDIS

Bit 4: OTEPDIS.

B2BSTUP

Bit 6: B2BSTUP.

DOEPTSIZ2

device OUT endpoint-2 transfer size register

Offset: 0x350, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDPID_STUPCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

RXDPID_STUPCNT

Bits 29-30: Received data PID/SETUP packet count.

DOEPCTL3

device endpoint-3 control register

Offset: 0x360, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SODDFRM
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		Stall
rw 		SNPM
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPID

Bit 16: EONUM/DPID.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

SNPM

Bit 20: SNPM.

Stall

Bit 21: Stall.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID/SEVNFRM.

SODDFRM

Bit 29: SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DOEPINT3

device endpoint-3 interrupt register

Offset: 0x368, size: 32, reset: 0x00000080, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2BSTUP
rw 		OTEPDIS
rw 		STUP
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

STUP

Bit 3: STUP.

OTEPDIS

Bit 4: OTEPDIS.

B2BSTUP

Bit 6: B2BSTUP.

DOEPTSIZ3

device OUT endpoint-3 transfer size register

Offset: 0x370, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDPID_STUPCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

RXDPID_STUPCNT

Bits 29-30: Received data PID/SETUP packet count.

OTG_FS_GLOBAL

0x50000000: USB on the go full speed

32/115 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 FS_GOTGCTL
0x4 FS_GOTGINT
0x8 FS_GAHBCFG
0xc FS_GUSBCFG
0x10 FS_GRSTCTL
0x14 FS_GINTSTS
0x18 FS_GINTMSK
0x1c FS_GRXSTSR_Device
0x1c FS_GRXSTSR_Host
0x24 FS_GRXFSIZ
0x28 FS_GNPTXFSIZ_Device
0x28 FS_GNPTXFSIZ_Host
0x2c FS_GNPTXSTS
0x38 FS_GCCFG
0x3c FS_CID
0x100 FS_HPTXFSIZ
0x104 FS_DIEPTXF1
0x108 FS_DIEPTXF2
0x10c FS_DIEPTXF3
Toggle registers

FS_GOTGCTL

OTG_FS control and status register (OTG_FS_GOTGCTL)

Offset: 0x0, size: 32, reset: 0x00000800, access: Unspecified

6/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BSVLD
r 		ASVLD
r 		DBCT
r 		CIDSTS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DHNPEN
rw 		HSHNPEN
rw 		HNPRQ
rw 		HNGSCS
r 		SRQ
rw 		SRQSCS
r
Toggle fields

SRQSCS

Bit 0: Session request success.

SRQ

Bit 1: Session request.

HNGSCS

Bit 8: Host negotiation success.

HNPRQ

Bit 9: HNP request.

HSHNPEN

Bit 10: Host set HNP enable.

DHNPEN

Bit 11: Device HNP enabled.

CIDSTS

Bit 16: Connector ID status.

DBCT

Bit 17: Long/short debounce time.

ASVLD

Bit 18: A-session valid.

BSVLD

Bit 19: B-session valid.

FS_GOTGINT

OTG_FS interrupt register (OTG_FS_GOTGINT)

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBCDNE
rw 		ADTOCHG
rw 		HNGDET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HNSSCHG
rw 		SRSSCHG
rw 		SEDET
rw
Toggle fields

SEDET

Bit 2: Session end detected.

SRSSCHG

Bit 8: Session request success status change.

HNSSCHG

Bit 9: Host negotiation success status change.

HNGDET

Bit 17: Host negotiation detected.

ADTOCHG

Bit 18: A-device timeout change.

DBCDNE

Bit 19: Debounce done.

FS_GAHBCFG

OTG_FS AHB configuration register (OTG_FS_GAHBCFG)

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTXFELVL
rw 		TXFELVL
rw 		GINT
rw
Toggle fields

GINT

Bit 0: Global interrupt mask.

TXFELVL

Bit 7: TxFIFO empty level.

PTXFELVL

Bit 8: Periodic TxFIFO empty level.

FS_GUSBCFG

OTG_FS USB configuration register (OTG_FS_GUSBCFG)

Offset: 0xc, size: 32, reset: 0x00000A00, access: Unspecified

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTXPKT
rw 		FDMOD
rw 		FHMOD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRDT
rw 		HNPCAP
rw 		SRPCAP
rw 		PHYSEL
w 		TOCAL
rw
Toggle fields

TOCAL

Bits 0-2: FS timeout calibration.

PHYSEL

Bit 6: Full Speed serial transceiver select.

SRPCAP

Bit 8: SRP-capable.

HNPCAP

Bit 9: HNP-capable.

TRDT

Bits 10-13: USB turnaround time.

FHMOD

Bit 29: Force host mode.

FDMOD

Bit 30: Force device mode.

CTXPKT

Bit 31: Corrupt Tx packet.

FS_GRSTCTL

OTG_FS reset register (OTG_FS_GRSTCTL)

Offset: 0x10, size: 32, reset: 0x20000000, access: Unspecified

1/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AHBIDL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFNUM
rw 		TXFFLSH
rw 		RXFFLSH
rw 		FCRST
rw 		HSRST
rw 		CSRST
rw
Toggle fields

CSRST

Bit 0: Core soft reset.

HSRST

Bit 1: HCLK soft reset.

FCRST

Bit 2: Host frame counter reset.

RXFFLSH

Bit 4: RxFIFO flush.

TXFFLSH

Bit 5: TxFIFO flush.

TXFNUM

Bits 6-10: TxFIFO number.

AHBIDL

Bit 31: AHB master idle.

FS_GINTSTS

OTG_FS core interrupt register (OTG_FS_GINTSTS)

Offset: 0x14, size: 32, reset: 0x04000020, access: Unspecified

11/25 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WKUPINT
rw 		SRQINT
rw 		DISCINT
rw 		CIDSCHG
rw 		PTXFE
r 		HCINT
r 		HPRTINT
r 		IPXFR_INCOMPISOOUT
rw 		IISOIXFR
rw 		OEPINT
r 		IEPINT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOPF
rw 		ISOODRP
rw 		ENUMDNE
rw 		USBRST
rw 		USBSUSP
rw 		ESUSP
rw 		GOUTNAKEFF
r 		GINAKEFF
r 		NPTXFE
r 		RXFLVL
r 		SOF
rw 		OTGINT
r 		MMIS
rw 		CMOD
r
Toggle fields

CMOD

Bit 0: Current mode of operation.

MMIS

Bit 1: Mode mismatch interrupt.

OTGINT

Bit 2: OTG interrupt.

SOF

Bit 3: Start of frame.

RXFLVL

Bit 4: RxFIFO non-empty.

NPTXFE

Bit 5: Non-periodic TxFIFO empty.

GINAKEFF

Bit 6: Global IN non-periodic NAK effective.

GOUTNAKEFF

Bit 7: Global OUT NAK effective.

ESUSP

Bit 10: Early suspend.

USBSUSP

Bit 11: USB suspend.

USBRST

Bit 12: USB reset.

ENUMDNE

Bit 13: Enumeration done.

ISOODRP

Bit 14: Isochronous OUT packet dropped interrupt.

EOPF

Bit 15: End of periodic frame interrupt.

IEPINT

Bit 18: IN endpoint interrupt.

OEPINT

Bit 19: OUT endpoint interrupt.

IISOIXFR

Bit 20: Incomplete isochronous IN transfer.

IPXFR_INCOMPISOOUT

Bit 21: Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode).

HPRTINT

Bit 24: Host port interrupt.

HCINT

Bit 25: Host channels interrupt.

PTXFE

Bit 26: Periodic TxFIFO empty.

CIDSCHG

Bit 28: Connector ID status change.

DISCINT

Bit 29: Disconnect detected interrupt.

SRQINT

Bit 30: Session request/new session detected interrupt.

WKUPINT

Bit 31: Resume/remote wakeup detected interrupt.

FS_GINTMSK

OTG_FS interrupt mask register (OTG_FS_GINTMSK)

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

1/25 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUIM
rw 		SRQIM
rw 		DISCINT
rw 		CIDSCHGM
rw 		PTXFEM
rw 		HCIM
rw 		PRTIM
r 		IPXFRM_IISOOXFRM
rw 		IISOIXFRM
rw 		OEPINT
rw 		IEPINT
rw 		EPMISM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOPFM
rw 		ISOODRPM
rw 		ENUMDNEM
rw 		USBRST
rw 		USBSUSPM
rw 		ESUSPM
rw 		GONAKEFFM
rw 		GINAKEFFM
rw 		NPTXFEM
rw 		RXFLVLM
rw 		SOFM
rw 		OTGINT
rw 		MMISM
rw
Toggle fields

MMISM

Bit 1: Mode mismatch interrupt mask.

OTGINT

Bit 2: OTG interrupt mask.

SOFM

Bit 3: Start of frame mask.

RXFLVLM

Bit 4: Receive FIFO non-empty mask.

NPTXFEM

Bit 5: Non-periodic TxFIFO empty mask.

GINAKEFFM

Bit 6: Global non-periodic IN NAK effective mask.

GONAKEFFM

Bit 7: Global OUT NAK effective mask.

ESUSPM

Bit 10: Early suspend mask.

USBSUSPM

Bit 11: USB suspend mask.

USBRST

Bit 12: USB reset mask.

ENUMDNEM

Bit 13: Enumeration done mask.

ISOODRPM

Bit 14: Isochronous OUT packet dropped interrupt mask.

EOPFM

Bit 15: End of periodic frame interrupt mask.

EPMISM

Bit 17: Endpoint mismatch interrupt mask.

IEPINT

Bit 18: IN endpoints interrupt mask.

OEPINT

Bit 19: OUT endpoints interrupt mask.

IISOIXFRM

Bit 20: Incomplete isochronous IN transfer mask.

IPXFRM_IISOOXFRM

Bit 21: Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode).

PRTIM

Bit 24: Host port interrupt mask.

HCIM

Bit 25: Host channels interrupt mask.

PTXFEM

Bit 26: Periodic TxFIFO empty mask.

CIDSCHGM

Bit 28: Connector ID status change mask.

DISCINT

Bit 29: Disconnect detected interrupt mask.

SRQIM

Bit 30: Session request/new session detected interrupt mask.

WUIM

Bit 31: Resume/remote wakeup detected interrupt mask.

FS_GRXSTSR_Device

OTG_FS Receive status debug read(Device mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FRMNUM
r 		PKTSTS
r 		DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPID
r 		BCNT
r 		EPNUM
r
Toggle fields

EPNUM

Bits 0-3: Endpoint number.

BCNT

Bits 4-14: Byte count.

DPID

Bits 15-16: Data PID.

PKTSTS

Bits 17-20: Packet status.

FRMNUM

Bits 21-24: Frame number.

FS_GRXSTSR_Host

OTG_FS Receive status debug read(Hostmode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FRMNUM
r 		PKTSTS
r 		DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPID
r 		BCNT
r 		EPNUM
r
Toggle fields

EPNUM

Bits 0-3: Endpoint number.

BCNT

Bits 4-14: Byte count.

DPID

Bits 15-16: Data PID.

PKTSTS

Bits 17-20: Packet status.

FRMNUM

Bits 21-24: Frame number.

FS_GRXFSIZ

OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)

Offset: 0x24, size: 32, reset: 0x00000200, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXFD
rw
Toggle fields

RXFD

Bits 0-15: RxFIFO depth.

FS_GNPTXFSIZ_Device

OTG_FS non-periodic transmit FIFO size register (Device mode)

Offset: 0x28, size: 32, reset: 0x00000200, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TX0FD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TX0FSA
rw
Toggle fields

TX0FSA

Bits 0-15: Endpoint 0 transmit RAM start address.

TX0FD

Bits 16-31: Endpoint 0 TxFIFO depth.

FS_GNPTXFSIZ_Host

OTG_FS non-periodic transmit FIFO size register (Host mode)

Offset: 0x28, size: 32, reset: 0x00000200, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPTXFSA
rw
Toggle fields

NPTXFSA

Bits 0-15: Non-periodic transmit RAM start address.

NPTXFD

Bits 16-31: Non-periodic TxFIFO depth.

FS_GNPTXSTS

OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)

Offset: 0x2c, size: 32, reset: 0x00080200, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPTXQTOP
r 		NPTQXSAV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPTXFSAV
r
Toggle fields

NPTXFSAV

Bits 0-15: Non-periodic TxFIFO space available.

NPTQXSAV

Bits 16-23: Non-periodic transmit request queue space available.

NPTXQTOP

Bits 24-30: Top of the non-periodic transmit request queue.

FS_GCCFG

OTG_FS general core configuration register (OTG_FS_GCCFG)

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SOFOUTEN
rw 		VBUSBSEN
rw 		VBUSASEN
rw 		PWRDWN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

PWRDWN

Bit 16: Power down.

VBUSASEN

Bit 18: Enable the VBUS sensing device.

VBUSBSEN

Bit 19: Enable the VBUS sensing device.

SOFOUTEN

Bit 20: SOF output enable.

FS_CID

core ID register

Offset: 0x3c, size: 32, reset: 0x00001000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRODUCT_ID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRODUCT_ID
rw
Toggle fields

PRODUCT_ID

Bits 0-31: Product ID field.

FS_HPTXFSIZ

OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)

Offset: 0x100, size: 32, reset: 0x02000600, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTXFSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTXSA
rw
Toggle fields

PTXSA

Bits 0-15: Host periodic TxFIFO start address.

PTXFSIZ

Bits 16-31: Host periodic TxFIFO depth.

FS_DIEPTXF1

OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)

Offset: 0x104, size: 32, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle fields

INEPTXSA

Bits 0-15: IN endpoint FIFO2 transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

FS_DIEPTXF2

OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)

Offset: 0x108, size: 32, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle fields

INEPTXSA

Bits 0-15: IN endpoint FIFO3 transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

FS_DIEPTXF3

OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)

Offset: 0x10c, size: 32, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle fields

INEPTXSA

Bits 0-15: IN endpoint FIFO4 transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

OTG_FS_HOST

0x50000400: USB on the go full speed

10/279 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 FS_HCFG
0x4 HFIR
0x8 FS_HFNUM
0x10 FS_HPTXSTS
0x14 HAINT
0x18 HAINTMSK
0x40 FS_HPRT
0x100 FS_HCCHAR0
0x108 FS_HCINT0
0x10c FS_HCINTMSK0
0x110 FS_HCTSIZ0
0x120 FS_HCCHAR1
0x128 FS_HCINT1
0x12c FS_HCINTMSK1
0x130 FS_HCTSIZ1
0x140 FS_HCCHAR2
0x148 FS_HCINT2
0x14c FS_HCINTMSK2
0x150 FS_HCTSIZ2
0x160 FS_HCCHAR3
0x168 FS_HCINT3
0x16c FS_HCINTMSK3
0x170 FS_HCTSIZ3
0x180 FS_HCCHAR4
0x188 FS_HCINT4
0x18c FS_HCINTMSK4
0x190 FS_HCTSIZ4
0x1a0 FS_HCCHAR5
0x1a8 FS_HCINT5
0x1ac FS_HCINTMSK5
0x1b0 FS_HCTSIZ5
0x1c0 FS_HCCHAR6
0x1c8 FS_HCINT6
0x1cc FS_HCINTMSK6
0x1d0 FS_HCTSIZ6
0x1e0 FS_HCCHAR7
0x1e8 FS_HCINT7
0x1ec FS_HCINTMSK7
0x1f0 FS_HCTSIZ7
Toggle registers

FS_HCFG

OTG_FS host configuration register (OTG_FS_HCFG)

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSLSS
r 		FSLSPCS
rw
Toggle fields

FSLSPCS

Bits 0-1: FS/LS PHY clock select.

FSLSS

Bit 2: FS- and LS-only support.

HFIR

OTG_FS Host frame interval register

Offset: 0x4, size: 32, reset: 0x0000EA60, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FRIVL
rw
Toggle fields

FRIVL

Bits 0-15: Frame interval.

FS_HFNUM

OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)

Offset: 0x8, size: 32, reset: 0x00003FFF, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FTREM
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FRNUM
r
Toggle fields

FRNUM

Bits 0-15: Frame number.

FTREM

Bits 16-31: Frame time remaining.

FS_HPTXSTS

OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)

Offset: 0x10, size: 32, reset: 0x00080100, access: Unspecified

2/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTXQTOP
r 		PTXQSAV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTXFSAVL
rw
Toggle fields

PTXFSAVL

Bits 0-15: Periodic transmit data FIFO space available.

PTXQSAV

Bits 16-23: Periodic transmit request queue space available.

PTXQTOP

Bits 24-31: Top of the periodic transmit request queue.

HAINT

OTG_FS Host all channels interrupt register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HAINT
r
Toggle fields

HAINT

Bits 0-15: Channel interrupts.

HAINTMSK

OTG_FS host all channels interrupt mask register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HAINTM
rw
Toggle fields

HAINTM

Bits 0-15: Channel interrupt mask.

FS_HPRT

OTG_FS host port control and status register (OTG_FS_HPRT)

Offset: 0x40, size: 32, reset: 0x00000000, access: Unspecified

4/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PSPD
r 		PTCTL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTCTL
rw 		PPWR
rw 		PLSTS
r 		PRST
rw 		PSUSP
rw 		PRES
rw 		POCCHNG
rw 		POCA
r 		PENCHNG
rw 		PENA
rw 		PCDET
rw 		PCSTS
r
Toggle fields

PCSTS

Bit 0: Port connect status.

PCDET

Bit 1: Port connect detected.

PENA

Bit 2: Port enable.

PENCHNG

Bit 3: Port enable/disable change.

POCA

Bit 4: Port overcurrent active.

POCCHNG

Bit 5: Port overcurrent change.

PRES

Bit 6: Port resume.

PSUSP

Bit 7: Port suspend.

PRST

Bit 8: Port reset.

PLSTS

Bits 10-11: Port line status.

PPWR

Bit 12: Port power.

PTCTL

Bits 13-16: Port test control.

PSPD

Bits 17-18: Port speed.

FS_HCCHAR0

OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		ODDFRM
rw 		DAD
rw 		MCNT
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

FS_HCINT0

OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		ACK
rw 		NAK
rw 		STALL
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

FS_HCINTMSK0

OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

FS_HCTSIZ0

OTG_FS host channel-0 transfer size register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

FS_HCCHAR1

OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1)

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		ODDFRM
rw 		DAD
rw 		MCNT
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

FS_HCINT1

OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1)

Offset: 0x128, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		ACK
rw 		NAK
rw 		STALL
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

FS_HCINTMSK1

OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1)

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

FS_HCTSIZ1

OTG_FS host channel-1 transfer size register

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

FS_HCCHAR2

OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2)

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		ODDFRM
rw 		DAD
rw 		MCNT
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

FS_HCINT2

OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2)

Offset: 0x148, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		ACK
rw 		NAK
rw 		STALL
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

FS_HCINTMSK2

OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2)

Offset: 0x14c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

FS_HCTSIZ2

OTG_FS host channel-2 transfer size register

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

FS_HCCHAR3

OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3)

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		ODDFRM
rw 		DAD
rw 		MCNT
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

FS_HCINT3

OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3)

Offset: 0x168, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		ACK
rw 		NAK
rw 		STALL
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

FS_HCINTMSK3

OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3)

Offset: 0x16c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

FS_HCTSIZ3

OTG_FS host channel-3 transfer size register

Offset: 0x170, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

FS_HCCHAR4

OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4)

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		ODDFRM
rw 		DAD
rw 		MCNT
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

FS_HCINT4

OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4)

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		ACK
rw 		NAK
rw 		STALL
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

FS_HCINTMSK4

OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4)

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

FS_HCTSIZ4

OTG_FS host channel-x transfer size register

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

FS_HCCHAR5

OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5)

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		ODDFRM
rw 		DAD
rw 		MCNT
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

FS_HCINT5

OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5)

Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		ACK
rw 		NAK
rw 		STALL
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

FS_HCINTMSK5

OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5)

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

FS_HCTSIZ5

OTG_FS host channel-5 transfer size register

Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

FS_HCCHAR6

OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6)

Offset: 0x1c0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		ODDFRM
rw 		DAD
rw 		MCNT
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

FS_HCINT6

OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6)

Offset: 0x1c8, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		ACK
rw 		NAK
rw 		STALL
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

FS_HCINTMSK6

OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6)

Offset: 0x1cc, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

FS_HCTSIZ6

OTG_FS host channel-6 transfer size register

Offset: 0x1d0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

FS_HCCHAR7

OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7)

Offset: 0x1e0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		ODDFRM
rw 		DAD
rw 		MCNT
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

FS_HCINT7

OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7)

Offset: 0x1e8, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		ACK
rw 		NAK
rw 		STALL
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

FS_HCINTMSK7

OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7)

Offset: 0x1ec, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

FS_HCTSIZ7

OTG_FS host channel-7 transfer size register

Offset: 0x1f0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

OTG_FS_PWRCLK

0x50000e00: USB on the go full speed

0/3 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 FS_PCGCCTL
Toggle registers

FS_PCGCCTL

OTG_FS power and clock gating control register (OTG_FS_PCGCCTL)

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PHYSUSP
rw 		GATEHCLK
rw 		STPPCLK
rw
Toggle fields

STPPCLK

Bit 0: Stop PHY clock.

GATEHCLK

Bit 1: Gate HCLK.

PHYSUSP

Bit 4: PHY Suspended.

OTG_HS_DEVICE

0x40040800: USB on the go high speed

49/403 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 OTG_HS_DCFG
0x4 OTG_HS_DCTL
0x8 OTG_HS_DSTS
0x10 OTG_HS_DIEPMSK
0x14 OTG_HS_DOEPMSK
0x18 OTG_HS_DAINT
0x1c OTG_HS_DAINTMSK
0x28 OTG_HS_DVBUSDIS
0x2c OTG_HS_DVBUSPULSE
0x30 OTG_HS_DTHRCTL
0x34 OTG_HS_DIEPEMPMSK
0x38 OTG_HS_DEACHINT
0x3c OTG_HS_DEACHINTMSK
0x40 OTG_HS_DIEPEACHMSK1
0x80 OTG_HS_DOEPEACHMSK1
0x100 OTG_HS_DIEPCTL0
0x108 OTG_HS_DIEPINT0
0x110 OTG_HS_DIEPTSIZ0
0x114 OTG_HS_DIEPDMA1
0x118 OTG_HS_DTXFSTS0
0x120 OTG_HS_DIEPCTL1
0x128 OTG_HS_DIEPINT1
0x130 OTG_HS_DIEPTSIZ1
0x134 OTG_HS_DIEPDMA2
0x138 OTG_HS_DTXFSTS1
0x140 OTG_HS_DIEPCTL2
0x148 OTG_HS_DIEPINT2
0x150 OTG_HS_DIEPTSIZ2
0x154 OTG_HS_DIEPDMA3
0x158 OTG_HS_DTXFSTS2
0x160 OTG_HS_DIEPCTL3
0x168 OTG_HS_DIEPINT3
0x170 OTG_HS_DIEPTSIZ3
0x174 OTG_HS_DIEPDMA4
0x178 OTG_HS_DTXFSTS3
0x180 OTG_HS_DIEPCTL4
0x188 OTG_HS_DIEPINT4
0x190 OTG_HS_DIEPTSIZ4
0x194 OTG_HS_DIEPDMA5
0x198 OTG_HS_DTXFSTS4
0x1a0 OTG_HS_DIEPCTL5
0x1a8 OTG_HS_DIEPINT5
0x1b0 OTG_HS_DIEPTSIZ5
0x1b8 OTG_HS_DTXFSTS5
0x1c0 OTG_HS_DIEPCTL6
0x1c8 OTG_HS_DIEPINT6
0x1e0 OTG_HS_DIEPCTL7
0x1e8 OTG_HS_DIEPINT7
0x300 OTG_HS_DOEPCTL0
0x308 OTG_HS_DOEPINT0
0x310 OTG_HS_DOEPTSIZ0
0x320 OTG_HS_DOEPCTL1
0x328 OTG_HS_DOEPINT1
0x330 OTG_HS_DOEPTSIZ1
0x340 OTG_HS_DOEPCTL2
0x348 OTG_HS_DOEPINT2
0x350 OTG_HS_DOEPTSIZ2
0x360 OTG_HS_DOEPCTL3
0x368 OTG_HS_DOEPINT3
0x370 OTG_HS_DOEPTSIZ3
0x388 OTG_HS_DOEPINT4
0x390 OTG_HS_DOEPTSIZ4
0x3a8 OTG_HS_DOEPINT5
0x3c8 OTG_HS_DOEPINT6
0x3e8 OTG_HS_DOEPINT7
Toggle registers

OTG_HS_DCFG

OTG_HS device configuration register

Offset: 0x0, size: 32, reset: 0x02200000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PERSCHIVL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PFIVL
rw 		DAD
rw 		NZLSOHSK
rw 		DSPD
rw
Toggle fields

DSPD

Bits 0-1: Device speed.

NZLSOHSK

Bit 2: Nonzero-length status OUT handshake.

DAD

Bits 4-10: Device address.

PFIVL

Bits 11-12: Periodic (micro)frame interval.

PERSCHIVL

Bits 24-25: Periodic scheduling interval.

OTG_HS_DCTL

OTG_HS device control register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

2/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POPRGDNE
rw 		CGONAK
w 		SGONAK
w 		CGINAK
w 		SGINAK
w 		TCTL
rw 		GONSTS
r 		GINSTS
r 		SDIS
rw 		RWUSIG
rw
Toggle fields

RWUSIG

Bit 0: Remote wakeup signaling.

SDIS

Bit 1: Soft disconnect.

GINSTS

Bit 2: Global IN NAK status.

GONSTS

Bit 3: Global OUT NAK status.

TCTL

Bits 4-6: Test control.

SGINAK

Bit 7: Set global IN NAK.

CGINAK

Bit 8: Clear global IN NAK.

SGONAK

Bit 9: Set global OUT NAK.

CGONAK

Bit 10: Clear global OUT NAK.

POPRGDNE

Bit 11: Power-on programming done.

OTG_HS_DSTS

OTG_HS device status register

Offset: 0x8, size: 32, reset: 0x00000010, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FNSOF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FNSOF
r 		EERR
r 		ENUMSPD
r 		SUSPSTS
r
Toggle fields

SUSPSTS

Bit 0: Suspend status.

ENUMSPD

Bits 1-2: Enumerated speed.

EERR

Bit 3: Erratic error.

FNSOF

Bits 8-21: Frame number of the received SOF.

OTG_HS_DIEPMSK

OTG_HS device IN endpoint common interrupt mask register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIM
rw 		TXFURM
rw 		INEPNEM
rw 		INEPNMM
rw 		ITTXFEMSK
rw 		TOM
rw 		EPDM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed interrupt mask.

EPDM

Bit 1: Endpoint disabled interrupt mask.

TOM

Bit 3: Timeout condition mask (nonisochronous endpoints).

ITTXFEMSK

Bit 4: IN token received when TxFIFO empty mask.

INEPNMM

Bit 5: IN token received with EP mismatch mask.

INEPNEM

Bit 6: IN endpoint NAK effective mask.

TXFURM

Bit 8: FIFO underrun mask.

BIM

Bit 9: BNA interrupt mask.

OTG_HS_DOEPMSK

OTG_HS device OUT endpoint common interrupt mask register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOIM
rw 		OPEM
rw 		B2BSTUP
rw 		OTEPDM
rw 		STUPM
rw 		EPDM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed interrupt mask.

EPDM

Bit 1: Endpoint disabled interrupt mask.

STUPM

Bit 3: SETUP phase done mask.

OTEPDM

Bit 4: OUT token received when endpoint disabled mask.

B2BSTUP

Bit 6: Back-to-back SETUP packets received mask.

OPEM

Bit 8: OUT packet error mask.

BOIM

Bit 9: BNA interrupt mask.

OTG_HS_DAINT

OTG_HS device all endpoints interrupt register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OEPINT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPINT
r
Toggle fields

IEPINT

Bits 0-15: IN endpoint interrupt bits.

OEPINT

Bits 16-31: OUT endpoint interrupt bits.

OTG_HS_DAINTMSK

OTG_HS all endpoints interrupt mask register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OEPM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPM
rw
Toggle fields

IEPM

Bits 0-15: IN EP interrupt mask bits.

OEPM

Bits 16-31: OUT EP interrupt mask bits.

OTG_HS_DVBUSDIS

OTG_HS device VBUS discharge time register

Offset: 0x28, size: 32, reset: 0x000017D7, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VBUSDT
rw
Toggle fields

VBUSDT

Bits 0-15: Device VBUS discharge time.

OTG_HS_DVBUSPULSE

OTG_HS device VBUS pulsing time register

Offset: 0x2c, size: 32, reset: 0x000005B8, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DVBUSP
rw
Toggle fields

DVBUSP

Bits 0-11: Device VBUS pulsing time.

OTG_HS_DTHRCTL

OTG_HS Device threshold control register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARPEN
rw 		RXTHRLEN
rw 		RXTHREN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXTHRLEN
rw 		ISOTHREN
rw 		NONISOTHREN
rw
Toggle fields

NONISOTHREN

Bit 0: Nonisochronous IN endpoints threshold enable.

ISOTHREN

Bit 1: ISO IN endpoint threshold enable.

TXTHRLEN

Bits 2-10: Transmit threshold length.

RXTHREN

Bit 16: Receive threshold enable.

RXTHRLEN

Bits 17-25: Receive threshold length.

ARPEN

Bit 27: Arbiter parking enable.

OTG_HS_DIEPEMPMSK

OTG_HS device IN endpoint FIFO empty interrupt mask register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXFEM
rw
Toggle fields

INEPTXFEM

Bits 0-15: IN EP Tx FIFO empty interrupt mask bits.

OTG_HS_DEACHINT

OTG_HS device each endpoint interrupt register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OEP1INT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEP1INT
rw
Toggle fields

IEP1INT

Bit 1: IN endpoint 1interrupt bit.

OEP1INT

Bit 17: OUT endpoint 1 interrupt bit.

OTG_HS_DEACHINTMSK

OTG_HS device each endpoint interrupt register mask

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OEP1INTM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEP1INTM
rw
Toggle fields

IEP1INTM

Bit 1: IN Endpoint 1 interrupt mask bit.

OEP1INTM

Bit 17: OUT Endpoint 1 interrupt mask bit.

OTG_HS_DIEPEACHMSK1

OTG_HS device each in endpoint-1 interrupt register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAKM
rw 		BIM
rw 		TXFURM
rw 		INEPNEM
rw 		INEPNMM
rw 		ITTXFEMSK
rw 		TOM
rw 		EPDM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed interrupt mask.

EPDM

Bit 1: Endpoint disabled interrupt mask.

TOM

Bit 3: Timeout condition mask (nonisochronous endpoints).

ITTXFEMSK

Bit 4: IN token received when TxFIFO empty mask.

INEPNMM

Bit 5: IN token received with EP mismatch mask.

INEPNEM

Bit 6: IN endpoint NAK effective mask.

TXFURM

Bit 8: FIFO underrun mask.

BIM

Bit 9: BNA interrupt mask.

NAKM

Bit 13: NAK interrupt mask.

OTG_HS_DOEPEACHMSK1

OTG_HS device each OUT endpoint-1 interrupt register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NYETM
rw 		NAKM
rw 		BERRM
rw 		BIM
rw 		TXFURM
rw 		INEPNEM
rw 		INEPNMM
rw 		ITTXFEMSK
rw 		TOM
rw 		EPDM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed interrupt mask.

EPDM

Bit 1: Endpoint disabled interrupt mask.

TOM

Bit 3: Timeout condition mask.

ITTXFEMSK

Bit 4: IN token received when TxFIFO empty mask.

INEPNMM

Bit 5: IN token received with EP mismatch mask.

INEPNEM

Bit 6: IN endpoint NAK effective mask.

TXFURM

Bit 8: OUT packet error mask.

BIM

Bit 9: BNA interrupt mask.

BERRM

Bit 12: Bubble error interrupt mask.

NAKM

Bit 13: NAK interrupt mask.

NYETM

Bit 14: NYET interrupt mask.

OTG_HS_DIEPCTL0

OTG device endpoint-0 control register

Offset: 0x100, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SODDFRM
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		TXFNUM
rw 		Stall
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even/odd frame.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

Stall

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TxFIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

OTG_HS_DIEPINT0

OTG device endpoint-0 interrupt register

Offset: 0x108, size: 32, reset: 0x00000080, access: Unspecified

1/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw 		BERR
rw 		PKTDRPSTS
rw 		BNA
rw 		TXFIFOUDRN
rw 		TXFE
r 		INEPNE
rw 		ITTXFE
rw 		TOC
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

TOC

Bit 3: Timeout condition.

ITTXFE

Bit 4: IN token received when TxFIFO is empty.

INEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

TXFIFOUDRN

Bit 8: Transmit Fifo Underrun.

BNA

Bit 9: Buffer not available interrupt.

PKTDRPSTS

Bit 11: Packet dropped status.

BERR

Bit 12: Babble error interrupt.

NAK

Bit 13: NAK interrupt.

OTG_HS_DIEPTSIZ0

OTG_HS device IN endpoint 0 transfer size register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PKTCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-6: Transfer size.

PKTCNT

Bits 19-20: Packet count.

OTG_HS_DIEPDMA1

OTG_HS device endpoint-1 DMA address register

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

OTG_HS_DTXFSTS0

OTG_HS device IN endpoint transmit FIFO status register

Offset: 0x118, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle fields

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space avail.

OTG_HS_DIEPCTL1

OTG device endpoint-1 control register

Offset: 0x120, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SODDFRM
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		TXFNUM
rw 		Stall
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even/odd frame.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

Stall

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TxFIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

OTG_HS_DIEPINT1

OTG device endpoint-1 interrupt register

Offset: 0x128, size: 32, reset: 0x00000000, access: Unspecified

1/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw 		BERR
rw 		PKTDRPSTS
rw 		BNA
rw 		TXFIFOUDRN
rw 		TXFE
r 		INEPNE
rw 		ITTXFE
rw 		TOC
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

TOC

Bit 3: Timeout condition.

ITTXFE

Bit 4: IN token received when TxFIFO is empty.

INEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

TXFIFOUDRN

Bit 8: Transmit Fifo Underrun.

BNA

Bit 9: Buffer not available interrupt.

PKTDRPSTS

Bit 11: Packet dropped status.

BERR

Bit 12: Babble error interrupt.

NAK

Bit 13: NAK interrupt.

OTG_HS_DIEPTSIZ1

OTG_HS device endpoint transfer size register

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

OTG_HS_DIEPDMA2

OTG_HS device endpoint-2 DMA address register

Offset: 0x134, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

OTG_HS_DTXFSTS1

OTG_HS device IN endpoint transmit FIFO status register

Offset: 0x138, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle fields

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space avail.

OTG_HS_DIEPCTL2

OTG device endpoint-2 control register

Offset: 0x140, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SODDFRM
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		TXFNUM
rw 		Stall
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even/odd frame.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

Stall

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TxFIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

OTG_HS_DIEPINT2

OTG device endpoint-2 interrupt register

Offset: 0x148, size: 32, reset: 0x00000000, access: Unspecified

1/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw 		BERR
rw 		PKTDRPSTS
rw 		BNA
rw 		TXFIFOUDRN
rw 		TXFE
r 		INEPNE
rw 		ITTXFE
rw 		TOC
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

TOC

Bit 3: Timeout condition.

ITTXFE

Bit 4: IN token received when TxFIFO is empty.

INEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

TXFIFOUDRN

Bit 8: Transmit Fifo Underrun.

BNA

Bit 9: Buffer not available interrupt.

PKTDRPSTS

Bit 11: Packet dropped status.

BERR

Bit 12: Babble error interrupt.

NAK

Bit 13: NAK interrupt.

OTG_HS_DIEPTSIZ2

OTG_HS device endpoint transfer size register

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

OTG_HS_DIEPDMA3

OTG_HS device endpoint-3 DMA address register

Offset: 0x154, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

OTG_HS_DTXFSTS2

OTG_HS device IN endpoint transmit FIFO status register

Offset: 0x158, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle fields

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space avail.

OTG_HS_DIEPCTL3

OTG device endpoint-3 control register

Offset: 0x160, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SODDFRM
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		TXFNUM
rw 		Stall
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even/odd frame.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

Stall

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TxFIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

OTG_HS_DIEPINT3

OTG device endpoint-3 interrupt register

Offset: 0x168, size: 32, reset: 0x00000000, access: Unspecified

1/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw 		BERR
rw 		PKTDRPSTS
rw 		BNA
rw 		TXFIFOUDRN
rw 		TXFE
r 		INEPNE
rw 		ITTXFE
rw 		TOC
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

TOC

Bit 3: Timeout condition.

ITTXFE

Bit 4: IN token received when TxFIFO is empty.

INEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

TXFIFOUDRN

Bit 8: Transmit Fifo Underrun.

BNA

Bit 9: Buffer not available interrupt.

PKTDRPSTS

Bit 11: Packet dropped status.

BERR

Bit 12: Babble error interrupt.

NAK

Bit 13: NAK interrupt.

OTG_HS_DIEPTSIZ3

OTG_HS device endpoint transfer size register

Offset: 0x170, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

OTG_HS_DIEPDMA4

OTG_HS device endpoint-4 DMA address register

Offset: 0x174, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

OTG_HS_DTXFSTS3

OTG_HS device IN endpoint transmit FIFO status register

Offset: 0x178, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle fields

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space avail.

OTG_HS_DIEPCTL4

OTG device endpoint-4 control register

Offset: 0x180, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SODDFRM
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		TXFNUM
rw 		Stall
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even/odd frame.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

Stall

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TxFIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

OTG_HS_DIEPINT4

OTG device endpoint-4 interrupt register

Offset: 0x188, size: 32, reset: 0x00000000, access: Unspecified

1/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw 		BERR
rw 		PKTDRPSTS
rw 		BNA
rw 		TXFIFOUDRN
rw 		TXFE
r 		INEPNE
rw 		ITTXFE
rw 		TOC
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

TOC

Bit 3: Timeout condition.

ITTXFE

Bit 4: IN token received when TxFIFO is empty.

INEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

TXFIFOUDRN

Bit 8: Transmit Fifo Underrun.

BNA

Bit 9: Buffer not available interrupt.

PKTDRPSTS

Bit 11: Packet dropped status.

BERR

Bit 12: Babble error interrupt.

NAK

Bit 13: NAK interrupt.

OTG_HS_DIEPTSIZ4

OTG_HS device endpoint transfer size register

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

OTG_HS_DIEPDMA5

OTG_HS device endpoint-5 DMA address register

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

OTG_HS_DTXFSTS4

OTG_HS device IN endpoint transmit FIFO status register

Offset: 0x198, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle fields

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space avail.

OTG_HS_DIEPCTL5

OTG device endpoint-5 control register

Offset: 0x1a0, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SODDFRM
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		TXFNUM
rw 		Stall
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even/odd frame.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

Stall

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TxFIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

OTG_HS_DIEPINT5

OTG device endpoint-5 interrupt register

Offset: 0x1a8, size: 32, reset: 0x00000000, access: Unspecified

1/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw 		BERR
rw 		PKTDRPSTS
rw 		BNA
rw 		TXFIFOUDRN
rw 		TXFE
r 		INEPNE
rw 		ITTXFE
rw 		TOC
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

TOC

Bit 3: Timeout condition.

ITTXFE

Bit 4: IN token received when TxFIFO is empty.

INEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

TXFIFOUDRN

Bit 8: Transmit Fifo Underrun.

BNA

Bit 9: Buffer not available interrupt.

PKTDRPSTS

Bit 11: Packet dropped status.

BERR

Bit 12: Babble error interrupt.

NAK

Bit 13: NAK interrupt.

OTG_HS_DIEPTSIZ5

OTG_HS device endpoint transfer size register

Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

OTG_HS_DTXFSTS5

OTG_HS device IN endpoint transmit FIFO status register

Offset: 0x1b8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle fields

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space avail.

OTG_HS_DIEPCTL6

OTG device endpoint-6 control register

Offset: 0x1c0, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SODDFRM
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		TXFNUM
rw 		Stall
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even/odd frame.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

Stall

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TxFIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

OTG_HS_DIEPINT6

OTG device endpoint-6 interrupt register

Offset: 0x1c8, size: 32, reset: 0x00000000, access: Unspecified

1/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw 		BERR
rw 		PKTDRPSTS
rw 		BNA
rw 		TXFIFOUDRN
rw 		TXFE
r 		INEPNE
rw 		ITTXFE
rw 		TOC
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

TOC

Bit 3: Timeout condition.

ITTXFE

Bit 4: IN token received when TxFIFO is empty.

INEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

TXFIFOUDRN

Bit 8: Transmit Fifo Underrun.

BNA

Bit 9: Buffer not available interrupt.

PKTDRPSTS

Bit 11: Packet dropped status.

BERR

Bit 12: Babble error interrupt.

NAK

Bit 13: NAK interrupt.

OTG_HS_DIEPCTL7

OTG device endpoint-7 control register

Offset: 0x1e0, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SODDFRM
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		TXFNUM
rw 		Stall
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even/odd frame.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

Stall

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TxFIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

OTG_HS_DIEPINT7

OTG device endpoint-7 interrupt register

Offset: 0x1e8, size: 32, reset: 0x00000000, access: Unspecified

1/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw 		BERR
rw 		PKTDRPSTS
rw 		BNA
rw 		TXFIFOUDRN
rw 		TXFE
r 		INEPNE
rw 		ITTXFE
rw 		TOC
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

TOC

Bit 3: Timeout condition.

ITTXFE

Bit 4: IN token received when TxFIFO is empty.

INEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

TXFIFOUDRN

Bit 8: Transmit Fifo Underrun.

BNA

Bit 9: Buffer not available interrupt.

PKTDRPSTS

Bit 11: Packet dropped status.

BERR

Bit 12: Babble error interrupt.

NAK

Bit 13: NAK interrupt.

OTG_HS_DOEPCTL0

OTG_HS device control OUT endpoint 0 control register

Offset: 0x300, size: 32, reset: 0x00008000, access: Unspecified

5/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
w 		EPDIS
r 		SNAK
w 		CNAK
w 		Stall
rw 		SNPM
rw 		EPTYP
r 		NAKSTS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
r 		MPSIZ
r
Toggle fields

MPSIZ

Bits 0-1: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

SNPM

Bit 20: Snoop mode.

Stall

Bit 21: STALL handshake.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

OTG_HS_DOEPINT0

OTG_HS device endpoint-0 interrupt register

Offset: 0x308, size: 32, reset: 0x00000080, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NYET
rw 		B2BSTUP
rw 		OTEPDIS
rw 		STUP
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

STUP

Bit 3: SETUP phase done.

OTEPDIS

Bit 4: OUT token received when endpoint disabled.

B2BSTUP

Bit 6: Back-to-back SETUP packets received.

NYET

Bit 14: NYET interrupt.

OTG_HS_DOEPTSIZ0

OTG_HS device endpoint-1 transfer size register

Offset: 0x310, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STUPCNT
rw 		PKTCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-6: Transfer size.

PKTCNT

Bit 19: Packet count.

STUPCNT

Bits 29-30: SETUP packet count.

OTG_HS_DOEPCTL1

OTG device endpoint-1 control register

Offset: 0x320, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SODDFRM
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		Stall
rw 		SNPM
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even odd frame/Endpoint data PID.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

SNPM

Bit 20: Snoop mode.

Stall

Bit 21: STALL handshake.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID/Set even frame.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

OTG_HS_DOEPINT1

OTG_HS device endpoint-1 interrupt register

Offset: 0x328, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NYET
rw 		B2BSTUP
rw 		OTEPDIS
rw 		STUP
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

STUP

Bit 3: SETUP phase done.

OTEPDIS

Bit 4: OUT token received when endpoint disabled.

B2BSTUP

Bit 6: Back-to-back SETUP packets received.

NYET

Bit 14: NYET interrupt.

OTG_HS_DOEPTSIZ1

OTG_HS device endpoint-2 transfer size register

Offset: 0x330, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDPID_STUPCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

RXDPID_STUPCNT

Bits 29-30: Received data PID/SETUP packet count.

OTG_HS_DOEPCTL2

OTG device endpoint-2 control register

Offset: 0x340, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SODDFRM
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		Stall
rw 		SNPM
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even odd frame/Endpoint data PID.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

SNPM

Bit 20: Snoop mode.

Stall

Bit 21: STALL handshake.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID/Set even frame.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

OTG_HS_DOEPINT2

OTG_HS device endpoint-2 interrupt register

Offset: 0x348, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NYET
rw 		B2BSTUP
rw 		OTEPDIS
rw 		STUP
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

STUP

Bit 3: SETUP phase done.

OTEPDIS

Bit 4: OUT token received when endpoint disabled.

B2BSTUP

Bit 6: Back-to-back SETUP packets received.

NYET

Bit 14: NYET interrupt.

OTG_HS_DOEPTSIZ2

OTG_HS device endpoint-3 transfer size register

Offset: 0x350, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDPID_STUPCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

RXDPID_STUPCNT

Bits 29-30: Received data PID/SETUP packet count.

OTG_HS_DOEPCTL3

OTG device endpoint-3 control register

Offset: 0x360, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SODDFRM
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		Stall
rw 		SNPM
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even odd frame/Endpoint data PID.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

SNPM

Bit 20: Snoop mode.

Stall

Bit 21: STALL handshake.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID/Set even frame.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

OTG_HS_DOEPINT3

OTG_HS device endpoint-3 interrupt register

Offset: 0x368, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NYET
rw 		B2BSTUP
rw 		OTEPDIS
rw 		STUP
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

STUP

Bit 3: SETUP phase done.

OTEPDIS

Bit 4: OUT token received when endpoint disabled.

B2BSTUP

Bit 6: Back-to-back SETUP packets received.

NYET

Bit 14: NYET interrupt.

OTG_HS_DOEPTSIZ3

OTG_HS device endpoint-4 transfer size register

Offset: 0x370, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDPID_STUPCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

RXDPID_STUPCNT

Bits 29-30: Received data PID/SETUP packet count.

OTG_HS_DOEPINT4

OTG_HS device endpoint-4 interrupt register

Offset: 0x388, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NYET
rw 		B2BSTUP
rw 		OTEPDIS
rw 		STUP
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

STUP

Bit 3: SETUP phase done.

OTEPDIS

Bit 4: OUT token received when endpoint disabled.

B2BSTUP

Bit 6: Back-to-back SETUP packets received.

NYET

Bit 14: NYET interrupt.

OTG_HS_DOEPTSIZ4

OTG_HS device endpoint-5 transfer size register

Offset: 0x390, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDPID_STUPCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

RXDPID_STUPCNT

Bits 29-30: Received data PID/SETUP packet count.

OTG_HS_DOEPINT5

OTG_HS device endpoint-5 interrupt register

Offset: 0x3a8, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NYET
rw 		B2BSTUP
rw 		OTEPDIS
rw 		STUP
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

STUP

Bit 3: SETUP phase done.

OTEPDIS

Bit 4: OUT token received when endpoint disabled.

B2BSTUP

Bit 6: Back-to-back SETUP packets received.

NYET

Bit 14: NYET interrupt.

OTG_HS_DOEPINT6

OTG_HS device endpoint-6 interrupt register

Offset: 0x3c8, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NYET
rw 		B2BSTUP
rw 		OTEPDIS
rw 		STUP
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

STUP

Bit 3: SETUP phase done.

OTEPDIS

Bit 4: OUT token received when endpoint disabled.

B2BSTUP

Bit 6: Back-to-back SETUP packets received.

NYET

Bit 14: NYET interrupt.

OTG_HS_DOEPINT7

OTG_HS device endpoint-7 interrupt register

Offset: 0x3e8, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NYET
rw 		B2BSTUP
rw 		OTEPDIS
rw 		STUP
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

STUP

Bit 3: SETUP phase done.

OTEPDIS

Bit 4: OUT token received when endpoint disabled.

B2BSTUP

Bit 6: Back-to-back SETUP packets received.

NYET

Bit 14: NYET interrupt.

OTG_HS_GLOBAL

0x40040000: USB on the go high speed

41/148 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 OTG_HS_GOTGCTL
0x4 OTG_HS_GOTGINT
0x8 OTG_HS_GAHBCFG
0xc OTG_HS_GUSBCFG
0x10 OTG_HS_GRSTCTL
0x14 OTG_HS_GINTSTS
0x18 OTG_HS_GINTMSK
0x1c OTG_HS_GRXSTSR_Host
0x1c OTG_HS_GRXSTSR_Peripheral
0x20 OTG_HS_GRXSTSP_Host
0x20 OTG_HS_GRXSTSP_Peripheral
0x24 OTG_HS_GRXFSIZ
0x28 OTG_HS_GNPTXFSIZ_Host
0x28 OTG_HS_TX0FSIZ_Peripheral
0x2c OTG_HS_GNPTXSTS
0x38 OTG_HS_GCCFG
0x3c OTG_HS_CID
0x100 OTG_HS_HPTXFSIZ
0x104 OTG_HS_DIEPTXF1
0x108 OTG_HS_DIEPTXF2
0x11c OTG_HS_DIEPTXF3
0x120 OTG_HS_DIEPTXF4
0x124 OTG_HS_DIEPTXF5
0x128 OTG_HS_DIEPTXF6
0x12c OTG_HS_DIEPTXF7
Toggle registers

OTG_HS_GOTGCTL

OTG_HS control and status register

Offset: 0x0, size: 32, reset: 0x00000800, access: Unspecified

6/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BSVLD
r 		ASVLD
r 		DBCT
r 		CIDSTS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DHNPEN
rw 		HSHNPEN
rw 		HNPRQ
rw 		HNGSCS
r 		SRQ
rw 		SRQSCS
r
Toggle fields

SRQSCS

Bit 0: Session request success.

SRQ

Bit 1: Session request.

HNGSCS

Bit 8: Host negotiation success.

HNPRQ

Bit 9: HNP request.

HSHNPEN

Bit 10: Host set HNP enable.

DHNPEN

Bit 11: Device HNP enabled.

CIDSTS

Bit 16: Connector ID status.

DBCT

Bit 17: Long/short debounce time.

ASVLD

Bit 18: A-session valid.

BSVLD

Bit 19: B-session valid.

OTG_HS_GOTGINT

OTG_HS interrupt register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBCDNE
rw 		ADTOCHG
rw 		HNGDET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HNSSCHG
rw 		SRSSCHG
rw 		SEDET
rw
Toggle fields

SEDET

Bit 2: Session end detected.

SRSSCHG

Bit 8: Session request success status change.

HNSSCHG

Bit 9: Host negotiation success status change.

HNGDET

Bit 17: Host negotiation detected.

ADTOCHG

Bit 18: A-device timeout change.

DBCDNE

Bit 19: Debounce done.

OTG_HS_GAHBCFG

OTG_HS AHB configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTXFELVL
rw 		TXFELVL
rw 		DMAEN
rw 		HBSTLEN
rw 		GINT
rw
Toggle fields

GINT

Bit 0: Global interrupt mask.

HBSTLEN

Bits 1-4: Burst length/type.

DMAEN

Bit 5: DMA enable.

TXFELVL

Bit 7: TxFIFO empty level.

PTXFELVL

Bit 8: Periodic TxFIFO empty level.

OTG_HS_GUSBCFG

OTG_HS USB configuration register

Offset: 0xc, size: 32, reset: 0x00000A00, access: Unspecified

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTXPKT
rw 		FDMOD
rw 		FHMOD
rw 		ULPIIPD
rw 		PTCI
rw 		PCCI
rw 		TSDPS
rw 		ULPIEVBUSI
rw 		ULPIEVBUSD
rw 		ULPICSM
rw 		ULPIAR
rw 		ULPIFSLS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PHYLPCS
rw 		TRDT
rw 		HNPCAP
rw 		SRPCAP
rw 		PHYSEL
w 		TOCAL
rw
Toggle fields

TOCAL

Bits 0-2: FS timeout calibration.

PHYSEL

Bit 6: USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select.

SRPCAP

Bit 8: SRP-capable.

HNPCAP

Bit 9: HNP-capable.

TRDT

Bits 10-13: USB turnaround time.

PHYLPCS

Bit 15: PHY Low-power clock select.

ULPIFSLS

Bit 17: ULPI FS/LS select.

ULPIAR

Bit 18: ULPI Auto-resume.

ULPICSM

Bit 19: ULPI Clock SuspendM.

ULPIEVBUSD

Bit 20: ULPI External VBUS Drive.

ULPIEVBUSI

Bit 21: ULPI external VBUS indicator.

TSDPS

Bit 22: TermSel DLine pulsing selection.

PCCI

Bit 23: Indicator complement.

PTCI

Bit 24: Indicator pass through.

ULPIIPD

Bit 25: ULPI interface protect disable.

FHMOD

Bit 29: Forced host mode.

FDMOD

Bit 30: Forced peripheral mode.

CTXPKT

Bit 31: Corrupt Tx packet.

OTG_HS_GRSTCTL

OTG_HS reset register

Offset: 0x10, size: 32, reset: 0x20000000, access: Unspecified

2/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AHBIDL
r 		DMAREQ
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFNUM
rw 		TXFFLSH
rw 		RXFFLSH
rw 		FCRST
rw 		HSRST
rw 		CSRST
rw
Toggle fields

CSRST

Bit 0: Core soft reset.

HSRST

Bit 1: HCLK soft reset.

FCRST

Bit 2: Host frame counter reset.

RXFFLSH

Bit 4: RxFIFO flush.

TXFFLSH

Bit 5: TxFIFO flush.

TXFNUM

Bits 6-10: TxFIFO number.

DMAREQ

Bit 30: DMA request signal.

AHBIDL

Bit 31: AHB master idle.

OTG_HS_GINTSTS

OTG_HS core interrupt register

Offset: 0x14, size: 32, reset: 0x04000020, access: Unspecified

11/26 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WKUINT
rw 		SRQINT
rw 		DISCINT
rw 		CIDSCHG
rw 		PTXFE
r 		HCINT
r 		HPRTINT
r 		DATAFSUSP
rw 		PXFR_INCOMPISOOUT
rw 		IISOIXFR
rw 		OEPINT
r 		IEPINT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOPF
rw 		ISOODRP
rw 		ENUMDNE
rw 		USBRST
rw 		USBSUSP
rw 		ESUSP
rw 		BOUTNAKEFF
r 		GINAKEFF
r 		NPTXFE
r 		RXFLVL
r 		SOF
rw 		OTGINT
r 		MMIS
rw 		CMOD
r
Toggle fields

CMOD

Bit 0: Current mode of operation.

MMIS

Bit 1: Mode mismatch interrupt.

OTGINT

Bit 2: OTG interrupt.

SOF

Bit 3: Start of frame.

RXFLVL

Bit 4: RxFIFO nonempty.

NPTXFE

Bit 5: Nonperiodic TxFIFO empty.

GINAKEFF

Bit 6: Global IN nonperiodic NAK effective.

BOUTNAKEFF

Bit 7: Global OUT NAK effective.

ESUSP

Bit 10: Early suspend.

USBSUSP

Bit 11: USB suspend.

USBRST

Bit 12: USB reset.

ENUMDNE

Bit 13: Enumeration done.

ISOODRP

Bit 14: Isochronous OUT packet dropped interrupt.

EOPF

Bit 15: End of periodic frame interrupt.

IEPINT

Bit 18: IN endpoint interrupt.

OEPINT

Bit 19: OUT endpoint interrupt.

IISOIXFR

Bit 20: Incomplete isochronous IN transfer.

PXFR_INCOMPISOOUT

Bit 21: Incomplete periodic transfer.

DATAFSUSP

Bit 22: Data fetch suspended.

HPRTINT

Bit 24: Host port interrupt.

HCINT

Bit 25: Host channels interrupt.

PTXFE

Bit 26: Periodic TxFIFO empty.

CIDSCHG

Bit 28: Connector ID status change.

DISCINT

Bit 29: Disconnect detected interrupt.

SRQINT

Bit 30: Session request/new session detected interrupt.

WKUINT

Bit 31: Resume/remote wakeup detected interrupt.

OTG_HS_GINTMSK

OTG_HS interrupt mask register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

1/26 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUIM
rw 		SRQIM
rw 		DISCINT
rw 		CIDSCHGM
rw 		PTXFEM
rw 		HCIM
rw 		PRTIM
r 		FSUSPM
rw 		PXFRM_IISOOXFRM
rw 		IISOIXFRM
rw 		OEPINT
rw 		IEPINT
rw 		EPMISM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOPFM
rw 		ISOODRPM
rw 		ENUMDNEM
rw 		USBRST
rw 		USBSUSPM
rw 		ESUSPM
rw 		GONAKEFFM
rw 		GINAKEFFM
rw 		NPTXFEM
rw 		RXFLVLM
rw 		SOFM
rw 		OTGINT
rw 		MMISM
rw
Toggle fields

MMISM

Bit 1: Mode mismatch interrupt mask.

OTGINT

Bit 2: OTG interrupt mask.

SOFM

Bit 3: Start of frame mask.

RXFLVLM

Bit 4: Receive FIFO nonempty mask.

NPTXFEM

Bit 5: Nonperiodic TxFIFO empty mask.

GINAKEFFM

Bit 6: Global nonperiodic IN NAK effective mask.

GONAKEFFM

Bit 7: Global OUT NAK effective mask.

ESUSPM

Bit 10: Early suspend mask.

USBSUSPM

Bit 11: USB suspend mask.

USBRST

Bit 12: USB reset mask.

ENUMDNEM

Bit 13: Enumeration done mask.

ISOODRPM

Bit 14: Isochronous OUT packet dropped interrupt mask.

EOPFM

Bit 15: End of periodic frame interrupt mask.

EPMISM

Bit 17: Endpoint mismatch interrupt mask.

IEPINT

Bit 18: IN endpoints interrupt mask.

OEPINT

Bit 19: OUT endpoints interrupt mask.

IISOIXFRM

Bit 20: Incomplete isochronous IN transfer mask.

PXFRM_IISOOXFRM

Bit 21: Incomplete periodic transfer mask.

FSUSPM

Bit 22: Data fetch suspended mask.

PRTIM

Bit 24: Host port interrupt mask.

HCIM

Bit 25: Host channels interrupt mask.

PTXFEM

Bit 26: Periodic TxFIFO empty mask.

CIDSCHGM

Bit 28: Connector ID status change mask.

DISCINT

Bit 29: Disconnect detected interrupt mask.

SRQIM

Bit 30: Session request/new session detected interrupt mask.

WUIM

Bit 31: Resume/remote wakeup detected interrupt mask.

OTG_HS_GRXSTSR_Host

OTG_HS Receive status debug read register (host mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PKTSTS
r 		DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPID
r 		BCNT
r 		CHNUM
r
Toggle fields

CHNUM

Bits 0-3: Channel number.

BCNT

Bits 4-14: Byte count.

DPID

Bits 15-16: Data PID.

PKTSTS

Bits 17-20: Packet status.

OTG_HS_GRXSTSR_Peripheral

OTG_HS Receive status debug read register (peripheral mode mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FRMNUM
r 		PKTSTS
r 		DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPID
r 		BCNT
r 		EPNUM
r
Toggle fields

EPNUM

Bits 0-3: Endpoint number.

BCNT

Bits 4-14: Byte count.

DPID

Bits 15-16: Data PID.

PKTSTS

Bits 17-20: Packet status.

FRMNUM

Bits 21-24: Frame number.

OTG_HS_GRXSTSP_Host

OTG_HS status read and pop register (host mode)

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PKTSTS
r 		DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPID
r 		BCNT
r 		CHNUM
r
Toggle fields

CHNUM

Bits 0-3: Channel number.

BCNT

Bits 4-14: Byte count.

DPID

Bits 15-16: Data PID.

PKTSTS

Bits 17-20: Packet status.

OTG_HS_GRXSTSP_Peripheral

OTG_HS status read and pop register (peripheral mode)

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FRMNUM
r 		PKTSTS
r 		DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPID
r 		BCNT
r 		EPNUM
r
Toggle fields

EPNUM

Bits 0-3: Endpoint number.

BCNT

Bits 4-14: Byte count.

DPID

Bits 15-16: Data PID.

PKTSTS

Bits 17-20: Packet status.

FRMNUM

Bits 21-24: Frame number.

OTG_HS_GRXFSIZ

OTG_HS Receive FIFO size register

Offset: 0x24, size: 32, reset: 0x00000200, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXFD
rw
Toggle fields

RXFD

Bits 0-15: RxFIFO depth.

OTG_HS_GNPTXFSIZ_Host

OTG_HS nonperiodic transmit FIFO size register (host mode)

Offset: 0x28, size: 32, reset: 0x00000200, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPTXFSA
rw
Toggle fields

NPTXFSA

Bits 0-15: Nonperiodic transmit RAM start address.

NPTXFD

Bits 16-31: Nonperiodic TxFIFO depth.

OTG_HS_TX0FSIZ_Peripheral

Endpoint 0 transmit FIFO size (peripheral mode)

Offset: 0x28, size: 32, reset: 0x00000200, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TX0FD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TX0FSA
rw
Toggle fields

TX0FSA

Bits 0-15: Endpoint 0 transmit RAM start address.

TX0FD

Bits 16-31: Endpoint 0 TxFIFO depth.

OTG_HS_GNPTXSTS

OTG_HS nonperiodic transmit FIFO/queue status register

Offset: 0x2c, size: 32, reset: 0x00080200, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPTXQTOP
r 		NPTQXSAV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPTXFSAV
r
Toggle fields

NPTXFSAV

Bits 0-15: Nonperiodic TxFIFO space available.

NPTQXSAV

Bits 16-23: Nonperiodic transmit request queue space available.

NPTXQTOP

Bits 24-30: Top of the nonperiodic transmit request queue.

OTG_HS_GCCFG

OTG_HS general core configuration register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NOVBUSSENS
rw 		SOFOUTEN
rw 		VBUSBSEN
rw 		VBUSASEN
rw 		I2CPADEN
rw 		PWRDWN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

PWRDWN

Bit 16: Power down.

I2CPADEN

Bit 17: Enable I2C bus connection for the external I2C PHY interface.

VBUSASEN

Bit 18: Enable the VBUS sensing device.

VBUSBSEN

Bit 19: Enable the VBUS sensing device.

SOFOUTEN

Bit 20: SOF output enable.

NOVBUSSENS

Bit 21: VBUS sensing disable option.

OTG_HS_CID

OTG_HS core ID register

Offset: 0x3c, size: 32, reset: 0x00001200, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRODUCT_ID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRODUCT_ID
rw
Toggle fields

PRODUCT_ID

Bits 0-31: Product ID field.

OTG_HS_HPTXFSIZ

OTG_HS Host periodic transmit FIFO size register

Offset: 0x100, size: 32, reset: 0x02000600, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTXSA
rw
Toggle fields

PTXSA

Bits 0-15: Host periodic TxFIFO start address.

PTXFD

Bits 16-31: Host periodic TxFIFO depth.

OTG_HS_DIEPTXF1

OTG_HS device IN endpoint transmit FIFO size register

Offset: 0x104, size: 32, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle fields

INEPTXSA

Bits 0-15: IN endpoint FIFOx transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

OTG_HS_DIEPTXF2

OTG_HS device IN endpoint transmit FIFO size register

Offset: 0x108, size: 32, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle fields

INEPTXSA

Bits 0-15: IN endpoint FIFOx transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

OTG_HS_DIEPTXF3

OTG_HS device IN endpoint transmit FIFO size register

Offset: 0x11c, size: 32, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle fields

INEPTXSA

Bits 0-15: IN endpoint FIFOx transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

OTG_HS_DIEPTXF4

OTG_HS device IN endpoint transmit FIFO size register

Offset: 0x120, size: 32, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle fields

INEPTXSA

Bits 0-15: IN endpoint FIFOx transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

OTG_HS_DIEPTXF5

OTG_HS device IN endpoint transmit FIFO size register

Offset: 0x124, size: 32, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle fields

INEPTXSA

Bits 0-15: IN endpoint FIFOx transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

OTG_HS_DIEPTXF6

OTG_HS device IN endpoint transmit FIFO size register

Offset: 0x128, size: 32, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle fields

INEPTXSA

Bits 0-15: IN endpoint FIFOx transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

OTG_HS_DIEPTXF7

OTG_HS device IN endpoint transmit FIFO size register

Offset: 0x12c, size: 32, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle fields

INEPTXSA

Bits 0-15: IN endpoint FIFOx transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

OTG_HS_HOST

0x40040400: USB on the go high speed

10/515 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 OTG_HS_HCFG
0x4 OTG_HS_HFIR
0x8 OTG_HS_HFNUM
0x10 OTG_HS_HPTXSTS
0x14 OTG_HS_HAINT
0x18 OTG_HS_HAINTMSK
0x40 OTG_HS_HPRT
0x100 OTG_HS_HCCHAR0
0x104 OTG_HS_HCSPLT0
0x108 OTG_HS_HCINT0
0x10c OTG_HS_HCINTMSK0
0x110 OTG_HS_HCTSIZ0
0x114 OTG_HS_HCDMA0
0x120 OTG_HS_HCCHAR1
0x124 OTG_HS_HCSPLT1
0x128 OTG_HS_HCINT1
0x12c OTG_HS_HCINTMSK1
0x130 OTG_HS_HCTSIZ1
0x134 OTG_HS_HCDMA1
0x140 OTG_HS_HCCHAR2
0x144 OTG_HS_HCSPLT2
0x148 OTG_HS_HCINT2
0x14c OTG_HS_HCINTMSK2
0x150 OTG_HS_HCTSIZ2
0x154 OTG_HS_HCDMA2
0x160 OTG_HS_HCCHAR3
0x164 OTG_HS_HCSPLT3
0x168 OTG_HS_HCINT3
0x16c OTG_HS_HCINTMSK3
0x170 OTG_HS_HCTSIZ3
0x174 OTG_HS_HCDMA3
0x180 OTG_HS_HCCHAR4
0x184 OTG_HS_HCSPLT4
0x188 OTG_HS_HCINT4
0x18c OTG_HS_HCINTMSK4
0x190 OTG_HS_HCTSIZ4
0x194 OTG_HS_HCDMA4
0x1a0 OTG_HS_HCCHAR5
0x1a4 OTG_HS_HCSPLT5
0x1a8 OTG_HS_HCINT5
0x1ac OTG_HS_HCINTMSK5
0x1b0 OTG_HS_HCTSIZ5
0x1b4 OTG_HS_HCDMA5
0x1c0 OTG_HS_HCCHAR6
0x1c4 OTG_HS_HCSPLT6
0x1c8 OTG_HS_HCINT6
0x1cc OTG_HS_HCINTMSK6
0x1d0 OTG_HS_HCTSIZ6
0x1d4 OTG_HS_HCDMA6
0x1e0 OTG_HS_HCCHAR7
0x1e4 OTG_HS_HCSPLT7
0x1e8 OTG_HS_HCINT7
0x1ec OTG_HS_HCINTMSK7
0x1f0 OTG_HS_HCTSIZ7
0x1f4 OTG_HS_HCDMA7
0x200 OTG_HS_HCCHAR8
0x204 OTG_HS_HCSPLT8
0x208 OTG_HS_HCINT8
0x20c OTG_HS_HCINTMSK8
0x210 OTG_HS_HCTSIZ8
0x214 OTG_HS_HCDMA8
0x220 OTG_HS_HCCHAR9
0x224 OTG_HS_HCSPLT9
0x228 OTG_HS_HCINT9
0x22c OTG_HS_HCINTMSK9
0x230 OTG_HS_HCTSIZ9
0x234 OTG_HS_HCDMA9
0x240 OTG_HS_HCCHAR10
0x244 OTG_HS_HCSPLT10
0x248 OTG_HS_HCINT10
0x24c OTG_HS_HCINTMSK10
0x250 OTG_HS_HCTSIZ10
0x254 OTG_HS_HCDMA10
0x260 OTG_HS_HCCHAR11
0x264 OTG_HS_HCSPLT11
0x268 OTG_HS_HCINT11
0x26c OTG_HS_HCINTMSK11
0x270 OTG_HS_HCTSIZ11
0x274 OTG_HS_HCDMA11
Toggle registers

OTG_HS_HCFG

OTG_HS host configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSLSS
r 		FSLSPCS
rw
Toggle fields

FSLSPCS

Bits 0-1: FS/LS PHY clock select.

FSLSS

Bit 2: FS- and LS-only support.

OTG_HS_HFIR

OTG_HS Host frame interval register

Offset: 0x4, size: 32, reset: 0x0000EA60, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FRIVL
rw
Toggle fields

FRIVL

Bits 0-15: Frame interval.

OTG_HS_HFNUM

OTG_HS host frame number/frame time remaining register

Offset: 0x8, size: 32, reset: 0x00003FFF, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FTREM
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FRNUM
r
Toggle fields

FRNUM

Bits 0-15: Frame number.

FTREM

Bits 16-31: Frame time remaining.

OTG_HS_HPTXSTS

OTG_HS_Host periodic transmit FIFO/queue status register

Offset: 0x10, size: 32, reset: 0x00080100, access: Unspecified

2/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTXQTOP
r 		PTXQSAV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTXFSAVL
rw
Toggle fields

PTXFSAVL

Bits 0-15: Periodic transmit data FIFO space available.

PTXQSAV

Bits 16-23: Periodic transmit request queue space available.

PTXQTOP

Bits 24-31: Top of the periodic transmit request queue.

OTG_HS_HAINT

OTG_HS Host all channels interrupt register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HAINT
r
Toggle fields

HAINT

Bits 0-15: Channel interrupts.

OTG_HS_HAINTMSK

OTG_HS host all channels interrupt mask register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HAINTM
rw
Toggle fields

HAINTM

Bits 0-15: Channel interrupt mask.

OTG_HS_HPRT

OTG_HS host port control and status register

Offset: 0x40, size: 32, reset: 0x00000000, access: Unspecified

4/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PSPD
r 		PTCTL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTCTL
rw 		PPWR
rw 		PLSTS
r 		PRST
rw 		PSUSP
rw 		PRES
rw 		POCCHNG
rw 		POCA
r 		PENCHNG
rw 		PENA
rw 		PCDET
rw 		PCSTS
r
Toggle fields

PCSTS

Bit 0: Port connect status.

PCDET

Bit 1: Port connect detected.

PENA

Bit 2: Port enable.

PENCHNG

Bit 3: Port enable/disable change.

POCA

Bit 4: Port overcurrent active.

POCCHNG

Bit 5: Port overcurrent change.

PRES

Bit 6: Port resume.

PSUSP

Bit 7: Port suspend.

PRST

Bit 8: Port reset.

PLSTS

Bits 10-11: Port line status.

PPWR

Bit 12: Port power.

PTCTL

Bits 13-16: Port test control.

PSPD

Bits 17-18: Port speed.

OTG_HS_HCCHAR0

OTG_HS host channel-0 characteristics register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		ODDFRM
rw 		DAD
rw 		MC
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

OTG_HS_HCSPLT0

OTG_HS host channel-0 split control register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw 		COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw 		HUBADDR
rw 		PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

OTG_HS_HCINT0

OTG_HS host channel-11 interrupt register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		AHBERR
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

OTG_HS_HCINTMSK0

OTG_HS host channel-11 interrupt mask register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		AHBERR
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

OTG_HS_HCTSIZ0

OTG_HS host channel-11 transfer size register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

OTG_HS_HCDMA0

OTG_HS host channel-0 DMA address register

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

OTG_HS_HCCHAR1

OTG_HS host channel-1 characteristics register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		ODDFRM
rw 		DAD
rw 		MC
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

OTG_HS_HCSPLT1

OTG_HS host channel-1 split control register

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw 		COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw 		HUBADDR
rw 		PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

OTG_HS_HCINT1

OTG_HS host channel-1 interrupt register

Offset: 0x128, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		AHBERR
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

OTG_HS_HCINTMSK1

OTG_HS host channel-1 interrupt mask register

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		AHBERR
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

OTG_HS_HCTSIZ1

OTG_HS host channel-1 transfer size register

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

OTG_HS_HCDMA1

OTG_HS host channel-1 DMA address register

Offset: 0x134, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

OTG_HS_HCCHAR2

OTG_HS host channel-2 characteristics register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		ODDFRM
rw 		DAD
rw 		MC
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

OTG_HS_HCSPLT2

OTG_HS host channel-2 split control register

Offset: 0x144, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw 		COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw 		HUBADDR
rw 		PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

OTG_HS_HCINT2

OTG_HS host channel-2 interrupt register

Offset: 0x148, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		AHBERR
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

OTG_HS_HCINTMSK2

OTG_HS host channel-2 interrupt mask register

Offset: 0x14c, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		AHBERR
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

OTG_HS_HCTSIZ2

OTG_HS host channel-2 transfer size register

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

OTG_HS_HCDMA2

OTG_HS host channel-2 DMA address register

Offset: 0x154, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

OTG_HS_HCCHAR3

OTG_HS host channel-3 characteristics register

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		ODDFRM
rw 		DAD
rw 		MC
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

OTG_HS_HCSPLT3

OTG_HS host channel-3 split control register

Offset: 0x164, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw 		COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw 		HUBADDR
rw 		PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

OTG_HS_HCINT3

OTG_HS host channel-3 interrupt register

Offset: 0x168, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		AHBERR
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

OTG_HS_HCINTMSK3

OTG_HS host channel-3 interrupt mask register

Offset: 0x16c, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		AHBERR
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

OTG_HS_HCTSIZ3

OTG_HS host channel-3 transfer size register

Offset: 0x170, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

OTG_HS_HCDMA3

OTG_HS host channel-3 DMA address register

Offset: 0x174, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

OTG_HS_HCCHAR4

OTG_HS host channel-4 characteristics register

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		ODDFRM
rw 		DAD
rw 		MC
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

OTG_HS_HCSPLT4

OTG_HS host channel-4 split control register

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw 		COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw 		HUBADDR
rw 		PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

OTG_HS_HCINT4

OTG_HS host channel-4 interrupt register

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		AHBERR
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

OTG_HS_HCINTMSK4

OTG_HS host channel-4 interrupt mask register

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		AHBERR
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

OTG_HS_HCTSIZ4

OTG_HS host channel-4 transfer size register

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

OTG_HS_HCDMA4

OTG_HS host channel-4 DMA address register

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

OTG_HS_HCCHAR5

OTG_HS host channel-5 characteristics register

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		ODDFRM
rw 		DAD
rw 		MC
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

OTG_HS_HCSPLT5

OTG_HS host channel-5 split control register

Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw 		COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw 		HUBADDR
rw 		PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

OTG_HS_HCINT5

OTG_HS host channel-5 interrupt register

Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		AHBERR
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

OTG_HS_HCINTMSK5

OTG_HS host channel-5 interrupt mask register

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		AHBERR
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

OTG_HS_HCTSIZ5

OTG_HS host channel-5 transfer size register

Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

OTG_HS_HCDMA5

OTG_HS host channel-5 DMA address register

Offset: 0x1b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

OTG_HS_HCCHAR6

OTG_HS host channel-6 characteristics register

Offset: 0x1c0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		ODDFRM
rw 		DAD
rw 		MC
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

OTG_HS_HCSPLT6

OTG_HS host channel-6 split control register

Offset: 0x1c4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw 		COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw 		HUBADDR
rw 		PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

OTG_HS_HCINT6

OTG_HS host channel-6 interrupt register

Offset: 0x1c8, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		AHBERR
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

OTG_HS_HCINTMSK6

OTG_HS host channel-6 interrupt mask register

Offset: 0x1cc, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		AHBERR
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

OTG_HS_HCTSIZ6

OTG_HS host channel-6 transfer size register

Offset: 0x1d0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

OTG_HS_HCDMA6

OTG_HS host channel-6 DMA address register

Offset: 0x1d4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

OTG_HS_HCCHAR7

OTG_HS host channel-7 characteristics register

Offset: 0x1e0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		ODDFRM
rw 		DAD
rw 		MC
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

OTG_HS_HCSPLT7

OTG_HS host channel-7 split control register

Offset: 0x1e4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw 		COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw 		HUBADDR
rw 		PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

OTG_HS_HCINT7

OTG_HS host channel-7 interrupt register

Offset: 0x1e8, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		AHBERR
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

OTG_HS_HCINTMSK7

OTG_HS host channel-7 interrupt mask register

Offset: 0x1ec, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		AHBERR
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

OTG_HS_HCTSIZ7

OTG_HS host channel-7 transfer size register

Offset: 0x1f0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

OTG_HS_HCDMA7

OTG_HS host channel-7 DMA address register

Offset: 0x1f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

OTG_HS_HCCHAR8

OTG_HS host channel-8 characteristics register

Offset: 0x200, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		ODDFRM
rw 		DAD
rw 		MC
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

OTG_HS_HCSPLT8

OTG_HS host channel-8 split control register

Offset: 0x204, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw 		COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw 		HUBADDR
rw 		PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

OTG_HS_HCINT8

OTG_HS host channel-8 interrupt register

Offset: 0x208, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		AHBERR
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

OTG_HS_HCINTMSK8

OTG_HS host channel-8 interrupt mask register

Offset: 0x20c, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		AHBERR
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

OTG_HS_HCTSIZ8

OTG_HS host channel-8 transfer size register

Offset: 0x210, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

OTG_HS_HCDMA8

OTG_HS host channel-8 DMA address register

Offset: 0x214, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

OTG_HS_HCCHAR9

OTG_HS host channel-9 characteristics register

Offset: 0x220, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		ODDFRM
rw 		DAD
rw 		MC
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

OTG_HS_HCSPLT9

OTG_HS host channel-9 split control register

Offset: 0x224, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw 		COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw 		HUBADDR
rw 		PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

OTG_HS_HCINT9

OTG_HS host channel-9 interrupt register

Offset: 0x228, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		AHBERR
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

OTG_HS_HCINTMSK9

OTG_HS host channel-9 interrupt mask register

Offset: 0x22c, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		AHBERR
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

OTG_HS_HCTSIZ9

OTG_HS host channel-9 transfer size register

Offset: 0x230, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

OTG_HS_HCDMA9

OTG_HS host channel-9 DMA address register

Offset: 0x234, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

OTG_HS_HCCHAR10

OTG_HS host channel-10 characteristics register

Offset: 0x240, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		ODDFRM
rw 		DAD
rw 		MC
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

OTG_HS_HCSPLT10

OTG_HS host channel-10 split control register

Offset: 0x244, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw 		COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw 		HUBADDR
rw 		PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

OTG_HS_HCINT10

OTG_HS host channel-10 interrupt register

Offset: 0x248, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		AHBERR
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

OTG_HS_HCINTMSK10

OTG_HS host channel-10 interrupt mask register

Offset: 0x24c, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		AHBERR
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

OTG_HS_HCTSIZ10

OTG_HS host channel-10 transfer size register

Offset: 0x250, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

OTG_HS_HCDMA10

OTG_HS host channel-10 DMA address register

Offset: 0x254, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

OTG_HS_HCCHAR11

OTG_HS host channel-11 characteristics register

Offset: 0x260, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		ODDFRM
rw 		DAD
rw 		MC
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

OTG_HS_HCSPLT11

OTG_HS host channel-11 split control register

Offset: 0x264, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw 		COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw 		HUBADDR
rw 		PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

OTG_HS_HCINT11

OTG_HS host channel-11 interrupt register

Offset: 0x268, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		AHBERR
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

OTG_HS_HCINTMSK11

OTG_HS host channel-11 interrupt mask register

Offset: 0x26c, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		AHBERR
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

OTG_HS_HCTSIZ11

OTG_HS host channel-11 transfer size register

Offset: 0x270, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

OTG_HS_HCDMA11

OTG_HS host channel-11 DMA address register

Offset: 0x274, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

OTG_HS_PWRCLK

0x40040e00: USB on the go high speed

0/3 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 OTG_HS_PCGCR
Toggle registers

OTG_HS_PCGCR

Power and clock gating control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PHYSUSP
rw 		GATEHCLK
rw 		STPPCLK
rw
Toggle fields

STPPCLK

Bit 0: Stop PHY clock.

GATEHCLK

Bit 1: Gate HCLK.

PHYSUSP

Bit 4: PHY suspended.

PWR

0x40007000: Power control

6/24 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 CSR
Toggle registers

CR

power control register

Offset: 0x0, size: 32, reset: 0x0000C000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UDEN
rw 		ODSWEN
rw 		ODEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VOS
rw 		MRLVDS
rw 		LPLVDS
rw 		FPDS
rw 		DBP
rw 		PLS
rw 		PVDE
rw 		CSBF
rw 		CWUF
rw 		PDDS
rw 		LPDS
rw
Toggle fields

LPDS

Bit 0: Low-power deep sleep.

PDDS

Bit 1: Power down deepsleep.

CWUF

Bit 2: Clear wakeup flag.

CSBF

Bit 3: Clear standby flag.

PVDE

Bit 4: Power voltage detector enable.

PLS

Bits 5-7: PVD level selection.

DBP

Bit 8: Disable backup domain write protection.

FPDS

Bit 9: Flash power down in Stop mode.

LPLVDS

Bit 10: Low-Power Regulator Low Voltage in deepsleep.

MRLVDS

Bit 11: Main regulator low voltage in deepsleep mode.

VOS

Bits 14-15: Regulator voltage scaling output selection.

ODEN

Bit 16: Over-drive enable.

ODSWEN

Bit 17: Over-drive switching enabled.

UDEN

Bits 18-19: Under-drive enable in stop mode.

CSR

power control/status register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

6/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UDRDY
rw 		ODSWRDY
r 		ODRDY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VOSRDY
rw 		BRE
rw 		EWUP
rw 		BRR
r 		PVDO
r 		SBF
r 		WUF
r
Toggle fields

WUF

Bit 0: Wakeup flag.

SBF

Bit 1: Standby flag.

PVDO

Bit 2: PVD output.

BRR

Bit 3: Backup regulator ready.

EWUP

Bit 8: Enable WKUP pin.

BRE

Bit 9: Backup regulator enable.

VOSRDY

Bit 14: Regulator voltage scaling output selection ready bit.

ODRDY

Bit 16: Over-drive mode ready.

ODSWRDY

Bit 17: Over-drive mode switching ready.

UDRDY

Bits 18-19: Under-drive ready flag.

RCC

0x40023800: Reset and clock control

16/287 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 PLLCFGR
0x8 CFGR
0xc CIR
0x10 AHB1RSTR
0x14 AHB2RSTR
0x18 AHB3RSTR
0x20 APB1RSTR
0x24 APB2RSTR
0x30 AHB1ENR
0x34 AHB2ENR
0x38 AHB3ENR
0x40 APB1ENR
0x44 APB2ENR
0x50 AHB1LPENR
0x54 AHB2LPENR
0x58 AHB3LPENR
0x60 APB1LPENR
0x64 APB2LPENR
0x70 BDCR
0x74 CSR
0x80 SSCGR
0x84 PLLI2SCFGR
Toggle registers

CR

clock control register

Offset: 0x0, size: 32, reset: 0x00000083, access: Unspecified

5/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLSAIRDY
rw 		PLLSAION
rw 		PLLI2SRDY
r 		PLLI2SON
rw 		PLLRDY
r 		PLLON
rw 		CSSON
rw 		HSEBYP
rw 		HSERDY
r 		HSEON
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSICAL
r 		HSITRIM
rw 		HSIRDY
r 		HSION
rw
Toggle fields

HSION

Bit 0: Internal high-speed clock enable.

HSIRDY

Bit 1: Internal high-speed clock ready flag.

HSITRIM

Bits 3-7: Internal high-speed clock trimming.

HSICAL

Bits 8-15: Internal high-speed clock calibration.

HSEON

Bit 16: HSE clock enable.

HSERDY

Bit 17: HSE clock ready flag.

HSEBYP

Bit 18: HSE clock bypass.

CSSON

Bit 19: Clock security system enable.

PLLON

Bit 24: Main PLL (PLL) enable.

PLLRDY

Bit 25: Main PLL (PLL) clock ready flag.

PLLI2SON

Bit 26: PLLI2S enable.

PLLI2SRDY

Bit 27: PLLI2S clock ready flag.

PLLSAION

Bit 28: PLLSAI enable.

PLLSAIRDY

Bit 29: PLLSAI clock ready flag.

PLLCFGR

PLL configuration register

Offset: 0x4, size: 32, reset: 0x24003010, access: read-write

0/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLQ3
rw 		PLLQ2
rw 		PLLQ1
rw 		PLLQ0
rw 		PLLSRC
rw 		PLLP1
rw 		PLLP0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLN8
rw 		PLLN7
rw 		PLLN6
rw 		PLLN5
rw 		PLLN4
rw 		PLLN3
rw 		PLLN2
rw 		PLLN1
rw 		PLLN0
rw 		PLLM5
rw 		PLLM4
rw 		PLLM3
rw 		PLLM2
rw 		PLLM1
rw 		PLLM0
rw
Toggle fields

PLLM0

Bit 0: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock.

PLLM1

Bit 1: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock.

PLLM2

Bit 2: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock.

PLLM3

Bit 3: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock.

PLLM4

Bit 4: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock.

PLLM5

Bit 5: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock.

PLLN0

Bit 6: Main PLL (PLL) multiplication factor for VCO.

PLLN1

Bit 7: Main PLL (PLL) multiplication factor for VCO.

PLLN2

Bit 8: Main PLL (PLL) multiplication factor for VCO.

PLLN3

Bit 9: Main PLL (PLL) multiplication factor for VCO.

PLLN4

Bit 10: Main PLL (PLL) multiplication factor for VCO.

PLLN5

Bit 11: Main PLL (PLL) multiplication factor for VCO.

PLLN6

Bit 12: Main PLL (PLL) multiplication factor for VCO.

PLLN7

Bit 13: Main PLL (PLL) multiplication factor for VCO.

PLLN8

Bit 14: Main PLL (PLL) multiplication factor for VCO.

PLLP0

Bit 16: Main PLL (PLL) division factor for main system clock.

PLLP1

Bit 17: Main PLL (PLL) division factor for main system clock.

PLLSRC

Bit 22: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source.

PLLQ0

Bit 24: Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks.

PLLQ1

Bit 25: Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks.

PLLQ2

Bit 26: Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks.

PLLQ3

Bit 27: Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks.

CFGR

clock configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCO2
rw 		MCO2PRE
rw 		MCO1PRE
rw 		I2SSRC
rw 		MCO1
rw 		RTCPRE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PPRE2
rw 		PPRE1
rw 		HPRE
rw 		SWS1
r 		SWS0
r 		SW1
rw 		SW0
rw
Toggle fields

SW0

Bit 0: System clock switch.

SW1

Bit 1: System clock switch.

SWS0

Bit 2: System clock switch status.

SWS1

Bit 3: System clock switch status.

HPRE

Bits 4-7: AHB prescaler.

PPRE1

Bits 10-12: APB Low speed prescaler (APB1).

PPRE2

Bits 13-15: APB high-speed prescaler (APB2).

RTCPRE

Bits 16-20: HSE division factor for RTC clock.

MCO1

Bits 21-22: Microcontroller clock output 1.

I2SSRC

Bit 23: I2S clock selection.

MCO1PRE

Bits 24-26: MCO1 prescaler.

MCO2PRE

Bits 27-29: MCO2 prescaler.

MCO2

Bits 30-31: Microcontroller clock output 2.

CIR

clock interrupt register

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

7/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSSC
w 		PLLI2SRDYC
w 		PLLRDYC
w 		HSERDYC
w 		HSIRDYC
w 		LSERDYC
w 		LSIRDYC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLI2SRDYIE
rw 		PLLRDYIE
rw 		HSERDYIE
rw 		HSIRDYIE
rw 		LSERDYIE
rw 		LSIRDYIE
rw 		CSSF
r 		PLLI2SRDYF
r 		PLLRDYF
r 		HSERDYF
r 		HSIRDYF
r 		LSERDYF
r 		LSIRDYF
r
Toggle fields

LSIRDYF

Bit 0: LSI ready interrupt flag.

LSERDYF

Bit 1: LSE ready interrupt flag.

HSIRDYF

Bit 2: HSI ready interrupt flag.

HSERDYF

Bit 3: HSE ready interrupt flag.

PLLRDYF

Bit 4: Main PLL (PLL) ready interrupt flag.

PLLI2SRDYF

Bit 5: PLLI2S ready interrupt flag.

CSSF

Bit 7: Clock security system interrupt flag.

LSIRDYIE

Bit 8: LSI ready interrupt enable.

LSERDYIE

Bit 9: LSE ready interrupt enable.

HSIRDYIE

Bit 10: HSI ready interrupt enable.

HSERDYIE

Bit 11: HSE ready interrupt enable.

PLLRDYIE

Bit 12: Main PLL (PLL) ready interrupt enable.

PLLI2SRDYIE

Bit 13: PLLI2S ready interrupt enable.

LSIRDYC

Bit 16: LSI ready interrupt clear.

LSERDYC

Bit 17: LSE ready interrupt clear.

HSIRDYC

Bit 18: HSI ready interrupt clear.

HSERDYC

Bit 19: HSE ready interrupt clear.

PLLRDYC

Bit 20: Main PLL(PLL) ready interrupt clear.

PLLI2SRDYC

Bit 21: PLLI2S ready interrupt clear.

CSSC

Bit 23: Clock security system interrupt clear.

AHB1RSTR

AHB1 peripheral reset register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTGHSRST
rw 		ETHMACRST
rw 		DMA2RST
rw 		DMA1RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCRST
rw 		GPIOIRST
rw 		GPIOHRST
rw 		GPIOGRST
rw 		GPIOFRST
rw 		GPIOERST
rw 		GPIODRST
rw 		GPIOCRST
rw 		GPIOBRST
rw 		GPIOARST
rw
Toggle fields

GPIOARST

Bit 0: IO port A reset.

GPIOBRST

Bit 1: IO port B reset.

GPIOCRST

Bit 2: IO port C reset.

GPIODRST

Bit 3: IO port D reset.

GPIOERST

Bit 4: IO port E reset.

GPIOFRST

Bit 5: IO port F reset.

GPIOGRST

Bit 6: IO port G reset.

GPIOHRST

Bit 7: IO port H reset.

GPIOIRST

Bit 8: IO port I reset.

CRCRST

Bit 12: CRC reset.

DMA1RST

Bit 21: DMA2 reset.

DMA2RST

Bit 22: DMA2 reset.

ETHMACRST

Bit 25: Ethernet MAC reset.

OTGHSRST

Bit 29: USB OTG HS module reset.

AHB2RSTR

AHB2 peripheral reset register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OTGFSRST
rw 		RNGRST
rw 		HSAHRST
rw 		CRYPRST
rw 		DCMIRST
rw
Toggle fields

DCMIRST

Bit 0: Camera interface reset.

CRYPRST

Bit 4: Cryptographic module reset.

HSAHRST

Bit 5: Hash module reset.

RNGRST

Bit 6: Random number generator module reset.

OTGFSRST

Bit 7: USB OTG FS module reset.

AHB3RSTR

AHB3 peripheral reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMCRST
rw
Toggle fields

FMCRST

Bit 0: Flexible static memory controller module reset.

APB1RSTR

APB1 peripheral reset register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/25 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UART8RST
rw 		UART7RST
rw 		DACRST
rw 		PWRRST
rw 		CAN2RST
rw 		CAN1RST
rw 		I2C3RST
rw 		I2C2RST
rw 		I2C1RST
rw 		UART5RST
rw 		UART4RST
rw 		UART3RST
rw 		UART2RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3RST
rw 		SPI2RST
rw 		WWDGRST
rw 		TIM14RST
rw 		TIM13RST
rw 		TIM12RST
rw 		TIM7RST
rw 		TIM6RST
rw 		TIM5RST
rw 		TIM4RST
rw 		TIM3RST
rw 		TIM2RST
rw
Toggle fields

TIM2RST

Bit 0: TIM2 reset.

TIM3RST

Bit 1: TIM3 reset.

TIM4RST

Bit 2: TIM4 reset.

TIM5RST

Bit 3: TIM5 reset.

TIM6RST

Bit 4: TIM6 reset.

TIM7RST

Bit 5: TIM7 reset.

TIM12RST

Bit 6: TIM12 reset.

TIM13RST

Bit 7: TIM13 reset.

TIM14RST

Bit 8: TIM14 reset.

WWDGRST

Bit 11: Window watchdog reset.

SPI2RST

Bit 14: SPI 2 reset.

SPI3RST

Bit 15: SPI 3 reset.

UART2RST

Bit 17: USART 2 reset.

UART3RST

Bit 18: USART 3 reset.

UART4RST

Bit 19: USART 4 reset.

UART5RST

Bit 20: USART 5 reset.

I2C1RST

Bit 21: I2C 1 reset.

I2C2RST

Bit 22: I2C 2 reset.

I2C3RST

Bit 23: I2C3 reset.

CAN1RST

Bit 25: CAN1 reset.

CAN2RST

Bit 26: CAN2 reset.

PWRRST

Bit 28: Power interface reset.

DACRST

Bit 29: DAC reset.

UART7RST

Bit 30: UART7 reset.

UART8RST

Bit 31: UART8 reset.

APB2RSTR

APB2 peripheral reset register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIM11RST
rw 		TIM10RST
rw 		TIM9RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYSCFGRST
rw 		SPI1RST
rw 		SDIORST
rw 		ADCRST
rw 		USART6RST
rw 		USART1RST
rw 		TIM8RST
rw 		TIM1RST
rw
Toggle fields

TIM1RST

Bit 0: TIM1 reset.

TIM8RST

Bit 1: TIM8 reset.

USART1RST

Bit 4: USART1 reset.

USART6RST

Bit 5: USART6 reset.

ADCRST

Bit 8: ADC interface reset (common to all ADCs).

SDIORST

Bit 11: SDIO reset.

SPI1RST

Bit 12: SPI 1 reset.

SYSCFGRST

Bit 14: System configuration controller reset.

TIM9RST

Bit 16: TIM9 reset.

TIM10RST

Bit 17: TIM10 reset.

TIM11RST

Bit 18: TIM11 reset.

AHB1ENR

AHB1 peripheral clock register

Offset: 0x30, size: 32, reset: 0x00100000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTGHSULPIEN
rw 		OTGHSEN
rw 		ETHMACPTPEN
rw 		ETHMACRXEN
rw 		ETHMACTXEN
rw 		ETHMACEN
rw 		DMA2EN
rw 		DMA1EN
rw 		CCMDATARAMEN
rw 		BKPSRAMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCEN
rw 		GPIOIEN
rw 		GPIOHEN
rw 		GPIOGEN
rw 		GPIOFEN
rw 		GPIOEEN
rw 		GPIODEN
rw 		GPIOCEN
rw 		GPIOBEN
rw 		GPIOAEN
rw
Toggle fields

GPIOAEN

Bit 0: IO port A clock enable.

GPIOBEN

Bit 1: IO port B clock enable.

GPIOCEN

Bit 2: IO port C clock enable.

GPIODEN

Bit 3: IO port D clock enable.

GPIOEEN

Bit 4: IO port E clock enable.

GPIOFEN

Bit 5: IO port F clock enable.

GPIOGEN

Bit 6: IO port G clock enable.

GPIOHEN

Bit 7: IO port H clock enable.

GPIOIEN

Bit 8: IO port I clock enable.

CRCEN

Bit 12: CRC clock enable.

BKPSRAMEN

Bit 18: Backup SRAM interface clock enable.

CCMDATARAMEN

Bit 20: CCM data RAM clock enable.

DMA1EN

Bit 21: DMA1 clock enable.

DMA2EN

Bit 22: DMA2 clock enable.

ETHMACEN

Bit 25: Ethernet MAC clock enable.

ETHMACTXEN

Bit 26: Ethernet Transmission clock enable.

ETHMACRXEN

Bit 27: Ethernet Reception clock enable.

ETHMACPTPEN

Bit 28: Ethernet PTP clock enable.

OTGHSEN

Bit 29: USB OTG HS clock enable.

OTGHSULPIEN

Bit 30: USB OTG HSULPI clock enable.

AHB2ENR

AHB2 peripheral clock enable register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OTGFSEN
rw 		RNGEN
rw 		HASHEN
rw 		CRYPEN
rw 		DCMIEN
rw
Toggle fields

DCMIEN

Bit 0: Camera interface enable.

CRYPEN

Bit 4: Cryptographic modules clock enable.

HASHEN

Bit 5: Hash modules clock enable.

RNGEN

Bit 6: Random number generator clock enable.

OTGFSEN

Bit 7: USB OTG FS clock enable.

AHB3ENR

AHB3 peripheral clock enable register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMCEN
rw
Toggle fields

FMCEN

Bit 0: Flexible static memory controller module clock enable.

APB1ENR

APB1 peripheral clock enable register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/25 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UART8ENR
rw 		UART7ENR
rw 		DACEN
rw 		PWREN
rw 		CAN2EN
rw 		CAN1EN
rw 		I2C3EN
rw 		I2C2EN
rw 		I2C1EN
rw 		UART5EN
rw 		UART4EN
rw 		USART3EN
rw 		USART2EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3EN
rw 		SPI2EN
rw 		WWDGEN
rw 		TIM14EN
rw 		TIM13EN
rw 		TIM12EN
rw 		TIM7EN
rw 		TIM6EN
rw 		TIM5EN
rw 		TIM4EN
rw 		TIM3EN
rw 		TIM2EN
rw
Toggle fields

TIM2EN

Bit 0: TIM2 clock enable.

TIM3EN

Bit 1: TIM3 clock enable.

TIM4EN

Bit 2: TIM4 clock enable.

TIM5EN

Bit 3: TIM5 clock enable.

TIM6EN

Bit 4: TIM6 clock enable.

TIM7EN

Bit 5: TIM7 clock enable.

TIM12EN

Bit 6: TIM12 clock enable.

TIM13EN

Bit 7: TIM13 clock enable.

TIM14EN

Bit 8: TIM14 clock enable.

WWDGEN

Bit 11: Window watchdog clock enable.

SPI2EN

Bit 14: SPI2 clock enable.

SPI3EN

Bit 15: SPI3 clock enable.

USART2EN

Bit 17: USART 2 clock enable.

USART3EN

Bit 18: USART3 clock enable.

UART4EN

Bit 19: UART4 clock enable.

UART5EN

Bit 20: UART5 clock enable.

I2C1EN

Bit 21: I2C1 clock enable.

I2C2EN

Bit 22: I2C2 clock enable.

I2C3EN

Bit 23: I2C3 clock enable.

CAN1EN

Bit 25: CAN 1 clock enable.

CAN2EN

Bit 26: CAN 2 clock enable.

PWREN

Bit 28: Power interface clock enable.

DACEN

Bit 29: DAC interface clock enable.

UART7ENR

Bit 30: UART7 clock enable.

UART8ENR

Bit 31: UART8 clock enable.

APB2ENR

APB2 peripheral clock enable register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LTDCEN
rw 		SAI1EN
rw 		SPI6EN
rw 		SPI5EN
rw 		TIM11EN
rw 		TIM10EN
rw 		TIM9EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYSCFGEN
rw 		SPI4EN
rw 		SPI1EN
rw 		SDIOEN
rw 		ADC3EN
rw 		ADC2EN
rw 		ADC1EN
rw 		USART6EN
rw 		USART1EN
rw 		TIM8EN
rw 		TIM1EN
rw
Toggle fields

TIM1EN

Bit 0: TIM1 clock enable.

TIM8EN

Bit 1: TIM8 clock enable.

USART1EN

Bit 4: USART1 clock enable.

USART6EN

Bit 5: USART6 clock enable.

ADC1EN

Bit 8: ADC1 clock enable.

ADC2EN

Bit 9: ADC2 clock enable.

ADC3EN

Bit 10: ADC3 clock enable.

SDIOEN

Bit 11: SDIO clock enable.

SPI1EN

Bit 12: SPI1 clock enable.

SPI4EN

Bit 13: SPI4 clock enable.

SYSCFGEN

Bit 14: System configuration controller clock enable.

TIM9EN

Bit 16: TIM9 clock enable.

TIM10EN

Bit 17: TIM10 clock enable.

TIM11EN

Bit 18: TIM11 clock enable.

SPI5EN

Bit 20: SPI5 clock enable.

SPI6EN

Bit 21: SPI6 clock enable.

SAI1EN

Bit 22: SAI1 clock enable.

LTDCEN

Bit 26: LTDC clock enable.

AHB1LPENR

AHB1 peripheral clock enable in low power mode register

Offset: 0x50, size: 32, reset: 0x7E6791FF, access: read-write

0/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTGHSULPILPEN
rw 		OTGHSLPEN
rw 		ETHMACPTPLPEN
rw 		ETHMACRXLPEN
rw 		ETHMACTXLPEN
rw 		ETHMACLPEN
rw 		DMA2LPEN
rw 		DMA1LPEN
rw 		SRAM3LPEN
rw 		BKPSRAMLPEN
rw 		SRAM2LPEN
rw 		SRAM1LPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLITFLPEN
rw 		CRCLPEN
rw 		GPIOILPEN
rw 		GPIOHLPEN
rw 		GPIOGLPEN
rw 		GPIOFLPEN
rw 		GPIOELPEN
rw 		GPIODLPEN
rw 		GPIOCLPEN
rw 		GPIOBLPEN
rw 		GPIOALPEN
rw
Toggle fields

GPIOALPEN

Bit 0: IO port A clock enable during sleep mode.

GPIOBLPEN

Bit 1: IO port B clock enable during Sleep mode.

GPIOCLPEN

Bit 2: IO port C clock enable during Sleep mode.

GPIODLPEN

Bit 3: IO port D clock enable during Sleep mode.

GPIOELPEN

Bit 4: IO port E clock enable during Sleep mode.

GPIOFLPEN

Bit 5: IO port F clock enable during Sleep mode.

GPIOGLPEN

Bit 6: IO port G clock enable during Sleep mode.

GPIOHLPEN

Bit 7: IO port H clock enable during Sleep mode.

GPIOILPEN

Bit 8: IO port I clock enable during Sleep mode.

CRCLPEN

Bit 12: CRC clock enable during Sleep mode.

FLITFLPEN

Bit 15: Flash interface clock enable during Sleep mode.

SRAM1LPEN

Bit 16: SRAM 1interface clock enable during Sleep mode.

SRAM2LPEN

Bit 17: SRAM 2 interface clock enable during Sleep mode.

BKPSRAMLPEN

Bit 18: Backup SRAM interface clock enable during Sleep mode.

SRAM3LPEN

Bit 19: SRAM 3 interface clock enable during Sleep mode.

DMA1LPEN

Bit 21: DMA1 clock enable during Sleep mode.

DMA2LPEN

Bit 22: DMA2 clock enable during Sleep mode.

ETHMACLPEN

Bit 25: Ethernet MAC clock enable during Sleep mode.

ETHMACTXLPEN

Bit 26: Ethernet transmission clock enable during Sleep mode.

ETHMACRXLPEN

Bit 27: Ethernet reception clock enable during Sleep mode.

ETHMACPTPLPEN

Bit 28: Ethernet PTP clock enable during Sleep mode.

OTGHSLPEN

Bit 29: USB OTG HS clock enable during Sleep mode.

OTGHSULPILPEN

Bit 30: USB OTG HS ULPI clock enable during Sleep mode.

AHB2LPENR

AHB2 peripheral clock enable in low power mode register

Offset: 0x54, size: 32, reset: 0x000000F1, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OTGFSLPEN
rw 		RNGLPEN
rw 		HASHLPEN
rw 		CRYPLPEN
rw 		DCMILPEN
rw
Toggle fields

DCMILPEN

Bit 0: Camera interface enable during Sleep mode.

CRYPLPEN

Bit 4: Cryptography modules clock enable during Sleep mode.

HASHLPEN

Bit 5: Hash modules clock enable during Sleep mode.

RNGLPEN

Bit 6: Random number generator clock enable during Sleep mode.

OTGFSLPEN

Bit 7: USB OTG FS clock enable during Sleep mode.

AHB3LPENR

AHB3 peripheral clock enable in low power mode register

Offset: 0x58, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMCLPEN
rw
Toggle fields

FMCLPEN

Bit 0: Flexible memory controller module clock enable during Sleep mode.

APB1LPENR

APB1 peripheral clock enable in low power mode register

Offset: 0x60, size: 32, reset: 0x36FEC9FF, access: read-write

0/25 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UART8LPEN
rw 		UART7LPEN
rw 		DACLPEN
rw 		PWRLPEN
rw 		CAN2LPEN
rw 		CAN1LPEN
rw 		I2C3LPEN
rw 		I2C2LPEN
rw 		I2C1LPEN
rw 		UART5LPEN
rw 		UART4LPEN
rw 		USART3LPEN
rw 		USART2LPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3LPEN
rw 		SPI2LPEN
rw 		WWDGLPEN
rw 		TIM14LPEN
rw 		TIM13LPEN
rw 		TIM12LPEN
rw 		TIM7LPEN
rw 		TIM6LPEN
rw 		TIM5LPEN
rw 		TIM4LPEN
rw 		TIM3LPEN
rw 		TIM2LPEN
rw
Toggle fields

TIM2LPEN

Bit 0: TIM2 clock enable during Sleep mode.

TIM3LPEN

Bit 1: TIM3 clock enable during Sleep mode.

TIM4LPEN

Bit 2: TIM4 clock enable during Sleep mode.

TIM5LPEN

Bit 3: TIM5 clock enable during Sleep mode.

TIM6LPEN

Bit 4: TIM6 clock enable during Sleep mode.

TIM7LPEN

Bit 5: TIM7 clock enable during Sleep mode.

TIM12LPEN

Bit 6: TIM12 clock enable during Sleep mode.

TIM13LPEN

Bit 7: TIM13 clock enable during Sleep mode.

TIM14LPEN

Bit 8: TIM14 clock enable during Sleep mode.

WWDGLPEN

Bit 11: Window watchdog clock enable during Sleep mode.

SPI2LPEN

Bit 14: SPI2 clock enable during Sleep mode.

SPI3LPEN

Bit 15: SPI3 clock enable during Sleep mode.

USART2LPEN

Bit 17: USART2 clock enable during Sleep mode.

USART3LPEN

Bit 18: USART3 clock enable during Sleep mode.

UART4LPEN

Bit 19: UART4 clock enable during Sleep mode.

UART5LPEN

Bit 20: UART5 clock enable during Sleep mode.

I2C1LPEN

Bit 21: I2C1 clock enable during Sleep mode.

I2C2LPEN

Bit 22: I2C2 clock enable during Sleep mode.

I2C3LPEN

Bit 23: I2C3 clock enable during Sleep mode.

CAN1LPEN

Bit 25: CAN 1 clock enable during Sleep mode.

CAN2LPEN

Bit 26: CAN 2 clock enable during Sleep mode.

PWRLPEN

Bit 28: Power interface clock enable during Sleep mode.

DACLPEN

Bit 29: DAC interface clock enable during Sleep mode.

UART7LPEN

Bit 30: UART7 clock enable during Sleep mode.

UART8LPEN

Bit 31: UART8 clock enable during Sleep mode.

APB2LPENR

APB2 peripheral clock enabled in low power mode register

Offset: 0x64, size: 32, reset: 0x00075F33, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPI6LPEN
rw 		SPI5LPEN
rw 		TIM11LPEN
rw 		TIM10LPEN
rw 		TIM9LPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYSCFGLPEN
rw 		SPI4LPEN
rw 		SPI1LPEN
rw 		SDIOLPEN
rw 		ADC3LPEN
rw 		ADC2LPEN
rw 		ADC1LPEN
rw 		USART6LPEN
rw 		USART1LPEN
rw 		TIM8LPEN
rw 		TIM1LPEN
rw
Toggle fields

TIM1LPEN

Bit 0: TIM1 clock enable during Sleep mode.

TIM8LPEN

Bit 1: TIM8 clock enable during Sleep mode.

USART1LPEN

Bit 4: USART1 clock enable during Sleep mode.

USART6LPEN

Bit 5: USART6 clock enable during Sleep mode.

ADC1LPEN

Bit 8: ADC1 clock enable during Sleep mode.

ADC2LPEN

Bit 9: ADC2 clock enable during Sleep mode.

ADC3LPEN

Bit 10: ADC 3 clock enable during Sleep mode.

SDIOLPEN

Bit 11: SDIO clock enable during Sleep mode.

SPI1LPEN

Bit 12: SPI 1 clock enable during Sleep mode.

SPI4LPEN

Bit 13: SPI 4 clock enable during Sleep mode.

SYSCFGLPEN

Bit 14: System configuration controller clock enable during Sleep mode.

TIM9LPEN

Bit 16: TIM9 clock enable during sleep mode.

TIM10LPEN

Bit 17: TIM10 clock enable during Sleep mode.

TIM11LPEN

Bit 18: TIM11 clock enable during Sleep mode.

SPI5LPEN

Bit 20: SPI 5 clock enable during Sleep mode.

SPI6LPEN

Bit 21: SPI 6 clock enable during Sleep mode.

BDCR

Backup domain control register

Offset: 0x70, size: 32, reset: 0x00000000, access: Unspecified

1/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BDRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCEN
rw 		RTCSEL1
rw 		RTCSEL0
rw 		LSEBYP
rw 		LSERDY
r 		LSEON
rw
Toggle fields

LSEON

Bit 0: External low-speed oscillator enable.

LSERDY

Bit 1: External low-speed oscillator ready.

LSEBYP

Bit 2: External low-speed oscillator bypass.

RTCSEL0

Bit 8: RTC clock source selection.

RTCSEL1

Bit 9: RTC clock source selection.

RTCEN

Bit 15: RTC clock enable.

BDRST

Bit 16: Backup domain software reset.

CSR

clock control & status register

Offset: 0x74, size: 32, reset: 0x0E000000, access: Unspecified

1/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPWRRSTF
rw 		WWDGRSTF
rw 		WDGRSTF
rw 		SFTRSTF
rw 		PORRSTF
rw 		PADRSTF
rw 		BORRSTF
rw 		RMVF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSIRDY
r 		LSION
rw
Toggle fields

LSION

Bit 0: Internal low-speed oscillator enable.

LSIRDY

Bit 1: Internal low-speed oscillator ready.

RMVF

Bit 24: Remove reset flag.

BORRSTF

Bit 25: BOR reset flag.

PADRSTF

Bit 26: PIN reset flag.

PORRSTF

Bit 27: POR/PDR reset flag.

SFTRSTF

Bit 28: Software reset flag.

WDGRSTF

Bit 29: Independent watchdog reset flag.

WWDGRSTF

Bit 30: Window watchdog reset flag.

LPWRRSTF

Bit 31: Low-power reset flag.

SSCGR

spread spectrum clock generation register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSCGEN
rw 		SPREADSEL
rw 		INCSTEP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INCSTEP
rw 		MODPER
rw
Toggle fields

MODPER

Bits 0-12: Modulation period.

INCSTEP

Bits 13-27: Incrementation step.

SPREADSEL

Bit 30: Spread Select.

SSCGEN

Bit 31: Spread spectrum modulation enable.

PLLI2SCFGR

PLLI2S configuration register

Offset: 0x84, size: 32, reset: 0x20003000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLI2SRx
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLI2SNx
rw
Toggle fields

PLLI2SNx

Bits 6-14: PLLI2S multiplication factor for VCO.

PLLI2SRx

Bits 28-30: PLLI2S division factor for I2S clocks.

RNG

0x50060800: Random number generator

4/8 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SR
0x8 DR
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IE
rw 		RNGEN
rw
Toggle fields

RNGEN

Bit 2: Random number generator enable.

IE

Bit 3: Interrupt enable.

SR

status register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

3/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEIS
rw 		CEIS
rw 		SECS
r 		CECS
r 		DRDY
r
Toggle fields

DRDY

Bit 0: Data ready.

CECS

Bit 1: Clock error current status.

SECS

Bit 2: Seed error current status.

CEIS

Bit 5: Clock error interrupt status.

SEIS

Bit 6: Seed error interrupt status.

DR

data register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RNDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RNDATA
r
Toggle fields

RNDATA

Bits 0-31: Random data.

RTC

0x40002800: Real-time clock

19/139 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 TR
0x4 DR
0x8 CR
0xc ISR
0x10 PRER
0x14 WUTR
0x18 CALIBR
0x1c ALRMAR
0x20 ALRMBR
0x24 WPR
0x28 SSR
0x2c SHIFTR
0x30 TSTR
0x34 TSDR
0x38 TSSSR
0x3c CALR
0x40 TAFCR
0x44 ALRMASSR
0x48 ALRMBSSR
0x50 BKP0R
0x54 BKP1R
0x58 BKP2R
0x5c BKP3R
0x60 BKP4R
0x64 BKP5R
0x68 BKP6R
0x6c BKP7R
0x70 BKP8R
0x74 BKP9R
0x78 BKP10R
0x7c BKP11R
0x80 BKP12R
0x84 BKP13R
0x88 BKP14R
0x8c BKP15R
0x90 BKP16R
0x94 BKP17R
0x98 BKP18R
0x9c BKP19R
Toggle registers

TR

time register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PM
rw 		HT
rw 		HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MNT
rw 		MNU
rw 		ST
rw 		SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

DR

date register

Offset: 0x4, size: 32, reset: 0x00002101, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
YT
rw 		YU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDU
rw 		MT
rw 		MU
rw 		DT
rw 		DU
rw
Toggle fields

DU

Bits 0-3: Date units in BCD format.

DT

Bits 4-5: Date tens in BCD format.

MU

Bits 8-11: Month units in BCD format.

MT

Bit 12: Month tens in BCD format.

WDU

Bits 13-15: Week day units.

YU

Bits 16-19: Year units in BCD format.

YT

Bits 20-23: Year tens in BCD format.

CR

control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COE
rw 		OSEL
rw 		POL
rw 		BKP
rw 		SUB1H
rw 		ADD1H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSIE
rw 		WUTIE
rw 		ALRBIE
rw 		ALRAIE
rw 		TSE
rw 		WUTE
rw 		ALRBE
rw 		ALRAE
rw 		DCE
rw 		FMT
rw 		REFCKON
rw 		TSEDGE
rw 		WCKSEL
rw
Toggle fields

WCKSEL

Bits 0-2: Wakeup clock selection.

TSEDGE

Bit 3: Time-stamp event active edge.

REFCKON

Bit 4: Reference clock detection enable (50 or 60 Hz).

FMT

Bit 6: Hour format.

DCE

Bit 7: Coarse digital calibration enable.

ALRAE

Bit 8: Alarm A enable.

ALRBE

Bit 9: Alarm B enable.

WUTE

Bit 10: Wakeup timer enable.

TSE

Bit 11: Time stamp enable.

ALRAIE

Bit 12: Alarm A interrupt enable.

ALRBIE

Bit 13: Alarm B interrupt enable.

WUTIE

Bit 14: Wakeup timer interrupt enable.

TSIE

Bit 15: Time-stamp interrupt enable.

ADD1H

Bit 16: Add 1 hour (summer time change).

SUB1H

Bit 17: Subtract 1 hour (winter time change).

BKP

Bit 18: Backup.

POL

Bit 20: Output polarity.

OSEL

Bits 21-22: Output selection.

COE

Bit 23: Calibration output enable.

ISR

initialization and status register

Offset: 0xc, size: 32, reset: 0x00000007, access: Unspecified

6/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RECALPF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP2F
rw 		TAMP1F
rw 		TSOVF
rw 		TSF
rw 		WUTF
rw 		ALRBF
rw 		ALRAF
rw 		INIT
rw 		INITF
r 		RSF
rw 		INITS
r 		SHPF
rw 		WUTWF
r 		ALRBWF
r 		ALRAWF
r
Toggle fields

ALRAWF

Bit 0: Alarm A write flag.

ALRBWF

Bit 1: Alarm B write flag.

WUTWF

Bit 2: Wakeup timer write flag.

SHPF

Bit 3: Shift operation pending.

INITS

Bit 4: Initialization status flag.

RSF

Bit 5: Registers synchronization flag.

INITF

Bit 6: Initialization flag.

INIT

Bit 7: Initialization mode.

ALRAF

Bit 8: Alarm A flag.

ALRBF

Bit 9: Alarm B flag.

WUTF

Bit 10: Wakeup timer flag.

TSF

Bit 11: Time-stamp flag.

TSOVF

Bit 12: Time-stamp overflow flag.

TAMP1F

Bit 13: Tamper detection flag.

TAMP2F

Bit 14: TAMPER2 detection flag.

RECALPF

Bit 16: Recalibration pending Flag.

PRER

prescaler register

Offset: 0x10, size: 32, reset: 0x007F00FF, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PREDIV_A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PREDIV_S
rw
Toggle fields

PREDIV_S

Bits 0-14: Synchronous prescaler factor.

PREDIV_A

Bits 16-22: Asynchronous prescaler factor.

WUTR

wakeup timer register

Offset: 0x14, size: 32, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WUT
rw
Toggle fields

WUT

Bits 0-15: Wakeup auto-reload value bits.

CALIBR

calibration register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCS
rw 		DC
rw
Toggle fields

DC

Bits 0-4: Digital calibration.

DCS

Bit 7: Digital calibration sign.

ALRMAR

alarm A register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSK4
rw 		WDSEL
rw 		DT
rw 		DU
rw 		MSK3
rw 		PM
rw 		HT
rw 		HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSK2
rw 		MNT
rw 		MNU
rw 		MSK1
rw 		ST
rw 		SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MSK1

Bit 7: Alarm A seconds mask.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

MSK2

Bit 15: Alarm A minutes mask.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

MSK3

Bit 23: Alarm A hours mask.

DU

Bits 24-27: Date units or day in BCD format.

DT

Bits 28-29: Date tens in BCD format.

WDSEL

Bit 30: Week day selection.

MSK4

Bit 31: Alarm A date mask.

ALRMBR

alarm B register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSK4
rw 		WDSEL
rw 		DT
rw 		DU
rw 		MSK3
rw 		PM
rw 		HT
rw 		HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSK2
rw 		MNT
rw 		MNU
rw 		MSK1
rw 		ST
rw 		SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MSK1

Bit 7: Alarm B seconds mask.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

MSK2

Bit 15: Alarm B minutes mask.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

MSK3

Bit 23: Alarm B hours mask.

DU

Bits 24-27: Date units or day in BCD format.

DT

Bits 28-29: Date tens in BCD format.

WDSEL

Bit 30: Week day selection.

MSK4

Bit 31: Alarm B date mask.

WPR

write protection register

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-7: Write protection key.

SSR

sub second register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
r
Toggle fields

SS

Bits 0-15: Sub second value.

SHIFTR

shift control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD1S
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUBFS
w
Toggle fields

SUBFS

Bits 0-14: Subtract a fraction of a second.

ADD1S

Bit 31: Add one second.

TSTR

time stamp time register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALARMOUTTYPE
r 		TSINSEL
r 		TAMP1INSEL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMPIE
r 		TAMP1TRG
r 		TAMP1E
r
Toggle fields

TAMP1E

Bit 0: Tamper 1 detection enable.

TAMP1TRG

Bit 1: Active level for tamper 1.

TAMPIE

Bit 2: Tamper interrupt enable.

TAMP1INSEL

Bit 16: TAMPER1 mapping.

TSINSEL

Bit 17: TIMESTAMP mapping.

ALARMOUTTYPE

Bit 18: AFO_ALARM output type.

TSDR

time stamp date register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDU
r 		MT
r 		MU
r 		DT
r 		DU
r
Toggle fields

DU

Bits 0-3: Date units in BCD format.

DT

Bits 4-5: Date tens in BCD format.

MU

Bits 8-11: Month units in BCD format.

MT

Bit 12: Month tens in BCD format.

WDU

Bits 13-15: Week day units.

TSSSR

timestamp sub second register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
r
Toggle fields

SS

Bits 0-15: Sub second value.

CALR

calibration register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALP
rw 		CALW8
rw 		CALW16
rw 		CALM
rw
Toggle fields

CALM

Bits 0-8: Calibration minus.

CALW16

Bit 13: Use a 16-second calibration cycle period.

CALW8

Bit 14: Use an 8-second calibration cycle period.

CALP

Bit 15: Increase frequency of RTC by 488.5 ppm.

TAFCR

tamper and alternate function configuration register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALARMOUTTYPE
rw 		TSINSEL
rw 		TAMP1INSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMPPUDIS
rw 		TAMPPRCH
rw 		TAMPFLT
rw 		TAMPFREQ
rw 		TAMPTS
rw 		TAMP2TRG
rw 		TAMP2E
rw 		TAMPIE
rw 		TAMP1TRG
rw 		TAMP1E
rw
Toggle fields

TAMP1E

Bit 0: Tamper 1 detection enable.

TAMP1TRG

Bit 1: Active level for tamper 1.

TAMPIE

Bit 2: Tamper interrupt enable.

TAMP2E

Bit 3: Tamper 2 detection enable.

TAMP2TRG

Bit 4: Active level for tamper 2.

TAMPTS

Bit 7: Activate timestamp on tamper detection event.

TAMPFREQ

Bits 8-10: Tamper sampling frequency.

TAMPFLT

Bits 11-12: Tamper filter count.

TAMPPRCH

Bits 13-14: Tamper precharge duration.

TAMPPUDIS

Bit 15: TAMPER pull-up disable.

TAMP1INSEL

Bit 16: TAMPER1 mapping.

TSINSEL

Bit 17: TIMESTAMP mapping.

ALARMOUTTYPE

Bit 18: AFO_ALARM output type.

ALRMASSR

alarm A sub second register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASKSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
rw
Toggle fields

SS

Bits 0-14: Sub seconds value.

MASKSS

Bits 24-27: Mask the most-significant bits starting at this bit.

ALRMBSSR

alarm B sub second register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASKSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
rw
Toggle fields

SS

Bits 0-14: Sub seconds value.

MASKSS

Bits 24-27: Mask the most-significant bits starting at this bit.

BKP0R

backup register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP1R

backup register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP2R

backup register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP3R

backup register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP4R

backup register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP5R

backup register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP6R

backup register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP7R

backup register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP8R

backup register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP9R

backup register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP10R

backup register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP11R

backup register

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP12R

backup register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP13R

backup register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP14R

backup register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP15R

backup register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP16R

backup register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP17R

backup register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP18R

backup register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP19R

backup register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

SAI

0x40015800: Serial audio interface

8/102 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x4 ACR1
0x8 ACR2
0xc AFRCR
0x10 ASLOTR
0x14 AIM
0x18 ASR
0x1c ACLRFR
0x20 ADR
0x24 BCR1
0x28 BCR2
0x2c BFRCR
0x30 BSLOTR
0x34 BIM
0x38 BSR
0x3c BCLRFR
0x40 BDR
Toggle registers

ACR1

AConfiguration register 1

Offset: 0x4, size: 32, reset: 0x00000040, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCJDIV
rw 		NODIV
rw 		DMAEN
rw 		SAIAEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OutDri
rw 		MONO
rw 		SYNCEN
rw 		CKSTR
rw 		LSBFIRST
rw 		DS
rw 		PRTCFG
rw 		MODE
rw
Toggle fields

MODE

Bits 0-1: Audio block mode.

PRTCFG

Bits 2-3: Protocol configuration.

DS

Bits 5-7: Data size.

LSBFIRST

Bit 8: Least significant bit first.

CKSTR

Bit 9: Clock strobing edge.

SYNCEN

Bits 10-11: Synchronization enable.

MONO

Bit 12: Mono mode.

OutDri

Bit 13: Output drive.

SAIAEN

Bit 16: Audio block A enable.

DMAEN

Bit 17: DMA enable.

NODIV

Bit 19: No divider.

MCJDIV

Bits 20-23: Master clock divider.

ACR2

AConfiguration register 2

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP
rw 		CPL
rw 		MUTECN
rw 		MUTEVAL
rw 		MUTE
rw 		TRIS
rw 		FFLUS
rw 		FTH
rw
Toggle fields

FTH

Bits 0-2: FIFO threshold.

FFLUS

Bit 3: FIFO flush.

TRIS

Bit 4: Tristate management on data line.

MUTE

Bit 5: Mute.

MUTEVAL

Bit 6: Mute value.

MUTECN

Bits 7-12: Mute counter.

CPL

Bit 13: Complement bit.

COMP

Bits 14-15: Companding mode.

AFRCR

AFRCR

Offset: 0xc, size: 32, reset: 0x00000007, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSOFF
rw 		FSPOL
rw 		FSDEF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSALL
rw 		FRL
rw
Toggle fields

FRL

Bits 0-7: Frame length.

FSALL

Bits 8-14: Frame synchronization active level length.

FSDEF

Bit 16: Frame synchronization definition.

FSPOL

Bit 17: Frame synchronization polarity.

FSOFF

Bit 18: Frame synchronization offset.

ASLOTR

ASlot register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLOTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBSLOT
rw 		SLOTSZ
rw 		FBOFF
rw
Toggle fields

FBOFF

Bits 0-4: First bit offset.

SLOTSZ

Bits 6-7: Slot size.

NBSLOT

Bits 8-11: Number of slots in an audio frame.

SLOTEN

Bits 16-31: Slot enable.

AIM

AInterrupt mask register2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDET
rw 		AFSDETIE
rw 		CNRDYIE
rw 		FREQIE
rw 		WCKCFG
rw 		MUTEDET
rw 		OVRUDRIE
rw
Toggle fields

OVRUDRIE

Bit 0: Overrun/underrun interrupt enable.

MUTEDET

Bit 1: Mute detection interrupt enable.

WCKCFG

Bit 2: Wrong clock configuration interrupt enable.

FREQIE

Bit 3: FIFO request interrupt enable.

CNRDYIE

Bit 4: Codec not ready interrupt enable.

AFSDETIE

Bit 5: Anticipated frame synchronization detection interrupt enable.

LFSDET

Bit 6: Late frame synchronization detection interrupt enable.

ASR

AStatus register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLVL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDET
rw 		AFSDET
rw 		CNRDY
rw 		FREQ
rw 		WCKCFG
rw 		MUTEDET
rw 		OVRUDR
rw
Toggle fields

OVRUDR

Bit 0: Overrun / underrun.

MUTEDET

Bit 1: Mute detection.

WCKCFG

Bit 2: Wrong clock configuration flag. This bit is read only..

FREQ

Bit 3: FIFO request.

CNRDY

Bit 4: Codec not ready.

AFSDET

Bit 5: Anticipated frame synchronization detection.

LFSDET

Bit 6: Late frame synchronization detection.

FLVL

Bits 16-18: FIFO level threshold.

ACLRFR

AClear flag register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDET
rw 		CAFSDET
rw 		CNRDY
rw 		WCKCFG
rw 		MUTEDET
rw 		OVRUDR
rw
Toggle fields

OVRUDR

Bit 0: Clear overrun / underrun.

MUTEDET

Bit 1: Mute detection flag.

WCKCFG

Bit 2: Clear wrong clock configuration flag.

CNRDY

Bit 4: Clear codec not ready flag.

CAFSDET

Bit 5: Clear anticipated frame synchronization detection flag..

LFSDET

Bit 6: Clear late frame synchronization detection flag.

ADR

AData register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: Data.

BCR1

BConfiguration register 1

Offset: 0x24, size: 32, reset: 0x00000040, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCJDIV
rw 		NODIV
rw 		DMAEN
rw 		SAIBEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OutDri
rw 		MONO
rw 		SYNCEN
rw 		CKSTR
rw 		LSBFIRST
rw 		DS
rw 		PRTCFG
rw 		MODE
rw
Toggle fields

MODE

Bits 0-1: Audio block mode.

PRTCFG

Bits 2-3: Protocol configuration.

DS

Bits 5-7: Data size.

LSBFIRST

Bit 8: Least significant bit first.

CKSTR

Bit 9: Clock strobing edge.

SYNCEN

Bits 10-11: Synchronization enable.

MONO

Bit 12: Mono mode.

OutDri

Bit 13: Output drive.

SAIBEN

Bit 16: Audio block B enable.

DMAEN

Bit 17: DMA enable.

NODIV

Bit 19: No divider.

MCJDIV

Bits 20-23: Master clock divider.

BCR2

BConfiguration register 2

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP
rw 		CPL
rw 		MUTECN
rw 		MUTEVAL
rw 		MUTE
rw 		TRIS
rw 		FFLUS
rw 		FTH
rw
Toggle fields

FTH

Bits 0-2: FIFO threshold.

FFLUS

Bit 3: FIFO flush.

TRIS

Bit 4: Tristate management on data line.

MUTE

Bit 5: Mute.

MUTEVAL

Bit 6: Mute value.

MUTECN

Bits 7-12: Mute counter.

CPL

Bit 13: Complement bit.

COMP

Bits 14-15: Companding mode.

BFRCR

BFRCR

Offset: 0x2c, size: 32, reset: 0x00000007, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSOFF
rw 		FSPOL
rw 		FSDEF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSALL
rw 		FRL
rw
Toggle fields

FRL

Bits 0-7: Frame length.

FSALL

Bits 8-14: Frame synchronization active level length.

FSDEF

Bit 16: Frame synchronization definition.

FSPOL

Bit 17: Frame synchronization polarity.

FSOFF

Bit 18: Frame synchronization offset.

BSLOTR

BSlot register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLOTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBSLOT
rw 		SLOTSZ
rw 		FBOFF
rw
Toggle fields

FBOFF

Bits 0-4: First bit offset.

SLOTSZ

Bits 6-7: Slot size.

NBSLOT

Bits 8-11: Number of slots in an audio frame.

SLOTEN

Bits 16-31: Slot enable.

BIM

BInterrupt mask register2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDETIE
rw 		AFSDETIE
rw 		CNRDYIE
rw 		FREQIE
rw 		WCKCFG
rw 		MUTEDET
rw 		OVRUDRIE
rw
Toggle fields

OVRUDRIE

Bit 0: Overrun/underrun interrupt enable.

MUTEDET

Bit 1: Mute detection interrupt enable.

WCKCFG

Bit 2: Wrong clock configuration interrupt enable.

FREQIE

Bit 3: FIFO request interrupt enable.

CNRDYIE

Bit 4: Codec not ready interrupt enable.

AFSDETIE

Bit 5: Anticipated frame synchronization detection interrupt enable.

LFSDETIE

Bit 6: Late frame synchronization detection interrupt enable.

BSR

BStatus register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLVL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDET
r 		AFSDET
r 		CNRDY
r 		FREQ
r 		WCKCFG
r 		MUTEDET
r 		OVRUDR
r
Toggle fields

OVRUDR

Bit 0: Overrun / underrun.

MUTEDET

Bit 1: Mute detection.

WCKCFG

Bit 2: Wrong clock configuration flag.

FREQ

Bit 3: FIFO request.

CNRDY

Bit 4: Codec not ready.

AFSDET

Bit 5: Anticipated frame synchronization detection.

LFSDET

Bit 6: Late frame synchronization detection.

FLVL

Bits 16-18: FIFO level threshold.

BCLRFR

BClear flag register

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDET
w 		CAFSDET
w 		CNRDY
w 		WCKCFG
w 		MUTEDET
w 		OVRUDR
w
Toggle fields

OVRUDR

Bit 0: Clear overrun / underrun.

MUTEDET

Bit 1: Mute detection flag.

WCKCFG

Bit 2: Clear wrong clock configuration flag.

CNRDY

Bit 4: Clear codec not ready flag.

CAFSDET

Bit 5: Clear anticipated frame synchronization detection flag.

LFSDET

Bit 6: Clear late frame synchronization detection flag.

BDR

BData register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: Data.

SDIO

0x40012c00: Secure digital input/output interface

31/98 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 POWER
0x4 CLKCR
0x8 ARG
0xc CMD
0x10 RESPCMD
0x14 RESP1
0x18 RESP2
0x1c RESP3
0x20 RESP4
0x24 DTIMER
0x28 DLEN
0x2c DCTRL
0x30 DCOUNT
0x34 STA
0x38 ICR
0x3c MASK
0x48 FIFOCNT
0x80 FIFO
Toggle registers

POWER

power control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWRCTRL
rw
Toggle fields

PWRCTRL

Bits 0-1: PWRCTRL.

CLKCR

SDI clock control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HWFC_EN
rw 		NEGEDGE
rw 		WIDBUS
rw 		BYPASS
rw 		PWRSAV
rw 		CLKEN
rw 		CLKDIV
rw
Toggle fields

CLKDIV

Bits 0-7: Clock divide factor.

CLKEN

Bit 8: Clock enable bit.

PWRSAV

Bit 9: Power saving configuration bit.

BYPASS

Bit 10: Clock divider bypass enable bit.

WIDBUS

Bits 11-12: Wide bus mode enable bit.

NEGEDGE

Bit 13: SDIO_CK dephasing selection bit.

HWFC_EN

Bit 14: HW Flow Control enable.

ARG

argument register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CMDARG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMDARG
rw
Toggle fields

CMDARG

Bits 0-31: Command argument.

CMD

command register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CE_ATACMD
rw 		nIEN
rw 		ENCMDcompl
rw 		SDIOSuspend
rw 		CPSMEN
rw 		WAITPEND
rw 		WAITINT
rw 		WAITRESP
rw 		CMDINDEX
rw
Toggle fields

CMDINDEX

Bits 0-5: Command index.

WAITRESP

Bits 6-7: Wait for response bits.

WAITINT

Bit 8: CPSM waits for interrupt request.

WAITPEND

Bit 9: CPSM Waits for ends of data transfer (CmdPend internal signal)..

CPSMEN

Bit 10: Command path state machine (CPSM) Enable bit.

SDIOSuspend

Bit 11: SD I/O suspend command.

ENCMDcompl

Bit 12: Enable CMD completion.

nIEN

Bit 13: not Interrupt Enable.

CE_ATACMD

Bit 14: CE-ATA command.

RESPCMD

command response register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESPCMD
r
Toggle fields

RESPCMD

Bits 0-5: Response command index.

RESP1

response 1..4 register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS1
r
Toggle fields

CARDSTATUS1

Bits 0-31: see Table 132..

RESP2

response 1..4 register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS2
r
Toggle fields

CARDSTATUS2

Bits 0-31: see Table 132..

RESP3

response 1..4 register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS3
r
Toggle fields

CARDSTATUS3

Bits 0-31: see Table 132..

RESP4

response 1..4 register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS4
r
Toggle fields

CARDSTATUS4

Bits 0-31: see Table 132..

DTIMER

data timer register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATATIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATATIME
rw
Toggle fields

DATATIME

Bits 0-31: Data timeout period.

DLEN

data length register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATALENGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATALENGTH
rw
Toggle fields

DATALENGTH

Bits 0-24: Data length value.

DCTRL

data control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDIOEN
rw 		RWMOD
rw 		RWSTOP
rw 		RWSTART
rw 		DBLOCKSIZE
rw 		DMAEN
rw 		DTMODE
rw 		DTDIR
rw 		DTEN
rw
Toggle fields

DTEN

Bit 0: DTEN.

DTDIR

Bit 1: Data transfer direction selection.

DTMODE

Bit 2: Data transfer mode selection 1: Stream or SDIO multibyte data transfer..

DMAEN

Bit 3: DMA enable bit.

DBLOCKSIZE

Bits 4-7: Data block size.

RWSTART

Bit 8: Read wait start.

RWSTOP

Bit 9: Read wait stop.

RWMOD

Bit 10: Read wait mode.

SDIOEN

Bit 11: SD I/O enable functions.

DCOUNT

data counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATACOUNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATACOUNT
r
Toggle fields

DATACOUNT

Bits 0-24: Data count value.

STA

status register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEATAEND
r 		SDIOIT
r 		RXDAVL
r 		TXDAVL
r 		RXFIFOE
r 		TXFIFOE
r 		RXFIFOF
r 		TXFIFOF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXFIFOHF
r 		TXFIFOHE
r 		RXACT
r 		TXACT
r 		CMDACT
r 		DBCKEND
r 		STBITERR
r 		DATAEND
r 		CMDSENT
r 		CMDREND
r 		RXOVERR
r 		TXUNDERR
r 		DTIMEOUT
r 		CTIMEOUT
r 		DCRCFAIL
r 		CCRCFAIL
r
Toggle fields

CCRCFAIL

Bit 0: Command response received (CRC check failed).

DCRCFAIL

Bit 1: Data block sent/received (CRC check failed).

CTIMEOUT

Bit 2: Command response timeout.

DTIMEOUT

Bit 3: Data timeout.

TXUNDERR

Bit 4: Transmit FIFO underrun error.

RXOVERR

Bit 5: Received FIFO overrun error.

CMDREND

Bit 6: Command response received (CRC check passed).

CMDSENT

Bit 7: Command sent (no response required).

DATAEND

Bit 8: Data end (data counter, SDIDCOUNT, is zero).

STBITERR

Bit 9: Start bit not detected on all data signals in wide bus mode.

DBCKEND

Bit 10: Data block sent/received (CRC check passed).

CMDACT

Bit 11: Command transfer in progress.

TXACT

Bit 12: Data transmit in progress.

RXACT

Bit 13: Data receive in progress.

TXFIFOHE

Bit 14: Transmit FIFO half empty: at least 8 words can be written into the FIFO.

RXFIFOHF

Bit 15: Receive FIFO half full: there are at least 8 words in the FIFO.

TXFIFOF

Bit 16: Transmit FIFO full.

RXFIFOF

Bit 17: Receive FIFO full.

TXFIFOE

Bit 18: Transmit FIFO empty.

RXFIFOE

Bit 19: Receive FIFO empty.

TXDAVL

Bit 20: Data available in transmit FIFO.

RXDAVL

Bit 21: Data available in receive FIFO.

SDIOIT

Bit 22: SDIO interrupt received.

CEATAEND

Bit 23: CE-ATA command completion signal received for CMD61.

ICR

interrupt clear register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEATAENDC
rw 		SDIOITC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBCKENDC
rw 		STBITERRC
rw 		DATAENDC
rw 		CMDSENTC
rw 		CMDRENDC
rw 		RXOVERRC
rw 		TXUNDERRC
rw 		DTIMEOUTC
rw 		CTIMEOUTC
rw 		DCRCFAILC
rw 		CCRCFAILC
rw
Toggle fields

CCRCFAILC

Bit 0: CCRCFAIL flag clear bit.

DCRCFAILC

Bit 1: DCRCFAIL flag clear bit.

CTIMEOUTC

Bit 2: CTIMEOUT flag clear bit.

DTIMEOUTC

Bit 3: DTIMEOUT flag clear bit.

TXUNDERRC

Bit 4: TXUNDERR flag clear bit.

RXOVERRC

Bit 5: RXOVERR flag clear bit.

CMDRENDC

Bit 6: CMDREND flag clear bit.

CMDSENTC

Bit 7: CMDSENT flag clear bit.

DATAENDC

Bit 8: DATAEND flag clear bit.

STBITERRC

Bit 9: STBITERR flag clear bit.

DBCKENDC

Bit 10: DBCKEND flag clear bit.

SDIOITC

Bit 22: SDIOIT flag clear bit.

CEATAENDC

Bit 23: CEATAEND flag clear bit.

MASK

mask register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEATAENDIE
rw 		SDIOITIE
rw 		RXDAVLIE
rw 		TXDAVLIE
rw 		RXFIFOEIE
rw 		TXFIFOEIE
rw 		RXFIFOFIE
rw 		TXFIFOFIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXFIFOHFIE
rw 		TXFIFOHEIE
rw 		RXACTIE
rw 		TXACTIE
rw 		CMDACTIE
rw 		DBCKENDIE
rw 		STBITERRIE
rw 		DATAENDIE
rw 		CMDSENTIE
rw 		CMDRENDIE
rw 		RXOVERRIE
rw 		TXUNDERRIE
rw 		DTIMEOUTIE
rw 		CTIMEOUTIE
rw 		DCRCFAILIE
rw 		CCRCFAILIE
rw
Toggle fields

CCRCFAILIE

Bit 0: Command CRC fail interrupt enable.

DCRCFAILIE

Bit 1: Data CRC fail interrupt enable.

CTIMEOUTIE

Bit 2: Command timeout interrupt enable.

DTIMEOUTIE

Bit 3: Data timeout interrupt enable.

TXUNDERRIE

Bit 4: Tx FIFO underrun error interrupt enable.

RXOVERRIE

Bit 5: Rx FIFO overrun error interrupt enable.

CMDRENDIE

Bit 6: Command response received interrupt enable.

CMDSENTIE

Bit 7: Command sent interrupt enable.

DATAENDIE

Bit 8: Data end interrupt enable.

STBITERRIE

Bit 9: Start bit error interrupt enable.

DBCKENDIE

Bit 10: Data block end interrupt enable.

CMDACTIE

Bit 11: Command acting interrupt enable.

TXACTIE

Bit 12: Data transmit acting interrupt enable.

RXACTIE

Bit 13: Data receive acting interrupt enable.

TXFIFOHEIE

Bit 14: Tx FIFO half empty interrupt enable.

RXFIFOHFIE

Bit 15: Rx FIFO half full interrupt enable.

TXFIFOFIE

Bit 16: Tx FIFO full interrupt enable.

RXFIFOFIE

Bit 17: Rx FIFO full interrupt enable.

TXFIFOEIE

Bit 18: Tx FIFO empty interrupt enable.

RXFIFOEIE

Bit 19: Rx FIFO empty interrupt enable.

TXDAVLIE

Bit 20: Data available in Tx FIFO interrupt enable.

RXDAVLIE

Bit 21: Data available in Rx FIFO interrupt enable.

SDIOITIE

Bit 22: SDIO mode interrupt received interrupt enable.

CEATAENDIE

Bit 23: CE-ATA command completion signal received interrupt enable.

FIFOCNT

FIFO counter register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFOCOUNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCOUNT
r
Toggle fields

FIFOCOUNT

Bits 0-23: Remaining number of words to be written to or read from the FIFO..

FIFO

data FIFO register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFOData
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOData
rw
Toggle fields

FIFOData

Bits 0-31: Receive and transmit FIFO data.

SPI1

0x40013000: Serial peripheral interface

10/45 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SR
0xc DR
0x10 CRCPR
0x14 RXCRCR
0x18 TXCRCR
0x1c I2SCFGR
0x20 I2SPR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw 		BIDIOE
rw 		CRCEN
rw 		CRCNEXT
rw 		DFF
rw 		RXONLY
rw 		SSM
rw 		SSI
rw 		LSBFIRST
rw 		SPE
rw 		BR
rw 		MSTR
rw 		CPOL
rw 		CPHA
rw
Toggle fields

CPHA

Bit 0: Clock phase.

CPOL

Bit 1: Clock polarity.

MSTR

Bit 2: Master selection.

BR

Bits 3-5: Baud rate control.

SPE

Bit 6: SPI enable.

LSBFIRST

Bit 7: Frame format.

SSI

Bit 8: Internal slave select.

SSM

Bit 9: Software slave management.

RXONLY

Bit 10: Receive only.

DFF

Bit 11: Data frame format.

CRCNEXT

Bit 12: CRC transfer next.

CRCEN

Bit 13: Hardware CRC calculation enable.

BIDIOE

Bit 14: Output enable in bidirectional mode.

BIDIMODE

Bit 15: Bidirectional data mode enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXEIE
rw 		RXNEIE
rw 		ERRIE
rw 		FRF
rw 		SSOE
rw 		TXDMAEN
rw 		RXDMAEN
rw
Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

TXDMAEN

Bit 1: Tx buffer DMA enable.

SSOE

Bit 2: SS output enable.

FRF

Bit 4: Frame format.

ERRIE

Bit 5: Error interrupt enable.

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

TXEIE

Bit 7: Tx buffer empty interrupt enable.

SR

status register

Offset: 0x8, size: 32, reset: 0x00000002, access: Unspecified

8/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIFRFE
r 		BSY
r 		OVR
r 		MODF
r 		CRCERR
rw 		UDR
r 		CHSIDE
r 		TXE
r 		RXNE
r
Toggle fields

RXNE

Bit 0: Receive buffer not empty.

TXE

Bit 1: Transmit buffer empty.

CHSIDE

Bit 2: Channel side.

UDR

Bit 3: Underrun flag.

CRCERR

Bit 4: CRC error flag.

MODF

Bit 5: Mode fault.

OVR

Bit 6: Overrun flag.

BSY

Bit 7: Busy flag.

TIFRFE

Bit 8: TI frame format error.

DR

data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-15: Data register.

CRCPR

CRC polynomial register

Offset: 0x10, size: 32, reset: 0x00000007, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

RXCRCR

RX CRC register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

TXCRCR

TX CRC register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

I2SCFGR

I2S configuration register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SMOD
rw 		I2SE
rw 		I2SCFG
rw 		PCMSYNC
rw 		I2SSTD
rw 		CKPOL
rw 		DATLEN
rw 		CHLEN
rw
Toggle fields

CHLEN

Bit 0: Channel length (number of bits per audio channel).

DATLEN

Bits 1-2: Data length to be transferred.

CKPOL

Bit 3: Steady state clock polarity.

I2SSTD

Bits 4-5: I2S standard selection.

PCMSYNC

Bit 7: PCM frame synchronization.

I2SCFG

Bits 8-9: I2S configuration mode.

I2SE

Bit 10: I2S Enable.

I2SMOD

Bit 11: I2S mode selection.

I2SPR

I2S prescaler register

Offset: 0x20, size: 32, reset: 0x0000000A, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOE
rw 		ODD
rw 		I2SDIV
rw
Toggle fields

I2SDIV

Bits 0-7: I2S Linear prescaler.

ODD

Bit 8: Odd factor for the prescaler.

MCKOE

Bit 9: Master clock output enable.

SPI2

0x40003800: Serial peripheral interface

10/45 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SR
0xc DR
0x10 CRCPR
0x14 RXCRCR
0x18 TXCRCR
0x1c I2SCFGR
0x20 I2SPR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw 		BIDIOE
rw 		CRCEN
rw 		CRCNEXT
rw 		DFF
rw 		RXONLY
rw 		SSM
rw 		SSI
rw 		LSBFIRST
rw 		SPE
rw 		BR
rw 		MSTR
rw 		CPOL
rw 		CPHA
rw
Toggle fields

CPHA

Bit 0: Clock phase.

CPOL

Bit 1: Clock polarity.

MSTR

Bit 2: Master selection.

BR

Bits 3-5: Baud rate control.

SPE

Bit 6: SPI enable.

LSBFIRST

Bit 7: Frame format.

SSI

Bit 8: Internal slave select.

SSM

Bit 9: Software slave management.

RXONLY

Bit 10: Receive only.

DFF

Bit 11: Data frame format.

CRCNEXT

Bit 12: CRC transfer next.

CRCEN

Bit 13: Hardware CRC calculation enable.

BIDIOE

Bit 14: Output enable in bidirectional mode.

BIDIMODE

Bit 15: Bidirectional data mode enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXEIE
rw 		RXNEIE
rw 		ERRIE
rw 		FRF
rw 		SSOE
rw 		TXDMAEN
rw 		RXDMAEN
rw
Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

TXDMAEN

Bit 1: Tx buffer DMA enable.

SSOE

Bit 2: SS output enable.

FRF

Bit 4: Frame format.

ERRIE

Bit 5: Error interrupt enable.

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

TXEIE

Bit 7: Tx buffer empty interrupt enable.

SR

status register

Offset: 0x8, size: 32, reset: 0x00000002, access: Unspecified

8/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIFRFE
r 		BSY
r 		OVR
r 		MODF
r 		CRCERR
rw 		UDR
r 		CHSIDE
r 		TXE
r 		RXNE
r
Toggle fields

RXNE

Bit 0: Receive buffer not empty.

TXE

Bit 1: Transmit buffer empty.

CHSIDE

Bit 2: Channel side.

UDR

Bit 3: Underrun flag.

CRCERR

Bit 4: CRC error flag.

MODF

Bit 5: Mode fault.

OVR

Bit 6: Overrun flag.

BSY

Bit 7: Busy flag.

TIFRFE

Bit 8: TI frame format error.

DR

data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-15: Data register.

CRCPR

CRC polynomial register

Offset: 0x10, size: 32, reset: 0x00000007, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

RXCRCR

RX CRC register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

TXCRCR

TX CRC register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

I2SCFGR

I2S configuration register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SMOD
rw 		I2SE
rw 		I2SCFG
rw 		PCMSYNC
rw 		I2SSTD
rw 		CKPOL
rw 		DATLEN
rw 		CHLEN
rw
Toggle fields

CHLEN

Bit 0: Channel length (number of bits per audio channel).

DATLEN

Bits 1-2: Data length to be transferred.

CKPOL

Bit 3: Steady state clock polarity.

I2SSTD

Bits 4-5: I2S standard selection.

PCMSYNC

Bit 7: PCM frame synchronization.

I2SCFG

Bits 8-9: I2S configuration mode.

I2SE

Bit 10: I2S Enable.

I2SMOD

Bit 11: I2S mode selection.

I2SPR

I2S prescaler register

Offset: 0x20, size: 32, reset: 0x0000000A, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOE
rw 		ODD
rw 		I2SDIV
rw
Toggle fields

I2SDIV

Bits 0-7: I2S Linear prescaler.

ODD

Bit 8: Odd factor for the prescaler.

MCKOE

Bit 9: Master clock output enable.

SPI3

0x40003c00: Serial peripheral interface

10/45 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SR
0xc DR
0x10 CRCPR
0x14 RXCRCR
0x18 TXCRCR
0x1c I2SCFGR
0x20 I2SPR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw 		BIDIOE
rw 		CRCEN
rw 		CRCNEXT
rw 		DFF
rw 		RXONLY
rw 		SSM
rw 		SSI
rw 		LSBFIRST
rw 		SPE
rw 		BR
rw 		MSTR
rw 		CPOL
rw 		CPHA
rw
Toggle fields

CPHA

Bit 0: Clock phase.

CPOL

Bit 1: Clock polarity.

MSTR

Bit 2: Master selection.

BR

Bits 3-5: Baud rate control.

SPE

Bit 6: SPI enable.

LSBFIRST

Bit 7: Frame format.

SSI

Bit 8: Internal slave select.

SSM

Bit 9: Software slave management.

RXONLY

Bit 10: Receive only.

DFF

Bit 11: Data frame format.

CRCNEXT

Bit 12: CRC transfer next.

CRCEN

Bit 13: Hardware CRC calculation enable.

BIDIOE

Bit 14: Output enable in bidirectional mode.

BIDIMODE

Bit 15: Bidirectional data mode enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXEIE
rw 		RXNEIE
rw 		ERRIE
rw 		FRF
rw 		SSOE
rw 		TXDMAEN
rw 		RXDMAEN
rw
Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

TXDMAEN

Bit 1: Tx buffer DMA enable.

SSOE

Bit 2: SS output enable.

FRF

Bit 4: Frame format.

ERRIE

Bit 5: Error interrupt enable.

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

TXEIE

Bit 7: Tx buffer empty interrupt enable.

SR

status register

Offset: 0x8, size: 32, reset: 0x00000002, access: Unspecified

8/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIFRFE
r 		BSY
r 		OVR
r 		MODF
r 		CRCERR
rw 		UDR
r 		CHSIDE
r 		TXE
r 		RXNE
r
Toggle fields

RXNE

Bit 0: Receive buffer not empty.

TXE

Bit 1: Transmit buffer empty.

CHSIDE

Bit 2: Channel side.

UDR

Bit 3: Underrun flag.

CRCERR

Bit 4: CRC error flag.

MODF

Bit 5: Mode fault.

OVR

Bit 6: Overrun flag.

BSY

Bit 7: Busy flag.

TIFRFE

Bit 8: TI frame format error.

DR

data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-15: Data register.

CRCPR

CRC polynomial register

Offset: 0x10, size: 32, reset: 0x00000007, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

RXCRCR

RX CRC register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

TXCRCR

TX CRC register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

I2SCFGR

I2S configuration register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SMOD
rw 		I2SE
rw 		I2SCFG
rw 		PCMSYNC
rw 		I2SSTD
rw 		CKPOL
rw 		DATLEN
rw 		CHLEN
rw
Toggle fields

CHLEN

Bit 0: Channel length (number of bits per audio channel).

DATLEN

Bits 1-2: Data length to be transferred.

CKPOL

Bit 3: Steady state clock polarity.

I2SSTD

Bits 4-5: I2S standard selection.

PCMSYNC

Bit 7: PCM frame synchronization.

I2SCFG

Bits 8-9: I2S configuration mode.

I2SE

Bit 10: I2S Enable.

I2SMOD

Bit 11: I2S mode selection.

I2SPR

I2S prescaler register

Offset: 0x20, size: 32, reset: 0x0000000A, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOE
rw 		ODD
rw 		I2SDIV
rw
Toggle fields

I2SDIV

Bits 0-7: I2S Linear prescaler.

ODD

Bit 8: Odd factor for the prescaler.

MCKOE

Bit 9: Master clock output enable.

SPI4

0x40013400: Serial peripheral interface

10/45 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SR
0xc DR
0x10 CRCPR
0x14 RXCRCR
0x18 TXCRCR
0x1c I2SCFGR
0x20 I2SPR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw 		BIDIOE
rw 		CRCEN
rw 		CRCNEXT
rw 		DFF
rw 		RXONLY
rw 		SSM
rw 		SSI
rw 		LSBFIRST
rw 		SPE
rw 		BR
rw 		MSTR
rw 		CPOL
rw 		CPHA
rw
Toggle fields

CPHA

Bit 0: Clock phase.

CPOL

Bit 1: Clock polarity.

MSTR

Bit 2: Master selection.

BR

Bits 3-5: Baud rate control.

SPE

Bit 6: SPI enable.

LSBFIRST

Bit 7: Frame format.

SSI

Bit 8: Internal slave select.

SSM

Bit 9: Software slave management.

RXONLY

Bit 10: Receive only.

DFF

Bit 11: Data frame format.

CRCNEXT

Bit 12: CRC transfer next.

CRCEN

Bit 13: Hardware CRC calculation enable.

BIDIOE

Bit 14: Output enable in bidirectional mode.

BIDIMODE

Bit 15: Bidirectional data mode enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXEIE
rw 		RXNEIE
rw 		ERRIE
rw 		FRF
rw 		SSOE
rw 		TXDMAEN
rw 		RXDMAEN
rw
Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

TXDMAEN

Bit 1: Tx buffer DMA enable.

SSOE

Bit 2: SS output enable.

FRF

Bit 4: Frame format.

ERRIE

Bit 5: Error interrupt enable.

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

TXEIE

Bit 7: Tx buffer empty interrupt enable.

SR

status register

Offset: 0x8, size: 32, reset: 0x00000002, access: Unspecified

8/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIFRFE
r 		BSY
r 		OVR
r 		MODF
r 		CRCERR
rw 		UDR
r 		CHSIDE
r 		TXE
r 		RXNE
r
Toggle fields

RXNE

Bit 0: Receive buffer not empty.

TXE

Bit 1: Transmit buffer empty.

CHSIDE

Bit 2: Channel side.

UDR

Bit 3: Underrun flag.

CRCERR

Bit 4: CRC error flag.

MODF

Bit 5: Mode fault.

OVR

Bit 6: Overrun flag.

BSY

Bit 7: Busy flag.

TIFRFE

Bit 8: TI frame format error.

DR

data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-15: Data register.

CRCPR

CRC polynomial register

Offset: 0x10, size: 32, reset: 0x00000007, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

RXCRCR

RX CRC register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

TXCRCR

TX CRC register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

I2SCFGR

I2S configuration register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SMOD
rw 		I2SE
rw 		I2SCFG
rw 		PCMSYNC
rw 		I2SSTD
rw 		CKPOL
rw 		DATLEN
rw 		CHLEN
rw
Toggle fields

CHLEN

Bit 0: Channel length (number of bits per audio channel).

DATLEN

Bits 1-2: Data length to be transferred.

CKPOL

Bit 3: Steady state clock polarity.

I2SSTD

Bits 4-5: I2S standard selection.

PCMSYNC

Bit 7: PCM frame synchronization.

I2SCFG

Bits 8-9: I2S configuration mode.

I2SE

Bit 10: I2S Enable.

I2SMOD

Bit 11: I2S mode selection.

I2SPR

I2S prescaler register

Offset: 0x20, size: 32, reset: 0x0000000A, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOE
rw 		ODD
rw 		I2SDIV
rw
Toggle fields

I2SDIV

Bits 0-7: I2S Linear prescaler.

ODD

Bit 8: Odd factor for the prescaler.

MCKOE

Bit 9: Master clock output enable.

SPI5

0x40015000: Serial peripheral interface

10/45 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SR
0xc DR
0x10 CRCPR
0x14 RXCRCR
0x18 TXCRCR
0x1c I2SCFGR
0x20 I2SPR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw 		BIDIOE
rw 		CRCEN
rw 		CRCNEXT
rw 		DFF
rw 		RXONLY
rw 		SSM
rw 		SSI
rw 		LSBFIRST
rw 		SPE
rw 		BR
rw 		MSTR
rw 		CPOL
rw 		CPHA
rw
Toggle fields

CPHA

Bit 0: Clock phase.

CPOL

Bit 1: Clock polarity.

MSTR

Bit 2: Master selection.

BR

Bits 3-5: Baud rate control.

SPE

Bit 6: SPI enable.

LSBFIRST

Bit 7: Frame format.

SSI

Bit 8: Internal slave select.

SSM

Bit 9: Software slave management.

RXONLY

Bit 10: Receive only.

DFF

Bit 11: Data frame format.

CRCNEXT

Bit 12: CRC transfer next.

CRCEN

Bit 13: Hardware CRC calculation enable.

BIDIOE

Bit 14: Output enable in bidirectional mode.

BIDIMODE

Bit 15: Bidirectional data mode enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXEIE
rw 		RXNEIE
rw 		ERRIE
rw 		FRF
rw 		SSOE
rw 		TXDMAEN
rw 		RXDMAEN
rw
Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

TXDMAEN

Bit 1: Tx buffer DMA enable.

SSOE

Bit 2: SS output enable.

FRF

Bit 4: Frame format.

ERRIE

Bit 5: Error interrupt enable.

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

TXEIE

Bit 7: Tx buffer empty interrupt enable.

SR

status register

Offset: 0x8, size: 32, reset: 0x00000002, access: Unspecified

8/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIFRFE
r 		BSY
r 		OVR
r 		MODF
r 		CRCERR
rw 		UDR
r 		CHSIDE
r 		TXE
r 		RXNE
r
Toggle fields

RXNE

Bit 0: Receive buffer not empty.

TXE

Bit 1: Transmit buffer empty.

CHSIDE

Bit 2: Channel side.

UDR

Bit 3: Underrun flag.

CRCERR

Bit 4: CRC error flag.

MODF

Bit 5: Mode fault.

OVR

Bit 6: Overrun flag.

BSY

Bit 7: Busy flag.

TIFRFE

Bit 8: TI frame format error.

DR

data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-15: Data register.

CRCPR

CRC polynomial register

Offset: 0x10, size: 32, reset: 0x00000007, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

RXCRCR

RX CRC register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

TXCRCR

TX CRC register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

I2SCFGR

I2S configuration register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SMOD
rw 		I2SE
rw 		I2SCFG
rw 		PCMSYNC
rw 		I2SSTD
rw 		CKPOL
rw 		DATLEN
rw 		CHLEN
rw
Toggle fields

CHLEN

Bit 0: Channel length (number of bits per audio channel).

DATLEN

Bits 1-2: Data length to be transferred.

CKPOL

Bit 3: Steady state clock polarity.

I2SSTD

Bits 4-5: I2S standard selection.

PCMSYNC

Bit 7: PCM frame synchronization.

I2SCFG

Bits 8-9: I2S configuration mode.

I2SE

Bit 10: I2S Enable.

I2SMOD

Bit 11: I2S mode selection.

I2SPR

I2S prescaler register

Offset: 0x20, size: 32, reset: 0x0000000A, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOE
rw 		ODD
rw 		I2SDIV
rw
Toggle fields

I2SDIV

Bits 0-7: I2S Linear prescaler.

ODD

Bit 8: Odd factor for the prescaler.

MCKOE

Bit 9: Master clock output enable.

SPI6

0x40015400: Serial peripheral interface

10/45 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SR
0xc DR
0x10 CRCPR
0x14 RXCRCR
0x18 TXCRCR
0x1c I2SCFGR
0x20 I2SPR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw 		BIDIOE
rw 		CRCEN
rw 		CRCNEXT
rw 		DFF
rw 		RXONLY
rw 		SSM
rw 		SSI
rw 		LSBFIRST
rw 		SPE
rw 		BR
rw 		MSTR
rw 		CPOL
rw 		CPHA
rw
Toggle fields

CPHA

Bit 0: Clock phase.

CPOL

Bit 1: Clock polarity.

MSTR

Bit 2: Master selection.

BR

Bits 3-5: Baud rate control.

SPE

Bit 6: SPI enable.

LSBFIRST

Bit 7: Frame format.

SSI

Bit 8: Internal slave select.

SSM

Bit 9: Software slave management.

RXONLY

Bit 10: Receive only.

DFF

Bit 11: Data frame format.

CRCNEXT

Bit 12: CRC transfer next.

CRCEN

Bit 13: Hardware CRC calculation enable.

BIDIOE

Bit 14: Output enable in bidirectional mode.

BIDIMODE

Bit 15: Bidirectional data mode enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXEIE
rw 		RXNEIE
rw 		ERRIE
rw 		FRF
rw 		SSOE
rw 		TXDMAEN
rw 		RXDMAEN
rw
Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

TXDMAEN

Bit 1: Tx buffer DMA enable.

SSOE

Bit 2: SS output enable.

FRF

Bit 4: Frame format.

ERRIE

Bit 5: Error interrupt enable.

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

TXEIE

Bit 7: Tx buffer empty interrupt enable.

SR

status register

Offset: 0x8, size: 32, reset: 0x00000002, access: Unspecified

8/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIFRFE
r 		BSY
r 		OVR
r 		MODF
r 		CRCERR
rw 		UDR
r 		CHSIDE
r 		TXE
r 		RXNE
r
Toggle fields

RXNE

Bit 0: Receive buffer not empty.

TXE

Bit 1: Transmit buffer empty.

CHSIDE

Bit 2: Channel side.

UDR

Bit 3: Underrun flag.

CRCERR

Bit 4: CRC error flag.

MODF

Bit 5: Mode fault.

OVR

Bit 6: Overrun flag.

BSY

Bit 7: Busy flag.

TIFRFE

Bit 8: TI frame format error.

DR

data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-15: Data register.

CRCPR

CRC polynomial register

Offset: 0x10, size: 32, reset: 0x00000007, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

RXCRCR

RX CRC register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

TXCRCR

TX CRC register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

I2SCFGR

I2S configuration register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SMOD
rw 		I2SE
rw 		I2SCFG
rw 		PCMSYNC
rw 		I2SSTD
rw 		CKPOL
rw 		DATLEN
rw 		CHLEN
rw
Toggle fields

CHLEN

Bit 0: Channel length (number of bits per audio channel).

DATLEN

Bits 1-2: Data length to be transferred.

CKPOL

Bit 3: Steady state clock polarity.

I2SSTD

Bits 4-5: I2S standard selection.

PCMSYNC

Bit 7: PCM frame synchronization.

I2SCFG

Bits 8-9: I2S configuration mode.

I2SE

Bit 10: I2S Enable.

I2SMOD

Bit 11: I2S mode selection.

I2SPR

I2S prescaler register

Offset: 0x20, size: 32, reset: 0x0000000A, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOE
rw 		ODD
rw 		I2SDIV
rw
Toggle fields

I2SDIV

Bits 0-7: I2S Linear prescaler.

ODD

Bit 8: Odd factor for the prescaler.

MCKOE

Bit 9: Master clock output enable.

SYSCFG

0x40013800: System configuration controller

2/25 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MEMRM
0x4 PMC
0x8 EXTICR1
0xc EXTICR2
0x10 EXTICR3
0x14 EXTICR4
0x20 CMPCR
Toggle registers

MEMRM

memory remap register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWP_FMC
rw 		FB_MODE
rw 		MEM_MODE
rw
Toggle fields

MEM_MODE

Bits 0-2: Memory mapping selection.

FB_MODE

Bit 8: Flash bank mode selection.

SWP_FMC

Bits 10-11: FMC memory mapping swap.

PMC

peripheral mode configuration register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MII_RMII_SEL
rw 		ADC3DC2
rw 		ADC2DC2
rw 		ADC1DC2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

ADC1DC2

Bit 16: ADC1DC2.

ADC2DC2

Bit 17: ADC2DC2.

ADC3DC2

Bit 18: ADC3DC2.

MII_RMII_SEL

Bit 23: Ethernet PHY interface selection.

EXTICR1

external interrupt configuration register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI3
rw 		EXTI2
rw 		EXTI1
rw 		EXTI0
rw
Toggle fields

EXTI0

Bits 0-3: EXTI x configuration (x = 0 to 3).

EXTI1

Bits 4-7: EXTI x configuration (x = 0 to 3).

EXTI2

Bits 8-11: EXTI x configuration (x = 0 to 3).

EXTI3

Bits 12-15: EXTI x configuration (x = 0 to 3).

EXTICR2

external interrupt configuration register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI7
rw 		EXTI6
rw 		EXTI5
rw 		EXTI4
rw
Toggle fields

EXTI4

Bits 0-3: EXTI x configuration (x = 4 to 7).

EXTI5

Bits 4-7: EXTI x configuration (x = 4 to 7).

EXTI6

Bits 8-11: EXTI x configuration (x = 4 to 7).

EXTI7

Bits 12-15: EXTI x configuration (x = 4 to 7).

EXTICR3

external interrupt configuration register 3

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI11
rw 		EXTI10
rw 		EXTI9
rw 		EXTI8
rw
Toggle fields

EXTI8

Bits 0-3: EXTI x configuration (x = 8 to 11).

EXTI9

Bits 4-7: EXTI x configuration (x = 8 to 11).

EXTI10

Bits 8-11: EXTI10.

EXTI11

Bits 12-15: EXTI x configuration (x = 8 to 11).

EXTICR4

external interrupt configuration register 4

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI15
rw 		EXTI14
rw 		EXTI13
rw 		EXTI12
rw
Toggle fields

EXTI12

Bits 0-3: EXTI x configuration (x = 12 to 15).

EXTI13

Bits 4-7: EXTI x configuration (x = 12 to 15).

EXTI14

Bits 8-11: EXTI x configuration (x = 12 to 15).

EXTI15

Bits 12-15: EXTI x configuration (x = 12 to 15).

CMPCR

Compensation cell control register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
READY
r 		CMP_PD
r
Toggle fields

CMP_PD

Bit 0: Compensation cell power-down.

READY

Bit 8: READY.

TIM1

0x40010000: Advanced-timers

0/127 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR1
0x38 CCR2
0x3c CCR3
0x40 CCR4
0x44 BDTR
0x48 DCR
0x4c DMAR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS4
rw 		OIS3N
rw 		OIS3
rw 		OIS2N
rw 		OIS2
rw 		OIS1N
rw 		OIS1
rw 		TI1S
rw 		MMS
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

OIS2

Bit 10: Output Idle state 2.

OIS2N

Bit 11: Output Idle state 2.

OIS3

Bit 12: Output Idle state 3.

OIS3N

Bit 13: Output Idle state 3.

OIS4

Bit 14: Output Idle state 4.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		COMDE
rw 		CC4DE
rw 		CC3DE
rw 		CC2DE
rw 		CC1DE
rw 		UDE
rw 		BIE
rw 		TIE
rw 		COMIE
rw 		CC4IE
rw 		CC3IE
rw 		CC2IE
rw 		CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4OF
rw 		CC3OF
rw 		CC2OF
rw 		CC1OF
rw 		BIF
rw 		TIF
rw 		COMIF
rw 		CC4IF
rw 		CC3IF
rw 		CC2IF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

BIF

Bit 7: Break interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w 		TG
w 		COMG
w 		CC4G
w 		CC3G
w 		CC2G
w 		CC1G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

CC3G

Bit 3: Capture/compare 3 generation.

CC4G

Bit 4: Capture/compare 4 generation.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw 		IC2PCS
rw 		CC2S
rw 		IC1F
rw 		ICPCS
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

ICPCS

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/Compare 2 selection.

IC2PCS

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC2CE
rw 		OC2M
rw 		OC2PE
rw 		OC2FE
rw 		CC2S
rw 		OC1CE
rw 		OC1M
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output Compare 1 fast enable.

OC1PE

Bit 3: Output Compare 1 preload enable.

OC1M

Bits 4-6: Output Compare 1 mode.

OC1CE

Bit 7: Output Compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2FE

Bit 10: Output Compare 2 fast enable.

OC2PE

Bit 11: Output Compare 2 preload enable.

OC2M

Bits 12-14: Output Compare 2 mode.

OC2CE

Bit 15: Output Compare 2 clear enable.

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw 		IC4PSC
rw 		CC4S
rw 		IC3F
rw 		IC3PSC
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/compare 3 selection.

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection.

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC4CE
rw 		OC4M
rw 		OC4PE
rw 		OC4FE
rw 		CC4S
rw 		OC3CE
rw 		OC3M
rw 		OC3PE
rw 		OC3FE
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

OC3FE

Bit 2: Output compare 3 fast enable.

OC3PE

Bit 3: Output compare 3 preload enable.

OC3M

Bits 4-6: Output compare 3 mode.

OC3CE

Bit 7: Output compare 3 clear enable.

CC4S

Bits 8-9: Capture/Compare 4 selection.

OC4FE

Bit 10: Output compare 4 fast enable.

OC4PE

Bit 11: Output compare 4 preload enable.

OC4M

Bits 12-14: Output compare 4 mode.

OC4CE

Bit 15: Output compare 4 clear enable.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4P
rw 		CC4E
rw 		CC3NP
rw 		CC3NE
rw 		CC3P
rw 		CC3E
rw 		CC2NP
rw 		CC2NE
rw 		CC2P
rw 		CC2E
rw 		CC1NP
rw 		CC1NE
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NE

Bit 6: Capture/Compare 2 complementary output enable.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NE

Bit 10: Capture/Compare 3 complementary output enable.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition counter value.

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle fields

CCR1

Bits 0-15: Capture/Compare 1 value.

CCR2

capture/compare register 2

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2
rw
Toggle fields

CCR2

Bits 0-15: Capture/Compare 2 value.

CCR3

capture/compare register 3

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR3
rw
Toggle fields

CCR3

Bits 0-15: Capture/Compare value.

CCR4

capture/compare register 4

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR4
rw
Toggle fields

CCR4

Bits 0-15: Capture/Compare value.

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

TIM10

0x40014400: General-purpose-timers

0/26 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR1
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw 		ARPE
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1OF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC1F
rw 		ICPCS
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

ICPCS

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC1M
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output Compare 1 fast enable.

OC1PE

Bit 3: Output Compare 1 preload enable.

OC1M

Bits 4-6: Output Compare 1 mode.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1NP
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle fields

CCR1

Bits 0-15: Capture/Compare 1 value.

TIM11

0x40014800: General-purpose-timers

0/27 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR1
0x50 OR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw 		ARPE
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1OF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC1F
rw 		ICPCS
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

ICPCS

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC1M
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output Compare 1 fast enable.

OC1PE

Bit 3: Output Compare 1 preload enable.

OC1M

Bits 4-6: Output Compare 1 mode.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1NP
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle fields

CCR1

Bits 0-15: Capture/Compare 1 value.

OR

option register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RMP
rw
Toggle fields

RMP

Bits 0-1: Input 1 remapping capability.

TIM12

0x40001800: General purpose timers

0/49 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR1
0x38 CCR2
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle fields

MMS

Bits 4-6: Master mode selection.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIE
rw 		CC2IE
rw 		CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC2OF
rw 		CC1OF
rw 		TIF
rw 		CC2IF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w 		CC2G
w 		CC1G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

TG

Bit 6: Trigger generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw 		IC2PCS
rw 		CC2S
rw 		IC1F
rw 		ICPCS
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

ICPCS

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-6: Input capture 1 filter.

CC2S

Bits 8-9: Capture/Compare 2 selection.

IC2PCS

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-14: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC2M
rw 		OC2PE
rw 		OC2FE
rw 		CC2S
rw 		OC1M
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output Compare 1 fast enable.

OC1PE

Bit 3: Output Compare 1 preload enable.

OC1M

Bits 4-6: Output Compare 1 mode.

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2FE

Bit 10: Output Compare 2 fast enable.

OC2PE

Bit 11: Output Compare 2 preload enable.

OC2M

Bits 12-14: Output Compare 2 mode.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC2NP
rw 		CC2P
rw 		CC2E
rw 		CC1NP
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle fields

CCR1

Bits 0-15: Capture/Compare 1 value.

CCR2

capture/compare register 2

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2
rw
Toggle fields

CCR2

Bits 0-15: Capture/Compare 2 value.

TIM13

0x40001c00: General-purpose-timers

0/26 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR1
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw 		ARPE
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1OF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC1F
rw 		ICPCS
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

ICPCS

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC1M
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output Compare 1 fast enable.

OC1PE

Bit 3: Output Compare 1 preload enable.

OC1M

Bits 4-6: Output Compare 1 mode.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1NP
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle fields

CCR1

Bits 0-15: Capture/Compare 1 value.

TIM14

0x40002000: General-purpose-timers

0/26 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR1
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw 		ARPE
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1OF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC1F
rw 		ICPCS
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

ICPCS

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC1M
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output Compare 1 fast enable.

OC1PE

Bit 3: Output Compare 1 preload enable.

OC1M

Bits 4-6: Output Compare 1 mode.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1NP
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle fields

CCR1

Bits 0-15: Capture/Compare 1 value.

TIM2

0x40000000: General purpose timers

0/107 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR1
0x38 CCR2
0x3c CCR3
0x40 CCR4
0x48 DCR
0x4c DMAR
0x50 OR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw 		MMS
rw 		CCDS
rw
Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		CC4DE
rw 		CC3DE
rw 		CC2DE
rw 		CC1DE
rw 		UDE
rw 		TIE
rw 		CC4IE
rw 		CC3IE
rw 		CC2IE
rw 		CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4OF
rw 		CC3OF
rw 		CC2OF
rw 		CC1OF
rw 		TIF
rw 		CC4IF
rw 		CC3IF
rw 		CC2IF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w 		CC4G
w 		CC3G
w 		CC2G
w 		CC1G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

CC3G

Bit 3: Capture/compare 3 generation.

CC4G

Bit 4: Capture/compare 4 generation.

TG

Bit 6: Trigger generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw 		IC2PCS
rw 		CC2S
rw 		IC1F
rw 		ICPCS
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

ICPCS

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/Compare 2 selection.

IC2PCS

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC2CE
rw 		OC2M
rw 		OC2PE
rw 		OC2FE
rw 		CC2S
rw 		OC1CE
rw 		OC1M
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: CC1S.

OC1FE

Bit 2: OC1FE.

OC1PE

Bit 3: OC1PE.

OC1M

Bits 4-6: OC1M.

OC1CE

Bit 7: OC1CE.

CC2S

Bits 8-9: CC2S.

OC2FE

Bit 10: OC2FE.

OC2PE

Bit 11: OC2PE.

OC2M

Bits 12-14: OC2M.

OC2CE

Bit 15: OC2CE.

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw 		IC4PSC
rw 		CC4S
rw 		IC3F
rw 		IC3PSC
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/compare 3 selection.

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection.

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
O24CE
rw 		OC4M
rw 		OC4PE
rw 		OC4FE
rw 		CC4S
rw 		OC3CE
rw 		OC3M
rw 		OC3PE
rw 		OC3FE
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: CC3S.

OC3FE

Bit 2: OC3FE.

OC3PE

Bit 3: OC3PE.

OC3M

Bits 4-6: OC3M.

OC3CE

Bit 7: OC3CE.

CC4S

Bits 8-9: CC4S.

OC4FE

Bit 10: OC4FE.

OC4PE

Bit 11: OC4PE.

OC4M

Bits 12-14: OC4M.

O24CE

Bit 15: O24CE.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP
rw 		CC4P
rw 		CC4E
rw 		CC3NP
rw 		CC3P
rw 		CC3E
rw 		CC2NP
rw 		CC2P
rw 		CC2E
rw 		CC1NP
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT_L
rw
Toggle fields

CNT_L

Bits 0-15: Low counter value.

CNT_H

Bits 16-31: High counter value.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARR_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR_L
rw
Toggle fields

ARR_L

Bits 0-15: Low Auto-reload value.

ARR_H

Bits 16-31: High Auto-reload value.

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR1_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1_L
rw
Toggle fields

CCR1_L

Bits 0-15: Low Capture/Compare 1 value.

CCR1_H

Bits 16-31: High Capture/Compare 1 value.

CCR2

capture/compare register 2

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR2_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2_L
rw
Toggle fields

CCR2_L

Bits 0-15: Low Capture/Compare 2 value.

CCR2_H

Bits 16-31: High Capture/Compare 2 value.

CCR3

capture/compare register 3

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR3_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR3_L
rw
Toggle fields

CCR3_L

Bits 0-15: Low Capture/Compare value.

CCR3_H

Bits 16-31: High Capture/Compare value.

CCR4

capture/compare register 4

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR4_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR4_L
rw
Toggle fields

CCR4_L

Bits 0-15: Low Capture/Compare value.

CCR4_H

Bits 16-31: High Capture/Compare value.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

OR

TIM5 option register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITR1_RMP
rw
Toggle fields

ITR1_RMP

Bits 10-11: Timer Input 4 remap.

TIM3

0x40000400: General purpose timers

0/106 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR1
0x38 CCR2
0x3c CCR3
0x40 CCR4
0x48 DCR
0x4c DMAR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw 		MMS
rw 		CCDS
rw
Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		CC4DE
rw 		CC3DE
rw 		CC2DE
rw 		CC1DE
rw 		UDE
rw 		TIE
rw 		CC4IE
rw 		CC3IE
rw 		CC2IE
rw 		CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4OF
rw 		CC3OF
rw 		CC2OF
rw 		CC1OF
rw 		TIF
rw 		CC4IF
rw 		CC3IF
rw 		CC2IF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w 		CC4G
w 		CC3G
w 		CC2G
w 		CC1G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

CC3G

Bit 3: Capture/compare 3 generation.

CC4G

Bit 4: Capture/compare 4 generation.

TG

Bit 6: Trigger generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw 		IC2PCS
rw 		CC2S
rw 		IC1F
rw 		ICPCS
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

ICPCS

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/Compare 2 selection.

IC2PCS

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC2CE
rw 		OC2M
rw 		OC2PE
rw 		OC2FE
rw 		CC2S
rw 		OC1CE
rw 		OC1M
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: CC1S.

OC1FE

Bit 2: OC1FE.

OC1PE

Bit 3: OC1PE.

OC1M

Bits 4-6: OC1M.

OC1CE

Bit 7: OC1CE.

CC2S

Bits 8-9: CC2S.

OC2FE

Bit 10: OC2FE.

OC2PE

Bit 11: OC2PE.

OC2M

Bits 12-14: OC2M.

OC2CE

Bit 15: OC2CE.

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw 		IC4PSC
rw 		CC4S
rw 		IC3F
rw 		IC3PSC
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/compare 3 selection.

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection.

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
O24CE
rw 		OC4M
rw 		OC4PE
rw 		OC4FE
rw 		CC4S
rw 		OC3CE
rw 		OC3M
rw 		OC3PE
rw 		OC3FE
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: CC3S.

OC3FE

Bit 2: OC3FE.

OC3PE

Bit 3: OC3PE.

OC3M

Bits 4-6: OC3M.

OC3CE

Bit 7: OC3CE.

CC4S

Bits 8-9: CC4S.

OC4FE

Bit 10: OC4FE.

OC4PE

Bit 11: OC4PE.

OC4M

Bits 12-14: OC4M.

O24CE

Bit 15: O24CE.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP
rw 		CC4P
rw 		CC4E
rw 		CC3NP
rw 		CC3P
rw 		CC3E
rw 		CC2NP
rw 		CC2P
rw 		CC2E
rw 		CC1NP
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT_L
rw
Toggle fields

CNT_L

Bits 0-15: Low counter value.

CNT_H

Bits 16-31: High counter value.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARR_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR_L
rw
Toggle fields

ARR_L

Bits 0-15: Low Auto-reload value.

ARR_H

Bits 16-31: High Auto-reload value.

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR1_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1_L
rw
Toggle fields

CCR1_L

Bits 0-15: Low Capture/Compare 1 value.

CCR1_H

Bits 16-31: High Capture/Compare 1 value.

CCR2

capture/compare register 2

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR2_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2_L
rw
Toggle fields

CCR2_L

Bits 0-15: Low Capture/Compare 2 value.

CCR2_H

Bits 16-31: High Capture/Compare 2 value.

CCR3

capture/compare register 3

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR3_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR3_L
rw
Toggle fields

CCR3_L

Bits 0-15: Low Capture/Compare value.

CCR3_H

Bits 16-31: High Capture/Compare value.

CCR4

capture/compare register 4

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR4_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR4_L
rw
Toggle fields

CCR4_L

Bits 0-15: Low Capture/Compare value.

CCR4_H

Bits 16-31: High Capture/Compare value.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

TIM4

0x40000800: General purpose timers

0/106 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR1
0x38 CCR2
0x3c CCR3
0x40 CCR4
0x48 DCR
0x4c DMAR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw 		MMS
rw 		CCDS
rw
Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		CC4DE
rw 		CC3DE
rw 		CC2DE
rw 		CC1DE
rw 		UDE
rw 		TIE
rw 		CC4IE
rw 		CC3IE
rw 		CC2IE
rw 		CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4OF
rw 		CC3OF
rw 		CC2OF
rw 		CC1OF
rw 		TIF
rw 		CC4IF
rw 		CC3IF
rw 		CC2IF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w 		CC4G
w 		CC3G
w 		CC2G
w 		CC1G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

CC3G

Bit 3: Capture/compare 3 generation.

CC4G

Bit 4: Capture/compare 4 generation.

TG

Bit 6: Trigger generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw 		IC2PCS
rw 		CC2S
rw 		IC1F
rw 		ICPCS
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

ICPCS

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/Compare 2 selection.

IC2PCS

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC2CE
rw 		OC2M
rw 		OC2PE
rw 		OC2FE
rw 		CC2S
rw 		OC1CE
rw 		OC1M
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: CC1S.

OC1FE

Bit 2: OC1FE.

OC1PE

Bit 3: OC1PE.

OC1M

Bits 4-6: OC1M.

OC1CE

Bit 7: OC1CE.

CC2S

Bits 8-9: CC2S.

OC2FE

Bit 10: OC2FE.

OC2PE

Bit 11: OC2PE.

OC2M

Bits 12-14: OC2M.

OC2CE

Bit 15: OC2CE.

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw 		IC4PSC
rw 		CC4S
rw 		IC3F
rw 		IC3PSC
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/compare 3 selection.

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection.

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
O24CE
rw 		OC4M
rw 		OC4PE
rw 		OC4FE
rw 		CC4S
rw 		OC3CE
rw 		OC3M
rw 		OC3PE
rw 		OC3FE
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: CC3S.

OC3FE

Bit 2: OC3FE.

OC3PE

Bit 3: OC3PE.

OC3M

Bits 4-6: OC3M.

OC3CE

Bit 7: OC3CE.

CC4S

Bits 8-9: CC4S.

OC4FE

Bit 10: OC4FE.

OC4PE

Bit 11: OC4PE.

OC4M

Bits 12-14: OC4M.

O24CE

Bit 15: O24CE.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP
rw 		CC4P
rw 		CC4E
rw 		CC3NP
rw 		CC3P
rw 		CC3E
rw 		CC2NP
rw 		CC2P
rw 		CC2E
rw 		CC1NP
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT_L
rw
Toggle fields

CNT_L

Bits 0-15: Low counter value.

CNT_H

Bits 16-31: High counter value.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARR_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR_L
rw
Toggle fields

ARR_L

Bits 0-15: Low Auto-reload value.

ARR_H

Bits 16-31: High Auto-reload value.

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR1_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1_L
rw
Toggle fields

CCR1_L

Bits 0-15: Low Capture/Compare 1 value.

CCR1_H

Bits 16-31: High Capture/Compare 1 value.

CCR2

capture/compare register 2

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR2_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2_L
rw
Toggle fields

CCR2_L

Bits 0-15: Low Capture/Compare 2 value.

CCR2_H

Bits 16-31: High Capture/Compare 2 value.

CCR3

capture/compare register 3

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR3_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR3_L
rw
Toggle fields

CCR3_L

Bits 0-15: Low Capture/Compare value.

CCR3_H

Bits 16-31: High Capture/Compare value.

CCR4

capture/compare register 4

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR4_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR4_L
rw
Toggle fields

CCR4_L

Bits 0-15: Low Capture/Compare value.

CCR4_H

Bits 16-31: High Capture/Compare value.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

TIM5

0x40000c00: General-purpose-timers

0/107 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR1
0x38 CCR2
0x3c CCR3
0x40 CCR4
0x48 DCR
0x4c DMAR
0x50 OR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw 		MMS
rw 		CCDS
rw
Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		CC4DE
rw 		CC3DE
rw 		CC2DE
rw 		CC1DE
rw 		UDE
rw 		TIE
rw 		CC4IE
rw 		CC3IE
rw 		CC2IE
rw 		CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4OF
rw 		CC3OF
rw 		CC2OF
rw 		CC1OF
rw 		TIF
rw 		CC4IF
rw 		CC3IF
rw 		CC2IF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w 		CC4G
w 		CC3G
w 		CC2G
w 		CC1G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

CC3G

Bit 3: Capture/compare 3 generation.

CC4G

Bit 4: Capture/compare 4 generation.

TG

Bit 6: Trigger generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw 		IC2PCS
rw 		CC2S
rw 		IC1F
rw 		ICPCS
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

ICPCS

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/Compare 2 selection.

IC2PCS

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC2CE
rw 		OC2M
rw 		OC2PE
rw 		OC2FE
rw 		CC2S
rw 		OC1CE
rw 		OC1M
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: CC1S.

OC1FE

Bit 2: OC1FE.

OC1PE

Bit 3: OC1PE.

OC1M

Bits 4-6: OC1M.

OC1CE

Bit 7: OC1CE.

CC2S

Bits 8-9: CC2S.

OC2FE

Bit 10: OC2FE.

OC2PE

Bit 11: OC2PE.

OC2M

Bits 12-14: OC2M.

OC2CE

Bit 15: OC2CE.

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw 		IC4PSC
rw 		CC4S
rw 		IC3F
rw 		IC3PSC
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/compare 3 selection.

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection.

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
O24CE
rw 		OC4M
rw 		OC4PE
rw 		OC4FE
rw 		CC4S
rw 		OC3CE
rw 		OC3M
rw 		OC3PE
rw 		OC3FE
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: CC3S.

OC3FE

Bit 2: OC3FE.

OC3PE

Bit 3: OC3PE.

OC3M

Bits 4-6: OC3M.

OC3CE

Bit 7: OC3CE.

CC4S

Bits 8-9: CC4S.

OC4FE

Bit 10: OC4FE.

OC4PE

Bit 11: OC4PE.

OC4M

Bits 12-14: OC4M.

O24CE

Bit 15: O24CE.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP
rw 		CC4P
rw 		CC4E
rw 		CC3NP
rw 		CC3P
rw 		CC3E
rw 		CC2NP
rw 		CC2P
rw 		CC2E
rw 		CC1NP
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT_L
rw
Toggle fields

CNT_L

Bits 0-15: Low counter value.

CNT_H

Bits 16-31: High counter value.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARR_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR_L
rw
Toggle fields

ARR_L

Bits 0-15: Low Auto-reload value.

ARR_H

Bits 16-31: High Auto-reload value.

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR1_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1_L
rw
Toggle fields

CCR1_L

Bits 0-15: Low Capture/Compare 1 value.

CCR1_H

Bits 16-31: High Capture/Compare 1 value.

CCR2

capture/compare register 2

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR2_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2_L
rw
Toggle fields

CCR2_L

Bits 0-15: Low Capture/Compare 2 value.

CCR2_H

Bits 16-31: High Capture/Compare 2 value.

CCR3

capture/compare register 3

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR3_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR3_L
rw
Toggle fields

CCR3_L

Bits 0-15: Low Capture/Compare value.

CCR3_H

Bits 16-31: High Capture/Compare value.

CCR4

capture/compare register 4

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR4_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR4_L
rw
Toggle fields

CCR4_L

Bits 0-15: Low Capture/Compare value.

CCR4_H

Bits 16-31: High Capture/Compare value.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

OR

TIM5 option register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IT4_RMP
rw
Toggle fields

IT4_RMP

Bits 6-7: Timer Input 4 remap.

TIM6

0x40001000: Basic timers

0/13 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x24 CNT
0x28 PSC
0x2c ARR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

ARPE

Bit 7: Auto-reload preload enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle fields

MMS

Bits 4-6: Master mode selection.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

UDE

Bit 8: Update DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UG
w
Toggle fields

UG

Bit 0: Update generation.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: Low counter value.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Low Auto-reload value.

TIM7

0x40001400: Basic timers

0/13 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x24 CNT
0x28 PSC
0x2c ARR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

ARPE

Bit 7: Auto-reload preload enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle fields

MMS

Bits 4-6: Master mode selection.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

UDE

Bit 8: Update DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UG
w
Toggle fields

UG

Bit 0: Update generation.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: Low counter value.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Low Auto-reload value.

TIM8

0x40010400: Advanced-timers

0/127 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR1
0x38 CCR2
0x3c CCR3
0x40 CCR4
0x44 BDTR
0x48 DCR
0x4c DMAR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS4
rw 		OIS3N
rw 		OIS3
rw 		OIS2N
rw 		OIS2
rw 		OIS1N
rw 		OIS1
rw 		TI1S
rw 		MMS
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

OIS2

Bit 10: Output Idle state 2.

OIS2N

Bit 11: Output Idle state 2.

OIS3

Bit 12: Output Idle state 3.

OIS3N

Bit 13: Output Idle state 3.

OIS4

Bit 14: Output Idle state 4.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		COMDE
rw 		CC4DE
rw 		CC3DE
rw 		CC2DE
rw 		CC1DE
rw 		UDE
rw 		BIE
rw 		TIE
rw 		COMIE
rw 		CC4IE
rw 		CC3IE
rw 		CC2IE
rw 		CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4OF
rw 		CC3OF
rw 		CC2OF
rw 		CC1OF
rw 		BIF
rw 		TIF
rw 		COMIF
rw 		CC4IF
rw 		CC3IF
rw 		CC2IF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

BIF

Bit 7: Break interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w 		TG
w 		COMG
w 		CC4G
w 		CC3G
w 		CC2G
w 		CC1G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

CC3G

Bit 3: Capture/compare 3 generation.

CC4G

Bit 4: Capture/compare 4 generation.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw 		IC2PCS
rw 		CC2S
rw 		IC1F
rw 		ICPCS
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

ICPCS

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/Compare 2 selection.

IC2PCS

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC2CE
rw 		OC2M
rw 		OC2PE
rw 		OC2FE
rw 		CC2S
rw 		OC1CE
rw 		OC1M
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output Compare 1 fast enable.

OC1PE

Bit 3: Output Compare 1 preload enable.

OC1M

Bits 4-6: Output Compare 1 mode.

OC1CE

Bit 7: Output Compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2FE

Bit 10: Output Compare 2 fast enable.

OC2PE

Bit 11: Output Compare 2 preload enable.

OC2M

Bits 12-14: Output Compare 2 mode.

OC2CE

Bit 15: Output Compare 2 clear enable.

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw 		IC4PSC
rw 		CC4S
rw 		IC3F
rw 		IC3PSC
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/compare 3 selection.

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection.

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC4CE
rw 		OC4M
rw 		OC4PE
rw 		OC4FE
rw 		CC4S
rw 		OC3CE
rw 		OC3M
rw 		OC3PE
rw 		OC3FE
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

OC3FE

Bit 2: Output compare 3 fast enable.

OC3PE

Bit 3: Output compare 3 preload enable.

OC3M

Bits 4-6: Output compare 3 mode.

OC3CE

Bit 7: Output compare 3 clear enable.

CC4S

Bits 8-9: Capture/Compare 4 selection.

OC4FE

Bit 10: Output compare 4 fast enable.

OC4PE

Bit 11: Output compare 4 preload enable.

OC4M

Bits 12-14: Output compare 4 mode.

OC4CE

Bit 15: Output compare 4 clear enable.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4P
rw 		CC4E
rw 		CC3NP
rw 		CC3NE
rw 		CC3P
rw 		CC3E
rw 		CC2NP
rw 		CC2NE
rw 		CC2P
rw 		CC2E
rw 		CC1NP
rw 		CC1NE
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NE

Bit 6: Capture/Compare 2 complementary output enable.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NE

Bit 10: Capture/Compare 3 complementary output enable.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition counter value.

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle fields

CCR1

Bits 0-15: Capture/Compare 1 value.

CCR2

capture/compare register 2

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2
rw
Toggle fields

CCR2

Bits 0-15: Capture/Compare 2 value.

CCR3

capture/compare register 3

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR3
rw
Toggle fields

CCR3

Bits 0-15: Capture/Compare value.

CCR4

capture/compare register 4

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR4
rw
Toggle fields

CCR4

Bits 0-15: Capture/Compare value.

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

TIM9

0x40014000: General purpose timers

0/49 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR1
0x38 CCR2
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle fields

MMS

Bits 4-6: Master mode selection.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIE
rw 		CC2IE
rw 		CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC2OF
rw 		CC1OF
rw 		TIF
rw 		CC2IF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w 		CC2G
w 		CC1G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

TG

Bit 6: Trigger generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw 		IC2PCS
rw 		CC2S
rw 		IC1F
rw 		ICPCS
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

ICPCS

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-6: Input capture 1 filter.

CC2S

Bits 8-9: Capture/Compare 2 selection.

IC2PCS

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-14: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC2M
rw 		OC2PE
rw 		OC2FE
rw 		CC2S
rw 		OC1M
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output Compare 1 fast enable.

OC1PE

Bit 3: Output Compare 1 preload enable.

OC1M

Bits 4-6: Output Compare 1 mode.

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2FE

Bit 10: Output Compare 2 fast enable.

OC2PE

Bit 11: Output Compare 2 preload enable.

OC2M

Bits 12-14: Output Compare 2 mode.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC2NP
rw 		CC2P
rw 		CC2E
rw 		CC1NP
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle fields

CCR1

Bits 0-15: Capture/Compare 1 value.

CCR2

capture/compare register 2

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2
rw
Toggle fields

CCR2

Bits 0-15: Capture/Compare 2 value.

UART4

0x40004c00: Universal synchronous asynchronous receiver transmitter

6/39 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 SR
0x4 DR
0x8 BRR
0xc CR1
0x10 CR2
0x14 CR3
Toggle registers

SR

Status register

Offset: 0x0, size: 32, reset: 0x00C00000, access: Unspecified

6/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LBD
rw 		TXE
r 		TC
rw 		RXNE
rw 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: Parity error.

FE

Bit 1: Framing error.

NF

Bit 2: Noise detected flag.

ORE

Bit 3: Overrun error.

IDLE

Bit 4: IDLE line detected.

RXNE

Bit 5: Read data register not empty.

TC

Bit 6: Transmission complete.

TXE

Bit 7: Transmit data register empty.

LBD

Bit 8: LIN break detection flag.

DR

Data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-8: Data value.

BRR

Baud rate register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV_Mantissa
rw 		DIV_Fraction
rw
Toggle fields

DIV_Fraction

Bits 0-3: fraction of USARTDIV.

DIV_Mantissa

Bits 4-15: mantissa of USARTDIV.

CR1

Control register 1

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		UE
rw 		M
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		RWU
rw 		SBK
rw
Toggle fields

SBK

Bit 0: Send break.

RWU

Bit 1: Receiver wakeup.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: TXE interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Wakeup method.

M

Bit 12: Word length.

UE

Bit 13: USART enable.

OVER8

Bit 15: Oversampling mode.

CR2

Control register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINEN
rw 		STOP
rw 		LBDIE
rw 		LBDL
rw 		ADD
rw
Toggle fields

ADD

Bits 0-3: Address of the USART node.

LBDL

Bit 5: lin break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

CR3

Control register 3

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ONEBIT
rw 		DMAT
rw 		DMAR
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: IrDA mode enable.

IRLP

Bit 2: IrDA low-power.

HDSEL

Bit 3: Half-duplex selection.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

ONEBIT

Bit 11: One sample bit method enable.

UART5

0x40005000: Universal synchronous asynchronous receiver transmitter

6/39 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 SR
0x4 DR
0x8 BRR
0xc CR1
0x10 CR2
0x14 CR3
Toggle registers

SR

Status register

Offset: 0x0, size: 32, reset: 0x00C00000, access: Unspecified

6/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LBD
rw 		TXE
r 		TC
rw 		RXNE
rw 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: Parity error.

FE

Bit 1: Framing error.

NF

Bit 2: Noise detected flag.

ORE

Bit 3: Overrun error.

IDLE

Bit 4: IDLE line detected.

RXNE

Bit 5: Read data register not empty.

TC

Bit 6: Transmission complete.

TXE

Bit 7: Transmit data register empty.

LBD

Bit 8: LIN break detection flag.

DR

Data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-8: Data value.

BRR

Baud rate register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV_Mantissa
rw 		DIV_Fraction
rw
Toggle fields

DIV_Fraction

Bits 0-3: fraction of USARTDIV.

DIV_Mantissa

Bits 4-15: mantissa of USARTDIV.

CR1

Control register 1

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		UE
rw 		M
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		RWU
rw 		SBK
rw
Toggle fields

SBK

Bit 0: Send break.

RWU

Bit 1: Receiver wakeup.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: TXE interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Wakeup method.

M

Bit 12: Word length.

UE

Bit 13: USART enable.

OVER8

Bit 15: Oversampling mode.

CR2

Control register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINEN
rw 		STOP
rw 		LBDIE
rw 		LBDL
rw 		ADD
rw
Toggle fields

ADD

Bits 0-3: Address of the USART node.

LBDL

Bit 5: lin break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

CR3

Control register 3

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ONEBIT
rw 		DMAT
rw 		DMAR
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: IrDA mode enable.

IRLP

Bit 2: IrDA low-power.

HDSEL

Bit 3: Half-duplex selection.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

ONEBIT

Bit 11: One sample bit method enable.

UART7

0x40007800: Universal synchronous asynchronous receiver transmitter

6/51 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 SR
0x4 DR
0x8 BRR
0xc CR1
0x10 CR2
0x14 CR3
0x18 GTPR
Toggle registers

SR

Status register

Offset: 0x0, size: 32, reset: 0x00C00000, access: Unspecified

6/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTS
rw 		LBD
rw 		TXE
r 		TC
rw 		RXNE
rw 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: Parity error.

FE

Bit 1: Framing error.

NF

Bit 2: Noise detected flag.

ORE

Bit 3: Overrun error.

IDLE

Bit 4: IDLE line detected.

RXNE

Bit 5: Read data register not empty.

TC

Bit 6: Transmission complete.

TXE

Bit 7: Transmit data register empty.

LBD

Bit 8: LIN break detection flag.

CTS

Bit 9: CTS flag.

DR

Data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-8: Data value.

BRR

Baud rate register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV_Mantissa
rw 		DIV_Fraction
rw
Toggle fields

DIV_Fraction

Bits 0-3: fraction of USARTDIV.

DIV_Mantissa

Bits 4-15: mantissa of USARTDIV.

CR1

Control register 1

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		UE
rw 		M
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		RWU
rw 		SBK
rw
Toggle fields

SBK

Bit 0: Send break.

RWU

Bit 1: Receiver wakeup.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: TXE interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Wakeup method.

M

Bit 12: Word length.

UE

Bit 13: USART enable.

OVER8

Bit 15: Oversampling mode.

CR2

Control register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADD
rw
Toggle fields

ADD

Bits 0-3: Address of the USART node.

LBDL

Bit 5: lin break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

CR3

Control register 3

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: IrDA mode enable.

IRLP

Bit 2: IrDA low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

GTPR

Guard time and prescaler register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

UART8

0x40007c00: Universal synchronous asynchronous receiver transmitter

6/51 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 SR
0x4 DR
0x8 BRR
0xc CR1
0x10 CR2
0x14 CR3
0x18 GTPR
Toggle registers

SR

Status register

Offset: 0x0, size: 32, reset: 0x00C00000, access: Unspecified

6/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTS
rw 		LBD
rw 		TXE
r 		TC
rw 		RXNE
rw 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: Parity error.

FE

Bit 1: Framing error.

NF

Bit 2: Noise detected flag.

ORE

Bit 3: Overrun error.

IDLE

Bit 4: IDLE line detected.

RXNE

Bit 5: Read data register not empty.

TC

Bit 6: Transmission complete.

TXE

Bit 7: Transmit data register empty.

LBD

Bit 8: LIN break detection flag.

CTS

Bit 9: CTS flag.

DR

Data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-8: Data value.

BRR

Baud rate register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV_Mantissa
rw 		DIV_Fraction
rw
Toggle fields

DIV_Fraction

Bits 0-3: fraction of USARTDIV.

DIV_Mantissa

Bits 4-15: mantissa of USARTDIV.

CR1

Control register 1

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		UE
rw 		M
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		RWU
rw 		SBK
rw
Toggle fields

SBK

Bit 0: Send break.

RWU

Bit 1: Receiver wakeup.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: TXE interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Wakeup method.

M

Bit 12: Word length.

UE

Bit 13: USART enable.

OVER8

Bit 15: Oversampling mode.

CR2

Control register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADD
rw
Toggle fields

ADD

Bits 0-3: Address of the USART node.

LBDL

Bit 5: lin break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

CR3

Control register 3

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: IrDA mode enable.

IRLP

Bit 2: IrDA low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

GTPR

Guard time and prescaler register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

USART1

0x40011000: Universal synchronous asynchronous receiver transmitter

6/51 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 SR
0x4 DR
0x8 BRR
0xc CR1
0x10 CR2
0x14 CR3
0x18 GTPR
Toggle registers

SR

Status register

Offset: 0x0, size: 32, reset: 0x00C00000, access: Unspecified

6/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTS
rw 		LBD
rw 		TXE
r 		TC
rw 		RXNE
rw 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: Parity error.

FE

Bit 1: Framing error.

NF

Bit 2: Noise detected flag.

ORE

Bit 3: Overrun error.

IDLE

Bit 4: IDLE line detected.

RXNE

Bit 5: Read data register not empty.

TC

Bit 6: Transmission complete.

TXE

Bit 7: Transmit data register empty.

LBD

Bit 8: LIN break detection flag.

CTS

Bit 9: CTS flag.

DR

Data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-8: Data value.

BRR

Baud rate register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV_Mantissa
rw 		DIV_Fraction
rw
Toggle fields

DIV_Fraction

Bits 0-3: fraction of USARTDIV.

DIV_Mantissa

Bits 4-15: mantissa of USARTDIV.

CR1

Control register 1

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		UE
rw 		M
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		RWU
rw 		SBK
rw
Toggle fields

SBK

Bit 0: Send break.

RWU

Bit 1: Receiver wakeup.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: TXE interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Wakeup method.

M

Bit 12: Word length.

UE

Bit 13: USART enable.

OVER8

Bit 15: Oversampling mode.

CR2

Control register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADD
rw
Toggle fields

ADD

Bits 0-3: Address of the USART node.

LBDL

Bit 5: lin break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

CR3

Control register 3

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: IrDA mode enable.

IRLP

Bit 2: IrDA low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

GTPR

Guard time and prescaler register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

USART2

0x40004400: Universal synchronous asynchronous receiver transmitter

6/51 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 SR
0x4 DR
0x8 BRR
0xc CR1
0x10 CR2
0x14 CR3
0x18 GTPR
Toggle registers

SR

Status register

Offset: 0x0, size: 32, reset: 0x00C00000, access: Unspecified

6/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTS
rw 		LBD
rw 		TXE
r 		TC
rw 		RXNE
rw 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: Parity error.

FE

Bit 1: Framing error.

NF

Bit 2: Noise detected flag.

ORE

Bit 3: Overrun error.

IDLE

Bit 4: IDLE line detected.

RXNE

Bit 5: Read data register not empty.

TC

Bit 6: Transmission complete.

TXE

Bit 7: Transmit data register empty.

LBD

Bit 8: LIN break detection flag.

CTS

Bit 9: CTS flag.

DR

Data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-8: Data value.

BRR

Baud rate register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV_Mantissa
rw 		DIV_Fraction
rw
Toggle fields

DIV_Fraction

Bits 0-3: fraction of USARTDIV.

DIV_Mantissa

Bits 4-15: mantissa of USARTDIV.

CR1

Control register 1

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		UE
rw 		M
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		RWU
rw 		SBK
rw
Toggle fields

SBK

Bit 0: Send break.

RWU

Bit 1: Receiver wakeup.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: TXE interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Wakeup method.

M

Bit 12: Word length.

UE

Bit 13: USART enable.

OVER8

Bit 15: Oversampling mode.

CR2

Control register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADD
rw
Toggle fields

ADD

Bits 0-3: Address of the USART node.

LBDL

Bit 5: lin break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

CR3

Control register 3

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: IrDA mode enable.

IRLP

Bit 2: IrDA low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

GTPR

Guard time and prescaler register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

USART3

0x40004800: Universal synchronous asynchronous receiver transmitter

6/51 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 SR
0x4 DR
0x8 BRR
0xc CR1
0x10 CR2
0x14 CR3
0x18 GTPR
Toggle registers

SR

Status register

Offset: 0x0, size: 32, reset: 0x00C00000, access: Unspecified

6/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTS
rw 		LBD
rw 		TXE
r 		TC
rw 		RXNE
rw 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: Parity error.

FE

Bit 1: Framing error.

NF

Bit 2: Noise detected flag.

ORE

Bit 3: Overrun error.

IDLE

Bit 4: IDLE line detected.

RXNE

Bit 5: Read data register not empty.

TC

Bit 6: Transmission complete.

TXE

Bit 7: Transmit data register empty.

LBD

Bit 8: LIN break detection flag.

CTS

Bit 9: CTS flag.

DR

Data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-8: Data value.

BRR

Baud rate register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV_Mantissa
rw 		DIV_Fraction
rw
Toggle fields

DIV_Fraction

Bits 0-3: fraction of USARTDIV.

DIV_Mantissa

Bits 4-15: mantissa of USARTDIV.

CR1

Control register 1

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		UE
rw 		M
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		RWU
rw 		SBK
rw
Toggle fields

SBK

Bit 0: Send break.

RWU

Bit 1: Receiver wakeup.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: TXE interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Wakeup method.

M

Bit 12: Word length.

UE

Bit 13: USART enable.

OVER8

Bit 15: Oversampling mode.

CR2

Control register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADD
rw
Toggle fields

ADD

Bits 0-3: Address of the USART node.

LBDL

Bit 5: lin break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

CR3

Control register 3

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: IrDA mode enable.

IRLP

Bit 2: IrDA low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

GTPR

Guard time and prescaler register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

USART6

0x40011400: Universal synchronous asynchronous receiver transmitter

6/51 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 SR
0x4 DR
0x8 BRR
0xc CR1
0x10 CR2
0x14 CR3
0x18 GTPR
Toggle registers

SR

Status register

Offset: 0x0, size: 32, reset: 0x00C00000, access: Unspecified

6/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTS
rw 		LBD
rw 		TXE
r 		TC
rw 		RXNE
rw 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: Parity error.

FE

Bit 1: Framing error.

NF

Bit 2: Noise detected flag.

ORE

Bit 3: Overrun error.

IDLE

Bit 4: IDLE line detected.

RXNE

Bit 5: Read data register not empty.

TC

Bit 6: Transmission complete.

TXE

Bit 7: Transmit data register empty.

LBD

Bit 8: LIN break detection flag.

CTS

Bit 9: CTS flag.

DR

Data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-8: Data value.

BRR

Baud rate register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV_Mantissa
rw 		DIV_Fraction
rw
Toggle fields

DIV_Fraction

Bits 0-3: fraction of USARTDIV.

DIV_Mantissa

Bits 4-15: mantissa of USARTDIV.

CR1

Control register 1

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		UE
rw 		M
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		RWU
rw 		SBK
rw
Toggle fields

SBK

Bit 0: Send break.

RWU

Bit 1: Receiver wakeup.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: TXE interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Wakeup method.

M

Bit 12: Word length.

UE

Bit 13: USART enable.

OVER8

Bit 15: Oversampling mode.

CR2

Control register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADD
rw
Toggle fields

ADD

Bits 0-3: Address of the USART node.

LBDL

Bit 5: lin break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

CR3

Control register 3

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: IrDA mode enable.

IRLP

Bit 2: IrDA low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

GTPR

Guard time and prescaler register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

WWDG

0x40002c00: Window watchdog

0/7 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 CFR
0x8 SR
Toggle registers

CR

Control register

Offset: 0x0, size: 32, reset: 0x0000007F, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDGA
rw 		T
rw
Toggle fields

T

Bits 0-6: 7-bit counter (MSB to LSB).

WDGA

Bit 7: Activation bit.

CFR

Configuration register

Offset: 0x4, size: 32, reset: 0x0000007F, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWI
rw 		WDGTB1
rw 		WDGTB0
rw 		W
rw
Toggle fields

W

Bits 0-6: 7-bit window value.

WDGTB0

Bit 7: Timer base.

WDGTB1

Bit 8: Timer base.

EWI

Bit 9: Early wakeup interrupt.

SR

Status register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWIF
rw
Toggle fields

EWIF

Bit 0: Early wakeup interrupt flag.