0x40012400: ADC address block description
146/146 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | ISR | ||||||||||||||||||||||||||||||||
0x4 | IER | ||||||||||||||||||||||||||||||||
0x8 | CR | ||||||||||||||||||||||||||||||||
0xc | CFGR1 | ||||||||||||||||||||||||||||||||
0x10 | CFGR2 | ||||||||||||||||||||||||||||||||
0x14 | SMPR | ||||||||||||||||||||||||||||||||
0x20 | AWD1TR | ||||||||||||||||||||||||||||||||
0x24 | AWD2TR | ||||||||||||||||||||||||||||||||
0x28 | CHSELR0 | ||||||||||||||||||||||||||||||||
0x28 | CHSELR1 | ||||||||||||||||||||||||||||||||
0x2c | AWD3TR | ||||||||||||||||||||||||||||||||
0x40 | DR | ||||||||||||||||||||||||||||||||
0xa0 | AWD2CR | ||||||||||||||||||||||||||||||||
0xa4 | AWD3CR | ||||||||||||||||||||||||||||||||
0xb4 | CALFACT | ||||||||||||||||||||||||||||||||
0x308 | CCR |
ADC interrupt and status register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
10/10 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CCRDY
rw |
EOCAL
rw |
AWD3
rw |
AWD2
rw |
AWD1
rw |
OVR
rw |
EOS
rw |
EOC
rw |
EOSMP
rw |
ADRDY
rw |
Bit 0: ADC ready This bit is set by hardware after the ADC has been enabled (ADENÂ =Â 1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it..
Allowed values:
0: NotReady: ADC not yet ready to start conversion
1: Ready: ADC ready to start conversion
Bit 1: End of sampling flag This bit is set by hardware during the conversion, at the end of the sampling phase.It is cleared by software by programming it to '1â..
Allowed values:
0: NotAtEnd: Not at the end of the samplings phase
1: AtEnd: End of sampling phase reached
Bit 2: End of conversion flag This bit is set by hardware at the end of each conversion of a channel when a new data result is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register..
Allowed values:
0: NotComplete: Channel conversion is not complete
1: Complete: Channel conversion complete
Bit 3: End of sequence flag This bit is set by hardware at the end of the conversion of a sequence of channels selected by the CHSEL bits. It is cleared by software writing 1 to it..
Allowed values:
0: NotComplete: Conversion sequence is not complete
1: Complete: Conversion sequence complete
Bit 4: ADC overrun This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete while the EOC flag was already set. It is cleared by software writing 1 to it..
Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred
Bit 7: Analog watchdog 1 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_TR1 and ADC_HR1 registers. It is cleared by software by programming it to 1..
Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred
Bit 8: Analog watchdog 2 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD2TR and ADC_AWD2TR registers. It is cleared by software programming it it..
Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred
Bit 9: Analog watchdog 3 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD3TR and ADC_AWD3TR registers. It is cleared by software by programming it to 1..
Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred
Bit 11: End Of Calibration flag This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it..
Allowed values:
0: NotComplete: Calibration is not complete
1: Complete: Calibration complete
Bit 13: Channel Configuration Ready flag This flag bit is set by hardware when the channel configuration is applied after programming to ADC_CHSELR register or changing CHSELRMOD or SCANDIR. It is cleared by software by programming it to it. Note: When the software configures the channels (by programming ADC_CHSELR or changing CHSELRMOD or SCANDIR), it must wait until the CCRDY flag rises before configuring again or starting conversions, otherwise the new configuration (or the START bit) is ignored. Once the flag is asserted, if the software needs to configure again the channels, it must clear the CCRDY flag before proceeding with a new configuration..
Allowed values:
0: NotComplete: Channel configuration update not applied
1: Complete: Channel configuration update is applied
ADC interrupt enable register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
10/10 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CCRDYIE
rw |
EOCALIE
rw |
AWD3IE
rw |
AWD2IE
rw |
AWD1IE
rw |
OVRIE
rw |
EOSIE
rw |
EOCIE
rw |
EOSMPIE
rw |
ADRDYIE
rw |
Bit 0: ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0: Disabled: ADRDY interrupt disabled
1: Enabled: ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.
Bit 1: End of sampling flag interrupt enable This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0: Disabled: EOSMP interrupt disabled
1: Enabled: EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.
Bit 2: End of conversion interrupt enable This bit is set and cleared by software to enable/disable the end of conversion interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0: Disabled: EOC interrupt disabled
1: Enabled: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.
Bit 3: End of conversion sequence interrupt enable This bit is set and cleared by software to enable/disable the end of sequence of conversions interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0: Disabled: EOS interrupt disabled
1: Enabled: EOS interrupt enabled. An interrupt is generated when the EOS bit is set.
Bit 4: Overrun interrupt enable This bit is set and cleared by software to enable/disable the overrun interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0: Disabled: Overrun interrupt disabled
1: Enabled: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.
Bit 7: Analog watchdog 1 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled
Bit 8: Analog watchdog 2 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled
Bit 9: Analog watchdog 3 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled
Bit 11: End of calibration interrupt enable This bit is set and cleared by software to enable/disable the end of calibration interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0: Disabled: End of calibration interrupt disabled
1: Enabled: End of calibration interrupt enabled
Bit 13: Channel Configuration Ready Interrupt enable This bit is set and cleared by software to enable/disable the channel configuration ready interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0: Disabled: Channel configuration ready interrupt disabled
1: Enabled: Channel configuration ready interrupt enabled
ADC control register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
6/6 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADCAL
rw |
ADVREGEN
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADSTP
rw |
ADSTART
rw |
ADDIS
rw |
ADEN
rw |
Bit 0: ADC enable command This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the ADRDY flag has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCALÂ =Â 0, ADSTPÂ =Â 0, ADSTARTÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0).
Allowed values:
0: Disabled: ADC disabled
1: Enabled: ADC enabled
Bit 1: ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: Setting ADDIS to '1â is only effective when ADENÂ =Â 1 and ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
Allowed values:
0: NotDisabling: No disable command active
1: Disabling: ADC disabling
Bit 2: ADC start conversion command This bit is set by software to start ADC conversion. Depending on the EXTEN [1:0] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: In single conversion mode (CONTÂ =Â 0, DISCENÂ =Â 0), when software trigger is selected (EXTENÂ =Â 00): at the assertion of the end of Conversion Sequence (EOS) flag. In discontinuous conversion mode(CONTÂ =Â 0, DISCENÂ =Â 1), when the software trigger is selected (EXTENÂ =Â 00): at the assertion of the end of Conversion (EOC) flag. In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is cleared by hardware. Note: The software is allowed to set ADSTART only when ADENÂ =Â 1 and ADDISÂ =Â 0 (ADC is enabled and there is no pending request to disable the ADC). After writing to ADC_CHSELR register or changing CHSELRMOD or SCANDIRW, it is mandatory to wait until CCRDY flag is asserted before setting ADSTART, otherwise, the value written to ADSTART is ignored..
Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting
Bit 4: ADC stop conversion command This bit is set by software to stop and discard an ongoing conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to accept a new start conversion command. Note: Setting ADSTP to '1â is only effective when ADSTARTÂ =Â 1 and ADDISÂ =Â 0 (ADC is enabled and may be converting and there is no pending request to disable the ADC).
Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion
Bit 28: ADC Voltage Regulator Enable This bit is set by software, to enable the ADC internal voltage regulator. The voltage regulator output is available after tADCVREG_SETUP. It is cleared by software to disable the voltage regulator. It can be cleared only if ADEN is et to 0. Note: The software is allowed to program this bit field only when the ADC is disabled (ADCALÂ =Â 0, ADSTARTÂ =Â 0, ADSTPÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0)..
Allowed values:
0: Disabled: ADC voltage regulator disabled
1: Enabled: ADC voltage regulator enabled
Bit 31: ADC calibration This bit is set by software to start the calibration of the ADC. It is cleared by hardware after calibration is complete. Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCALÂ =Â 0, ADSTARTÂ =Â 0, ADSTPÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0). The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADENÂ =Â 1 and ADSTARTÂ =Â 0 (ADC enabled and no conversion is ongoing)..
Allowed values:
0: NotCalibrating: ADC calibration either not yet performed or completed
1: Calibrating: ADC calibration in progress
ADC configuration register 1
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AWD1CH
rw |
AWD1EN
rw |
AWD1SGL
rw |
CHSELRMOD
rw |
DISCEN
rw |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTOFF
rw |
WAIT
rw |
CONT
rw |
OVRMOD
rw |
EXTEN
rw |
EXTSEL
rw |
ALIGN
rw |
RES
rw |
SCANDIR
rw |
DMACFG
rw |
DMAEN
rw |
Bit 0: Direct memory access enable This bit is set and cleared by software to enable the generation of DMA requests. This allows the DMA controller to be used to manage automatically the converted data. For more details, refer to . Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled
Bit 1: Direct memory access configuration This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN = 1. For more details, refer to page 391 Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0: OneShot: DMA one shot mode selected
1: Circular: DMA circular mode selected
Bit 2: Scan sequence direction This bit is set and cleared by software to select the direction in which the channels is scanned in the sequence. It is effective only if CHSELMOD bit is cleared to 0. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0: Upward: Upward scan (from CHSEL0 to CHSEL17)
1: Backward: Backward scan (from CHSEL17 to CHSEL0)
Bits 3-4: Data resolution These bits are written by software to select the resolution of the conversion. Note: The software is allowed to write these bits only when ADENÂ =Â 0..
Allowed values:
0: Bits12: 12 bits
1: Bits10: 10 bits
2: Bits8: 8 bits
3: Bits6: 6 bits
Bit 5: Data alignment This bit is set and cleared by software to select right or left alignment. Refer to Data alignment and resolution (oversampling disabled: OVSE = 0) on page 389 Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0: Right: Right alignment
1: Left: Left alignment
Bits 6-8: External trigger selection These bits select the external event used to trigger the start of conversion (refer to External triggers for details): Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0: TIM1_TRGO: Timer 1 TRGO event
1: TIM1_CC4: Timer 1 CC4 event
2: TIM2_TRGO: Timer 2 TRGO event
3: TIM2_CH4: Timer 2 CH4 event
5: TIM2_CH3: Timer 2 CH3 event
7: EXTI_LINE11: EXTI line 11 event
Bits 10-11: External trigger enable and polarity selection These bits are set and cleared by software to select the external trigger polarity and enable the trigger. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0: Disabled: Hardware trigger detection disabled
1: RisingEdge: Hardware trigger detection on the rising edge
2: FallingEdge: Hardware trigger detection on the falling edge
3: BothEdges: Hardware trigger detection on both the rising and falling edges
Bit 12: Overrun management mode This bit is set and cleared by software and configure the way data overruns are managed. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0: Preserve: ADC_DR register is preserved with the old data when an overrun is detected
1: Overwrite: ADC_DR register is overwritten with the last conversion result when an overrun is detected
Bit 13: Single / continuous conversion mode This bit is set and cleared by software. If it is set, conversion takes place continuously until it is cleared. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCENÂ =Â 1 and CONTÂ =Â 1. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode
Bit 14: Wait conversion mode This bit is set and cleared by software to enable/disable wait conversion mode.. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0: Disabled: Wait conversion mode off
1: Enabled: Wait conversion mode on
Bit 15: Auto-off mode This bit is set and cleared by software to enable/disable auto-off mode.. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0: Disabled: Auto-off mode disabled
1: Enabled: Auto-off mode enabled
Bit 16: Discontinuous mode This bit is set and cleared by software to enable/disable discontinuous mode. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCENÂ =Â 1 and CONTÂ =Â 1. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0: Disabled: Discontinuous mode disabled
1: Enabled: Discontinuous mode enabled
Bit 21: Mode selection of the ADC_CHSELR register This bit is set and cleared by software to control the ADC_CHSELR feature: Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0: BitPerInput: Each bit of the ADC_CHSELR register enables an input
1: Sequence: ADC_CHSELR register is able to sequence up to 8 channels
Bit 22: Enable the watchdog on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWDCH[4:0] bits or on all the channels Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0: AllChannels: Analog watchdog 1 enabled on all channels
1: SingleChannel: Analog watchdog 1 enabled on a single channel
Bit 23: Analog watchdog enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0: Disabled: Analog watchdog 1 disabled
1: Enabled: Analog watchdog 1 enabled
Bits 26-30: Analog watchdog channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. ..... Others: Reserved Note: The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR register. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values: 0x0-0x11
ADC configuration register 2
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
6/6 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CKMODE
rw |
LFTRIG
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TOVS
rw |
OVSS
rw |
OVSR
rw |
OVSE
rw |
Bit 0: Oversampler Enable This bit is set and cleared by software. Note: Software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: Disabled: Oversampler disabled
1: Enabled: Oversampler enabled
Bits 2-4: Oversampling ratio This bit filed defines the number of oversampling ratio. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: Mul2: 2x
1: Mul4: 4x
2: Mul8: 8x
3: Mul16: 16x
4: Mul32: 32x
5: Mul64: 64x
6: Mul128: 128x
7: Mul256: 256x
Bits 5-8: Oversampling shift This bit is set and cleared by software. Others: Reserved Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NoShift: No shift
1: Shift1: Shift 1-bit
2: Shift2: Shift 2-bits
3: Shift3: Shift 3-bits
4: Shift4: Shift 4-bits
5: Shift5: Shift 5-bits
6: Shift6: Shift 6-bits
7: Shift7: Shift 7-bits
8: Shift8: Shift 8-bits
Bit 9: Triggered Oversampling This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: TriggerAll: All oversampled conversions for a channel are done consecutively after a trigger
1: TriggerEach: Each oversampled conversion for a channel needs a trigger
Bit 29: Low frequency trigger mode enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0: Disabled: Low Frequency Trigger Mode disabled
1: Enabled: Low Frequency Trigger Mode enabled
Bits 30-31: ADC clock mode These bits are set and cleared by software to define how the analog ADC is clocked: In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADC is disabled (ADCALÂ =Â 0, ADSTARTÂ =Â 0, ADSTPÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0)..
Allowed values:
0: ADCLK: ADCCLK (Asynchronous clock mode)
1: PCLK_Div2: PCLK/2 (Synchronous clock mode)
2: PCLK_Div4: PCLK/4 (Synchronous clock mode)
3: PCLK: PCLK (Synchronous clock mode)
ADC sampling time register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
21/21 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SMPSEL18
rw |
SMPSEL17
rw |
SMPSEL16
rw |
SMPSEL15
rw |
SMPSEL14
rw |
SMPSEL13
rw |
SMPSEL12
rw |
SMPSEL11
rw |
SMPSEL10
rw |
SMPSEL9
rw |
SMPSEL8
rw |
|||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SMPSEL7
rw |
SMPSEL6
rw |
SMPSEL5
rw |
SMPSEL4
rw |
SMPSEL3
rw |
SMPSEL2
rw |
SMPSEL1
rw |
SMPSEL0
rw |
SMP2
rw |
SMP1
rw |
Bits 0-2: Sampling time selection 1 These bits are written by software to select the sampling time that applies to all channels. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles3_5: 3.5 ADC clock cycles
2: Cycles7_5: 7.5 ADC clock cycles
3: Cycles12_5: 12.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles39_5: 39.5 ADC clock cycles
6: Cycles79_5: 79.5 ADC clock cycles
7: Cycles160_5: 160.5 ADC clock cycles
Bits 4-6: Sampling time selection 2 These bits are written by software to select the sampling time that applies to all channels. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles3_5: 3.5 ADC clock cycles
2: Cycles7_5: 7.5 ADC clock cycles
3: Cycles12_5: 12.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles39_5: 39.5 ADC clock cycles
6: Cycles79_5: 79.5 ADC clock cycles
7: Cycles160_5: 160.5 ADC clock cycles
Bit 8: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register
Bit 9: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register
Bit 10: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register
Bit 11: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register
Bit 12: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register
Bit 13: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register
Bit 14: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register
Bit 15: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register
Bit 16: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register
Bit 17: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register
Bit 18: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register
Bit 19: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register
Bit 20: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register
Bit 21: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register
Bit 22: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register
Bit 23: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register
Bit 24: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register
Bit 25: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register
Bit 26: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: Smp1: Sampling time of CHANNELx use the setting of SMP1 register
1: Smp2: Sampling time of CHANNELx use the setting of SMP2 register
ADC watchdog threshold register
Offset: 0x20, size: 32, reset: 0x0FFF0000, access: read-write
2/2 fields covered.
Bits 0-11: Analog watchdog 1 lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 395..
Allowed values: 0x0-0xfff
Bits 16-27: Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 395..
Allowed values: 0x0-0xfff
ADC watchdog threshold register
Offset: 0x24, size: 32, reset: 0x0FFF0000, access: read-write
2/2 fields covered.
Bits 0-11: Analog watchdog 2 lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 395..
Allowed values: 0x0-0xfff
Bits 16-27: Analog watchdog 2 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 395..
Allowed values: 0x0-0xfff
ADC channel selection register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
19/19 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHSEL18
rw |
CHSEL17
rw |
CHSEL16
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CHSEL15
rw |
CHSEL14
rw |
CHSEL13
rw |
CHSEL12
rw |
CHSEL11
rw |
CHSEL10
rw |
CHSEL9
rw |
CHSEL8
rw |
CHSEL7
rw |
CHSEL6
rw |
CHSEL5
rw |
CHSEL4
rw |
CHSEL3
rw |
CHSEL2
rw |
CHSEL1
rw |
CHSEL0
rw |
Bit 0: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion
Bit 1: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion
Bit 2: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion
Bit 3: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion
Bit 4: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion
Bit 5: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion
Bit 6: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion
Bit 7: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion
Bit 8: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion
Bit 9: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion
Bit 10: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion
Bit 11: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion
Bit 12: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion
Bit 13: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion
Bit 14: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion
Bit 15: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion
Bit 16: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion
Bit 17: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion
Bit 18: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion
ADC channel selection register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SQ8
rw |
SQ7
rw |
SQ6
rw |
SQ5
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SQ4
rw |
SQ3
rw |
SQ2
rw |
SQ1
rw |
Bits 0-3: 1st conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: Ch0: Channel 0 selected for the Nth conversion
1: Ch1: Channel 1 selected for the Nth conversion
2: Ch2: Channel 2 selected for the Nth conversion
3: Ch3: Channel 3 selected for the Nth conversion
4: Ch4: Channel 4 selected for the Nth conversion
5: Ch5: Channel 5 selected for the Nth conversion
6: Ch6: Channel 6 selected for the Nth conversion
7: Ch7: Channel 7 selected for the Nth conversion
8: Ch8: Channel 8 selected for the Nth conversion
9: Ch9: Channel 9 selected for the Nth conversion
10: Ch10: Channel 10 selected for the Nth conversion
11: Ch11: Channel 11 selected for the Nth conversion
12: Ch12: Channel 12 selected for the Nth conversion
13: Ch13: Channel 13 selected for the Nth conversion
14: Ch14: Channel 14 selected for the Nth conversion
15: EOS: End of sequence
Bits 4-7: 2nd conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: Ch0: Channel 0 selected for the Nth conversion
1: Ch1: Channel 1 selected for the Nth conversion
2: Ch2: Channel 2 selected for the Nth conversion
3: Ch3: Channel 3 selected for the Nth conversion
4: Ch4: Channel 4 selected for the Nth conversion
5: Ch5: Channel 5 selected for the Nth conversion
6: Ch6: Channel 6 selected for the Nth conversion
7: Ch7: Channel 7 selected for the Nth conversion
8: Ch8: Channel 8 selected for the Nth conversion
9: Ch9: Channel 9 selected for the Nth conversion
10: Ch10: Channel 10 selected for the Nth conversion
11: Ch11: Channel 11 selected for the Nth conversion
12: Ch12: Channel 12 selected for the Nth conversion
13: Ch13: Channel 13 selected for the Nth conversion
14: Ch14: Channel 14 selected for the Nth conversion
15: EOS: End of sequence
Bits 8-11: 3rd conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: Ch0: Channel 0 selected for the Nth conversion
1: Ch1: Channel 1 selected for the Nth conversion
2: Ch2: Channel 2 selected for the Nth conversion
3: Ch3: Channel 3 selected for the Nth conversion
4: Ch4: Channel 4 selected for the Nth conversion
5: Ch5: Channel 5 selected for the Nth conversion
6: Ch6: Channel 6 selected for the Nth conversion
7: Ch7: Channel 7 selected for the Nth conversion
8: Ch8: Channel 8 selected for the Nth conversion
9: Ch9: Channel 9 selected for the Nth conversion
10: Ch10: Channel 10 selected for the Nth conversion
11: Ch11: Channel 11 selected for the Nth conversion
12: Ch12: Channel 12 selected for the Nth conversion
13: Ch13: Channel 13 selected for the Nth conversion
14: Ch14: Channel 14 selected for the Nth conversion
15: EOS: End of sequence
Bits 12-15: 4th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: Ch0: Channel 0 selected for the Nth conversion
1: Ch1: Channel 1 selected for the Nth conversion
2: Ch2: Channel 2 selected for the Nth conversion
3: Ch3: Channel 3 selected for the Nth conversion
4: Ch4: Channel 4 selected for the Nth conversion
5: Ch5: Channel 5 selected for the Nth conversion
6: Ch6: Channel 6 selected for the Nth conversion
7: Ch7: Channel 7 selected for the Nth conversion
8: Ch8: Channel 8 selected for the Nth conversion
9: Ch9: Channel 9 selected for the Nth conversion
10: Ch10: Channel 10 selected for the Nth conversion
11: Ch11: Channel 11 selected for the Nth conversion
12: Ch12: Channel 12 selected for the Nth conversion
13: Ch13: Channel 13 selected for the Nth conversion
14: Ch14: Channel 14 selected for the Nth conversion
15: EOS: End of sequence
Bits 16-19: 5th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: Ch0: Channel 0 selected for the Nth conversion
1: Ch1: Channel 1 selected for the Nth conversion
2: Ch2: Channel 2 selected for the Nth conversion
3: Ch3: Channel 3 selected for the Nth conversion
4: Ch4: Channel 4 selected for the Nth conversion
5: Ch5: Channel 5 selected for the Nth conversion
6: Ch6: Channel 6 selected for the Nth conversion
7: Ch7: Channel 7 selected for the Nth conversion
8: Ch8: Channel 8 selected for the Nth conversion
9: Ch9: Channel 9 selected for the Nth conversion
10: Ch10: Channel 10 selected for the Nth conversion
11: Ch11: Channel 11 selected for the Nth conversion
12: Ch12: Channel 12 selected for the Nth conversion
13: Ch13: Channel 13 selected for the Nth conversion
14: Ch14: Channel 14 selected for the Nth conversion
15: EOS: End of sequence
Bits 20-23: 6th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: Ch0: Channel 0 selected for the Nth conversion
1: Ch1: Channel 1 selected for the Nth conversion
2: Ch2: Channel 2 selected for the Nth conversion
3: Ch3: Channel 3 selected for the Nth conversion
4: Ch4: Channel 4 selected for the Nth conversion
5: Ch5: Channel 5 selected for the Nth conversion
6: Ch6: Channel 6 selected for the Nth conversion
7: Ch7: Channel 7 selected for the Nth conversion
8: Ch8: Channel 8 selected for the Nth conversion
9: Ch9: Channel 9 selected for the Nth conversion
10: Ch10: Channel 10 selected for the Nth conversion
11: Ch11: Channel 11 selected for the Nth conversion
12: Ch12: Channel 12 selected for the Nth conversion
13: Ch13: Channel 13 selected for the Nth conversion
14: Ch14: Channel 14 selected for the Nth conversion
15: EOS: End of sequence
Bits 24-27: 7th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: Ch0: Channel 0 selected for the Nth conversion
1: Ch1: Channel 1 selected for the Nth conversion
2: Ch2: Channel 2 selected for the Nth conversion
3: Ch3: Channel 3 selected for the Nth conversion
4: Ch4: Channel 4 selected for the Nth conversion
5: Ch5: Channel 5 selected for the Nth conversion
6: Ch6: Channel 6 selected for the Nth conversion
7: Ch7: Channel 7 selected for the Nth conversion
8: Ch8: Channel 8 selected for the Nth conversion
9: Ch9: Channel 9 selected for the Nth conversion
10: Ch10: Channel 10 selected for the Nth conversion
11: Ch11: Channel 11 selected for the Nth conversion
12: Ch12: Channel 12 selected for the Nth conversion
13: Ch13: Channel 13 selected for the Nth conversion
14: Ch14: Channel 14 selected for the Nth conversion
15: EOS: End of sequence
Bits 28-31: 8th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates the end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. ... Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: Ch0: Channel 0 selected for the Nth conversion
1: Ch1: Channel 1 selected for the Nth conversion
2: Ch2: Channel 2 selected for the Nth conversion
3: Ch3: Channel 3 selected for the Nth conversion
4: Ch4: Channel 4 selected for the Nth conversion
5: Ch5: Channel 5 selected for the Nth conversion
6: Ch6: Channel 6 selected for the Nth conversion
7: Ch7: Channel 7 selected for the Nth conversion
8: Ch8: Channel 8 selected for the Nth conversion
9: Ch9: Channel 9 selected for the Nth conversion
10: Ch10: Channel 10 selected for the Nth conversion
11: Ch11: Channel 11 selected for the Nth conversion
12: Ch12: Channel 12 selected for the Nth conversion
13: Ch13: Channel 13 selected for the Nth conversion
14: Ch14: Channel 14 selected for the Nth conversion
15: EOS: End of sequence
ADC watchdog threshold register
Offset: 0x2c, size: 32, reset: 0x0FFF0000, access: read-write
2/2 fields covered.
Bits 0-11: Analog watchdog 3lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 395..
Allowed values: 0x0-0xfff
Bits 16-27: Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 395..
Allowed values: 0x0-0xfff
ADC data register
Offset: 0x40, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
r |
Bits 0-15: Converted data These bits are read-only. They contain the conversion result from the last converted channel. The data are left- or right-aligned as shown in OVSE = 0) on page 389. Just after a calibration is complete, DATA[6:0] contains the calibration factor..
Allowed values: 0x0-0xffff
ADC Analog Watchdog 2 Configuration register
Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write
19/19 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AWD2CH18
rw |
AWD2CH17
rw |
AWD2CH16
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AWD2CH15
rw |
AWD2CH14
rw |
AWD2CH13
rw |
AWD2CH12
rw |
AWD2CH11
rw |
AWD2CH10
rw |
AWD2CH9
rw |
AWD2CH8
rw |
AWD2CH7
rw |
AWD2CH6
rw |
AWD2CH5
rw |
AWD2CH4
rw |
AWD2CH3
rw |
AWD2CH2
rw |
AWD2CH1
rw |
AWD2CH0
rw |
Bit 0: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2
Bit 1: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2
Bit 2: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2
Bit 3: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2
Bit 4: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2
Bit 5: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2
Bit 6: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2
Bit 7: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2
Bit 8: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2
Bit 9: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2
Bit 10: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2
Bit 11: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2
Bit 12: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2
Bit 13: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2
Bit 14: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2
Bit 15: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2
Bit 16: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2
Bit 17: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2
Bit 18: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD2
1: Monitored: ADC analog channel-x is monitored by AWD2
ADC Analog Watchdog 3 Configuration register
Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write
19/19 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AWD3CH18
rw |
AWD3CH17
rw |
AWD3CH16
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AWD3CH15
rw |
AWD3CH14
rw |
AWD3CH13
rw |
AWD3CH12
rw |
AWD3CH11
rw |
AWD3CH10
rw |
AWD3CH9
rw |
AWD3CH8
rw |
AWD3CH7
rw |
AWD3CH6
rw |
AWD3CH5
rw |
AWD3CH4
rw |
AWD3CH3
rw |
AWD3CH2
rw |
AWD3CH1
rw |
AWD3CH0
rw |
Bit 0: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3
Bit 1: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3
Bit 2: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3
Bit 3: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3
Bit 4: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3
Bit 5: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3
Bit 6: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3
Bit 7: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3
Bit 8: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3
Bit 9: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3
Bit 10: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3
Bit 11: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3
Bit 12: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3
Bit 13: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3
Bit 14: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3
Bit 15: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3
Bit 16: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3
Bit 17: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3
Bit 18: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..
Allowed values:
0: NotMonitored: ADC analog channel-x is not monitored by AWD3
1: Monitored: ADC analog channel-x is monitored by AWD3
ADC Calibration factor
Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CALFACT
rw |
Bits 0-6: Calibration factor These bits are written by hardware or by software. Once a calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new calibration is launched. Just after a calibration is complete, DATA[6:0] contains the calibration factor. Note: Software can write these bits only when ADEN=1 (ADC is enabled and no calibration is ongoing and no conversion is ongoing). Refer to SQ8[3:0] for a definition of channel selection..
Allowed values: 0x0-0x7f
ADC common configuration register
Offset: 0x308, size: 32, reset: 0x00000000, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VBATEN
rw |
TSEN
rw |
VREFEN
rw |
PRESC
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits 18-21: ADC prescaler Set and cleared by software to select the frequency of the clock to the ADC. Other: Reserved Note: Software is allowed to write these bits only when the ADC is disabled (ADCALÂ =Â 0, ADSTARTÂ =Â 0, ADSTPÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0)..
Allowed values:
0: Div1: Input ADC clock not divided
1: Div2: Input ADC clock divided by 2
2: Div4: Input ADC clock divided by 4
3: Div6: Input ADC clock divided by 6
4: Div8: Input ADC clock divided by 8
5: Div10: Input ADC clock divided by 10
6: Div12: Input ADC clock divided by 12
7: Div16: Input ADC clock divided by 16
8: Div32: Input ADC clock divided by 32
9: Div64: Input ADC clock divided by 64
10: Div128: Input ADC clock divided by 128
11: Div256: Input ADC clock divided by 256
Bit 22: VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT. Note: Software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: Disabled: VREFINT disabled
1: Enabled: VREFINT enabled
Bit 23: Temperature sensor enable This bit is set and cleared by software to enable/disable the temperature sensor. Note: Software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0: Disabled: Temperature sensor disabled
1: Enabled: Temperature sensor enabled
Bit 24: VBAT enable This bit is set and cleared by software to enable/disable the VBAT channel. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
Allowed values:
0: Disabled: VBAT channel disabled
1: Enabled: VBAT channel enabled
0x40023000: Cyclic redundancy check calculation unit
0/8 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | DR | ||||||||||||||||||||||||||||||||
0x4 | IDR | ||||||||||||||||||||||||||||||||
0x8 | CR | ||||||||||||||||||||||||||||||||
0x10 | INIT | ||||||||||||||||||||||||||||||||
0x14 | POL |
Independent data register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Control register
Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified
0/4 fields covered.
Bit 0: RESET bit.
Bits 3-4: Polynomial size These bits control the size of the polynomial..
Bits 5-6: Reverse input data These bits control the reversal of the bit order of the input data.
Bit 7: Reverse output data This bit controls the reversal of the bit order of the output data..
0x40015800: Debug support
2/17 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | IDCODE | ||||||||||||||||||||||||||||||||
0x4 | CR | ||||||||||||||||||||||||||||||||
0x8 | APB_FZ1 | ||||||||||||||||||||||||||||||||
0xc | APB_FZ2 |
MCU Device ID Code Register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-only
2/2 fields covered.
DBG configuration register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DBG_STANDBY
rw |
DBG_STOP
rw |
DBG APB freeze register 1
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
0/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DBG_I2C2_SMBUS_TIMEOUT
rw |
DBG_I2C1_SMBUS_TIMEOUT
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DBG_IWDG_STOP
rw |
DBG_WWDG_STOP
rw |
DBG_RTC_STOP
rw |
DBG_TIM7_STOP
rw |
DBG_TIM6_STOP
rw |
DBG_TIM3_STOP
rw |
Bit 1: Clocking of TIM3 counter when the core is halted This bit enables/disables the clock to the counter of TIM3 when the core is halted:.
Bit 4: Clocking of TIM6 counter when the core is halted This bit enables/disables the clock to the counter of TIM6 when the core is halted:.
Bit 5: Clocking of TIM7 counter when the core is halted. This bit enables/disables the clock to the counter of ITIM7 when the core is halted:.
Bit 10: Clocking of RTC counter when the core is halted This bit enables/disables the clock to the counter of RTC when the core is halted:.
Bit 11: Clocking of WWDG counter when the core is halted This bit enables/disables the clock to the counter of WWDG when the core is halted:.
Bit 12: Clocking of IWDG counter when the core is halted This bit enables/disables the clock to the counter of IWDG when the core is halted:.
Bit 21: SMBUS timeout when core is halted.
Bit 22: SMBUS timeout when core is halted.
DBG APB freeze register 2
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
0/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DBG_TIM17_STOP
rw |
DBG_TIM16_STOP
rw |
DBG_TIM15_STOP
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DBG_TIM14_STOP
rw |
DBG_TIM1_STOP
rw |
Bit 11: Clocking of TIM1 counter when the core is halted This bit enables/disables the clock to the counter of TIM1 when the core is halted:.
Bit 15: Clocking of TIM14 counter when the core is halted This bit enables/disables the clock to the counter of TIM14 when the core is halted:.
Bit 16: Clocking of TIM15 counter when the core is halted This bit enables/disables the clock to the counter of TIM15 when the core is halted: Only available on STM32G071xx and STM32G081xx, reserved on STM32G031xx and STM32G041xx..
Bit 17: Clocking of TIM16 counter when the core is halted This bit enables/disables the clock to the counter of TIM16 when the core is halted:.
Bit 18: Clocking of TIM17 counter when the core is halted This bit enables/disables the clock to the counter of TIM17 when the core is halted:.
0x40020800: DMAMUX
16/136 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CCR[0] | ||||||||||||||||||||||||||||||||
0x4 | CCR[1] | ||||||||||||||||||||||||||||||||
0x8 | CCR[2] | ||||||||||||||||||||||||||||||||
0xc | CCR[3] | ||||||||||||||||||||||||||||||||
0x10 | CCR[4] | ||||||||||||||||||||||||||||||||
0x14 | CCR[5] | ||||||||||||||||||||||||||||||||
0x18 | CCR[6] | ||||||||||||||||||||||||||||||||
0x1c | CCR[7] | ||||||||||||||||||||||||||||||||
0x20 | CCR[8] | ||||||||||||||||||||||||||||||||
0x24 | CCR[9] | ||||||||||||||||||||||||||||||||
0x28 | CCR[10] | ||||||||||||||||||||||||||||||||
0x2c | CCR[11] | ||||||||||||||||||||||||||||||||
0x80 | CSR | ||||||||||||||||||||||||||||||||
0x84 | CFR | ||||||||||||||||||||||||||||||||
0x100 | RGCR[0] | ||||||||||||||||||||||||||||||||
0x104 | RGCR[1] | ||||||||||||||||||||||||||||||||
0x108 | RGCR[2] | ||||||||||||||||||||||||||||||||
0x10c | RGCR[3] | ||||||||||||||||||||||||||||||||
0x140 | RGSR | ||||||||||||||||||||||||||||||||
0x144 | RGCFR |
DMA Multiplexer Channel 0 Control register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
0/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SYNC_ID
rw |
NBREQ
rw |
SPOL
rw |
SE
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EGE
rw |
SOIE
rw |
DMAREQ_ID
rw |
Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..
Bit 8: Synchronization overrun interrupt enable.
Bit 9: Event generation enable.
Bit 16: Synchronization enable.
Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.
Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..
Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources STM32G0)..
DMA Multiplexer Channel 1 Control register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
0/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SYNC_ID
rw |
NBREQ
rw |
SPOL
rw |
SE
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EGE
rw |
SOIE
rw |
DMAREQ_ID
rw |
Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..
Bit 8: Synchronization overrun interrupt enable.
Bit 9: Event generation enable.
Bit 16: Synchronization enable.
Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.
Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..
Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources STM32G0)..
DMA Multiplexer Channel 2 Control register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
0/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SYNC_ID
rw |
NBREQ
rw |
SPOL
rw |
SE
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EGE
rw |
SOIE
rw |
DMAREQ_ID
rw |
Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..
Bit 8: Synchronization overrun interrupt enable.
Bit 9: Event generation enable.
Bit 16: Synchronization enable.
Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.
Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..
Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources STM32G0)..
DMA Multiplexer Channel 3 Control register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
0/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SYNC_ID
rw |
NBREQ
rw |
SPOL
rw |
SE
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EGE
rw |
SOIE
rw |
DMAREQ_ID
rw |
Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..
Bit 8: Synchronization overrun interrupt enable.
Bit 9: Event generation enable.
Bit 16: Synchronization enable.
Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.
Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..
Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources STM32G0)..
DMA Multiplexer Channel 4 Control register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
0/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SYNC_ID
rw |
NBREQ
rw |
SPOL
rw |
SE
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EGE
rw |
SOIE
rw |
DMAREQ_ID
rw |
Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..
Bit 8: Synchronization overrun interrupt enable.
Bit 9: Event generation enable.
Bit 16: Synchronization enable.
Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.
Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..
Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources STM32G0)..
DMA Multiplexer Channel 5 Control register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
0/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SYNC_ID
rw |
NBREQ
rw |
SPOL
rw |
SE
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EGE
rw |
SOIE
rw |
DMAREQ_ID
rw |
Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..
Bit 8: Synchronization overrun interrupt enable.
Bit 9: Event generation enable.
Bit 16: Synchronization enable.
Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.
Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..
Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources STM32G0)..
DMA Multiplexer Channel 6 Control register
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
0/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SYNC_ID
rw |
NBREQ
rw |
SPOL
rw |
SE
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EGE
rw |
SOIE
rw |
DMAREQ_ID
rw |
Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..
Bit 8: Synchronization overrun interrupt enable.
Bit 9: Event generation enable.
Bit 16: Synchronization enable.
Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.
Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..
Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources STM32G0)..
DMA Multiplexer Channel 7 Control register
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
0/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SYNC_ID
rw |
NBREQ
rw |
SPOL
rw |
SE
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EGE
rw |
SOIE
rw |
DMAREQ_ID
rw |
Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..
Bit 8: Synchronization overrun interrupt enable.
Bit 9: Event generation enable.
Bit 16: Synchronization enable.
Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.
Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..
Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources STM32G0)..
DMA Multiplexer Channel 8 Control register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
0/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SYNC_ID
rw |
NBREQ
rw |
SPOL
rw |
SE
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EGE
rw |
SOIE
rw |
DMAREQ_ID
rw |
Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..
Bit 8: Synchronization overrun interrupt enable.
Bit 9: Event generation enable.
Bit 16: Synchronization enable.
Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.
Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..
Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources STM32G0)..
DMA Multiplexer Channel 9 Control register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
0/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SYNC_ID
rw |
NBREQ
rw |
SPOL
rw |
SE
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EGE
rw |
SOIE
rw |
DMAREQ_ID
rw |
Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..
Bit 8: Synchronization overrun interrupt enable.
Bit 9: Event generation enable.
Bit 16: Synchronization enable.
Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.
Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..
Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources STM32G0)..
DMA Multiplexer Channel 10 Control register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
0/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SYNC_ID
rw |
NBREQ
rw |
SPOL
rw |
SE
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EGE
rw |
SOIE
rw |
DMAREQ_ID
rw |
Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..
Bit 8: Synchronization overrun interrupt enable.
Bit 9: Event generation enable.
Bit 16: Synchronization enable.
Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.
Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..
Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources STM32G0)..
DMA Multiplexer Channel 11 Control register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
0/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SYNC_ID
rw |
NBREQ
rw |
SPOL
rw |
SE
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EGE
rw |
SOIE
rw |
DMAREQ_ID
rw |
Bits 0-5: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources..
Bit 8: Synchronization overrun interrupt enable.
Bit 9: Event generation enable.
Bit 16: Synchronization enable.
Bits 17-18: Synchronization polarity Defines the edge polarity of the selected synchronization input:.
Bits 19-23: Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low..
Bits 24-28: Synchronization identification Selects the synchronization input (see inputs to resources STM32G0)..
DMAMUX request line multiplexer interrupt channel status register
Offset: 0x80, size: 32, reset: 0x00000000, access: read-only
12/12 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SOF11
r |
SOF10
r |
SOF9
r |
SOF8
r |
SOF7
r |
SOF6
r |
SOF5
r |
SOF4
r |
SOF3
r |
SOF2
r |
SOF1
r |
SOF0
r |
Bit 0: Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register..
Bit 1: Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register..
Bit 2: Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register..
Bit 3: Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register..
Bit 4: Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register..
Bit 5: Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register..
Bit 6: Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register..
Bit 7: Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register..
Bit 8: Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register..
Bit 9: Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register..
Bit 10: Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register..
Bit 11: Synchronization overrun event flag The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ. The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register..
DMAMUX request line multiplexer interrupt clear flag register
Offset: 0x84, size: 32, reset: 0x00000000, access: write-only
0/12 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CSOF11
w |
CSOF10
w |
CSOF9
w |
CSOF8
w |
CSOF7
w |
CSOF6
w |
CSOF5
w |
CSOF4
w |
CSOF3
w |
CSOF2
w |
CSOF1
w |
CSOF0
w |
Bit 0: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register..
Bit 1: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register..
Bit 2: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register..
Bit 3: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register..
Bit 4: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register..
Bit 5: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register..
Bit 6: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register..
Bit 7: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register..
Bit 8: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register..
Bit 9: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register..
Bit 10: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register..
Bit 11: Clear synchronization overrun event flag Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register..
DMAMUX request generator channel x configuration register
Offset: 0x100, size: 32, reset: 0x00000000, access: read-write
0/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GNBREQ
rw |
GPOL
rw |
GE
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OIE
rw |
SIG_ID
rw |
Bits 0-4: Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator.
Bit 8: Trigger overrun interrupt enable.
Bit 16: DMA request generator channel x enable.
Bits 17-18: DMA request generator trigger polarity Defines the edge polarity of the selected trigger input.
Bits 19-23: Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field shall only be written when GE bit is disabled..
DMAMUX request generator channel x configuration register
Offset: 0x104, size: 32, reset: 0x00000000, access: read-write
0/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GNBREQ
rw |
GPOL
rw |
GE
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OIE
rw |
SIG_ID
rw |
Bits 0-4: Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator.
Bit 8: Trigger overrun interrupt enable.
Bit 16: DMA request generator channel x enable.
Bits 17-18: DMA request generator trigger polarity Defines the edge polarity of the selected trigger input.
Bits 19-23: Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field shall only be written when GE bit is disabled..
DMAMUX request generator channel x configuration register
Offset: 0x108, size: 32, reset: 0x00000000, access: read-write
0/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GNBREQ
rw |
GPOL
rw |
GE
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OIE
rw |
SIG_ID
rw |
Bits 0-4: Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator.
Bit 8: Trigger overrun interrupt enable.
Bit 16: DMA request generator channel x enable.
Bits 17-18: DMA request generator trigger polarity Defines the edge polarity of the selected trigger input.
Bits 19-23: Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field shall only be written when GE bit is disabled..
DMAMUX request generator channel x configuration register
Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write
0/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GNBREQ
rw |
GPOL
rw |
GE
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OIE
rw |
SIG_ID
rw |
Bits 0-4: Signal identification Selects the DMA request trigger input used for the channel x of the DMA request generator.
Bit 8: Trigger overrun interrupt enable.
Bit 16: DMA request generator channel x enable.
Bits 17-18: DMA request generator trigger polarity Defines the edge polarity of the selected trigger input.
Bits 19-23: Number of DMA requests to be generated (minus 1) Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1. Note: This field shall only be written when GE bit is disabled..
DMAMUX request generator interrupt status register
Offset: 0x140, size: 32, reset: 0x00000000, access: read-only
4/4 fields covered.
Bit 0: Trigger overrun event flag The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register..
Bit 1: Trigger overrun event flag The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register..
Bit 2: Trigger overrun event flag The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register..
Bit 3: Trigger overrun event flag The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register..
DMAMUX request generator interrupt clear flag register
Offset: 0x144, size: 32, reset: 0x00000000, access: write-only
0/4 fields covered.
Bit 0: Clear trigger overrun event flag Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register..
Bit 1: Clear trigger overrun event flag Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register..
Bit 2: Clear trigger overrun event flag Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register..
Bit 3: Clear trigger overrun event flag Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register..
0x50000000: General-purpose I/Os
177/177 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | MODER | ||||||||||||||||||||||||||||||||
0x4 | OTYPER | ||||||||||||||||||||||||||||||||
0x8 | OSPEEDR | ||||||||||||||||||||||||||||||||
0xc | PUPDR | ||||||||||||||||||||||||||||||||
0x10 | IDR | ||||||||||||||||||||||||||||||||
0x14 | ODR | ||||||||||||||||||||||||||||||||
0x18 | BSRR | ||||||||||||||||||||||||||||||||
0x1c | LCKR | ||||||||||||||||||||||||||||||||
0x20 | AFRL | ||||||||||||||||||||||||||||||||
0x24 | AFRH | ||||||||||||||||||||||||||||||||
0x28 | BRR |
GPIO port mode register
Offset: 0x0, size: 32, reset: 0xEBFFFFFF, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MODER[15]
rw |
MODER[14]
rw |
MODER[13]
rw |
MODER[12]
rw |
MODER[11]
rw |
MODER[10]
rw |
MODER[9]
rw |
MODER[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MODER[7]
rw |
MODER[6]
rw |
MODER[5]
rw |
MODER[4]
rw |
MODER[3]
rw |
MODER[2]
rw |
MODER[1]
rw |
MODER[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
GPIO port output type register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OT[15]
rw |
OT[14]
rw |
OT[13]
rw |
OT[12]
rw |
OT[11]
rw |
OT[10]
rw |
OT[9]
rw |
OT[8]
rw |
OT[7]
rw |
OT[6]
rw |
OT[5]
rw |
OT[4]
rw |
OT[3]
rw |
OT[2]
rw |
OT[1]
rw |
OT[0]
rw |
Bit 0: Port x configuration pin 0.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 1: Port x configuration pin 1.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 2: Port x configuration pin 2.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 3: Port x configuration pin 3.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 4: Port x configuration pin 4.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 5: Port x configuration pin 5.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 6: Port x configuration pin 6.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 7: Port x configuration pin 7.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 8: Port x configuration pin 8.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 9: Port x configuration pin 9.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 10: Port x configuration pin 10.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 11: Port x configuration pin 11.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 12: Port x configuration pin 12.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 13: Port x configuration pin 13.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 14: Port x configuration pin 14.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 15: Port x configuration pin 15.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
GPIO port output speed register
Offset: 0x8, size: 32, reset: 0x0C000000, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OSPEEDR[15]
rw |
OSPEEDR[14]
rw |
OSPEEDR[13]
rw |
OSPEEDR[12]
rw |
OSPEEDR[11]
rw |
OSPEEDR[10]
rw |
OSPEEDR[9]
rw |
OSPEEDR[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OSPEEDR[7]
rw |
OSPEEDR[6]
rw |
OSPEEDR[5]
rw |
OSPEEDR[4]
rw |
OSPEEDR[3]
rw |
OSPEEDR[2]
rw |
OSPEEDR[1]
rw |
OSPEEDR[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
GPIO port pull-up/pull-down register
Offset: 0xc, size: 32, reset: 0x24000000, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUPDR[15]
rw |
PUPDR[14]
rw |
PUPDR[13]
rw |
PUPDR[12]
rw |
PUPDR[11]
rw |
PUPDR[10]
rw |
PUPDR[9]
rw |
PUPDR[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PUPDR[7]
rw |
PUPDR[6]
rw |
PUPDR[5]
rw |
PUPDR[4]
rw |
PUPDR[3]
rw |
PUPDR[2]
rw |
PUPDR[1]
rw |
PUPDR[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
GPIO port input data register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-only
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IDR[15]
r |
IDR[14]
r |
IDR[13]
r |
IDR[12]
r |
IDR[11]
r |
IDR[10]
r |
IDR[9]
r |
IDR[8]
r |
IDR[7]
r |
IDR[6]
r |
IDR[5]
r |
IDR[4]
r |
IDR[3]
r |
IDR[2]
r |
IDR[1]
r |
IDR[0]
r |
Bit 0: Port input data pin 0.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 1: Port input data pin 1.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 2: Port input data pin 2.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 3: Port input data pin 3.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 4: Port input data pin 4.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 5: Port input data pin 5.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 6: Port input data pin 6.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 7: Port input data pin 7.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 8: Port input data pin 8.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 9: Port input data pin 9.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 10: Port input data pin 10.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 11: Port input data pin 11.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 12: Port input data pin 12.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 13: Port input data pin 13.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 14: Port input data pin 14.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 15: Port input data pin 15.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
GPIO port output data register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ODR[15]
rw |
ODR[14]
rw |
ODR[13]
rw |
ODR[12]
rw |
ODR[11]
rw |
ODR[10]
rw |
ODR[9]
rw |
ODR[8]
rw |
ODR[7]
rw |
ODR[6]
rw |
ODR[5]
rw |
ODR[4]
rw |
ODR[3]
rw |
ODR[2]
rw |
ODR[1]
rw |
ODR[0]
rw |
Bit 0: Port output data pin 0.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 1: Port output data pin 1.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 2: Port output data pin 2.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 3: Port output data pin 3.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 4: Port output data pin 4.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 5: Port output data pin 5.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 6: Port output data pin 6.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 7: Port output data pin 7.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 8: Port output data pin 8.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 9: Port output data pin 9.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 10: Port output data pin 10.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 11: Port output data pin 11.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 12: Port output data pin 12.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 13: Port output data pin 13.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 14: Port output data pin 14.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 15: Port output data pin 15.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
GPIO port bit set/reset register
Offset: 0x18, size: 32, reset: 0x00000000, access: write-only
32/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BS[15]
w |
BS[14]
w |
BS[13]
w |
BS[12]
w |
BS[11]
w |
BS[10]
w |
BS[9]
w |
BS[8]
w |
BS[7]
w |
BS[6]
w |
BS[5]
w |
BS[4]
w |
BS[3]
w |
BS[2]
w |
BS[1]
w |
BS[0]
w |
Bit 0: Port x set pin 0.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 1: Port x set pin 1.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 2: Port x set pin 2.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 3: Port x set pin 3.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 4: Port x set pin 4.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 5: Port x set pin 5.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 6: Port x set pin 6.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 7: Port x set pin 7.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 8: Port x set pin 8.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 9: Port x set pin 9.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 10: Port x set pin 10.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 11: Port x set pin 11.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 12: Port x set pin 12.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 13: Port x set pin 13.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 14: Port x set pin 14.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 15: Port x set pin 15.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 16: Port x reset pin 0.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 17: Port x reset pin 1.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 18: Port x reset pin 2.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 19: Port x reset pin 3.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 20: Port x reset pin 4.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 21: Port x reset pin 5.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 22: Port x reset pin 6.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 23: Port x reset pin 7.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 24: Port x reset pin 8.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 25: Port x reset pin 9.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 26: Port x reset pin 10.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 27: Port x reset pin 11.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 28: Port x reset pin 12.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 29: Port x reset pin 13.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 30: Port x reset pin 14.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 31: Port x reset pin 15.
Allowed values:
1: Reset: Resets the corresponding ODx bit
GPIO port configuration lock register
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
17/17 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LCKK
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LCK[15]
rw |
LCK[14]
rw |
LCK[13]
rw |
LCK[12]
rw |
LCK[11]
rw |
LCK[10]
rw |
LCK[9]
rw |
LCK[8]
rw |
LCK[7]
rw |
LCK[6]
rw |
LCK[5]
rw |
LCK[4]
rw |
LCK[3]
rw |
LCK[2]
rw |
LCK[1]
rw |
LCK[0]
rw |
Bit 0: Port x lock pin 0.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 1: Port x lock pin 1.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 2: Port x lock pin 2.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 3: Port x lock pin 3.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 4: Port x lock pin 4.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 5: Port x lock pin 5.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 6: Port x lock pin 6.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 7: Port x lock pin 7.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 8: Port x lock pin 8.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 9: Port x lock pin 9.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 10: Port x lock pin 10.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 11: Port x lock pin 11.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 12: Port x lock pin 12.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 13: Port x lock pin 13.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 14: Port x lock pin 14.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 15: Port x lock pin 15.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 16: Port x lock bit y (y= 0..15).
Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active
GPIO alternate function low register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AFR[EL7]
rw |
AFR[EL6]
rw |
AFR[EL5]
rw |
AFR[EL4]
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AFR[EL3]
rw |
AFR[EL2]
rw |
AFR[EL1]
rw |
AFR[EL0]
rw |
Bits 0-3: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 4-7: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 8-11: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 12-15: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 16-19: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 20-23: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 24-27: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 28-31: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
GPIO alternate function high register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AFR[EL15]
rw |
AFR[EL14]
rw |
AFR[EL13]
rw |
AFR[EL12]
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AFR[EL11]
rw |
AFR[EL10]
rw |
AFR[EL9]
rw |
AFR[EL8]
rw |
Bits 0-3: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 4-7: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 8-11: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 12-15: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 16-19: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 20-23: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 24-27: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 28-31: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
port bit reset register
Offset: 0x28, size: 32, reset: 0x00000000, access: write-only
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
Bit 0: Port x reset pin 0.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 1: Port x reset pin 1.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 2: Port x reset pin 2.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 3: Port x reset pin 3.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 4: Port x reset pin 4.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 5: Port x reset pin 5.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 6: Port x reset pin 6.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 7: Port x reset pin 7.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 8: Port x reset pin 8.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 9: Port x reset pin 9.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 10: Port x reset pin 10.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 11: Port x reset pin 11.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 12: Port x reset pin 12.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 13: Port x reset pin 13.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 14: Port x reset pin 14.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 15: Port x reset pin 15.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
0x50000400: General-purpose I/Os
177/177 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | MODER | ||||||||||||||||||||||||||||||||
0x4 | OTYPER | ||||||||||||||||||||||||||||||||
0x8 | OSPEEDR | ||||||||||||||||||||||||||||||||
0xc | PUPDR | ||||||||||||||||||||||||||||||||
0x10 | IDR | ||||||||||||||||||||||||||||||||
0x14 | ODR | ||||||||||||||||||||||||||||||||
0x18 | BSRR | ||||||||||||||||||||||||||||||||
0x1c | LCKR | ||||||||||||||||||||||||||||||||
0x20 | AFRL | ||||||||||||||||||||||||||||||||
0x24 | AFRH | ||||||||||||||||||||||||||||||||
0x28 | BRR |
GPIO port mode register
Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MODER[15]
rw |
MODER[14]
rw |
MODER[13]
rw |
MODER[12]
rw |
MODER[11]
rw |
MODER[10]
rw |
MODER[9]
rw |
MODER[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MODER[7]
rw |
MODER[6]
rw |
MODER[5]
rw |
MODER[4]
rw |
MODER[3]
rw |
MODER[2]
rw |
MODER[1]
rw |
MODER[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
GPIO port output type register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OT[15]
rw |
OT[14]
rw |
OT[13]
rw |
OT[12]
rw |
OT[11]
rw |
OT[10]
rw |
OT[9]
rw |
OT[8]
rw |
OT[7]
rw |
OT[6]
rw |
OT[5]
rw |
OT[4]
rw |
OT[3]
rw |
OT[2]
rw |
OT[1]
rw |
OT[0]
rw |
Bit 0: Port x configuration pin 0.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 1: Port x configuration pin 1.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 2: Port x configuration pin 2.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 3: Port x configuration pin 3.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 4: Port x configuration pin 4.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 5: Port x configuration pin 5.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 6: Port x configuration pin 6.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 7: Port x configuration pin 7.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 8: Port x configuration pin 8.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 9: Port x configuration pin 9.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 10: Port x configuration pin 10.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 11: Port x configuration pin 11.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 12: Port x configuration pin 12.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 13: Port x configuration pin 13.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 14: Port x configuration pin 14.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 15: Port x configuration pin 15.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
GPIO port output speed register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OSPEEDR[15]
rw |
OSPEEDR[14]
rw |
OSPEEDR[13]
rw |
OSPEEDR[12]
rw |
OSPEEDR[11]
rw |
OSPEEDR[10]
rw |
OSPEEDR[9]
rw |
OSPEEDR[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OSPEEDR[7]
rw |
OSPEEDR[6]
rw |
OSPEEDR[5]
rw |
OSPEEDR[4]
rw |
OSPEEDR[3]
rw |
OSPEEDR[2]
rw |
OSPEEDR[1]
rw |
OSPEEDR[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
GPIO port pull-up/pull-down register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUPDR[15]
rw |
PUPDR[14]
rw |
PUPDR[13]
rw |
PUPDR[12]
rw |
PUPDR[11]
rw |
PUPDR[10]
rw |
PUPDR[9]
rw |
PUPDR[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PUPDR[7]
rw |
PUPDR[6]
rw |
PUPDR[5]
rw |
PUPDR[4]
rw |
PUPDR[3]
rw |
PUPDR[2]
rw |
PUPDR[1]
rw |
PUPDR[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
GPIO port input data register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-only
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IDR[15]
r |
IDR[14]
r |
IDR[13]
r |
IDR[12]
r |
IDR[11]
r |
IDR[10]
r |
IDR[9]
r |
IDR[8]
r |
IDR[7]
r |
IDR[6]
r |
IDR[5]
r |
IDR[4]
r |
IDR[3]
r |
IDR[2]
r |
IDR[1]
r |
IDR[0]
r |
Bit 0: Port input data pin 0.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 1: Port input data pin 1.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 2: Port input data pin 2.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 3: Port input data pin 3.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 4: Port input data pin 4.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 5: Port input data pin 5.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 6: Port input data pin 6.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 7: Port input data pin 7.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 8: Port input data pin 8.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 9: Port input data pin 9.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 10: Port input data pin 10.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 11: Port input data pin 11.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 12: Port input data pin 12.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 13: Port input data pin 13.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 14: Port input data pin 14.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 15: Port input data pin 15.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
GPIO port output data register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ODR[15]
rw |
ODR[14]
rw |
ODR[13]
rw |
ODR[12]
rw |
ODR[11]
rw |
ODR[10]
rw |
ODR[9]
rw |
ODR[8]
rw |
ODR[7]
rw |
ODR[6]
rw |
ODR[5]
rw |
ODR[4]
rw |
ODR[3]
rw |
ODR[2]
rw |
ODR[1]
rw |
ODR[0]
rw |
Bit 0: Port output data pin 0.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 1: Port output data pin 1.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 2: Port output data pin 2.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 3: Port output data pin 3.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 4: Port output data pin 4.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 5: Port output data pin 5.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 6: Port output data pin 6.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 7: Port output data pin 7.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 8: Port output data pin 8.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 9: Port output data pin 9.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 10: Port output data pin 10.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 11: Port output data pin 11.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 12: Port output data pin 12.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 13: Port output data pin 13.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 14: Port output data pin 14.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 15: Port output data pin 15.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
GPIO port bit set/reset register
Offset: 0x18, size: 32, reset: 0x00000000, access: write-only
32/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BS[15]
w |
BS[14]
w |
BS[13]
w |
BS[12]
w |
BS[11]
w |
BS[10]
w |
BS[9]
w |
BS[8]
w |
BS[7]
w |
BS[6]
w |
BS[5]
w |
BS[4]
w |
BS[3]
w |
BS[2]
w |
BS[1]
w |
BS[0]
w |
Bit 0: Port x set pin 0.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 1: Port x set pin 1.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 2: Port x set pin 2.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 3: Port x set pin 3.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 4: Port x set pin 4.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 5: Port x set pin 5.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 6: Port x set pin 6.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 7: Port x set pin 7.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 8: Port x set pin 8.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 9: Port x set pin 9.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 10: Port x set pin 10.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 11: Port x set pin 11.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 12: Port x set pin 12.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 13: Port x set pin 13.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 14: Port x set pin 14.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 15: Port x set pin 15.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 16: Port x reset pin 0.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 17: Port x reset pin 1.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 18: Port x reset pin 2.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 19: Port x reset pin 3.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 20: Port x reset pin 4.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 21: Port x reset pin 5.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 22: Port x reset pin 6.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 23: Port x reset pin 7.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 24: Port x reset pin 8.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 25: Port x reset pin 9.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 26: Port x reset pin 10.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 27: Port x reset pin 11.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 28: Port x reset pin 12.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 29: Port x reset pin 13.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 30: Port x reset pin 14.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 31: Port x reset pin 15.
Allowed values:
1: Reset: Resets the corresponding ODx bit
GPIO port configuration lock register
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
17/17 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LCKK
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LCK[15]
rw |
LCK[14]
rw |
LCK[13]
rw |
LCK[12]
rw |
LCK[11]
rw |
LCK[10]
rw |
LCK[9]
rw |
LCK[8]
rw |
LCK[7]
rw |
LCK[6]
rw |
LCK[5]
rw |
LCK[4]
rw |
LCK[3]
rw |
LCK[2]
rw |
LCK[1]
rw |
LCK[0]
rw |
Bit 0: Port x lock pin 0.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 1: Port x lock pin 1.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 2: Port x lock pin 2.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 3: Port x lock pin 3.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 4: Port x lock pin 4.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 5: Port x lock pin 5.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 6: Port x lock pin 6.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 7: Port x lock pin 7.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 8: Port x lock pin 8.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 9: Port x lock pin 9.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 10: Port x lock pin 10.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 11: Port x lock pin 11.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 12: Port x lock pin 12.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 13: Port x lock pin 13.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 14: Port x lock pin 14.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 15: Port x lock pin 15.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 16: Port x lock bit y (y= 0..15).
Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active
GPIO alternate function low register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AFR[EL7]
rw |
AFR[EL6]
rw |
AFR[EL5]
rw |
AFR[EL4]
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AFR[EL3]
rw |
AFR[EL2]
rw |
AFR[EL1]
rw |
AFR[EL0]
rw |
Bits 0-3: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 4-7: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 8-11: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 12-15: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 16-19: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 20-23: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 24-27: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 28-31: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
GPIO alternate function high register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AFR[EL15]
rw |
AFR[EL14]
rw |
AFR[EL13]
rw |
AFR[EL12]
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AFR[EL11]
rw |
AFR[EL10]
rw |
AFR[EL9]
rw |
AFR[EL8]
rw |
Bits 0-3: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 4-7: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 8-11: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 12-15: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 16-19: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 20-23: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 24-27: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 28-31: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
port bit reset register
Offset: 0x28, size: 32, reset: 0x00000000, access: write-only
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
Bit 0: Port x reset pin 0.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 1: Port x reset pin 1.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 2: Port x reset pin 2.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 3: Port x reset pin 3.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 4: Port x reset pin 4.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 5: Port x reset pin 5.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 6: Port x reset pin 6.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 7: Port x reset pin 7.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 8: Port x reset pin 8.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 9: Port x reset pin 9.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 10: Port x reset pin 10.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 11: Port x reset pin 11.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 12: Port x reset pin 12.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 13: Port x reset pin 13.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 14: Port x reset pin 14.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 15: Port x reset pin 15.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
0x50000800: General-purpose I/Os
177/177 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | MODER | ||||||||||||||||||||||||||||||||
0x4 | OTYPER | ||||||||||||||||||||||||||||||||
0x8 | OSPEEDR | ||||||||||||||||||||||||||||||||
0xc | PUPDR | ||||||||||||||||||||||||||||||||
0x10 | IDR | ||||||||||||||||||||||||||||||||
0x14 | ODR | ||||||||||||||||||||||||||||||||
0x18 | BSRR | ||||||||||||||||||||||||||||||||
0x1c | LCKR | ||||||||||||||||||||||||||||||||
0x20 | AFRL | ||||||||||||||||||||||||||||||||
0x24 | AFRH | ||||||||||||||||||||||||||||||||
0x28 | BRR |
GPIO port mode register
Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MODER[15]
rw |
MODER[14]
rw |
MODER[13]
rw |
MODER[12]
rw |
MODER[11]
rw |
MODER[10]
rw |
MODER[9]
rw |
MODER[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MODER[7]
rw |
MODER[6]
rw |
MODER[5]
rw |
MODER[4]
rw |
MODER[3]
rw |
MODER[2]
rw |
MODER[1]
rw |
MODER[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
GPIO port output type register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OT[15]
rw |
OT[14]
rw |
OT[13]
rw |
OT[12]
rw |
OT[11]
rw |
OT[10]
rw |
OT[9]
rw |
OT[8]
rw |
OT[7]
rw |
OT[6]
rw |
OT[5]
rw |
OT[4]
rw |
OT[3]
rw |
OT[2]
rw |
OT[1]
rw |
OT[0]
rw |
Bit 0: Port x configuration pin 0.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 1: Port x configuration pin 1.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 2: Port x configuration pin 2.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 3: Port x configuration pin 3.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 4: Port x configuration pin 4.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 5: Port x configuration pin 5.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 6: Port x configuration pin 6.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 7: Port x configuration pin 7.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 8: Port x configuration pin 8.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 9: Port x configuration pin 9.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 10: Port x configuration pin 10.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 11: Port x configuration pin 11.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 12: Port x configuration pin 12.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 13: Port x configuration pin 13.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 14: Port x configuration pin 14.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 15: Port x configuration pin 15.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
GPIO port output speed register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OSPEEDR[15]
rw |
OSPEEDR[14]
rw |
OSPEEDR[13]
rw |
OSPEEDR[12]
rw |
OSPEEDR[11]
rw |
OSPEEDR[10]
rw |
OSPEEDR[9]
rw |
OSPEEDR[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OSPEEDR[7]
rw |
OSPEEDR[6]
rw |
OSPEEDR[5]
rw |
OSPEEDR[4]
rw |
OSPEEDR[3]
rw |
OSPEEDR[2]
rw |
OSPEEDR[1]
rw |
OSPEEDR[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
GPIO port pull-up/pull-down register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUPDR[15]
rw |
PUPDR[14]
rw |
PUPDR[13]
rw |
PUPDR[12]
rw |
PUPDR[11]
rw |
PUPDR[10]
rw |
PUPDR[9]
rw |
PUPDR[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PUPDR[7]
rw |
PUPDR[6]
rw |
PUPDR[5]
rw |
PUPDR[4]
rw |
PUPDR[3]
rw |
PUPDR[2]
rw |
PUPDR[1]
rw |
PUPDR[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
GPIO port input data register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-only
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IDR[15]
r |
IDR[14]
r |
IDR[13]
r |
IDR[12]
r |
IDR[11]
r |
IDR[10]
r |
IDR[9]
r |
IDR[8]
r |
IDR[7]
r |
IDR[6]
r |
IDR[5]
r |
IDR[4]
r |
IDR[3]
r |
IDR[2]
r |
IDR[1]
r |
IDR[0]
r |
Bit 0: Port input data pin 0.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 1: Port input data pin 1.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 2: Port input data pin 2.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 3: Port input data pin 3.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 4: Port input data pin 4.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 5: Port input data pin 5.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 6: Port input data pin 6.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 7: Port input data pin 7.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 8: Port input data pin 8.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 9: Port input data pin 9.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 10: Port input data pin 10.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 11: Port input data pin 11.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 12: Port input data pin 12.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 13: Port input data pin 13.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 14: Port input data pin 14.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 15: Port input data pin 15.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
GPIO port output data register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ODR[15]
rw |
ODR[14]
rw |
ODR[13]
rw |
ODR[12]
rw |
ODR[11]
rw |
ODR[10]
rw |
ODR[9]
rw |
ODR[8]
rw |
ODR[7]
rw |
ODR[6]
rw |
ODR[5]
rw |
ODR[4]
rw |
ODR[3]
rw |
ODR[2]
rw |
ODR[1]
rw |
ODR[0]
rw |
Bit 0: Port output data pin 0.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 1: Port output data pin 1.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 2: Port output data pin 2.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 3: Port output data pin 3.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 4: Port output data pin 4.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 5: Port output data pin 5.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 6: Port output data pin 6.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 7: Port output data pin 7.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 8: Port output data pin 8.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 9: Port output data pin 9.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 10: Port output data pin 10.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 11: Port output data pin 11.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 12: Port output data pin 12.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 13: Port output data pin 13.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 14: Port output data pin 14.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 15: Port output data pin 15.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
GPIO port bit set/reset register
Offset: 0x18, size: 32, reset: 0x00000000, access: write-only
32/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BS[15]
w |
BS[14]
w |
BS[13]
w |
BS[12]
w |
BS[11]
w |
BS[10]
w |
BS[9]
w |
BS[8]
w |
BS[7]
w |
BS[6]
w |
BS[5]
w |
BS[4]
w |
BS[3]
w |
BS[2]
w |
BS[1]
w |
BS[0]
w |
Bit 0: Port x set pin 0.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 1: Port x set pin 1.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 2: Port x set pin 2.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 3: Port x set pin 3.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 4: Port x set pin 4.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 5: Port x set pin 5.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 6: Port x set pin 6.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 7: Port x set pin 7.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 8: Port x set pin 8.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 9: Port x set pin 9.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 10: Port x set pin 10.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 11: Port x set pin 11.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 12: Port x set pin 12.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 13: Port x set pin 13.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 14: Port x set pin 14.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 15: Port x set pin 15.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 16: Port x reset pin 0.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 17: Port x reset pin 1.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 18: Port x reset pin 2.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 19: Port x reset pin 3.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 20: Port x reset pin 4.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 21: Port x reset pin 5.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 22: Port x reset pin 6.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 23: Port x reset pin 7.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 24: Port x reset pin 8.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 25: Port x reset pin 9.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 26: Port x reset pin 10.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 27: Port x reset pin 11.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 28: Port x reset pin 12.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 29: Port x reset pin 13.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 30: Port x reset pin 14.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 31: Port x reset pin 15.
Allowed values:
1: Reset: Resets the corresponding ODx bit
GPIO port configuration lock register
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
17/17 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LCKK
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LCK[15]
rw |
LCK[14]
rw |
LCK[13]
rw |
LCK[12]
rw |
LCK[11]
rw |
LCK[10]
rw |
LCK[9]
rw |
LCK[8]
rw |
LCK[7]
rw |
LCK[6]
rw |
LCK[5]
rw |
LCK[4]
rw |
LCK[3]
rw |
LCK[2]
rw |
LCK[1]
rw |
LCK[0]
rw |
Bit 0: Port x lock pin 0.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 1: Port x lock pin 1.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 2: Port x lock pin 2.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 3: Port x lock pin 3.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 4: Port x lock pin 4.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 5: Port x lock pin 5.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 6: Port x lock pin 6.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 7: Port x lock pin 7.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 8: Port x lock pin 8.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 9: Port x lock pin 9.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 10: Port x lock pin 10.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 11: Port x lock pin 11.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 12: Port x lock pin 12.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 13: Port x lock pin 13.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 14: Port x lock pin 14.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 15: Port x lock pin 15.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 16: Port x lock bit y (y= 0..15).
Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active
GPIO alternate function low register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AFR[EL7]
rw |
AFR[EL6]
rw |
AFR[EL5]
rw |
AFR[EL4]
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AFR[EL3]
rw |
AFR[EL2]
rw |
AFR[EL1]
rw |
AFR[EL0]
rw |
Bits 0-3: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 4-7: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 8-11: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 12-15: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 16-19: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 20-23: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 24-27: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 28-31: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
GPIO alternate function high register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AFR[EL15]
rw |
AFR[EL14]
rw |
AFR[EL13]
rw |
AFR[EL12]
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AFR[EL11]
rw |
AFR[EL10]
rw |
AFR[EL9]
rw |
AFR[EL8]
rw |
Bits 0-3: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 4-7: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 8-11: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 12-15: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 16-19: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 20-23: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 24-27: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 28-31: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
port bit reset register
Offset: 0x28, size: 32, reset: 0x00000000, access: write-only
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
Bit 0: Port x reset pin 0.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 1: Port x reset pin 1.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 2: Port x reset pin 2.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 3: Port x reset pin 3.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 4: Port x reset pin 4.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 5: Port x reset pin 5.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 6: Port x reset pin 6.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 7: Port x reset pin 7.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 8: Port x reset pin 8.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 9: Port x reset pin 9.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 10: Port x reset pin 10.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 11: Port x reset pin 11.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 12: Port x reset pin 12.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 13: Port x reset pin 13.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 14: Port x reset pin 14.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 15: Port x reset pin 15.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
0x50000c00: General-purpose I/Os
177/177 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | MODER | ||||||||||||||||||||||||||||||||
0x4 | OTYPER | ||||||||||||||||||||||||||||||||
0x8 | OSPEEDR | ||||||||||||||||||||||||||||||||
0xc | PUPDR | ||||||||||||||||||||||||||||||||
0x10 | IDR | ||||||||||||||||||||||||||||||||
0x14 | ODR | ||||||||||||||||||||||||||||||||
0x18 | BSRR | ||||||||||||||||||||||||||||||||
0x1c | LCKR | ||||||||||||||||||||||||||||||||
0x20 | AFRL | ||||||||||||||||||||||||||||||||
0x24 | AFRH | ||||||||||||||||||||||||||||||||
0x28 | BRR |
GPIO port mode register
Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MODER[15]
rw |
MODER[14]
rw |
MODER[13]
rw |
MODER[12]
rw |
MODER[11]
rw |
MODER[10]
rw |
MODER[9]
rw |
MODER[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MODER[7]
rw |
MODER[6]
rw |
MODER[5]
rw |
MODER[4]
rw |
MODER[3]
rw |
MODER[2]
rw |
MODER[1]
rw |
MODER[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
GPIO port output type register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OT[15]
rw |
OT[14]
rw |
OT[13]
rw |
OT[12]
rw |
OT[11]
rw |
OT[10]
rw |
OT[9]
rw |
OT[8]
rw |
OT[7]
rw |
OT[6]
rw |
OT[5]
rw |
OT[4]
rw |
OT[3]
rw |
OT[2]
rw |
OT[1]
rw |
OT[0]
rw |
Bit 0: Port x configuration pin 0.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 1: Port x configuration pin 1.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 2: Port x configuration pin 2.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 3: Port x configuration pin 3.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 4: Port x configuration pin 4.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 5: Port x configuration pin 5.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 6: Port x configuration pin 6.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 7: Port x configuration pin 7.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 8: Port x configuration pin 8.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 9: Port x configuration pin 9.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 10: Port x configuration pin 10.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 11: Port x configuration pin 11.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 12: Port x configuration pin 12.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 13: Port x configuration pin 13.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 14: Port x configuration pin 14.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 15: Port x configuration pin 15.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
GPIO port output speed register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OSPEEDR[15]
rw |
OSPEEDR[14]
rw |
OSPEEDR[13]
rw |
OSPEEDR[12]
rw |
OSPEEDR[11]
rw |
OSPEEDR[10]
rw |
OSPEEDR[9]
rw |
OSPEEDR[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OSPEEDR[7]
rw |
OSPEEDR[6]
rw |
OSPEEDR[5]
rw |
OSPEEDR[4]
rw |
OSPEEDR[3]
rw |
OSPEEDR[2]
rw |
OSPEEDR[1]
rw |
OSPEEDR[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
GPIO port pull-up/pull-down register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUPDR[15]
rw |
PUPDR[14]
rw |
PUPDR[13]
rw |
PUPDR[12]
rw |
PUPDR[11]
rw |
PUPDR[10]
rw |
PUPDR[9]
rw |
PUPDR[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PUPDR[7]
rw |
PUPDR[6]
rw |
PUPDR[5]
rw |
PUPDR[4]
rw |
PUPDR[3]
rw |
PUPDR[2]
rw |
PUPDR[1]
rw |
PUPDR[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
GPIO port input data register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-only
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IDR[15]
r |
IDR[14]
r |
IDR[13]
r |
IDR[12]
r |
IDR[11]
r |
IDR[10]
r |
IDR[9]
r |
IDR[8]
r |
IDR[7]
r |
IDR[6]
r |
IDR[5]
r |
IDR[4]
r |
IDR[3]
r |
IDR[2]
r |
IDR[1]
r |
IDR[0]
r |
Bit 0: Port input data pin 0.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 1: Port input data pin 1.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 2: Port input data pin 2.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 3: Port input data pin 3.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 4: Port input data pin 4.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 5: Port input data pin 5.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 6: Port input data pin 6.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 7: Port input data pin 7.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 8: Port input data pin 8.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 9: Port input data pin 9.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 10: Port input data pin 10.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 11: Port input data pin 11.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 12: Port input data pin 12.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 13: Port input data pin 13.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 14: Port input data pin 14.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 15: Port input data pin 15.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
GPIO port output data register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ODR[15]
rw |
ODR[14]
rw |
ODR[13]
rw |
ODR[12]
rw |
ODR[11]
rw |
ODR[10]
rw |
ODR[9]
rw |
ODR[8]
rw |
ODR[7]
rw |
ODR[6]
rw |
ODR[5]
rw |
ODR[4]
rw |
ODR[3]
rw |
ODR[2]
rw |
ODR[1]
rw |
ODR[0]
rw |
Bit 0: Port output data pin 0.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 1: Port output data pin 1.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 2: Port output data pin 2.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 3: Port output data pin 3.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 4: Port output data pin 4.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 5: Port output data pin 5.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 6: Port output data pin 6.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 7: Port output data pin 7.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 8: Port output data pin 8.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 9: Port output data pin 9.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 10: Port output data pin 10.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 11: Port output data pin 11.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 12: Port output data pin 12.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 13: Port output data pin 13.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 14: Port output data pin 14.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 15: Port output data pin 15.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
GPIO port bit set/reset register
Offset: 0x18, size: 32, reset: 0x00000000, access: write-only
32/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BS[15]
w |
BS[14]
w |
BS[13]
w |
BS[12]
w |
BS[11]
w |
BS[10]
w |
BS[9]
w |
BS[8]
w |
BS[7]
w |
BS[6]
w |
BS[5]
w |
BS[4]
w |
BS[3]
w |
BS[2]
w |
BS[1]
w |
BS[0]
w |
Bit 0: Port x set pin 0.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 1: Port x set pin 1.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 2: Port x set pin 2.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 3: Port x set pin 3.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 4: Port x set pin 4.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 5: Port x set pin 5.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 6: Port x set pin 6.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 7: Port x set pin 7.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 8: Port x set pin 8.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 9: Port x set pin 9.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 10: Port x set pin 10.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 11: Port x set pin 11.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 12: Port x set pin 12.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 13: Port x set pin 13.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 14: Port x set pin 14.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 15: Port x set pin 15.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 16: Port x reset pin 0.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 17: Port x reset pin 1.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 18: Port x reset pin 2.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 19: Port x reset pin 3.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 20: Port x reset pin 4.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 21: Port x reset pin 5.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 22: Port x reset pin 6.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 23: Port x reset pin 7.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 24: Port x reset pin 8.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 25: Port x reset pin 9.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 26: Port x reset pin 10.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 27: Port x reset pin 11.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 28: Port x reset pin 12.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 29: Port x reset pin 13.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 30: Port x reset pin 14.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 31: Port x reset pin 15.
Allowed values:
1: Reset: Resets the corresponding ODx bit
GPIO port configuration lock register
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
17/17 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LCKK
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LCK[15]
rw |
LCK[14]
rw |
LCK[13]
rw |
LCK[12]
rw |
LCK[11]
rw |
LCK[10]
rw |
LCK[9]
rw |
LCK[8]
rw |
LCK[7]
rw |
LCK[6]
rw |
LCK[5]
rw |
LCK[4]
rw |
LCK[3]
rw |
LCK[2]
rw |
LCK[1]
rw |
LCK[0]
rw |
Bit 0: Port x lock pin 0.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 1: Port x lock pin 1.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 2: Port x lock pin 2.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 3: Port x lock pin 3.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 4: Port x lock pin 4.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 5: Port x lock pin 5.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 6: Port x lock pin 6.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 7: Port x lock pin 7.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 8: Port x lock pin 8.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 9: Port x lock pin 9.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 10: Port x lock pin 10.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 11: Port x lock pin 11.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 12: Port x lock pin 12.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 13: Port x lock pin 13.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 14: Port x lock pin 14.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 15: Port x lock pin 15.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 16: Port x lock bit y (y= 0..15).
Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active
GPIO alternate function low register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AFR[EL7]
rw |
AFR[EL6]
rw |
AFR[EL5]
rw |
AFR[EL4]
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AFR[EL3]
rw |
AFR[EL2]
rw |
AFR[EL1]
rw |
AFR[EL0]
rw |
Bits 0-3: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 4-7: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 8-11: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 12-15: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 16-19: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 20-23: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 24-27: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 28-31: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
GPIO alternate function high register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AFR[EL15]
rw |
AFR[EL14]
rw |
AFR[EL13]
rw |
AFR[EL12]
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AFR[EL11]
rw |
AFR[EL10]
rw |
AFR[EL9]
rw |
AFR[EL8]
rw |
Bits 0-3: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 4-7: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 8-11: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 12-15: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 16-19: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 20-23: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 24-27: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 28-31: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
port bit reset register
Offset: 0x28, size: 32, reset: 0x00000000, access: write-only
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
Bit 0: Port x reset pin 0.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 1: Port x reset pin 1.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 2: Port x reset pin 2.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 3: Port x reset pin 3.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 4: Port x reset pin 4.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 5: Port x reset pin 5.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 6: Port x reset pin 6.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 7: Port x reset pin 7.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 8: Port x reset pin 8.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 9: Port x reset pin 9.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 10: Port x reset pin 10.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 11: Port x reset pin 11.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 12: Port x reset pin 12.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 13: Port x reset pin 13.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 14: Port x reset pin 14.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 15: Port x reset pin 15.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
0x50001000: General-purpose I/Os
177/177 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | MODER | ||||||||||||||||||||||||||||||||
0x4 | OTYPER | ||||||||||||||||||||||||||||||||
0x8 | OSPEEDR | ||||||||||||||||||||||||||||||||
0xc | PUPDR | ||||||||||||||||||||||||||||||||
0x10 | IDR | ||||||||||||||||||||||||||||||||
0x14 | ODR | ||||||||||||||||||||||||||||||||
0x18 | BSRR | ||||||||||||||||||||||||||||||||
0x1c | LCKR | ||||||||||||||||||||||||||||||||
0x20 | AFRL | ||||||||||||||||||||||||||||||||
0x24 | AFRH | ||||||||||||||||||||||||||||||||
0x28 | BRR |
GPIO port mode register
Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MODER[15]
rw |
MODER[14]
rw |
MODER[13]
rw |
MODER[12]
rw |
MODER[11]
rw |
MODER[10]
rw |
MODER[9]
rw |
MODER[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MODER[7]
rw |
MODER[6]
rw |
MODER[5]
rw |
MODER[4]
rw |
MODER[3]
rw |
MODER[2]
rw |
MODER[1]
rw |
MODER[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
GPIO port output type register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OT[15]
rw |
OT[14]
rw |
OT[13]
rw |
OT[12]
rw |
OT[11]
rw |
OT[10]
rw |
OT[9]
rw |
OT[8]
rw |
OT[7]
rw |
OT[6]
rw |
OT[5]
rw |
OT[4]
rw |
OT[3]
rw |
OT[2]
rw |
OT[1]
rw |
OT[0]
rw |
Bit 0: Port x configuration pin 0.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 1: Port x configuration pin 1.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 2: Port x configuration pin 2.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 3: Port x configuration pin 3.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 4: Port x configuration pin 4.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 5: Port x configuration pin 5.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 6: Port x configuration pin 6.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 7: Port x configuration pin 7.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 8: Port x configuration pin 8.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 9: Port x configuration pin 9.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 10: Port x configuration pin 10.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 11: Port x configuration pin 11.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 12: Port x configuration pin 12.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 13: Port x configuration pin 13.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 14: Port x configuration pin 14.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 15: Port x configuration pin 15.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
GPIO port output speed register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OSPEEDR[15]
rw |
OSPEEDR[14]
rw |
OSPEEDR[13]
rw |
OSPEEDR[12]
rw |
OSPEEDR[11]
rw |
OSPEEDR[10]
rw |
OSPEEDR[9]
rw |
OSPEEDR[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OSPEEDR[7]
rw |
OSPEEDR[6]
rw |
OSPEEDR[5]
rw |
OSPEEDR[4]
rw |
OSPEEDR[3]
rw |
OSPEEDR[2]
rw |
OSPEEDR[1]
rw |
OSPEEDR[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
GPIO port pull-up/pull-down register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUPDR[15]
rw |
PUPDR[14]
rw |
PUPDR[13]
rw |
PUPDR[12]
rw |
PUPDR[11]
rw |
PUPDR[10]
rw |
PUPDR[9]
rw |
PUPDR[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PUPDR[7]
rw |
PUPDR[6]
rw |
PUPDR[5]
rw |
PUPDR[4]
rw |
PUPDR[3]
rw |
PUPDR[2]
rw |
PUPDR[1]
rw |
PUPDR[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
GPIO port input data register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-only
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IDR[15]
r |
IDR[14]
r |
IDR[13]
r |
IDR[12]
r |
IDR[11]
r |
IDR[10]
r |
IDR[9]
r |
IDR[8]
r |
IDR[7]
r |
IDR[6]
r |
IDR[5]
r |
IDR[4]
r |
IDR[3]
r |
IDR[2]
r |
IDR[1]
r |
IDR[0]
r |
Bit 0: Port input data pin 0.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 1: Port input data pin 1.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 2: Port input data pin 2.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 3: Port input data pin 3.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 4: Port input data pin 4.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 5: Port input data pin 5.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 6: Port input data pin 6.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 7: Port input data pin 7.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 8: Port input data pin 8.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 9: Port input data pin 9.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 10: Port input data pin 10.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 11: Port input data pin 11.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 12: Port input data pin 12.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 13: Port input data pin 13.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 14: Port input data pin 14.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 15: Port input data pin 15.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
GPIO port output data register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ODR[15]
rw |
ODR[14]
rw |
ODR[13]
rw |
ODR[12]
rw |
ODR[11]
rw |
ODR[10]
rw |
ODR[9]
rw |
ODR[8]
rw |
ODR[7]
rw |
ODR[6]
rw |
ODR[5]
rw |
ODR[4]
rw |
ODR[3]
rw |
ODR[2]
rw |
ODR[1]
rw |
ODR[0]
rw |
Bit 0: Port output data pin 0.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 1: Port output data pin 1.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 2: Port output data pin 2.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 3: Port output data pin 3.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 4: Port output data pin 4.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 5: Port output data pin 5.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 6: Port output data pin 6.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 7: Port output data pin 7.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 8: Port output data pin 8.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 9: Port output data pin 9.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 10: Port output data pin 10.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 11: Port output data pin 11.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 12: Port output data pin 12.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 13: Port output data pin 13.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 14: Port output data pin 14.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 15: Port output data pin 15.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
GPIO port bit set/reset register
Offset: 0x18, size: 32, reset: 0x00000000, access: write-only
32/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BS[15]
w |
BS[14]
w |
BS[13]
w |
BS[12]
w |
BS[11]
w |
BS[10]
w |
BS[9]
w |
BS[8]
w |
BS[7]
w |
BS[6]
w |
BS[5]
w |
BS[4]
w |
BS[3]
w |
BS[2]
w |
BS[1]
w |
BS[0]
w |
Bit 0: Port x set pin 0.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 1: Port x set pin 1.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 2: Port x set pin 2.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 3: Port x set pin 3.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 4: Port x set pin 4.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 5: Port x set pin 5.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 6: Port x set pin 6.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 7: Port x set pin 7.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 8: Port x set pin 8.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 9: Port x set pin 9.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 10: Port x set pin 10.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 11: Port x set pin 11.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 12: Port x set pin 12.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 13: Port x set pin 13.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 14: Port x set pin 14.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 15: Port x set pin 15.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 16: Port x reset pin 0.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 17: Port x reset pin 1.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 18: Port x reset pin 2.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 19: Port x reset pin 3.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 20: Port x reset pin 4.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 21: Port x reset pin 5.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 22: Port x reset pin 6.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 23: Port x reset pin 7.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 24: Port x reset pin 8.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 25: Port x reset pin 9.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 26: Port x reset pin 10.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 27: Port x reset pin 11.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 28: Port x reset pin 12.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 29: Port x reset pin 13.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 30: Port x reset pin 14.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 31: Port x reset pin 15.
Allowed values:
1: Reset: Resets the corresponding ODx bit
GPIO port configuration lock register
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
17/17 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LCKK
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LCK[15]
rw |
LCK[14]
rw |
LCK[13]
rw |
LCK[12]
rw |
LCK[11]
rw |
LCK[10]
rw |
LCK[9]
rw |
LCK[8]
rw |
LCK[7]
rw |
LCK[6]
rw |
LCK[5]
rw |
LCK[4]
rw |
LCK[3]
rw |
LCK[2]
rw |
LCK[1]
rw |
LCK[0]
rw |
Bit 0: Port x lock pin 0.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 1: Port x lock pin 1.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 2: Port x lock pin 2.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 3: Port x lock pin 3.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 4: Port x lock pin 4.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 5: Port x lock pin 5.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 6: Port x lock pin 6.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 7: Port x lock pin 7.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 8: Port x lock pin 8.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 9: Port x lock pin 9.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 10: Port x lock pin 10.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 11: Port x lock pin 11.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 12: Port x lock pin 12.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 13: Port x lock pin 13.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 14: Port x lock pin 14.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 15: Port x lock pin 15.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 16: Port x lock bit y (y= 0..15).
Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active
GPIO alternate function low register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AFR[EL7]
rw |
AFR[EL6]
rw |
AFR[EL5]
rw |
AFR[EL4]
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AFR[EL3]
rw |
AFR[EL2]
rw |
AFR[EL1]
rw |
AFR[EL0]
rw |
Bits 0-3: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 4-7: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 8-11: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 12-15: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 16-19: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 20-23: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 24-27: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 28-31: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
GPIO alternate function high register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AFR[EL15]
rw |
AFR[EL14]
rw |
AFR[EL13]
rw |
AFR[EL12]
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AFR[EL11]
rw |
AFR[EL10]
rw |
AFR[EL9]
rw |
AFR[EL8]
rw |
Bits 0-3: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 4-7: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 8-11: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 12-15: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 16-19: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 20-23: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 24-27: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 28-31: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
port bit reset register
Offset: 0x28, size: 32, reset: 0x00000000, access: write-only
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
Bit 0: Port x reset pin 0.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 1: Port x reset pin 1.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 2: Port x reset pin 2.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 3: Port x reset pin 3.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 4: Port x reset pin 4.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 5: Port x reset pin 5.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 6: Port x reset pin 6.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 7: Port x reset pin 7.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 8: Port x reset pin 8.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 9: Port x reset pin 9.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 10: Port x reset pin 10.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 11: Port x reset pin 11.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 12: Port x reset pin 12.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 13: Port x reset pin 13.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 14: Port x reset pin 14.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 15: Port x reset pin 15.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
0x50001400: General-purpose I/Os
177/177 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | MODER | ||||||||||||||||||||||||||||||||
0x4 | OTYPER | ||||||||||||||||||||||||||||||||
0x8 | OSPEEDR | ||||||||||||||||||||||||||||||||
0xc | PUPDR | ||||||||||||||||||||||||||||||||
0x10 | IDR | ||||||||||||||||||||||||||||||||
0x14 | ODR | ||||||||||||||||||||||||||||||||
0x18 | BSRR | ||||||||||||||||||||||||||||||||
0x1c | LCKR | ||||||||||||||||||||||||||||||||
0x20 | AFRL | ||||||||||||||||||||||||||||||||
0x24 | AFRH | ||||||||||||||||||||||||||||||||
0x28 | BRR |
GPIO port mode register
Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MODER[15]
rw |
MODER[14]
rw |
MODER[13]
rw |
MODER[12]
rw |
MODER[11]
rw |
MODER[10]
rw |
MODER[9]
rw |
MODER[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MODER[7]
rw |
MODER[6]
rw |
MODER[5]
rw |
MODER[4]
rw |
MODER[3]
rw |
MODER[2]
rw |
MODER[1]
rw |
MODER[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
GPIO port output type register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OT[15]
rw |
OT[14]
rw |
OT[13]
rw |
OT[12]
rw |
OT[11]
rw |
OT[10]
rw |
OT[9]
rw |
OT[8]
rw |
OT[7]
rw |
OT[6]
rw |
OT[5]
rw |
OT[4]
rw |
OT[3]
rw |
OT[2]
rw |
OT[1]
rw |
OT[0]
rw |
Bit 0: Port x configuration pin 0.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 1: Port x configuration pin 1.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 2: Port x configuration pin 2.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 3: Port x configuration pin 3.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 4: Port x configuration pin 4.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 5: Port x configuration pin 5.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 6: Port x configuration pin 6.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 7: Port x configuration pin 7.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 8: Port x configuration pin 8.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 9: Port x configuration pin 9.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 10: Port x configuration pin 10.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 11: Port x configuration pin 11.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 12: Port x configuration pin 12.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 13: Port x configuration pin 13.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 14: Port x configuration pin 14.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 15: Port x configuration pin 15.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
GPIO port output speed register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OSPEEDR[15]
rw |
OSPEEDR[14]
rw |
OSPEEDR[13]
rw |
OSPEEDR[12]
rw |
OSPEEDR[11]
rw |
OSPEEDR[10]
rw |
OSPEEDR[9]
rw |
OSPEEDR[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OSPEEDR[7]
rw |
OSPEEDR[6]
rw |
OSPEEDR[5]
rw |
OSPEEDR[4]
rw |
OSPEEDR[3]
rw |
OSPEEDR[2]
rw |
OSPEEDR[1]
rw |
OSPEEDR[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
GPIO port pull-up/pull-down register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUPDR[15]
rw |
PUPDR[14]
rw |
PUPDR[13]
rw |
PUPDR[12]
rw |
PUPDR[11]
rw |
PUPDR[10]
rw |
PUPDR[9]
rw |
PUPDR[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PUPDR[7]
rw |
PUPDR[6]
rw |
PUPDR[5]
rw |
PUPDR[4]
rw |
PUPDR[3]
rw |
PUPDR[2]
rw |
PUPDR[1]
rw |
PUPDR[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
GPIO port input data register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-only
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IDR[15]
r |
IDR[14]
r |
IDR[13]
r |
IDR[12]
r |
IDR[11]
r |
IDR[10]
r |
IDR[9]
r |
IDR[8]
r |
IDR[7]
r |
IDR[6]
r |
IDR[5]
r |
IDR[4]
r |
IDR[3]
r |
IDR[2]
r |
IDR[1]
r |
IDR[0]
r |
Bit 0: Port input data pin 0.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 1: Port input data pin 1.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 2: Port input data pin 2.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 3: Port input data pin 3.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 4: Port input data pin 4.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 5: Port input data pin 5.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 6: Port input data pin 6.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 7: Port input data pin 7.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 8: Port input data pin 8.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 9: Port input data pin 9.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 10: Port input data pin 10.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 11: Port input data pin 11.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 12: Port input data pin 12.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 13: Port input data pin 13.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 14: Port input data pin 14.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 15: Port input data pin 15.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
GPIO port output data register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ODR[15]
rw |
ODR[14]
rw |
ODR[13]
rw |
ODR[12]
rw |
ODR[11]
rw |
ODR[10]
rw |
ODR[9]
rw |
ODR[8]
rw |
ODR[7]
rw |
ODR[6]
rw |
ODR[5]
rw |
ODR[4]
rw |
ODR[3]
rw |
ODR[2]
rw |
ODR[1]
rw |
ODR[0]
rw |
Bit 0: Port output data pin 0.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 1: Port output data pin 1.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 2: Port output data pin 2.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 3: Port output data pin 3.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 4: Port output data pin 4.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 5: Port output data pin 5.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 6: Port output data pin 6.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 7: Port output data pin 7.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 8: Port output data pin 8.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 9: Port output data pin 9.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 10: Port output data pin 10.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 11: Port output data pin 11.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 12: Port output data pin 12.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 13: Port output data pin 13.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 14: Port output data pin 14.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 15: Port output data pin 15.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
GPIO port bit set/reset register
Offset: 0x18, size: 32, reset: 0x00000000, access: write-only
32/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BS[15]
w |
BS[14]
w |
BS[13]
w |
BS[12]
w |
BS[11]
w |
BS[10]
w |
BS[9]
w |
BS[8]
w |
BS[7]
w |
BS[6]
w |
BS[5]
w |
BS[4]
w |
BS[3]
w |
BS[2]
w |
BS[1]
w |
BS[0]
w |
Bit 0: Port x set pin 0.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 1: Port x set pin 1.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 2: Port x set pin 2.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 3: Port x set pin 3.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 4: Port x set pin 4.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 5: Port x set pin 5.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 6: Port x set pin 6.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 7: Port x set pin 7.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 8: Port x set pin 8.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 9: Port x set pin 9.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 10: Port x set pin 10.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 11: Port x set pin 11.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 12: Port x set pin 12.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 13: Port x set pin 13.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 14: Port x set pin 14.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 15: Port x set pin 15.
Allowed values:
1: Set: Sets the corresponding ODx bit
Bit 16: Port x reset pin 0.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 17: Port x reset pin 1.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 18: Port x reset pin 2.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 19: Port x reset pin 3.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 20: Port x reset pin 4.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 21: Port x reset pin 5.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 22: Port x reset pin 6.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 23: Port x reset pin 7.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 24: Port x reset pin 8.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 25: Port x reset pin 9.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 26: Port x reset pin 10.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 27: Port x reset pin 11.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 28: Port x reset pin 12.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 29: Port x reset pin 13.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 30: Port x reset pin 14.
Allowed values:
1: Reset: Resets the corresponding ODx bit
Bit 31: Port x reset pin 15.
Allowed values:
1: Reset: Resets the corresponding ODx bit
GPIO port configuration lock register
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
17/17 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LCKK
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LCK[15]
rw |
LCK[14]
rw |
LCK[13]
rw |
LCK[12]
rw |
LCK[11]
rw |
LCK[10]
rw |
LCK[9]
rw |
LCK[8]
rw |
LCK[7]
rw |
LCK[6]
rw |
LCK[5]
rw |
LCK[4]
rw |
LCK[3]
rw |
LCK[2]
rw |
LCK[1]
rw |
LCK[0]
rw |
Bit 0: Port x lock pin 0.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 1: Port x lock pin 1.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 2: Port x lock pin 2.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 3: Port x lock pin 3.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 4: Port x lock pin 4.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 5: Port x lock pin 5.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 6: Port x lock pin 6.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 7: Port x lock pin 7.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 8: Port x lock pin 8.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 9: Port x lock pin 9.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 10: Port x lock pin 10.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 11: Port x lock pin 11.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 12: Port x lock pin 12.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 13: Port x lock pin 13.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 14: Port x lock pin 14.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 15: Port x lock pin 15.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 16: Port x lock bit y (y= 0..15).
Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active
GPIO alternate function low register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AFR[EL7]
rw |
AFR[EL6]
rw |
AFR[EL5]
rw |
AFR[EL4]
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AFR[EL3]
rw |
AFR[EL2]
rw |
AFR[EL1]
rw |
AFR[EL0]
rw |
Bits 0-3: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 4-7: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 8-11: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 12-15: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 16-19: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 20-23: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 24-27: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 28-31: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
GPIO alternate function high register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AFR[EL15]
rw |
AFR[EL14]
rw |
AFR[EL13]
rw |
AFR[EL12]
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AFR[EL11]
rw |
AFR[EL10]
rw |
AFR[EL9]
rw |
AFR[EL8]
rw |
Bits 0-3: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 4-7: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 8-11: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 12-15: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 16-19: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 20-23: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 24-27: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
Bits 28-31: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
port bit reset register
Offset: 0x28, size: 32, reset: 0x00000000, access: write-only
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
Bit 0: Port x reset pin 0.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 1: Port x reset pin 1.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 2: Port x reset pin 2.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 3: Port x reset pin 3.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 4: Port x reset pin 4.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 5: Port x reset pin 5.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 6: Port x reset pin 6.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 7: Port x reset pin 7.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 8: Port x reset pin 8.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 9: Port x reset pin 9.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 10: Port x reset pin 10.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 11: Port x reset pin 11.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 12: Port x reset pin 12.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 13: Port x reset pin 13.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 14: Port x reset pin 14.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 15: Port x reset pin 15.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
0x40005400: Inter-integrated circuit
76/76 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CR1 | ||||||||||||||||||||||||||||||||
0x4 | CR2 | ||||||||||||||||||||||||||||||||
0x8 | OAR1 | ||||||||||||||||||||||||||||||||
0xc | OAR2 | ||||||||||||||||||||||||||||||||
0x10 | TIMINGR | ||||||||||||||||||||||||||||||||
0x14 | TIMEOUTR | ||||||||||||||||||||||||||||||||
0x18 | ISR | ||||||||||||||||||||||||||||||||
0x1c | ICR | ||||||||||||||||||||||||||||||||
0x20 | PECR | ||||||||||||||||||||||||||||||||
0x24 | RXDR | ||||||||||||||||||||||||||||||||
0x28 | TXDR |
Control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
20/20 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PECEN
rw |
ALERTEN
rw |
SMBDEN
rw |
SMBHEN
rw |
GCEN
rw |
WUPEN
rw |
NOSTRETCH
rw |
SBC
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXDMAEN
rw |
TXDMAEN
rw |
ANFOFF
rw |
DNF
rw |
ERRIE
rw |
TCIE
rw |
STOPIE
rw |
NACKIE
rw |
ADDRIE
rw |
RXIE
rw |
TXIE
rw |
PE
rw |
Bit 0: Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles..
Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled
Bit 1: TX Interrupt enable.
Allowed values:
0: Disabled: Transmit (TXIS) interrupt disabled
1: Enabled: Transmit (TXIS) interrupt enabled
Bit 2: RX Interrupt enable.
Allowed values:
0: Disabled: Receive (RXNE) interrupt disabled
1: Enabled: Receive (RXNE) interrupt enabled
Bit 3: Address match Interrupt enable (slave only).
Allowed values:
0: Disabled: Address match (ADDR) interrupts disabled
1: Enabled: Address match (ADDR) interrupts enabled
Bit 4: Not acknowledge received Interrupt enable.
Allowed values:
0: Disabled: Not acknowledge (NACKF) received interrupts disabled
1: Enabled: Not acknowledge (NACKF) received interrupts enabled
Bit 5: Stop detection Interrupt enable.
Allowed values:
0: Disabled: Stop detection (STOPF) interrupt disabled
1: Enabled: Stop detection (STOPF) interrupt enabled
Bit 6: Transfer Complete interrupt enable Note: Any of these events generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR).
Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled
Bit 7: Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT).
Allowed values:
0: Disabled: Error detection interrupts disabled
1: Enabled: Error detection interrupts enabled
Bits 8-11: Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * tI2CCLK ... Note: If the analog filter is also enabled, the digital filter is added to the analog filter. This filter can only be programmed when the I2C is disabled (PE = 0)..
Allowed values:
0: NoFilter: Digital filter disabled
1: Filter1: Digital filter enabled and filtering capability up to 1 tI2CCLK
2: Filter2: Digital filter enabled and filtering capability up to 2 tI2CCLK
3: Filter3: Digital filter enabled and filtering capability up to 3 tI2CCLK
4: Filter4: Digital filter enabled and filtering capability up to 4 tI2CCLK
5: Filter5: Digital filter enabled and filtering capability up to 5 tI2CCLK
6: Filter6: Digital filter enabled and filtering capability up to 6 tI2CCLK
7: Filter7: Digital filter enabled and filtering capability up to 7 tI2CCLK
8: Filter8: Digital filter enabled and filtering capability up to 8 tI2CCLK
9: Filter9: Digital filter enabled and filtering capability up to 9 tI2CCLK
10: Filter10: Digital filter enabled and filtering capability up to 10 tI2CCLK
11: Filter11: Digital filter enabled and filtering capability up to 11 tI2CCLK
12: Filter12: Digital filter enabled and filtering capability up to 12 tI2CCLK
13: Filter13: Digital filter enabled and filtering capability up to 13 tI2CCLK
14: Filter14: Digital filter enabled and filtering capability up to 14 tI2CCLK
15: Filter15: Digital filter enabled and filtering capability up to 15 tI2CCLK
Bit 12: Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0)..
Allowed values:
0: Enabled: Analog noise filter enabled
1: Disabled: Analog noise filter disabled
Bit 14: DMA transmission requests enable.
Allowed values:
0: Disabled: DMA mode disabled for transmission
1: Enabled: DMA mode enabled for transmission
Bit 15: DMA reception requests enable.
Allowed values:
0: Disabled: DMA mode disabled for reception
1: Enabled: DMA mode enabled for reception
Bit 16: Slave byte control This bit is used to enable hardware byte control in slave mode..
Allowed values:
0: Disabled: Slave byte control disabled
1: Enabled: Slave byte control enabled
Bit 17: Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0)..
Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled
Bit 18: Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to . Note: WUPEN can be set only when DNF = '0000â.
Allowed values:
0: Disabled: Wakeup from Stop mode disabled
1: Enabled: Wakeup from Stop mode enabled
Bit 19: General call enable.
Allowed values:
0: Disabled: General call disabled. Address 0b00000000 is NACKed
1: Enabled: General call enabled. Address 0b00000000 is ACKed
Bit 20: SMBus Host Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to ..
Allowed values:
0: Disabled: Host address disabled. Address 0b0001000x is NACKed
1: Enabled: Host address enabled. Address 0b0001000x is ACKed
Bit 21: SMBus Device Default Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to ..
Allowed values:
0: Disabled: Device default address disabled. Address 0b1100001x is NACKed
1: Enabled: Device default address enabled. Address 0b1100001x is ACKed
Bit 22: SMBus alert enable Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to ..
Allowed values:
0: Disabled: In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
1: Enabled: In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported
Bit 23: PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to ..
Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled
Control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
11/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PECBYTE
rw |
AUTOEND
rw |
RELOAD
rw |
NBYTES
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NACK
rw |
STOP
rw |
START
rw |
HEAD10R
rw |
ADD10
rw |
RD_WRN
rw |
SADD
rw |
Bits 0-9: Slave address (master mode) In 7-bit addressing mode (ADD10 = 0): SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9], SADD[8] and SADD[0] are don't care. In 10-bit addressing mode (ADD10 = 1): SADD[9:0] should be written with the 10-bit slave address to be sent. Note: Changing these bits when the START bit is set is not allowed..
Allowed values: 0x0-0x3ff
Bit 10: Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed..
Allowed values:
0: Write: Master requests a write transfer
1: Read: Master requests a read transfer
Bit 11: 10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed..
Allowed values:
0: Bit7: The master operates in 7-bit addressing mode
1: Bit10: The master operates in 10-bit addressing mode
Bit 12: 10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed..
Allowed values:
0: Complete: The master sends the complete 10 bit slave address read sequence
1: Partial: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction
Bit 13: Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing '1â to the ADDRCF bit in the I2C_ICR register. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit generates a START condition once the bus is free. Note: Writing '0â to this bit has no effect. The START bit can be set even if the bus is BUSY or I2C is in slave mode. This bit has no effect when RELOAD is set..
Allowed values:
0: NoStart: No Start generation
1: Start: Restart/Start generation
Bit 14: Stop generation (master mode) The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. In Master Mode: Note: Writing '0â to this bit has no effect..
Allowed values:
0: NoStop: No Stop generation
1: Stop: Stop generation after current byte transfer
Bit 15: NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. Note: Writing '0â to this bit has no effect. This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value..
Allowed values:
0: Ack: an ACK is sent after current received byte
1: Nack: a NACK is sent after current received byte
Bits 16-23: Number of bytes The number of bytes to be transmitted/received is programmed there. This field is donât care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed..
Allowed values: 0x0-0xff
Bit 24: NBYTES reload mode This bit is set and cleared by software..
Allowed values:
0: Completed: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)
1: NotCompleted: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)
Bit 25: Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set..
Allowed values:
0: Software: Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low
1: Automatic: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred
Bit 26: Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. Note: Writing '0â to this bit has no effect. This bit has no effect when RELOAD is set. This bit has no effect is slave mode when SBC=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to ..
Allowed values:
0: NoPec: No PEC transfer
1: Pec: PEC transmission/reception is requested
Own address register 1
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
3/3 fields covered.
Bits 0-9: Interface own slave address 7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. The bits OA1[9], OA1[8] and OA1[0] are don't care. 10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address. Note: These bits can be written only when OA1EN=0..
Allowed values: 0x0-0x3ff
Bit 10: Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0..
Allowed values:
0: Bit7: Own address 1 is a 7-bit address
1: Bit10: Own address 1 is a 10-bit address
Bit 15: Own Address 1 enable.
Allowed values:
0: Disabled: Own address 1 disabled. The received slave address OA1 is NACKed
1: Enabled: Own address 1 enabled. The received slave address OA1 is ACKed
Own address register 2
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
3/3 fields covered.
Bits 1-7: Interface address 7-bit addressing mode: 7-bit address Note: These bits can be written only when OA2EN=0..
Allowed values: 0x0-0x7f
Bits 8-10: Own Address 2 masks Note: These bits can be written only when OA2EN=0. As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches..
Allowed values:
0: NoMask: No mask
1: Mask1: OA2[1] is masked and don’t care. Only OA2[7:2] are compared
2: Mask2: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
3: Mask3: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
4: Mask4: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
5: Mask5: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
6: Mask6: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
7: Mask7: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged
Bit 15: Own Address 2 enable.
Allowed values:
0: Disabled: Own address 2 disabled. The received slave address OA2 is NACKed
1: Enabled: Own address 2 enabled. The received slave address OA2 is ACKed
Timing register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
5/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PRESC
rw |
SCLDEL
rw |
SDADEL
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SCLH
rw |
SCLL
rw |
Bits 0-7: SCL low period (master mode).
Allowed values: 0x0-0xff
Bits 8-15: SCL high period (master mode).
Allowed values: 0x0-0xff
Bits 16-19: Data hold time.
Allowed values: 0x0-0xf
Bits 20-23: Data setup time.
Allowed values: 0x0-0xf
Bits 28-31: Timing prescaler.
Allowed values: 0x0-0xf
Status register 1
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
5/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TEXTEN
rw |
TIMEOUTB
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TIMOUTEN
rw |
TIDLE
rw |
TIMEOUTA
rw |
Bits 0-11: Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0..
Allowed values: 0x0-0xfff
Bit 12: Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0..
Allowed values:
0: Disabled: TIMEOUTA is used to detect SCL low timeout
1: Enabled: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)
Bit 15: Clock timeout enable.
Allowed values:
0: Disabled: SCL timeout detection is disabled
1: Enabled: SCL timeout detection is enabled
Bits 16-27: Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0..
Allowed values: 0x0-0xfff
Bit 31: Extended clock timeout enable.
Allowed values:
0: Disabled: Extended clock timeout detection is disabled
1: Enabled: Extended clock timeout detection is enabled
Interrupt and Status register
Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified
17/17 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADDCODE
r |
DIR
r |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BUSY
r |
ALERT
r |
TIMEOUT
r |
PECERR
r |
OVR
r |
ARLO
r |
BERR
r |
TCR
r |
TC
r |
STOPF
r |
NACKF
r |
ADDR
r |
RXNE
r |
TXIS
rw |
TXE
rw |
Bit 0: Transmit data register empty (transmitters).
Allowed values:
0: NotEmpty: TXDR register not empty
1: Empty: TXDR register empty
Bit 1: Transmit interrupt status (transmitters).
Allowed values:
0: NotEmpty: The TXDR register is not empty
1: Empty: The TXDR register is empty and the data to be transmitted must be written in the TXDR register
Bit 2: Receive data register not empty (receivers).
Allowed values:
0: Empty: The RXDR register is empty
1: NotEmpty: Received data is copied into the RXDR register, and is ready to be read
Bit 3: Address matched (slave mode).
Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses
Bit 4: Not acknowledge received flag.
Allowed values:
0: NoNack: No NACK has been received
1: Nack: NACK has been received
Bit 5: Stop detection flag.
Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected
Bit 6: Transfer Complete (master mode).
Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered
Bit 7: Transfer Complete Reload.
Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered
Bit 8: Bus error.
Allowed values:
0: NoError: No bus error
1: Error: Misplaced Start and Stop condition is detected
Bit 9: Arbitration lost.
Allowed values:
0: NotLost: No arbitration lost
1: Lost: Arbitration lost
Bit 10: Overrun/Underrun (slave mode).
Allowed values:
0: NoOverrun: No overrun/underrun error occurs
1: Overrun: slave mode with NOSTRETCH=1, when an overrun/underrun error occurs
Bit 11: PEC Error in reception.
Allowed values:
0: Match: Received PEC does match with PEC register
1: NoMatch: Received PEC does not match with PEC register
Bit 12: Timeout or t_low detection flag.
Allowed values:
0: NoTimeout: No timeout occured
1: Timeout: Timeout occured
Bit 13: SMBus alert.
Allowed values:
0: NoAlert: SMBA alert is not detected
1: Alert: SMBA alert event is detected on SMBA pin
Bit 15: Bus busy.
Allowed values:
0: NotBusy: No communication is in progress on the bus
1: Busy: A communication is in progress on the bus
Bit 16: Transfer direction (Slave mode) This flag is updated when an address match event occurs (ADDR=1)..
Allowed values:
0: Write: Write transfer, slave enters receiver mode
1: Read: Read transfer, slave enters transmitter mode
Bits 17-23: Address match code (Slave mode).
Allowed values: 0x0-0x7f
Interrupt clear register
Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only
9/9 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ALERTCF
w |
TIMOUTCF
w |
PECCF
w |
OVRCF
w |
ARLOCF
w |
BERRCF
w |
STOPCF
w |
NACKCF
w |
ADDRCF
w |
Bit 3: Address Matched flag clear.
Allowed values:
1: Clear: Clears the ADDR flag in ISR register
Bit 4: Not Acknowledge flag clear.
Allowed values:
1: Clear: Clears the NACK flag in ISR register
Bit 5: Stop detection flag clear.
Allowed values:
1: Clear: Clears the STOP flag in ISR register
Bit 8: Bus error flag clear.
Allowed values:
1: Clear: Clears the BERR flag in ISR register
Bit 9: Arbitration lost flag clear.
Allowed values:
1: Clear: Clears the ARLO flag in ISR register
Bit 10: Overrun/Underrun flag clear.
Allowed values:
1: Clear: Clears the OVR flag in ISR register
Bit 11: PEC Error flag clear.
Allowed values:
1: Clear: Clears the PEC flag in ISR register
Bit 12: Timeout detection flag clear.
Allowed values:
1: Clear: Clears the TIMOUT flag in ISR register
Bit 13: Alert flag clear.
Allowed values:
1: Clear: Clears the ALERT flag in ISR register
PEC register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PEC
r |
Receive data register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXDATA
r |
Transmit data register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TXDATA
rw |
0x40005800: Inter-integrated circuit
76/76 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CR1 | ||||||||||||||||||||||||||||||||
0x4 | CR2 | ||||||||||||||||||||||||||||||||
0x8 | OAR1 | ||||||||||||||||||||||||||||||||
0xc | OAR2 | ||||||||||||||||||||||||||||||||
0x10 | TIMINGR | ||||||||||||||||||||||||||||||||
0x14 | TIMEOUTR | ||||||||||||||||||||||||||||||||
0x18 | ISR | ||||||||||||||||||||||||||||||||
0x1c | ICR | ||||||||||||||||||||||||||||||||
0x20 | PECR | ||||||||||||||||||||||||||||||||
0x24 | RXDR | ||||||||||||||||||||||||||||||||
0x28 | TXDR |
Control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
20/20 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PECEN
rw |
ALERTEN
rw |
SMBDEN
rw |
SMBHEN
rw |
GCEN
rw |
WUPEN
rw |
NOSTRETCH
rw |
SBC
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXDMAEN
rw |
TXDMAEN
rw |
ANFOFF
rw |
DNF
rw |
ERRIE
rw |
TCIE
rw |
STOPIE
rw |
NACKIE
rw |
ADDRIE
rw |
RXIE
rw |
TXIE
rw |
PE
rw |
Bit 0: Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles..
Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled
Bit 1: TX Interrupt enable.
Allowed values:
0: Disabled: Transmit (TXIS) interrupt disabled
1: Enabled: Transmit (TXIS) interrupt enabled
Bit 2: RX Interrupt enable.
Allowed values:
0: Disabled: Receive (RXNE) interrupt disabled
1: Enabled: Receive (RXNE) interrupt enabled
Bit 3: Address match Interrupt enable (slave only).
Allowed values:
0: Disabled: Address match (ADDR) interrupts disabled
1: Enabled: Address match (ADDR) interrupts enabled
Bit 4: Not acknowledge received Interrupt enable.
Allowed values:
0: Disabled: Not acknowledge (NACKF) received interrupts disabled
1: Enabled: Not acknowledge (NACKF) received interrupts enabled
Bit 5: Stop detection Interrupt enable.
Allowed values:
0: Disabled: Stop detection (STOPF) interrupt disabled
1: Enabled: Stop detection (STOPF) interrupt enabled
Bit 6: Transfer Complete interrupt enable Note: Any of these events generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR).
Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled
Bit 7: Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT).
Allowed values:
0: Disabled: Error detection interrupts disabled
1: Enabled: Error detection interrupts enabled
Bits 8-11: Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * tI2CCLK ... Note: If the analog filter is also enabled, the digital filter is added to the analog filter. This filter can only be programmed when the I2C is disabled (PE = 0)..
Allowed values:
0: NoFilter: Digital filter disabled
1: Filter1: Digital filter enabled and filtering capability up to 1 tI2CCLK
2: Filter2: Digital filter enabled and filtering capability up to 2 tI2CCLK
3: Filter3: Digital filter enabled and filtering capability up to 3 tI2CCLK
4: Filter4: Digital filter enabled and filtering capability up to 4 tI2CCLK
5: Filter5: Digital filter enabled and filtering capability up to 5 tI2CCLK
6: Filter6: Digital filter enabled and filtering capability up to 6 tI2CCLK
7: Filter7: Digital filter enabled and filtering capability up to 7 tI2CCLK
8: Filter8: Digital filter enabled and filtering capability up to 8 tI2CCLK
9: Filter9: Digital filter enabled and filtering capability up to 9 tI2CCLK
10: Filter10: Digital filter enabled and filtering capability up to 10 tI2CCLK
11: Filter11: Digital filter enabled and filtering capability up to 11 tI2CCLK
12: Filter12: Digital filter enabled and filtering capability up to 12 tI2CCLK
13: Filter13: Digital filter enabled and filtering capability up to 13 tI2CCLK
14: Filter14: Digital filter enabled and filtering capability up to 14 tI2CCLK
15: Filter15: Digital filter enabled and filtering capability up to 15 tI2CCLK
Bit 12: Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0)..
Allowed values:
0: Enabled: Analog noise filter enabled
1: Disabled: Analog noise filter disabled
Bit 14: DMA transmission requests enable.
Allowed values:
0: Disabled: DMA mode disabled for transmission
1: Enabled: DMA mode enabled for transmission
Bit 15: DMA reception requests enable.
Allowed values:
0: Disabled: DMA mode disabled for reception
1: Enabled: DMA mode enabled for reception
Bit 16: Slave byte control This bit is used to enable hardware byte control in slave mode..
Allowed values:
0: Disabled: Slave byte control disabled
1: Enabled: Slave byte control enabled
Bit 17: Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0)..
Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled
Bit 18: Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to . Note: WUPEN can be set only when DNF = '0000â.
Allowed values:
0: Disabled: Wakeup from Stop mode disabled
1: Enabled: Wakeup from Stop mode enabled
Bit 19: General call enable.
Allowed values:
0: Disabled: General call disabled. Address 0b00000000 is NACKed
1: Enabled: General call enabled. Address 0b00000000 is ACKed
Bit 20: SMBus Host Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to ..
Allowed values:
0: Disabled: Host address disabled. Address 0b0001000x is NACKed
1: Enabled: Host address enabled. Address 0b0001000x is ACKed
Bit 21: SMBus Device Default Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to ..
Allowed values:
0: Disabled: Device default address disabled. Address 0b1100001x is NACKed
1: Enabled: Device default address enabled. Address 0b1100001x is ACKed
Bit 22: SMBus alert enable Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to ..
Allowed values:
0: Disabled: In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
1: Enabled: In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported
Bit 23: PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to ..
Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled
Control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
11/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PECBYTE
rw |
AUTOEND
rw |
RELOAD
rw |
NBYTES
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NACK
rw |
STOP
rw |
START
rw |
HEAD10R
rw |
ADD10
rw |
RD_WRN
rw |
SADD
rw |
Bits 0-9: Slave address (master mode) In 7-bit addressing mode (ADD10 = 0): SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9], SADD[8] and SADD[0] are don't care. In 10-bit addressing mode (ADD10 = 1): SADD[9:0] should be written with the 10-bit slave address to be sent. Note: Changing these bits when the START bit is set is not allowed..
Allowed values: 0x0-0x3ff
Bit 10: Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed..
Allowed values:
0: Write: Master requests a write transfer
1: Read: Master requests a read transfer
Bit 11: 10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed..
Allowed values:
0: Bit7: The master operates in 7-bit addressing mode
1: Bit10: The master operates in 10-bit addressing mode
Bit 12: 10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed..
Allowed values:
0: Complete: The master sends the complete 10 bit slave address read sequence
1: Partial: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction
Bit 13: Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing '1â to the ADDRCF bit in the I2C_ICR register. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit generates a START condition once the bus is free. Note: Writing '0â to this bit has no effect. The START bit can be set even if the bus is BUSY or I2C is in slave mode. This bit has no effect when RELOAD is set..
Allowed values:
0: NoStart: No Start generation
1: Start: Restart/Start generation
Bit 14: Stop generation (master mode) The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. In Master Mode: Note: Writing '0â to this bit has no effect..
Allowed values:
0: NoStop: No Stop generation
1: Stop: Stop generation after current byte transfer
Bit 15: NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. Note: Writing '0â to this bit has no effect. This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value..
Allowed values:
0: Ack: an ACK is sent after current received byte
1: Nack: a NACK is sent after current received byte
Bits 16-23: Number of bytes The number of bytes to be transmitted/received is programmed there. This field is donât care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed..
Allowed values: 0x0-0xff
Bit 24: NBYTES reload mode This bit is set and cleared by software..
Allowed values:
0: Completed: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)
1: NotCompleted: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)
Bit 25: Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set..
Allowed values:
0: Software: Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low
1: Automatic: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred
Bit 26: Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. Note: Writing '0â to this bit has no effect. This bit has no effect when RELOAD is set. This bit has no effect is slave mode when SBC=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to ..
Allowed values:
0: NoPec: No PEC transfer
1: Pec: PEC transmission/reception is requested
Own address register 1
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
3/3 fields covered.
Bits 0-9: Interface own slave address 7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. The bits OA1[9], OA1[8] and OA1[0] are don't care. 10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address. Note: These bits can be written only when OA1EN=0..
Allowed values: 0x0-0x3ff
Bit 10: Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0..
Allowed values:
0: Bit7: Own address 1 is a 7-bit address
1: Bit10: Own address 1 is a 10-bit address
Bit 15: Own Address 1 enable.
Allowed values:
0: Disabled: Own address 1 disabled. The received slave address OA1 is NACKed
1: Enabled: Own address 1 enabled. The received slave address OA1 is ACKed
Own address register 2
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
3/3 fields covered.
Bits 1-7: Interface address 7-bit addressing mode: 7-bit address Note: These bits can be written only when OA2EN=0..
Allowed values: 0x0-0x7f
Bits 8-10: Own Address 2 masks Note: These bits can be written only when OA2EN=0. As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches..
Allowed values:
0: NoMask: No mask
1: Mask1: OA2[1] is masked and don’t care. Only OA2[7:2] are compared
2: Mask2: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
3: Mask3: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
4: Mask4: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
5: Mask5: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
6: Mask6: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
7: Mask7: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged
Bit 15: Own Address 2 enable.
Allowed values:
0: Disabled: Own address 2 disabled. The received slave address OA2 is NACKed
1: Enabled: Own address 2 enabled. The received slave address OA2 is ACKed
Timing register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
5/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PRESC
rw |
SCLDEL
rw |
SDADEL
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SCLH
rw |
SCLL
rw |
Bits 0-7: SCL low period (master mode).
Allowed values: 0x0-0xff
Bits 8-15: SCL high period (master mode).
Allowed values: 0x0-0xff
Bits 16-19: Data hold time.
Allowed values: 0x0-0xf
Bits 20-23: Data setup time.
Allowed values: 0x0-0xf
Bits 28-31: Timing prescaler.
Allowed values: 0x0-0xf
Status register 1
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
5/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TEXTEN
rw |
TIMEOUTB
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TIMOUTEN
rw |
TIDLE
rw |
TIMEOUTA
rw |
Bits 0-11: Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0..
Allowed values: 0x0-0xfff
Bit 12: Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0..
Allowed values:
0: Disabled: TIMEOUTA is used to detect SCL low timeout
1: Enabled: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)
Bit 15: Clock timeout enable.
Allowed values:
0: Disabled: SCL timeout detection is disabled
1: Enabled: SCL timeout detection is enabled
Bits 16-27: Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0..
Allowed values: 0x0-0xfff
Bit 31: Extended clock timeout enable.
Allowed values:
0: Disabled: Extended clock timeout detection is disabled
1: Enabled: Extended clock timeout detection is enabled
Interrupt and Status register
Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified
17/17 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADDCODE
r |
DIR
r |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BUSY
r |
ALERT
r |
TIMEOUT
r |
PECERR
r |
OVR
r |
ARLO
r |
BERR
r |
TCR
r |
TC
r |
STOPF
r |
NACKF
r |
ADDR
r |
RXNE
r |
TXIS
rw |
TXE
rw |
Bit 0: Transmit data register empty (transmitters).
Allowed values:
0: NotEmpty: TXDR register not empty
1: Empty: TXDR register empty
Bit 1: Transmit interrupt status (transmitters).
Allowed values:
0: NotEmpty: The TXDR register is not empty
1: Empty: The TXDR register is empty and the data to be transmitted must be written in the TXDR register
Bit 2: Receive data register not empty (receivers).
Allowed values:
0: Empty: The RXDR register is empty
1: NotEmpty: Received data is copied into the RXDR register, and is ready to be read
Bit 3: Address matched (slave mode).
Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses
Bit 4: Not acknowledge received flag.
Allowed values:
0: NoNack: No NACK has been received
1: Nack: NACK has been received
Bit 5: Stop detection flag.
Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected
Bit 6: Transfer Complete (master mode).
Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered
Bit 7: Transfer Complete Reload.
Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered
Bit 8: Bus error.
Allowed values:
0: NoError: No bus error
1: Error: Misplaced Start and Stop condition is detected
Bit 9: Arbitration lost.
Allowed values:
0: NotLost: No arbitration lost
1: Lost: Arbitration lost
Bit 10: Overrun/Underrun (slave mode).
Allowed values:
0: NoOverrun: No overrun/underrun error occurs
1: Overrun: slave mode with NOSTRETCH=1, when an overrun/underrun error occurs
Bit 11: PEC Error in reception.
Allowed values:
0: Match: Received PEC does match with PEC register
1: NoMatch: Received PEC does not match with PEC register
Bit 12: Timeout or t_low detection flag.
Allowed values:
0: NoTimeout: No timeout occured
1: Timeout: Timeout occured
Bit 13: SMBus alert.
Allowed values:
0: NoAlert: SMBA alert is not detected
1: Alert: SMBA alert event is detected on SMBA pin
Bit 15: Bus busy.
Allowed values:
0: NotBusy: No communication is in progress on the bus
1: Busy: A communication is in progress on the bus
Bit 16: Transfer direction (Slave mode) This flag is updated when an address match event occurs (ADDR=1)..
Allowed values:
0: Write: Write transfer, slave enters receiver mode
1: Read: Read transfer, slave enters transmitter mode
Bits 17-23: Address match code (Slave mode).
Allowed values: 0x0-0x7f
Interrupt clear register
Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only
9/9 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ALERTCF
w |
TIMOUTCF
w |
PECCF
w |
OVRCF
w |
ARLOCF
w |
BERRCF
w |
STOPCF
w |
NACKCF
w |
ADDRCF
w |
Bit 3: Address Matched flag clear.
Allowed values:
1: Clear: Clears the ADDR flag in ISR register
Bit 4: Not Acknowledge flag clear.
Allowed values:
1: Clear: Clears the NACK flag in ISR register
Bit 5: Stop detection flag clear.
Allowed values:
1: Clear: Clears the STOP flag in ISR register
Bit 8: Bus error flag clear.
Allowed values:
1: Clear: Clears the BERR flag in ISR register
Bit 9: Arbitration lost flag clear.
Allowed values:
1: Clear: Clears the ARLO flag in ISR register
Bit 10: Overrun/Underrun flag clear.
Allowed values:
1: Clear: Clears the OVR flag in ISR register
Bit 11: PEC Error flag clear.
Allowed values:
1: Clear: Clears the PEC flag in ISR register
Bit 12: Timeout detection flag clear.
Allowed values:
1: Clear: Clears the TIMOUT flag in ISR register
Bit 13: Alert flag clear.
Allowed values:
1: Clear: Clears the ALERT flag in ISR register
PEC register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PEC
r |
Receive data register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXDATA
r |
Transmit data register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TXDATA
rw |
0x40003000: Independent watchdog
7/7 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | KR | ||||||||||||||||||||||||||||||||
0x4 | PR | ||||||||||||||||||||||||||||||||
0x8 | RLR | ||||||||||||||||||||||||||||||||
0xc | SR | ||||||||||||||||||||||||||||||||
0x10 | WINR |
Key register
Offset: 0x0, size: 32, reset: 0x00000000, access: write-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KEY
w |
Prescaler register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PR
rw |
Bits 0-2: Prescaler divider These bits are write access protected see . They are written by software to select the prescaler divider feeding the counter clock. PVU bit of the must be reset in order to be able to change the prescaler divider. Note: Reading this register returns the prescaler value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the PVU bit in the status register (IWDG_SR) is reset..
Allowed values:
0: DivideBy4: Divider /4
1: DivideBy8: Divider /8
2: DivideBy16: Divider /16
3: DivideBy32: Divider /32
4: DivideBy64: Divider /64
5: DivideBy128: Divider /128
6: DivideBy256: Divider /256
Reload register
Offset: 0x8, size: 32, reset: 0x00000FFF, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RL
rw |
Status register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-only
3/3 fields covered.
Bit 0: Watchdog prescaler value update This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by hardware when the prescaler update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Prescaler value can be updated only when PVU bit is reset..
Bit 1: Watchdog counter reload value update This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Reload value can be updated only when RVU bit is reset..
Bit 2: Watchdog counter window value update This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Window value can be updated only when WVU bit is reset..
Window register
Offset: 0x10, size: 32, reset: 0x00000FFF, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WIN
rw |
0x40012c00: Advanced-timers
48/181 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CR1 | ||||||||||||||||||||||||||||||||
0x4 | CR2 | ||||||||||||||||||||||||||||||||
0x8 | SMCR | ||||||||||||||||||||||||||||||||
0xc | DIER | ||||||||||||||||||||||||||||||||
0x10 | SR | ||||||||||||||||||||||||||||||||
0x14 | EGR | ||||||||||||||||||||||||||||||||
0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
0x1c | CCMR2_Input | ||||||||||||||||||||||||||||||||
0x1c | CCMR2_Output | ||||||||||||||||||||||||||||||||
0x20 | CCER | ||||||||||||||||||||||||||||||||
0x24 | CNT | ||||||||||||||||||||||||||||||||
0x28 | PSC | ||||||||||||||||||||||||||||||||
0x2c | ARR | ||||||||||||||||||||||||||||||||
0x30 | RCR | ||||||||||||||||||||||||||||||||
0x34 | CCR[1] | ||||||||||||||||||||||||||||||||
0x38 | CCR[2] | ||||||||||||||||||||||||||||||||
0x3c | CCR[3] | ||||||||||||||||||||||||||||||||
0x40 | CCR[4] | ||||||||||||||||||||||||||||||||
0x44 | BDTR | ||||||||||||||||||||||||||||||||
0x48 | DCR | ||||||||||||||||||||||||||||||||
0x4c | DMAR | ||||||||||||||||||||||||||||||||
0x54 | CCMR3_Output | ||||||||||||||||||||||||||||||||
0x58 | CCR5 | ||||||||||||||||||||||||||||||||
0x5c | CCR6 | ||||||||||||||||||||||||||||||||
0x60 | AF1 | ||||||||||||||||||||||||||||||||
0x64 | AF2 | ||||||||||||||||||||||||||||||||
0x68 | TISEL |
control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
8/9 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
UIFREMAP
rw |
CKD
rw |
ARPE
rw |
CMS
rw |
DIR
rw |
OPM
rw |
URS
rw |
UDIS
rw |
CEN
rw |
Bit 0: Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware..
Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled
Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..
Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled
Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.
Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request
Bit 3: One pulse mode.
Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)
Bit 4: Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode..
Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter
Bits 5-6: Center-aligned mode selection Note: Switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) is not allowed.
Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
Bit 7: Auto-reload preload enable.
Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered
Bits 8-9: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (ETR, TIx): Note: tDTS = 1/fDTS, tCK_INT = 1/fCK_INT..
Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT
Bit 11: UIF status bit remapping.
control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
9/15 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MMS2
rw |
OIS[6]
rw |
OIS[5]
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OIS[4]
rw |
OIS[3]N
rw |
OIS[3]
rw |
OIS[2]N
rw |
OIS[2]
rw |
OIS[1]N
rw |
OIS[1]
rw |
TI1S
rw |
MMS
rw |
CCDS
rw |
CCUS
rw |
CCPC
rw |
Bit 0: Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output..
Bit 2: Capture/compare control update selection Note: This bit acts only on channels that have a complementary output..
Bit 3: Capture/compare DMA selection.
Bits 4-6: Master mode selection These bits allow selected information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer..
Bit 7: TI1 selection.
Bit 8: Output Idle state (OC1 output).
Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
Bit 9: Output Idle state (OC1N output).
Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0
Bit 10: Output Idle state (OC2 output).
Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
Bit 11: Output Idle state (OC2N output).
Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0
Bit 12: Output Idle state (OC3 output).
Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
Bit 13: Output Idle state (OC3N output).
Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0
Bit 14: Output Idle state (OC4 output).
Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
Bit 16: Output Idle state (OC5 output).
Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
Bit 18: Output Idle state (OC6 output).
Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
Bits 20-23: Master mode selection 2 These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer..
slave mode control register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
0/10 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TS2
rw |
SMS2
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ETP
rw |
ECE
rw |
ETPS
rw |
ETF
rw |
MSM
rw |
TS1
rw |
OCCS
rw |
SMS1
rw |
Bits 0-2: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..
Bit 3: OCREF clear selection This bit is used to select the OCREF clear source..
Bits 4-6: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..
Bit 7: Master/slave mode.
Bits 8-11: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.
Bits 12-13: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of fCK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks..
Bit 14: External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF..
Bit 15: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations.
Bit 16: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..
Bits 20-21: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..
DMA/Interrupt enable register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
1/15 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TDE
rw |
COMDE
rw |
CC[4]DE
rw |
CC[3]DE
rw |
CC[2]DE
rw |
CC[1]DE
rw |
UDE
rw |
BIE
rw |
TIE
rw |
COMIE
rw |
CC[4]IE
rw |
CC[3]IE
rw |
CC[2]IE
rw |
CC[1]IE
rw |
UIE
rw |
Bit 0: Update interrupt enable.
Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled
Bit 1: Capture/Compare 1 interrupt enable.
Bit 2: Capture/Compare 2 interrupt enable.
Bit 3: Capture/Compare 3 interrupt enable.
Bit 4: Capture/Compare 4 interrupt enable.
Bit 5: COM interrupt enable.
Bit 6: Trigger interrupt enable.
Bit 7: Break interrupt enable.
Bit 8: Update DMA request enable.
Bit 9: Capture/Compare 1 DMA request enable.
Bit 10: Capture/Compare 2 DMA request enable.
Bit 11: Capture/Compare 3 DMA request enable.
Bit 12: Capture/Compare 4 DMA request enable.
Bit 13: COM DMA request enable.
Bit 14: Trigger DMA request enable.
status register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
1/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CC6IF
rw |
CC5IF
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SBIF
rw |
CC[4]OF
rw |
CC[3]OF
rw |
CC[2]OF
rw |
CC[1]OF
rw |
B2IF
rw |
BIF
rw |
TIF
rw |
COMIF
rw |
CC[4]IF
rw |
CC[3]IF
rw |
CC[2]IF
rw |
CC[1]IF
rw |
UIF
rw |
Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM1_SMCRTIMx_SMCR)N/A), if URS=0 and UDIS=0 in the TIMx_CR1 register..
Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending
Bit 1: Capture/compare 1 interrupt flag.
Bit 2: Capture/compare 2 interrupt flag.
Bit 3: Capture/compare 3 interrupt flag.
Bit 4: Capture/compare 4 interrupt flag.
Bit 5: COM interrupt flag This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE, CCxNE, OCxM - have been updated). It is cleared by software..
Bit 6: Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software..
Bit 7: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active..
Bit 8: Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active..
Bit 9: Capture/Compare 1 overcapture flag.
Bit 10: Capture/Compare 2 overcapture flag.
Bit 11: Capture/Compare 3 overcapture flag.
Bit 12: Capture/Compare 4 overcapture flag.
Bit 13: System Break interrupt flag This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. This flag must be reset to re-start PWM operation..
Bit 16: Compare 5 interrupt flag Refer to CC1IF description (Note: Channel 5 can only be configured as output).
Bit 17: Compare 6 interrupt flag Refer to CC1IF description (Note: Channel 6 can only be configured as output).
event generation register
Offset: 0x14, size: 32, reset: 0x00000000, access: write-only
1/9 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
B2G
w |
BG
w |
TG
w |
COMG
w |
CC[4]G
w |
CC[3]G
w |
CC[2]G
w |
CC[1]G
w |
UG
w |
Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..
Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.
Bit 1: Capture/compare 1 generation.
Bit 2: Capture/compare 2 generation.
Bit 3: Capture/compare 3 generation.
Bit 4: Capture/compare 4 generation.
Bit 5: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware Note: This bit acts only on channels having a complementary output..
Bit 6: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..
Bit 7: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..
Bit 8: Break 2 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..
capture/compare mode register 1 (output mode)
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
0/6 fields covered.
capture/compare mode register 1 (output mode)
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
2/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OC[2]M_3
rw |
OC1M2
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OC[2]CE
rw |
OC[2]M
rw |
OC[2]PE
rw |
OC[2]FE
rw |
CC[2]S
rw |
OC[1]CE
rw |
OC1M1
rw |
OC[1]PE
rw |
OC[1]FE
rw |
CC[1]S
rw |
Bits 0-1: Capture/Compare 1 selection.
Bit 2: Output compare 1 fast enable.
Bit 3: Output compare 1 preload enable.
Bits 4-6: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from âfrozenâ mode to âPWMâ mode. Note: On channels having a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. Note: The OC1M[3] bit is not contiguous, located in bit 16..
Bit 7: Output compare 1 clear enable.
Bits 8-9: Capture/Compare 2 selection.
Bit 10: Output compare 2 fast enable.
Bit 11: Output compare 2 preload enable.
Bits 12-14: Output compare 2 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bit 15: Output compare 2 clear enable.
Bit 16: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from âfrozenâ mode to âPWMâ mode. Note: On channels having a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. Note: The OC1M[3] bit is not contiguous, located in bit 16..
Bit 24: Output compare 2 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
capture/compare mode register 2 (output mode)
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
0/6 fields covered.
capture/compare mode register 2 (output mode)
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
4/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OC[4]M_3
rw |
OC[3]M_3
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OC[4]CE
rw |
OC[4]M
rw |
OC[4]PE
rw |
OC[4]FE
rw |
CC[4]S
rw |
OC[3]CE
rw |
OC[3]M
rw |
OC[3]PE
rw |
OC[3]FE
rw |
CC[3]S
rw |
Bits 0-1: Capture/Compare 3 selection.
Bit 2: Output compare 3 fast enable.
Bit 3: Output compare 3 preload enable.
Bits 4-6: Output compare 3 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bit 7: Output compare 3 clear enable.
Bits 8-9: Capture/Compare 4 selection.
Bit 10: Output compare 4 fast enable.
Bit 11: Output compare 4 preload enable.
Bits 12-14: Output compare 4 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bit 15: Output compare 4 clear enable.
Bit 16: Output compare 3 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
Bit 24: Output compare 4 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
capture/compare enable register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
0/19 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CC[6]P
rw |
CC[6]E
rw |
CC[5]P
rw |
CC[5]E
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CC[4]NP
rw |
CC[4]P
rw |
CC[4]E
rw |
CC[3]NP
rw |
CC[3]NE
rw |
CC[3]P
rw |
CC[3]E
rw |
CC[2]NP
rw |
CC[2]NE
rw |
CC[2]P
rw |
CC[2]E
rw |
CC[1]NP
rw |
CC[1]NE
rw |
CC[1]P
rw |
CC[1]E
rw |
Bit 0: Capture/Compare 1 output enable.
Bit 1: Capture/Compare 1 output Polarity.
Bit 2: Capture/Compare 1 complementary output enable.
Bit 3: Capture/Compare 1 output Polarity.
Bit 4: Capture/Compare 2 output enable.
Bit 5: Capture/Compare 2 output Polarity.
Bit 6: Capture/Compare 2 complementary output enable.
Bit 7: Capture/Compare 2 output Polarity.
Bit 8: Capture/Compare 3 output enable.
Bit 9: Capture/Compare 3 output Polarity.
Bit 10: Capture/Compare 3 complementary output enable.
Bit 11: Capture/Compare 3 output Polarity.
Bit 12: Capture/Compare 4 output enable.
Bit 13: Capture/Compare 4 output Polarity.
Bit 15: Capture/Compare 4 output Polarity.
Bit 16: Capture/Compare 5 output enable.
Bit 17: Capture/Compare 5 output Polarity.
Bit 20: Capture/Compare 6 output enable.
Bit 21: Capture/Compare 6 output Polarity.
counter
Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified
2/2 fields covered.
prescaler
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PSC
rw |
Bits 0-15: Prescaler value The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in âreset modeâ)..
Allowed values: 0x0-0xffff
auto-reload register
Offset: 0x2c, size: 32, reset: 0x0000FFFF, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ARR
rw |
repetition counter register
Offset: 0x30, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
REP
rw |
capture/compare register
Offset: 0x34, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CCR
rw |
capture/compare register
Offset: 0x38, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CCR
rw |
capture/compare register
Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CCR
rw |
capture/compare register
Offset: 0x40, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CCR
rw |
break and dead-time register
Offset: 0x44, size: 32, reset: 0x00000000, access: read-write
10/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BK2BID
rw |
BKBID
rw |
BK2DSRM
rw |
BKDSRM
rw |
BK2P
rw |
BK2E
rw |
BK2F
rw |
BKF
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MOE
rw |
AOE
rw |
BKP
rw |
BKE
rw |
OSSR
rw |
OSSI
rw |
LOCK
rw |
DTG
rw |
Bits 0-7: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tDTG with tDTG=tDTS. DTG[7:5]=10x => DT=(64+DTG[5:0])xtDTG with tDTG=2xtDTS. DTG[7:5]=110 => DT=(32+DTG[4:0])xtDTG with tDTG=8xtDTS. DTG[7:5]=111 => DT=(32+DTG[4:0])xtDTG with tDTG=16xtDTS. Example if tDTS=125 ns (8 MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 μs to 31750 ns by 250 ns steps, 32 μs to 63 μs by 1 μs steps, 64 μs to 126 μs by 2 μs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values: 0x0-0xff
Bits 8-9: Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset..
Allowed values:
0: Off: No bit is write protected
1: Level1: Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
2: Level2: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
3: Level3: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written
Bit 10: Off-state selection for Idle mode This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0: Disabled: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are forced to idle level
Bit 11: Off-state selection for Run mode This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0: Disabled: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are enabled with their inactive level
Bit 12: Break enable This bit enables the complete break protection (including all sources connected to bk_acth and BKIN sources, as per ). Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x disabled
Bit 13: Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high
Bit 14: Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0: Manual: MOE can be set only by software
1: Automatic: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)
Bit 15: Main output enable This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. In response to a break event or if MOE is written to 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A)..
Allowed values:
0: DisabledIdle: OC/OCN are disabled or forced idle depending on OSSI
1: Enabled: OC/OCN are enabled if CCxE/CCxNE are set
Bits 16-19: Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bits 20-23: Break 2 filter This bit-field defines the frequency used to sample BRK2 input and the length of the digital filter applied to BRK2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 24: Break 2 enable Note: The BRK2 must only be used with OSSR = OSSI = 1. Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x disabled
Bit 25: Break 2 polarity Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high
Bit 26: Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Bit 27: Break2 Disarm Refer to BKDSRM description.
Bit 28: Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Bit 29: Break2 bidirectional Refer to BKBID description.
DMA control register
Offset: 0x48, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
Bits 0-4: DMA base address This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ....
Bits 8-12: DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ... Example: Let us consider the following transfer: DBL = 7 bytes & DBA = TIMx_CR1. If DBL = 7 bytes and DBA = TIMx_CR1 represents the address of the byte to be transferred, the address of the transfer should be given by the following equation: (TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL In this example, 7 bytes are added to (TIMx_CR1 address) + DBA, which gives us the address from/to which the data is copied. In this case, the transfer is done to 7 registers starting from the following address: (TIMx_CR1 address) + DBA According to the configuration of the DMA Data Size, several cases may occur: If the DMA Data Size is configured in half-words, 16-bit data is transferred to each of the 7 registers. If the DMA Data Size is configured in bytes, the data is also transferred to 7 registers: the first register contains the first MSB byte, the second register, the first LSB byte and so on. So with the transfer Timer, one also has to specify the size of data transferred by DMA..
DMA address for full transfer
Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DMAB
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMAB
rw |
Bits 0-31: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR)..
capture/compare mode register 2 (output mode)
Offset: 0x54, size: 32, reset: 0x00000000, access: read-write
4/10 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OC[6]M_3
rw |
OC[5]M_3
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OC[6]CE
rw |
OC[6]M
rw |
OC[6]PE
rw |
OC[6]FE
rw |
OC[5]CE
rw |
OC[5]M
rw |
OC[5]PE
rw |
OC[5]FE
rw |
Bit 2: Output compare 5 fast enable.
Bit 3: Output compare 5 preload enable.
Bits 4-6: Output compare 5 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bit 7: Output compare 5 clear enable.
Bit 10: Output compare 6 fast enable.
Bit 11: Output compare 6 preload enable.
Bits 12-14: Output compare 6 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bit 15: Output compare 6 clear enable.
Bit 16: Output compare 5 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
Bit 24: Output compare 6 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
capture/compare register
Offset: 0x58, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GC5C3
rw |
GC5C2
rw |
GC5C1
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CCR
rw |
Bits 0-15: Capture/Compare value.
Bit 29: Group Channel 5 and Channel 1 Distortion on Channel 1 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals..
Bit 30: Group Channel 5 and Channel 2 Distortion on Channel 2 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals..
Bit 31: Group Channel 5 and Channel 3 Distortion on Channel 3 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2). Note: it is also possible to apply this distortion on combined PWM signals..
capture/compare register
Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CCR
rw |
TIM1 alternate function option register 1
Offset: 0x60, size: 32, reset: 0x00000001, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ETRSEL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ETRSEL
rw |
BKINP
rw |
BKINE
rw |
Bit 0: BRK BKIN input enable This bit enables the BKIN alternate function input for the timerâs BRK input. BKIN input is 'ORedâ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 9: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bits 14-17: ETR source selection These bits select the ETR input source. Others: Reserved Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
TIM1 alternate function option register 2
Offset: 0x64, size: 32, reset: 0x00000001, access: read-write
0/2 fields covered.
Bit 0: BRK2 BKIN input enable This bit enables the BKIN2 alternate function input for the timerâs BRK2 input. BKIN2 input is 'ORedâ with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 9: BRK2 BKIN2 input polarity This bit selects the BKIN2 alternate function input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
0x40002000: General purpose timers
11/31 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CR1 | ||||||||||||||||||||||||||||||||
0xc | DIER | ||||||||||||||||||||||||||||||||
0x10 | SR | ||||||||||||||||||||||||||||||||
0x14 | EGR | ||||||||||||||||||||||||||||||||
0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
0x20 | CCER | ||||||||||||||||||||||||||||||||
0x24 | CNT | ||||||||||||||||||||||||||||||||
0x28 | PSC | ||||||||||||||||||||||||||||||||
0x2c | ARR | ||||||||||||||||||||||||||||||||
0x34 | CCR[1] | ||||||||||||||||||||||||||||||||
0x68 | TISEL |
control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
6/7 fields covered.
Bit 0: Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware..
Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled
Bit 1: Update disable This bit is set and cleared by software to enable/disable update interrupt (UEV) event generation. Counter overflow Setting the UG bit. Buffered registers are then loaded with their preload values..
Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled
Bit 2: Update request source This bit is set and cleared by software to select the update interrupt (UEV) sources. Counter overflow Setting the UG bit.
Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request
Bit 3: One-pulse mode.
Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)
Bit 7: Auto-reload preload enable.
Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered
Bits 8-9: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (TIx),.
Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT
Bit 11: UIF status bit remapping.
DMA/Interrupt enable register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
1/2 fields covered.
status register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
1/3 fields covered.
Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow and if UDIS=â0â in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=â0â and UDIS=â0â in the TIMx_CR1 register..
Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending
Bit 1: Capture/compare 1 interrupt flag.
Bit 9: Capture/Compare 1 overcapture flag.
event generation register
Offset: 0x14, size: 32, reset: 0x00000000, access: write-only
1/2 fields covered.
capture/compare mode register 1 (input mode)
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
capture/compare mode register 1 (output mode)
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
1/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OC[1]M_3
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OC[1]M
rw |
OC[1]PE
rw |
OC[1]FE
rw |
CC[1]S
rw |
Bits 0-1: Capture/Compare 1 selection.
Bit 2: Output compare 1 fast enable.
Bit 3: Output compare 1 preload enable.
Bits 4-6: Output compare 1 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1
Bit 16: Output compare 1 mode, bit 3.
capture/compare enable register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
counter
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
prescaler
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PSC
rw |
auto-reload register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ARR
rw |
capture/compare register
Offset: 0x34, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CCR
rw |
TIM timer input selection register
Offset: 0x68, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TI1SEL
rw |
0x40014000: General purpose timers
13/93 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CR1 | ||||||||||||||||||||||||||||||||
0x4 | CR2 | ||||||||||||||||||||||||||||||||
0x8 | SMCR | ||||||||||||||||||||||||||||||||
0xc | DIER | ||||||||||||||||||||||||||||||||
0x10 | SR | ||||||||||||||||||||||||||||||||
0x14 | EGR | ||||||||||||||||||||||||||||||||
0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
0x20 | CCER | ||||||||||||||||||||||||||||||||
0x24 | CNT | ||||||||||||||||||||||||||||||||
0x28 | PSC | ||||||||||||||||||||||||||||||||
0x2c | ARR | ||||||||||||||||||||||||||||||||
0x30 | RCR | ||||||||||||||||||||||||||||||||
0x34 | CCR[1] | ||||||||||||||||||||||||||||||||
0x38 | CCR[2] | ||||||||||||||||||||||||||||||||
0x44 | BDTR | ||||||||||||||||||||||||||||||||
0x48 | DCR | ||||||||||||||||||||||||||||||||
0x4c | DMAR | ||||||||||||||||||||||||||||||||
0x60 | AF1 | ||||||||||||||||||||||||||||||||
0x68 | TISEL |
control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
6/7 fields covered.
Bit 0: Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware..
Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled
Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..
Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled
Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.
Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request
Bit 3: One-pulse mode.
Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)
Bit 7: Auto-reload preload enable.
Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered
Bits 8-9: Clock division This bitfield indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS) used by the dead-time generators and the digital filters (TIx).
Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT
Bit 11: UIF status bit remapping.
control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
0/8 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OIS2
rw |
OIS1N
rw |
OIS1
rw |
TI1S
rw |
MMS
rw |
CCDS
rw |
CCUS
rw |
CCPC
rw |
Bit 0: Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output..
Bit 2: Capture/compare control update selection Note: This bit acts only on channels that have a complementary output..
Bit 3: Capture/compare DMA selection.
Bits 4-6: Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows:.
Bit 7: TI1 selection.
Bit 8: Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register)..
Bit 9: Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register)..
Bit 10: Output idle state 2 (OC2 output) Note: This bit cannot be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in the TIM15_BDTR register)..
slave mode control register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
0/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TS2
rw |
SMS2
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSM
rw |
TS1
rw |
SMS1
rw |
Bits 0-2: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Other codes: reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=â00100â). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..
Bits 4-6: Trigger selection This bit field selects the trigger input to be used to synchronize the counter. Other: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..
Bit 7: Master/slave mode.
Bit 16: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Other codes: reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=â00100â). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..
Bits 20-21: Trigger selection This bit field selects the trigger input to be used to synchronize the counter. Other: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..
DMA/Interrupt enable register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
1/11 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TDE
rw |
COMDE
rw |
CC[2]DE
rw |
CC[1]DE
rw |
UDE
rw |
BIE
rw |
TIE
rw |
COMIE
rw |
CC[2]IE
rw |
CC[1]IE
rw |
UIE
rw |
Bit 0: Update interrupt enable.
Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled
Bit 1: Capture/Compare 1 interrupt enable.
Bit 2: Capture/Compare 2 interrupt enable.
Bit 5: COM interrupt enable.
Bit 6: Trigger interrupt enable.
Bit 7: Break interrupt enable.
Bit 8: Update DMA request enable.
Bit 9: Capture/Compare 1 DMA request enable.
Bit 10: Capture/Compare 2 DMA request enable.
Bit 13: COM DMA request enable.
Bit 14: Trigger DMA request enable.
status register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
1/8 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CC[2]OF
rw |
CC[1]OF
rw |
BIF
rw |
TIF
rw |
COMIF
rw |
CC[2]IF
rw |
CC[1]IF
rw |
UIF
rw |
Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM15_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register..
Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending
Bit 1: Capture/compare 1 interrupt flag.
Bit 2: Capture/compare 2 interrupt flag.
Bit 5: COM interrupt flag This flag is set by hardware on a COM event (once the capture/compare control bits âCCxE, CCxNE, OCxMâ have been updated). It is cleared by software..
Bit 6: Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode, both edges in case gated mode is selected). It is set when the counter starts or stops when gated mode is selected. It is cleared by software..
Bit 7: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active..
Bit 9: Capture/Compare 1 overcapture flag.
Bit 10: Capture/Compare 2 overcapture flag.
event generation register
Offset: 0x14, size: 32, reset: 0x00000000, access: write-only
1/6 fields covered.
Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..
Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.
Bit 1: Capture/compare 1 generation.
Bit 2: Capture/compare 2 generation.
Bit 5: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output..
Bit 6: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..
Bit 7: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..
capture/compare mode register 1 (input mode)
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
0/6 fields covered.
capture/compare mode register (output mode)
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
2/10 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OC[2]M_3
rw |
OC1M2
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OC[2]M
rw |
OC[2]PE
rw |
OC[2]FE
rw |
CC[2]S
rw |
OC1M1
rw |
OC[1]PE
rw |
OC[1]FE
rw |
CC[1]S
rw |
Bits 0-1: Capture/Compare 1 selection.
Bit 2: Output compare 1 fast enable.
Bit 3: Output compare 1 preload enable.
Bits 4-6: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from âfrozenâ mode to âPWMâ mode. On channels that have a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. The OC1M[3] bit is not contiguous, located in bit 16..
Bits 8-9: Capture/Compare 2 selection.
Bit 10: Output compare 2 fast enable.
Bit 11: Output compare 2 preload enable.
Bits 12-14: Output compare 2 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / Reserved
7: PwmMode2: Inversely to PwmMode1 / Reserved
Bit 16: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from âfrozenâ mode to âPWMâ mode. On channels that have a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. The OC1M[3] bit is not contiguous, located in bit 16..
Bit 24: Output compare 2 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
capture/compare enable register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
0/7 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CC[2]NP
rw |
CC[2]P
rw |
CC[2]E
rw |
CC[1]NP
rw |
CC[1]NE
rw |
CC[1]P
rw |
CC[1]E
rw |
Bit 0: Capture/Compare 1 output enable.
Bit 1: Capture/Compare 1 output Polarity.
Bit 2: Capture/Compare 1 complementary output enable.
Bit 3: Capture/Compare 1 output Polarity.
Bit 4: Capture/Compare 2 output enable.
Bit 5: Capture/Compare 2 output Polarity.
Bit 7: Capture/Compare 2 output Polarity.
counter
Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified
1/2 fields covered.
prescaler
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PSC
rw |
auto-reload register
Offset: 0x2c, size: 32, reset: 0x0000FFFF, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ARR
rw |
repetition counter register
Offset: 0x30, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
REP
rw |
capture/compare register
Offset: 0x34, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CCR
rw |
capture/compare register
Offset: 0x38, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CCR
rw |
break and dead-time register
Offset: 0x44, size: 32, reset: 0x00000000, access: read-write
0/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BKBID
rw |
BKDSRM
rw |
BKF
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MOE
rw |
AOE
rw |
BKP
rw |
BKE
rw |
OSSR
rw |
OSSI
rw |
LOCK
rw |
DTG
rw |
Bits 0-7: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 µs to 31750 ns by 250 ns steps, 32 µs to 63 µs by 1 µs steps, 64 µs to 126 µs by 2 µs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..
Bits 8-9: Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset..
Bit 10: Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 11: Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 12: Break enable 1; Break inputs (BRK and CCS clock failure event) enabled This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Bit 13: Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Bit 14: Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 15: Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818)..
Bits 16-19: Break filter This bit-field defines the frequency used to sample the BRK input signal and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 26: Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Bit 28: Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
DMA control register
Offset: 0x48, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
Bits 0-4: DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ....
Bits 8-12: DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ....
DMA address for full transfer
Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DMAB
rw |
TIM15 alternate register 1
Offset: 0x60, size: 32, reset: 0x00000001, access: read-write
0/2 fields covered.
Bit 0: BRK BKIN input enable This bit enables the BKIN alternate function input for the timerâs BRK input. BKIN input is 'ORedâ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 9: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
0x40014400: General purpose timers
12/62 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CR1 | ||||||||||||||||||||||||||||||||
0x4 | CR2 | ||||||||||||||||||||||||||||||||
0xc | DIER | ||||||||||||||||||||||||||||||||
0x10 | SR | ||||||||||||||||||||||||||||||||
0x14 | EGR | ||||||||||||||||||||||||||||||||
0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
0x20 | CCER | ||||||||||||||||||||||||||||||||
0x24 | CNT | ||||||||||||||||||||||||||||||||
0x28 | PSC | ||||||||||||||||||||||||||||||||
0x2c | ARR | ||||||||||||||||||||||||||||||||
0x30 | RCR | ||||||||||||||||||||||||||||||||
0x34 | CCR[1] | ||||||||||||||||||||||||||||||||
0x44 | BDTR | ||||||||||||||||||||||||||||||||
0x48 | DCR | ||||||||||||||||||||||||||||||||
0x4c | DMAR | ||||||||||||||||||||||||||||||||
0x60 | AF1 | ||||||||||||||||||||||||||||||||
0x68 | TISEL |
control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
6/7 fields covered.
Bit 0: Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware..
Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled
Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..
Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled
Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.
Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request
Bit 3: One pulse mode.
Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)
Bit 7: Auto-reload preload enable.
Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered
Bits 8-9: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (TIx),.
Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT
Bit 11: UIF status bit remapping.
control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
0/5 fields covered.
Bit 0: Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output..
Bit 2: Capture/compare control update selection Note: This bit acts only on channels that have a complementary output..
Bit 3: Capture/compare DMA selection.
Bit 8: Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 9: Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..
DMA/Interrupt enable register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
1/6 fields covered.
Bit 0: Update interrupt enable.
Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled
Bit 1: Capture/Compare 1 interrupt enable.
Bit 5: COM interrupt enable.
Bit 7: Break interrupt enable.
Bit 8: Update DMA request enable.
Bit 9: Capture/Compare 1 DMA request enable.
status register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
1/5 fields covered.
Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register..
Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending
Bit 1: Capture/compare 1 interrupt flag.
Bit 5: COM interrupt flag This flag is set by hardware on a COM event (once the capture/compare control bits âCCxE, CCxNE, OCxMâ have been updated). It is cleared by software..
Bit 7: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active..
Bit 9: Capture/Compare 1 overcapture flag.
event generation register
Offset: 0x14, size: 32, reset: 0x00000000, access: write-only
1/4 fields covered.
Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..
Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.
Bit 1: Capture/compare 1 generation.
Bit 5: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output..
Bit 7: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..
capture/compare mode register 1 (input mode)
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
capture/compare mode register (output mode)
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
1/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OC[1]M_3
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OC[1]M
rw |
OC[1]PE
rw |
OC[1]FE
rw |
CC[1]S
rw |
Bits 0-1: Capture/Compare 1 selection.
Bit 2: Output compare 1 fast enable.
Bit 3: Output compare 1 preload enable.
Bits 4-6: Output compare 1 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1
Bit 16: Output compare 1 mode, bit 3.
capture/compare enable register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
counter
Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified
1/2 fields covered.
prescaler
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PSC
rw |
auto-reload register
Offset: 0x2c, size: 32, reset: 0x0000FFFF, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ARR
rw |
repetition counter register
Offset: 0x30, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
REP
rw |
capture/compare register
Offset: 0x34, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CCR
rw |
break and dead-time register
Offset: 0x44, size: 32, reset: 0x00000000, access: read-write
0/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BKBID
rw |
BKDSRM
rw |
BKF
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MOE
rw |
AOE
rw |
BKP
rw |
BKE
rw |
OSSR
rw |
OSSI
rw |
LOCK
rw |
DTG
rw |
Bits 0-7: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 µs to 31750 ns by 250 ns steps, 32 µs to 63 µs by 1 µs steps, 64 µs to 126 µs by 2 µs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..
Bits 8-9: Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset..
Bit 10: Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 11: Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 12: Break enable 1; Break inputs (BRK and CCS clock failure event) enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Bit 13: Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Bit 14: Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 15: Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846)..
Bits 16-19: Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 26: Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Bit 28: Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
DMA control register
Offset: 0x48, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
Bits 0-4: DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address..
Bits 8-12: DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ....
DMA address for full transfer
Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DMAB
rw |
TIM17 option register 1
Offset: 0x60, size: 32, reset: 0x00000001, access: read-write
0/2 fields covered.
Bit 0: BRK BKIN input enable This bit enables the BKIN alternate function input for the timerâs BRK input. BKIN input is 'ORedâ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 9: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
input selection register
Offset: 0x68, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TI1SEL
rw |
0x40014800: General purpose timers
12/62 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CR1 | ||||||||||||||||||||||||||||||||
0x4 | CR2 | ||||||||||||||||||||||||||||||||
0xc | DIER | ||||||||||||||||||||||||||||||||
0x10 | SR | ||||||||||||||||||||||||||||||||
0x14 | EGR | ||||||||||||||||||||||||||||||||
0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
0x20 | CCER | ||||||||||||||||||||||||||||||||
0x24 | CNT | ||||||||||||||||||||||||||||||||
0x28 | PSC | ||||||||||||||||||||||||||||||||
0x2c | ARR | ||||||||||||||||||||||||||||||||
0x30 | RCR | ||||||||||||||||||||||||||||||||
0x34 | CCR[1] | ||||||||||||||||||||||||||||||||
0x44 | BDTR | ||||||||||||||||||||||||||||||||
0x48 | DCR | ||||||||||||||||||||||||||||||||
0x4c | DMAR | ||||||||||||||||||||||||||||||||
0x60 | AF1 | ||||||||||||||||||||||||||||||||
0x68 | TISEL |
control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
6/7 fields covered.
Bit 0: Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware..
Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled
Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..
Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled
Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.
Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request
Bit 3: One pulse mode.
Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)
Bit 7: Auto-reload preload enable.
Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered
Bits 8-9: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (TIx),.
Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT
Bit 11: UIF status bit remapping.
control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
0/5 fields covered.
Bit 0: Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output..
Bit 2: Capture/compare control update selection Note: This bit acts only on channels that have a complementary output..
Bit 3: Capture/compare DMA selection.
Bit 8: Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 9: Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..
DMA/Interrupt enable register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
1/6 fields covered.
Bit 0: Update interrupt enable.
Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled
Bit 1: Capture/Compare 1 interrupt enable.
Bit 5: COM interrupt enable.
Bit 7: Break interrupt enable.
Bit 8: Update DMA request enable.
Bit 9: Capture/Compare 1 DMA request enable.
status register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
1/5 fields covered.
Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register..
Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending
Bit 1: Capture/compare 1 interrupt flag.
Bit 5: COM interrupt flag This flag is set by hardware on a COM event (once the capture/compare control bits âCCxE, CCxNE, OCxMâ have been updated). It is cleared by software..
Bit 7: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active..
Bit 9: Capture/Compare 1 overcapture flag.
event generation register
Offset: 0x14, size: 32, reset: 0x00000000, access: write-only
1/4 fields covered.
Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..
Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.
Bit 1: Capture/compare 1 generation.
Bit 5: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output..
Bit 7: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..
capture/compare mode register 1 (input mode)
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
capture/compare mode register (output mode)
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
1/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OC[1]M_3
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OC[1]M
rw |
OC[1]PE
rw |
OC[1]FE
rw |
CC[1]S
rw |
Bits 0-1: Capture/Compare 1 selection.
Bit 2: Output compare 1 fast enable.
Bit 3: Output compare 1 preload enable.
Bits 4-6: Output compare 1 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1
Bit 16: Output compare 1 mode, bit 3.
capture/compare enable register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
counter
Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified
1/2 fields covered.
prescaler
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PSC
rw |
auto-reload register
Offset: 0x2c, size: 32, reset: 0x0000FFFF, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ARR
rw |
repetition counter register
Offset: 0x30, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
REP
rw |
capture/compare register
Offset: 0x34, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CCR
rw |
break and dead-time register
Offset: 0x44, size: 32, reset: 0x00000000, access: read-write
0/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BKBID
rw |
BKDSRM
rw |
BKF
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MOE
rw |
AOE
rw |
BKP
rw |
BKE
rw |
OSSR
rw |
OSSI
rw |
LOCK
rw |
DTG
rw |
Bits 0-7: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 µs to 31750 ns by 250 ns steps, 32 µs to 63 µs by 1 µs steps, 64 µs to 126 µs by 2 µs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..
Bits 8-9: Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset..
Bit 10: Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 11: Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 12: Break enable 1; Break inputs (BRK and CCS clock failure event) enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Bit 13: Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Bit 14: Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 15: Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846)..
Bits 16-19: Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 26: Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Bit 28: Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
DMA control register
Offset: 0x48, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
Bits 0-4: DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address..
Bits 8-12: DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ....
DMA address for full transfer
Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DMAB
rw |
TIM17 option register 1
Offset: 0x60, size: 32, reset: 0x00000001, access: read-write
0/2 fields covered.
Bit 0: BRK BKIN input enable This bit enables the BKIN alternate function input for the timerâs BRK input. BKIN input is 'ORedâ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 9: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
input selection register
Offset: 0x68, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TI1SEL
rw |
0x40000400: General-purpose-timers
20/113 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CR1 | ||||||||||||||||||||||||||||||||
0x4 | CR2 | ||||||||||||||||||||||||||||||||
0x8 | SMCR | ||||||||||||||||||||||||||||||||
0xc | DIER | ||||||||||||||||||||||||||||||||
0x10 | SR | ||||||||||||||||||||||||||||||||
0x14 | EGR | ||||||||||||||||||||||||||||||||
0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
0x1c | CCMR2_Input | ||||||||||||||||||||||||||||||||
0x1c | CCMR2_Output | ||||||||||||||||||||||||||||||||
0x20 | CCER | ||||||||||||||||||||||||||||||||
0x24 | CNT | ||||||||||||||||||||||||||||||||
0x28 | PSC | ||||||||||||||||||||||||||||||||
0x2c | ARR | ||||||||||||||||||||||||||||||||
0x34 | CCR[1] | ||||||||||||||||||||||||||||||||
0x38 | CCR[2] | ||||||||||||||||||||||||||||||||
0x3c | CCR[3] | ||||||||||||||||||||||||||||||||
0x40 | CCR[4] | ||||||||||||||||||||||||||||||||
0x48 | DCR | ||||||||||||||||||||||||||||||||
0x4c | DMAR | ||||||||||||||||||||||||||||||||
0x60 | AF1 | ||||||||||||||||||||||||||||||||
0x68 | TISEL |
control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
8/9 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
UIFREMAP
rw |
CKD
rw |
ARPE
rw |
CMS
rw |
DIR
rw |
OPM
rw |
URS
rw |
UDIS
rw |
CEN
rw |
Bit 0: Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs..
Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled
Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..
Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled
Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.
Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request
Bit 3: One-pulse mode.
Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)
Bit 4: Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode..
Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter
Bits 5-6: Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1).
Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
Bit 7: Auto-reload preload enable.
Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered
Bits 8-9: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx),.
Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT
Bit 11: UIF status bit remapping.
control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Bit 3: Capture/compare DMA selection.
Bits 4-6: Master mode selection These bits permit to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer..
Bit 7: TI1 selection.
slave mode control register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
0/10 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TS2
rw |
SMS2
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ETP
rw |
ECE
rw |
ETPS
rw |
ETF
rw |
MSM
rw |
TS1
rw |
OCCS
rw |
SMS1
rw |
Bits 0-2: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..
Bit 3: OCREF clear selection This bit is used to select the OCREF clear source.
Bits 4-6: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..
Bit 7: Master/Slave mode.
Bits 8-11: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.
Bits 12-13: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks..
Bit 14: External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF..
Bit 15: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations.
Bit 16: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..
Bits 20-21: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..
DMA/Interrupt enable register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
1/12 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TDE
rw |
CC[4]DE
rw |
CC[3]DE
rw |
CC[2]DE
rw |
CC[1]DE
rw |
UDE
rw |
TIE
rw |
CC[4]IE
rw |
CC[3]IE
rw |
CC[2]IE
rw |
CC[1]IE
rw |
UIE
rw |
Bit 0: Update interrupt enable.
Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled
Bit 1: Capture/Compare 1 interrupt enable.
Bit 2: Capture/Compare 2 interrupt enable.
Bit 3: Capture/Compare 3 interrupt enable.
Bit 4: Capture/Compare 4 interrupt enable.
Bit 6: Trigger interrupt enable.
Bit 8: Update DMA request enable.
Bit 9: Capture/Compare 1 DMA request enable.
Bit 10: Capture/Compare 2 DMA request enable.
Bit 11: Capture/Compare 3 DMA request enable.
Bit 12: Capture/Compare 4 DMA request enable.
Bit 14: Trigger DMA request enable.
status register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
1/10 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CC[4]OF
rw |
CC[3]OF
rw |
CC[2]OF
rw |
CC[1]OF
rw |
TIF
rw |
CC[4]IF
rw |
CC[3]IF
rw |
CC[2]IF
rw |
CC[1]IF
rw |
UIF
rw |
Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow and if UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register..
Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending
Bit 1: Capture/compare 1 interrupt flag.
Bit 2: Capture/compare 2 interrupt flag.
Bit 3: Capture/compare 3 interrupt flag.
Bit 4: Capture/compare 4 interrupt flag.
Bit 6: Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software..
Bit 9: Capture/Compare 1 overcapture flag.
Bit 10: Capture/Compare 2 overcapture flag.
Bit 11: Capture/Compare 3 overcapture flag.
Bit 12: Capture/Compare 4 overcapture flag.
event generation register
Offset: 0x14, size: 32, reset: 0x00000000, access: write-only
1/6 fields covered.
Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..
Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.
Bit 1: Capture/compare 1 generation.
Bit 2: Capture/compare 2 generation.
Bit 3: Capture/compare 3 generation.
Bit 4: Capture/compare 4 generation.
Bit 6: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..
capture/compare mode register 1 (input mode)
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
0/6 fields covered.
capture/compare mode register 1 (output mode)
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
4/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OC[2]M_3
rw |
OC[1]M_3
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OC[2]CE
rw |
OC[2]M
rw |
OC[2]PE
rw |
OC[2]FE
rw |
CC[2]S
rw |
OC[1]CE
rw |
OC[1]M
rw |
OC[1]PE
rw |
OC[1]FE
rw |
CC[1]S
rw |
Bits 0-1: Capture/Compare 1 selection.
Bit 2: Output compare 1 fast enable.
Bit 3: Output compare 1 preload enable.
Bits 4-6: Output compare 1 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bit 7: Output compare 1 clear enable.
Bits 8-9: Capture/Compare 2 selection.
Bit 10: Output compare 2 fast enable.
Bit 11: Output compare 2 preload enable.
Bits 12-14: Output compare 2 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bit 15: Output compare 2 clear enable.
Bit 16: Output compare 1 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
Bit 24: Output compare 2 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
capture/compare mode register 2 (input mode)
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
0/6 fields covered.
capture/compare mode register 2 (output mode)
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
4/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OC[4]M_3
rw |
OC[3]M_3
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OC[4]CE
rw |
OC[4]M
rw |
OC[4]PE
rw |
OC[4]FE
rw |
CC[4]S
rw |
OC[3]CE
rw |
OC[3]M
rw |
OC[3]PE
rw |
OC[3]FE
rw |
CC[3]S
rw |
Bits 0-1: Capture/Compare 3 selection.
Bit 2: Output compare 3 fast enable.
Bit 3: Output compare 3 preload enable.
Bits 4-6: Output compare 3 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bit 7: Output compare 3 clear enable.
Bits 8-9: Capture/Compare 4 selection.
Bit 10: Output compare 4 fast enable.
Bit 11: Output compare 4 preload enable.
Bits 12-14: Output compare 4 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bit 15: Output compare 4 clear enable.
Bit 16: Output compare 3 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
Bit 24: Output compare 4 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
capture/compare enable register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
0/12 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CC[4]NP
rw |
CC[4]P
rw |
CC[4]E
rw |
CC[3]NP
rw |
CC[3]P
rw |
CC[3]E
rw |
CC[2]NP
rw |
CC[2]P
rw |
CC[2]E
rw |
CC[1]NP
rw |
CC[1]P
rw |
CC[1]E
rw |
Bit 0: Capture/Compare 1 output enable.
Bit 1: Capture/Compare 1 output Polarity.
Bit 3: Capture/Compare 1 output Polarity.
Bit 4: Capture/Compare 2 output enable.
Bit 5: Capture/Compare 2 output Polarity.
Bit 7: Capture/Compare 2 output Polarity.
Bit 8: Capture/Compare 3 output enable.
Bit 9: Capture/Compare 3 output Polarity.
Bit 11: Capture/Compare 3 output Polarity.
Bit 12: Capture/Compare 4 output enable.
Bit 13: Capture/Compare 4 output Polarity.
Bit 15: Capture/Compare 4 output Polarity.
counter
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
prescaler
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PSC
rw |
auto-reload register
Offset: 0x2c, size: 32, reset: 0xFFFFFFFF, access: read-write
0/1 fields covered.
capture/compare register
Offset: 0x34, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
capture/compare register
Offset: 0x38, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
capture/compare register
Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
capture/compare register
Offset: 0x40, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
DMA control register
Offset: 0x48, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
Bits 0-4: DMA base address This 5-bit vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address..
Bits 8-12: DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ....
DMA address for full transfer
Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DMAB
rw |
TIM alternate function option register 1
Offset: 0x60, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
TIM alternate function option register 1
Offset: 0x68, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TI3SEL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TI2SEL
rw |
TI1SEL
rw |
Bits 0-3: TI1[0] to TI1[15] input selection These bits select the TI1[0] to TI1[15] input source. Others: Reserved.
Bits 8-11: TI2[0] to TI2[15] input selection These bits select the TI2[0] to TI2[15] input source. Others: Reserved.
Bits 16-19: TI3[0] to TI3[15] input selection These bits select the TI3[0] to TI3[15] input source. Others: Reserved.
0x40001000: Basic timers
14/15 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CR1 | ||||||||||||||||||||||||||||||||
0x4 | CR2 | ||||||||||||||||||||||||||||||||
0xc | DIER | ||||||||||||||||||||||||||||||||
0x10 | SR | ||||||||||||||||||||||||||||||||
0x14 | EGR | ||||||||||||||||||||||||||||||||
0x24 | CNT | ||||||||||||||||||||||||||||||||
0x28 | PSC | ||||||||||||||||||||||||||||||||
0x2c | ARR |
control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
5/6 fields covered.
Bit 0: Counter enable Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs..
Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled
Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..
Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled
Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.
Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request
Bit 3: One-pulse mode.
Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)
Bit 7: Auto-reload preload enable.
Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered
Bit 11: UIF status bit remapping.
control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MMS
rw |
Bits 4-6: Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer..
Allowed values:
0: Reset: Use UG bit from TIMx_EGR register
1: Enable: Use CNT bit from TIMx_CEN register
2: Update: Use the update event
DMA/Interrupt enable register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
2/2 fields covered.
status register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
UIF
rw |
Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0 and UDIS = 0 in the TIMx_CR1 register..
Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending
event generation register
Offset: 0x14, size: 32, reset: 0x00000000, access: write-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
UG
w |
counter
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
2/2 fields covered.
prescaler
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PSC
rw |
auto-reload register
Offset: 0x2c, size: 32, reset: 0x0000FFFF, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ARR
rw |
0x40001400: Basic timers
14/15 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CR1 | ||||||||||||||||||||||||||||||||
0x4 | CR2 | ||||||||||||||||||||||||||||||||
0xc | DIER | ||||||||||||||||||||||||||||||||
0x10 | SR | ||||||||||||||||||||||||||||||||
0x14 | EGR | ||||||||||||||||||||||||||||||||
0x24 | CNT | ||||||||||||||||||||||||||||||||
0x28 | PSC | ||||||||||||||||||||||||||||||||
0x2c | ARR |
control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
5/6 fields covered.
Bit 0: Counter enable Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs..
Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled
Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..
Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled
Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.
Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request
Bit 3: One-pulse mode.
Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)
Bit 7: Auto-reload preload enable.
Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered
Bit 11: UIF status bit remapping.
control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MMS
rw |
Bits 4-6: Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer..
Allowed values:
0: Reset: Use UG bit from TIMx_EGR register
1: Enable: Use CNT bit from TIMx_CEN register
2: Update: Use the update event
DMA/Interrupt enable register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
2/2 fields covered.
status register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
UIF
rw |
Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0 and UDIS = 0 in the TIMx_CR1 register..
Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending
event generation register
Offset: 0x14, size: 32, reset: 0x00000000, access: write-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
UG
w |
counter
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
2/2 fields covered.
prescaler
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PSC
rw |
auto-reload register
Offset: 0x2c, size: 32, reset: 0x0000FFFF, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ARR
rw |
0x40013800: Universal synchronous asynchronous receiver transmitter
29/124 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CR1 | ||||||||||||||||||||||||||||||||
0x4 | CR2 | ||||||||||||||||||||||||||||||||
0x8 | CR3 | ||||||||||||||||||||||||||||||||
0xc | BRR | ||||||||||||||||||||||||||||||||
0x10 | GTPR | ||||||||||||||||||||||||||||||||
0x14 | RTOR | ||||||||||||||||||||||||||||||||
0x18 | RQR | ||||||||||||||||||||||||||||||||
0x1c | ISR | ||||||||||||||||||||||||||||||||
0x20 | ICR | ||||||||||||||||||||||||||||||||
0x24 | RDR | ||||||||||||||||||||||||||||||||
0x28 | TDR | ||||||||||||||||||||||||||||||||
0x2c | PRESC |
Control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
0/24 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXFFIE
rw |
TXFEIE
rw |
FIFOEN
rw |
M1
rw |
EOBIE
rw |
RTOIE
rw |
DEAT
rw |
DEDT
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OVER8
rw |
CMIE
rw |
MME
rw |
M0
rw |
WAKE
rw |
PCE
rw |
PS
rw |
PEIE
rw |
TXFNFIE
rw |
TCIE
rw |
RXFNEIE
rw |
IDLEIE
rw |
TE
rw |
RE
rw |
UESM
rw |
UE
rw |
Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value..
Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to ..
Bit 2: Receiver enable This bit enables the receiver. It is set and cleared by software..
Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0â followed by '1â) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1â. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..
Bit 4: IDLE interrupt enable This bit is set and cleared by software..
Bit 5: RXFIFO not empty interrupt enable This bit is set and cleared by software..
Bit 6: Transmission complete interrupt enable This bit is set and cleared by software..
Bit 7: TXFIFO not full interrupt enable This bit is set and cleared by software..
Bit 8: PE interrupt enable This bit is set and cleared by software..
Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1; 8th bit if MÂ =Â 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Bit 11: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Bit 12: Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UEÂ =Â 0)..
Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..
Bit 14: Character match interrupt enable This bit is set and cleared by software..
Bit 15: Oversampling mode This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared..
Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ..
Bit 27: End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00â: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01â: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10â: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..
Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..
Bit 30: TXFIFO empty interrupt enable This bit is set and cleared by software..
Bit 31: RXFIFO Full interrupt enable This bit is set and cleared by software..
Control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
0/20 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADD
rw |
RTOEN
rw |
ABRMOD
rw |
ABREN
rw |
MSBFIRST
rw |
DATAINV
rw |
TXINV
rw |
RXINV
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SWAP
rw |
LINEN
rw |
STOP
rw |
CLKEN
rw |
CPOL
rw |
CPHA
rw |
LBCL
rw |
LBDIE
rw |
LBDL
rw |
ADDM7
rw |
DIS_NSS
rw |
SLVEN
rw |
Bit 0: Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 3: When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 4: 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively..
Bit 5: LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 6: LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 8: Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 9: Clock phase This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see and ) This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 10: Clock polarity This bit enables the user to select the polarity of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 11: Clock enable This bit enables the user to enable the SCLK pin. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to . In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1.
Bits 12-13: stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Bit 14: LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to ..
Bit 15: Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Bit 16: RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Bit 17: TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Bit 18: Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Bit 19: Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Bit 20: Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..
Bits 21-22: Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UEÂ =Â 0). Note: If DATAINVÂ =Â 1 and/or MSBFIRSTÂ =Â 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..
Bit 23: Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to ..
Bits 24-31: Address of the USART node ADD[7:4]: These bits give the address of the USART node or a character code to be recognized. They are used to wake up the MCU with 7-bit address mark detection in multiprocessor communication during Mute mode or low-power mode. The MSB of the character sent by the transmitter should be equal to 1. They can also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UEÂ =Â 0). ADD[3:0]: These bits give the address of the USART node or a character code to be recognized. They are used for wakeup with address mark detection, in multiprocessor communication during Mute mode or low-power mode. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UEÂ =Â 0)..
Control register 3
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
0/24 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TXFTCFG
rw |
RXFTIE
rw |
RXFTCFG
rw |
TCBGTIE
rw |
TXFTIE
rw |
WUFIE
rw |
WUS
rw |
SCARCNT
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DEP
rw |
DEM
rw |
DDRE
rw |
OVRDIS
rw |
ONEBIT
rw |
CTSIE
rw |
CTSE
rw |
RTSE
rw |
DMAT
rw |
DMAR
rw |
SCEN
rw |
NACK
rw |
HDSEL
rw |
IRLP
rw |
IREN
rw |
EIE
rw |
Bit 0: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FEÂ =Â 1 or OREÂ =Â 1 or NEÂ =Â 1 or UDR = 1 in the USART_ISR register)..
Bit 1: IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 2: IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 3: Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UEÂ =Â 0)..
Bit 4: Smartcard NACK enable This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Bit 5: Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Bit 6: DMA enable receiver This bit is set/reset by software.
Bit 7: DMA enable transmitter This bit is set/reset by software.
Bit 8: RTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 9: CTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 10: CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 11: One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UEÂ =Â 0)..
Bit 12: Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: This control bit enables checking the communication flow w/o reading the data.
Bit 13: DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error..
Bit 14: Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. ..
Bit 15: Driver enable polarity selection This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bits 17-19: Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UEÂ =Â 0). When the USART is enabled (UEÂ =Â 1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bits 20-21: Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..
Bit 22: Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..
Bit 23: TXFIFO threshold interrupt enable This bit is set and cleared by software..
Bit 24: Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Bits 25-27: Receive FIFO threshold configuration Remaining combinations: Reserved.
Bit 28: RXFIFO threshold interrupt enable This bit is set and cleared by software..
Bits 29-31: TXFIFO threshold configuration Remaining combinations: Reserved.
Baud rate register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BRR
rw |
Guard time and prescaler register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
Bits 0-7: Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power baud rate PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0]Â =Â Prescaler value PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... 0010Â 0000: Divides the source clock by 32 (IrDA mode) ... 1111Â 1111: Divides the source clock by 255 (IrDA mode) This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to '0â when the Smartcard and IrDA modes are not supported. Refer to ..
Bits 8-15: Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Receiver timeout register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
Request register
Offset: 0x18, size: 32, reset: 0x00000000, access: write-only
0/5 fields covered.
Bit 0: Auto baud rate request Writing 1 to this bit resets the ABRF flag in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..
Bit 1: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit..
Bit 2: Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag..
Bit 3: Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition..
Bit 4: Transmit data flush request When FIFO mode is disabled, writing '1â to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register..
Interrupt & status register
Offset: 0x1c, size: 32, reset: 0x008000C0, access: read-only
28/28 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TXFT
r |
RXFT
r |
TCBGT
r |
RXFF
r |
TXFE
r |
REACK
r |
TEACK
r |
WUF
r |
RWU
r |
SBKF
r |
CMF
r |
BUSY
r |
||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ABRF
r |
ABRE
r |
UDR
r |
EOBF
r |
RTOF
r |
CTS
r |
CTSIF
r |
LBDF
r |
TXFNF
r |
TC
r |
RXFNE
r |
IDLE
r |
ORE
r |
NE
r |
FE
r |
PE
r |
Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR..
Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIEÂ =Â 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR..
Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861). This error is associated with the character in the USART_RDR..
Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIEÂ =Â 1 or EIE = 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..
Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIEÂ =Â 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MMEÂ =Â 1), IDLE is set if the USART is not mute (RWUÂ =Â 0), whatever the Mute mode selected by the WAKE bit. If RWUÂ =Â 1, IDLE is not set..
Bit 5: RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIEÂ =Â 1 in the USART_CR1 register..
Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIEÂ =Â 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set..
Bit 7: TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). This bit is used during single buffer transmission..
Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ..
Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIEÂ =Â 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..
Bit 10: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..
Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIEÂ =Â 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..
Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example TÂ =Â 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIEÂ =Â 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ..
Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..
Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..
Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABREÂ =Â 1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..
Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..
Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIEÂ =Â 1in the USART_CR1 register..
Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..
Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIEÂ =Â 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TEÂ =Â 0, followed by TEÂ =Â 1 in the USART_CR1 register, in order to respect the TEÂ =Â 0 minimum period..
Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Bit 23: TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit  = 1 (bit 30) in the USART_CR1 register..
Bit 24: RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit  = 1 in the USART_CR1 register..
Bit 25: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1â. Refer to on page 835..
Bit 26: RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit  = 1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to '101â, RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data..
Bit 27: TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit  = 1 (bit 31) in the USART_CR3 register..
Interrupt flag clear register
Offset: 0x20, size: 32, reset: 0x00000000, access: write-only
0/15 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WUCF
w |
CMCF
w |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UDRCF
w |
EOBCF
w |
RTOCF
w |
CTSCF
w |
LBDCF
w |
TCBGTCF
w |
TCCF
w |
TXFECF
w |
IDLECF
w |
ORECF
w |
NECF
w |
FECF
w |
PECF
w |
Bit 0: Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register..
Bit 1: Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register..
Bit 2: Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register..
Bit 3: Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register..
Bit 4: Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register..
Bit 5: TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register..
Bit 6: Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register..
Bit 7: Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register..
Bit 8: LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 9: CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 11: Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to page 835..
Bit 12: End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Bit 13: SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to.
Bit 17: Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register..
Bit 20: Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..
Receive data register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RDR
r |
Transmit data register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TDR
rw |
Prescaler register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PRESCALER
rw |
0x40004400: Universal synchronous asynchronous receiver transmitter
29/124 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CR1 | ||||||||||||||||||||||||||||||||
0x4 | CR2 | ||||||||||||||||||||||||||||||||
0x8 | CR3 | ||||||||||||||||||||||||||||||||
0xc | BRR | ||||||||||||||||||||||||||||||||
0x10 | GTPR | ||||||||||||||||||||||||||||||||
0x14 | RTOR | ||||||||||||||||||||||||||||||||
0x18 | RQR | ||||||||||||||||||||||||||||||||
0x1c | ISR | ||||||||||||||||||||||||||||||||
0x20 | ICR | ||||||||||||||||||||||||||||||||
0x24 | RDR | ||||||||||||||||||||||||||||||||
0x28 | TDR | ||||||||||||||||||||||||||||||||
0x2c | PRESC |
Control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
0/24 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXFFIE
rw |
TXFEIE
rw |
FIFOEN
rw |
M1
rw |
EOBIE
rw |
RTOIE
rw |
DEAT
rw |
DEDT
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OVER8
rw |
CMIE
rw |
MME
rw |
M0
rw |
WAKE
rw |
PCE
rw |
PS
rw |
PEIE
rw |
TXFNFIE
rw |
TCIE
rw |
RXFNEIE
rw |
IDLEIE
rw |
TE
rw |
RE
rw |
UESM
rw |
UE
rw |
Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value..
Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to ..
Bit 2: Receiver enable This bit enables the receiver. It is set and cleared by software..
Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0â followed by '1â) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1â. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..
Bit 4: IDLE interrupt enable This bit is set and cleared by software..
Bit 5: RXFIFO not empty interrupt enable This bit is set and cleared by software..
Bit 6: Transmission complete interrupt enable This bit is set and cleared by software..
Bit 7: TXFIFO not full interrupt enable This bit is set and cleared by software..
Bit 8: PE interrupt enable This bit is set and cleared by software..
Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1; 8th bit if MÂ =Â 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Bit 11: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Bit 12: Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UEÂ =Â 0)..
Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..
Bit 14: Character match interrupt enable This bit is set and cleared by software..
Bit 15: Oversampling mode This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared..
Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ..
Bit 27: End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00â: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01â: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10â: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..
Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..
Bit 30: TXFIFO empty interrupt enable This bit is set and cleared by software..
Bit 31: RXFIFO Full interrupt enable This bit is set and cleared by software..
Control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
0/20 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADD
rw |
RTOEN
rw |
ABRMOD
rw |
ABREN
rw |
MSBFIRST
rw |
DATAINV
rw |
TXINV
rw |
RXINV
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SWAP
rw |
LINEN
rw |
STOP
rw |
CLKEN
rw |
CPOL
rw |
CPHA
rw |
LBCL
rw |
LBDIE
rw |
LBDL
rw |
ADDM7
rw |
DIS_NSS
rw |
SLVEN
rw |
Bit 0: Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 3: When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 4: 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively..
Bit 5: LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 6: LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 8: Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 9: Clock phase This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see and ) This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 10: Clock polarity This bit enables the user to select the polarity of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 11: Clock enable This bit enables the user to enable the SCLK pin. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to . In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1.
Bits 12-13: stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Bit 14: LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to ..
Bit 15: Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Bit 16: RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Bit 17: TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Bit 18: Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Bit 19: Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Bit 20: Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..
Bits 21-22: Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UEÂ =Â 0). Note: If DATAINVÂ =Â 1 and/or MSBFIRSTÂ =Â 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..
Bit 23: Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to ..
Bits 24-31: Address of the USART node ADD[7:4]: These bits give the address of the USART node or a character code to be recognized. They are used to wake up the MCU with 7-bit address mark detection in multiprocessor communication during Mute mode or low-power mode. The MSB of the character sent by the transmitter should be equal to 1. They can also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UEÂ =Â 0). ADD[3:0]: These bits give the address of the USART node or a character code to be recognized. They are used for wakeup with address mark detection, in multiprocessor communication during Mute mode or low-power mode. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UEÂ =Â 0)..
Control register 3
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
0/24 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TXFTCFG
rw |
RXFTIE
rw |
RXFTCFG
rw |
TCBGTIE
rw |
TXFTIE
rw |
WUFIE
rw |
WUS
rw |
SCARCNT
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DEP
rw |
DEM
rw |
DDRE
rw |
OVRDIS
rw |
ONEBIT
rw |
CTSIE
rw |
CTSE
rw |
RTSE
rw |
DMAT
rw |
DMAR
rw |
SCEN
rw |
NACK
rw |
HDSEL
rw |
IRLP
rw |
IREN
rw |
EIE
rw |
Bit 0: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FEÂ =Â 1 or OREÂ =Â 1 or NEÂ =Â 1 or UDR = 1 in the USART_ISR register)..
Bit 1: IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 2: IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 3: Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UEÂ =Â 0)..
Bit 4: Smartcard NACK enable This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Bit 5: Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Bit 6: DMA enable receiver This bit is set/reset by software.
Bit 7: DMA enable transmitter This bit is set/reset by software.
Bit 8: RTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 9: CTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 10: CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 11: One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UEÂ =Â 0)..
Bit 12: Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: This control bit enables checking the communication flow w/o reading the data.
Bit 13: DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error..
Bit 14: Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. ..
Bit 15: Driver enable polarity selection This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bits 17-19: Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UEÂ =Â 0). When the USART is enabled (UEÂ =Â 1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bits 20-21: Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..
Bit 22: Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..
Bit 23: TXFIFO threshold interrupt enable This bit is set and cleared by software..
Bit 24: Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Bits 25-27: Receive FIFO threshold configuration Remaining combinations: Reserved.
Bit 28: RXFIFO threshold interrupt enable This bit is set and cleared by software..
Bits 29-31: TXFIFO threshold configuration Remaining combinations: Reserved.
Baud rate register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BRR
rw |
Guard time and prescaler register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
Bits 0-7: Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power baud rate PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0]Â =Â Prescaler value PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... 0010Â 0000: Divides the source clock by 32 (IrDA mode) ... 1111Â 1111: Divides the source clock by 255 (IrDA mode) This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to '0â when the Smartcard and IrDA modes are not supported. Refer to ..
Bits 8-15: Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Receiver timeout register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
Request register
Offset: 0x18, size: 32, reset: 0x00000000, access: write-only
0/5 fields covered.
Bit 0: Auto baud rate request Writing 1 to this bit resets the ABRF flag in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..
Bit 1: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit..
Bit 2: Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag..
Bit 3: Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition..
Bit 4: Transmit data flush request When FIFO mode is disabled, writing '1â to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register..
Interrupt & status register
Offset: 0x1c, size: 32, reset: 0x008000C0, access: read-only
28/28 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TXFT
r |
RXFT
r |
TCBGT
r |
RXFF
r |
TXFE
r |
REACK
r |
TEACK
r |
WUF
r |
RWU
r |
SBKF
r |
CMF
r |
BUSY
r |
||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ABRF
r |
ABRE
r |
UDR
r |
EOBF
r |
RTOF
r |
CTS
r |
CTSIF
r |
LBDF
r |
TXFNF
r |
TC
r |
RXFNE
r |
IDLE
r |
ORE
r |
NE
r |
FE
r |
PE
r |
Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR..
Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIEÂ =Â 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR..
Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861). This error is associated with the character in the USART_RDR..
Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIEÂ =Â 1 or EIE = 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..
Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIEÂ =Â 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MMEÂ =Â 1), IDLE is set if the USART is not mute (RWUÂ =Â 0), whatever the Mute mode selected by the WAKE bit. If RWUÂ =Â 1, IDLE is not set..
Bit 5: RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIEÂ =Â 1 in the USART_CR1 register..
Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIEÂ =Â 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set..
Bit 7: TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). This bit is used during single buffer transmission..
Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ..
Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIEÂ =Â 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..
Bit 10: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..
Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIEÂ =Â 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..
Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example TÂ =Â 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIEÂ =Â 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ..
Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..
Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..
Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABREÂ =Â 1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..
Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..
Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIEÂ =Â 1in the USART_CR1 register..
Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..
Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIEÂ =Â 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TEÂ =Â 0, followed by TEÂ =Â 1 in the USART_CR1 register, in order to respect the TEÂ =Â 0 minimum period..
Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Bit 23: TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit  = 1 (bit 30) in the USART_CR1 register..
Bit 24: RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit  = 1 in the USART_CR1 register..
Bit 25: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1â. Refer to on page 835..
Bit 26: RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit  = 1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to '101â, RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data..
Bit 27: TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit  = 1 (bit 31) in the USART_CR3 register..
Interrupt flag clear register
Offset: 0x20, size: 32, reset: 0x00000000, access: write-only
0/15 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WUCF
w |
CMCF
w |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UDRCF
w |
EOBCF
w |
RTOCF
w |
CTSCF
w |
LBDCF
w |
TCBGTCF
w |
TCCF
w |
TXFECF
w |
IDLECF
w |
ORECF
w |
NECF
w |
FECF
w |
PECF
w |
Bit 0: Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register..
Bit 1: Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register..
Bit 2: Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register..
Bit 3: Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register..
Bit 4: Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register..
Bit 5: TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register..
Bit 6: Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register..
Bit 7: Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register..
Bit 8: LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 9: CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 11: Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to page 835..
Bit 12: End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Bit 13: SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to.
Bit 17: Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register..
Bit 20: Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..
Receive data register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RDR
r |
Transmit data register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TDR
rw |
Prescaler register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PRESCALER
rw |
0x40002c00: System window watchdog
6/6 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CR | ||||||||||||||||||||||||||||||||
0x4 | CFR | ||||||||||||||||||||||||||||||||
0x8 | SR |
Control register
Offset: 0x0, size: 32, reset: 0x0000007F, access: read-write
2/2 fields covered.
Bits 0-6: 7-bit counter (MSB to LSB) These bits contain the value of the watchdog counter, decremented every (4096 x 2WDGTB[1:0]) PCLK cycles. A reset is produced when it is decremented from 0x40 to 0x3F (T6 becomes cleared)..
Allowed values: 0x0-0x7f
Bit 7: Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGAÂ =Â 1, the watchdog can generate a reset..
Allowed values:
0: Disabled: Watchdog disabled
1: Enabled: Watchdog enabled
Configuration register
Offset: 0x4, size: 32, reset: 0x0000007F, access: read-write
3/3 fields covered.
Bits 0-6: 7-bit window value These bits contain the window value to be compared with the down-counter..
Allowed values: 0x0-0x7f
Bit 9: Early wakeup interrupt When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is only cleared by hardware after a reset..
Allowed values:
1: Enable: interrupt occurs whenever the counter reaches the value 0x40
Bits 11-13: Timer base The timebase of the prescaler can be modified as follows:.
Allowed values:
0: Div1: Counter clock (PCLK1 div 4096) div 1
1: Div2: Counter clock (PCLK1 div 4096) div 2
2: Div4: Counter clock (PCLK1 div 4096) div 4
3: Div8: Counter clock (PCLK1 div 4096) div 8
4: Div16: Counter clock (PCLK1 div 4096) div 16
5: Div32: Counter clock (PCLK1 div 4096) div 32
6: Div64: Counter clock (PCLK1 div 4096) div 64
7: Div128: Counter clock (PCLK1 div 4096) div 128
Status register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
EWIF
rw |