ADRDY

Bit 0: ADC ready flag.

Allowed values:
0: NotReady: ADC is not ready to start conversion
1: Ready: ADC is ready to start conversion

EOSMP

Bit 1: ADC group regular end of sampling flag.

Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached

EOC

Bit 2: ADC group regular end of unitary conversion flag.

Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete

EOS

Bit 3: ADC group regular end of sequence conversions flag.

Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete

OVR

Bit 4: ADC group regular overrun flag.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

JEOC

Bit 5: ADC group injected end of unitary conversion flag.

Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete

JEOS

Bit 6: ADC group injected end of sequence conversions flag.

Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete

AWD[1]

Bit 7: Analog watchdog 1 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD[2]

Bit 8: Analog watchdog 2 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD[3]

Bit 9: Analog watchdog 3 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

JQOVF

Bit 10: ADC group injected contexts queue overflow flag.

Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred

ADRDYIE

Bit 0: ADC ready interrupt.

Allowed values:
0: Disabled: ADC ready interrupt disabled
1: Enabled: ADC ready interrupt enabled

EOSMPIE

Bit 1: ADC group regular end of sampling interrupt.

Allowed values:
0: Disabled: End of regular conversion sampling phase interrupt disabled
1: Enabled: End of regular conversion sampling phase interrupt enabled

EOCIE

Bit 2: ADC group regular end of unitary conversion interrupt.

Allowed values:
0: Disabled: End of regular conversion interrupt disabled
1: Enabled: End of regular conversion interrupt enabled

EOSIE

Bit 3: ADC group regular end of sequence conversions interrupt.

Allowed values:
0: Disabled: End of regular sequence interrupt disabled
1: Enabled: End of regular sequence interrupt enabled

OVRIE

Bit 4: ADC group regular overrun interrupt.

Allowed values:
0: Disabled: Overrun interrupt disabled
1: Enabled: Overrun interrupt enabled

JEOCIE

Bit 5: ADC group injected end of unitary conversion interrupt.

Allowed values:
0: Disabled: End of injected conversion interrupt disabled
1: Enabled: End of injected conversion interrupt enabled

JEOSIE

Bit 6: ADC group injected end of sequence conversions interrupt.

Allowed values:
0: Disabled: End of injected sequence interrupt disabled
1: Enabled: End of injected sequence interrupt enabled

AWD[1]IE

Bit 7: Analog watchdog 1 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

AWD[2]IE

Bit 8: Analog watchdog 2 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

AWD[3]IE

Bit 9: Analog watchdog 3 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

JQOVFIE

Bit 10: ADC group injected contexts queue overflow interrupt.

Allowed values:
0: Disabled: Injected context queue overflow interrupt disabled
1: Enabled: Injected context queue overflow interrupt enabled

ADEN

Bit 0: ADC enable.

Allowed values:
0: Disabled: ADC disabled
1: Enabled: ADC enabled

ADDIS

Bit 1: ADC disable.

Allowed values:
0: NotDisabling: No disable command active
1: Disabling: ADC disabling

ADSTART

Bit 2: ADC group regular conversion start.

Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting

JADSTART

Bit 3: ADC group injected conversion start.

Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting

ADSTP

Bit 4: ADC group regular conversion stop.

Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion

JADSTP

Bit 5: ADC group injected conversion stop.

Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion

BOOST

Bits 8-9: Boost mode control.

Allowed values:
0: LT6_25: Boost mode used when ADC clock ≤ 6.25 MHz
1: LT12_5: Boost mode used when 6.25 MHz < ADC clock ≤ 12.5 MHz
2: LT25: Boost mode used when 12.5 MHz < ADC clock ≤ 25.0 MHz
3: LT50: Boost mode used when 25.0 MHz < ADC clock ≤ 50.0 MHz

ADCALLIN

Bit 16: Linearity calibration.

Allowed values:
0: NoLinearity: ADC calibration without linearaity calibration
1: Linearity: ADC calibration with linearaity calibration

LINCALRDYW[1]

Bit 22: Linearity calibration ready Word 1.

Allowed values:
0: Reset: LINCALFACT Word Read
1: Set: LINCALFACT Word Write

LINCALRDYW[2]

Bit 23: Linearity calibration ready Word 2.

Allowed values:
0: Reset: LINCALFACT Word Read
1: Set: LINCALFACT Word Write

LINCALRDYW[3]

Bit 24: Linearity calibration ready Word 3.

Allowed values:
0: Reset: LINCALFACT Word Read
1: Set: LINCALFACT Word Write

LINCALRDYW[4]

Bit 25: Linearity calibration ready Word 4.

Allowed values:
0: Reset: LINCALFACT Word Read
1: Set: LINCALFACT Word Write

LINCALRDYW[5]

Bit 26: Linearity calibration ready Word 5.

Allowed values:
0: Reset: LINCALFACT Word Read
1: Set: LINCALFACT Word Write

LINCALRDYW[6]

Bit 27: Linearity calibration ready Word 6.

Allowed values:
0: Reset: LINCALFACT Word Read
1: Set: LINCALFACT Word Write

ADVREGEN

Bit 28: ADC voltage regulator enable.

Allowed values:
0: Disabled: ADC voltage regulator disabled
1: Enabled: ADC voltage regulator enabled

DEEPPWD

Bit 29: ADC deep power down enable.

Allowed values:
0: PowerUp: ADC not in deep power down
1: PowerDown: ADC in deep power down

ADCALDIF

Bit 30: ADC differential mode for calibration.

Allowed values:
0: SingleEnded: Calibration for single-ended mode
1: Differential: Calibration for differential mode

ADCAL

Bit 31: ADC calibration.

Allowed values:
0: NotCalibrating: ADC calibration either not yet performed or completed
1: Calibrating: ADC calibration in progress

DMNGT

Bits 0-1: ADC DMA transfer enable.

Allowed values:
0: DR: Store output data in DR only
1: DMA_OneShot: DMA One Shot Mode selected
2: DFSDM: DFSDM mode selected
3: DMA_Circular: DMA Circular Mode selected

RES

Bits 2-4: ADC data resolution.

Allowed values:
0: SixteenBit: 16-bit resolution
1: FourteenBit: 14-bit resolution in legacy mode (not optimized power consumption)
2: TwelveBit: 12-bit resolution in legacy mode (not optimized power consumption)
3: TenBit: 10-bit resolution
5: FourteenBitV: 14-bit resolution
6: TwelveBitV: 12-bit resolution
7: EightBit: 8-bit resolution

EXTSEL

Bits 5-9: ADC group regular external trigger source.

Allowed values:
0: TIM1_CC1: Timer 1 CC1 event
1: TIM1_CC2: Timer 1 CC2 event
2: TIM1_CC3: Timer 1 CC3 event
3: TIM2_CC2: Timer 2 CC2 event
4: TIM3_TRGO: Timer 3 TRGO event
5: TIM4_CC4: Timer 4 CC4 event
6: EXTI11: EXTI line 11
7: TIM8_TRGO: Timer 8 TRGO event
8: TIM8_TRGO2: Timer 8 TRGO2 event
9: TIM1_TRGO: Timer 1 TRGO event
10: TIM1_TRGO2: Timer 1 TRGO2 event
11: TIM2_TRGO: Timer 2 TRGO event
12: TIM4_TRGO: Timer 4 TRGO event
13: TIM6_TRGO: Timer 6 TRGO event
14: TIM15_TRGO: Timer 15 TRGO event
15: TIM3_CC4: Timer 3 CC4 event
16: HRTIM1_ADCTRG1: HRTIM1_ADCTRG1 event
17: HRTIM1_ADCTRG3: HRTIM1_ADCTRG3 event
18: LPTIM1_OUT: LPTIM1_OUT event
19: LPTIM2_OUT: LPTIM2_OUT event
20: LPTIM3_OUT: LPTIM3_OUT event

EXTEN

Bits 10-11: ADC group regular external trigger polarity.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

OVRMOD

Bit 12: ADC group regular overrun configuration.

Allowed values:
0: Preserve: Preserve DR register when an overrun is detected
1: Overwrite: Overwrite DR register when an overrun is detected

CONT

Bit 13: ADC group regular continuous conversion mode.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

AUTDLY

Bit 14: ADC low power auto wait.

Allowed values:
0: Off: Auto delayed conversion mode off
1: On: Auto delayed conversion mode on

DISCEN

Bit 16: ADC group regular sequencer discontinuous mode.

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

DISCNUM

Bits 17-19: ADC group regular sequencer discontinuous number of ranks.

Allowed values: 0x0-0x7

JDISCEN

Bit 20: ADC group injected sequencer discontinuous mode.

Allowed values:
0: Disabled: Discontinuous mode on injected channels disabled
1: Enabled: Discontinuous mode on injected channels enabled

JQM

Bit 21: ADC group injected contexts queue mode.

Allowed values:
0: Mode0: JSQR Mode 0: Queue maintains the last written configuration into JSQR
1: Mode1: JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence

AWD1SGL

Bit 22: ADC analog watchdog 1 monitoring a single channel or all channels.

Allowed values:
0: All: Analog watchdog 1 enabled on all channels
1: Single: Analog watchdog 1 enabled on single channel selected in AWD1CH

AWD1EN

Bit 23: ADC analog watchdog 1 enable on scope ADC group regular.

Allowed values:
0: Disabled: Analog watchdog 1 disabled on regular channels
1: Enabled: Analog watchdog 1 enabled on regular channels

JAWD1EN

Bit 24: ADC analog watchdog 1 enable on scope ADC group injected.

Allowed values:
0: Disabled: Analog watchdog 1 disabled on injected channels
1: Enabled: Analog watchdog 1 enabled on injected channels

JAUTO

Bit 25: ADC group injected automatic trigger mode.

Allowed values:
0: Disabled: Automatic injected group conversion disabled
1: Enabled: Automatic injected group conversion enabled

AWD1CH

Bits 26-30: ADC analog watchdog 1 monitored channel selection.

Allowed values: 0x0-0x13

JQDIS

Bit 31: ADC group injected contexts queue disable.

Allowed values:
0: Enabled: Injected Queue enabled
1: Disabled: Injected Queue disabled

ROVSE

Bit 0: ADC oversampler enable on scope ADC group regular.

Allowed values:
0: Disabled: Regular oversampling disabled
1: Enabled: Regular oversampling enabled

JOVSE

Bit 1: ADC oversampler enable on scope ADC group injected.

Allowed values:
0: Disabled: Injected oversampling disabled
1: Enabled: Injected oversampling enabled

OVSS

Bits 5-8: ADC oversampling shift.

Allowed values: 0x0-0xb

TROVS

Bit 9: ADC oversampling discontinuous mode (triggered mode) for ADC group regular.

Allowed values:
0: Automatic: All oversampled conversions for a channel are run following a trigger
1: Triggered: Each oversampled conversion for a channel needs a new trigger

ROVSM

Bit 10: Regular Oversampling mode.

Allowed values:
0: Continued: Oversampling is temporary stopped and continued after injection sequence
1: Resumed: Oversampling is aborted and resumed from start after injection sequence

RSHIFT[1]

Bit 11: Right-shift data after Offset 1 correction.

Allowed values:
0: Disabled: Right-shifting disabled
1: Enabled: Data is right-shifted 1-bit

RSHIFT[2]

Bit 12: Right-shift data after Offset 2 correction.

Allowed values:
0: Disabled: Right-shifting disabled
1: Enabled: Data is right-shifted 1-bit

RSHIFT[3]

Bit 13: Right-shift data after Offset 3 correction.

Allowed values:
0: Disabled: Right-shifting disabled
1: Enabled: Data is right-shifted 1-bit

RSHIFT[4]

Bit 14: Right-shift data after Offset 4 correction.

Allowed values:
0: Disabled: Right-shifting disabled
1: Enabled: Data is right-shifted 1-bit

OSVR

Bits 16-25: Oversampling ratio.

Allowed values: 0x0-0x3ff

LSHIFT

Bits 28-31: Left shift factor.

Allowed values: 0x0-0xf

SMP[0]

Bits 0-2: Channel 0 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[1]

Bits 3-5: Channel 1 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[2]

Bits 6-8: Channel 2 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[3]

Bits 9-11: Channel 3 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[4]

Bits 12-14: Channel 4 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[5]

Bits 15-17: Channel 5 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[6]

Bits 18-20: Channel 6 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[7]

Bits 21-23: Channel 7 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[8]

Bits 24-26: Channel 8 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[9]

Bits 27-29: Channel 9 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[10]

Bits 0-2: Channel 10 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[11]

Bits 3-5: Channel 11 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[12]

Bits 6-8: Channel 12 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[13]

Bits 9-11: Channel 13 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[14]

Bits 12-14: Channel 14 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[15]

Bits 15-17: Channel 15 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[16]

Bits 18-20: Channel 16 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[17]

Bits 21-23: Channel 17 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[18]

Bits 24-26: Channel 18 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[19]

Bits 27-29: Channel 19 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

PCSEL

Bits 0-19: Channel x (VINP[i]) pre selection.

Allowed values:
0: NotPreselected: Input channel x is not pre-selected
1: Preselected: Pre-select input channel x

LTR1

Bits 0-25: ADC analog watchdog 1 threshold low.

Allowed values: 0x0-0x3ffffff

HTR1

Bits 0-25: ADC analog watchdog 2 threshold low.

Allowed values: 0x0-0x3ffffff

L

Bits 0-3: L3.

Allowed values: 0x0-0xf

SQ[1]

Bits 6-10: 1 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[2]

Bits 12-16: 2 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[3]

Bits 18-22: 3 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[4]

Bits 24-28: 4 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[5]

Bits 0-4: 5 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[6]

Bits 6-10: 6 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[7]

Bits 12-16: 7 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[8]

Bits 18-22: 8 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[9]

Bits 24-28: 9 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[10]

Bits 0-4: 10 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[11]

Bits 6-10: 11 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[12]

Bits 12-16: 12 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[13]

Bits 18-22: 13 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[14]

Bits 24-28: 14 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[15]

Bits 0-4: 15 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[16]

Bits 6-10: 16 conversion in regular sequence.

Allowed values: 0x0-0x13

RDATA

Bits 0-31: ADC group regular conversion data.

JL

Bits 0-1: ADC group injected sequencer scan length.

Allowed values: 0x0-0x3

JEXTSEL

Bits 2-6: ADC group injected external trigger source.

Allowed values:
0: TIM1_TRGO: Timer 1 TRGO event
1: TIM1_CC4: Timer 1 CC4 event
2: TIM2_TRGO: Timer 2 TRGO event
3: TIM2_CC1: Timer 2 CC1 event
4: TIM3_CC4: Timer 3 CC4 event
5: TIM4_TRGO: Timer 4 TRGO event
6: EXTI15: EXTI line 15
7: TIM8_CC4: Timer 8 CC4 event
8: TIM1_TRGO2: Timer 1 TRGO2 event
9: TIM8_TRGO: Timer 8 TRGO event
10: TIM8_TRGO2: Timer 8 TRGO2 event
11: TIM3_CC3: Timer 3 CC3 event
12: TIM3_TRGO: Timer 3 TRGO event
13: TIM3_CC1: Timer 3 CC1 event
14: TIM6_TRGO: Timer 6 TRGO event
15: TIM15_TRGO: Timer 15 TRGO event
16: HRTIM1_ADCTRG2: HRTIM1_ADCTRG2 event
17: HRTIM1_ADCTRG4: HRTIM1_ADCTRG4 event
18: LPTIM1_OUT: LPTIM1_OUT event
19: LPTIM2_OUT: LPTIM2_OUT event
20: LPTIM3_OUT: LPTIM3_OUT event

JEXTEN

Bits 7-8: ADC group injected external trigger polarity.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

JSQ[1]

Bits 9-13: 1 conversion in injected sequence.

Allowed values: 0x0-0x13

JSQ[2]

Bits 15-19: 2 conversion in injected sequence.

Allowed values: 0x0-0x13

JSQ[3]

Bits 21-25: 3 conversion in injected sequence.

Allowed values: 0x0-0x13

JSQ[4]

Bits 27-31: 4 conversion in injected sequence.

Allowed values: 0x0-0x13

OFFSET

Bits 0-25: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0x3ffffff

OFFSET_CH

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

SSATE

Bit 31: Signed saturation enable.

Allowed values:
0: Disabled: Offset is subtracted maintaining data integrity and extending result size (9-bit and 17-bit signed format)
1: Enabled: Offset is subtracted and result is saturated to maintain result size

OFFSET

Bits 0-25: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0x3ffffff

OFFSET_CH

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

SSATE

Bit 31: Signed saturation enable.

Allowed values:
0: Disabled: Offset is subtracted maintaining data integrity and extending result size (9-bit and 17-bit signed format)
1: Enabled: Offset is subtracted and result is saturated to maintain result size

OFFSET

Bits 0-25: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0x3ffffff

OFFSET_CH

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

SSATE

Bit 31: Signed saturation enable.

Allowed values:
0: Disabled: Offset is subtracted maintaining data integrity and extending result size (9-bit and 17-bit signed format)
1: Enabled: Offset is subtracted and result is saturated to maintain result size

OFFSET

Bits 0-25: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0x3ffffff

OFFSET_CH

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

SSATE

Bit 31: Signed saturation enable.

Allowed values:
0: Disabled: Offset is subtracted maintaining data integrity and extending result size (9-bit and 17-bit signed format)
1: Enabled: Offset is subtracted and result is saturated to maintain result size

JDATA

Bits 0-31: Injected data.

JDATA

Bits 0-31: Injected data.

JDATA

Bits 0-31: Injected data.

JDATA

Bits 0-31: Injected data.

AWD2CH[0]

Bit 0: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[1]

Bit 1: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[2]

Bit 2: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[3]

Bit 3: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[4]

Bit 4: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[5]

Bit 5: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[6]

Bit 6: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[7]

Bit 7: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[8]

Bit 8: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[9]

Bit 9: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[10]

Bit 10: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[11]

Bit 11: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[12]

Bit 12: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[13]

Bit 13: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[14]

Bit 14: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[15]

Bit 15: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[16]

Bit 16: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[17]

Bit 17: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[18]

Bit 18: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[19]

Bit 19: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[0]

Bit 1: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[1]

Bit 2: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[2]

Bit 3: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[3]

Bit 4: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[4]

Bit 5: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[5]

Bit 6: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[6]

Bit 7: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[7]

Bit 8: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[8]

Bit 9: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[9]

Bit 10: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[10]

Bit 11: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[11]

Bit 12: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[12]

Bit 13: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[13]

Bit 14: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[14]

Bit 15: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[15]

Bit 16: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[16]

Bit 17: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[17]

Bit 18: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[18]

Bit 19: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[19]

Bit 20: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

LTR2

Bits 0-25: Analog watchdog 2 lower threshold.

Allowed values: 0x0-0x3ffffff

HTR2

Bits 0-25: Analog watchdog 2 higher threshold.

Allowed values: 0x0-0x3ffffff

LTR3

Bits 0-25: Analog watchdog 3 lower threshold.

Allowed values: 0x0-0x3ffffff

HTR3

Bits 0-25: Analog watchdog 3 higher threshold.

Allowed values: 0x0-0x3ffffff

DIFSEL[0]

Bit 0: Differential mode for channel 0.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[1]

Bit 1: Differential mode for channel 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[2]

Bit 2: Differential mode for channel 2.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[3]

Bit 3: Differential mode for channel 3.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[4]

Bit 4: Differential mode for channel 4.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[5]

Bit 5: Differential mode for channel 5.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[6]

Bit 6: Differential mode for channel 6.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[7]

Bit 7: Differential mode for channel 7.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[8]

Bit 8: Differential mode for channel 8.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[9]

Bit 9: Differential mode for channel 9.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[10]

Bit 10: Differential mode for channel 10.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[11]

Bit 11: Differential mode for channel 11.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[12]

Bit 12: Differential mode for channel 12.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[13]

Bit 13: Differential mode for channel 13.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[14]

Bit 14: Differential mode for channel 14.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[15]

Bit 15: Differential mode for channel 15.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[16]

Bit 16: Differential mode for channel 16.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[17]

Bit 17: Differential mode for channel 17.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[18]

Bit 18: Differential mode for channel 18.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[19]

Bit 19: Differential mode for channel 19.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

CALFACT_S

Bits 0-10: ADC calibration factor in single-ended mode.

Allowed values: 0x0-0x7ff

CALFACT_D

Bits 16-26: ADC calibration factor in differential mode.

Allowed values: 0x0-0x7ff

LINCALFACT

Bits 0-29: Linearity Calibration Factor.

Allowed values: 0x0-0x3fffffff

ADRDY_MST

Bit 0: Master ADC ready.

Allowed values:
0: NotReady: ADC is not ready to start conversion
1: Ready: ADC is ready to start conversion

EOSMP_MST

Bit 1: End of Sampling phase flag of the master ADC.

Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached

EOC_MST

Bit 2: End of regular conversion of the master ADC.

Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete

EOS_MST

Bit 3: End of regular sequence flag of the master ADC.

Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete

OVR_MST

Bit 4: Overrun flag of the master ADC.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

JEOC_MST

Bit 5: End of injected conversion flag of the master ADC.

Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete

JEOS_MST

Bit 6: End of injected sequence flag of the master ADC.

Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete

AWD1_MST

Bit 7: Analog watchdog 1 flag of the master ADC.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD2_MST

Bit 8: Analog watchdog 2 flag of the master ADC.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD3_MST

Bit 9: Analog watchdog 3 flag of the master ADC.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

JQOVF_MST

Bit 10: Injected Context Queue Overflow flag of the master ADC.

Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred

ADRDY_SLV

Bit 16: Slave ADC ready.

Allowed values:
0: NotReady: ADC is not ready to start conversion
1: Ready: ADC is ready to start conversion

EOSMP_SLV

Bit 17: End of Sampling phase flag of the slave ADC.

Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached

EOC_SLV

Bit 18: End of regular conversion of the slave ADC.

Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete

EOS_SLV

Bit 19: End of regular sequence flag of the slave ADC.

Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete

OVR_SLV

Bit 20: Overrun flag of the slave ADC.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

JEOC_SLV

Bit 21: End of injected conversion flag of the slave ADC.

Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete

JEOS_SLV

Bit 22: End of injected sequence flag of the slave ADC.

Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete

AWD1_SLV

Bit 23: Analog watchdog 1 flag of the slave ADC.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD2_SLV

Bit 24: Analog watchdog 2 flag of the slave ADC.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD3_SLV

Bit 25: Analog watchdog 3 flag of the slave ADC.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

JQOVF_SLV

Bit 26: Injected Context Queue Overflow flag of the slave ADC.

Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred

DUAL

Bits 0-4: Dual ADC mode selection.

Allowed values:
0: Independent: Independent mode
1: DualRJ: Dual, combined regular simultaneous + injected simultaneous mode
2: DualRA: Dual, combined regular simultaneous + alternate trigger mode
3: DualIJ: Dual, combined interleaved mode + injected simultaneous mode
5: DualJ: Dual, injected simultaneous mode only
6: DualR: Dual, regular simultaneous mode only
7: DualI: Dual, interleaved mode only
9: DualA: Dual, alternate trigger mode only

DELAY

Bits 8-11: Delay between 2 sampling phases.

Allowed values: 0x0-0xf

DAMDF

Bits 14-15: Dual ADC Mode Data Format.

Allowed values:
0: NoPack: Without data packing, CDR/CDR2 not used
2: Format32to10: CDR formatted for 32-bit down to 10-bit resolution
3: Format8: CDR formatted for 8-bit resolution

CKMODE

Bits 16-17: ADC clock mode.

Allowed values:
0: Asynchronous: Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock
1: SyncDiv1: Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck
2: SyncDiv2: Use AHB clock rcc_hclk3 divided by 2
3: SyncDiv4: Use AHB clock rcc_hclk3 divided by 4

PRESC

Bits 18-21: ADC prescaler.

Allowed values:
0: Div1: adc_ker_ck_input not divided
1: Div2: adc_ker_ck_input divided by 2
2: Div4: adc_ker_ck_input divided by 4
3: Div6: adc_ker_ck_input divided by 6
4: Div8: adc_ker_ck_input divided by 8
5: Div10: adc_ker_ck_input divided by 10
6: Div12: adc_ker_ck_input divided by 12
7: Div16: adc_ker_ck_input divided by 16
8: Div32: adc_ker_ck_input divided by 32
9: Div64: adc_ker_ck_input divided by 64
10: Div128: adc_ker_ck_input divided by 128
11: Div256: adc_ker_ck_input divided by 256

VREFEN

Bit 22: VREFINT enable.

Allowed values:
0: Disabled: V_REFINT channel disabled
1: Enabled: V_REFINT channel enabled

VSENSEEN

Bit 23: Temperature sensor enable.

Allowed values:
0: Disabled: The selected ADC channel disabled
1: Enabled: The selected ADC channel enabled

VBATEN

Bit 24: VBAT enable.

Allowed values:
0: Disabled: The selected ADC channel disabled
1: Enabled: The selected ADC channel enabled

RDATA_MST

Bits 0-15: Regular data of the master ADC.

RDATA_SLV

Bits 16-31: Regular data of the slave ADC.

ADRDY

Bit 0: ADC ready flag.

Allowed values:
0: NotReady: ADC is not ready to start conversion
1: Ready: ADC is ready to start conversion

EOSMP

Bit 1: ADC group regular end of sampling flag.

Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached

EOC

Bit 2: ADC group regular end of unitary conversion flag.

Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete

EOS

Bit 3: ADC group regular end of sequence conversions flag.

Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete

OVR

Bit 4: ADC group regular overrun flag.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

JEOC

Bit 5: ADC group injected end of unitary conversion flag.

Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete

JEOS

Bit 6: ADC group injected end of sequence conversions flag.

Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete

AWD[1]

Bit 7: Analog watchdog 1 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD[2]

Bit 8: Analog watchdog 2 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD[3]

Bit 9: Analog watchdog 3 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

JQOVF

Bit 10: ADC group injected contexts queue overflow flag.

Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred

ADRDYIE

Bit 0: ADC ready interrupt.

Allowed values:
0: Disabled: ADC ready interrupt disabled
1: Enabled: ADC ready interrupt enabled

EOSMPIE

Bit 1: ADC group regular end of sampling interrupt.

Allowed values:
0: Disabled: End of regular conversion sampling phase interrupt disabled
1: Enabled: End of regular conversion sampling phase interrupt enabled

EOCIE

Bit 2: ADC group regular end of unitary conversion interrupt.

Allowed values:
0: Disabled: End of regular conversion interrupt disabled
1: Enabled: End of regular conversion interrupt enabled

EOSIE

Bit 3: ADC group regular end of sequence conversions interrupt.

Allowed values:
0: Disabled: End of regular sequence interrupt disabled
1: Enabled: End of regular sequence interrupt enabled

OVRIE

Bit 4: ADC group regular overrun interrupt.

Allowed values:
0: Disabled: Overrun interrupt disabled
1: Enabled: Overrun interrupt enabled

JEOCIE

Bit 5: ADC group injected end of unitary conversion interrupt.

Allowed values:
0: Disabled: End of injected conversion interrupt disabled
1: Enabled: End of injected conversion interrupt enabled

JEOSIE

Bit 6: ADC group injected end of sequence conversions interrupt.

Allowed values:
0: Disabled: End of injected sequence interrupt disabled
1: Enabled: End of injected sequence interrupt enabled

AWD[1]IE

Bit 7: Analog watchdog 1 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

AWD[2]IE

Bit 8: Analog watchdog 2 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

AWD[3]IE

Bit 9: Analog watchdog 3 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

JQOVFIE

Bit 10: ADC group injected contexts queue overflow interrupt.

Allowed values:
0: Disabled: Injected context queue overflow interrupt disabled
1: Enabled: Injected context queue overflow interrupt enabled

ADEN

Bit 0: ADC enable.

Allowed values:
0: Disabled: ADC disabled
1: Enabled: ADC enabled

ADDIS

Bit 1: ADC disable.

Allowed values:
0: NotDisabling: No disable command active
1: Disabling: ADC disabling

ADSTART

Bit 2: ADC group regular conversion start.

Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting

JADSTART

Bit 3: ADC group injected conversion start.

Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting

ADSTP

Bit 4: ADC group regular conversion stop.

Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion

JADSTP

Bit 5: ADC group injected conversion stop.

Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion

BOOST

Bits 8-9: Boost mode control.

Allowed values:
0: LT6_25: Boost mode used when ADC clock ≤ 6.25 MHz
1: LT12_5: Boost mode used when 6.25 MHz < ADC clock ≤ 12.5 MHz
2: LT25: Boost mode used when 12.5 MHz < ADC clock ≤ 25.0 MHz
3: LT50: Boost mode used when 25.0 MHz < ADC clock ≤ 50.0 MHz

ADCALLIN

Bit 16: Linearity calibration.

Allowed values:
0: NoLinearity: ADC calibration without linearaity calibration
1: Linearity: ADC calibration with linearaity calibration