Overall: 12093/17592 fields covered

ADC1

0x40022000: Analog to Digital Converter

199/199 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 IER
0x8 CR
0xc CFGR
0x10 CFGR2
0x14 SMPR1
0x18 SMPR2
0x1c PCSEL
0x20 LTR1
0x24 HTR1
0x30 SQR1
0x34 SQR2
0x38 SQR3
0x3c SQR4
0x40 DR
0x4c JSQR
0x60 OFR[1]
0x64 OFR[2]
0x68 OFR[3]
0x6c OFR[4]
0x80 JDR[1]
0x84 JDR[2]
0x88 JDR[3]
0x8c JDR[4]
0xa0 AWD2CR
0xa4 AWD3CR
0xb0 LTR2
0xb4 HTR2
0xb8 LTR3
0xbc HTR3
0xc0 DIFSEL
0xc4 CALFACT
0xc8 CALFACT2
Toggle registers

ISR

ADC interrupt and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVF
r/w1c
AWD[3]
r/w1c
AWD[2]
r/w1c
AWD[1]
r/w1c
JEOS
r/w1c
JEOC
r/w1c
OVR
r/w1c
EOS
r/w1c
EOC
r/w1c
EOSMP
r/w1c
ADRDY
r/w1c
Toggle fields

ADRDY

Bit 0: ADC ready flag.

Allowed values:
0: NotReady: ADC is not ready to start conversion
1: Ready: ADC is ready to start conversion

EOSMP

Bit 1: ADC group regular end of sampling flag.

Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached

EOC

Bit 2: ADC group regular end of unitary conversion flag.

Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete

EOS

Bit 3: ADC group regular end of sequence conversions flag.

Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete

OVR

Bit 4: ADC group regular overrun flag.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

JEOC

Bit 5: ADC group injected end of unitary conversion flag.

Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete

JEOS

Bit 6: ADC group injected end of sequence conversions flag.

Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete

AWD[1]

Bit 7: Analog watchdog 1 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD[2]

Bit 8: Analog watchdog 2 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD[3]

Bit 9: Analog watchdog 3 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

JQOVF

Bit 10: ADC group injected contexts queue overflow flag.

Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred

IER

ADC interrupt enable register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

Toggle fields

ADRDYIE

Bit 0: ADC ready interrupt.

Allowed values:
0: Disabled: ADC ready interrupt disabled
1: Enabled: ADC ready interrupt enabled

EOSMPIE

Bit 1: ADC group regular end of sampling interrupt.

Allowed values:
0: Disabled: End of regular conversion sampling phase interrupt disabled
1: Enabled: End of regular conversion sampling phase interrupt enabled

EOCIE

Bit 2: ADC group regular end of unitary conversion interrupt.

Allowed values:
0: Disabled: End of regular conversion interrupt disabled
1: Enabled: End of regular conversion interrupt enabled

EOSIE

Bit 3: ADC group regular end of sequence conversions interrupt.

Allowed values:
0: Disabled: End of regular sequence interrupt disabled
1: Enabled: End of regular sequence interrupt enabled

OVRIE

Bit 4: ADC group regular overrun interrupt.

Allowed values:
0: Disabled: Overrun interrupt disabled
1: Enabled: Overrun interrupt enabled

JEOCIE

Bit 5: ADC group injected end of unitary conversion interrupt.

Allowed values:
0: Disabled: End of injected conversion interrupt disabled
1: Enabled: End of injected conversion interrupt enabled

JEOSIE

Bit 6: ADC group injected end of sequence conversions interrupt.

Allowed values:
0: Disabled: End of injected sequence interrupt disabled
1: Enabled: End of injected sequence interrupt enabled

AWD[1]IE

Bit 7: Analog watchdog 1 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

AWD[2]IE

Bit 8: Analog watchdog 2 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

AWD[3]IE

Bit 9: Analog watchdog 3 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

JQOVFIE

Bit 10: ADC group injected contexts queue overflow interrupt.

Allowed values:
0: Disabled: Injected context queue overflow interrupt disabled
1: Enabled: Injected context queue overflow interrupt enabled

CR

ADC control register

Offset: 0x8, size: 32, reset: 0x20000000, access: read-write

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADCAL
r/w1s
ADCALDIF
rw
DEEPPWD
rw
ADVREGEN
rw
LINCALRDYW[6]
rw
LINCALRDYW[5]
rw
LINCALRDYW[4]
rw
LINCALRDYW[3]
rw
LINCALRDYW[2]
rw
LINCALRDYW[1]
rw
ADCALLIN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOST
rw
JADSTP
r/w1s
ADSTP
r/w1s
JADSTART
r/w1s
ADSTART
r/w1s
ADDIS
r/w1s
ADEN
r/w1s
Toggle fields

ADEN

Bit 0: ADC enable.

Allowed values:
0: Disabled: ADC disabled
1: Enabled: ADC enabled

ADDIS

Bit 1: ADC disable.

Allowed values:
0: NotDisabling: No disable command active
1: Disabling: ADC disabling

ADSTART

Bit 2: ADC group regular conversion start.

Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting

JADSTART

Bit 3: ADC group injected conversion start.

Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting

ADSTP

Bit 4: ADC group regular conversion stop.

Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion

JADSTP

Bit 5: ADC group injected conversion stop.

Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion

BOOST

Bits 8-9: Boost mode control.

Allowed values:
0: LT6_25: Boost mode used when ADC clock ≤ 6.25 MHz
1: LT12_5: Boost mode used when 6.25 MHz < ADC clock ≤ 12.5 MHz
2: LT25: Boost mode used when 12.5 MHz < ADC clock ≤ 25.0 MHz
3: LT50: Boost mode used when 25.0 MHz < ADC clock ≤ 50.0 MHz

ADCALLIN

Bit 16: Linearity calibration.

Allowed values:
0: NoLinearity: ADC calibration without linearaity calibration
1: Linearity: ADC calibration with linearaity calibration

LINCALRDYW[1]

Bit 22: Linearity calibration ready Word 1.

Allowed values:
0: Reset: LINCALFACT Word Read
1: Set: LINCALFACT Word Write

LINCALRDYW[2]

Bit 23: Linearity calibration ready Word 2.

Allowed values:
0: Reset: LINCALFACT Word Read
1: Set: LINCALFACT Word Write

LINCALRDYW[3]

Bit 24: Linearity calibration ready Word 3.

Allowed values:
0: Reset: LINCALFACT Word Read
1: Set: LINCALFACT Word Write

LINCALRDYW[4]

Bit 25: Linearity calibration ready Word 4.

Allowed values:
0: Reset: LINCALFACT Word Read
1: Set: LINCALFACT Word Write

LINCALRDYW[5]

Bit 26: Linearity calibration ready Word 5.

Allowed values:
0: Reset: LINCALFACT Word Read
1: Set: LINCALFACT Word Write

LINCALRDYW[6]

Bit 27: Linearity calibration ready Word 6.

Allowed values:
0: Reset: LINCALFACT Word Read
1: Set: LINCALFACT Word Write

ADVREGEN

Bit 28: ADC voltage regulator enable.

Allowed values:
0: Disabled: ADC voltage regulator disabled
1: Enabled: ADC voltage regulator enabled

DEEPPWD

Bit 29: ADC deep power down enable.

Allowed values:
0: PowerUp: ADC not in deep power down
1: PowerDown: ADC in deep power down

ADCALDIF

Bit 30: ADC differential mode for calibration.

Allowed values:
0: SingleEnded: Calibration for single-ended mode
1: Differential: Calibration for differential mode

ADCAL

Bit 31: ADC calibration.

Allowed values:
0: NotCalibrating: ADC calibration either not yet performed or completed
1: Calibrating: ADC calibration in progress

CFGR

ADC configuration register 1

Offset: 0xc, size: 32, reset: 0x80000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JQDIS
rw
AWD1CH
rw
JAUTO
rw
JAWD1EN
rw
AWD1EN
rw
AWD1SGL
rw
JQM
rw
JDISCEN
rw
DISCNUM
rw
DISCEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUTDLY
rw
CONT
rw
OVRMOD
rw
EXTEN
rw
EXTSEL
rw
RES
rw
DMNGT
rw
Toggle fields

DMNGT

Bits 0-1: ADC DMA transfer enable.

Allowed values:
0: DR: Store output data in DR only
1: DMA_OneShot: DMA One Shot Mode selected
2: DFSDM: DFSDM mode selected
3: DMA_Circular: DMA Circular Mode selected

RES

Bits 2-4: ADC data resolution.

Allowed values:
0: SixteenBit: 16-bit resolution
1: FourteenBit: 14-bit resolution in legacy mode (not optimized power consumption)
2: TwelveBit: 12-bit resolution in legacy mode (not optimized power consumption)
3: TenBit: 10-bit resolution
5: FourteenBitV: 14-bit resolution
6: TwelveBitV: 12-bit resolution
7: EightBit: 8-bit resolution

EXTSEL

Bits 5-9: ADC group regular external trigger source.

Allowed values:
0: TIM1_CC1: Timer 1 CC1 event
1: TIM1_CC2: Timer 1 CC2 event
2: TIM1_CC3: Timer 1 CC3 event
3: TIM2_CC2: Timer 2 CC2 event
4: TIM3_TRGO: Timer 3 TRGO event
5: TIM4_CC4: Timer 4 CC4 event
6: EXTI11: EXTI line 11
7: TIM8_TRGO: Timer 8 TRGO event
8: TIM8_TRGO2: Timer 8 TRGO2 event
9: TIM1_TRGO: Timer 1 TRGO event
10: TIM1_TRGO2: Timer 1 TRGO2 event
11: TIM2_TRGO: Timer 2 TRGO event
12: TIM4_TRGO: Timer 4 TRGO event
13: TIM6_TRGO: Timer 6 TRGO event
14: TIM15_TRGO: Timer 15 TRGO event
15: TIM3_CC4: Timer 3 CC4 event
16: HRTIM1_ADCTRG1: HRTIM1_ADCTRG1 event
17: HRTIM1_ADCTRG3: HRTIM1_ADCTRG3 event
18: LPTIM1_OUT: LPTIM1_OUT event
19: LPTIM2_OUT: LPTIM2_OUT event
20: LPTIM3_OUT: LPTIM3_OUT event

EXTEN

Bits 10-11: ADC group regular external trigger polarity.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

OVRMOD

Bit 12: ADC group regular overrun configuration.

Allowed values:
0: Preserve: Preserve DR register when an overrun is detected
1: Overwrite: Overwrite DR register when an overrun is detected

CONT

Bit 13: ADC group regular continuous conversion mode.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

AUTDLY

Bit 14: ADC low power auto wait.

Allowed values:
0: Off: Auto delayed conversion mode off
1: On: Auto delayed conversion mode on

DISCEN

Bit 16: ADC group regular sequencer discontinuous mode.

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

DISCNUM

Bits 17-19: ADC group regular sequencer discontinuous number of ranks.

Allowed values: 0x0-0x7

JDISCEN

Bit 20: ADC group injected sequencer discontinuous mode.

Allowed values:
0: Disabled: Discontinuous mode on injected channels disabled
1: Enabled: Discontinuous mode on injected channels enabled

JQM

Bit 21: ADC group injected contexts queue mode.

Allowed values:
0: Mode0: JSQR Mode 0: Queue maintains the last written configuration into JSQR
1: Mode1: JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence

AWD1SGL

Bit 22: ADC analog watchdog 1 monitoring a single channel or all channels.

Allowed values:
0: All: Analog watchdog 1 enabled on all channels
1: Single: Analog watchdog 1 enabled on single channel selected in AWD1CH

AWD1EN

Bit 23: ADC analog watchdog 1 enable on scope ADC group regular.

Allowed values:
0: Disabled: Analog watchdog 1 disabled on regular channels
1: Enabled: Analog watchdog 1 enabled on regular channels

JAWD1EN

Bit 24: ADC analog watchdog 1 enable on scope ADC group injected.

Allowed values:
0: Disabled: Analog watchdog 1 disabled on injected channels
1: Enabled: Analog watchdog 1 enabled on injected channels

JAUTO

Bit 25: ADC group injected automatic trigger mode.

Allowed values:
0: Disabled: Automatic injected group conversion disabled
1: Enabled: Automatic injected group conversion enabled

AWD1CH

Bits 26-30: ADC analog watchdog 1 monitored channel selection.

Allowed values: 0x0-0x13

JQDIS

Bit 31: ADC group injected contexts queue disable.

Allowed values:
0: Enabled: Injected Queue enabled
1: Disabled: Injected Queue disabled

CFGR2

ADC configuration register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LSHIFT
rw
OSVR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSHIFT[4]
rw
RSHIFT[3]
rw
RSHIFT[2]
rw
RSHIFT[1]
rw
ROVSM
rw
TROVS
rw
OVSS
rw
JOVSE
rw
ROVSE
rw
Toggle fields

ROVSE

Bit 0: ADC oversampler enable on scope ADC group regular.

Allowed values:
0: Disabled: Regular oversampling disabled
1: Enabled: Regular oversampling enabled

JOVSE

Bit 1: ADC oversampler enable on scope ADC group injected.

Allowed values:
0: Disabled: Injected oversampling disabled
1: Enabled: Injected oversampling enabled

OVSS

Bits 5-8: ADC oversampling shift.

Allowed values: 0x0-0xb

TROVS

Bit 9: ADC oversampling discontinuous mode (triggered mode) for ADC group regular.

Allowed values:
0: Automatic: All oversampled conversions for a channel are run following a trigger
1: Triggered: Each oversampled conversion for a channel needs a new trigger

ROVSM

Bit 10: Regular Oversampling mode.

Allowed values:
0: Continued: Oversampling is temporary stopped and continued after injection sequence
1: Resumed: Oversampling is aborted and resumed from start after injection sequence

RSHIFT[1]

Bit 11: Right-shift data after Offset 1 correction.

Allowed values:
0: Disabled: Right-shifting disabled
1: Enabled: Data is right-shifted 1-bit

RSHIFT[2]

Bit 12: Right-shift data after Offset 2 correction.

Allowed values:
0: Disabled: Right-shifting disabled
1: Enabled: Data is right-shifted 1-bit

RSHIFT[3]

Bit 13: Right-shift data after Offset 3 correction.

Allowed values:
0: Disabled: Right-shifting disabled
1: Enabled: Data is right-shifted 1-bit

RSHIFT[4]

Bit 14: Right-shift data after Offset 4 correction.

Allowed values:
0: Disabled: Right-shifting disabled
1: Enabled: Data is right-shifted 1-bit

OSVR

Bits 16-25: Oversampling ratio.

Allowed values: 0x0-0x3ff

LSHIFT

Bits 28-31: Left shift factor.

Allowed values: 0x0-0xf

SMPR1

ADC sampling time register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP[9]
rw
SMP[8]
rw
SMP[7]
rw
SMP[6]
rw
SMP[5]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP[5]
rw
SMP[4]
rw
SMP[3]
rw
SMP[2]
rw
SMP[1]
rw
SMP[0]
rw
Toggle fields

SMP[0]

Bits 0-2: Channel 0 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[1]

Bits 3-5: Channel 1 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[2]

Bits 6-8: Channel 2 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[3]

Bits 9-11: Channel 3 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[4]

Bits 12-14: Channel 4 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[5]

Bits 15-17: Channel 5 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[6]

Bits 18-20: Channel 6 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[7]

Bits 21-23: Channel 7 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[8]

Bits 24-26: Channel 8 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[9]

Bits 27-29: Channel 9 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMPR2

ADC sampling time register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP[19]
rw
SMP[18]
rw
SMP[17]
rw
SMP[16]
rw
SMP[15]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP[15]
rw
SMP[14]
rw
SMP[13]
rw
SMP[12]
rw
SMP[11]
rw
SMP[10]
rw
Toggle fields

SMP[10]

Bits 0-2: Channel 10 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[11]

Bits 3-5: Channel 11 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[12]

Bits 6-8: Channel 12 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[13]

Bits 9-11: Channel 13 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[14]

Bits 12-14: Channel 14 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[15]

Bits 15-17: Channel 15 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[16]

Bits 18-20: Channel 16 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[17]

Bits 21-23: Channel 17 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[18]

Bits 24-26: Channel 18 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[19]

Bits 27-29: Channel 19 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

PCSEL

ADC pre channel selection register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCSEL
rw
Toggle fields

PCSEL

Bits 0-19: Channel x (VINP[i]) pre selection.

Allowed values:
0: NotPreselected: Input channel x is not pre-selected
1: Preselected: Pre-select input channel x

LTR1

ADC analog watchdog 1 threshold register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LTR1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LTR1
rw
Toggle fields

LTR1

Bits 0-25: ADC analog watchdog 1 threshold low.

Allowed values: 0x0-0x3ffffff

HTR1

ADC analog watchdog 2 threshold register

Offset: 0x24, size: 32, reset: 0x03FFFFFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HTR1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HTR1
rw
Toggle fields

HTR1

Bits 0-25: ADC analog watchdog 2 threshold low.

Allowed values: 0x0-0x3ffffff

SQR1

ADC group regular sequencer ranks register 1

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ[4]
rw
SQ[3]
rw
SQ[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ[2]
rw
SQ[1]
rw
L
rw
Toggle fields

L

Bits 0-3: L3.

Allowed values: 0x0-0xf

SQ[1]

Bits 6-10: 1 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[2]

Bits 12-16: 2 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[3]

Bits 18-22: 3 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[4]

Bits 24-28: 4 conversion in regular sequence.

Allowed values: 0x0-0x13

SQR2

ADC group regular sequencer ranks register 2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ[9]
rw
SQ[8]
rw
SQ[7]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ[7]
rw
SQ[6]
rw
SQ[5]
rw
Toggle fields

SQ[5]

Bits 0-4: 5 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[6]

Bits 6-10: 6 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[7]

Bits 12-16: 7 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[8]

Bits 18-22: 8 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[9]

Bits 24-28: 9 conversion in regular sequence.

Allowed values: 0x0-0x13

SQR3

ADC group regular sequencer ranks register 3

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ[14]
rw
SQ[13]
rw
SQ[12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ[12]
rw
SQ[11]
rw
SQ[10]
rw
Toggle fields

SQ[10]

Bits 0-4: 10 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[11]

Bits 6-10: 11 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[12]

Bits 12-16: 12 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[13]

Bits 18-22: 13 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[14]

Bits 24-28: 14 conversion in regular sequence.

Allowed values: 0x0-0x13

SQR4

ADC group regular sequencer ranks register 4

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ[16]
rw
SQ[15]
rw
Toggle fields

SQ[15]

Bits 0-4: 15 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[16]

Bits 6-10: 16 conversion in regular sequence.

Allowed values: 0x0-0x13

DR

ADC group regular conversion data register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
Toggle fields

RDATA

Bits 0-31: ADC group regular conversion data.

JSQR

ADC group injected sequencer register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JSQ[4]
rw
JSQ[3]
rw
JSQ[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JSQ[2]
rw
JSQ[1]
rw
JEXTEN
rw
JEXTSEL
rw
JL
rw
Toggle fields

JL

Bits 0-1: ADC group injected sequencer scan length.

Allowed values: 0x0-0x3

JEXTSEL

Bits 2-6: ADC group injected external trigger source.

Allowed values:
0: TIM1_TRGO: Timer 1 TRGO event
1: TIM1_CC4: Timer 1 CC4 event
2: TIM2_TRGO: Timer 2 TRGO event
3: TIM2_CC1: Timer 2 CC1 event
4: TIM3_CC4: Timer 3 CC4 event
5: TIM4_TRGO: Timer 4 TRGO event
6: EXTI15: EXTI line 15
7: TIM8_CC4: Timer 8 CC4 event
8: TIM1_TRGO2: Timer 1 TRGO2 event
9: TIM8_TRGO: Timer 8 TRGO event
10: TIM8_TRGO2: Timer 8 TRGO2 event
11: TIM3_CC3: Timer 3 CC3 event
12: TIM3_TRGO: Timer 3 TRGO event
13: TIM3_CC1: Timer 3 CC1 event
14: TIM6_TRGO: Timer 6 TRGO event
15: TIM15_TRGO: Timer 15 TRGO event
16: HRTIM1_ADCTRG2: HRTIM1_ADCTRG2 event
17: HRTIM1_ADCTRG4: HRTIM1_ADCTRG4 event
18: LPTIM1_OUT: LPTIM1_OUT event
19: LPTIM2_OUT: LPTIM2_OUT event
20: LPTIM3_OUT: LPTIM3_OUT event

JEXTEN

Bits 7-8: ADC group injected external trigger polarity.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

JSQ[1]

Bits 9-13: 1 conversion in injected sequence.

Allowed values: 0x0-0x13

JSQ[2]

Bits 15-19: 2 conversion in injected sequence.

Allowed values: 0x0-0x13

JSQ[3]

Bits 21-25: 3 conversion in injected sequence.

Allowed values: 0x0-0x13

JSQ[4]

Bits 27-31: 4 conversion in injected sequence.

Allowed values: 0x0-0x13

OFR[1]

ADC offset number 1 register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSATE
rw
OFFSET_CH
rw
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
Toggle fields

OFFSET

Bits 0-25: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0x3ffffff

OFFSET_CH

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

SSATE

Bit 31: Signed saturation enable.

Allowed values:
0: Disabled: Offset is subtracted maintaining data integrity and extending result size (9-bit and 17-bit signed format)
1: Enabled: Offset is subtracted and result is saturated to maintain result size

OFR[2]

ADC offset number 2 register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSATE
rw
OFFSET_CH
rw
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
Toggle fields

OFFSET

Bits 0-25: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0x3ffffff

OFFSET_CH

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

SSATE

Bit 31: Signed saturation enable.

Allowed values:
0: Disabled: Offset is subtracted maintaining data integrity and extending result size (9-bit and 17-bit signed format)
1: Enabled: Offset is subtracted and result is saturated to maintain result size

OFR[3]

ADC offset number 3 register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSATE
rw
OFFSET_CH
rw
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
Toggle fields

OFFSET

Bits 0-25: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0x3ffffff

OFFSET_CH

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

SSATE

Bit 31: Signed saturation enable.

Allowed values:
0: Disabled: Offset is subtracted maintaining data integrity and extending result size (9-bit and 17-bit signed format)
1: Enabled: Offset is subtracted and result is saturated to maintain result size

OFR[4]

ADC offset number 4 register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSATE
rw
OFFSET_CH
rw
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
Toggle fields

OFFSET

Bits 0-25: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0x3ffffff

OFFSET_CH

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

SSATE

Bit 31: Signed saturation enable.

Allowed values:
0: Disabled: Offset is subtracted maintaining data integrity and extending result size (9-bit and 17-bit signed format)
1: Enabled: Offset is subtracted and result is saturated to maintain result size

JDR[1]

ADC group injected sequencer rank 1 register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-31: Injected data.

JDR[2]

ADC group injected sequencer rank 2 register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-31: Injected data.

JDR[3]

ADC group injected sequencer rank 3 register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-31: Injected data.

JDR[4]

ADC group injected sequencer rank 4 register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-31: Injected data.

AWD2CR

ADC analog watchdog 2 configuration register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

Toggle fields

AWD2CH[0]

Bit 0: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[1]

Bit 1: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[2]

Bit 2: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[3]

Bit 3: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[4]

Bit 4: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[5]

Bit 5: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[6]

Bit 6: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[7]

Bit 7: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[8]

Bit 8: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[9]

Bit 9: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[10]

Bit 10: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[11]

Bit 11: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[12]

Bit 12: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[13]

Bit 13: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[14]

Bit 14: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[15]

Bit 15: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[16]

Bit 16: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[17]

Bit 17: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[18]

Bit 18: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[19]

Bit 19: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CR

ADC analog watchdog 3 configuration register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

Toggle fields

AWD3CH[0]

Bit 1: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[1]

Bit 2: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[2]

Bit 3: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[3]

Bit 4: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[4]

Bit 5: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[5]

Bit 6: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[6]

Bit 7: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[7]

Bit 8: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[8]

Bit 9: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[9]

Bit 10: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[10]

Bit 11: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[11]

Bit 12: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[12]

Bit 13: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[13]

Bit 14: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[14]

Bit 15: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[15]

Bit 16: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[16]

Bit 17: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[17]

Bit 18: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[18]

Bit 19: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[19]

Bit 20: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

LTR2

ADC watchdog lower threshold register 2

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LTR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LTR2
rw
Toggle fields

LTR2

Bits 0-25: Analog watchdog 2 lower threshold.

Allowed values: 0x0-0x3ffffff

HTR2

ADC watchdog higher threshold register 2

Offset: 0xb4, size: 32, reset: 0x03FFFFFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HTR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HTR2
rw
Toggle fields

HTR2

Bits 0-25: Analog watchdog 2 higher threshold.

Allowed values: 0x0-0x3ffffff

LTR3

ADC watchdog lower threshold register 3

Offset: 0xb8, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LTR3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LTR3
rw
Toggle fields

LTR3

Bits 0-25: Analog watchdog 3 lower threshold.

Allowed values: 0x0-0x3ffffff

HTR3

ADC watchdog higher threshold register 3

Offset: 0xbc, size: 32, reset: 0x03FFFFFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HTR3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HTR3
rw
Toggle fields

HTR3

Bits 0-25: Analog watchdog 3 higher threshold.

Allowed values: 0x0-0x3ffffff

DIFSEL

ADC channel differential or single-ended mode selection register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

Toggle fields

DIFSEL[0]

Bit 0: Differential mode for channel 0.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[1]

Bit 1: Differential mode for channel 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[2]

Bit 2: Differential mode for channel 2.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[3]

Bit 3: Differential mode for channel 3.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[4]

Bit 4: Differential mode for channel 4.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[5]

Bit 5: Differential mode for channel 5.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[6]

Bit 6: Differential mode for channel 6.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[7]

Bit 7: Differential mode for channel 7.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[8]

Bit 8: Differential mode for channel 8.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[9]

Bit 9: Differential mode for channel 9.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[10]

Bit 10: Differential mode for channel 10.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[11]

Bit 11: Differential mode for channel 11.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[12]

Bit 12: Differential mode for channel 12.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[13]

Bit 13: Differential mode for channel 13.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[14]

Bit 14: Differential mode for channel 14.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[15]

Bit 15: Differential mode for channel 15.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[16]

Bit 16: Differential mode for channel 16.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[17]

Bit 17: Differential mode for channel 17.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[18]

Bit 18: Differential mode for channel 18.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[19]

Bit 19: Differential mode for channel 19.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

CALFACT

ADC calibration factors register

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CALFACT_D
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALFACT_S
rw
Toggle fields

CALFACT_S

Bits 0-10: ADC calibration factor in single-ended mode.

Allowed values: 0x0-0x7ff

CALFACT_D

Bits 16-26: ADC calibration factor in differential mode.

Allowed values: 0x0-0x7ff

CALFACT2

ADC Calibration Factor register 2

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LINCALFACT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINCALFACT
rw
Toggle fields

LINCALFACT

Bits 0-29: Linearity Calibration Factor.

Allowed values: 0x0-0x3fffffff

ADC12_Common

0x40022300: Analog-to-Digital Converter

32/32 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CSR
0x8 CCR
0xc CDR
Toggle registers

CSR

ADC Common status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

22/22 fields covered.

Toggle fields

ADRDY_MST

Bit 0: Master ADC ready.

Allowed values:
0: NotReady: ADC is not ready to start conversion
1: Ready: ADC is ready to start conversion

EOSMP_MST

Bit 1: End of Sampling phase flag of the master ADC.

Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached

EOC_MST

Bit 2: End of regular conversion of the master ADC.

Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete

EOS_MST

Bit 3: End of regular sequence flag of the master ADC.

Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete

OVR_MST

Bit 4: Overrun flag of the master ADC.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

JEOC_MST

Bit 5: End of injected conversion flag of the master ADC.

Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete

JEOS_MST

Bit 6: End of injected sequence flag of the master ADC.

Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete

AWD1_MST

Bit 7: Analog watchdog 1 flag of the master ADC.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD2_MST

Bit 8: Analog watchdog 2 flag of the master ADC.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD3_MST

Bit 9: Analog watchdog 3 flag of the master ADC.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

JQOVF_MST

Bit 10: Injected Context Queue Overflow flag of the master ADC.

Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred

ADRDY_SLV

Bit 16: Slave ADC ready.

Allowed values:
0: NotReady: ADC is not ready to start conversion
1: Ready: ADC is ready to start conversion

EOSMP_SLV

Bit 17: End of Sampling phase flag of the slave ADC.

Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached

EOC_SLV

Bit 18: End of regular conversion of the slave ADC.

Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete

EOS_SLV

Bit 19: End of regular sequence flag of the slave ADC.

Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete

OVR_SLV

Bit 20: Overrun flag of the slave ADC.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

JEOC_SLV

Bit 21: End of injected conversion flag of the slave ADC.

Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete

JEOS_SLV

Bit 22: End of injected sequence flag of the slave ADC.

Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete

AWD1_SLV

Bit 23: Analog watchdog 1 flag of the slave ADC.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD2_SLV

Bit 24: Analog watchdog 2 flag of the slave ADC.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD3_SLV

Bit 25: Analog watchdog 3 flag of the slave ADC.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

JQOVF_SLV

Bit 26: Injected Context Queue Overflow flag of the slave ADC.

Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred

CCR

ADC common control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VBATEN
rw
VSENSEEN
rw
VREFEN
rw
PRESC
rw
CKMODE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAMDF
rw
DELAY
rw
DUAL
rw
Toggle fields

DUAL

Bits 0-4: Dual ADC mode selection.

Allowed values:
0: Independent: Independent mode
1: DualRJ: Dual, combined regular simultaneous + injected simultaneous mode
2: DualRA: Dual, combined regular simultaneous + alternate trigger mode
3: DualIJ: Dual, combined interleaved mode + injected simultaneous mode
5: DualJ: Dual, injected simultaneous mode only
6: DualR: Dual, regular simultaneous mode only
7: DualI: Dual, interleaved mode only
9: DualA: Dual, alternate trigger mode only

DELAY

Bits 8-11: Delay between 2 sampling phases.

Allowed values: 0x0-0xf

DAMDF

Bits 14-15: Dual ADC Mode Data Format.

Allowed values:
0: NoPack: Without data packing, CDR/CDR2 not used
2: Format32to10: CDR formatted for 32-bit down to 10-bit resolution
3: Format8: CDR formatted for 8-bit resolution

CKMODE

Bits 16-17: ADC clock mode.

Allowed values:
0: Asynchronous: Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock
1: SyncDiv1: Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck
2: SyncDiv2: Use AHB clock rcc_hclk3 divided by 2
3: SyncDiv4: Use AHB clock rcc_hclk3 divided by 4

PRESC

Bits 18-21: ADC prescaler.

Allowed values:
0: Div1: adc_ker_ck_input not divided
1: Div2: adc_ker_ck_input divided by 2
2: Div4: adc_ker_ck_input divided by 4
3: Div6: adc_ker_ck_input divided by 6
4: Div8: adc_ker_ck_input divided by 8
5: Div10: adc_ker_ck_input divided by 10
6: Div12: adc_ker_ck_input divided by 12
7: Div16: adc_ker_ck_input divided by 16
8: Div32: adc_ker_ck_input divided by 32
9: Div64: adc_ker_ck_input divided by 64
10: Div128: adc_ker_ck_input divided by 128
11: Div256: adc_ker_ck_input divided by 256

VREFEN

Bit 22: VREFINT enable.

Allowed values:
0: Disabled: V_REFINT channel disabled
1: Enabled: V_REFINT channel enabled

VSENSEEN

Bit 23: Temperature sensor enable.

Allowed values:
0: Disabled: The selected ADC channel disabled
1: Enabled: The selected ADC channel enabled

VBATEN

Bit 24: VBAT enable.

Allowed values:
0: Disabled: The selected ADC channel disabled
1: Enabled: The selected ADC channel enabled

CDR

ADC common regular data register for dual and triple modes

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA_SLV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA_MST
r
Toggle fields

RDATA_MST

Bits 0-15: Regular data of the master ADC.

RDATA_SLV

Bits 16-31: Regular data of the slave ADC.

ADC2

0x40022100: Analog to Digital Converter

199/199 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 IER
0x8 CR
0xc CFGR
0x10 CFGR2
0x14 SMPR1
0x18 SMPR2
0x1c PCSEL
0x20 LTR1
0x24 HTR1
0x30 SQR1
0x34 SQR2
0x38 SQR3
0x3c SQR4
0x40 DR
0x4c JSQR
0x60 OFR[1]
0x64 OFR[2]
0x68 OFR[3]
0x6c OFR[4]
0x80 JDR[1]
0x84 JDR[2]
0x88 JDR[3]
0x8c JDR[4]
0xa0 AWD2CR
0xa4 AWD3CR
0xb0 LTR2
0xb4 HTR2
0xb8 LTR3
0xbc HTR3
0xc0 DIFSEL
0xc4 CALFACT
0xc8 CALFACT2
Toggle registers

ISR

ADC interrupt and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVF
r/w1c
AWD[3]
r/w1c
AWD[2]
r/w1c
AWD[1]
r/w1c
JEOS
r/w1c
JEOC
r/w1c
OVR
r/w1c
EOS
r/w1c
EOC
r/w1c
EOSMP
r/w1c
ADRDY
r/w1c
Toggle fields

ADRDY

Bit 0: ADC ready flag.

Allowed values:
0: NotReady: ADC is not ready to start conversion
1: Ready: ADC is ready to start conversion

EOSMP

Bit 1: ADC group regular end of sampling flag.

Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached

EOC

Bit 2: ADC group regular end of unitary conversion flag.

Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete

EOS

Bit 3: ADC group regular end of sequence conversions flag.

Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete

OVR

Bit 4: ADC group regular overrun flag.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

JEOC

Bit 5: ADC group injected end of unitary conversion flag.

Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete

JEOS

Bit 6: ADC group injected end of sequence conversions flag.

Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete

AWD[1]

Bit 7: Analog watchdog 1 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD[2]

Bit 8: Analog watchdog 2 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD[3]

Bit 9: Analog watchdog 3 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

JQOVF

Bit 10: ADC group injected contexts queue overflow flag.

Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred

IER

ADC interrupt enable register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

Toggle fields

ADRDYIE

Bit 0: ADC ready interrupt.

Allowed values:
0: Disabled: ADC ready interrupt disabled
1: Enabled: ADC ready interrupt enabled

EOSMPIE

Bit 1: ADC group regular end of sampling interrupt.

Allowed values:
0: Disabled: End of regular conversion sampling phase interrupt disabled
1: Enabled: End of regular conversion sampling phase interrupt enabled

EOCIE

Bit 2: ADC group regular end of unitary conversion interrupt.

Allowed values:
0: Disabled: End of regular conversion interrupt disabled
1: Enabled: End of regular conversion interrupt enabled

EOSIE

Bit 3: ADC group regular end of sequence conversions interrupt.

Allowed values:
0: Disabled: End of regular sequence interrupt disabled
1: Enabled: End of regular sequence interrupt enabled

OVRIE

Bit 4: ADC group regular overrun interrupt.

Allowed values:
0: Disabled: Overrun interrupt disabled
1: Enabled: Overrun interrupt enabled

JEOCIE

Bit 5: ADC group injected end of unitary conversion interrupt.

Allowed values:
0: Disabled: End of injected conversion interrupt disabled
1: Enabled: End of injected conversion interrupt enabled

JEOSIE

Bit 6: ADC group injected end of sequence conversions interrupt.

Allowed values:
0: Disabled: End of injected sequence interrupt disabled
1: Enabled: End of injected sequence interrupt enabled

AWD[1]IE

Bit 7: Analog watchdog 1 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

AWD[2]IE

Bit 8: Analog watchdog 2 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

AWD[3]IE

Bit 9: Analog watchdog 3 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

JQOVFIE

Bit 10: ADC group injected contexts queue overflow interrupt.

Allowed values:
0: Disabled: Injected context queue overflow interrupt disabled
1: Enabled: Injected context queue overflow interrupt enabled

CR

ADC control register

Offset: 0x8, size: 32, reset: 0x20000000, access: read-write

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADCAL
r/w1s
ADCALDIF
rw
DEEPPWD
rw
ADVREGEN
rw
LINCALRDYW[6]
rw
LINCALRDYW[5]
rw
LINCALRDYW[4]
rw
LINCALRDYW[3]
rw
LINCALRDYW[2]
rw
LINCALRDYW[1]
rw
ADCALLIN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOST
rw
JADSTP
r/w1s
ADSTP
r/w1s
JADSTART
r/w1s
ADSTART
r/w1s
ADDIS
r/w1s
ADEN
r/w1s
Toggle fields

ADEN

Bit 0: ADC enable.

Allowed values:
0: Disabled: ADC disabled
1: Enabled: ADC enabled

ADDIS

Bit 1: ADC disable.

Allowed values:
0: NotDisabling: No disable command active
1: Disabling: ADC disabling

ADSTART

Bit 2: ADC group regular conversion start.

Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting

JADSTART

Bit 3: ADC group injected conversion start.

Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting

ADSTP

Bit 4: ADC group regular conversion stop.

Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion

JADSTP

Bit 5: ADC group injected conversion stop.

Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion

BOOST

Bits 8-9: Boost mode control.

Allowed values:
0: LT6_25: Boost mode used when ADC clock ≤ 6.25 MHz
1: LT12_5: Boost mode used when 6.25 MHz < ADC clock ≤ 12.5 MHz
2: LT25: Boost mode used when 12.5 MHz < ADC clock ≤ 25.0 MHz
3: LT50: Boost mode used when 25.0 MHz < ADC clock ≤ 50.0 MHz

ADCALLIN

Bit 16: Linearity calibration.

Allowed values:
0: NoLinearity: ADC calibration without linearaity calibration
1: Linearity: ADC calibration with linearaity calibration

LINCALRDYW[1]

Bit 22: Linearity calibration ready Word 1.

Allowed values:
0: Reset: LINCALFACT Word Read
1: Set: LINCALFACT Word Write

LINCALRDYW[2]

Bit 23: Linearity calibration ready Word 2.

Allowed values:
0: Reset: LINCALFACT Word Read
1: Set: LINCALFACT Word Write

LINCALRDYW[3]

Bit 24: Linearity calibration ready Word 3.

Allowed values:
0: Reset: LINCALFACT Word Read
1: Set: LINCALFACT Word Write

LINCALRDYW[4]

Bit 25: Linearity calibration ready Word 4.

Allowed values:
0: Reset: LINCALFACT Word Read
1: Set: LINCALFACT Word Write

LINCALRDYW[5]

Bit 26: Linearity calibration ready Word 5.

Allowed values:
0: Reset: LINCALFACT Word Read
1: Set: LINCALFACT Word Write

LINCALRDYW[6]

Bit 27: Linearity calibration ready Word 6.

Allowed values:
0: Reset: LINCALFACT Word Read
1: Set: LINCALFACT Word Write

ADVREGEN

Bit 28: ADC voltage regulator enable.

Allowed values:
0: Disabled: ADC voltage regulator disabled
1: Enabled: ADC voltage regulator enabled

DEEPPWD

Bit 29: ADC deep power down enable.

Allowed values:
0: PowerUp: ADC not in deep power down
1: PowerDown: ADC in deep power down

ADCALDIF

Bit 30: ADC differential mode for calibration.

Allowed values:
0: SingleEnded: Calibration for single-ended mode
1: Differential: Calibration for differential mode

ADCAL

Bit 31: ADC calibration.

Allowed values:
0: NotCalibrating: ADC calibration either not yet performed or completed
1: Calibrating: ADC calibration in progress

CFGR

ADC configuration register 1

Offset: 0xc, size: 32, reset: 0x80000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JQDIS
rw
AWD1CH
rw
JAUTO
rw
JAWD1EN
rw
AWD1EN
rw
AWD1SGL
rw
JQM
rw
JDISCEN
rw
DISCNUM
rw
DISCEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUTDLY
rw
CONT
rw
OVRMOD
rw
EXTEN
rw
EXTSEL
rw
RES
rw
DMNGT
rw
Toggle fields

DMNGT

Bits 0-1: ADC DMA transfer enable.

Allowed values:
0: DR: Store output data in DR only
1: DMA_OneShot: DMA One Shot Mode selected
2: DFSDM: DFSDM mode selected
3: DMA_Circular: DMA Circular Mode selected

RES

Bits 2-4: ADC data resolution.

Allowed values:
0: SixteenBit: 16-bit resolution
1: FourteenBit: 14-bit resolution in legacy mode (not optimized power consumption)
2: TwelveBit: 12-bit resolution in legacy mode (not optimized power consumption)
3: TenBit: 10-bit resolution
5: FourteenBitV: 14-bit resolution
6: TwelveBitV: 12-bit resolution
7: EightBit: 8-bit resolution

EXTSEL

Bits 5-9: ADC group regular external trigger source.

Allowed values:
0: TIM1_CC1: Timer 1 CC1 event
1: TIM1_CC2: Timer 1 CC2 event
2: TIM1_CC3: Timer 1 CC3 event
3: TIM2_CC2: Timer 2 CC2 event
4: TIM3_TRGO: Timer 3 TRGO event
5: TIM4_CC4: Timer 4 CC4 event
6: EXTI11: EXTI line 11
7: TIM8_TRGO: Timer 8 TRGO event
8: TIM8_TRGO2: Timer 8 TRGO2 event
9: TIM1_TRGO: Timer 1 TRGO event
10: TIM1_TRGO2: Timer 1 TRGO2 event
11: TIM2_TRGO: Timer 2 TRGO event
12: TIM4_TRGO: Timer 4 TRGO event
13: TIM6_TRGO: Timer 6 TRGO event
14: TIM15_TRGO: Timer 15 TRGO event
15: TIM3_CC4: Timer 3 CC4 event
16: HRTIM1_ADCTRG1: HRTIM1_ADCTRG1 event
17: HRTIM1_ADCTRG3: HRTIM1_ADCTRG3 event
18: LPTIM1_OUT: LPTIM1_OUT event
19: LPTIM2_OUT: LPTIM2_OUT event
20: LPTIM3_OUT: LPTIM3_OUT event

EXTEN

Bits 10-11: ADC group regular external trigger polarity.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

OVRMOD

Bit 12: ADC group regular overrun configuration.

Allowed values:
0: Preserve: Preserve DR register when an overrun is detected
1: Overwrite: Overwrite DR register when an overrun is detected

CONT

Bit 13: ADC group regular continuous conversion mode.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

AUTDLY

Bit 14: ADC low power auto wait.

Allowed values:
0: Off: Auto delayed conversion mode off
1: On: Auto delayed conversion mode on

DISCEN

Bit 16: ADC group regular sequencer discontinuous mode.

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

DISCNUM

Bits 17-19: ADC group regular sequencer discontinuous number of ranks.

Allowed values: 0x0-0x7

JDISCEN

Bit 20: ADC group injected sequencer discontinuous mode.

Allowed values:
0: Disabled: Discontinuous mode on injected channels disabled
1: Enabled: Discontinuous mode on injected channels enabled

JQM

Bit 21: ADC group injected contexts queue mode.

Allowed values:
0: Mode0: JSQR Mode 0: Queue maintains the last written configuration into JSQR
1: Mode1: JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence

AWD1SGL

Bit 22: ADC analog watchdog 1 monitoring a single channel or all channels.

Allowed values:
0: All: Analog watchdog 1 enabled on all channels
1: Single: Analog watchdog 1 enabled on single channel selected in AWD1CH

AWD1EN

Bit 23: ADC analog watchdog 1 enable on scope ADC group regular.

Allowed values:
0: Disabled: Analog watchdog 1 disabled on regular channels
1: Enabled: Analog watchdog 1 enabled on regular channels

JAWD1EN

Bit 24: ADC analog watchdog 1 enable on scope ADC group injected.

Allowed values:
0: Disabled: Analog watchdog 1 disabled on injected channels
1: Enabled: Analog watchdog 1 enabled on injected channels

JAUTO

Bit 25: ADC group injected automatic trigger mode.

Allowed values:
0: Disabled: Automatic injected group conversion disabled
1: Enabled: Automatic injected group conversion enabled

AWD1CH

Bits 26-30: ADC analog watchdog 1 monitored channel selection.

Allowed values: 0x0-0x13

JQDIS

Bit 31: ADC group injected contexts queue disable.

Allowed values:
0: Enabled: Injected Queue enabled
1: Disabled: Injected Queue disabled

CFGR2

ADC configuration register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LSHIFT
rw
OSVR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSHIFT[4]
rw
RSHIFT[3]
rw
RSHIFT[2]
rw
RSHIFT[1]
rw
ROVSM
rw
TROVS
rw
OVSS
rw
JOVSE
rw
ROVSE
rw
Toggle fields

ROVSE

Bit 0: ADC oversampler enable on scope ADC group regular.

Allowed values:
0: Disabled: Regular oversampling disabled
1: Enabled: Regular oversampling enabled

JOVSE

Bit 1: ADC oversampler enable on scope ADC group injected.

Allowed values:
0: Disabled: Injected oversampling disabled
1: Enabled: Injected oversampling enabled

OVSS

Bits 5-8: ADC oversampling shift.

Allowed values: 0x0-0xb

TROVS

Bit 9: ADC oversampling discontinuous mode (triggered mode) for ADC group regular.

Allowed values:
0: Automatic: All oversampled conversions for a channel are run following a trigger
1: Triggered: Each oversampled conversion for a channel needs a new trigger

ROVSM

Bit 10: Regular Oversampling mode.

Allowed values:
0: Continued: Oversampling is temporary stopped and continued after injection sequence
1: Resumed: Oversampling is aborted and resumed from start after injection sequence

RSHIFT[1]

Bit 11: Right-shift data after Offset 1 correction.

Allowed values:
0: Disabled: Right-shifting disabled
1: Enabled: Data is right-shifted 1-bit

RSHIFT[2]

Bit 12: Right-shift data after Offset 2 correction.

Allowed values:
0: Disabled: Right-shifting disabled
1: Enabled: Data is right-shifted 1-bit

RSHIFT[3]

Bit 13: Right-shift data after Offset 3 correction.

Allowed values:
0: Disabled: Right-shifting disabled
1: Enabled: Data is right-shifted 1-bit

RSHIFT[4]

Bit 14: Right-shift data after Offset 4 correction.

Allowed values:
0: Disabled: Right-shifting disabled
1: Enabled: Data is right-shifted 1-bit

OSVR

Bits 16-25: Oversampling ratio.

Allowed values: 0x0-0x3ff

LSHIFT

Bits 28-31: Left shift factor.

Allowed values: 0x0-0xf

SMPR1

ADC sampling time register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP[9]
rw
SMP[8]
rw
SMP[7]
rw
SMP[6]
rw
SMP[5]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP[5]
rw
SMP[4]
rw
SMP[3]
rw
SMP[2]
rw
SMP[1]
rw
SMP[0]
rw
Toggle fields

SMP[0]

Bits 0-2: Channel 0 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[1]

Bits 3-5: Channel 1 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[2]

Bits 6-8: Channel 2 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[3]

Bits 9-11: Channel 3 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[4]

Bits 12-14: Channel 4 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[5]

Bits 15-17: Channel 5 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[6]

Bits 18-20: Channel 6 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[7]

Bits 21-23: Channel 7 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[8]

Bits 24-26: Channel 8 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[9]

Bits 27-29: Channel 9 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMPR2

ADC sampling time register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP[19]
rw
SMP[18]
rw
SMP[17]
rw
SMP[16]
rw
SMP[15]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP[15]
rw
SMP[14]
rw
SMP[13]
rw
SMP[12]
rw
SMP[11]
rw
SMP[10]
rw
Toggle fields

SMP[10]

Bits 0-2: Channel 10 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[11]

Bits 3-5: Channel 11 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[12]

Bits 6-8: Channel 12 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[13]

Bits 9-11: Channel 13 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[14]

Bits 12-14: Channel 14 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[15]

Bits 15-17: Channel 15 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[16]

Bits 18-20: Channel 16 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[17]

Bits 21-23: Channel 17 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[18]

Bits 24-26: Channel 18 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

SMP[19]

Bits 27-29: Channel 19 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles2_5: 2.5 ADC clock cycles
2: Cycles8_5: 8.5 ADC clock cycles
3: Cycles16_5: 16.5 ADC clock cycles
4: Cycles32_5: 32.5 ADC clock cycles
5: Cycles64_5: 64.5 ADC clock cycles
6: Cycles387_5: 387.5 ADC clock cycles
7: Cycles810_5: 810.5 ADC clock cycles

PCSEL

ADC pre channel selection register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCSEL
rw
Toggle fields

PCSEL

Bits 0-19: Channel x (VINP[i]) pre selection.

Allowed values:
0: NotPreselected: Input channel x is not pre-selected
1: Preselected: Pre-select input channel x

LTR1

ADC analog watchdog 1 threshold register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LTR1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LTR1
rw
Toggle fields

LTR1

Bits 0-25: ADC analog watchdog 1 threshold low.

Allowed values: 0x0-0x3ffffff

HTR1

ADC analog watchdog 2 threshold register

Offset: 0x24, size: 32, reset: 0x03FFFFFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HTR1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HTR1
rw
Toggle fields

HTR1

Bits 0-25: ADC analog watchdog 2 threshold low.

Allowed values: 0x0-0x3ffffff

SQR1

ADC group regular sequencer ranks register 1

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ[4]
rw
SQ[3]
rw
SQ[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ[2]
rw
SQ[1]
rw
L
rw
Toggle fields

L

Bits 0-3: L3.

Allowed values: 0x0-0xf

SQ[1]

Bits 6-10: 1 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[2]

Bits 12-16: 2 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[3]

Bits 18-22: 3 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[4]

Bits 24-28: 4 conversion in regular sequence.

Allowed values: 0x0-0x13

SQR2

ADC group regular sequencer ranks register 2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ[9]
rw
SQ[8]
rw
SQ[7]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ[7]
rw
SQ[6]
rw
SQ[5]
rw
Toggle fields

SQ[5]

Bits 0-4: 5 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[6]

Bits 6-10: 6 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[7]

Bits 12-16: 7 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[8]

Bits 18-22: 8 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[9]

Bits 24-28: 9 conversion in regular sequence.

Allowed values: 0x0-0x13

SQR3

ADC group regular sequencer ranks register 3

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ[14]
rw
SQ[13]
rw
SQ[12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ[12]
rw
SQ[11]
rw
SQ[10]
rw
Toggle fields

SQ[10]

Bits 0-4: 10 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[11]

Bits 6-10: 11 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[12]

Bits 12-16: 12 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[13]

Bits 18-22: 13 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[14]

Bits 24-28: 14 conversion in regular sequence.

Allowed values: 0x0-0x13

SQR4

ADC group regular sequencer ranks register 4

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ[16]
rw
SQ[15]
rw
Toggle fields

SQ[15]

Bits 0-4: 15 conversion in regular sequence.

Allowed values: 0x0-0x13

SQ[16]

Bits 6-10: 16 conversion in regular sequence.

Allowed values: 0x0-0x13

DR

ADC group regular conversion data register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
Toggle fields

RDATA

Bits 0-31: ADC group regular conversion data.

JSQR

ADC group injected sequencer register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JSQ[4]
rw
JSQ[3]
rw
JSQ[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JSQ[2]
rw
JSQ[1]
rw
JEXTEN
rw
JEXTSEL
rw
JL
rw
Toggle fields

JL

Bits 0-1: ADC group injected sequencer scan length.

Allowed values: 0x0-0x3

JEXTSEL

Bits 2-6: ADC group injected external trigger source.

Allowed values:
0: TIM1_TRGO: Timer 1 TRGO event
1: TIM1_CC4: Timer 1 CC4 event
2: TIM2_TRGO: Timer 2 TRGO event
3: TIM2_CC1: Timer 2 CC1 event
4: TIM3_CC4: Timer 3 CC4 event
5: TIM4_TRGO: Timer 4 TRGO event
6: EXTI15: EXTI line 15
7: TIM8_CC4: Timer 8 CC4 event
8: TIM1_TRGO2: Timer 1 TRGO2 event
9: TIM8_TRGO: Timer 8 TRGO event
10: TIM8_TRGO2: Timer 8 TRGO2 event
11: TIM3_CC3: Timer 3 CC3 event
12: TIM3_TRGO: Timer 3 TRGO event
13: TIM3_CC1: Timer 3 CC1 event
14: TIM6_TRGO: Timer 6 TRGO event
15: TIM15_TRGO: Timer 15 TRGO event
16: HRTIM1_ADCTRG2: HRTIM1_ADCTRG2 event
17: HRTIM1_ADCTRG4: HRTIM1_ADCTRG4 event
18: LPTIM1_OUT: LPTIM1_OUT event
19: LPTIM2_OUT: LPTIM2_OUT event
20: LPTIM3_OUT: LPTIM3_OUT event

JEXTEN

Bits 7-8: ADC group injected external trigger polarity.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

JSQ[1]

Bits 9-13: 1 conversion in injected sequence.

Allowed values: 0x0-0x13

JSQ[2]

Bits 15-19: 2 conversion in injected sequence.

Allowed values: 0x0-0x13

JSQ[3]

Bits 21-25: 3 conversion in injected sequence.

Allowed values: 0x0-0x13

JSQ[4]

Bits 27-31: 4 conversion in injected sequence.

Allowed values: 0x0-0x13

OFR[1]

ADC offset number 1 register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSATE
rw
OFFSET_CH
rw
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
Toggle fields

OFFSET

Bits 0-25: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0x3ffffff

OFFSET_CH

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

SSATE

Bit 31: Signed saturation enable.

Allowed values:
0: Disabled: Offset is subtracted maintaining data integrity and extending result size (9-bit and 17-bit signed format)
1: Enabled: Offset is subtracted and result is saturated to maintain result size

OFR[2]

ADC offset number 2 register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSATE
rw
OFFSET_CH
rw
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
Toggle fields

OFFSET

Bits 0-25: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0x3ffffff

OFFSET_CH

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

SSATE

Bit 31: Signed saturation enable.

Allowed values:
0: Disabled: Offset is subtracted maintaining data integrity and extending result size (9-bit and 17-bit signed format)
1: Enabled: Offset is subtracted and result is saturated to maintain result size

OFR[3]

ADC offset number 3 register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSATE
rw
OFFSET_CH
rw
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
Toggle fields

OFFSET

Bits 0-25: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0x3ffffff

OFFSET_CH

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

SSATE

Bit 31: Signed saturation enable.

Allowed values:
0: Disabled: Offset is subtracted maintaining data integrity and extending result size (9-bit and 17-bit signed format)
1: Enabled: Offset is subtracted and result is saturated to maintain result size

OFR[4]

ADC offset number 4 register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSATE
rw
OFFSET_CH
rw
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
Toggle fields

OFFSET

Bits 0-25: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0x3ffffff

OFFSET_CH

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

SSATE

Bit 31: Signed saturation enable.

Allowed values:
0: Disabled: Offset is subtracted maintaining data integrity and extending result size (9-bit and 17-bit signed format)
1: Enabled: Offset is subtracted and result is saturated to maintain result size

JDR[1]

ADC group injected sequencer rank 1 register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-31: Injected data.

JDR[2]

ADC group injected sequencer rank 2 register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-31: Injected data.

JDR[3]

ADC group injected sequencer rank 3 register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-31: Injected data.

JDR[4]

ADC group injected sequencer rank 4 register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-31: Injected data.

AWD2CR

ADC analog watchdog 2 configuration register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

Toggle fields

AWD2CH[0]

Bit 0: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[1]

Bit 1: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[2]

Bit 2: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[3]

Bit 3: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[4]

Bit 4: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[5]

Bit 5: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[6]

Bit 6: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[7]

Bit 7: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[8]

Bit 8: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[9]

Bit 9: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[10]

Bit 10: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[11]

Bit 11: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[12]

Bit 12: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[13]

Bit 13: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[14]

Bit 14: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[15]

Bit 15: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[16]

Bit 16: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[17]

Bit 17: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[18]

Bit 18: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[19]

Bit 19: ADC analog watchdog 2 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CR

ADC analog watchdog 3 configuration register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

Toggle fields

AWD3CH[0]

Bit 1: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[1]

Bit 2: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[2]

Bit 3: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[3]

Bit 4: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[4]

Bit 5: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[5]

Bit 6: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[6]

Bit 7: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[7]

Bit 8: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[8]

Bit 9: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[9]

Bit 10: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[10]

Bit 11: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[11]

Bit 12: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[12]

Bit 13: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[13]

Bit 14: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[14]

Bit 15: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[15]

Bit 16: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[16]

Bit 17: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[17]

Bit 18: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[18]

Bit 19: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[19]

Bit 20: ADC analog watchdog 3 monitored channel selection.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

LTR2

ADC watchdog lower threshold register 2

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LTR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LTR2
rw
Toggle fields

LTR2

Bits 0-25: Analog watchdog 2 lower threshold.

Allowed values: 0x0-0x3ffffff

HTR2

ADC watchdog higher threshold register 2

Offset: 0xb4, size: 32, reset: 0x03FFFFFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HTR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HTR2
rw
Toggle fields

HTR2

Bits 0-25: Analog watchdog 2 higher threshold.

Allowed values: 0x0-0x3ffffff

LTR3

ADC watchdog lower threshold register 3

Offset: 0xb8, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LTR3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LTR3
rw
Toggle fields

LTR3

Bits 0-25: Analog watchdog 3 lower threshold.

Allowed values: 0x0-0x3ffffff

HTR3

ADC watchdog higher threshold register 3

Offset: 0xbc, size: 32, reset: 0x03FFFFFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HTR3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HTR3
rw
Toggle fields

HTR3

Bits 0-25: Analog watchdog 3 higher threshold.

Allowed values: 0x0-0x3ffffff

DIFSEL

ADC channel differential or single-ended mode selection register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

Toggle fields

DIFSEL[0]

Bit 0: Differential mode for channel 0.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[1]

Bit 1: Differential mode for channel 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[2]

Bit 2: Differential mode for channel 2.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[3]

Bit 3: Differential mode for channel 3.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[4]

Bit 4: Differential mode for channel 4.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[5]

Bit 5: Differential mode for channel 5.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[6]

Bit 6: Differential mode for channel 6.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[7]

Bit 7: Differential mode for channel 7.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[8]

Bit 8: Differential mode for channel 8.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[9]

Bit 9: Differential mode for channel 9.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[10]

Bit 10: Differential mode for channel 10.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[11]

Bit 11: Differential mode for channel 11.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[12]

Bit 12: Differential mode for channel 12.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[13]

Bit 13: Differential mode for channel 13.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[14]

Bit 14: Differential mode for channel 14.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[15]

Bit 15: Differential mode for channel 15.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[16]

Bit 16: Differential mode for channel 16.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[17]

Bit 17: Differential mode for channel 17.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[18]

Bit 18: Differential mode for channel 18.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[19]

Bit 19: Differential mode for channel 19.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

CALFACT

ADC calibration factors register

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CALFACT_D
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALFACT_S
rw
Toggle fields

CALFACT_S

Bits 0-10: ADC calibration factor in single-ended mode.

Allowed values: 0x0-0x7ff

CALFACT_D

Bits 16-26: ADC calibration factor in differential mode.

Allowed values: 0x0-0x7ff

CALFACT2

ADC Calibration Factor register 2

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LINCALFACT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINCALFACT
rw
Toggle fields

LINCALFACT

Bits 0-29: Linearity Calibration Factor.

Allowed values: 0x0-0x3fffffff

AXI

0x51000000: AXI interconnect registers

39/70 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x1fd0 PERIPH_ID_4
0x1fe0 PERIPH_ID_0
0x1fe4 PERIPH_ID_1
0x1fe8 PERIPH_ID_2
0x1fec PERIPH_ID_3
0x1ff0 COMP_ID_0
0x1ff4 COMP_ID_1
0x1ff8 COMP_ID_2
0x1ffc COMP_ID_3
0x2008 TARG1_FN_MOD_ISS_BM
0x2024 TARG1_FN_MOD2
0x202c TARG1_FN_MOD_LB
0x2108 TARG1_FN_MOD
0x3008 TARG2_FN_MOD_ISS_BM
0x3024 TARG2_FN_MOD2
0x302c TARG2_FN_MOD_LB
0x3108 TARG2_FN_MOD
0x4008 TARG3_FN_MOD_ISS_BM
0x5008 TARG4_FN_MOD_ISS_BM
0x6008 TARG5_FN_MOD_ISS_BM
0x7008 TARG6_FN_MOD_ISS_BM
0x800c TARG7_FN_MOD_ISS_BM
0x8024 TARG7_FN_MOD2
0x8108 TARG7_FN_MOD
0x42024 INI1_FN_MOD2
0x42028 INI1_FN_MOD_AHB
0x42100 INI1_READ_QOS
0x42104 INI1_WRITE_QOS
0x42108 INI1_FN_MOD
0x43100 INI2_READ_QOS
0x43104 INI2_WRITE_QOS
0x43108 INI2_FN_MOD
0x44024 INI3_FN_MOD2
0x44028 INI3_FN_MOD_AHB
0x44100 INI3_READ_QOS
0x44104 INI3_WRITE_QOS
0x44108 INI3_FN_MOD
0x45100 INI4_READ_QOS
0x45104 INI4_WRITE_QOS
0x45108 INI4_FN_MOD
0x46100 INI5_READ_QOS
0x46104 INI5_WRITE_QOS
0x46108 INI5_FN_MOD
0x47100 INI6_READ_QOS
0x47104 INI6_WRITE_QOS
0x47108 INI6_FN_MOD
Toggle registers

PERIPH_ID_4

AXI interconnect - peripheral ID4 register

Offset: 0x1fd0, size: 32, reset: 0x00000004, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KCOUNT4
r
JEP106CON
r
Toggle fields

JEP106CON

Bits 0-3: JEP106 continuation code.

KCOUNT4

Bits 4-7: Register file size.

PERIPH_ID_0

AXI interconnect - peripheral ID0 register

Offset: 0x1fe0, size: 32, reset: 0x00000004, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PARTNUM
r
Toggle fields

PARTNUM

Bits 0-7: Peripheral part number bits 0 to 7.

PERIPH_ID_1

AXI interconnect - peripheral ID1 register

Offset: 0x1fe4, size: 32, reset: 0x00000004, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEP106I
r
PARTNUM
r
Toggle fields

PARTNUM

Bits 0-3: Peripheral part number bits 8 to 11.

JEP106I

Bits 4-7: JEP106 identity bits 0 to 3.

PERIPH_ID_2

AXI interconnect - peripheral ID2 register

Offset: 0x1fe8, size: 32, reset: 0x00000004, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REVISION
r
JEDEC
r
JEP106ID
r
Toggle fields

JEP106ID

Bits 0-2: JEP106 Identity bits 4 to 6.

JEDEC

Bit 3: JEP106 code flag.

REVISION

Bits 4-7: Peripheral revision number.

PERIPH_ID_3

AXI interconnect - peripheral ID3 register

Offset: 0x1fec, size: 32, reset: 0x00000004, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REV_AND
r
CUST_MOD_NUM
r
Toggle fields

CUST_MOD_NUM

Bits 0-3: Customer modification.

REV_AND

Bits 4-7: Customer version.

COMP_ID_0

AXI interconnect - component ID0 register

Offset: 0x1ff0, size: 32, reset: 0x00000004, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PREAMBLE
r
Toggle fields

PREAMBLE

Bits 0-7: Preamble bits 0 to 7.

COMP_ID_1

AXI interconnect - component ID1 register

Offset: 0x1ff4, size: 32, reset: 0x00000004, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLASS
r
PREAMBLE
r
Toggle fields

PREAMBLE

Bits 0-3: Preamble bits 8 to 11.

CLASS

Bits 4-7: Component class.

COMP_ID_2

AXI interconnect - component ID2 register

Offset: 0x1ff8, size: 32, reset: 0x00000004, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PREAMBLE
r
Toggle fields

PREAMBLE

Bits 0-7: Preamble bits 12 to 19.

COMP_ID_3

AXI interconnect - component ID3 register

Offset: 0x1ffc, size: 32, reset: 0x00000004, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PREAMBLE
r
Toggle fields

PREAMBLE

Bits 0-7: Preamble bits 20 to 27.

TARG1_FN_MOD_ISS_BM

AXI interconnect - TARG x bus matrix issuing functionality register

Offset: 0x2008, size: 32, reset: 0x00000004, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRITE_ISS_OVERRIDE
rw
READ_ISS_OVERRIDE
rw
Toggle fields

READ_ISS_OVERRIDE

Bit 0: READ_ISS_OVERRIDE.

WRITE_ISS_OVERRIDE

Bit 1: Switch matrix write issuing override for target.

TARG1_FN_MOD2

AXI interconnect - TARG x bus matrix functionality 2 register

Offset: 0x2024, size: 32, reset: 0x00000004, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BYPASS_MERGE
rw
Toggle fields

BYPASS_MERGE

Bit 0: Disable packing of beats to match the output data width.

TARG1_FN_MOD_LB

AXI interconnect - TARG x long burst functionality modification

Offset: 0x202c, size: 32, reset: 0x00000004, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FN_MOD_LB
rw
Toggle fields

FN_MOD_LB

Bit 0: Controls burst breaking of long bursts.

TARG1_FN_MOD

AXI interconnect - TARG x long burst functionality modification

Offset: 0x2108, size: 32, reset: 0x00000004, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRITE_ISS_OVERRIDE
rw
READ_ISS_OVERRIDE
rw
Toggle fields

READ_ISS_OVERRIDE

Bit 0: Override AMIB read issuing capability.

WRITE_ISS_OVERRIDE

Bit 1: Override AMIB write issuing capability.

TARG2_FN_MOD_ISS_BM

AXI interconnect - TARG x bus matrix issuing functionality register

Offset: 0x3008, size: 32, reset: 0x00000004, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRITE_ISS_OVERRIDE
rw
READ_ISS_OVERRIDE
rw
Toggle fields

READ_ISS_OVERRIDE

Bit 0: READ_ISS_OVERRIDE.

WRITE_ISS_OVERRIDE

Bit 1: Switch matrix write issuing override for target.

TARG2_FN_MOD2

AXI interconnect - TARG x bus matrix functionality 2 register

Offset: 0x3024, size: 32, reset: 0x00000004, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BYPASS_MERGE
rw
Toggle fields

BYPASS_MERGE

Bit 0: Disable packing of beats to match the output data width.

TARG2_FN_MOD_LB

AXI interconnect - TARG x long burst functionality modification

Offset: 0x302c, size: 32, reset: 0x00000004, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FN_MOD_LB
rw
Toggle fields

FN_MOD_LB

Bit 0: Controls burst breaking of long bursts.

TARG2_FN_MOD

AXI interconnect - TARG x long burst functionality modification

Offset: 0x3108, size: 32, reset: 0x00000004, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRITE_ISS_OVERRIDE
rw
READ_ISS_OVERRIDE
rw
Toggle fields

READ_ISS_OVERRIDE

Bit 0: Override AMIB read issuing capability.

WRITE_ISS_OVERRIDE

Bit 1: Override AMIB write issuing capability.

TARG3_FN_MOD_ISS_BM

AXI interconnect - TARG x bus matrix issuing functionality register

Offset: 0x4008, size: 32, reset: 0x00000004, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRITE_ISS_OVERRIDE
rw
READ_ISS_OVERRIDE
rw
Toggle fields

READ_ISS_OVERRIDE

Bit 0: READ_ISS_OVERRIDE.

WRITE_ISS_OVERRIDE

Bit 1: Switch matrix write issuing override for target.

TARG4_FN_MOD_ISS_BM

AXI interconnect - TARG x bus matrix issuing functionality register

Offset: 0x5008, size: 32, reset: 0x00000004, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRITE_ISS_OVERRIDE
rw
READ_ISS_OVERRIDE
rw
Toggle fields

READ_ISS_OVERRIDE

Bit 0: READ_ISS_OVERRIDE.

WRITE_ISS_OVERRIDE

Bit 1: Switch matrix write issuing override for target.

TARG5_FN_MOD_ISS_BM

AXI interconnect - TARG x bus matrix issuing functionality register

Offset: 0x6008, size: 32, reset: 0x00000004, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRITE_ISS_OVERRIDE
rw
READ_ISS_OVERRIDE
rw
Toggle fields

READ_ISS_OVERRIDE

Bit 0: READ_ISS_OVERRIDE.

WRITE_ISS_OVERRIDE

Bit 1: Switch matrix write issuing override for target.

TARG6_FN_MOD_ISS_BM

AXI interconnect - TARG x bus matrix issuing functionality register

Offset: 0x7008, size: 32, reset: 0x00000004, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRITE_ISS_OVERRIDE
rw
READ_ISS_OVERRIDE
rw
Toggle fields

READ_ISS_OVERRIDE

Bit 0: READ_ISS_OVERRIDE.

WRITE_ISS_OVERRIDE

Bit 1: Switch matrix write issuing override for target.

TARG7_FN_MOD_ISS_BM

AXI interconnect - TARG x bus matrix issuing functionality register

Offset: 0x800c, size: 32, reset: 0x00000004, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRITE_ISS_OVERRIDE
rw
READ_ISS_OVERRIDE
rw
Toggle fields

READ_ISS_OVERRIDE

Bit 0: READ_ISS_OVERRIDE.

WRITE_ISS_OVERRIDE

Bit 1: Switch matrix write issuing override for target.

TARG7_FN_MOD2

AXI interconnect - TARG x bus matrix functionality 2 register

Offset: 0x8024, size: 32, reset: 0x00000004, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BYPASS_MERGE
rw
Toggle fields

BYPASS_MERGE

Bit 0: Disable packing of beats to match the output data width.

TARG7_FN_MOD

AXI interconnect - TARG x long burst functionality modification

Offset: 0x8108, size: 32, reset: 0x00000004, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRITE_ISS_OVERRIDE
rw
READ_ISS_OVERRIDE
rw
Toggle fields

READ_ISS_OVERRIDE

Bit 0: Override AMIB read issuing capability.

WRITE_ISS_OVERRIDE

Bit 1: Override AMIB write issuing capability.

INI1_FN_MOD2

AXI interconnect - INI x functionality modification 2 register

Offset: 0x42024, size: 32, reset: 0x00000004, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BYPASS_MERGE
rw
Toggle fields

BYPASS_MERGE

Bit 0: Disables alteration of transactions by the up-sizer unless required by the protocol.

INI1_FN_MOD_AHB

AXI interconnect - INI x AHB functionality modification register

Offset: 0x42028, size: 32, reset: 0x00000004, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WR_INC_OVERRIDE
rw
RD_INC_OVERRIDE
rw
Toggle fields

RD_INC_OVERRIDE

Bit 0: Converts all AHB-Lite write transactions to a series of single beat AXI.

WR_INC_OVERRIDE

Bit 1: Converts all AHB-Lite read transactions to a series of single beat AXI.

INI1_READ_QOS

AXI interconnect - INI x read QoS register

Offset: 0x42100, size: 32, reset: 0x00000004, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AR_QOS
rw
Toggle fields

AR_QOS

Bits 0-3: Read channel QoS setting.

Allowed values: 0x0-0xf

INI1_WRITE_QOS

AXI interconnect - INI x write QoS register

Offset: 0x42104, size: 32, reset: 0x00000004, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AW_QOS
rw
Toggle fields

AW_QOS

Bits 0-3: Write channel QoS setting.

Allowed values: 0x0-0xf

INI1_FN_MOD

AXI interconnect - INI x issuing functionality modification register

Offset: 0x42108, size: 32, reset: 0x00000004, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRITE_ISS_OVERRIDE
rw
READ_ISS_OVERRIDE
rw
Toggle fields

READ_ISS_OVERRIDE

Bit 0: Override ASIB read issuing capability.

Allowed values:
0: Normal: Normal ASIB read issuing capability
1: Force1: Force ASIB read issuing capability to 1

WRITE_ISS_OVERRIDE

Bit 1: Override ASIB write issuing capability.

Allowed values:
0: Normal: Normal ASIB write issuing capability
1: Force1: Force ASIB write issuing capability to 1

INI2_READ_QOS

AXI interconnect - INI x read QoS register

Offset: 0x43100, size: 32, reset: 0x00000004, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AR_QOS
rw
Toggle fields

AR_QOS

Bits 0-3: Read channel QoS setting.

Allowed values: 0x0-0xf

INI2_WRITE_QOS

AXI interconnect - INI x write QoS register

Offset: 0x43104, size: 32, reset: 0x00000004, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AW_QOS
rw
Toggle fields

AW_QOS

Bits 0-3: Write channel QoS setting.

Allowed values: 0x0-0xf

INI2_FN_MOD

AXI interconnect - INI x issuing functionality modification register

Offset: 0x43108, size: 32, reset: 0x00000004, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRITE_ISS_OVERRIDE
rw
READ_ISS_OVERRIDE
rw
Toggle fields

READ_ISS_OVERRIDE

Bit 0: Override ASIB read issuing capability.

Allowed values:
0: Normal: Normal ASIB read issuing capability
1: Force1: Force ASIB read issuing capability to 1

WRITE_ISS_OVERRIDE

Bit 1: Override ASIB write issuing capability.

Allowed values:
0: Normal: Normal ASIB write issuing capability
1: Force1: Force ASIB write issuing capability to 1

INI3_FN_MOD2

AXI interconnect - INI x functionality modification 2 register

Offset: 0x44024, size: 32, reset: 0x00000004, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BYPASS_MERGE
rw
Toggle fields

BYPASS_MERGE

Bit 0: Disables alteration of transactions by the up-sizer unless required by the protocol.

INI3_FN_MOD_AHB

AXI interconnect - INI x AHB functionality modification register

Offset: 0x44028, size: 32, reset: 0x00000004, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WR_INC_OVERRIDE
rw
RD_INC_OVERRIDE
rw
Toggle fields

RD_INC_OVERRIDE

Bit 0: Converts all AHB-Lite write transactions to a series of single beat AXI.

WR_INC_OVERRIDE

Bit 1: Converts all AHB-Lite read transactions to a series of single beat AXI.

INI3_READ_QOS

AXI interconnect - INI x read QoS register

Offset: 0x44100, size: 32, reset: 0x00000004, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AR_QOS
rw
Toggle fields

AR_QOS

Bits 0-3: Read channel QoS setting.

Allowed values: 0x0-0xf

INI3_WRITE_QOS

AXI interconnect - INI x write QoS register

Offset: 0x44104, size: 32, reset: 0x00000004, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AW_QOS
rw
Toggle fields

AW_QOS

Bits 0-3: Write channel QoS setting.

Allowed values: 0x0-0xf

INI3_FN_MOD

AXI interconnect - INI x issuing functionality modification register

Offset: 0x44108, size: 32, reset: 0x00000004, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRITE_ISS_OVERRIDE
rw
READ_ISS_OVERRIDE
rw
Toggle fields

READ_ISS_OVERRIDE

Bit 0: Override ASIB read issuing capability.

Allowed values:
0: Normal: Normal ASIB read issuing capability
1: Force1: Force ASIB read issuing capability to 1

WRITE_ISS_OVERRIDE

Bit 1: Override ASIB write issuing capability.

Allowed values:
0: Normal: Normal ASIB write issuing capability
1: Force1: Force ASIB write issuing capability to 1

INI4_READ_QOS

AXI interconnect - INI x read QoS register

Offset: 0x45100, size: 32, reset: 0x00000004, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AR_QOS
rw
Toggle fields

AR_QOS

Bits 0-3: Read channel QoS setting.

Allowed values: 0x0-0xf

INI4_WRITE_QOS

AXI interconnect - INI x write QoS register

Offset: 0x45104, size: 32, reset: 0x00000004, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AW_QOS
rw
Toggle fields

AW_QOS

Bits 0-3: Write channel QoS setting.

Allowed values: 0x0-0xf

INI4_FN_MOD

AXI interconnect - INI x issuing functionality modification register

Offset: 0x45108, size: 32, reset: 0x00000004, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRITE_ISS_OVERRIDE
rw
READ_ISS_OVERRIDE
rw
Toggle fields

READ_ISS_OVERRIDE

Bit 0: Override ASIB read issuing capability.

Allowed values:
0: Normal: Normal ASIB read issuing capability
1: Force1: Force ASIB read issuing capability to 1

WRITE_ISS_OVERRIDE

Bit 1: Override ASIB write issuing capability.

Allowed values:
0: Normal: Normal ASIB write issuing capability
1: Force1: Force ASIB write issuing capability to 1

INI5_READ_QOS

AXI interconnect - INI x read QoS register

Offset: 0x46100, size: 32, reset: 0x00000004, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AR_QOS
rw
Toggle fields

AR_QOS

Bits 0-3: Read channel QoS setting.

Allowed values: 0x0-0xf

INI5_WRITE_QOS

AXI interconnect - INI x write QoS register

Offset: 0x46104, size: 32, reset: 0x00000004, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AW_QOS
rw
Toggle fields

AW_QOS

Bits 0-3: Write channel QoS setting.

Allowed values: 0x0-0xf

INI5_FN_MOD

AXI interconnect - INI x issuing functionality modification register

Offset: 0x46108, size: 32, reset: 0x00000004, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRITE_ISS_OVERRIDE
rw
READ_ISS_OVERRIDE
rw
Toggle fields

READ_ISS_OVERRIDE

Bit 0: Override ASIB read issuing capability.

Allowed values:
0: Normal: Normal ASIB read issuing capability
1: Force1: Force ASIB read issuing capability to 1

WRITE_ISS_OVERRIDE

Bit 1: Override ASIB write issuing capability.

Allowed values:
0: Normal: Normal ASIB write issuing capability
1: Force1: Force ASIB write issuing capability to 1

INI6_READ_QOS

AXI interconnect - INI x read QoS register

Offset: 0x47100, size: 32, reset: 0x00000004, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AR_QOS
rw
Toggle fields

AR_QOS

Bits 0-3: Read channel QoS setting.

Allowed values: 0x0-0xf

INI6_WRITE_QOS

AXI interconnect - INI x write QoS register

Offset: 0x47104, size: 32, reset: 0x00000004, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AW_QOS
rw
Toggle fields

AW_QOS

Bits 0-3: Write channel QoS setting.

Allowed values: 0x0-0xf

INI6_FN_MOD

AXI interconnect - INI x issuing functionality modification register

Offset: 0x47108, size: 32, reset: 0x00000004, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRITE_ISS_OVERRIDE
rw
READ_ISS_OVERRIDE
rw
Toggle fields

READ_ISS_OVERRIDE

Bit 0: Override ASIB read issuing capability.

Allowed values:
0: Normal: Normal ASIB read issuing capability
1: Force1: Force ASIB read issuing capability to 1

WRITE_ISS_OVERRIDE

Bit 1: Override ASIB write issuing capability.

Allowed values:
0: Normal: Normal ASIB write issuing capability
1: Force1: Force ASIB write issuing capability to 1

BDMA1

0x48022c00: Basic direct memory access controller

184/208 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 IFCR
0x8 CR [0]
0xc NDTR [0]
0x10 PAR [0]
0x14 M0AR [0]
0x18 M1AR [0]
0x1c CR [1]
0x20 NDTR [1]
0x24 PAR [1]
0x28 M0AR [1]
0x2c M1AR [1]
0x30 CR [2]
0x34 NDTR [2]
0x38 PAR [2]
0x3c M0AR [2]
0x40 M1AR [2]
0x44 CR [3]
0x48 NDTR [3]
0x4c PAR [3]
0x50 M0AR [3]
0x54 M1AR [3]
0x58 CR [4]
0x5c NDTR [4]
0x60 PAR [4]
0x64 M0AR [4]
0x68 M1AR [4]
0x6c CR [5]
0x70 NDTR [5]
0x74 PAR [5]
0x78 M0AR [5]
0x7c M1AR [5]
0x80 CR [6]
0x84 NDTR [6]
0x88 PAR [6]
0x8c M0AR [6]
0x90 M1AR [6]
0x94 CR [7]
0x98 NDTR [7]
0x9c PAR [7]
0xa0 M0AR [7]
0xa4 M1AR [7]
Toggle registers

ISR

DMA interrupt status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

32/32 fields covered.

Toggle fields

GIF[1]

Bit 0: Channel 1 Global interrupt flag.

Allowed values:
0: NoEvent: No TE, HT or TC event on channel x
1: Event: A TE, HT or TC event occurred on channel x

TCIF[1]

Bit 1: Channel 1 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event on channel x
1: Complete: A transfer complete event occurred on channel x

HTIF[1]

Bit 2: Channel 1 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event on channel x
1: Half: A half transfer event occurred on channel x

TEIF[1]

Bit 3: Channel 1 Transfer Error flag.

Allowed values:
0: NoError: No transfer error on channel x
1: Error: A transfer error occurred on channel x

GIF[2]

Bit 4: Channel 2 Global interrupt flag.

Allowed values:
0: NoEvent: No TE, HT or TC event on channel x
1: Event: A TE, HT or TC event occurred on channel x

TCIF[2]

Bit 5: Channel 2 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event on channel x
1: Complete: A transfer complete event occurred on channel x

HTIF[2]

Bit 6: Channel 2 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event on channel x
1: Half: A half transfer event occurred on channel x

TEIF[2]

Bit 7: Channel 2 Transfer Error flag.

Allowed values:
0: NoError: No transfer error on channel x
1: Error: A transfer error occurred on channel x

GIF[3]

Bit 8: Channel 3 Global interrupt flag.

Allowed values:
0: NoEvent: No TE, HT or TC event on channel x
1: Event: A TE, HT or TC event occurred on channel x

TCIF[3]

Bit 9: Channel 3 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event on channel x
1: Complete: A transfer complete event occurred on channel x

HTIF[3]

Bit 10: Channel 3 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event on channel x
1: Half: A half transfer event occurred on channel x

TEIF[3]

Bit 11: Channel 3 Transfer Error flag.

Allowed values:
0: NoError: No transfer error on channel x
1: Error: A transfer error occurred on channel x

GIF[4]

Bit 12: Channel 4 Global interrupt flag.

Allowed values:
0: NoEvent: No TE, HT or TC event on channel x
1: Event: A TE, HT or TC event occurred on channel x

TCIF[4]

Bit 13: Channel 4 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event on channel x
1: Complete: A transfer complete event occurred on channel x

HTIF[4]

Bit 14: Channel 4 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event on channel x
1: Half: A half transfer event occurred on channel x

TEIF[4]

Bit 15: Channel 4 Transfer Error flag.

Allowed values:
0: NoError: No transfer error on channel x
1: Error: A transfer error occurred on channel x

GIF[5]

Bit 16: Channel 5 Global interrupt flag.

Allowed values:
0: NoEvent: No TE, HT or TC event on channel x
1: Event: A TE, HT or TC event occurred on channel x

TCIF[5]

Bit 17: Channel 5 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event on channel x
1: Complete: A transfer complete event occurred on channel x

HTIF[5]

Bit 18: Channel 5 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event on channel x
1: Half: A half transfer event occurred on channel x

TEIF[5]

Bit 19: Channel 5 Transfer Error flag.

Allowed values:
0: NoError: No transfer error on channel x
1: Error: A transfer error occurred on channel x

GIF[6]

Bit 20: Channel 6 Global interrupt flag.

Allowed values:
0: NoEvent: No TE, HT or TC event on channel x
1: Event: A TE, HT or TC event occurred on channel x

TCIF[6]

Bit 21: Channel 6 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event on channel x
1: Complete: A transfer complete event occurred on channel x

HTIF[6]

Bit 22: Channel 6 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event on channel x
1: Half: A half transfer event occurred on channel x

TEIF[6]

Bit 23: Channel 6 Transfer Error flag.

Allowed values:
0: NoError: No transfer error on channel x
1: Error: A transfer error occurred on channel x

GIF[7]

Bit 24: Channel 7 Global interrupt flag.

Allowed values:
0: NoEvent: No TE, HT or TC event on channel x
1: Event: A TE, HT or TC event occurred on channel x

TCIF[7]

Bit 25: Channel 7 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event on channel x
1: Complete: A transfer complete event occurred on channel x

HTIF[7]

Bit 26: Channel 7 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event on channel x
1: Half: A half transfer event occurred on channel x

TEIF[7]

Bit 27: Channel 7 Transfer Error flag.

Allowed values:
0: NoError: No transfer error on channel x
1: Error: A transfer error occurred on channel x

GIF[8]

Bit 28: Channel 8 Global interrupt flag.

Allowed values:
0: NoEvent: No TE, HT or TC event on channel x
1: Event: A TE, HT or TC event occurred on channel x

TCIF[8]

Bit 29: Channel 8 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event on channel x
1: Complete: A transfer complete event occurred on channel x

HTIF[8]

Bit 30: Channel 8 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event on channel x
1: Half: A half transfer event occurred on channel x

TEIF[8]

Bit 31: Channel 8 Transfer Error flag.

Allowed values:
0: NoError: No transfer error on channel x
1: Error: A transfer error occurred on channel x

IFCR

DMA interrupt flag clear register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

Toggle fields

CGIF[1]

Bit 0: Channel 1 Global interrupt clear.

Allowed values:
1: Clear: Clear the corresponding CGIFx flag

CTCIF[1]

Bit 1: Channel 1 Transfer Complete clear.

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CHTIF[1]

Bit 2: Channel 1 Half Transfer clear.

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTEIF[1]

Bit 3: Channel 1 Transfer Error clear.

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CGIF[2]

Bit 4: Channel 2 Global interrupt clear.

Allowed values:
1: Clear: Clear the corresponding CGIFx flag

CTCIF[2]

Bit 5: Channel 2 Transfer Complete clear.

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CHTIF[2]

Bit 6: Channel 2 Half Transfer clear.

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTEIF[2]

Bit 7: Channel 2 Transfer Error clear.

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CGIF[3]

Bit 8: Channel 3 Global interrupt clear.

Allowed values:
1: Clear: Clear the corresponding CGIFx flag

CTCIF[3]

Bit 9: Channel 3 Transfer Complete clear.

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CHTIF[3]

Bit 10: Channel 3 Half Transfer clear.

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTEIF[3]

Bit 11: Channel 3 Transfer Error clear.

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CGIF[4]

Bit 12: Channel 4 Global interrupt clear.

Allowed values:
1: Clear: Clear the corresponding CGIFx flag

CTCIF[4]

Bit 13: Channel 4 Transfer Complete clear.

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CHTIF[4]

Bit 14: Channel 4 Half Transfer clear.

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTEIF[4]

Bit 15: Channel 4 Transfer Error clear.

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CGIF[5]

Bit 16: Channel 5 Global interrupt clear.

Allowed values:
1: Clear: Clear the corresponding CGIFx flag

CTCIF[5]

Bit 17: Channel 5 Transfer Complete clear.

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CHTIF[5]

Bit 18: Channel 5 Half Transfer clear.

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTEIF[5]

Bit 19: Channel 5 Transfer Error clear.

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CGIF[6]

Bit 20: Channel 6 Global interrupt clear.

Allowed values:
1: Clear: Clear the corresponding CGIFx flag

CTCIF[6]

Bit 21: Channel 6 Transfer Complete clear.

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CHTIF[6]

Bit 22: Channel 6 Half Transfer clear.

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTEIF[6]

Bit 23: Channel 6 Transfer Error clear.

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CGIF[7]

Bit 24: Channel 7 Global interrupt clear.

Allowed values:
1: Clear: Clear the corresponding CGIFx flag

CTCIF[7]

Bit 25: Channel 7 Transfer Complete clear.

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CHTIF[7]

Bit 26: Channel 7 Half Transfer clear.

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTEIF[7]

Bit 27: Channel 7 Transfer Error clear.

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CGIF[8]

Bit 28: Channel 8 Global interrupt clear.

Allowed values:
1: Clear: Clear the corresponding CGIFx flag

CTCIF[8]

Bit 29: Channel 8 Transfer Complete clear.

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CHTIF[8]

Bit 30: Channel 8 Half Transfer clear.

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTEIF[8]

Bit 31: Channel 8 Transfer Error clear.

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CR [0]

DMA channel x configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable This bit is set and cleared by software..

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

DIR

Bit 4: Data transfer direction This bit is set and cleared by software..

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral

CIRC

Bit 5: Circular mode This bit is set and cleared by software..

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 6: Peripheral increment mode This bit is set and cleared by software..

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 7: Memory increment mode This bit is set and cleared by software..

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 8-9: Peripheral size These bits are set and cleared by software..

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 10-11: Memory size These bits are set and cleared by software..

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PL

Bits 12-13: Channel priority level These bits are set and cleared by software..

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

MEM2MEM

Bit 14: Memory to memory mode This bit is set and cleared by software..

Allowed values:
0: Disabled: Memory-to-memory mode disabled
1: Enabled: Memory-to-memory mode enabled

DBM

Bit 15: Double-buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 16: Current target memory in double-buffer mode.

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

NDTR [0]

DMA channel x number of data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

Allowed values: 0x0-0xffff

PAR [0]

This register must not be written when the channel is enabled.

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a half-word address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

M0AR [0]

This register must not be written when the channel is enabled.

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

M1AR [0]

This register must not be written when the channel is enabled

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CR [1]

DMA channel x configuration register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable This bit is set and cleared by software..

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

DIR

Bit 4: Data transfer direction This bit is set and cleared by software..

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral

CIRC

Bit 5: Circular mode This bit is set and cleared by software..

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 6: Peripheral increment mode This bit is set and cleared by software..

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 7: Memory increment mode This bit is set and cleared by software..

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 8-9: Peripheral size These bits are set and cleared by software..

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 10-11: Memory size These bits are set and cleared by software..

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PL

Bits 12-13: Channel priority level These bits are set and cleared by software..

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

MEM2MEM

Bit 14: Memory to memory mode This bit is set and cleared by software..

Allowed values:
0: Disabled: Memory-to-memory mode disabled
1: Enabled: Memory-to-memory mode enabled

DBM

Bit 15: Double-buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 16: Current target memory in double-buffer mode.

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

NDTR [1]

DMA channel x number of data register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

Allowed values: 0x0-0xffff

PAR [1]

This register must not be written when the channel is enabled.

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a half-word address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

M0AR [1]

This register must not be written when the channel is enabled.

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

M1AR [1]

This register must not be written when the channel is enabled

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CR [2]

DMA channel x configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable This bit is set and cleared by software..

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

DIR

Bit 4: Data transfer direction This bit is set and cleared by software..

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral

CIRC

Bit 5: Circular mode This bit is set and cleared by software..

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 6: Peripheral increment mode This bit is set and cleared by software..

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 7: Memory increment mode This bit is set and cleared by software..

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 8-9: Peripheral size These bits are set and cleared by software..

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 10-11: Memory size These bits are set and cleared by software..

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PL

Bits 12-13: Channel priority level These bits are set and cleared by software..

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

MEM2MEM

Bit 14: Memory to memory mode This bit is set and cleared by software..

Allowed values:
0: Disabled: Memory-to-memory mode disabled
1: Enabled: Memory-to-memory mode enabled

DBM

Bit 15: Double-buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 16: Current target memory in double-buffer mode.

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

NDTR [2]

DMA channel x number of data register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

Allowed values: 0x0-0xffff

PAR [2]

This register must not be written when the channel is enabled.

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
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Toggle fields

PA

Bits 0-31: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a half-word address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

M0AR [2]

This register must not be written when the channel is enabled.

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

M1AR [2]

This register must not be written when the channel is enabled

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
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Toggle fields

MA

Bits 0-31: Memory address.

CR [3]

DMA channel x configuration register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable This bit is set and cleared by software..

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

DIR

Bit 4: Data transfer direction This bit is set and cleared by software..

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral

CIRC

Bit 5: Circular mode This bit is set and cleared by software..

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 6: Peripheral increment mode This bit is set and cleared by software..

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 7: Memory increment mode This bit is set and cleared by software..

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 8-9: Peripheral size These bits are set and cleared by software..

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 10-11: Memory size These bits are set and cleared by software..

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PL

Bits 12-13: Channel priority level These bits are set and cleared by software..

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

MEM2MEM

Bit 14: Memory to memory mode This bit is set and cleared by software..

Allowed values:
0: Disabled: Memory-to-memory mode disabled
1: Enabled: Memory-to-memory mode enabled

DBM

Bit 15: Double-buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 16: Current target memory in double-buffer mode.

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

NDTR [3]

DMA channel x number of data register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

Allowed values: 0x0-0xffff

PAR [3]

This register must not be written when the channel is enabled.

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a half-word address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

M0AR [3]

This register must not be written when the channel is enabled.

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

M1AR [3]

This register must not be written when the channel is enabled

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CR [4]

DMA channel x configuration register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable This bit is set and cleared by software..

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

DIR

Bit 4: Data transfer direction This bit is set and cleared by software..

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral

CIRC

Bit 5: Circular mode This bit is set and cleared by software..

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 6: Peripheral increment mode This bit is set and cleared by software..

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 7: Memory increment mode This bit is set and cleared by software..

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 8-9: Peripheral size These bits are set and cleared by software..

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 10-11: Memory size These bits are set and cleared by software..

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PL

Bits 12-13: Channel priority level These bits are set and cleared by software..

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

MEM2MEM

Bit 14: Memory to memory mode This bit is set and cleared by software..

Allowed values:
0: Disabled: Memory-to-memory mode disabled
1: Enabled: Memory-to-memory mode enabled

DBM

Bit 15: Double-buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 16: Current target memory in double-buffer mode.

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

NDTR [4]

DMA channel x number of data register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

Allowed values: 0x0-0xffff

PAR [4]

This register must not be written when the channel is enabled.

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a half-word address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

M0AR [4]

This register must not be written when the channel is enabled.

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

M1AR [4]

This register must not be written when the channel is enabled

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CR [5]

DMA channel x configuration register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable This bit is set and cleared by software..

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

DIR

Bit 4: Data transfer direction This bit is set and cleared by software..

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral

CIRC

Bit 5: Circular mode This bit is set and cleared by software..

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 6: Peripheral increment mode This bit is set and cleared by software..

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 7: Memory increment mode This bit is set and cleared by software..

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 8-9: Peripheral size These bits are set and cleared by software..

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 10-11: Memory size These bits are set and cleared by software..

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PL

Bits 12-13: Channel priority level These bits are set and cleared by software..

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

MEM2MEM

Bit 14: Memory to memory mode This bit is set and cleared by software..

Allowed values:
0: Disabled: Memory-to-memory mode disabled
1: Enabled: Memory-to-memory mode enabled

DBM

Bit 15: Double-buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 16: Current target memory in double-buffer mode.

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

NDTR [5]

DMA channel x number of data register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

Allowed values: 0x0-0xffff

PAR [5]

This register must not be written when the channel is enabled.

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a half-word address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

M0AR [5]

This register must not be written when the channel is enabled.

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

M1AR [5]

This register must not be written when the channel is enabled

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CR [6]

DMA channel x configuration register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable This bit is set and cleared by software..

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

DIR

Bit 4: Data transfer direction This bit is set and cleared by software..

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral

CIRC

Bit 5: Circular mode This bit is set and cleared by software..

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 6: Peripheral increment mode This bit is set and cleared by software..

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 7: Memory increment mode This bit is set and cleared by software..

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 8-9: Peripheral size These bits are set and cleared by software..

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 10-11: Memory size These bits are set and cleared by software..

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PL

Bits 12-13: Channel priority level These bits are set and cleared by software..

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

MEM2MEM

Bit 14: Memory to memory mode This bit is set and cleared by software..

Allowed values:
0: Disabled: Memory-to-memory mode disabled
1: Enabled: Memory-to-memory mode enabled

DBM

Bit 15: Double-buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 16: Current target memory in double-buffer mode.

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

NDTR [6]

DMA channel x number of data register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

Allowed values: 0x0-0xffff

PAR [6]

This register must not be written when the channel is enabled.

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a half-word address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

M0AR [6]

This register must not be written when the channel is enabled.

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

M1AR [6]

This register must not be written when the channel is enabled

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CR [7]

DMA channel x configuration register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable This bit is set and cleared by software..

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

DIR

Bit 4: Data transfer direction This bit is set and cleared by software..

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral

CIRC

Bit 5: Circular mode This bit is set and cleared by software..

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 6: Peripheral increment mode This bit is set and cleared by software..

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 7: Memory increment mode This bit is set and cleared by software..

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 8-9: Peripheral size These bits are set and cleared by software..

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 10-11: Memory size These bits are set and cleared by software..

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PL

Bits 12-13: Channel priority level These bits are set and cleared by software..

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

MEM2MEM

Bit 14: Memory to memory mode This bit is set and cleared by software..

Allowed values:
0: Disabled: Memory-to-memory mode disabled
1: Enabled: Memory-to-memory mode enabled

DBM

Bit 15: Double-buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 16: Current target memory in double-buffer mode.

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

NDTR [7]

DMA channel x number of data register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

Allowed values: 0x0-0xffff

PAR [7]

This register must not be written when the channel is enabled.

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a half-word address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

M0AR [7]

This register must not be written when the channel is enabled.

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

M1AR [7]

This register must not be written when the channel is enabled

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

BDMA2

0x58025400: Basic direct memory access controller

184/208 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 IFCR
0x8 CR [0]
0xc NDTR [0]
0x10 PAR [0]
0x14 M0AR [0]
0x18 M1AR [0]
0x1c CR [1]
0x20 NDTR [1]
0x24 PAR [1]
0x28 M0AR [1]
0x2c M1AR [1]
0x30 CR [2]
0x34 NDTR [2]
0x38 PAR [2]
0x3c M0AR [2]
0x40 M1AR [2]
0x44 CR [3]
0x48 NDTR [3]
0x4c PAR [3]
0x50 M0AR [3]
0x54 M1AR [3]
0x58 CR [4]
0x5c NDTR [4]
0x60 PAR [4]
0x64 M0AR [4]
0x68 M1AR [4]
0x6c CR [5]
0x70 NDTR [5]
0x74 PAR [5]
0x78 M0AR [5]
0x7c M1AR [5]
0x80 CR [6]
0x84 NDTR [6]
0x88 PAR [6]
0x8c M0AR [6]
0x90 M1AR [6]
0x94 CR [7]
0x98 NDTR [7]
0x9c PAR [7]
0xa0 M0AR [7]
0xa4 M1AR [7]
Toggle registers

ISR

DMA interrupt status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

32/32 fields covered.

Toggle fields

GIF[1]

Bit 0: Channel 1 Global interrupt flag.

Allowed values:
0: NoEvent: No TE, HT or TC event on channel x
1: Event: A TE, HT or TC event occurred on channel x

TCIF[1]

Bit 1: Channel 1 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event on channel x
1: Complete: A transfer complete event occurred on channel x

HTIF[1]

Bit 2: Channel 1 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event on channel x
1: Half: A half transfer event occurred on channel x

TEIF[1]

Bit 3: Channel 1 Transfer Error flag.

Allowed values:
0: NoError: No transfer error on channel x
1: Error: A transfer error occurred on channel x

GIF[2]

Bit 4: Channel 2 Global interrupt flag.

Allowed values:
0: NoEvent: No TE, HT or TC event on channel x
1: Event: A TE, HT or TC event occurred on channel x

TCIF[2]

Bit 5: Channel 2 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event on channel x
1: Complete: A transfer complete event occurred on channel x

HTIF[2]

Bit 6: Channel 2 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event on channel x
1: Half: A half transfer event occurred on channel x

TEIF[2]

Bit 7: Channel 2 Transfer Error flag.

Allowed values:
0: NoError: No transfer error on channel x
1: Error: A transfer error occurred on channel x

GIF[3]

Bit 8: Channel 3 Global interrupt flag.

Allowed values:
0: NoEvent: No TE, HT or TC event on channel x
1: Event: A TE, HT or TC event occurred on channel x

TCIF[3]

Bit 9: Channel 3 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event on channel x
1: Complete: A transfer complete event occurred on channel x

HTIF[3]

Bit 10: Channel 3 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event on channel x
1: Half: A half transfer event occurred on channel x

TEIF[3]

Bit 11: Channel 3 Transfer Error flag.

Allowed values:
0: NoError: No transfer error on channel x
1: Error: A transfer error occurred on channel x

GIF[4]

Bit 12: Channel 4 Global interrupt flag.

Allowed values:
0: NoEvent: No TE, HT or TC event on channel x
1: Event: A TE, HT or TC event occurred on channel x

TCIF[4]

Bit 13: Channel 4 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event on channel x
1: Complete: A transfer complete event occurred on channel x

HTIF[4]

Bit 14: Channel 4 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event on channel x
1: Half: A half transfer event occurred on channel x

TEIF[4]

Bit 15: Channel 4 Transfer Error flag.

Allowed values:
0: NoError: No transfer error on channel x
1: Error: A transfer error occurred on channel x

GIF[5]

Bit 16: Channel 5 Global interrupt flag.

Allowed values:
0: NoEvent: No TE, HT or TC event on channel x
1: Event: A TE, HT or TC event occurred on channel x

TCIF[5]

Bit 17: Channel 5 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event on channel x
1: Complete: A transfer complete event occurred on channel x

HTIF[5]

Bit 18: Channel 5 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event on channel x
1: Half: A half transfer event occurred on channel x

TEIF[5]

Bit 19: Channel 5 Transfer Error flag.

Allowed values:
0: NoError: No transfer error on channel x
1: Error: A transfer error occurred on channel x

GIF[6]

Bit 20: Channel 6 Global interrupt flag.

Allowed values:
0: NoEvent: No TE, HT or TC event on channel x
1: Event: A TE, HT or TC event occurred on channel x

TCIF[6]

Bit 21: Channel 6 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event on channel x
1: Complete: A transfer complete event occurred on channel x

HTIF[6]

Bit 22: Channel 6 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event on channel x
1: Half: A half transfer event occurred on channel x

TEIF[6]

Bit 23: Channel 6 Transfer Error flag.

Allowed values:
0: NoError: No transfer error on channel x
1: Error: A transfer error occurred on channel x

GIF[7]

Bit 24: Channel 7 Global interrupt flag.

Allowed values:
0: NoEvent: No TE, HT or TC event on channel x
1: Event: A TE, HT or TC event occurred on channel x

TCIF[7]

Bit 25: Channel 7 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event on channel x
1: Complete: A transfer complete event occurred on channel x

HTIF[7]

Bit 26: Channel 7 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event on channel x
1: Half: A half transfer event occurred on channel x

TEIF[7]

Bit 27: Channel 7 Transfer Error flag.

Allowed values:
0: NoError: No transfer error on channel x
1: Error: A transfer error occurred on channel x

GIF[8]

Bit 28: Channel 8 Global interrupt flag.

Allowed values:
0: NoEvent: No TE, HT or TC event on channel x
1: Event: A TE, HT or TC event occurred on channel x

TCIF[8]

Bit 29: Channel 8 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event on channel x
1: Complete: A transfer complete event occurred on channel x

HTIF[8]

Bit 30: Channel 8 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event on channel x
1: Half: A half transfer event occurred on channel x

TEIF[8]

Bit 31: Channel 8 Transfer Error flag.

Allowed values:
0: NoError: No transfer error on channel x
1: Error: A transfer error occurred on channel x

IFCR

DMA interrupt flag clear register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

Toggle fields

CGIF[1]

Bit 0: Channel 1 Global interrupt clear.

Allowed values:
1: Clear: Clear the corresponding CGIFx flag

CTCIF[1]

Bit 1: Channel 1 Transfer Complete clear.

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CHTIF[1]

Bit 2: Channel 1 Half Transfer clear.

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTEIF[1]

Bit 3: Channel 1 Transfer Error clear.

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CGIF[2]

Bit 4: Channel 2 Global interrupt clear.

Allowed values:
1: Clear: Clear the corresponding CGIFx flag

CTCIF[2]

Bit 5: Channel 2 Transfer Complete clear.

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CHTIF[2]

Bit 6: Channel 2 Half Transfer clear.

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTEIF[2]

Bit 7: Channel 2 Transfer Error clear.

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CGIF[3]

Bit 8: Channel 3 Global interrupt clear.

Allowed values:
1: Clear: Clear the corresponding CGIFx flag

CTCIF[3]

Bit 9: Channel 3 Transfer Complete clear.

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CHTIF[3]

Bit 10: Channel 3 Half Transfer clear.

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTEIF[3]

Bit 11: Channel 3 Transfer Error clear.

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CGIF[4]

Bit 12: Channel 4 Global interrupt clear.

Allowed values:
1: Clear: Clear the corresponding CGIFx flag

CTCIF[4]

Bit 13: Channel 4 Transfer Complete clear.

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CHTIF[4]

Bit 14: Channel 4 Half Transfer clear.

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTEIF[4]

Bit 15: Channel 4 Transfer Error clear.

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CGIF[5]

Bit 16: Channel 5 Global interrupt clear.

Allowed values:
1: Clear: Clear the corresponding CGIFx flag

CTCIF[5]

Bit 17: Channel 5 Transfer Complete clear.

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CHTIF[5]

Bit 18: Channel 5 Half Transfer clear.

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTEIF[5]

Bit 19: Channel 5 Transfer Error clear.

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CGIF[6]

Bit 20: Channel 6 Global interrupt clear.

Allowed values:
1: Clear: Clear the corresponding CGIFx flag

CTCIF[6]

Bit 21: Channel 6 Transfer Complete clear.

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CHTIF[6]

Bit 22: Channel 6 Half Transfer clear.

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTEIF[6]

Bit 23: Channel 6 Transfer Error clear.

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CGIF[7]

Bit 24: Channel 7 Global interrupt clear.

Allowed values:
1: Clear: Clear the corresponding CGIFx flag

CTCIF[7]

Bit 25: Channel 7 Transfer Complete clear.

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CHTIF[7]

Bit 26: Channel 7 Half Transfer clear.

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTEIF[7]

Bit 27: Channel 7 Transfer Error clear.

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CGIF[8]

Bit 28: Channel 8 Global interrupt clear.

Allowed values:
1: Clear: Clear the corresponding CGIFx flag

CTCIF[8]

Bit 29: Channel 8 Transfer Complete clear.

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CHTIF[8]

Bit 30: Channel 8 Half Transfer clear.

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTEIF[8]

Bit 31: Channel 8 Transfer Error clear.

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CR [0]

DMA channel x configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable This bit is set and cleared by software..

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

DIR

Bit 4: Data transfer direction This bit is set and cleared by software..

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral

CIRC

Bit 5: Circular mode This bit is set and cleared by software..

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 6: Peripheral increment mode This bit is set and cleared by software..

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 7: Memory increment mode This bit is set and cleared by software..

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 8-9: Peripheral size These bits are set and cleared by software..

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 10-11: Memory size These bits are set and cleared by software..

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PL

Bits 12-13: Channel priority level These bits are set and cleared by software..

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

MEM2MEM

Bit 14: Memory to memory mode This bit is set and cleared by software..

Allowed values:
0: Disabled: Memory-to-memory mode disabled
1: Enabled: Memory-to-memory mode enabled

DBM

Bit 15: Double-buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 16: Current target memory in double-buffer mode.

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

NDTR [0]

DMA channel x number of data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

Allowed values: 0x0-0xffff

PAR [0]

This register must not be written when the channel is enabled.

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a half-word address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

M0AR [0]

This register must not be written when the channel is enabled.

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

M1AR [0]

This register must not be written when the channel is enabled

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
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MA

Bits 0-31: Memory address.

CR [1]

DMA channel x configuration register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable This bit is set and cleared by software..

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

DIR

Bit 4: Data transfer direction This bit is set and cleared by software..

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral

CIRC

Bit 5: Circular mode This bit is set and cleared by software..

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 6: Peripheral increment mode This bit is set and cleared by software..

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 7: Memory increment mode This bit is set and cleared by software..

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 8-9: Peripheral size These bits are set and cleared by software..

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 10-11: Memory size These bits are set and cleared by software..

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PL

Bits 12-13: Channel priority level These bits are set and cleared by software..

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

MEM2MEM

Bit 14: Memory to memory mode This bit is set and cleared by software..

Allowed values:
0: Disabled: Memory-to-memory mode disabled
1: Enabled: Memory-to-memory mode enabled

DBM

Bit 15: Double-buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 16: Current target memory in double-buffer mode.

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

NDTR [1]

DMA channel x number of data register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
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NDT

Bits 0-15: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

Allowed values: 0x0-0xffff

PAR [1]

This register must not be written when the channel is enabled.

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
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PA

Bits 0-31: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a half-word address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

M0AR [1]

This register must not be written when the channel is enabled.

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
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MA

Bits 0-31: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

M1AR [1]

This register must not be written when the channel is enabled

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
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MA

Bits 0-31: Memory address.

CR [2]

DMA channel x configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable This bit is set and cleared by software..

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

DIR

Bit 4: Data transfer direction This bit is set and cleared by software..

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral

CIRC

Bit 5: Circular mode This bit is set and cleared by software..

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 6: Peripheral increment mode This bit is set and cleared by software..

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 7: Memory increment mode This bit is set and cleared by software..

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 8-9: Peripheral size These bits are set and cleared by software..

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 10-11: Memory size These bits are set and cleared by software..

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PL

Bits 12-13: Channel priority level These bits are set and cleared by software..

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

MEM2MEM

Bit 14: Memory to memory mode This bit is set and cleared by software..

Allowed values:
0: Disabled: Memory-to-memory mode disabled
1: Enabled: Memory-to-memory mode enabled

DBM

Bit 15: Double-buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 16: Current target memory in double-buffer mode.

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

NDTR [2]

DMA channel x number of data register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
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NDT

Bits 0-15: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

Allowed values: 0x0-0xffff

PAR [2]

This register must not be written when the channel is enabled.

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
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PA

Bits 0-31: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a half-word address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

M0AR [2]

This register must not be written when the channel is enabled.

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
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MA

Bits 0-31: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

M1AR [2]

This register must not be written when the channel is enabled

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
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MA

Bits 0-31: Memory address.

CR [3]

DMA channel x configuration register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
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Toggle fields

EN

Bit 0: Channel enable This bit is set and cleared by software..

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

DIR

Bit 4: Data transfer direction This bit is set and cleared by software..

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral

CIRC

Bit 5: Circular mode This bit is set and cleared by software..

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 6: Peripheral increment mode This bit is set and cleared by software..

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 7: Memory increment mode This bit is set and cleared by software..

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 8-9: Peripheral size These bits are set and cleared by software..

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 10-11: Memory size These bits are set and cleared by software..

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PL

Bits 12-13: Channel priority level These bits are set and cleared by software..

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

MEM2MEM

Bit 14: Memory to memory mode This bit is set and cleared by software..

Allowed values:
0: Disabled: Memory-to-memory mode disabled
1: Enabled: Memory-to-memory mode enabled

DBM

Bit 15: Double-buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 16: Current target memory in double-buffer mode.

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

NDTR [3]

DMA channel x number of data register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
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NDT

Bits 0-15: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

Allowed values: 0x0-0xffff

PAR [3]

This register must not be written when the channel is enabled.

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
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PA

Bits 0-31: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a half-word address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

M0AR [3]

This register must not be written when the channel is enabled.

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
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MA

Bits 0-31: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

M1AR [3]

This register must not be written when the channel is enabled

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
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MA

Bits 0-31: Memory address.

CR [4]

DMA channel x configuration register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable This bit is set and cleared by software..

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

DIR

Bit 4: Data transfer direction This bit is set and cleared by software..

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral

CIRC

Bit 5: Circular mode This bit is set and cleared by software..

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 6: Peripheral increment mode This bit is set and cleared by software..

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 7: Memory increment mode This bit is set and cleared by software..

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 8-9: Peripheral size These bits are set and cleared by software..

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 10-11: Memory size These bits are set and cleared by software..

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PL

Bits 12-13: Channel priority level These bits are set and cleared by software..

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

MEM2MEM

Bit 14: Memory to memory mode This bit is set and cleared by software..

Allowed values:
0: Disabled: Memory-to-memory mode disabled
1: Enabled: Memory-to-memory mode enabled

DBM

Bit 15: Double-buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 16: Current target memory in double-buffer mode.

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

NDTR [4]

DMA channel x number of data register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
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NDT

Bits 0-15: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

Allowed values: 0x0-0xffff

PAR [4]

This register must not be written when the channel is enabled.

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
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PA

Bits 0-31: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a half-word address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

M0AR [4]

This register must not be written when the channel is enabled.

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
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MA

Bits 0-31: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

M1AR [4]

This register must not be written when the channel is enabled

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
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MA

Bits 0-31: Memory address.

CR [5]

DMA channel x configuration register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable This bit is set and cleared by software..

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

DIR

Bit 4: Data transfer direction This bit is set and cleared by software..

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral

CIRC

Bit 5: Circular mode This bit is set and cleared by software..

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 6: Peripheral increment mode This bit is set and cleared by software..

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 7: Memory increment mode This bit is set and cleared by software..

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 8-9: Peripheral size These bits are set and cleared by software..

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 10-11: Memory size These bits are set and cleared by software..

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PL

Bits 12-13: Channel priority level These bits are set and cleared by software..

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

MEM2MEM

Bit 14: Memory to memory mode This bit is set and cleared by software..

Allowed values:
0: Disabled: Memory-to-memory mode disabled
1: Enabled: Memory-to-memory mode enabled

DBM

Bit 15: Double-buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 16: Current target memory in double-buffer mode.

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

NDTR [5]

DMA channel x number of data register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
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Toggle fields

NDT

Bits 0-15: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

Allowed values: 0x0-0xffff

PAR [5]

This register must not be written when the channel is enabled.

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
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Toggle fields

PA

Bits 0-31: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a half-word address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

M0AR [5]

This register must not be written when the channel is enabled.

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

M1AR [5]

This register must not be written when the channel is enabled

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CR [6]

DMA channel x configuration register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable This bit is set and cleared by software..

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

DIR

Bit 4: Data transfer direction This bit is set and cleared by software..

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral

CIRC

Bit 5: Circular mode This bit is set and cleared by software..

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 6: Peripheral increment mode This bit is set and cleared by software..

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 7: Memory increment mode This bit is set and cleared by software..

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 8-9: Peripheral size These bits are set and cleared by software..

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 10-11: Memory size These bits are set and cleared by software..

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PL

Bits 12-13: Channel priority level These bits are set and cleared by software..

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

MEM2MEM

Bit 14: Memory to memory mode This bit is set and cleared by software..

Allowed values:
0: Disabled: Memory-to-memory mode disabled
1: Enabled: Memory-to-memory mode enabled

DBM

Bit 15: Double-buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 16: Current target memory in double-buffer mode.

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

NDTR [6]

DMA channel x number of data register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

Allowed values: 0x0-0xffff

PAR [6]

This register must not be written when the channel is enabled.

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a half-word address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

M0AR [6]

This register must not be written when the channel is enabled.

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

M1AR [6]

This register must not be written when the channel is enabled

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CR [7]

DMA channel x configuration register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable This bit is set and cleared by software..

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

DIR

Bit 4: Data transfer direction This bit is set and cleared by software..

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral

CIRC

Bit 5: Circular mode This bit is set and cleared by software..

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 6: Peripheral increment mode This bit is set and cleared by software..

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 7: Memory increment mode This bit is set and cleared by software..

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 8-9: Peripheral size These bits are set and cleared by software..

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 10-11: Memory size These bits are set and cleared by software..

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PL

Bits 12-13: Channel priority level These bits are set and cleared by software..

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

MEM2MEM

Bit 14: Memory to memory mode This bit is set and cleared by software..

Allowed values:
0: Disabled: Memory-to-memory mode disabled
1: Enabled: Memory-to-memory mode enabled

DBM

Bit 15: Double-buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 16: Current target memory in double-buffer mode.

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

NDTR [7]

DMA channel x number of data register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not..

Allowed values: 0x0-0xffff

PAR [7]

This register must not be written when the channel is enabled.

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a half-word address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address..

M0AR [7]

This register must not be written when the channel is enabled.

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address..

M1AR [7]

This register must not be written when the channel is enabled

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CAN_CCU

0x4000a800: CCU registers

0/21 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CREL
0x4 CCFG
0x8 CSTAT
0xc CWD
0x10 IR
0x14 IE
Toggle registers

CREL

Clock Calibration Unit Core Release Register

Offset: 0x0, size: 32, reset: 0x11141218, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REL
rw
STEP
rw
SUBSTEP
rw
YEAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MON
rw
DAY
rw
Toggle fields

DAY

Bits 0-7: Time Stamp Day.

MON

Bits 8-15: Time Stamp Month.

YEAR

Bits 16-19: Time Stamp Year.

SUBSTEP

Bits 20-23: Sub-step of Core Release.

STEP

Bits 24-27: Step of Core Release.

REL

Bits 28-31: Core Release.

CCFG

Calibration Configuration Register

Offset: 0x4, size: 32, reset: 0x00000004, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWR
rw
CDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCPM
rw
CFL
rw
BCC
rw
TQBT
rw
Toggle fields

TQBT

Bits 0-4: Time Quanta per Bit Time.

BCC

Bit 6: Bypass Clock Calibration.

CFL

Bit 7: Calibration Field Length.

OCPM

Bits 8-15: Oscillator Clock Periods Minimum.

CDIV

Bits 16-19: Clock Divider.

SWR

Bit 31: Software Reset.

CSTAT

Calibration Status Register

Offset: 0x8, size: 32, reset: 0x0203FFFF, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CALS
rw
TQC
rw
OCPC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCPC
rw
Toggle fields

OCPC

Bits 0-17: Oscillator Clock Period Counter.

TQC

Bits 18-28: Time Quanta Counter.

CALS

Bits 30-31: Calibration State.

CWD

Calibration Watchdog Register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDC
rw
Toggle fields

WDC

Bits 0-15: WDC.

WDV

Bits 16-31: WDV.

IR

Clock Calibration Unit Interrupt Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSC
rw
CWE
rw
Toggle fields

CWE

Bit 0: Calibration Watchdog Event.

CSC

Bit 1: Calibration State Changed.

IE

Clock Calibration Unit Interrupt Enable Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSCE
rw
CWEE
rw
Toggle fields

CWEE

Bit 0: Calibration Watchdog Event Enable.

CSCE

Bit 1: Calibration State Changed Enable.

CEC

0x40006c00: CEC

4/40 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 CFGR
0x8 TXDR
0xc RXDR
0x10 ISR
0x14 IER
Toggle registers

CR

CEC control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXEOM
rw
TXSOM
rw
CECEN
rw
Toggle fields

CECEN

Bit 0: CEC Enable The CECEN bit is set and cleared by software. CECEN=1 starts message reception and enables the TXSOM control. CECEN=0 disables the CEC peripheral, clears all bits of CEC_CR register and aborts any on-going reception or transmission..

TXSOM

Bit 1: Tx Start Of Message TXSOM is set by software to command transmission of the first byte of a CEC message. If the CEC message consists of only one byte, TXEOM must be set before of TXSOM. Start-Bit is effectively started on the CEC line after SFT is counted. If TXSOM is set while a message reception is ongoing, transmission will start after the end of reception. TXSOM is cleared by hardware after the last byte of the message is sent with a positive acknowledge (TXEND=1), in case of transmission underrun (TXUDR=1), negative acknowledge (TXACKE=1), and transmission error (TXERR=1). It is also cleared by CECEN=0. It is not cleared and transmission is automatically retried in case of arbitration lost (ARBLST=1). TXSOM can be also used as a status bit informing application whether any transmission request is pending or under execution. The application can abort a transmission request at any time by clearing the CECEN bit. Note: TXSOM must be set when CECEN=1 TXSOM must be set when transmission data is available into TXDR HEADERs first four bits containing own peripheral address are taken from TXDR[7:4], not from CEC_CFGR.OAR which is used only for reception.

TXEOM

Bit 2: Tx End Of Message The TXEOM bit is set by software to command transmission of the last byte of a CEC message. TXEOM is cleared by hardware at the same time and under the same conditions as for TXSOM. Note: TXEOM must be set when CECEN=1 TXEOM must be set before writing transmission data to TXDR If TXEOM is set when TXSOM=0, transmitted message will consist of 1 byte (HEADER) only (PING message).

CFGR

This register is used to configure the HDMI-CEC controller. It is mandatory to write CEC_CFGR only when CECEN=0.

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

2/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LSTN
rw
OAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SFTOPT
rw
BRDNOGEN
rw
LBPEGEN
rw
BREGEN
rw
BRESTP
rw
RXTOL
rw
SFT
rw
Toggle fields

SFT

Bits 0-2: Signal Free Time SFT bits are set by software. In the SFT=0x0 configuration the number of nominal data bit periods waited before transmission is ruled by hardware according to the transmission history. In all the other configurations the SFT number is determined by software. * 0x0 ** 2.5 Data-Bit periods if CEC is the last bus initiator with unsuccessful transmission (ARBLST=1, TXERR=1, TXUDR=1 or TXACKE= 1) ** 4 Data-Bit periods if CEC is the new bus initiator ** 6 Data-Bit periods if CEC is the last bus initiator with successful transmission (TXEOM=1) * 0x1: 0.5 nominal data bit periods * 0x2: 1.5 nominal data bit periods * 0x3: 2.5 nominal data bit periods * 0x4: 3.5 nominal data bit periods * 0x5: 4.5 nominal data bit periods * 0x6: 5.5 nominal data bit periods * 0x7: 6.5 nominal data bit periods.

Allowed values: 0x0-0x7

RXTOL

Bit 3: Rx-Tolerance The RXTOL bit is set and cleared by software. ** Start-Bit, +/- 200 s rise, +/- 200 s fall. ** Data-Bit: +/- 200 s rise. +/- 350 s fall. ** Start-Bit: +/- 400 s rise, +/- 400 s fall ** Data-Bit: +/-300 s rise, +/- 500 s fall.

BRESTP

Bit 4: Rx-Stop on Bit Rising Error The BRESTP bit is set and cleared by software..

BREGEN

Bit 5: Generate Error-Bit on Bit Rising Error The BREGEN bit is set and cleared by software. Note: If BRDNOGEN=0, an Error-bit is generated upon BRE detection with BRESTP=1 in broadcast even if BREGEN=0.

LBPEGEN

Bit 6: Generate Error-Bit on Long Bit Period Error The LBPEGEN bit is set and cleared by software. Note: If BRDNOGEN=0, an Error-bit is generated upon LBPE detection in broadcast even if LBPEGEN=0.

BRDNOGEN

Bit 7: Avoid Error-Bit Generation in Broadcast The BRDNOGEN bit is set and cleared by software..

SFTOPT

Bit 8: SFT Option Bit The SFTOPT bit is set and cleared by software..

OAR

Bits 16-30: Own addresses configuration The OAR bits are set by software to select which destination logical addresses has to be considered in receive mode. Each bit, when set, enables the CEC logical address identified by the given bit position. At the end of HEADER reception, the received destination address is compared with the enabled addresses. In case of matching address, the incoming message is acknowledged and received. In case of non-matching address, the incoming message is received only in listen mode (LSTN=1), but without acknowledge sent. Broadcast messages are always received. Example: OAR = 0b000 0000 0010 0001 means that CEC acknowledges addresses 0x0 and 0x5. Consequently, each message directed to one of these addresses is received..

Allowed values: 0x0-0x7fff

LSTN

Bit 31: Listen mode LSTN bit is set and cleared by software..

TXDR

CEC Tx data register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXD
w
Toggle fields

TXD

Bits 0-7: Tx Data register. TXD is a write-only register containing the data byte to be transmitted. Note: TXD must be written when TXSTART=1.

Allowed values: 0x0-0xff

RXDR

CEC Rx Data Register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXD
r
Toggle fields

RXD

Bits 0-7: Rx Data register. RXD is read-only and contains the last data byte which has been received from the CEC line..

ISR

CEC Interrupt and Status Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXACKE
rw
TXERR
rw
TXUDR
rw
TXEND
rw
TXBR
rw
ARBLST
rw
RXACKE
rw
LBPE
rw
SBPE
rw
BRE
rw
RXOVR
rw
RXEND
rw
RXBR
rw
Toggle fields

RXBR

Bit 0: Rx-Byte Received The RXBR bit is set by hardware to inform application that a new byte has been received from the CEC line and stored into the RXD buffer. RXBR is cleared by software write at 1..

RXEND

Bit 1: End Of Reception RXEND is set by hardware to inform application that the last byte of a CEC message is received from the CEC line and stored into the RXD buffer. RXEND is set at the same time of RXBR. RXEND is cleared by software write at 1..

RXOVR

Bit 2: Rx-Overrun RXOVR is set by hardware if RXBR is not yet cleared at the time a new byte is received on the CEC line and stored into RXD. RXOVR assertion stops message reception so that no acknowledge is sent. In case of broadcast, a negative acknowledge is sent. RXOVR is cleared by software write at 1..

BRE

Bit 3: Rx-Bit Rising Error BRE is set by hardware in case a Data-Bit waveform is detected with Bit Rising Error. BRE is set either at the time the misplaced rising edge occurs, or at the end of the maximum BRE tolerance allowed by RXTOL, in case rising edge is still longing. BRE stops message reception if BRESTP=1. BRE generates an Error-Bit on the CEC line if BREGEN=1. BRE is cleared by software write at 1..

SBPE

Bit 4: Rx-Short Bit Period Error SBPE is set by hardware in case a Data-Bit waveform is detected with Short Bit Period Error. SBPE is set at the time the anticipated falling edge occurs. SBPE generates an Error-Bit on the CEC line. SBPE is cleared by software write at 1..

LBPE

Bit 5: Rx-Long Bit Period Error LBPE is set by hardware in case a Data-Bit waveform is detected with Long Bit Period Error. LBPE is set at the end of the maximum bit-extension tolerance allowed by RXTOL, in case falling edge is still longing. LBPE always stops reception of the CEC message. LBPE generates an Error-Bit on the CEC line if LBPEGEN=1. In case of broadcast, Error-Bit is generated even in case of LBPEGEN=0. LBPE is cleared by software write at 1..

RXACKE

Bit 6: Rx-Missing Acknowledge In receive mode, RXACKE is set by hardware to inform application that no acknowledge was seen on the CEC line. RXACKE applies only for broadcast messages and in listen mode also for not directly addressed messages (destination address not enabled in OAR). RXACKE aborts message reception. RXACKE is cleared by software write at 1..

ARBLST

Bit 7: Arbitration Lost ARBLST is set by hardware to inform application that CEC device is switching to reception due to arbitration lost event following the TXSOM command. ARBLST can be due either to a contending CEC device starting earlier or starting at the same time but with higher HEADER priority. After ARBLST assertion TXSOM bit keeps pending for next transmission attempt. ARBLST is cleared by software write at 1..

TXBR

Bit 8: Tx-Byte Request TXBR is set by hardware to inform application that the next transmission data has to be written to TXDR. TXBR is set when the 4th bit of currently transmitted byte is sent. Application must write the next byte to TXDR within 6 nominal data-bit periods before transmission underrun error occurs (TXUDR). TXBR is cleared by software write at 1..

TXEND

Bit 9: End of Transmission TXEND is set by hardware to inform application that the last byte of the CEC message has been successfully transmitted. TXEND clears the TXSOM and TXEOM control bits. TXEND is cleared by software write at 1..

TXUDR

Bit 10: Tx-Buffer Underrun In transmission mode, TXUDR is set by hardware if application was not in time to load TXDR before of next byte transmission. TXUDR aborts message transmission and clears TXSOM and TXEOM control bits. TXUDR is cleared by software write at 1.

TXERR

Bit 11: Tx-Error In transmission mode, TXERR is set by hardware if the CEC initiator detects low impedance on the CEC line while it is released. TXERR aborts message transmission and clears TXSOM and TXEOM controls. TXERR is cleared by software write at 1..

TXACKE

Bit 12: Tx-Missing Acknowledge Error In transmission mode, TXACKE is set by hardware to inform application that no acknowledge was received. In case of broadcast transmission, TXACKE informs application that a negative acknowledge was received. TXACKE aborts message transmission and clears TXSOM and TXEOM controls. TXACKE is cleared by software write at 1..

IER

CEC interrupt enable register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

Toggle fields

RXBRIE

Bit 0: Rx-Byte Received Interrupt Enable The RXBRIE bit is set and cleared by software..

RXENDIE

Bit 1: End Of Reception Interrupt Enable The RXENDIE bit is set and cleared by software..

RXOVRIE

Bit 2: Rx-Buffer Overrun Interrupt Enable The RXOVRIE bit is set and cleared by software..

BREIE

Bit 3: Bit Rising Error Interrupt Enable The BREIE bit is set and cleared by software..

SBPEIE

Bit 4: Short Bit Period Error Interrupt Enable The SBPEIE bit is set and cleared by software..

LBPEIE

Bit 5: Long Bit Period Error Interrupt Enable The LBPEIE bit is set and cleared by software..

RXACKIE

Bit 6: Rx-Missing Acknowledge Error Interrupt Enable The RXACKIE bit is set and cleared by software..

ARBLSTIE

Bit 7: Arbitration Lost Interrupt Enable The ARBLSTIE bit is set and cleared by software..

TXBRIE

Bit 8: Tx-Byte Request Interrupt Enable The TXBRIE bit is set and cleared by software..

TXENDIE

Bit 9: Tx-End Of Message Interrupt Enable The TXENDIE bit is set and cleared by software..

TXUDRIE

Bit 10: Tx-Underrun Interrupt Enable The TXUDRIE bit is set and cleared by software..

TXERRIE

Bit 11: Tx-Error Interrupt Enable The TXERRIE bit is set and cleared by software..

TXACKIE

Bit 12: Tx-Missing Acknowledge Error Interrupt Enable The TXACKEIE bit is set and cleared by software..

COMP1

0x58003800: COMP1

4/31 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 SR
0x4 ICFR
0x8 OR
0xc CFGR1
0x10 CFGR2
Toggle registers

SR

Comparator status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
C2IF
r
C1IF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C2VAL
r
C1VAL
r
Toggle fields

C1VAL

Bit 0: COMP channel 1 output status bit.

C2VAL

Bit 1: COMP channel 2 output status bit.

C1IF

Bit 16: COMP channel 1 Interrupt Flag.

C2IF

Bit 17: COMP channel 2 Interrupt Flag.

ICFR

Comparator interrupt clear flag register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC2IF
w
CC1IF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

CC1IF

Bit 16: Clear COMP channel 1 Interrupt Flag.

CC2IF

Bit 17: Clear COMP channel 2 Interrupt Flag.

OR

Comparator option register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR
rw
AFOP
rw
Toggle fields

AFOP

Bits 0-10: Selection of source for alternate function of output ports.

OR

Bits 11-31: Option Register.

CFGR1

Comparator configuration register 1

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
BLANKING
rw
INPSEL
rw
INMSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWRMODE
rw
HYST
rw
ITEN
rw
POLARITY
rw
SCALEN
rw
BRGEN
rw
EN
rw
Toggle fields

EN

Bit 0: COMP channel 1 enable bit.

BRGEN

Bit 1: Scaler bridge enable.

SCALEN

Bit 2: Voltage scaler enable bit.

POLARITY

Bit 3: COMP channel 1 polarity selection bit.

ITEN

Bit 6: COMP channel 1 interrupt enable.

HYST

Bits 8-9: COMP channel 1 hysteresis selection bits.

PWRMODE

Bits 12-13: Power Mode of the COMP channel 1.

INMSEL

Bits 16-18: COMP channel 1 inverting input selection field.

INPSEL

Bit 20: COMP channel 1 non-inverting input selection bit.

BLANKING

Bits 24-27: COMP channel 1 blanking source selection bits.

LOCK

Bit 31: Lock bit.

CFGR2

Comparator configuration register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
BLANKING
rw
INPSEL
rw
INMSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWRMODE
rw
HYST
rw
ITEN
rw
WINMODE
rw
POLARITY
rw
SCALEN
rw
BRGEN
rw
EN
rw
Toggle fields

EN

Bit 0: COMP channel 1 enable bit.

BRGEN

Bit 1: Scaler bridge enable.

SCALEN

Bit 2: Voltage scaler enable bit.

POLARITY

Bit 3: COMP channel 1 polarity selection bit.

WINMODE

Bit 4: Window comparator mode selection bit.

ITEN

Bit 6: COMP channel 1 interrupt enable.

HYST

Bits 8-9: COMP channel 1 hysteresis selection bits.

PWRMODE

Bits 12-13: Power Mode of the COMP channel 1.

INMSEL

Bits 16-18: COMP channel 1 inverting input selection field.

INPSEL

Bit 20: COMP channel 1 non-inverting input selection bit.

BLANKING

Bits 24-27: COMP channel 1 blanking source selection bits.

LOCK

Bit 31: Lock bit.

CRC

0x40023000: Cryptographic processor

10/10 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 DR
0x0 (16-bit) DR16
0x0 (8-bit) DR8
0x4 IDR
0x8 CR
0x10 INIT
0x14 POL
Toggle registers

DR

Data register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-31: Data Register.

Allowed values: 0x0-0xffffffff

DR16

Data register - half-word sized

Offset: 0x0, size: 16, reset: 0x0000FFFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR16
rw
Toggle fields

DR16

Bits 0-15: Data register bits.

Allowed values: 0x0-0xffff

DR8

Data register - byte sized

Offset: 0x0, size: 8, reset: 0x000000FF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR8
rw
Toggle fields

DR8

Bits 0-7: Data register bits.

Allowed values: 0x0-0xff

IDR

Independent Data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR
rw
Toggle fields

IDR

Bits 0-31: Independent Data register.

Allowed values: 0x0-0xffffffff

CR

Control register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REV_OUT
rw
REV_IN
rw
POLYSIZE
rw
RESET
w
Toggle fields

RESET

Bit 0: RESET bit.

Allowed values:
1: Reset: Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF

POLYSIZE

Bits 3-4: Polynomial size.

Allowed values:
0: Polysize32: 32-bit polynomial
1: Polysize16: 16-bit polynomial
2: Polysize8: 8-bit polynomial
3: Polysize7: 7-bit polynomial

REV_IN

Bits 5-6: Reverse input data.

Allowed values:
0: Normal: Bit order not affected
1: Byte: Bit reversal done by byte
2: HalfWord: Bit reversal done by half-word
3: Word: Bit reversal done by word

REV_OUT

Bit 7: Reverse output data.

Allowed values:
0: Normal: Bit order not affected
1: Reversed: Bit reversed output

INIT

Initial CRC value

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INIT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INIT
rw
Toggle fields

INIT

Bits 0-31: Programmable initial CRC value.

Allowed values: 0x0-0xffffffff

POL

CRC polynomial

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
POL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POL
rw
Toggle fields

POL

Bits 0-31: Programmable polynomial.

Allowed values: 0x0-0xffffffff

CRS

0x40008400: CRS

10/26 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 CFGR
0x8 ISR
0xc ICR
Toggle registers

CR

CRS control register

Offset: 0x0, size: 32, reset: 0x00002000, access: Unspecified

1/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIM
rw
SWSYNC
r
AUTOTRIMEN
rw
CEN
rw
ESYNCIE
rw
ERRIE
rw
SYNCWARNIE
rw
SYNCOKIE
rw
Toggle fields

SYNCOKIE

Bit 0: SYNC event OK interrupt enable.

SYNCWARNIE

Bit 1: SYNC warning interrupt enable.

ERRIE

Bit 2: Synchronization or trimming error interrupt enable.

ESYNCIE

Bit 3: Expected SYNC interrupt enable.

CEN

Bit 5: Frequency error counter enable This bit enables the oscillator clock for the frequency error counter. When this bit is set, the CRS_CFGR register is write-protected and cannot be modified..

AUTOTRIMEN

Bit 6: Automatic trimming enable This bit enables the automatic hardware adjustment of TRIM bits according to the measured frequency error between two SYNC events. If this bit is set, the TRIM bits are read-only. The TRIM value can be adjusted by hardware by one or two steps at a time, depending on the measured frequency error value. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details..

SWSYNC

Bit 7: Generate software SYNC event This bit is set by software in order to generate a software SYNC event. It is automatically cleared by hardware..

TRIM

Bits 8-13: HSI48 oscillator smooth trimming These bits provide a user-programmable trimming value to the HSI48 oscillator. They can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI48. The default value is 32, which corresponds to the middle of the trimming interval. The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value corresponds to a higher output frequency. When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only..

CFGR

This register can be written only when the frequency error counter is disabled (CEN bit is cleared in CRS_CR). When the counter is enabled, this register is write-protected.

Offset: 0x4, size: 32, reset: 0x2022BB7F, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNCPOL
rw
SYNCSRC
rw
SYNCDIV
rw
FELIM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RELOAD
rw
Toggle fields

RELOAD

Bits 0-15: Counter reload value RELOAD is the value to be loaded in the frequency error counter with each SYNC event. Refer to Section7.3.3: Frequency error measurement for more details about counter behavior..

FELIM

Bits 16-23: Frequency error limit FELIM contains the value to be used to evaluate the captured frequency error value latched in the FECAP[15:0] bits of the CRS_ISR register. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details about FECAP evaluation..

SYNCDIV

Bits 24-26: SYNC divider These bits are set and cleared by software to control the division factor of the SYNC signal..

SYNCSRC

Bits 28-29: SYNC signal source selection These bits are set and cleared by software to select the SYNC signal source. Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the periodic USB SOF will not be generated by the host. No SYNC signal will therefore be provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs should be used as SYNC signal..

SYNCPOL

Bit 31: SYNC polarity selection This bit is set and cleared by software to select the input polarity for the SYNC signal source..

ISR

CRS interrupt and status register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FECAP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEDIR
r
TRIMOVF
r
SYNCMISS
r
SYNCERR
r
ESYNCF
r
ERRF
r
SYNCWARNF
r
SYNCOKF
r
Toggle fields

SYNCOKF

Bit 0: SYNC event OK flag This flag is set by hardware when the measured frequency error is smaller than FELIM * 3. This means that either no adjustment of the TRIM value is needed or that an adjustment by one trimming step is enough to compensate the frequency error. An interrupt is generated if the SYNCOKIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCOKC bit in the CRS_ICR register..

SYNCWARNF

Bit 1: SYNC warning flag This flag is set by hardware when the measured frequency error is greater than or equal to FELIM * 3, but smaller than FELIM * 128. This means that to compensate the frequency error, the TRIM value must be adjusted by two steps or more. An interrupt is generated if the SYNCWARNIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCWARNC bit in the CRS_ICR register..

ERRF

Bit 2: Error flag This flag is set by hardware in case of any synchronization or trimming error. It is the logical OR of the TRIMOVF, SYNCMISS and SYNCERR bits. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software in reaction to setting the ERRC bit in the CRS_ICR register, which clears the TRIMOVF, SYNCMISS and SYNCERR bits..

ESYNCF

Bit 3: Expected SYNC flag This flag is set by hardware when the frequency error counter reached a zero value. An interrupt is generated if the ESYNCIE bit is set in the CRS_CR register. It is cleared by software by setting the ESYNCC bit in the CRS_ICR register..

SYNCERR

Bit 8: SYNC error This flag is set by hardware when the SYNC pulse arrives before the ESYNC event and the measured frequency error is greater than or equal to FELIM * 128. This means that the frequency error is too big (internal frequency too low) to be compensated by adjusting the TRIM value, and that some other action should be taken. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register..

SYNCMISS

Bit 9: SYNC missed This flag is set by hardware when the frequency error counter reached value FELIM * 128 and no SYNC was detected, meaning either that a SYNC pulse was missed or that the frequency error is too big (internal frequency too high) to be compensated by adjusting the TRIM value, and that some other action should be taken. At this point, the frequency error counter is stopped (waiting for a next SYNC) and an interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register..

TRIMOVF

Bit 10: Trimming overflow or underflow This flag is set by hardware when the automatic trimming tries to over- or under-flow the TRIM value. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register..

FEDIR

Bit 15: Frequency error direction FEDIR is the counting direction of the frequency error counter latched in the time of the last SYNC event. It shows whether the actual frequency is below or above the target..

FECAP

Bits 16-31: Frequency error capture FECAP is the frequency error counter value latched in the time of the last SYNC event. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details about FECAP usage..

ICR

CRS interrupt flag clear register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ESYNCC
rw
ERRC
rw
SYNCWARNC
rw
SYNCOKC
rw
Toggle fields

SYNCOKC

Bit 0: SYNC event OK clear flag Writing 1 to this bit clears the SYNCOKF flag in the CRS_ISR register..

SYNCWARNC

Bit 1: SYNC warning clear flag Writing 1 to this bit clears the SYNCWARNF flag in the CRS_ISR register..

ERRC

Bit 2: Error clear flag Writing 1 to this bit clears TRIMOVF, SYNCMISS and SYNCERR bits and consequently also the ERRF flag in the CRS_ISR register..

ESYNCC

Bit 3: Expected SYNC clear flag Writing 1 to this bit clears the ESYNCF flag in the CRS_ISR register..

CRYP

0x48021000: Cryptographic processor

10/51 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SR
0x8 DIN
0xc DOUT
0x10 DMACR
0x14 IMSCR
0x18 RISR
0x1c MISR
0x20 K0LR
0x24 K0RR
0x28 K1LR
0x2c K1RR
0x30 K2LR
0x34 K2RR
0x38 K3LR
0x3c K3RR
0x40 IV0LR
0x44 IV0RR
0x48 IV1LR
0x4c IV1RR
0x50 CSGCMCCM0R
0x54 CSGCMCCM1R
0x58 CSGCMCCM2R
0x5c CSGCMCCM3R
0x60 CSGCMCCM4R
0x64 CSGCMCCM5R
0x68 CSGCMCCM6R
0x6c CSGCMCCM7R
0x70 CSGCM0R
0x74 CSGCM1R
0x78 CSGCM2R
0x7c CSGCM3R
0x80 CSGCM4R
0x84 CSGCM5R
0x88 CSGCM6R
0x8c CSGCM7R
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALGOMODE3
rw
GCM_CCMPH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRYPEN
rw
FFLUSH
w
KEYSIZE
rw
DATATYPE
rw
ALGOMODE0
rw
ALGODIR
rw
Toggle fields

ALGODIR

Bit 2: Algorithm direction.

ALGOMODE0

Bits 3-5: Algorithm mode.

DATATYPE

Bits 6-7: Data type selection.

KEYSIZE

Bits 8-9: Key size selection (AES mode only).

FFLUSH

Bit 14: FIFO flush.

CRYPEN

Bit 15: Cryptographic processor enable.

GCM_CCMPH

Bits 16-17: GCM_CCMPH.

ALGOMODE3

Bit 19: ALGOMODE.

SR

status register

Offset: 0x4, size: 32, reset: 0x00000003, access: read-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r
OFFU
r
OFNE
r
IFNF
r
IFEM
r
Toggle fields

IFEM

Bit 0: Input FIFO empty.

IFNF

Bit 1: Input FIFO not full.

OFNE

Bit 2: Output FIFO not empty.

OFFU

Bit 3: Output FIFO full.

BUSY

Bit 4: Busy bit.

DIN

data input register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAIN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAIN
rw
Toggle fields

DATAIN

Bits 0-31: Data input.

DOUT

data output register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAOUT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAOUT
r
Toggle fields

DATAOUT

Bits 0-31: Data output.

DMACR

DMA control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOEN
rw
DIEN
rw
Toggle fields

DIEN

Bit 0: DMA input enable.

DOEN

Bit 1: DMA output enable.

IMSCR

interrupt mask set/clear register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTIM
rw
INIM
rw
Toggle fields

INIM

Bit 0: Input FIFO service interrupt mask.

OUTIM

Bit 1: Output FIFO service interrupt mask.

RISR

raw interrupt status register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTRIS
r
INRIS
r
Toggle fields

INRIS

Bit 0: Input FIFO service raw interrupt status.

OUTRIS

Bit 1: Output FIFO service raw interrupt status.

MISR

masked interrupt status register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTMIS
r
INMIS
r
Toggle fields

INMIS

Bit 0: Input FIFO service masked interrupt status.

OUTMIS

Bit 1: Output FIFO service masked interrupt status.

K0LR

key registers

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
b2
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
b2
w
Toggle fields

b2

Bits 0-31: b224.

K0RR

key registers

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
b
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
b
w
Toggle fields

b

Bits 0-31: b192.

K1LR

key registers

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
b1
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
b1
w
Toggle fields

b1

Bits 0-31: b160.

K1RR

key registers

Offset: 0x2c, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
b1
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
b1
w
Toggle fields

b1

Bits 0-31: b128.

K2LR

key registers

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
b
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
b
w
Toggle fields

b

Bits 0-31: b96.

K2RR

key registers

Offset: 0x34, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
b
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
b
w
Toggle fields

b

Bits 0-31: b64.

K3LR

key registers

Offset: 0x38, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
b
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
b
w
Toggle fields

b

Bits 0-31: b32.

K3RR

key registers

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
b
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
b
w
Toggle fields

b

Bits 0-31: b0.

IV0LR

initialization vector registers

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IV
rw
Toggle fields

IV

Bits 0-31: IV31.

IV0RR

initialization vector registers

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IV
rw
Toggle fields

IV

Bits 0-31: IV63.

IV1LR

initialization vector registers

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IV
rw
Toggle fields

IV

Bits 0-31: IV95.

IV1RR

initialization vector registers

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IV
rw
Toggle fields

IV

Bits 0-31: IV127.

CSGCMCCM0R

context swap register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCMCCM0R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCMCCM0R
rw
Toggle fields

CSGCMCCM0R

Bits 0-31: CSGCMCCM0R.

CSGCMCCM1R

context swap register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCMCCM1R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCMCCM1R
rw
Toggle fields

CSGCMCCM1R

Bits 0-31: CSGCMCCM1R.

CSGCMCCM2R

context swap register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCMCCM2R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCMCCM2R
rw
Toggle fields

CSGCMCCM2R

Bits 0-31: CSGCMCCM2R.

CSGCMCCM3R

context swap register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCMCCM3R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCMCCM3R
rw
Toggle fields

CSGCMCCM3R

Bits 0-31: CSGCMCCM3R.

CSGCMCCM4R

context swap register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCMCCM4R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCMCCM4R
rw
Toggle fields

CSGCMCCM4R

Bits 0-31: CSGCMCCM4R.

CSGCMCCM5R

context swap register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCMCCM5R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCMCCM5R
rw
Toggle fields

CSGCMCCM5R

Bits 0-31: CSGCMCCM5R.

CSGCMCCM6R

context swap register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCMCCM6R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCMCCM6R
rw
Toggle fields

CSGCMCCM6R

Bits 0-31: CSGCMCCM6R.

CSGCMCCM7R

context swap register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCMCCM7R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCMCCM7R
rw
Toggle fields

CSGCMCCM7R

Bits 0-31: CSGCMCCM7R.

CSGCM0R

context swap register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCM0R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCM0R
rw
Toggle fields

CSGCM0R

Bits 0-31: CSGCM0R.

CSGCM1R

context swap register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCM1R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCM1R
rw
Toggle fields

CSGCM1R

Bits 0-31: CSGCM1R.

CSGCM2R

context swap register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCM2R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCM2R
rw
Toggle fields

CSGCM2R

Bits 0-31: CSGCM2R.

CSGCM3R

context swap register

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCM3R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCM3R
rw
Toggle fields

CSGCM3R

Bits 0-31: CSGCM3R.

CSGCM4R

context swap register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCM4R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCM4R
rw
Toggle fields

CSGCM4R

Bits 0-31: CSGCM4R.

CSGCM5R

context swap register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCM5R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCM5R
rw
Toggle fields

CSGCM5R

Bits 0-31: CSGCM5R.

CSGCM6R

context swap register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCM6R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCM6R
rw
Toggle fields

CSGCM6R

Bits 0-31: CSGCM6R.

CSGCM7R

context swap register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCM7R
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCM7R
rw
Toggle fields

CSGCM7R

Bits 0-31: CSGCM7R.

DAC1

0x40007400: Digital-to-analog converter

48/48 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SWTRGR
0x8 DHR12R[1]
0xc DHR12L[1]
0x10 DHR8R[1]
0x14 DHR12R[2]
0x18 DHR12L[2]
0x1c DHR8R[2]
0x20 DHR12RD
0x24 DHR12LD
0x28 DHR8RD
0x2c DOR[1]
0x30 DOR[2]
0x34 SR
0x38 CCR
0x3c MCR
0x40 SHSR[1]
0x44 SHSR[2]
0x48 SHHR
0x4c SHRR
Toggle registers

CR

DAC control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEN[2]
rw
DMAUDRIE[2]
rw
DMAEN[2]
rw
MAMP[2]
rw
WAVE[2]
rw
TSEL2
rw
TEN[2]
rw
EN[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CEN[1]
rw
DMAUDRIE[1]
rw
DMAEN[1]
rw
MAMP[1]
rw
WAVE[1]
rw
TSEL1
rw
TEN[1]
rw
EN[1]
rw
Toggle fields

EN[1]

Bit 0: DAC channel1 enable.

Allowed values:
0: Disabled: DAC Channel X disabled
1: Enabled: DAC Channel X enabled

TEN[1]

Bit 1: DAC channel1 trigger enable.

Allowed values:
0: Disabled: DAC Channel X trigger disabled
1: Enabled: DAC Channel X trigger enabled

TSEL1

Bits 2-5: DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled)..

Allowed values:
0: Swtrig: Software trigger
1: Tim1Trgo: Timer 1 TRGO event
2: Tim2Trgo: Timer 2 TRGO event
3: Tim4Trgo: Timer 4 TRGO event
4: Tim5Trgo: Timer 5 TRGO event
5: Tim6Trgo: Timer 6 TRGO event
6: Tim7Trgo: Timer 7 TRGO event
7: Tim8Trgo: Timer 8 TRGO event
8: Tim15Trgo: Timer 15 TRGO event
11: Lptim1Out: LPTIM1 OUT event
12: Lptim2Out: LPTIM2 OUT event
13: Exti9: EXTI line 9
14: Lptim2or3Out: LPTIM2 (DAC1)/ LPTIM3 (DAC2) OUT event

WAVE[1]

Bits 6-7: DAC channel1 noise/triangle wave generation enable.

Allowed values:
0: Disabled: Wave generation disabled
1: Noise: Noise wave generation enabled
2 (+): Triangle: Triangle wave generation enabled

MAMP[1]

Bits 8-11: DAC channel1 mask/amplitude selector.

Allowed values:
0: Amp1: Unmask bit0 of LFSR/ triangle amplitude equal to 1
1: Amp3: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
2: Amp7: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
3: Amp15: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
4: Amp31: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
5: Amp63: Unmask bits[5:0] of LFSR/ triangle amplitude equal 63
6: Amp127: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
7: Amp255: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
8: Amp511: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
9: Amp1023: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
10: Amp2047: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
11 (+): Amp4095: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095

DMAEN[1]

Bit 12: DAC channel1 DMA enable.

Allowed values:
0: Disabled: DAC Channel X DMA mode disabled
1: Enabled: DAC Channel X DMA mode enabled

DMAUDRIE[1]

Bit 13: DAC channel1 DMA Underrun Interrupt enable.

Allowed values:
0: Disabled: DAC channel X DMA Underrun Interrupt disabled
1: Enabled: DAC channel X DMA Underrun Interrupt enabled

CEN[1]

Bit 14: DAC channel1 calibration enable.

Allowed values:
0: Normal: DAC Channel X Normal operating mode
1: Calibration: DAC Channel X calibration mode

EN[2]

Bit 16: DAC channel2 enable.

Allowed values:
0: Disabled: DAC Channel X disabled
1: Enabled: DAC Channel X enabled

TEN[2]

Bit 17: DAC channel2 trigger enable.

Allowed values:
0: Disabled: DAC Channel X trigger disabled
1: Enabled: DAC Channel X trigger enabled

TSEL2

Bits 18-21: DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled)..

Allowed values:
0: Swtrig: Software trigger
1: Tim1Trgo: Timer 1 TRGO event
2: Tim2Trgo: Timer 2 TRGO event
3: Tim4Trgo: Timer 4 TRGO event
4: Tim5Trgo: Timer 5 TRGO event
5: Tim6Trgo: Timer 6 TRGO event
6: Tim7Trgo: Timer 7 TRGO event
7: Tim8Trgo: Timer 8 TRGO event
8: Tim15Trgo: Timer 15 TRGO event
11: Lptim1Out: LPTIM1 OUT event
12: Lptim2Out: LPTIM2 OUT event
13: Exti9: EXTI line 9
14: Lptim2or3Out: LPTIM2 (DAC1)/ LPTIM3 (DAC2) OUT event

WAVE[2]

Bits 22-23: DAC channel2 noise/triangle wave generation enable.

Allowed values:
0: Disabled: Wave generation disabled
1: Noise: Noise wave generation enabled
2 (+): Triangle: Triangle wave generation enabled

MAMP[2]

Bits 24-27: DAC channel2 mask/amplitude selector.

Allowed values:
0: Amp1: Unmask bit0 of LFSR/ triangle amplitude equal to 1
1: Amp3: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
2: Amp7: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
3: Amp15: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
4: Amp31: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
5: Amp63: Unmask bits[5:0] of LFSR/ triangle amplitude equal 63
6: Amp127: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
7: Amp255: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
8: Amp511: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
9: Amp1023: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
10: Amp2047: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
11 (+): Amp4095: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095

DMAEN[2]

Bit 28: DAC channel2 DMA enable.

Allowed values:
0: Disabled: DAC Channel X DMA mode disabled
1: Enabled: DAC Channel X DMA mode enabled

DMAUDRIE[2]

Bit 29: DAC channel2 DMA Underrun Interrupt enable.

Allowed values:
0: Disabled: DAC channel X DMA Underrun Interrupt disabled
1: Enabled: DAC channel X DMA Underrun Interrupt enabled

CEN[2]

Bit 30: DAC channel2 calibration enable.

Allowed values:
0: Normal: DAC Channel X Normal operating mode
1: Calibration: DAC Channel X calibration mode

SWTRGR

DAC software trigger register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWTRIG[2]
w
SWTRIG[1]
w
Toggle fields

SWTRIG[1]

Bit 0: DAC channel1 software trigger.

Allowed values:
0: NoTrigger: No trigger
1: Trigger: Trigger

SWTRIG[2]

Bit 1: DAC channel2 software trigger.

Allowed values:
0: NoTrigger: No trigger
1: Trigger: Trigger

DHR12R[1]

channel1 12-bit right-aligned data holding register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACCDHR
rw
Toggle fields

DACCDHR

Bits 0-11: DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

Allowed values: 0x0-0xfff

DHR12L[1]

channel1 12-bit left aligned data holding register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACCDHR
rw
Toggle fields

DACCDHR

Bits 4-15: DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

Allowed values: 0x0-0xfff

DHR8R[1]

channel1 8-bit right aligned data holding register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACCDHR
rw
Toggle fields

DACCDHR

Bits 0-7: DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1..

Allowed values: 0x0-0xff

DHR12R[2]

channel2 12-bit right-aligned data holding register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACCDHR
rw
Toggle fields

DACCDHR

Bits 0-11: DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

Allowed values: 0x0-0xfff

DHR12L[2]

channel2 12-bit left aligned data holding register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACCDHR
rw
Toggle fields

DACCDHR

Bits 4-15: DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

Allowed values: 0x0-0xfff

DHR8R[2]

channel2 8-bit right aligned data holding register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACCDHR
rw
Toggle fields

DACCDHR

Bits 0-7: DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1..

Allowed values: 0x0-0xff

DHR12RD

Dual DAC 12-bit right-aligned data holding register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACC[2]DHR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC[1]DHR
rw
Toggle fields

DACC[1]DHR

Bits 0-11: DAC channel1 12-bit right-aligned data.

Allowed values: 0x0-0xfff

DACC[2]DHR

Bits 16-27: DAC channel2 12-bit right-aligned data.

Allowed values: 0x0-0xfff

DHR12LD

DUAL DAC 12-bit left aligned data holding register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACC[2]DHR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC[1]DHR
rw
Toggle fields

DACC[1]DHR

Bits 4-15: DAC channel1 12-bit left-aligned data.

Allowed values: 0x0-0xfff

DACC[2]DHR

Bits 20-31: DAC channel2 12-bit left-aligned data.

Allowed values: 0x0-0xfff

DHR8RD

DUAL DAC 8-bit right aligned data holding register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC[2]DHR
rw
DACC[1]DHR
rw
Toggle fields

DACC[1]DHR

Bits 0-7: DAC channel1 8-bit right-aligned data.

Allowed values: 0x0-0xff

DACC[2]DHR

Bits 8-15: DAC channel2 8-bit right-aligned data.

Allowed values: 0x0-0xff

DOR[1]

channel1 data output register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACCDOR
r
Toggle fields

DACCDOR

Bits 0-11: DAC channel1 data output These bits are read-only, they contain data output for DAC channel1..

Allowed values: 0x0-0xfff

DOR[2]

channel2 data output register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACCDOR
r
Toggle fields

DACCDOR

Bits 0-11: DAC channel1 data output These bits are read-only, they contain data output for DAC channel1..

Allowed values: 0x0-0xfff

SR

DAC status register

Offset: 0x34, size: 32, reset: 0x00000000, access: Unspecified

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWST[2]
r
CAL_FLAG[2]
r
DMAUDR[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BWST[1]
r
CAL_FLAG[1]
r
DMAUDR[1]
rw
Toggle fields

DMAUDR[1]

Bit 13: DAC channel1 DMA underrun flag.

Allowed values:
0: NoUnderrun: No DMA underrun error condition occurred for DAC channel x
1: Underrun: DMA underrun error condition occurred for DAC channel x (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)

CAL_FLAG[1]

Bit 14: DAC channel1 calibration offset status.

Allowed values:
0: Lower: Calibration trimming value is lower than the offset correction value
1: Equal_Higher: Calibration trimming value is equal or greater than the offset correction value

BWST[1]

Bit 15: DAC channel1 busy writing sample time flag.

Allowed values:
0: Idle: There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written
1: Busy: There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written

DMAUDR[2]

Bit 29: DAC channel2 DMA underrun flag.

Allowed values:
0: NoUnderrun: No DMA underrun error condition occurred for DAC channel x
1: Underrun: DMA underrun error condition occurred for DAC channel x (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)

CAL_FLAG[2]

Bit 30: DAC channel2 calibration offset status.

Allowed values:
0: Lower: Calibration trimming value is lower than the offset correction value
1: Equal_Higher: Calibration trimming value is equal or greater than the offset correction value

BWST[2]

Bit 31: DAC channel2 busy writing sample time flag.

Allowed values:
0: Idle: There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written
1: Busy: There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written

CCR

DAC calibration control register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTRIM[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OTRIM[1]
rw
Toggle fields

OTRIM[1]

Bits 0-4: DAC channel1 offset trimming value.

Allowed values: 0x0-0x1f

OTRIM[2]

Bits 16-20: DAC channel2 offset trimming value.

Allowed values: 0x0-0x1f

MCR

DAC mode control register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODE[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODE[1]
rw
Toggle fields

MODE[1]

Bits 0-2: DAC channel1 mode.

Allowed values:
0: NormalPinBuffer: Normal mode - DAC channelx is connected to external pin with Buffer enabled
1: NormalPinChipBuffer: Normal mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
2: NormalPinNoBuffer: Normal mode - DAC channelx is connected to external pin with Buffer disabled
3: NormalChipNoBuffer: Normal mode - DAC channelx is connected to on chip peripherals with Buffer disabled
4: SHPinBuffer: S&H mode - DAC channelx is connected to external pin with Buffer enabled
5: SHPinChipBuffer: S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
6: SHPinNoBuffer: S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer disabled
7: SHChipNoBuffer: S&H mode - DAC channelx is connected to on chip peripherals with Buffer disabled

MODE[2]

Bits 16-18: DAC channel2 mode.

Allowed values:
0: NormalPinBuffer: Normal mode - DAC channelx is connected to external pin with Buffer enabled
1: NormalPinChipBuffer: Normal mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
2: NormalPinNoBuffer: Normal mode - DAC channelx is connected to external pin with Buffer disabled
3: NormalChipNoBuffer: Normal mode - DAC channelx is connected to on chip peripherals with Buffer disabled
4: SHPinBuffer: S&H mode - DAC channelx is connected to external pin with Buffer enabled
5: SHPinChipBuffer: S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
6: SHPinNoBuffer: S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer disabled
7: SHChipNoBuffer: S&H mode - DAC channelx is connected to on chip peripherals with Buffer disabled

SHSR[1]

DAC channel1 sample and hold sample time register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSAMPLE
rw
Toggle fields

TSAMPLE

Bits 0-9: DAC Channel 1 sample Time (only valid in sample &amp; hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored..

Allowed values: 0x0-0x3ff

SHSR[2]

DAC channel2 sample and hold sample time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSAMPLE
rw
Toggle fields

TSAMPLE

Bits 0-9: DAC Channel 1 sample Time (only valid in sample &amp; hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored..

Allowed values: 0x0-0x3ff

SHHR

DAC Sample and Hold hold time register

Offset: 0x48, size: 32, reset: 0x00010001, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
THOLD[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
THOLD[1]
rw
Toggle fields

THOLD[1]

Bits 0-9: DAC channel1 hold time (only valid in Sample and hold mode).

Allowed values: 0x0-0x3ff

THOLD[2]

Bits 16-25: DAC channel2 hold time (only valid in Sample and hold mode).

Allowed values: 0x0-0x3ff

SHRR

DAC Sample and Hold refresh time register

Offset: 0x4c, size: 32, reset: 0x00010001, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TREFRESH[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TREFRESH[1]
rw
Toggle fields

TREFRESH[1]

Bits 0-7: DAC channel1 refresh time (only valid in Sample and hold mode).

Allowed values: 0x0-0xff

TREFRESH[2]

Bits 16-23: DAC channel2 refresh time (only valid in Sample and hold mode).

Allowed values: 0x0-0xff

DAC2

0x58003400: Digital-to-analog converter

48/48 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SWTRGR
0x8 DHR12R[1]
0xc DHR12L[1]
0x10 DHR8R[1]
0x14 DHR12R[2]
0x18 DHR12L[2]
0x1c DHR8R[2]
0x20 DHR12RD
0x24 DHR12LD
0x28 DHR8RD
0x2c DOR[1]
0x30 DOR[2]
0x34 SR
0x38 CCR
0x3c MCR
0x40 SHSR[1]
0x44 SHSR[2]
0x48 SHHR
0x4c SHRR
Toggle registers

CR

DAC control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEN[2]
rw
DMAUDRIE[2]
rw
DMAEN[2]
rw
MAMP[2]
rw
WAVE[2]
rw
TSEL2
rw
TEN[2]
rw
EN[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CEN[1]
rw
DMAUDRIE[1]
rw
DMAEN[1]
rw
MAMP[1]
rw
WAVE[1]
rw
TSEL1
rw
TEN[1]
rw
EN[1]
rw
Toggle fields

EN[1]

Bit 0: DAC channel1 enable.

Allowed values:
0: Disabled: DAC Channel X disabled
1: Enabled: DAC Channel X enabled

TEN[1]

Bit 1: DAC channel1 trigger enable.

Allowed values:
0: Disabled: DAC Channel X trigger disabled
1: Enabled: DAC Channel X trigger enabled

TSEL1

Bits 2-5: DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled)..

Allowed values:
0: Swtrig: Software trigger
1: Tim1Trgo: Timer 1 TRGO event
2: Tim2Trgo: Timer 2 TRGO event
3: Tim4Trgo: Timer 4 TRGO event
4: Tim5Trgo: Timer 5 TRGO event
5: Tim6Trgo: Timer 6 TRGO event
6: Tim7Trgo: Timer 7 TRGO event
7: Tim8Trgo: Timer 8 TRGO event
8: Tim15Trgo: Timer 15 TRGO event
11: Lptim1Out: LPTIM1 OUT event
12: Lptim2Out: LPTIM2 OUT event
13: Exti9: EXTI line 9
14: Lptim2or3Out: LPTIM2 (DAC1)/ LPTIM3 (DAC2) OUT event

WAVE[1]

Bits 6-7: DAC channel1 noise/triangle wave generation enable.

Allowed values:
0: Disabled: Wave generation disabled
1: Noise: Noise wave generation enabled
2 (+): Triangle: Triangle wave generation enabled

MAMP[1]

Bits 8-11: DAC channel1 mask/amplitude selector.

Allowed values:
0: Amp1: Unmask bit0 of LFSR/ triangle amplitude equal to 1
1: Amp3: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
2: Amp7: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
3: Amp15: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
4: Amp31: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
5: Amp63: Unmask bits[5:0] of LFSR/ triangle amplitude equal 63
6: Amp127: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
7: Amp255: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
8: Amp511: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
9: Amp1023: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
10: Amp2047: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
11 (+): Amp4095: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095

DMAEN[1]

Bit 12: DAC channel1 DMA enable.

Allowed values:
0: Disabled: DAC Channel X DMA mode disabled
1: Enabled: DAC Channel X DMA mode enabled

DMAUDRIE[1]

Bit 13: DAC channel1 DMA Underrun Interrupt enable.

Allowed values:
0: Disabled: DAC channel X DMA Underrun Interrupt disabled
1: Enabled: DAC channel X DMA Underrun Interrupt enabled

CEN[1]

Bit 14: DAC channel1 calibration enable.

Allowed values:
0: Normal: DAC Channel X Normal operating mode
1: Calibration: DAC Channel X calibration mode

EN[2]

Bit 16: DAC channel2 enable.

Allowed values:
0: Disabled: DAC Channel X disabled
1: Enabled: DAC Channel X enabled

TEN[2]

Bit 17: DAC channel2 trigger enable.

Allowed values:
0: Disabled: DAC Channel X trigger disabled
1: Enabled: DAC Channel X trigger enabled

TSEL2

Bits 18-21: DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled)..

Allowed values:
0: Swtrig: Software trigger
1: Tim1Trgo: Timer 1 TRGO event
2: Tim2Trgo: Timer 2 TRGO event
3: Tim4Trgo: Timer 4 TRGO event
4: Tim5Trgo: Timer 5 TRGO event
5: Tim6Trgo: Timer 6 TRGO event
6: Tim7Trgo: Timer 7 TRGO event
7: Tim8Trgo: Timer 8 TRGO event
8: Tim15Trgo: Timer 15 TRGO event
11: Lptim1Out: LPTIM1 OUT event
12: Lptim2Out: LPTIM2 OUT event
13: Exti9: EXTI line 9
14: Lptim2or3Out: LPTIM2 (DAC1)/ LPTIM3 (DAC2) OUT event

WAVE[2]

Bits 22-23: DAC channel2 noise/triangle wave generation enable.

Allowed values:
0: Disabled: Wave generation disabled
1: Noise: Noise wave generation enabled
2 (+): Triangle: Triangle wave generation enabled

MAMP[2]

Bits 24-27: DAC channel2 mask/amplitude selector.

Allowed values:
0: Amp1: Unmask bit0 of LFSR/ triangle amplitude equal to 1
1: Amp3: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
2: Amp7: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
3: Amp15: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
4: Amp31: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
5: Amp63: Unmask bits[5:0] of LFSR/ triangle amplitude equal 63
6: Amp127: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
7: Amp255: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
8: Amp511: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
9: Amp1023: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
10: Amp2047: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
11 (+): Amp4095: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095

DMAEN[2]

Bit 28: DAC channel2 DMA enable.

Allowed values:
0: Disabled: DAC Channel X DMA mode disabled
1: Enabled: DAC Channel X DMA mode enabled

DMAUDRIE[2]

Bit 29: DAC channel2 DMA Underrun Interrupt enable.

Allowed values:
0: Disabled: DAC channel X DMA Underrun Interrupt disabled
1: Enabled: DAC channel X DMA Underrun Interrupt enabled

CEN[2]

Bit 30: DAC channel2 calibration enable.

Allowed values:
0: Normal: DAC Channel X Normal operating mode
1: Calibration: DAC Channel X calibration mode

SWTRGR

DAC software trigger register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWTRIG[2]
w
SWTRIG[1]
w
Toggle fields

SWTRIG[1]

Bit 0: DAC channel1 software trigger.

Allowed values:
0: NoTrigger: No trigger
1: Trigger: Trigger

SWTRIG[2]

Bit 1: DAC channel2 software trigger.

Allowed values:
0: NoTrigger: No trigger
1: Trigger: Trigger

DHR12R[1]

channel1 12-bit right-aligned data holding register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACCDHR
rw
Toggle fields

DACCDHR

Bits 0-11: DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

Allowed values: 0x0-0xfff

DHR12L[1]

channel1 12-bit left aligned data holding register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACCDHR
rw
Toggle fields

DACCDHR

Bits 4-15: DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

Allowed values: 0x0-0xfff

DHR8R[1]

channel1 8-bit right aligned data holding register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACCDHR
rw
Toggle fields

DACCDHR

Bits 0-7: DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1..

Allowed values: 0x0-0xff

DHR12R[2]

channel2 12-bit right-aligned data holding register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACCDHR
rw
Toggle fields

DACCDHR

Bits 0-11: DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

Allowed values: 0x0-0xfff

DHR12L[2]

channel2 12-bit left aligned data holding register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACCDHR
rw
Toggle fields

DACCDHR

Bits 4-15: DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

Allowed values: 0x0-0xfff

DHR8R[2]

channel2 8-bit right aligned data holding register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACCDHR
rw
Toggle fields

DACCDHR

Bits 0-7: DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1..

Allowed values: 0x0-0xff

DHR12RD

Dual DAC 12-bit right-aligned data holding register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACC[2]DHR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC[1]DHR
rw
Toggle fields

DACC[1]DHR

Bits 0-11: DAC channel1 12-bit right-aligned data.

Allowed values: 0x0-0xfff

DACC[2]DHR

Bits 16-27: DAC channel2 12-bit right-aligned data.

Allowed values: 0x0-0xfff

DHR12LD

DUAL DAC 12-bit left aligned data holding register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACC[2]DHR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC[1]DHR
rw
Toggle fields

DACC[1]DHR

Bits 4-15: DAC channel1 12-bit left-aligned data.

Allowed values: 0x0-0xfff

DACC[2]DHR

Bits 20-31: DAC channel2 12-bit left-aligned data.

Allowed values: 0x0-0xfff

DHR8RD

DUAL DAC 8-bit right aligned data holding register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC[2]DHR
rw
DACC[1]DHR
rw
Toggle fields

DACC[1]DHR

Bits 0-7: DAC channel1 8-bit right-aligned data.

Allowed values: 0x0-0xff

DACC[2]DHR

Bits 8-15: DAC channel2 8-bit right-aligned data.

Allowed values: 0x0-0xff

DOR[1]

channel1 data output register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACCDOR
r
Toggle fields

DACCDOR

Bits 0-11: DAC channel1 data output These bits are read-only, they contain data output for DAC channel1..

Allowed values: 0x0-0xfff

DOR[2]

channel2 data output register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACCDOR
r
Toggle fields

DACCDOR

Bits 0-11: DAC channel1 data output These bits are read-only, they contain data output for DAC channel1..

Allowed values: 0x0-0xfff

SR

DAC status register

Offset: 0x34, size: 32, reset: 0x00000000, access: Unspecified

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWST[2]
r
CAL_FLAG[2]
r
DMAUDR[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BWST[1]
r
CAL_FLAG[1]
r
DMAUDR[1]
rw
Toggle fields

DMAUDR[1]

Bit 13: DAC channel1 DMA underrun flag.

Allowed values:
0: NoUnderrun: No DMA underrun error condition occurred for DAC channel x
1: Underrun: DMA underrun error condition occurred for DAC channel x (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)

CAL_FLAG[1]

Bit 14: DAC channel1 calibration offset status.

Allowed values:
0: Lower: Calibration trimming value is lower than the offset correction value
1: Equal_Higher: Calibration trimming value is equal or greater than the offset correction value

BWST[1]

Bit 15: DAC channel1 busy writing sample time flag.

Allowed values:
0: Idle: There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written
1: Busy: There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written

DMAUDR[2]

Bit 29: DAC channel2 DMA underrun flag.

Allowed values:
0: NoUnderrun: No DMA underrun error condition occurred for DAC channel x
1: Underrun: DMA underrun error condition occurred for DAC channel x (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)

CAL_FLAG[2]

Bit 30: DAC channel2 calibration offset status.

Allowed values:
0: Lower: Calibration trimming value is lower than the offset correction value
1: Equal_Higher: Calibration trimming value is equal or greater than the offset correction value

BWST[2]

Bit 31: DAC channel2 busy writing sample time flag.

Allowed values:
0: Idle: There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written
1: Busy: There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written

CCR

DAC calibration control register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTRIM[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OTRIM[1]
rw
Toggle fields

OTRIM[1]

Bits 0-4: DAC channel1 offset trimming value.

Allowed values: 0x0-0x1f

OTRIM[2]

Bits 16-20: DAC channel2 offset trimming value.

Allowed values: 0x0-0x1f

MCR

DAC mode control register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODE[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODE[1]
rw
Toggle fields

MODE[1]

Bits 0-2: DAC channel1 mode.

Allowed values:
0: NormalPinBuffer: Normal mode - DAC channelx is connected to external pin with Buffer enabled
1: NormalPinChipBuffer: Normal mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
2: NormalPinNoBuffer: Normal mode - DAC channelx is connected to external pin with Buffer disabled
3: NormalChipNoBuffer: Normal mode - DAC channelx is connected to on chip peripherals with Buffer disabled
4: SHPinBuffer: S&H mode - DAC channelx is connected to external pin with Buffer enabled
5: SHPinChipBuffer: S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
6: SHPinNoBuffer: S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer disabled
7: SHChipNoBuffer: S&H mode - DAC channelx is connected to on chip peripherals with Buffer disabled

MODE[2]

Bits 16-18: DAC channel2 mode.

Allowed values:
0: NormalPinBuffer: Normal mode - DAC channelx is connected to external pin with Buffer enabled
1: NormalPinChipBuffer: Normal mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
2: NormalPinNoBuffer: Normal mode - DAC channelx is connected to external pin with Buffer disabled
3: NormalChipNoBuffer: Normal mode - DAC channelx is connected to on chip peripherals with Buffer disabled
4: SHPinBuffer: S&H mode - DAC channelx is connected to external pin with Buffer enabled
5: SHPinChipBuffer: S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
6: SHPinNoBuffer: S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer disabled
7: SHChipNoBuffer: S&H mode - DAC channelx is connected to on chip peripherals with Buffer disabled

SHSR[1]

DAC channel1 sample and hold sample time register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSAMPLE
rw
Toggle fields

TSAMPLE

Bits 0-9: DAC Channel 1 sample Time (only valid in sample &amp; hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored..

Allowed values: 0x0-0x3ff

SHSR[2]

DAC channel2 sample and hold sample time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSAMPLE
rw
Toggle fields

TSAMPLE

Bits 0-9: DAC Channel 1 sample Time (only valid in sample &amp; hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored..

Allowed values: 0x0-0x3ff

SHHR

DAC Sample and Hold hold time register

Offset: 0x48, size: 32, reset: 0x00010001, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
THOLD[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
THOLD[1]
rw
Toggle fields

THOLD[1]

Bits 0-9: DAC channel1 hold time (only valid in Sample and hold mode).

Allowed values: 0x0-0x3ff

THOLD[2]

Bits 16-25: DAC channel2 hold time (only valid in Sample and hold mode).

Allowed values: 0x0-0x3ff

SHRR

DAC Sample and Hold refresh time register

Offset: 0x4c, size: 32, reset: 0x00010001, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TREFRESH[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TREFRESH[1]
rw
Toggle fields

TREFRESH[1]

Bits 0-7: DAC channel1 refresh time (only valid in Sample and hold mode).

Allowed values: 0x0-0xff

TREFRESH[2]

Bits 16-23: DAC channel2 refresh time (only valid in Sample and hold mode).

Allowed values: 0x0-0xff

DBGMCU

0x5c001000: Microcontroller Debug Unit

2/35 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 IDC
0x4 CR
0x34 APB3FZ1
0x3c APB1LFZ1
0x4c APB2FZ1
0x54 APB4FZ1
Toggle registers

IDC

DBGMCU Identity Code Register

Offset: 0x0, size: 32, reset: 0x10006480, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REV_ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEV_ID
r
Toggle fields

DEV_ID

Bits 0-11: Device ID.

REV_ID

Bits 16-31: Revision.

CR

DBGMCU Configuration Register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TRGOEN
rw
SRDDBGCKEN
rw
CDDBGCKEN
rw
TRACECLKEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBGSTBY_SRD
rw
DBGSTOP_SRD
rw
DBGSTBY_CD
rw
DBGSTOP_CD
rw
DBGSLEEP_CD
rw
Toggle fields

DBGSLEEP_CD

Bit 0: Allow D1 domain debug in Sleep mode.

DBGSTOP_CD

Bit 1: Allow D1 domain debug in Stop mode.

DBGSTBY_CD

Bit 2: Allow D1 domain debug in Standby mode.

DBGSTOP_SRD

Bit 7: debug in SmartRun domain Stop mode.

DBGSTBY_SRD

Bit 8: debug in SmartRun domain Standby mode.

TRACECLKEN

Bit 20: Trace port clock enable.

CDDBGCKEN

Bit 21: CPU domain debug clock enable.

SRDDBGCKEN

Bit 22: SmartRun domain debug clock enable.

TRGOEN

Bit 28: External trigger output enable.

APB3FZ1

DBGMCU APB3 peripheral freeze register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WWDG
rw
Toggle fields

WWDG

Bit 6: WWDG stop in debug.

APB1LFZ1

DBGMCU APB1L peripheral freeze register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
I2C3
rw
I2C2
rw
I2C1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPTIM1
rw
TIM14
rw
TIM13
rw
TIM12
rw
TIM7
rw
TIM6
rw
TIM5
rw
TIM4
rw
TIM3
rw
TIM2
rw
Toggle fields

TIM2

Bit 0: TIM2 stop in debug.

TIM3

Bit 1: TIM3 stop in debug.

TIM4

Bit 2: TIM4 stop in debug.

TIM5

Bit 3: TIM5 stop in debug.

TIM6

Bit 4: TIM6 stop in debug.

TIM7

Bit 5: TIM7 stop in debug.

TIM12

Bit 6: TIM12 stop in debug.

TIM13

Bit 7: TIM13 stop in debug.

TIM14

Bit 8: TIM14 stop in debug.

LPTIM1

Bit 9: LPTIM1 stop in debug.

I2C1

Bit 21: I2C1 SMBUS timeout stop in debug.

I2C2

Bit 22: I2C2 SMBUS timeout stop in debug.

I2C3

Bit 23: I2C3 SMBUS timeout stop in debug.

APB2FZ1

DBGMCU APB2 peripheral freeze register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIM17
rw
TIM16
rw
TIM15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIM8
rw
TIM1
rw
Toggle fields

TIM1

Bit 0: TIM1 stop in debug.

TIM8

Bit 1: TIM8 stop in debug.

TIM15

Bit 16: TIM15 stop in debug.

TIM16

Bit 17: TIM16 stop in debug.

TIM17

Bit 18: TIM17 stop in debug.

APB4FZ1

DBGMCU APB4 peripheral freeze register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDGLSCD
rw
RTC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPTIM3
rw
LPTIM2
rw
I2C4
rw
Toggle fields

I2C4

Bit 7: I2C4 SMBUS timeout stop in debug.

LPTIM2

Bit 9: LPTIM2 stop in debug.

LPTIM3

Bit 10: LPTIM3 stop in debug.

RTC

Bit 16: RTC stop in debug.

WDGLSCD

Bit 18: LS watchdog for CPU domain stop in debug.

DCMI

0x48020000: Digital camera interface

17/54 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SR
0x8 RIS
0xc IER
0x10 MIS
0x14 ICR
0x18 ESCR
0x1c ESUR
0x20 CWSTRT
0x24 CWSIZE
0x28 DR
Toggle registers

CR

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OELS
rw
LSM
rw
OEBS
rw
BSM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENABLE
rw
EDM
rw
FCRC
rw
VSPOL
rw
HSPOL
rw
PCKPOL
rw
ESS
rw
JPEG
rw
CROP
rw
CM
rw
CAPTURE
rw
Toggle fields

CAPTURE

Bit 0: Capture enable.

CM

Bit 1: Capture mode.

CROP

Bit 2: Crop feature.

JPEG

Bit 3: JPEG format.

ESS

Bit 4: Embedded synchronization select.

PCKPOL

Bit 5: Pixel clock polarity.

HSPOL

Bit 6: Horizontal synchronization polarity.

VSPOL

Bit 7: Vertical synchronization polarity.

FCRC

Bits 8-9: Frame capture rate control.

EDM

Bits 10-11: Extended data mode.

ENABLE

Bit 14: DCMI enable.

BSM

Bits 16-17: Byte Select mode.

OEBS

Bit 18: Odd/Even Byte Select (Byte Select Start).

LSM

Bit 19: Line Select mode.

OELS

Bit 20: Odd/Even Line Select (Line Select Start).

SR

status register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FNE
r
VSYNC
r
HSYNC
r
Toggle fields

HSYNC

Bit 0: HSYNC.

VSYNC

Bit 1: VSYNC.

FNE

Bit 2: FIFO not empty.

RIS

raw interrupt status register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINE_RIS
r
VSYNC_RIS
r
ERR_RIS
r
OVR_RIS
r
FRAME_RIS
r
Toggle fields

FRAME_RIS

Bit 0: Capture complete raw interrupt status.

OVR_RIS

Bit 1: Overrun raw interrupt status.

ERR_RIS

Bit 2: Synchronization error raw interrupt status.

VSYNC_RIS

Bit 3: VSYNC raw interrupt status.

LINE_RIS

Bit 4: Line raw interrupt status.

IER

interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINE_IE
rw
VSYNC_IE
rw
ERR_IE
rw
OVR_IE
rw
FRAME_IE
rw
Toggle fields

FRAME_IE

Bit 0: Capture complete interrupt enable.

OVR_IE

Bit 1: Overrun interrupt enable.

ERR_IE

Bit 2: Synchronization error interrupt enable.

VSYNC_IE

Bit 3: VSYNC interrupt enable.

LINE_IE

Bit 4: Line interrupt enable.

MIS

masked interrupt status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINE_MIS
r
VSYNC_MIS
r
ERR_MIS
r
OVR_MIS
r
FRAME_MIS
r
Toggle fields

FRAME_MIS

Bit 0: Capture complete masked interrupt status.

OVR_MIS

Bit 1: Overrun masked interrupt status.

ERR_MIS

Bit 2: Synchronization error masked interrupt status.

VSYNC_MIS

Bit 3: VSYNC masked interrupt status.

LINE_MIS

Bit 4: Line masked interrupt status.

ICR

interrupt clear register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINE_ISC
w
VSYNC_ISC
w
ERR_ISC
w
OVR_ISC
w
FRAME_ISC
w
Toggle fields

FRAME_ISC

Bit 0: Capture complete interrupt status clear.

OVR_ISC

Bit 1: Overrun interrupt status clear.

ERR_ISC

Bit 2: Synchronization error interrupt status clear.

VSYNC_ISC

Bit 3: Vertical synch interrupt status clear.

LINE_ISC

Bit 4: line interrupt status clear.

ESCR

embedded synchronization code register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FEC
rw
LEC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSC
rw
FSC
rw
Toggle fields

FSC

Bits 0-7: Frame start delimiter code.

LSC

Bits 8-15: Line start delimiter code.

LEC

Bits 16-23: Line end delimiter code.

FEC

Bits 24-31: Frame end delimiter code.

ESUR

embedded synchronization unmask register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FEU
rw
LEU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSU
rw
FSU
rw
Toggle fields

FSU

Bits 0-7: Frame start delimiter unmask.

LSU

Bits 8-15: Line start delimiter unmask.

LEU

Bits 16-23: Line end delimiter unmask.

FEU

Bits 24-31: Frame end delimiter unmask.

CWSTRT

crop window start

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HOFFCNT
rw
Toggle fields

HOFFCNT

Bits 0-13: Horizontal offset count.

VST

Bits 16-28: Vertical start line count.

CWSIZE

crop window size

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VLINE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAPCNT
rw
Toggle fields

CAPCNT

Bits 0-13: Capture count.

VLINE

Bits 16-29: Vertical line count.

DR

data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Byte3
r
Byte2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Byte1
r
Byte0
r
Toggle fields

Byte0

Bits 0-7: Data byte 0.

Byte1

Bits 8-15: Data byte 1.

Byte2

Bits 16-23: Data byte 2.

Byte3

Bits 24-31: Data byte 3.

Delay_Block_OCTOSPI1

0x52006000: DELAY_Block_SDMMC1

0/6 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 CFGR
Toggle registers

CR

DLYB control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEN
rw
DEN
rw
Toggle fields

DEN

Bit 0: Delay block enable bit.

SEN

Bit 1: Sampler length enable bit.

CFGR

DLYB configuration register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LNGF
rw
LNG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UNIT
rw
SEL
rw
Toggle fields

SEL

Bits 0-3: Select the phase for the Output clock.

UNIT

Bits 8-14: Delay Defines the delay of a Unit delay cell.

LNG

Bits 16-27: Delay line length value.

LNGF

Bit 31: Length valid flag.

Delay_Block_OCTOSPI2

0x5200b000: DELAY_Block_SDMMC1

0/6 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 CFGR
Toggle registers

CR

DLYB control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEN
rw
DEN
rw
Toggle fields

DEN

Bit 0: Delay block enable bit.

SEN

Bit 1: Sampler length enable bit.

CFGR

DLYB configuration register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LNGF
rw
LNG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UNIT
rw
SEL
rw
Toggle fields

SEL

Bits 0-3: Select the phase for the Output clock.

UNIT

Bits 8-14: Delay Defines the delay of a Unit delay cell.

LNG

Bits 16-27: Delay line length value.

LNGF

Bit 31: Length valid flag.

DELAY_Block_SDMMC1

0x52008000: DELAY_Block_SDMMC1

0/6 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 CFGR
Toggle registers

CR

DLYB control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEN
rw
DEN
rw
Toggle fields

DEN

Bit 0: Delay block enable bit.

SEN

Bit 1: Sampler length enable bit.

CFGR

DLYB configuration register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LNGF
rw
LNG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UNIT
rw
SEL
rw
Toggle fields

SEL

Bits 0-3: Select the phase for the Output clock.

UNIT

Bits 8-14: Delay Defines the delay of a Unit delay cell.

LNG

Bits 16-27: Delay line length value.

LNGF

Bit 31: Length valid flag.

DELAY_Block_SDMMC2

0x48022800: DELAY_Block_SDMMC1

0/6 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 CFGR
Toggle registers

CR

DLYB control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEN
rw
DEN
rw
Toggle fields

DEN

Bit 0: Delay block enable bit.

SEN

Bit 1: Sampler length enable bit.

CFGR

DLYB configuration register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LNGF
rw
LNG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UNIT
rw
SEL
rw
Toggle fields

SEL

Bits 0-3: Select the phase for the Output clock.

UNIT

Bits 8-14: Delay Defines the delay of a Unit delay cell.

LNG

Bits 16-27: Delay line length value.

LNGF

Bit 31: Length valid flag.

DFSDM1

0x40017800: Digital filter for sigma delta modulators

168/632 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CFGR1 [0]
0x4 CFGR2 [0]
0x8 AWSCDR [0]
0xc WDATR [0]
0x10 DATINR [0]
0x14 DLYR [0]
0x20 CFGR1 [1]
0x24 CFGR2 [1]
0x28 AWSCDR [1]
0x2c WDATR [1]
0x30 DATINR [1]
0x34 DLYR [1]
0x40 CFGR1 [2]
0x44 CFGR2 [2]
0x48 AWSCDR [2]
0x4c WDATR [2]
0x50 DATINR [2]
0x54 DLYR [2]
0x60 CFGR1 [3]
0x64 CFGR2 [3]
0x68 AWSCDR [3]
0x6c WDATR [3]
0x70 DATINR [3]
0x74 DLYR [3]
0x80 CFGR1 [4]
0x84 CFGR2 [4]
0x88 AWSCDR [4]
0x8c WDATR [4]
0x90 DATINR [4]
0x94 DLYR [4]
0xa0 CFGR1 [5]
0xa4 CFGR2 [5]
0xa8 AWSCDR [5]
0xac WDATR [5]
0xb0 DATINR [5]
0xb4 DLYR [5]
0xc0 CFGR1 [6]
0xc4 CFGR2 [6]
0xc8 AWSCDR [6]
0xcc WDATR [6]
0xd0 DATINR [6]
0xd4 DLYR [6]
0xe0 CFGR1 [7]
0xe4 CFGR2 [7]
0xe8 AWSCDR [7]
0xec WDATR [7]
0xf0 DATINR [7]
0xf4 DLYR [7]
0x100 CR1 [0]
0x104 CR2 [0]
0x108 ISR [0]
0x10c ICR [0]
0x110 JCHGR [0]
0x114 FCR [0]
0x118 JDATAR [0]
0x11c RDATAR [0]
0x120 AWHTR [0]
0x124 AWLTR [0]
0x128 AWSR [0]
0x12c AWCFR [0]
0x130 EXMAX [0]
0x134 EXMIN [0]
0x138 CNVTIMR [0]
0x180 CR1 [1]
0x184 CR2 [1]
0x188 ISR [1]
0x18c ICR [1]
0x190 JCHGR [1]
0x194 FCR [1]
0x198 JDATAR [1]
0x19c RDATAR [1]
0x1a0 AWHTR [1]
0x1a4 AWLTR [1]
0x1a8 AWSR [1]
0x1ac AWCFR [1]
0x1b0 EXMAX [1]
0x1b4 EXMIN [1]
0x1b8 CNVTIMR [1]
0x200 CR1 [2]
0x204 CR2 [2]
0x208 ISR [2]
0x20c ICR [2]
0x210 JCHGR [2]
0x214 FCR [2]
0x218 JDATAR [2]
0x21c RDATAR [2]
0x220 AWHTR [2]
0x224 AWLTR [2]
0x228 AWSR [2]
0x22c AWCFR [2]
0x230 EXMAX [2]
0x234 EXMIN [2]
0x238 CNVTIMR [2]
0x280 CR1 [3]
0x284 CR2 [3]
0x288 ISR [3]
0x28c ICR [3]
0x290 JCHGR [3]
0x294 FCR [3]
0x298 JDATAR [3]
0x29c RDATAR [3]
0x2a0 AWHTR [3]
0x2a4 AWLTR [3]
0x2a8 AWSR [3]
0x2ac AWCFR [3]
0x2b0 EXMAX [3]
0x2b4 EXMIN [3]
0x2b8 CNVTIMR [3]
0x300 CR1 [4]
0x304 CR2 [4]
0x308 ISR [4]
0x30c ICR [4]
0x310 JCHGR [4]
0x314 FCR [4]
0x318 JDATAR [4]
0x31c RDATAR [4]
0x320 AWHTR [4]
0x324 AWLTR [4]
0x328 AWSR [4]
0x32c AWCFR [4]
0x330 EXMAX [4]
0x334 EXMIN [4]
0x338 CNVTIMR [4]
0x380 CR1 [5]
0x384 CR2 [5]
0x388 ISR [5]
0x38c ICR [5]
0x390 JCHGR [5]
0x394 FCR [5]
0x398 JDATAR [5]
0x39c RDATAR [5]
0x3a0 AWHTR [5]
0x3a4 AWLTR [5]
0x3a8 AWSR [5]
0x3ac AWCFR [5]
0x3b0 EXMAX [5]
0x3b4 EXMIN [5]
0x3b8 CNVTIMR [5]
0x400 CR1 [6]
0x404 CR2 [6]
0x408 ISR [6]
0x40c ICR [6]
0x410 JCHGR [6]
0x414 FCR [6]
0x418 JDATAR [6]
0x41c RDATAR [6]
0x420 AWHTR [6]
0x424 AWLTR [6]
0x428 AWSR [6]
0x42c AWCFR [6]
0x430 EXMAX [6]
0x434 EXMIN [6]
0x438 CNVTIMR [6]
0x480 CR1 [7]
0x484 CR2 [7]
0x488 ISR [7]
0x48c ICR [7]
0x490 JCHGR [7]
0x494 FCR [7]
0x498 JDATAR [7]
0x49c RDATAR [7]
0x4a0 AWHTR [7]
0x4a4 AWLTR [7]
0x4a8 AWSR [7]
0x4ac AWCFR [7]
0x4b0 EXMAX [7]
0x4b4 EXMIN [7]
0x4b8 CNVTIMR [7]
Toggle registers

CFGR1 [0]

DFSDM channel 0 configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw
CKOUTSRC
rw
CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw
DATMPX
rw
CHINSEL
rw
CHEN
rw
CKABEN
rw
SCDEN
rw
SPICKSEL
rw
SITP
rw
Toggle fields

SITP

Bits 0-1: Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register)..

SPICKSEL

Bits 2-3: SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

SCDEN

Bit 5: Short-circuit detector enable on channel y.

CKABEN

Bit 6: Clock absence detector enable on channel y.

CHEN

Bit 7: Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting..

CHINSEL

Bit 8: Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

DATMPX

Bits 12-13: Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

DATPACK

Bits 14-15: Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

CKOUTDIV

Bits 16-23: Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -.

CKOUTSRC

Bit 30: Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0).

DFSDMEN

Bit 31: Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0).

CFGR2 [0]

DFSDM channel 0 configuration register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right.

OFFSET

Bits 8-31: 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software..

AWSCDR [0]

DFSDM channel 0 analog watchdog and short-circuit detector register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw
AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw
SCDT
rw
Toggle fields

SCDT

Bits 0-7: short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel..

BKSCD

Bits 12-15: Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y.

AWFOSR

Bits 16-20: Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is.

AWFORD

Bits 22-23: Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

WDATR [0]

DFSDM channel 0 watchdog filter data register

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
r
Toggle fields

WDATA

Bits 0-15: Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3)..

DATINR [0]

DFSDM channel 0 data input register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format..

INDAT1

Bits 16-31: Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format..

DLYR [0]

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied.

CFGR1 [1]

DFSDM channel 0 configuration register

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw
CKOUTSRC
rw
CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw
DATMPX
rw
CHINSEL
rw
CHEN
rw
CKABEN
rw
SCDEN
rw
SPICKSEL
rw
SITP
rw
Toggle fields

SITP

Bits 0-1: Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register)..

SPICKSEL

Bits 2-3: SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

SCDEN

Bit 5: Short-circuit detector enable on channel y.

CKABEN

Bit 6: Clock absence detector enable on channel y.

CHEN

Bit 7: Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting..

CHINSEL

Bit 8: Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

DATMPX

Bits 12-13: Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

DATPACK

Bits 14-15: Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

CKOUTDIV

Bits 16-23: Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -.

CKOUTSRC

Bit 30: Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0).

DFSDMEN

Bit 31: Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0).

CFGR2 [1]

DFSDM channel 0 configuration register

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right.

OFFSET

Bits 8-31: 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software..

AWSCDR [1]

DFSDM channel 0 analog watchdog and short-circuit detector register

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw
AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw
SCDT
rw
Toggle fields

SCDT

Bits 0-7: short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel..

BKSCD

Bits 12-15: Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y.

AWFOSR

Bits 16-20: Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is.

AWFORD

Bits 22-23: Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

WDATR [1]

DFSDM channel 0 watchdog filter data register

Offset: 0x2c, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
r
Toggle fields

WDATA

Bits 0-15: Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3)..

DATINR [1]

DFSDM channel 0 data input register

Offset: 0x30, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format..

INDAT1

Bits 16-31: Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format..

DLYR [1]

Offset: 0x34, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied.

CFGR1 [2]

DFSDM channel 0 configuration register

Offset: 0x40, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw
CKOUTSRC
rw
CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw
DATMPX
rw
CHINSEL
rw
CHEN
rw
CKABEN
rw
SCDEN
rw
SPICKSEL
rw
SITP
rw
Toggle fields

SITP

Bits 0-1: Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register)..

SPICKSEL

Bits 2-3: SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

SCDEN

Bit 5: Short-circuit detector enable on channel y.

CKABEN

Bit 6: Clock absence detector enable on channel y.

CHEN

Bit 7: Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting..

CHINSEL

Bit 8: Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

DATMPX

Bits 12-13: Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

DATPACK

Bits 14-15: Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

CKOUTDIV

Bits 16-23: Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -.

CKOUTSRC

Bit 30: Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0).

DFSDMEN

Bit 31: Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0).

CFGR2 [2]

DFSDM channel 0 configuration register

Offset: 0x44, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right.

OFFSET

Bits 8-31: 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software..

AWSCDR [2]

DFSDM channel 0 analog watchdog and short-circuit detector register

Offset: 0x48, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw
AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw
SCDT
rw
Toggle fields

SCDT

Bits 0-7: short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel..

BKSCD

Bits 12-15: Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y.

AWFOSR

Bits 16-20: Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is.

AWFORD

Bits 22-23: Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

WDATR [2]

DFSDM channel 0 watchdog filter data register

Offset: 0x4c, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
r
Toggle fields

WDATA

Bits 0-15: Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3)..

DATINR [2]

DFSDM channel 0 data input register

Offset: 0x50, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format..

INDAT1

Bits 16-31: Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format..

DLYR [2]

Offset: 0x54, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied.

CFGR1 [3]

DFSDM channel 0 configuration register

Offset: 0x60, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw
CKOUTSRC
rw
CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw
DATMPX
rw
CHINSEL
rw
CHEN
rw
CKABEN
rw
SCDEN
rw
SPICKSEL
rw
SITP
rw
Toggle fields

SITP

Bits 0-1: Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register)..

SPICKSEL

Bits 2-3: SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

SCDEN

Bit 5: Short-circuit detector enable on channel y.

CKABEN

Bit 6: Clock absence detector enable on channel y.

CHEN

Bit 7: Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting..

CHINSEL

Bit 8: Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

DATMPX

Bits 12-13: Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

DATPACK

Bits 14-15: Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

CKOUTDIV

Bits 16-23: Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -.

CKOUTSRC

Bit 30: Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0).

DFSDMEN

Bit 31: Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0).

CFGR2 [3]

DFSDM channel 0 configuration register

Offset: 0x64, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right.

OFFSET

Bits 8-31: 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software..

AWSCDR [3]

DFSDM channel 0 analog watchdog and short-circuit detector register

Offset: 0x68, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw
AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw
SCDT
rw
Toggle fields

SCDT

Bits 0-7: short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel..

BKSCD

Bits 12-15: Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y.

AWFOSR

Bits 16-20: Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is.

AWFORD

Bits 22-23: Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

WDATR [3]

DFSDM channel 0 watchdog filter data register

Offset: 0x6c, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
r
Toggle fields

WDATA

Bits 0-15: Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3)..

DATINR [3]

DFSDM channel 0 data input register

Offset: 0x70, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format..

INDAT1

Bits 16-31: Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format..

DLYR [3]

Offset: 0x74, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied.

CFGR1 [4]

DFSDM channel 0 configuration register

Offset: 0x80, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw
CKOUTSRC
rw
CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw
DATMPX
rw
CHINSEL
rw
CHEN
rw
CKABEN
rw
SCDEN
rw
SPICKSEL
rw
SITP
rw
Toggle fields

SITP

Bits 0-1: Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register)..

SPICKSEL

Bits 2-3: SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

SCDEN

Bit 5: Short-circuit detector enable on channel y.

CKABEN

Bit 6: Clock absence detector enable on channel y.

CHEN

Bit 7: Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting..

CHINSEL

Bit 8: Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

DATMPX

Bits 12-13: Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

DATPACK

Bits 14-15: Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

CKOUTDIV

Bits 16-23: Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -.

CKOUTSRC

Bit 30: Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0).

DFSDMEN

Bit 31: Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0).

CFGR2 [4]

DFSDM channel 0 configuration register

Offset: 0x84, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right.

OFFSET

Bits 8-31: 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software..

AWSCDR [4]

DFSDM channel 0 analog watchdog and short-circuit detector register

Offset: 0x88, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw
AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw
SCDT
rw
Toggle fields

SCDT

Bits 0-7: short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel..

BKSCD

Bits 12-15: Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y.

AWFOSR

Bits 16-20: Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is.

AWFORD

Bits 22-23: Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

WDATR [4]

DFSDM channel 0 watchdog filter data register

Offset: 0x8c, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
r
Toggle fields

WDATA

Bits 0-15: Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3)..

DATINR [4]

DFSDM channel 0 data input register

Offset: 0x90, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format..

INDAT1

Bits 16-31: Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format..

DLYR [4]

Offset: 0x94, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied.

CFGR1 [5]

DFSDM channel 0 configuration register

Offset: 0xa0, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw
CKOUTSRC
rw
CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw
DATMPX
rw
CHINSEL
rw
CHEN
rw
CKABEN
rw
SCDEN
rw
SPICKSEL
rw
SITP
rw
Toggle fields

SITP

Bits 0-1: Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register)..

SPICKSEL

Bits 2-3: SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

SCDEN

Bit 5: Short-circuit detector enable on channel y.

CKABEN

Bit 6: Clock absence detector enable on channel y.

CHEN

Bit 7: Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting..

CHINSEL

Bit 8: Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

DATMPX

Bits 12-13: Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

DATPACK

Bits 14-15: Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

CKOUTDIV

Bits 16-23: Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -.

CKOUTSRC

Bit 30: Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0).

DFSDMEN

Bit 31: Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0).

CFGR2 [5]

DFSDM channel 0 configuration register

Offset: 0xa4, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right.

OFFSET

Bits 8-31: 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software..

AWSCDR [5]

DFSDM channel 0 analog watchdog and short-circuit detector register

Offset: 0xa8, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw
AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw
SCDT
rw
Toggle fields

SCDT

Bits 0-7: short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel..

BKSCD

Bits 12-15: Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y.

AWFOSR

Bits 16-20: Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is.

AWFORD

Bits 22-23: Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

WDATR [5]

DFSDM channel 0 watchdog filter data register

Offset: 0xac, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
r
Toggle fields

WDATA

Bits 0-15: Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3)..

DATINR [5]

DFSDM channel 0 data input register

Offset: 0xb0, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format..

INDAT1

Bits 16-31: Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format..

DLYR [5]

Offset: 0xb4, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied.

CFGR1 [6]

DFSDM channel 0 configuration register

Offset: 0xc0, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw
CKOUTSRC
rw
CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw
DATMPX
rw
CHINSEL
rw
CHEN
rw
CKABEN
rw
SCDEN
rw
SPICKSEL
rw
SITP
rw
Toggle fields

SITP

Bits 0-1: Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register)..

SPICKSEL

Bits 2-3: SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

SCDEN

Bit 5: Short-circuit detector enable on channel y.

CKABEN

Bit 6: Clock absence detector enable on channel y.

CHEN

Bit 7: Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting..

CHINSEL

Bit 8: Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

DATMPX

Bits 12-13: Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

DATPACK

Bits 14-15: Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

CKOUTDIV

Bits 16-23: Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -.

CKOUTSRC

Bit 30: Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0).

DFSDMEN

Bit 31: Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0).

CFGR2 [6]

DFSDM channel 0 configuration register

Offset: 0xc4, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right.

OFFSET

Bits 8-31: 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software..

AWSCDR [6]

DFSDM channel 0 analog watchdog and short-circuit detector register

Offset: 0xc8, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw
AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw
SCDT
rw
Toggle fields

SCDT

Bits 0-7: short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel..

BKSCD

Bits 12-15: Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y.

AWFOSR

Bits 16-20: Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is.

AWFORD

Bits 22-23: Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

WDATR [6]

DFSDM channel 0 watchdog filter data register

Offset: 0xcc, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
r
Toggle fields

WDATA

Bits 0-15: Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3)..

DATINR [6]

DFSDM channel 0 data input register

Offset: 0xd0, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format..

INDAT1

Bits 16-31: Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format..

DLYR [6]

Offset: 0xd4, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied.

CFGR1 [7]

DFSDM channel 0 configuration register

Offset: 0xe0, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw
CKOUTSRC
rw
CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw
DATMPX
rw
CHINSEL
rw
CHEN
rw
CKABEN
rw
SCDEN
rw
SPICKSEL
rw
SITP
rw
Toggle fields

SITP

Bits 0-1: Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register)..

SPICKSEL

Bits 2-3: SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

SCDEN

Bit 5: Short-circuit detector enable on channel y.

CKABEN

Bit 6: Clock absence detector enable on channel y.

CHEN

Bit 7: Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting..

CHINSEL

Bit 8: Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

DATMPX

Bits 12-13: Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

DATPACK

Bits 14-15: Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

CKOUTDIV

Bits 16-23: Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -.

CKOUTSRC

Bit 30: Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0).

DFSDMEN

Bit 31: Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0).

CFGR2 [7]

DFSDM channel 0 configuration register

Offset: 0xe4, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right.

OFFSET

Bits 8-31: 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software..

AWSCDR [7]

DFSDM channel 0 analog watchdog and short-circuit detector register

Offset: 0xe8, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw
AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw
SCDT
rw
Toggle fields

SCDT

Bits 0-7: short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel..

BKSCD

Bits 12-15: Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y.

AWFOSR

Bits 16-20: Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is.

AWFORD

Bits 22-23: Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

WDATR [7]

DFSDM channel 0 watchdog filter data register

Offset: 0xec, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
r
Toggle fields

WDATA

Bits 0-15: Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3)..

DATINR [7]

DFSDM channel 0 data input register

Offset: 0xf0, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format..

INDAT1

Bits 16-31: Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format..

DLYR [7]

Offset: 0xf4, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied.

CR1 [0]

Offset: 0x100, size: 32, reset: 0x00000000, access: Unspecified

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw
FAST
rw
RCH
rw
RDMAEN
rw
RSYNC
rw
RCONT
rw
RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw
JEXTSEL
rw
JDMAEN
rw
JSCAN
rw
JSYNC
rw
JSWSTART
rw
DFEN
rw
Toggle fields

DFEN

Bit 0: DFSDM_FLTx enable Data which are cleared by setting DFEN=0: register DFSDM_FLTxISR is set to the reset state register DFSDM_FLTxAWSR is set to the reset state.

JSWSTART

Bit 1: Start a conversion of the injected group of channels This bit is always read as '0’..

JSYNC

Bit 3: Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

JSCAN

Bit 4: Scanning conversion mode for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel..

JDMAEN

Bit 5: DMA channel enabled to read data for the injected channel group This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

JEXTSEL

Bits 8-12: Trigger signal selection for launching injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). DFSDM_FLTx 0x00 dfsdm_jtrg0 0x01 dfsdm_jtrg1 ... 0x1E dfsdm_jtrg30 0x1F dfsdm_jtrg31 Refer to . 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger)..

JEXTEN

Bits 13-14: Trigger enable and trigger edge selection for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RSWSTART

Bit 17: Software start of a conversion on the regular channel This bit is always read as '0’..

RCONT

Bit 18: Continuous mode selection for regular conversions Writing '0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately..

RSYNC

Bit 19: Launch regular conversion synchronously with DFSDM_FLT0 This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RDMAEN

Bit 21: DMA channel enabled to read data for the regular conversion This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RCH

Bits 24-26: Regular channel selection ... 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion)..

FAST

Bit 29: Fast conversion mode selection for regular conversions When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (... but CNVCNT=0) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input..

AWFSEL

Bit 30: Analog watchdog fast mode select.

CR2 [0]

Offset: 0x104, size: 32, reset: 0x00000000, access: Unspecified

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw
CKABIE
rw
SCDIE
rw
AWDIE
rw
ROVRIE
rw
JOVRIE
rw
REOCIE
rw
JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: Injected end of conversion interrupt enable Please see the explanation of JEOCF in DFSDM_FLTxISR..

REOCIE

Bit 1: Regular end of conversion interrupt enable Please see the explanation of REOCF in DFSDM_FLTxISR..

JOVRIE

Bit 2: Injected data overrun interrupt enable Please see the explanation of JOVRF in DFSDM_FLTxISR..

ROVRIE

Bit 3: Regular data overrun interrupt enable Please see the explanation of ROVRF in DFSDM_FLTxISR..

AWDIE

Bit 4: Analog watchdog interrupt enable Please see the explanation of AWDF in DFSDM_FLTxISR..

SCDIE

Bit 5: Short-circuit detector interrupt enable Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR. Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0).

CKABIE

Bit 6: Clock absence interrupt enable Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR. Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0).

EXCH

Bits 8-15: Extremes detector channel selection These bits select the input channels to be taken by the Extremes detector. EXCH[y] = 0: Extremes detector does not accept data from channel y EXCH[y] = 1: Extremes detector accepts data from channel y.

AWDCH

Bits 16-23: Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog. AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y.

ISR [0]

Offset: 0x108, size: 32, reset: 0x00FF0000, access: Unspecified

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r
CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r
JCIP
r
AWDF
r
ROVRF
r
JOVRF
r
REOCF
r
JEOCF
r
Toggle fields

JEOCF

Bit 0: End of injected conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR..

REOCF

Bit 1: End of regular conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR..

JOVRF

Bit 2: Injected conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register..

ROVRF

Bit 3: Regular conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register..

AWDF

Bit 4: Analog watchdog This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1’ into the clear bits in DFSDM_FLTxAWCFR register)..

JCIP

Bit 13: Injected conversion in progress status A request to start an injected conversion is ignored when JCIP=1..

RCIP

Bit 14: Regular conversion in progress status A request to start a regular conversion is ignored when RCIP=1..

CKABF

Bits 16-23: Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0).

SCDF

Bits 24-31: short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0).

ICR [0]

Offset: 0x10c, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw
CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw
CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: Clear the injected conversion overrun flag.

CLRROVRF

Bit 3: Clear the regular conversion overrun flag.

CLRCKABF

Bits 16-23: Clear the clock absence flag CLRCKABF[y]=0: Writing '0’ has no effect CLRCKABF[y]=1: Writing '1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0).

CLRSCDF

Bits 24-31: Clear the short-circuit detector flag CLRSCDF[y]=0: Writing '0’ has no effect CLRSCDF[y]=1: Writing '1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0).

JCHGR [0]

Offset: 0x110, size: 32, reset: 0x00000001, access: Unspecified

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored..

FCR [0]

Offset: 0x114, size: 32, reset: 0x00000000, access: Unspecified

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw
FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: Integrator oversampling ratio (averaging length) from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). 0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples.

FOSR

Bits 16-25: Sinc filter oversampling ratio (decimation rate) number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If FOSR = 0, then the filter has no effect (filter bypass). 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This.

FORD

Bits 29-31: Sinc filter order 2: Sinc2 filter type 3: Sinc3 filter type 4: Sinc4 filter type 5: Sinc5 filter type 6-7: Reserved Sincx filter type transfer function: FastSinc filter type transfer function: This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)..

JDATAR [0]

Offset: 0x118, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
JDATACH
r
Toggle fields

JDATACH

Bits 0-2: Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0]..

JDATA

Bits 8-31: Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF..

RDATAR [0]

Offset: 0x11c, size: 32, reset: 0x00000000, access: Unspecified

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
RPEND
r
RDATACH
r
Toggle fields

RDATACH

Bits 0-2: Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0]..

RPEND

Bit 4: Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion.

RDATA

Bits 8-31: Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF..

AWHTR [0]

Offset: 0x120, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw
BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: Break signal assignment to analog watchdog high threshold event BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event.

AWHT

Bits 8-31: Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case..

AWLTR [0]

Offset: 0x124, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw
BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: Break signal assignment to analog watchdog low threshold event BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event.

AWLT

Bits 8-31: Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case..

AWSR [0]

Offset: 0x128, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r
AWLTF
r
Toggle fields

AWLTF

Bits 0-7: Analog watchdog low threshold flag AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register..

AWHTF

Bits 8-15: Analog watchdog high threshold flag AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register..

AWCFR [0]

Offset: 0x12c, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw
CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing '0’ has no effect CLRAWLTF[y]=1: Writing '1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register.

CLRAWHTF

Bits 8-15: Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing '0’ has no effect CLRAWHTF[y]=1: Writing '1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register.

EXMAX [0]

Offset: 0x130, size: 32, reset: 0x80000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
rs
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
rs
EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: Extremes detector maximum data channel. These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register..

EXMAX

Bits 8-31: Extremes detector maximum value These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register..

EXMIN [0]

Offset: 0x134, size: 32, reset: 0x7FFFFF00, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
rc/w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
rc/w
EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: Extremes detector minimum data channel These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register..

EXMIN

Bits 8-31: Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register..

CNVTIMR [0]

Offset: 0x138, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time..

CR1 [1]

Offset: 0x180, size: 32, reset: 0x00000000, access: Unspecified

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw
FAST
rw
RCH
rw
RDMAEN
rw
RSYNC
rw
RCONT
rw
RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw
JEXTSEL
rw
JDMAEN
rw
JSCAN
rw
JSYNC
rw
JSWSTART
rw
DFEN
rw
Toggle fields

DFEN

Bit 0: DFSDM_FLTx enable Data which are cleared by setting DFEN=0: register DFSDM_FLTxISR is set to the reset state register DFSDM_FLTxAWSR is set to the reset state.

JSWSTART

Bit 1: Start a conversion of the injected group of channels This bit is always read as '0’..

JSYNC

Bit 3: Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

JSCAN

Bit 4: Scanning conversion mode for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel..

JDMAEN

Bit 5: DMA channel enabled to read data for the injected channel group This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

JEXTSEL

Bits 8-12: Trigger signal selection for launching injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). DFSDM_FLTx 0x00 dfsdm_jtrg0 0x01 dfsdm_jtrg1 ... 0x1E dfsdm_jtrg30 0x1F dfsdm_jtrg31 Refer to . 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger)..

JEXTEN

Bits 13-14: Trigger enable and trigger edge selection for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RSWSTART

Bit 17: Software start of a conversion on the regular channel This bit is always read as '0’..

RCONT

Bit 18: Continuous mode selection for regular conversions Writing '0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately..

RSYNC

Bit 19: Launch regular conversion synchronously with DFSDM_FLT0 This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RDMAEN

Bit 21: DMA channel enabled to read data for the regular conversion This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RCH

Bits 24-26: Regular channel selection ... 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion)..

FAST

Bit 29: Fast conversion mode selection for regular conversions When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (... but CNVCNT=0) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input..

AWFSEL

Bit 30: Analog watchdog fast mode select.

CR2 [1]

Offset: 0x184, size: 32, reset: 0x00000000, access: Unspecified

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw
CKABIE
rw
SCDIE
rw
AWDIE
rw
ROVRIE
rw
JOVRIE
rw
REOCIE
rw
JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: Injected end of conversion interrupt enable Please see the explanation of JEOCF in DFSDM_FLTxISR..

REOCIE

Bit 1: Regular end of conversion interrupt enable Please see the explanation of REOCF in DFSDM_FLTxISR..

JOVRIE

Bit 2: Injected data overrun interrupt enable Please see the explanation of JOVRF in DFSDM_FLTxISR..

ROVRIE

Bit 3: Regular data overrun interrupt enable Please see the explanation of ROVRF in DFSDM_FLTxISR..

AWDIE

Bit 4: Analog watchdog interrupt enable Please see the explanation of AWDF in DFSDM_FLTxISR..

SCDIE

Bit 5: Short-circuit detector interrupt enable Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR. Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0).

CKABIE

Bit 6: Clock absence interrupt enable Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR. Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0).

EXCH

Bits 8-15: Extremes detector channel selection These bits select the input channels to be taken by the Extremes detector. EXCH[y] = 0: Extremes detector does not accept data from channel y EXCH[y] = 1: Extremes detector accepts data from channel y.

AWDCH

Bits 16-23: Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog. AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y.

ISR [1]

Offset: 0x188, size: 32, reset: 0x00FF0000, access: Unspecified

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r
CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r
JCIP
r
AWDF
r
ROVRF
r
JOVRF
r
REOCF
r
JEOCF
r
Toggle fields

JEOCF

Bit 0: End of injected conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR..

REOCF

Bit 1: End of regular conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR..

JOVRF

Bit 2: Injected conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register..

ROVRF

Bit 3: Regular conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register..

AWDF

Bit 4: Analog watchdog This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1’ into the clear bits in DFSDM_FLTxAWCFR register)..

JCIP

Bit 13: Injected conversion in progress status A request to start an injected conversion is ignored when JCIP=1..

RCIP

Bit 14: Regular conversion in progress status A request to start a regular conversion is ignored when RCIP=1..

CKABF

Bits 16-23: Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0).

SCDF

Bits 24-31: short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0).

ICR [1]

Offset: 0x18c, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw
CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw
CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: Clear the injected conversion overrun flag.

CLRROVRF

Bit 3: Clear the regular conversion overrun flag.

CLRCKABF

Bits 16-23: Clear the clock absence flag CLRCKABF[y]=0: Writing '0’ has no effect CLRCKABF[y]=1: Writing '1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0).

CLRSCDF

Bits 24-31: Clear the short-circuit detector flag CLRSCDF[y]=0: Writing '0’ has no effect CLRSCDF[y]=1: Writing '1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0).

JCHGR [1]

Offset: 0x190, size: 32, reset: 0x00000001, access: Unspecified

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored..

FCR [1]

Offset: 0x194, size: 32, reset: 0x00000000, access: Unspecified

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw
FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: Integrator oversampling ratio (averaging length) from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). 0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples.

FOSR

Bits 16-25: Sinc filter oversampling ratio (decimation rate) number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If FOSR = 0, then the filter has no effect (filter bypass). 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This.

FORD

Bits 29-31: Sinc filter order 2: Sinc2 filter type 3: Sinc3 filter type 4: Sinc4 filter type 5: Sinc5 filter type 6-7: Reserved Sincx filter type transfer function: FastSinc filter type transfer function: This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)..

JDATAR [1]

Offset: 0x198, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
JDATACH
r
Toggle fields

JDATACH

Bits 0-2: Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0]..

JDATA

Bits 8-31: Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF..

RDATAR [1]

Offset: 0x19c, size: 32, reset: 0x00000000, access: Unspecified

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
RPEND
r
RDATACH
r
Toggle fields

RDATACH

Bits 0-2: Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0]..

RPEND

Bit 4: Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion.

RDATA

Bits 8-31: Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF..

AWHTR [1]

Offset: 0x1a0, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw
BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: Break signal assignment to analog watchdog high threshold event BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event.

AWHT

Bits 8-31: Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case..

AWLTR [1]

Offset: 0x1a4, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw
BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: Break signal assignment to analog watchdog low threshold event BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event.

AWLT

Bits 8-31: Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case..

AWSR [1]

Offset: 0x1a8, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r
AWLTF
r
Toggle fields

AWLTF

Bits 0-7: Analog watchdog low threshold flag AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register..

AWHTF

Bits 8-15: Analog watchdog high threshold flag AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register..

AWCFR [1]

Offset: 0x1ac, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw
CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing '0’ has no effect CLRAWLTF[y]=1: Writing '1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register.

CLRAWHTF

Bits 8-15: Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing '0’ has no effect CLRAWHTF[y]=1: Writing '1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register.

EXMAX [1]

Offset: 0x1b0, size: 32, reset: 0x80000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
rs
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
rs
EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: Extremes detector maximum data channel. These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register..

EXMAX

Bits 8-31: Extremes detector maximum value These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register..

EXMIN [1]

Offset: 0x1b4, size: 32, reset: 0x7FFFFF00, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
rc/w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
rc/w
EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: Extremes detector minimum data channel These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register..

EXMIN

Bits 8-31: Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register..

CNVTIMR [1]

Offset: 0x1b8, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time..

CR1 [2]

Offset: 0x200, size: 32, reset: 0x00000000, access: Unspecified

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw
FAST
rw
RCH
rw
RDMAEN
rw
RSYNC
rw
RCONT
rw
RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw
JEXTSEL
rw
JDMAEN
rw
JSCAN
rw
JSYNC
rw
JSWSTART
rw
DFEN
rw
Toggle fields

DFEN

Bit 0: DFSDM_FLTx enable Data which are cleared by setting DFEN=0: register DFSDM_FLTxISR is set to the reset state register DFSDM_FLTxAWSR is set to the reset state.

JSWSTART

Bit 1: Start a conversion of the injected group of channels This bit is always read as '0’..

JSYNC

Bit 3: Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

JSCAN

Bit 4: Scanning conversion mode for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel..

JDMAEN

Bit 5: DMA channel enabled to read data for the injected channel group This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

JEXTSEL

Bits 8-12: Trigger signal selection for launching injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). DFSDM_FLTx 0x00 dfsdm_jtrg0 0x01 dfsdm_jtrg1 ... 0x1E dfsdm_jtrg30 0x1F dfsdm_jtrg31 Refer to . 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger)..

JEXTEN

Bits 13-14: Trigger enable and trigger edge selection for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RSWSTART

Bit 17: Software start of a conversion on the regular channel This bit is always read as '0’..

RCONT

Bit 18: Continuous mode selection for regular conversions Writing '0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately..

RSYNC

Bit 19: Launch regular conversion synchronously with DFSDM_FLT0 This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RDMAEN

Bit 21: DMA channel enabled to read data for the regular conversion This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RCH

Bits 24-26: Regular channel selection ... 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion)..

FAST

Bit 29: Fast conversion mode selection for regular conversions When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (... but CNVCNT=0) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input..

AWFSEL

Bit 30: Analog watchdog fast mode select.

CR2 [2]

Offset: 0x204, size: 32, reset: 0x00000000, access: Unspecified

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw
CKABIE
rw
SCDIE
rw
AWDIE
rw
ROVRIE
rw
JOVRIE
rw
REOCIE
rw
JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: Injected end of conversion interrupt enable Please see the explanation of JEOCF in DFSDM_FLTxISR..

REOCIE

Bit 1: Regular end of conversion interrupt enable Please see the explanation of REOCF in DFSDM_FLTxISR..

JOVRIE

Bit 2: Injected data overrun interrupt enable Please see the explanation of JOVRF in DFSDM_FLTxISR..

ROVRIE

Bit 3: Regular data overrun interrupt enable Please see the explanation of ROVRF in DFSDM_FLTxISR..

AWDIE

Bit 4: Analog watchdog interrupt enable Please see the explanation of AWDF in DFSDM_FLTxISR..

SCDIE

Bit 5: Short-circuit detector interrupt enable Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR. Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0).

CKABIE

Bit 6: Clock absence interrupt enable Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR. Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0).

EXCH

Bits 8-15: Extremes detector channel selection These bits select the input channels to be taken by the Extremes detector. EXCH[y] = 0: Extremes detector does not accept data from channel y EXCH[y] = 1: Extremes detector accepts data from channel y.

AWDCH

Bits 16-23: Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog. AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y.

ISR [2]

Offset: 0x208, size: 32, reset: 0x00FF0000, access: Unspecified

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r
CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r
JCIP
r
AWDF
r
ROVRF
r
JOVRF
r
REOCF
r
JEOCF
r
Toggle fields

JEOCF

Bit 0: End of injected conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR..

REOCF

Bit 1: End of regular conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR..

JOVRF

Bit 2: Injected conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register..

ROVRF

Bit 3: Regular conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register..

AWDF

Bit 4: Analog watchdog This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1’ into the clear bits in DFSDM_FLTxAWCFR register)..

JCIP

Bit 13: Injected conversion in progress status A request to start an injected conversion is ignored when JCIP=1..

RCIP

Bit 14: Regular conversion in progress status A request to start a regular conversion is ignored when RCIP=1..

CKABF

Bits 16-23: Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0).

SCDF

Bits 24-31: short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0).

ICR [2]

Offset: 0x20c, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw
CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw
CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: Clear the injected conversion overrun flag.

CLRROVRF

Bit 3: Clear the regular conversion overrun flag.

CLRCKABF

Bits 16-23: Clear the clock absence flag CLRCKABF[y]=0: Writing '0’ has no effect CLRCKABF[y]=1: Writing '1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0).

CLRSCDF

Bits 24-31: Clear the short-circuit detector flag CLRSCDF[y]=0: Writing '0’ has no effect CLRSCDF[y]=1: Writing '1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0).

JCHGR [2]

Offset: 0x210, size: 32, reset: 0x00000001, access: Unspecified

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored..

FCR [2]

Offset: 0x214, size: 32, reset: 0x00000000, access: Unspecified

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw
FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: Integrator oversampling ratio (averaging length) from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). 0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples.

FOSR

Bits 16-25: Sinc filter oversampling ratio (decimation rate) number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If FOSR = 0, then the filter has no effect (filter bypass). 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This.

FORD

Bits 29-31: Sinc filter order 2: Sinc2 filter type 3: Sinc3 filter type 4: Sinc4 filter type 5: Sinc5 filter type 6-7: Reserved Sincx filter type transfer function: FastSinc filter type transfer function: This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)..

JDATAR [2]

Offset: 0x218, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
JDATACH
r
Toggle fields

JDATACH

Bits 0-2: Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0]..

JDATA

Bits 8-31: Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF..

RDATAR [2]

Offset: 0x21c, size: 32, reset: 0x00000000, access: Unspecified

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
RPEND
r
RDATACH
r
Toggle fields

RDATACH

Bits 0-2: Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0]..

RPEND

Bit 4: Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion.

RDATA

Bits 8-31: Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF..

AWHTR [2]

Offset: 0x220, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw
BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: Break signal assignment to analog watchdog high threshold event BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event.

AWHT

Bits 8-31: Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case..

AWLTR [2]

Offset: 0x224, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw
BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: Break signal assignment to analog watchdog low threshold event BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event.

AWLT

Bits 8-31: Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case..

AWSR [2]

Offset: 0x228, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r
AWLTF
r
Toggle fields

AWLTF

Bits 0-7: Analog watchdog low threshold flag AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register..

AWHTF

Bits 8-15: Analog watchdog high threshold flag AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register..

AWCFR [2]

Offset: 0x22c, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw
CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing '0’ has no effect CLRAWLTF[y]=1: Writing '1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register.

CLRAWHTF

Bits 8-15: Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing '0’ has no effect CLRAWHTF[y]=1: Writing '1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register.

EXMAX [2]

Offset: 0x230, size: 32, reset: 0x80000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
rs
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
rs
EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: Extremes detector maximum data channel. These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register..

EXMAX

Bits 8-31: Extremes detector maximum value These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register..

EXMIN [2]

Offset: 0x234, size: 32, reset: 0x7FFFFF00, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
rc/w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
rc/w
EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: Extremes detector minimum data channel These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register..

EXMIN

Bits 8-31: Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register..

CNVTIMR [2]

Offset: 0x238, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time..

CR1 [3]

Offset: 0x280, size: 32, reset: 0x00000000, access: Unspecified

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw
FAST
rw
RCH
rw
RDMAEN
rw
RSYNC
rw
RCONT
rw
RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw
JEXTSEL
rw
JDMAEN
rw
JSCAN
rw
JSYNC
rw
JSWSTART
rw
DFEN
rw
Toggle fields

DFEN

Bit 0: DFSDM_FLTx enable Data which are cleared by setting DFEN=0: register DFSDM_FLTxISR is set to the reset state register DFSDM_FLTxAWSR is set to the reset state.

JSWSTART

Bit 1: Start a conversion of the injected group of channels This bit is always read as '0’..

JSYNC

Bit 3: Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

JSCAN

Bit 4: Scanning conversion mode for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel..

JDMAEN

Bit 5: DMA channel enabled to read data for the injected channel group This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

JEXTSEL

Bits 8-12: Trigger signal selection for launching injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). DFSDM_FLTx 0x00 dfsdm_jtrg0 0x01 dfsdm_jtrg1 ... 0x1E dfsdm_jtrg30 0x1F dfsdm_jtrg31 Refer to . 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger)..

JEXTEN

Bits 13-14: Trigger enable and trigger edge selection for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RSWSTART

Bit 17: Software start of a conversion on the regular channel This bit is always read as '0’..

RCONT

Bit 18: Continuous mode selection for regular conversions Writing '0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately..

RSYNC

Bit 19: Launch regular conversion synchronously with DFSDM_FLT0 This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RDMAEN

Bit 21: DMA channel enabled to read data for the regular conversion This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RCH

Bits 24-26: Regular channel selection ... 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion)..

FAST

Bit 29: Fast conversion mode selection for regular conversions When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (... but CNVCNT=0) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input..

AWFSEL

Bit 30: Analog watchdog fast mode select.

CR2 [3]

Offset: 0x284, size: 32, reset: 0x00000000, access: Unspecified

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw
CKABIE
rw
SCDIE
rw
AWDIE
rw
ROVRIE
rw
JOVRIE
rw
REOCIE
rw
JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: Injected end of conversion interrupt enable Please see the explanation of JEOCF in DFSDM_FLTxISR..

REOCIE

Bit 1: Regular end of conversion interrupt enable Please see the explanation of REOCF in DFSDM_FLTxISR..

JOVRIE

Bit 2: Injected data overrun interrupt enable Please see the explanation of JOVRF in DFSDM_FLTxISR..

ROVRIE

Bit 3: Regular data overrun interrupt enable Please see the explanation of ROVRF in DFSDM_FLTxISR..

AWDIE

Bit 4: Analog watchdog interrupt enable Please see the explanation of AWDF in DFSDM_FLTxISR..

SCDIE

Bit 5: Short-circuit detector interrupt enable Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR. Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0).

CKABIE

Bit 6: Clock absence interrupt enable Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR. Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0).

EXCH

Bits 8-15: Extremes detector channel selection These bits select the input channels to be taken by the Extremes detector. EXCH[y] = 0: Extremes detector does not accept data from channel y EXCH[y] = 1: Extremes detector accepts data from channel y.

AWDCH

Bits 16-23: Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog. AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y.

ISR [3]

Offset: 0x288, size: 32, reset: 0x00FF0000, access: Unspecified

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r
CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r
JCIP
r
AWDF
r
ROVRF
r
JOVRF
r
REOCF
r
JEOCF
r
Toggle fields

JEOCF

Bit 0: End of injected conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR..

REOCF

Bit 1: End of regular conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR..

JOVRF

Bit 2: Injected conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register..

ROVRF

Bit 3: Regular conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register..

AWDF

Bit 4: Analog watchdog This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1’ into the clear bits in DFSDM_FLTxAWCFR register)..

JCIP

Bit 13: Injected conversion in progress status A request to start an injected conversion is ignored when JCIP=1..

RCIP

Bit 14: Regular conversion in progress status A request to start a regular conversion is ignored when RCIP=1..

CKABF

Bits 16-23: Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0).

SCDF

Bits 24-31: short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0).

ICR [3]

Offset: 0x28c, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw
CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw
CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: Clear the injected conversion overrun flag.

CLRROVRF

Bit 3: Clear the regular conversion overrun flag.

CLRCKABF

Bits 16-23: Clear the clock absence flag CLRCKABF[y]=0: Writing '0’ has no effect CLRCKABF[y]=1: Writing '1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0).

CLRSCDF

Bits 24-31: Clear the short-circuit detector flag CLRSCDF[y]=0: Writing '0’ has no effect CLRSCDF[y]=1: Writing '1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0).

JCHGR [3]

Offset: 0x290, size: 32, reset: 0x00000001, access: Unspecified

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored..

FCR [3]

Offset: 0x294, size: 32, reset: 0x00000000, access: Unspecified

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw
FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: Integrator oversampling ratio (averaging length) from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). 0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples.

FOSR

Bits 16-25: Sinc filter oversampling ratio (decimation rate) number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If FOSR = 0, then the filter has no effect (filter bypass). 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This.

FORD

Bits 29-31: Sinc filter order 2: Sinc2 filter type 3: Sinc3 filter type 4: Sinc4 filter type 5: Sinc5 filter type 6-7: Reserved Sincx filter type transfer function: FastSinc filter type transfer function: This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)..

JDATAR [3]

Offset: 0x298, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
JDATACH
r
Toggle fields

JDATACH

Bits 0-2: Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0]..

JDATA

Bits 8-31: Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF..

RDATAR [3]

Offset: 0x29c, size: 32, reset: 0x00000000, access: Unspecified

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
RPEND
r
RDATACH
r
Toggle fields

RDATACH

Bits 0-2: Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0]..

RPEND

Bit 4: Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion.

RDATA

Bits 8-31: Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF..

AWHTR [3]

Offset: 0x2a0, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw
BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: Break signal assignment to analog watchdog high threshold event BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event.

AWHT

Bits 8-31: Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case..

AWLTR [3]

Offset: 0x2a4, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw
BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: Break signal assignment to analog watchdog low threshold event BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event.

AWLT

Bits 8-31: Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case..

AWSR [3]

Offset: 0x2a8, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r
AWLTF
r
Toggle fields

AWLTF

Bits 0-7: Analog watchdog low threshold flag AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register..

AWHTF

Bits 8-15: Analog watchdog high threshold flag AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register..

AWCFR [3]

Offset: 0x2ac, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw
CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing '0’ has no effect CLRAWLTF[y]=1: Writing '1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register.

CLRAWHTF

Bits 8-15: Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing '0’ has no effect CLRAWHTF[y]=1: Writing '1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register.

EXMAX [3]

Offset: 0x2b0, size: 32, reset: 0x80000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
rs
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
rs
EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: Extremes detector maximum data channel. These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register..

EXMAX

Bits 8-31: Extremes detector maximum value These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register..

EXMIN [3]

Offset: 0x2b4, size: 32, reset: 0x7FFFFF00, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
rc/w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
rc/w
EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: Extremes detector minimum data channel These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register..

EXMIN

Bits 8-31: Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register..

CNVTIMR [3]

Offset: 0x2b8, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time..

CR1 [4]

Offset: 0x300, size: 32, reset: 0x00000000, access: Unspecified

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw
FAST
rw
RCH
rw
RDMAEN
rw
RSYNC
rw
RCONT
rw
RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw
JEXTSEL
rw
JDMAEN
rw
JSCAN
rw
JSYNC
rw
JSWSTART
rw
DFEN
rw
Toggle fields

DFEN

Bit 0: DFSDM_FLTx enable Data which are cleared by setting DFEN=0: register DFSDM_FLTxISR is set to the reset state register DFSDM_FLTxAWSR is set to the reset state.

JSWSTART

Bit 1: Start a conversion of the injected group of channels This bit is always read as '0’..

JSYNC

Bit 3: Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

JSCAN

Bit 4: Scanning conversion mode for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel..

JDMAEN

Bit 5: DMA channel enabled to read data for the injected channel group This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

JEXTSEL

Bits 8-12: Trigger signal selection for launching injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). DFSDM_FLTx 0x00 dfsdm_jtrg0 0x01 dfsdm_jtrg1 ... 0x1E dfsdm_jtrg30 0x1F dfsdm_jtrg31 Refer to . 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger)..

JEXTEN

Bits 13-14: Trigger enable and trigger edge selection for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RSWSTART

Bit 17: Software start of a conversion on the regular channel This bit is always read as '0’..

RCONT

Bit 18: Continuous mode selection for regular conversions Writing '0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately..

RSYNC

Bit 19: Launch regular conversion synchronously with DFSDM_FLT0 This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RDMAEN

Bit 21: DMA channel enabled to read data for the regular conversion This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RCH

Bits 24-26: Regular channel selection ... 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion)..

FAST

Bit 29: Fast conversion mode selection for regular conversions When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (... but CNVCNT=0) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input..

AWFSEL

Bit 30: Analog watchdog fast mode select.

CR2 [4]

Offset: 0x304, size: 32, reset: 0x00000000, access: Unspecified

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw
CKABIE
rw
SCDIE
rw
AWDIE
rw
ROVRIE
rw
JOVRIE
rw
REOCIE
rw
JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: Injected end of conversion interrupt enable Please see the explanation of JEOCF in DFSDM_FLTxISR..

REOCIE

Bit 1: Regular end of conversion interrupt enable Please see the explanation of REOCF in DFSDM_FLTxISR..

JOVRIE

Bit 2: Injected data overrun interrupt enable Please see the explanation of JOVRF in DFSDM_FLTxISR..

ROVRIE

Bit 3: Regular data overrun interrupt enable Please see the explanation of ROVRF in DFSDM_FLTxISR..

AWDIE

Bit 4: Analog watchdog interrupt enable Please see the explanation of AWDF in DFSDM_FLTxISR..

SCDIE

Bit 5: Short-circuit detector interrupt enable Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR. Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0).

CKABIE

Bit 6: Clock absence interrupt enable Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR. Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0).

EXCH

Bits 8-15: Extremes detector channel selection These bits select the input channels to be taken by the Extremes detector. EXCH[y] = 0: Extremes detector does not accept data from channel y EXCH[y] = 1: Extremes detector accepts data from channel y.

AWDCH

Bits 16-23: Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog. AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y.

ISR [4]

Offset: 0x308, size: 32, reset: 0x00FF0000, access: Unspecified

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r
CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r
JCIP
r
AWDF
r
ROVRF
r
JOVRF
r
REOCF
r
JEOCF
r
Toggle fields

JEOCF

Bit 0: End of injected conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR..

REOCF

Bit 1: End of regular conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR..

JOVRF

Bit 2: Injected conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register..

ROVRF

Bit 3: Regular conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register..

AWDF

Bit 4: Analog watchdog This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1’ into the clear bits in DFSDM_FLTxAWCFR register)..

JCIP

Bit 13: Injected conversion in progress status A request to start an injected conversion is ignored when JCIP=1..

RCIP

Bit 14: Regular conversion in progress status A request to start a regular conversion is ignored when RCIP=1..

CKABF

Bits 16-23: Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0).

SCDF

Bits 24-31: short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0).

ICR [4]

Offset: 0x30c, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw
CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw
CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: Clear the injected conversion overrun flag.

CLRROVRF

Bit 3: Clear the regular conversion overrun flag.

CLRCKABF

Bits 16-23: Clear the clock absence flag CLRCKABF[y]=0: Writing '0’ has no effect CLRCKABF[y]=1: Writing '1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0).

CLRSCDF

Bits 24-31: Clear the short-circuit detector flag CLRSCDF[y]=0: Writing '0’ has no effect CLRSCDF[y]=1: Writing '1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0).

JCHGR [4]

Offset: 0x310, size: 32, reset: 0x00000001, access: Unspecified

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored..

FCR [4]

Offset: 0x314, size: 32, reset: 0x00000000, access: Unspecified

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw
FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: Integrator oversampling ratio (averaging length) from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). 0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples.

FOSR

Bits 16-25: Sinc filter oversampling ratio (decimation rate) number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If FOSR = 0, then the filter has no effect (filter bypass). 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This.

FORD

Bits 29-31: Sinc filter order 2: Sinc2 filter type 3: Sinc3 filter type 4: Sinc4 filter type 5: Sinc5 filter type 6-7: Reserved Sincx filter type transfer function: FastSinc filter type transfer function: This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)..

JDATAR [4]

Offset: 0x318, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
JDATACH
r
Toggle fields

JDATACH

Bits 0-2: Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0]..

JDATA

Bits 8-31: Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF..

RDATAR [4]

Offset: 0x31c, size: 32, reset: 0x00000000, access: Unspecified

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
RPEND
r
RDATACH
r
Toggle fields

RDATACH

Bits 0-2: Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0]..

RPEND

Bit 4: Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion.

RDATA

Bits 8-31: Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF..

AWHTR [4]

Offset: 0x320, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw
BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: Break signal assignment to analog watchdog high threshold event BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event.

AWHT

Bits 8-31: Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case..

AWLTR [4]

Offset: 0x324, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw
BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: Break signal assignment to analog watchdog low threshold event BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event.

AWLT

Bits 8-31: Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case..

AWSR [4]

Offset: 0x328, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r
AWLTF
r
Toggle fields

AWLTF

Bits 0-7: Analog watchdog low threshold flag AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register..

AWHTF

Bits 8-15: Analog watchdog high threshold flag AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register..

AWCFR [4]

Offset: 0x32c, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw
CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing '0’ has no effect CLRAWLTF[y]=1: Writing '1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register.

CLRAWHTF

Bits 8-15: Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing '0’ has no effect CLRAWHTF[y]=1: Writing '1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register.

EXMAX [4]

Offset: 0x330, size: 32, reset: 0x80000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
rs
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
rs
EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: Extremes detector maximum data channel. These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register..

EXMAX

Bits 8-31: Extremes detector maximum value These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register..

EXMIN [4]

Offset: 0x334, size: 32, reset: 0x7FFFFF00, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
rc/w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
rc/w
EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: Extremes detector minimum data channel These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register..

EXMIN

Bits 8-31: Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register..

CNVTIMR [4]

Offset: 0x338, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time..

CR1 [5]

Offset: 0x380, size: 32, reset: 0x00000000, access: Unspecified

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw
FAST
rw
RCH
rw
RDMAEN
rw
RSYNC
rw
RCONT
rw
RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw
JEXTSEL
rw
JDMAEN
rw
JSCAN
rw
JSYNC
rw
JSWSTART
rw
DFEN
rw
Toggle fields

DFEN

Bit 0: DFSDM_FLTx enable Data which are cleared by setting DFEN=0: register DFSDM_FLTxISR is set to the reset state register DFSDM_FLTxAWSR is set to the reset state.

JSWSTART

Bit 1: Start a conversion of the injected group of channels This bit is always read as '0’..

JSYNC

Bit 3: Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

JSCAN

Bit 4: Scanning conversion mode for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel..

JDMAEN

Bit 5: DMA channel enabled to read data for the injected channel group This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

JEXTSEL

Bits 8-12: Trigger signal selection for launching injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). DFSDM_FLTx 0x00 dfsdm_jtrg0 0x01 dfsdm_jtrg1 ... 0x1E dfsdm_jtrg30 0x1F dfsdm_jtrg31 Refer to . 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger)..

JEXTEN

Bits 13-14: Trigger enable and trigger edge selection for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RSWSTART

Bit 17: Software start of a conversion on the regular channel This bit is always read as '0’..

RCONT

Bit 18: Continuous mode selection for regular conversions Writing '0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately..

RSYNC

Bit 19: Launch regular conversion synchronously with DFSDM_FLT0 This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RDMAEN

Bit 21: DMA channel enabled to read data for the regular conversion This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RCH

Bits 24-26: Regular channel selection ... 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion)..

FAST

Bit 29: Fast conversion mode selection for regular conversions When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (... but CNVCNT=0) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input..

AWFSEL

Bit 30: Analog watchdog fast mode select.

CR2 [5]

Offset: 0x384, size: 32, reset: 0x00000000, access: Unspecified

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw
CKABIE
rw
SCDIE
rw
AWDIE
rw
ROVRIE
rw
JOVRIE
rw
REOCIE
rw
JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: Injected end of conversion interrupt enable Please see the explanation of JEOCF in DFSDM_FLTxISR..

REOCIE

Bit 1: Regular end of conversion interrupt enable Please see the explanation of REOCF in DFSDM_FLTxISR..

JOVRIE

Bit 2: Injected data overrun interrupt enable Please see the explanation of JOVRF in DFSDM_FLTxISR..

ROVRIE

Bit 3: Regular data overrun interrupt enable Please see the explanation of ROVRF in DFSDM_FLTxISR..

AWDIE

Bit 4: Analog watchdog interrupt enable Please see the explanation of AWDF in DFSDM_FLTxISR..

SCDIE

Bit 5: Short-circuit detector interrupt enable Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR. Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0).

CKABIE

Bit 6: Clock absence interrupt enable Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR. Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0).

EXCH

Bits 8-15: Extremes detector channel selection These bits select the input channels to be taken by the Extremes detector. EXCH[y] = 0: Extremes detector does not accept data from channel y EXCH[y] = 1: Extremes detector accepts data from channel y.

AWDCH

Bits 16-23: Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog. AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y.

ISR [5]

Offset: 0x388, size: 32, reset: 0x00FF0000, access: Unspecified

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r
CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r
JCIP
r
AWDF
r
ROVRF
r
JOVRF
r
REOCF
r
JEOCF
r
Toggle fields

JEOCF

Bit 0: End of injected conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR..

REOCF

Bit 1: End of regular conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR..

JOVRF

Bit 2: Injected conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register..

ROVRF

Bit 3: Regular conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register..

AWDF

Bit 4: Analog watchdog This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1’ into the clear bits in DFSDM_FLTxAWCFR register)..

JCIP

Bit 13: Injected conversion in progress status A request to start an injected conversion is ignored when JCIP=1..

RCIP

Bit 14: Regular conversion in progress status A request to start a regular conversion is ignored when RCIP=1..

CKABF

Bits 16-23: Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0).

SCDF

Bits 24-31: short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0).

ICR [5]

Offset: 0x38c, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw
CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw
CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: Clear the injected conversion overrun flag.

CLRROVRF

Bit 3: Clear the regular conversion overrun flag.

CLRCKABF

Bits 16-23: Clear the clock absence flag CLRCKABF[y]=0: Writing '0’ has no effect CLRCKABF[y]=1: Writing '1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0).

CLRSCDF

Bits 24-31: Clear the short-circuit detector flag CLRSCDF[y]=0: Writing '0’ has no effect CLRSCDF[y]=1: Writing '1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0).

JCHGR [5]

Offset: 0x390, size: 32, reset: 0x00000001, access: Unspecified

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored..

FCR [5]

Offset: 0x394, size: 32, reset: 0x00000000, access: Unspecified

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw
FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: Integrator oversampling ratio (averaging length) from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). 0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples.

FOSR

Bits 16-25: Sinc filter oversampling ratio (decimation rate) number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If FOSR = 0, then the filter has no effect (filter bypass). 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This.

FORD

Bits 29-31: Sinc filter order 2: Sinc2 filter type 3: Sinc3 filter type 4: Sinc4 filter type 5: Sinc5 filter type 6-7: Reserved Sincx filter type transfer function: FastSinc filter type transfer function: This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)..

JDATAR [5]

Offset: 0x398, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
JDATACH
r
Toggle fields

JDATACH

Bits 0-2: Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0]..

JDATA

Bits 8-31: Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF..

RDATAR [5]

Offset: 0x39c, size: 32, reset: 0x00000000, access: Unspecified

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
RPEND
r
RDATACH
r
Toggle fields

RDATACH

Bits 0-2: Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0]..

RPEND

Bit 4: Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion.

RDATA

Bits 8-31: Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF..

AWHTR [5]

Offset: 0x3a0, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw
BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: Break signal assignment to analog watchdog high threshold event BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event.

AWHT

Bits 8-31: Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case..

AWLTR [5]

Offset: 0x3a4, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw
BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: Break signal assignment to analog watchdog low threshold event BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event.

AWLT

Bits 8-31: Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case..

AWSR [5]

Offset: 0x3a8, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r
AWLTF
r
Toggle fields

AWLTF

Bits 0-7: Analog watchdog low threshold flag AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register..

AWHTF

Bits 8-15: Analog watchdog high threshold flag AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register..

AWCFR [5]

Offset: 0x3ac, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw
CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing '0’ has no effect CLRAWLTF[y]=1: Writing '1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register.

CLRAWHTF

Bits 8-15: Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing '0’ has no effect CLRAWHTF[y]=1: Writing '1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register.

EXMAX [5]

Offset: 0x3b0, size: 32, reset: 0x80000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
rs
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
rs
EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: Extremes detector maximum data channel. These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register..

EXMAX

Bits 8-31: Extremes detector maximum value These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register..

EXMIN [5]

Offset: 0x3b4, size: 32, reset: 0x7FFFFF00, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
rc/w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
rc/w
EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: Extremes detector minimum data channel These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register..

EXMIN

Bits 8-31: Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register..

CNVTIMR [5]

Offset: 0x3b8, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time..

CR1 [6]

Offset: 0x400, size: 32, reset: 0x00000000, access: Unspecified

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw
FAST
rw
RCH
rw
RDMAEN
rw
RSYNC
rw
RCONT
rw
RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw
JEXTSEL
rw
JDMAEN
rw
JSCAN
rw
JSYNC
rw
JSWSTART
rw
DFEN
rw
Toggle fields

DFEN

Bit 0: DFSDM_FLTx enable Data which are cleared by setting DFEN=0: register DFSDM_FLTxISR is set to the reset state register DFSDM_FLTxAWSR is set to the reset state.

JSWSTART

Bit 1: Start a conversion of the injected group of channels This bit is always read as '0’..

JSYNC

Bit 3: Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

JSCAN

Bit 4: Scanning conversion mode for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel..

JDMAEN

Bit 5: DMA channel enabled to read data for the injected channel group This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

JEXTSEL

Bits 8-12: Trigger signal selection for launching injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). DFSDM_FLTx 0x00 dfsdm_jtrg0 0x01 dfsdm_jtrg1 ... 0x1E dfsdm_jtrg30 0x1F dfsdm_jtrg31 Refer to . 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger)..

JEXTEN

Bits 13-14: Trigger enable and trigger edge selection for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RSWSTART

Bit 17: Software start of a conversion on the regular channel This bit is always read as '0’..

RCONT

Bit 18: Continuous mode selection for regular conversions Writing '0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately..

RSYNC

Bit 19: Launch regular conversion synchronously with DFSDM_FLT0 This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RDMAEN

Bit 21: DMA channel enabled to read data for the regular conversion This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RCH

Bits 24-26: Regular channel selection ... 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion)..

FAST

Bit 29: Fast conversion mode selection for regular conversions When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (... but CNVCNT=0) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input..

AWFSEL

Bit 30: Analog watchdog fast mode select.

CR2 [6]

Offset: 0x404, size: 32, reset: 0x00000000, access: Unspecified

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw
CKABIE
rw
SCDIE
rw
AWDIE
rw
ROVRIE
rw
JOVRIE
rw
REOCIE
rw
JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: Injected end of conversion interrupt enable Please see the explanation of JEOCF in DFSDM_FLTxISR..

REOCIE

Bit 1: Regular end of conversion interrupt enable Please see the explanation of REOCF in DFSDM_FLTxISR..

JOVRIE

Bit 2: Injected data overrun interrupt enable Please see the explanation of JOVRF in DFSDM_FLTxISR..

ROVRIE

Bit 3: Regular data overrun interrupt enable Please see the explanation of ROVRF in DFSDM_FLTxISR..

AWDIE

Bit 4: Analog watchdog interrupt enable Please see the explanation of AWDF in DFSDM_FLTxISR..

SCDIE

Bit 5: Short-circuit detector interrupt enable Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR. Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0).

CKABIE

Bit 6: Clock absence interrupt enable Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR. Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0).

EXCH

Bits 8-15: Extremes detector channel selection These bits select the input channels to be taken by the Extremes detector. EXCH[y] = 0: Extremes detector does not accept data from channel y EXCH[y] = 1: Extremes detector accepts data from channel y.

AWDCH

Bits 16-23: Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog. AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y.

ISR [6]

Offset: 0x408, size: 32, reset: 0x00FF0000, access: Unspecified

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r
CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r
JCIP
r
AWDF
r
ROVRF
r
JOVRF
r
REOCF
r
JEOCF
r
Toggle fields

JEOCF

Bit 0: End of injected conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR..

REOCF

Bit 1: End of regular conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR..

JOVRF

Bit 2: Injected conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register..

ROVRF

Bit 3: Regular conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register..

AWDF

Bit 4: Analog watchdog This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1’ into the clear bits in DFSDM_FLTxAWCFR register)..

JCIP

Bit 13: Injected conversion in progress status A request to start an injected conversion is ignored when JCIP=1..

RCIP

Bit 14: Regular conversion in progress status A request to start a regular conversion is ignored when RCIP=1..

CKABF

Bits 16-23: Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0).

SCDF

Bits 24-31: short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0).

ICR [6]

Offset: 0x40c, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw
CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw
CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: Clear the injected conversion overrun flag.

CLRROVRF

Bit 3: Clear the regular conversion overrun flag.

CLRCKABF

Bits 16-23: Clear the clock absence flag CLRCKABF[y]=0: Writing '0’ has no effect CLRCKABF[y]=1: Writing '1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0).

CLRSCDF

Bits 24-31: Clear the short-circuit detector flag CLRSCDF[y]=0: Writing '0’ has no effect CLRSCDF[y]=1: Writing '1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0).

JCHGR [6]

Offset: 0x410, size: 32, reset: 0x00000001, access: Unspecified

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored..

FCR [6]

Offset: 0x414, size: 32, reset: 0x00000000, access: Unspecified

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw
FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: Integrator oversampling ratio (averaging length) from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). 0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples.

FOSR

Bits 16-25: Sinc filter oversampling ratio (decimation rate) number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If FOSR = 0, then the filter has no effect (filter bypass). 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This.

FORD

Bits 29-31: Sinc filter order 2: Sinc2 filter type 3: Sinc3 filter type 4: Sinc4 filter type 5: Sinc5 filter type 6-7: Reserved Sincx filter type transfer function: FastSinc filter type transfer function: This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)..

JDATAR [6]

Offset: 0x418, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
JDATACH
r
Toggle fields

JDATACH

Bits 0-2: Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0]..

JDATA

Bits 8-31: Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF..

RDATAR [6]

Offset: 0x41c, size: 32, reset: 0x00000000, access: Unspecified

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
RPEND
r
RDATACH
r
Toggle fields

RDATACH

Bits 0-2: Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0]..

RPEND

Bit 4: Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion.

RDATA

Bits 8-31: Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF..

AWHTR [6]

Offset: 0x420, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw
BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: Break signal assignment to analog watchdog high threshold event BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event.

AWHT

Bits 8-31: Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case..

AWLTR [6]

Offset: 0x424, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw
BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: Break signal assignment to analog watchdog low threshold event BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event.

AWLT

Bits 8-31: Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case..

AWSR [6]

Offset: 0x428, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r
AWLTF
r
Toggle fields

AWLTF

Bits 0-7: Analog watchdog low threshold flag AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register..

AWHTF

Bits 8-15: Analog watchdog high threshold flag AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register..

AWCFR [6]

Offset: 0x42c, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw
CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing '0’ has no effect CLRAWLTF[y]=1: Writing '1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register.

CLRAWHTF

Bits 8-15: Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing '0’ has no effect CLRAWHTF[y]=1: Writing '1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register.

EXMAX [6]

Offset: 0x430, size: 32, reset: 0x80000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
rs
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
rs
EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: Extremes detector maximum data channel. These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register..

EXMAX

Bits 8-31: Extremes detector maximum value These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register..

EXMIN [6]

Offset: 0x434, size: 32, reset: 0x7FFFFF00, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
rc/w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
rc/w
EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: Extremes detector minimum data channel These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register..

EXMIN

Bits 8-31: Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register..

CNVTIMR [6]

Offset: 0x438, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time..

CR1 [7]

Offset: 0x480, size: 32, reset: 0x00000000, access: Unspecified

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw
FAST
rw
RCH
rw
RDMAEN
rw
RSYNC
rw
RCONT
rw
RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw
JEXTSEL
rw
JDMAEN
rw
JSCAN
rw
JSYNC
rw
JSWSTART
rw
DFEN
rw
Toggle fields

DFEN

Bit 0: DFSDM_FLTx enable Data which are cleared by setting DFEN=0: register DFSDM_FLTxISR is set to the reset state register DFSDM_FLTxAWSR is set to the reset state.

JSWSTART

Bit 1: Start a conversion of the injected group of channels This bit is always read as '0’..

JSYNC

Bit 3: Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

JSCAN

Bit 4: Scanning conversion mode for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel..

JDMAEN

Bit 5: DMA channel enabled to read data for the injected channel group This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

JEXTSEL

Bits 8-12: Trigger signal selection for launching injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). DFSDM_FLTx 0x00 dfsdm_jtrg0 0x01 dfsdm_jtrg1 ... 0x1E dfsdm_jtrg30 0x1F dfsdm_jtrg31 Refer to . 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger)..

JEXTEN

Bits 13-14: Trigger enable and trigger edge selection for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RSWSTART

Bit 17: Software start of a conversion on the regular channel This bit is always read as '0’..

RCONT

Bit 18: Continuous mode selection for regular conversions Writing '0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately..

RSYNC

Bit 19: Launch regular conversion synchronously with DFSDM_FLT0 This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RDMAEN

Bit 21: DMA channel enabled to read data for the regular conversion This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RCH

Bits 24-26: Regular channel selection ... 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion)..

FAST

Bit 29: Fast conversion mode selection for regular conversions When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (... but CNVCNT=0) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input..

AWFSEL

Bit 30: Analog watchdog fast mode select.

CR2 [7]

Offset: 0x484, size: 32, reset: 0x00000000, access: Unspecified

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw
CKABIE
rw
SCDIE
rw
AWDIE
rw
ROVRIE
rw
JOVRIE
rw
REOCIE
rw
JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: Injected end of conversion interrupt enable Please see the explanation of JEOCF in DFSDM_FLTxISR..

REOCIE

Bit 1: Regular end of conversion interrupt enable Please see the explanation of REOCF in DFSDM_FLTxISR..

JOVRIE

Bit 2: Injected data overrun interrupt enable Please see the explanation of JOVRF in DFSDM_FLTxISR..

ROVRIE

Bit 3: Regular data overrun interrupt enable Please see the explanation of ROVRF in DFSDM_FLTxISR..

AWDIE

Bit 4: Analog watchdog interrupt enable Please see the explanation of AWDF in DFSDM_FLTxISR..

SCDIE

Bit 5: Short-circuit detector interrupt enable Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR. Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0).

CKABIE

Bit 6: Clock absence interrupt enable Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR. Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0).

EXCH

Bits 8-15: Extremes detector channel selection These bits select the input channels to be taken by the Extremes detector. EXCH[y] = 0: Extremes detector does not accept data from channel y EXCH[y] = 1: Extremes detector accepts data from channel y.

AWDCH

Bits 16-23: Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog. AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y.

ISR [7]

Offset: 0x488, size: 32, reset: 0x00FF0000, access: Unspecified

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r
CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r
JCIP
r
AWDF
r
ROVRF
r
JOVRF
r
REOCF
r
JEOCF
r
Toggle fields

JEOCF

Bit 0: End of injected conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR..

REOCF

Bit 1: End of regular conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR..

JOVRF

Bit 2: Injected conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register..

ROVRF

Bit 3: Regular conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register..

AWDF

Bit 4: Analog watchdog This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1’ into the clear bits in DFSDM_FLTxAWCFR register)..

JCIP

Bit 13: Injected conversion in progress status A request to start an injected conversion is ignored when JCIP=1..

RCIP

Bit 14: Regular conversion in progress status A request to start a regular conversion is ignored when RCIP=1..

CKABF

Bits 16-23: Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0).

SCDF

Bits 24-31: short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0).

ICR [7]

Offset: 0x48c, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw
CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw
CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: Clear the injected conversion overrun flag.

CLRROVRF

Bit 3: Clear the regular conversion overrun flag.

CLRCKABF

Bits 16-23: Clear the clock absence flag CLRCKABF[y]=0: Writing '0’ has no effect CLRCKABF[y]=1: Writing '1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0).

CLRSCDF

Bits 24-31: Clear the short-circuit detector flag CLRSCDF[y]=0: Writing '0’ has no effect CLRSCDF[y]=1: Writing '1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0).

JCHGR [7]

Offset: 0x490, size: 32, reset: 0x00000001, access: Unspecified

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored..

FCR [7]

Offset: 0x494, size: 32, reset: 0x00000000, access: Unspecified

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw
FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: Integrator oversampling ratio (averaging length) from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). 0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples.

FOSR

Bits 16-25: Sinc filter oversampling ratio (decimation rate) number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If FOSR = 0, then the filter has no effect (filter bypass). 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This.

FORD

Bits 29-31: Sinc filter order 2: Sinc2 filter type 3: Sinc3 filter type 4: Sinc4 filter type 5: Sinc5 filter type 6-7: Reserved Sincx filter type transfer function: FastSinc filter type transfer function: This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)..

JDATAR [7]

Offset: 0x498, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
JDATACH
r
Toggle fields

JDATACH

Bits 0-2: Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0]..

JDATA

Bits 8-31: Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF..

RDATAR [7]

Offset: 0x49c, size: 32, reset: 0x00000000, access: Unspecified

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
RPEND
r
RDATACH
r
Toggle fields

RDATACH

Bits 0-2: Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0]..

RPEND

Bit 4: Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion.

RDATA

Bits 8-31: Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF..

AWHTR [7]

Offset: 0x4a0, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw
BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: Break signal assignment to analog watchdog high threshold event BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event.

AWHT

Bits 8-31: Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case..

AWLTR [7]

Offset: 0x4a4, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw
BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: Break signal assignment to analog watchdog low threshold event BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event.

AWLT

Bits 8-31: Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case..

AWSR [7]

Offset: 0x4a8, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r
AWLTF
r
Toggle fields

AWLTF

Bits 0-7: Analog watchdog low threshold flag AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register..

AWHTF

Bits 8-15: Analog watchdog high threshold flag AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register..

AWCFR [7]

Offset: 0x4ac, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw
CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing '0’ has no effect CLRAWLTF[y]=1: Writing '1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register.

CLRAWHTF

Bits 8-15: Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing '0’ has no effect CLRAWHTF[y]=1: Writing '1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register.

EXMAX [7]

Offset: 0x4b0, size: 32, reset: 0x80000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
rs
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
rs
EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: Extremes detector maximum data channel. These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register..

EXMAX

Bits 8-31: Extremes detector maximum value These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register..

EXMIN [7]

Offset: 0x4b4, size: 32, reset: 0x7FFFFF00, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
rc/w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
rc/w
EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: Extremes detector minimum data channel These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register..

EXMIN

Bits 8-31: Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register..

CNVTIMR [7]

Offset: 0x4b8, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time..

DFSDM2

0x58006c00: Digital filter for sigma delta modulators

168/632 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CFGR1 [0]
0x4 CFGR2 [0]
0x8 AWSCDR [0]
0xc WDATR [0]
0x10 DATINR [0]
0x14 DLYR [0]
0x20 CFGR1 [1]
0x24 CFGR2 [1]
0x28 AWSCDR [1]
0x2c WDATR [1]
0x30 DATINR [1]
0x34 DLYR [1]
0x40 CFGR1 [2]
0x44 CFGR2 [2]
0x48 AWSCDR [2]
0x4c WDATR [2]
0x50 DATINR [2]
0x54 DLYR [2]
0x60 CFGR1 [3]
0x64 CFGR2 [3]
0x68 AWSCDR [3]
0x6c WDATR [3]
0x70 DATINR [3]
0x74 DLYR [3]
0x80 CFGR1 [4]
0x84 CFGR2 [4]
0x88 AWSCDR [4]
0x8c WDATR [4]
0x90 DATINR [4]
0x94 DLYR [4]
0xa0 CFGR1 [5]
0xa4 CFGR2 [5]
0xa8 AWSCDR [5]
0xac WDATR [5]
0xb0 DATINR [5]
0xb4 DLYR [5]
0xc0 CFGR1 [6]
0xc4 CFGR2 [6]
0xc8 AWSCDR [6]
0xcc WDATR [6]
0xd0 DATINR [6]
0xd4 DLYR [6]
0xe0 CFGR1 [7]
0xe4 CFGR2 [7]
0xe8 AWSCDR [7]
0xec WDATR [7]
0xf0 DATINR [7]
0xf4 DLYR [7]
0x100 CR1 [0]
0x104 CR2 [0]
0x108 ISR [0]
0x10c ICR [0]
0x110 JCHGR [0]
0x114 FCR [0]
0x118 JDATAR [0]
0x11c RDATAR [0]
0x120 AWHTR [0]
0x124 AWLTR [0]
0x128 AWSR [0]
0x12c AWCFR [0]
0x130 EXMAX [0]
0x134 EXMIN [0]
0x138 CNVTIMR [0]
0x180 CR1 [1]
0x184 CR2 [1]
0x188 ISR [1]
0x18c ICR [1]
0x190 JCHGR [1]
0x194 FCR [1]
0x198 JDATAR [1]
0x19c RDATAR [1]
0x1a0 AWHTR [1]
0x1a4 AWLTR [1]
0x1a8 AWSR [1]
0x1ac AWCFR [1]
0x1b0 EXMAX [1]
0x1b4 EXMIN [1]
0x1b8 CNVTIMR [1]
0x200 CR1 [2]
0x204 CR2 [2]
0x208 ISR [2]
0x20c ICR [2]
0x210 JCHGR [2]
0x214 FCR [2]
0x218 JDATAR [2]
0x21c RDATAR [2]
0x220 AWHTR [2]
0x224 AWLTR [2]
0x228 AWSR [2]
0x22c AWCFR [2]
0x230 EXMAX [2]
0x234 EXMIN [2]
0x238 CNVTIMR [2]
0x280 CR1 [3]
0x284 CR2 [3]
0x288 ISR [3]
0x28c ICR [3]
0x290 JCHGR [3]
0x294 FCR [3]
0x298 JDATAR [3]
0x29c RDATAR [3]
0x2a0 AWHTR [3]
0x2a4 AWLTR [3]
0x2a8 AWSR [3]
0x2ac AWCFR [3]
0x2b0 EXMAX [3]
0x2b4 EXMIN [3]
0x2b8 CNVTIMR [3]
0x300 CR1 [4]
0x304 CR2 [4]
0x308 ISR [4]
0x30c ICR [4]
0x310 JCHGR [4]
0x314 FCR [4]
0x318 JDATAR [4]
0x31c RDATAR [4]
0x320 AWHTR [4]
0x324 AWLTR [4]
0x328 AWSR [4]
0x32c AWCFR [4]
0x330 EXMAX [4]
0x334 EXMIN [4]
0x338 CNVTIMR [4]
0x380 CR1 [5]
0x384 CR2 [5]
0x388 ISR [5]
0x38c ICR [5]
0x390 JCHGR [5]
0x394 FCR [5]
0x398 JDATAR [5]
0x39c RDATAR [5]
0x3a0 AWHTR [5]
0x3a4 AWLTR [5]
0x3a8 AWSR [5]
0x3ac AWCFR [5]
0x3b0 EXMAX [5]
0x3b4 EXMIN [5]
0x3b8 CNVTIMR [5]
0x400 CR1 [6]
0x404 CR2 [6]
0x408 ISR [6]
0x40c ICR [6]
0x410 JCHGR [6]
0x414 FCR [6]
0x418 JDATAR [6]
0x41c RDATAR [6]
0x420 AWHTR [6]
0x424 AWLTR [6]
0x428 AWSR [6]
0x42c AWCFR [6]
0x430 EXMAX [6]
0x434 EXMIN [6]
0x438 CNVTIMR [6]
0x480 CR1 [7]
0x484 CR2 [7]
0x488 ISR [7]
0x48c ICR [7]
0x490 JCHGR [7]
0x494 FCR [7]
0x498 JDATAR [7]
0x49c RDATAR [7]
0x4a0 AWHTR [7]
0x4a4 AWLTR [7]
0x4a8 AWSR [7]
0x4ac AWCFR [7]
0x4b0 EXMAX [7]
0x4b4 EXMIN [7]
0x4b8 CNVTIMR [7]
Toggle registers

CFGR1 [0]

DFSDM channel 0 configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw
CKOUTSRC
rw
CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw
DATMPX
rw
CHINSEL
rw
CHEN
rw
CKABEN
rw
SCDEN
rw
SPICKSEL
rw
SITP
rw
Toggle fields

SITP

Bits 0-1: Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register)..

SPICKSEL

Bits 2-3: SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

SCDEN

Bit 5: Short-circuit detector enable on channel y.

CKABEN

Bit 6: Clock absence detector enable on channel y.

CHEN

Bit 7: Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting..

CHINSEL

Bit 8: Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

DATMPX

Bits 12-13: Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

DATPACK

Bits 14-15: Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

CKOUTDIV

Bits 16-23: Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -.

CKOUTSRC

Bit 30: Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0).

DFSDMEN

Bit 31: Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0).

CFGR2 [0]

DFSDM channel 0 configuration register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right.

OFFSET

Bits 8-31: 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software..

AWSCDR [0]

DFSDM channel 0 analog watchdog and short-circuit detector register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw
AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw
SCDT
rw
Toggle fields

SCDT

Bits 0-7: short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel..

BKSCD

Bits 12-15: Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y.

AWFOSR

Bits 16-20: Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is.

AWFORD

Bits 22-23: Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

WDATR [0]

DFSDM channel 0 watchdog filter data register

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
r
Toggle fields

WDATA

Bits 0-15: Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3)..

DATINR [0]

DFSDM channel 0 data input register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format..

INDAT1

Bits 16-31: Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format..

DLYR [0]

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied.

CFGR1 [1]

DFSDM channel 0 configuration register

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw
CKOUTSRC
rw
CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw
DATMPX
rw
CHINSEL
rw
CHEN
rw
CKABEN
rw
SCDEN
rw
SPICKSEL
rw
SITP
rw
Toggle fields

SITP

Bits 0-1: Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register)..

SPICKSEL

Bits 2-3: SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

SCDEN

Bit 5: Short-circuit detector enable on channel y.

CKABEN

Bit 6: Clock absence detector enable on channel y.

CHEN

Bit 7: Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting..

CHINSEL

Bit 8: Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

DATMPX

Bits 12-13: Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

DATPACK

Bits 14-15: Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

CKOUTDIV

Bits 16-23: Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -.

CKOUTSRC

Bit 30: Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0).

DFSDMEN

Bit 31: Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0).

CFGR2 [1]

DFSDM channel 0 configuration register

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right.

OFFSET

Bits 8-31: 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software..

AWSCDR [1]

DFSDM channel 0 analog watchdog and short-circuit detector register

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw
AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw
SCDT
rw
Toggle fields

SCDT

Bits 0-7: short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel..

BKSCD

Bits 12-15: Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y.

AWFOSR

Bits 16-20: Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is.

AWFORD

Bits 22-23: Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

WDATR [1]

DFSDM channel 0 watchdog filter data register

Offset: 0x2c, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
r
Toggle fields

WDATA

Bits 0-15: Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3)..

DATINR [1]

DFSDM channel 0 data input register

Offset: 0x30, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format..

INDAT1

Bits 16-31: Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format..

DLYR [1]

Offset: 0x34, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied.

CFGR1 [2]

DFSDM channel 0 configuration register

Offset: 0x40, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw
CKOUTSRC
rw
CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw
DATMPX
rw
CHINSEL
rw
CHEN
rw
CKABEN
rw
SCDEN
rw
SPICKSEL
rw
SITP
rw
Toggle fields

SITP

Bits 0-1: Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register)..

SPICKSEL

Bits 2-3: SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

SCDEN

Bit 5: Short-circuit detector enable on channel y.

CKABEN

Bit 6: Clock absence detector enable on channel y.

CHEN

Bit 7: Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting..

CHINSEL

Bit 8: Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

DATMPX

Bits 12-13: Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

DATPACK

Bits 14-15: Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

CKOUTDIV

Bits 16-23: Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -.

CKOUTSRC

Bit 30: Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0).

DFSDMEN

Bit 31: Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0).

CFGR2 [2]

DFSDM channel 0 configuration register

Offset: 0x44, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right.

OFFSET

Bits 8-31: 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software..

AWSCDR [2]

DFSDM channel 0 analog watchdog and short-circuit detector register

Offset: 0x48, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw
AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw
SCDT
rw
Toggle fields

SCDT

Bits 0-7: short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel..

BKSCD

Bits 12-15: Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y.

AWFOSR

Bits 16-20: Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is.

AWFORD

Bits 22-23: Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

WDATR [2]

DFSDM channel 0 watchdog filter data register

Offset: 0x4c, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
r
Toggle fields

WDATA

Bits 0-15: Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3)..

DATINR [2]

DFSDM channel 0 data input register

Offset: 0x50, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format..

INDAT1

Bits 16-31: Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format..

DLYR [2]

Offset: 0x54, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied.

CFGR1 [3]

DFSDM channel 0 configuration register

Offset: 0x60, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw
CKOUTSRC
rw
CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw
DATMPX
rw
CHINSEL
rw
CHEN
rw
CKABEN
rw
SCDEN
rw
SPICKSEL
rw
SITP
rw
Toggle fields

SITP

Bits 0-1: Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register)..

SPICKSEL

Bits 2-3: SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

SCDEN

Bit 5: Short-circuit detector enable on channel y.

CKABEN

Bit 6: Clock absence detector enable on channel y.

CHEN

Bit 7: Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting..

CHINSEL

Bit 8: Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

DATMPX

Bits 12-13: Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

DATPACK

Bits 14-15: Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

CKOUTDIV

Bits 16-23: Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -.

CKOUTSRC

Bit 30: Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0).

DFSDMEN

Bit 31: Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0).

CFGR2 [3]

DFSDM channel 0 configuration register

Offset: 0x64, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right.

OFFSET

Bits 8-31: 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software..

AWSCDR [3]

DFSDM channel 0 analog watchdog and short-circuit detector register

Offset: 0x68, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw
AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw
SCDT
rw
Toggle fields

SCDT

Bits 0-7: short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel..

BKSCD

Bits 12-15: Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y.

AWFOSR

Bits 16-20: Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is.

AWFORD

Bits 22-23: Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

WDATR [3]

DFSDM channel 0 watchdog filter data register

Offset: 0x6c, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
r
Toggle fields

WDATA

Bits 0-15: Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3)..

DATINR [3]

DFSDM channel 0 data input register

Offset: 0x70, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format..

INDAT1

Bits 16-31: Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format..

DLYR [3]

Offset: 0x74, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied.

CFGR1 [4]

DFSDM channel 0 configuration register

Offset: 0x80, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw
CKOUTSRC
rw
CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw
DATMPX
rw
CHINSEL
rw
CHEN
rw
CKABEN
rw
SCDEN
rw
SPICKSEL
rw
SITP
rw
Toggle fields

SITP

Bits 0-1: Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register)..

SPICKSEL

Bits 2-3: SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

SCDEN

Bit 5: Short-circuit detector enable on channel y.

CKABEN

Bit 6: Clock absence detector enable on channel y.

CHEN

Bit 7: Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting..

CHINSEL

Bit 8: Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

DATMPX

Bits 12-13: Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

DATPACK

Bits 14-15: Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

CKOUTDIV

Bits 16-23: Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -.

CKOUTSRC

Bit 30: Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0).

DFSDMEN

Bit 31: Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0).

CFGR2 [4]

DFSDM channel 0 configuration register

Offset: 0x84, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right.

OFFSET

Bits 8-31: 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software..

AWSCDR [4]

DFSDM channel 0 analog watchdog and short-circuit detector register

Offset: 0x88, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw
AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw
SCDT
rw
Toggle fields

SCDT

Bits 0-7: short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel..

BKSCD

Bits 12-15: Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y.

AWFOSR

Bits 16-20: Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is.

AWFORD

Bits 22-23: Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

WDATR [4]

DFSDM channel 0 watchdog filter data register

Offset: 0x8c, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
r
Toggle fields

WDATA

Bits 0-15: Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3)..

DATINR [4]

DFSDM channel 0 data input register

Offset: 0x90, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format..

INDAT1

Bits 16-31: Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format..

DLYR [4]

Offset: 0x94, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied.

CFGR1 [5]

DFSDM channel 0 configuration register

Offset: 0xa0, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw
CKOUTSRC
rw
CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw
DATMPX
rw
CHINSEL
rw
CHEN
rw
CKABEN
rw
SCDEN
rw
SPICKSEL
rw
SITP
rw
Toggle fields

SITP

Bits 0-1: Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register)..

SPICKSEL

Bits 2-3: SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

SCDEN

Bit 5: Short-circuit detector enable on channel y.

CKABEN

Bit 6: Clock absence detector enable on channel y.

CHEN

Bit 7: Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting..

CHINSEL

Bit 8: Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

DATMPX

Bits 12-13: Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

DATPACK

Bits 14-15: Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

CKOUTDIV

Bits 16-23: Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -.

CKOUTSRC

Bit 30: Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0).

DFSDMEN

Bit 31: Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0).

CFGR2 [5]

DFSDM channel 0 configuration register

Offset: 0xa4, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right.

OFFSET

Bits 8-31: 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software..

AWSCDR [5]

DFSDM channel 0 analog watchdog and short-circuit detector register

Offset: 0xa8, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw
AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw
SCDT
rw
Toggle fields

SCDT

Bits 0-7: short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel..

BKSCD

Bits 12-15: Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y.

AWFOSR

Bits 16-20: Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is.

AWFORD

Bits 22-23: Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

WDATR [5]

DFSDM channel 0 watchdog filter data register

Offset: 0xac, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
r
Toggle fields

WDATA

Bits 0-15: Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3)..

DATINR [5]

DFSDM channel 0 data input register

Offset: 0xb0, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format..

INDAT1

Bits 16-31: Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format..

DLYR [5]

Offset: 0xb4, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied.

CFGR1 [6]

DFSDM channel 0 configuration register

Offset: 0xc0, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw
CKOUTSRC
rw
CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw
DATMPX
rw
CHINSEL
rw
CHEN
rw
CKABEN
rw
SCDEN
rw
SPICKSEL
rw
SITP
rw
Toggle fields

SITP

Bits 0-1: Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register)..

SPICKSEL

Bits 2-3: SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

SCDEN

Bit 5: Short-circuit detector enable on channel y.

CKABEN

Bit 6: Clock absence detector enable on channel y.

CHEN

Bit 7: Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting..

CHINSEL

Bit 8: Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

DATMPX

Bits 12-13: Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

DATPACK

Bits 14-15: Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

CKOUTDIV

Bits 16-23: Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -.

CKOUTSRC

Bit 30: Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0).

DFSDMEN

Bit 31: Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0).

CFGR2 [6]

DFSDM channel 0 configuration register

Offset: 0xc4, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right.

OFFSET

Bits 8-31: 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software..

AWSCDR [6]

DFSDM channel 0 analog watchdog and short-circuit detector register

Offset: 0xc8, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw
AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw
SCDT
rw
Toggle fields

SCDT

Bits 0-7: short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel..

BKSCD

Bits 12-15: Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y.

AWFOSR

Bits 16-20: Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is.

AWFORD

Bits 22-23: Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

WDATR [6]

DFSDM channel 0 watchdog filter data register

Offset: 0xcc, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
r
Toggle fields

WDATA

Bits 0-15: Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3)..

DATINR [6]

DFSDM channel 0 data input register

Offset: 0xd0, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format..

INDAT1

Bits 16-31: Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format..

DLYR [6]

Offset: 0xd4, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied.

CFGR1 [7]

DFSDM channel 0 configuration register

Offset: 0xe0, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw
CKOUTSRC
rw
CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw
DATMPX
rw
CHINSEL
rw
CHEN
rw
CKABEN
rw
SCDEN
rw
SPICKSEL
rw
SITP
rw
Toggle fields

SITP

Bits 0-1: Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register)..

SPICKSEL

Bits 2-3: SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

SCDEN

Bit 5: Short-circuit detector enable on channel y.

CKABEN

Bit 6: Clock absence detector enable on channel y.

CHEN

Bit 7: Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting..

CHINSEL

Bit 8: Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

DATMPX

Bits 12-13: Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

DATPACK

Bits 14-15: Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

CKOUTDIV

Bits 16-23: Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -.

CKOUTSRC

Bit 30: Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0).

DFSDMEN

Bit 31: Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0).

CFGR2 [7]

DFSDM channel 0 configuration register

Offset: 0xe4, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right.

OFFSET

Bits 8-31: 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software..

AWSCDR [7]

DFSDM channel 0 analog watchdog and short-circuit detector register

Offset: 0xe8, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw
AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw
SCDT
rw
Toggle fields

SCDT

Bits 0-7: short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel..

BKSCD

Bits 12-15: Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y.

AWFOSR

Bits 16-20: Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is.

AWFORD

Bits 22-23: Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register)..

WDATR [7]

DFSDM channel 0 watchdog filter data register

Offset: 0xec, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
r
Toggle fields

WDATA

Bits 0-15: Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3)..

DATINR [7]

DFSDM channel 0 data input register

Offset: 0xf0, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format..

INDAT1

Bits 16-31: Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format..

DLYR [7]

Offset: 0xf4, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied.

CR1 [0]

Offset: 0x100, size: 32, reset: 0x00000000, access: Unspecified

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw
FAST
rw
RCH
rw
RDMAEN
rw
RSYNC
rw
RCONT
rw
RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw
JEXTSEL
rw
JDMAEN
rw
JSCAN
rw
JSYNC
rw
JSWSTART
rw
DFEN
rw
Toggle fields

DFEN

Bit 0: DFSDM_FLTx enable Data which are cleared by setting DFEN=0: register DFSDM_FLTxISR is set to the reset state register DFSDM_FLTxAWSR is set to the reset state.

JSWSTART

Bit 1: Start a conversion of the injected group of channels This bit is always read as '0’..

JSYNC

Bit 3: Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

JSCAN

Bit 4: Scanning conversion mode for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel..

JDMAEN

Bit 5: DMA channel enabled to read data for the injected channel group This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

JEXTSEL

Bits 8-12: Trigger signal selection for launching injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). DFSDM_FLTx 0x00 dfsdm_jtrg0 0x01 dfsdm_jtrg1 ... 0x1E dfsdm_jtrg30 0x1F dfsdm_jtrg31 Refer to . 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger)..

JEXTEN

Bits 13-14: Trigger enable and trigger edge selection for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RSWSTART

Bit 17: Software start of a conversion on the regular channel This bit is always read as '0’..

RCONT

Bit 18: Continuous mode selection for regular conversions Writing '0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately..

RSYNC

Bit 19: Launch regular conversion synchronously with DFSDM_FLT0 This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RDMAEN

Bit 21: DMA channel enabled to read data for the regular conversion This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RCH

Bits 24-26: Regular channel selection ... 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion)..

FAST

Bit 29: Fast conversion mode selection for regular conversions When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (... but CNVCNT=0) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input..

AWFSEL

Bit 30: Analog watchdog fast mode select.

CR2 [0]

Offset: 0x104, size: 32, reset: 0x00000000, access: Unspecified

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw
CKABIE
rw
SCDIE
rw
AWDIE
rw
ROVRIE
rw
JOVRIE
rw
REOCIE
rw
JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: Injected end of conversion interrupt enable Please see the explanation of JEOCF in DFSDM_FLTxISR..

REOCIE

Bit 1: Regular end of conversion interrupt enable Please see the explanation of REOCF in DFSDM_FLTxISR..

JOVRIE

Bit 2: Injected data overrun interrupt enable Please see the explanation of JOVRF in DFSDM_FLTxISR..

ROVRIE

Bit 3: Regular data overrun interrupt enable Please see the explanation of ROVRF in DFSDM_FLTxISR..

AWDIE

Bit 4: Analog watchdog interrupt enable Please see the explanation of AWDF in DFSDM_FLTxISR..

SCDIE

Bit 5: Short-circuit detector interrupt enable Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR. Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0).

CKABIE

Bit 6: Clock absence interrupt enable Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR. Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0).

EXCH

Bits 8-15: Extremes detector channel selection These bits select the input channels to be taken by the Extremes detector. EXCH[y] = 0: Extremes detector does not accept data from channel y EXCH[y] = 1: Extremes detector accepts data from channel y.

AWDCH

Bits 16-23: Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog. AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y.

ISR [0]

Offset: 0x108, size: 32, reset: 0x00FF0000, access: Unspecified

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r
CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r
JCIP
r
AWDF
r
ROVRF
r
JOVRF
r
REOCF
r
JEOCF
r
Toggle fields

JEOCF

Bit 0: End of injected conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR..

REOCF

Bit 1: End of regular conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR..

JOVRF

Bit 2: Injected conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register..

ROVRF

Bit 3: Regular conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register..

AWDF

Bit 4: Analog watchdog This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1’ into the clear bits in DFSDM_FLTxAWCFR register)..

JCIP

Bit 13: Injected conversion in progress status A request to start an injected conversion is ignored when JCIP=1..

RCIP

Bit 14: Regular conversion in progress status A request to start a regular conversion is ignored when RCIP=1..

CKABF

Bits 16-23: Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0).

SCDF

Bits 24-31: short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0).

ICR [0]

Offset: 0x10c, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw
CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw
CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: Clear the injected conversion overrun flag.

CLRROVRF

Bit 3: Clear the regular conversion overrun flag.

CLRCKABF

Bits 16-23: Clear the clock absence flag CLRCKABF[y]=0: Writing '0’ has no effect CLRCKABF[y]=1: Writing '1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0).

CLRSCDF

Bits 24-31: Clear the short-circuit detector flag CLRSCDF[y]=0: Writing '0’ has no effect CLRSCDF[y]=1: Writing '1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0).

JCHGR [0]

Offset: 0x110, size: 32, reset: 0x00000001, access: Unspecified

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored..

FCR [0]

Offset: 0x114, size: 32, reset: 0x00000000, access: Unspecified

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw
FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: Integrator oversampling ratio (averaging length) from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). 0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples.

FOSR

Bits 16-25: Sinc filter oversampling ratio (decimation rate) number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If FOSR = 0, then the filter has no effect (filter bypass). 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This.

FORD

Bits 29-31: Sinc filter order 2: Sinc2 filter type 3: Sinc3 filter type 4: Sinc4 filter type 5: Sinc5 filter type 6-7: Reserved Sincx filter type transfer function: FastSinc filter type transfer function: This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)..

JDATAR [0]

Offset: 0x118, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
JDATACH
r
Toggle fields

JDATACH

Bits 0-2: Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0]..

JDATA

Bits 8-31: Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF..

RDATAR [0]

Offset: 0x11c, size: 32, reset: 0x00000000, access: Unspecified

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
RPEND
r
RDATACH
r
Toggle fields

RDATACH

Bits 0-2: Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0]..

RPEND

Bit 4: Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion.

RDATA

Bits 8-31: Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF..

AWHTR [0]

Offset: 0x120, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw
BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: Break signal assignment to analog watchdog high threshold event BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event.

AWHT

Bits 8-31: Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case..

AWLTR [0]

Offset: 0x124, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw
BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: Break signal assignment to analog watchdog low threshold event BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event.

AWLT

Bits 8-31: Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case..

AWSR [0]

Offset: 0x128, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r
AWLTF
r
Toggle fields

AWLTF

Bits 0-7: Analog watchdog low threshold flag AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register..

AWHTF

Bits 8-15: Analog watchdog high threshold flag AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register..

AWCFR [0]

Offset: 0x12c, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw
CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing '0’ has no effect CLRAWLTF[y]=1: Writing '1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register.

CLRAWHTF

Bits 8-15: Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing '0’ has no effect CLRAWHTF[y]=1: Writing '1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register.

EXMAX [0]

Offset: 0x130, size: 32, reset: 0x80000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
rs
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
rs
EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: Extremes detector maximum data channel. These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register..

EXMAX

Bits 8-31: Extremes detector maximum value These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register..

EXMIN [0]

Offset: 0x134, size: 32, reset: 0x7FFFFF00, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
rc/w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
rc/w
EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: Extremes detector minimum data channel These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register..

EXMIN

Bits 8-31: Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register..

CNVTIMR [0]

Offset: 0x138, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time..

CR1 [1]

Offset: 0x180, size: 32, reset: 0x00000000, access: Unspecified

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw
FAST
rw
RCH
rw
RDMAEN
rw
RSYNC
rw
RCONT
rw
RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw
JEXTSEL
rw
JDMAEN
rw
JSCAN
rw
JSYNC
rw
JSWSTART
rw
DFEN
rw
Toggle fields

DFEN

Bit 0: DFSDM_FLTx enable Data which are cleared by setting DFEN=0: register DFSDM_FLTxISR is set to the reset state register DFSDM_FLTxAWSR is set to the reset state.

JSWSTART

Bit 1: Start a conversion of the injected group of channels This bit is always read as '0’..

JSYNC

Bit 3: Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

JSCAN

Bit 4: Scanning conversion mode for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel..

JDMAEN

Bit 5: DMA channel enabled to read data for the injected channel group This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

JEXTSEL

Bits 8-12: Trigger signal selection for launching injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). DFSDM_FLTx 0x00 dfsdm_jtrg0 0x01 dfsdm_jtrg1 ... 0x1E dfsdm_jtrg30 0x1F dfsdm_jtrg31 Refer to . 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger)..

JEXTEN

Bits 13-14: Trigger enable and trigger edge selection for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RSWSTART

Bit 17: Software start of a conversion on the regular channel This bit is always read as '0’..

RCONT

Bit 18: Continuous mode selection for regular conversions Writing '0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately..

RSYNC

Bit 19: Launch regular conversion synchronously with DFSDM_FLT0 This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RDMAEN

Bit 21: DMA channel enabled to read data for the regular conversion This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RCH

Bits 24-26: Regular channel selection ... 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion)..

FAST

Bit 29: Fast conversion mode selection for regular conversions When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (... but CNVCNT=0) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input..

AWFSEL

Bit 30: Analog watchdog fast mode select.

CR2 [1]

Offset: 0x184, size: 32, reset: 0x00000000, access: Unspecified

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw
CKABIE
rw
SCDIE
rw
AWDIE
rw
ROVRIE
rw
JOVRIE
rw
REOCIE
rw
JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: Injected end of conversion interrupt enable Please see the explanation of JEOCF in DFSDM_FLTxISR..

REOCIE

Bit 1: Regular end of conversion interrupt enable Please see the explanation of REOCF in DFSDM_FLTxISR..

JOVRIE

Bit 2: Injected data overrun interrupt enable Please see the explanation of JOVRF in DFSDM_FLTxISR..

ROVRIE

Bit 3: Regular data overrun interrupt enable Please see the explanation of ROVRF in DFSDM_FLTxISR..

AWDIE

Bit 4: Analog watchdog interrupt enable Please see the explanation of AWDF in DFSDM_FLTxISR..

SCDIE

Bit 5: Short-circuit detector interrupt enable Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR. Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0).

CKABIE

Bit 6: Clock absence interrupt enable Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR. Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0).

EXCH

Bits 8-15: Extremes detector channel selection These bits select the input channels to be taken by the Extremes detector. EXCH[y] = 0: Extremes detector does not accept data from channel y EXCH[y] = 1: Extremes detector accepts data from channel y.

AWDCH

Bits 16-23: Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog. AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y.

ISR [1]

Offset: 0x188, size: 32, reset: 0x00FF0000, access: Unspecified

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r
CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r
JCIP
r
AWDF
r
ROVRF
r
JOVRF
r
REOCF
r
JEOCF
r
Toggle fields

JEOCF

Bit 0: End of injected conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR..

REOCF

Bit 1: End of regular conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR..

JOVRF

Bit 2: Injected conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register..

ROVRF

Bit 3: Regular conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register..

AWDF

Bit 4: Analog watchdog This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1’ into the clear bits in DFSDM_FLTxAWCFR register)..

JCIP

Bit 13: Injected conversion in progress status A request to start an injected conversion is ignored when JCIP=1..

RCIP

Bit 14: Regular conversion in progress status A request to start a regular conversion is ignored when RCIP=1..

CKABF

Bits 16-23: Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0).

SCDF

Bits 24-31: short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0).

ICR [1]

Offset: 0x18c, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw
CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw
CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: Clear the injected conversion overrun flag.

CLRROVRF

Bit 3: Clear the regular conversion overrun flag.

CLRCKABF

Bits 16-23: Clear the clock absence flag CLRCKABF[y]=0: Writing '0’ has no effect CLRCKABF[y]=1: Writing '1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0).

CLRSCDF

Bits 24-31: Clear the short-circuit detector flag CLRSCDF[y]=0: Writing '0’ has no effect CLRSCDF[y]=1: Writing '1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0).

JCHGR [1]

Offset: 0x190, size: 32, reset: 0x00000001, access: Unspecified

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored..

FCR [1]

Offset: 0x194, size: 32, reset: 0x00000000, access: Unspecified

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw
FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: Integrator oversampling ratio (averaging length) from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). 0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples.

FOSR

Bits 16-25: Sinc filter oversampling ratio (decimation rate) number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If FOSR = 0, then the filter has no effect (filter bypass). 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This.

FORD

Bits 29-31: Sinc filter order 2: Sinc2 filter type 3: Sinc3 filter type 4: Sinc4 filter type 5: Sinc5 filter type 6-7: Reserved Sincx filter type transfer function: FastSinc filter type transfer function: This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)..

JDATAR [1]

Offset: 0x198, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
JDATACH
r
Toggle fields

JDATACH

Bits 0-2: Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0]..

JDATA

Bits 8-31: Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF..

RDATAR [1]

Offset: 0x19c, size: 32, reset: 0x00000000, access: Unspecified

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
RPEND
r
RDATACH
r
Toggle fields

RDATACH

Bits 0-2: Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0]..

RPEND

Bit 4: Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion.

RDATA

Bits 8-31: Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF..

AWHTR [1]

Offset: 0x1a0, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw
BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: Break signal assignment to analog watchdog high threshold event BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event.

AWHT

Bits 8-31: Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case..

AWLTR [1]

Offset: 0x1a4, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw
BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: Break signal assignment to analog watchdog low threshold event BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event.

AWLT

Bits 8-31: Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case..

AWSR [1]

Offset: 0x1a8, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r
AWLTF
r
Toggle fields

AWLTF

Bits 0-7: Analog watchdog low threshold flag AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register..

AWHTF

Bits 8-15: Analog watchdog high threshold flag AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register..

AWCFR [1]

Offset: 0x1ac, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw
CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing '0’ has no effect CLRAWLTF[y]=1: Writing '1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register.

CLRAWHTF

Bits 8-15: Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing '0’ has no effect CLRAWHTF[y]=1: Writing '1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register.

EXMAX [1]

Offset: 0x1b0, size: 32, reset: 0x80000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
rs
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
rs
EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: Extremes detector maximum data channel. These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register..

EXMAX

Bits 8-31: Extremes detector maximum value These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register..

EXMIN [1]

Offset: 0x1b4, size: 32, reset: 0x7FFFFF00, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
rc/w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
rc/w
EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: Extremes detector minimum data channel These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register..

EXMIN

Bits 8-31: Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register..

CNVTIMR [1]

Offset: 0x1b8, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time..

CR1 [2]

Offset: 0x200, size: 32, reset: 0x00000000, access: Unspecified

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw
FAST
rw
RCH
rw
RDMAEN
rw
RSYNC
rw
RCONT
rw
RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw
JEXTSEL
rw
JDMAEN
rw
JSCAN
rw
JSYNC
rw
JSWSTART
rw
DFEN
rw
Toggle fields

DFEN

Bit 0: DFSDM_FLTx enable Data which are cleared by setting DFEN=0: register DFSDM_FLTxISR is set to the reset state register DFSDM_FLTxAWSR is set to the reset state.

JSWSTART

Bit 1: Start a conversion of the injected group of channels This bit is always read as '0’..

JSYNC

Bit 3: Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

JSCAN

Bit 4: Scanning conversion mode for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel..

JDMAEN

Bit 5: DMA channel enabled to read data for the injected channel group This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

JEXTSEL

Bits 8-12: Trigger signal selection for launching injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). DFSDM_FLTx 0x00 dfsdm_jtrg0 0x01 dfsdm_jtrg1 ... 0x1E dfsdm_jtrg30 0x1F dfsdm_jtrg31 Refer to . 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger)..

JEXTEN

Bits 13-14: Trigger enable and trigger edge selection for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RSWSTART

Bit 17: Software start of a conversion on the regular channel This bit is always read as '0’..

RCONT

Bit 18: Continuous mode selection for regular conversions Writing '0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately..

RSYNC

Bit 19: Launch regular conversion synchronously with DFSDM_FLT0 This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RDMAEN

Bit 21: DMA channel enabled to read data for the regular conversion This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RCH

Bits 24-26: Regular channel selection ... 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion)..

FAST

Bit 29: Fast conversion mode selection for regular conversions When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (... but CNVCNT=0) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input..

AWFSEL

Bit 30: Analog watchdog fast mode select.

CR2 [2]

Offset: 0x204, size: 32, reset: 0x00000000, access: Unspecified

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw
CKABIE
rw
SCDIE
rw
AWDIE
rw
ROVRIE
rw
JOVRIE
rw
REOCIE
rw
JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: Injected end of conversion interrupt enable Please see the explanation of JEOCF in DFSDM_FLTxISR..

REOCIE

Bit 1: Regular end of conversion interrupt enable Please see the explanation of REOCF in DFSDM_FLTxISR..

JOVRIE

Bit 2: Injected data overrun interrupt enable Please see the explanation of JOVRF in DFSDM_FLTxISR..

ROVRIE

Bit 3: Regular data overrun interrupt enable Please see the explanation of ROVRF in DFSDM_FLTxISR..

AWDIE

Bit 4: Analog watchdog interrupt enable Please see the explanation of AWDF in DFSDM_FLTxISR..

SCDIE

Bit 5: Short-circuit detector interrupt enable Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR. Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0).

CKABIE

Bit 6: Clock absence interrupt enable Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR. Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0).

EXCH

Bits 8-15: Extremes detector channel selection These bits select the input channels to be taken by the Extremes detector. EXCH[y] = 0: Extremes detector does not accept data from channel y EXCH[y] = 1: Extremes detector accepts data from channel y.

AWDCH

Bits 16-23: Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog. AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y.

ISR [2]

Offset: 0x208, size: 32, reset: 0x00FF0000, access: Unspecified

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r
CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r
JCIP
r
AWDF
r
ROVRF
r
JOVRF
r
REOCF
r
JEOCF
r
Toggle fields

JEOCF

Bit 0: End of injected conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR..

REOCF

Bit 1: End of regular conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR..

JOVRF

Bit 2: Injected conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register..

ROVRF

Bit 3: Regular conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register..

AWDF

Bit 4: Analog watchdog This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1’ into the clear bits in DFSDM_FLTxAWCFR register)..

JCIP

Bit 13: Injected conversion in progress status A request to start an injected conversion is ignored when JCIP=1..

RCIP

Bit 14: Regular conversion in progress status A request to start a regular conversion is ignored when RCIP=1..

CKABF

Bits 16-23: Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0).

SCDF

Bits 24-31: short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0).

ICR [2]

Offset: 0x20c, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw
CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw
CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: Clear the injected conversion overrun flag.

CLRROVRF

Bit 3: Clear the regular conversion overrun flag.

CLRCKABF

Bits 16-23: Clear the clock absence flag CLRCKABF[y]=0: Writing '0’ has no effect CLRCKABF[y]=1: Writing '1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0).

CLRSCDF

Bits 24-31: Clear the short-circuit detector flag CLRSCDF[y]=0: Writing '0’ has no effect CLRSCDF[y]=1: Writing '1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0).

JCHGR [2]

Offset: 0x210, size: 32, reset: 0x00000001, access: Unspecified

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored..

FCR [2]

Offset: 0x214, size: 32, reset: 0x00000000, access: Unspecified

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw
FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: Integrator oversampling ratio (averaging length) from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). 0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples.

FOSR

Bits 16-25: Sinc filter oversampling ratio (decimation rate) number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If FOSR = 0, then the filter has no effect (filter bypass). 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This.

FORD

Bits 29-31: Sinc filter order 2: Sinc2 filter type 3: Sinc3 filter type 4: Sinc4 filter type 5: Sinc5 filter type 6-7: Reserved Sincx filter type transfer function: FastSinc filter type transfer function: This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)..

JDATAR [2]

Offset: 0x218, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
JDATACH
r
Toggle fields

JDATACH

Bits 0-2: Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0]..

JDATA

Bits 8-31: Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF..

RDATAR [2]

Offset: 0x21c, size: 32, reset: 0x00000000, access: Unspecified

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
RPEND
r
RDATACH
r
Toggle fields

RDATACH

Bits 0-2: Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0]..

RPEND

Bit 4: Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion.

RDATA

Bits 8-31: Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF..

AWHTR [2]

Offset: 0x220, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw
BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: Break signal assignment to analog watchdog high threshold event BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event.

AWHT

Bits 8-31: Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case..

AWLTR [2]

Offset: 0x224, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw
BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: Break signal assignment to analog watchdog low threshold event BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event.

AWLT

Bits 8-31: Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case..

AWSR [2]

Offset: 0x228, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r
AWLTF
r
Toggle fields

AWLTF

Bits 0-7: Analog watchdog low threshold flag AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register..

AWHTF

Bits 8-15: Analog watchdog high threshold flag AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register..

AWCFR [2]

Offset: 0x22c, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw
CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing '0’ has no effect CLRAWLTF[y]=1: Writing '1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register.

CLRAWHTF

Bits 8-15: Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing '0’ has no effect CLRAWHTF[y]=1: Writing '1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register.

EXMAX [2]

Offset: 0x230, size: 32, reset: 0x80000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
rs
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
rs
EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: Extremes detector maximum data channel. These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register..

EXMAX

Bits 8-31: Extremes detector maximum value These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register..

EXMIN [2]

Offset: 0x234, size: 32, reset: 0x7FFFFF00, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
rc/w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
rc/w
EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: Extremes detector minimum data channel These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register..

EXMIN

Bits 8-31: Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register..

CNVTIMR [2]

Offset: 0x238, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time..

CR1 [3]

Offset: 0x280, size: 32, reset: 0x00000000, access: Unspecified

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw
FAST
rw
RCH
rw
RDMAEN
rw
RSYNC
rw
RCONT
rw
RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw
JEXTSEL
rw
JDMAEN
rw
JSCAN
rw
JSYNC
rw
JSWSTART
rw
DFEN
rw
Toggle fields

DFEN

Bit 0: DFSDM_FLTx enable Data which are cleared by setting DFEN=0: register DFSDM_FLTxISR is set to the reset state register DFSDM_FLTxAWSR is set to the reset state.

JSWSTART

Bit 1: Start a conversion of the injected group of channels This bit is always read as '0’..

JSYNC

Bit 3: Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

JSCAN

Bit 4: Scanning conversion mode for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel..

JDMAEN

Bit 5: DMA channel enabled to read data for the injected channel group This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

JEXTSEL

Bits 8-12: Trigger signal selection for launching injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). DFSDM_FLTx 0x00 dfsdm_jtrg0 0x01 dfsdm_jtrg1 ... 0x1E dfsdm_jtrg30 0x1F dfsdm_jtrg31 Refer to . 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger)..

JEXTEN

Bits 13-14: Trigger enable and trigger edge selection for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RSWSTART

Bit 17: Software start of a conversion on the regular channel This bit is always read as '0’..

RCONT

Bit 18: Continuous mode selection for regular conversions Writing '0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately..

RSYNC

Bit 19: Launch regular conversion synchronously with DFSDM_FLT0 This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RDMAEN

Bit 21: DMA channel enabled to read data for the regular conversion This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RCH

Bits 24-26: Regular channel selection ... 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion)..

FAST

Bit 29: Fast conversion mode selection for regular conversions When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (... but CNVCNT=0) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input..

AWFSEL

Bit 30: Analog watchdog fast mode select.

CR2 [3]

Offset: 0x284, size: 32, reset: 0x00000000, access: Unspecified

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw
CKABIE
rw
SCDIE
rw
AWDIE
rw
ROVRIE
rw
JOVRIE
rw
REOCIE
rw
JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: Injected end of conversion interrupt enable Please see the explanation of JEOCF in DFSDM_FLTxISR..

REOCIE

Bit 1: Regular end of conversion interrupt enable Please see the explanation of REOCF in DFSDM_FLTxISR..

JOVRIE

Bit 2: Injected data overrun interrupt enable Please see the explanation of JOVRF in DFSDM_FLTxISR..

ROVRIE

Bit 3: Regular data overrun interrupt enable Please see the explanation of ROVRF in DFSDM_FLTxISR..

AWDIE

Bit 4: Analog watchdog interrupt enable Please see the explanation of AWDF in DFSDM_FLTxISR..

SCDIE

Bit 5: Short-circuit detector interrupt enable Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR. Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0).

CKABIE

Bit 6: Clock absence interrupt enable Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR. Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0).

EXCH

Bits 8-15: Extremes detector channel selection These bits select the input channels to be taken by the Extremes detector. EXCH[y] = 0: Extremes detector does not accept data from channel y EXCH[y] = 1: Extremes detector accepts data from channel y.

AWDCH

Bits 16-23: Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog. AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y.

ISR [3]

Offset: 0x288, size: 32, reset: 0x00FF0000, access: Unspecified

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r
CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r
JCIP
r
AWDF
r
ROVRF
r
JOVRF
r
REOCF
r
JEOCF
r
Toggle fields

JEOCF

Bit 0: End of injected conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR..

REOCF

Bit 1: End of regular conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR..

JOVRF

Bit 2: Injected conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register..

ROVRF

Bit 3: Regular conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register..

AWDF

Bit 4: Analog watchdog This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1’ into the clear bits in DFSDM_FLTxAWCFR register)..

JCIP

Bit 13: Injected conversion in progress status A request to start an injected conversion is ignored when JCIP=1..

RCIP

Bit 14: Regular conversion in progress status A request to start a regular conversion is ignored when RCIP=1..

CKABF

Bits 16-23: Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0).

SCDF

Bits 24-31: short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0).

ICR [3]

Offset: 0x28c, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw
CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw
CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: Clear the injected conversion overrun flag.

CLRROVRF

Bit 3: Clear the regular conversion overrun flag.

CLRCKABF

Bits 16-23: Clear the clock absence flag CLRCKABF[y]=0: Writing '0’ has no effect CLRCKABF[y]=1: Writing '1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0).

CLRSCDF

Bits 24-31: Clear the short-circuit detector flag CLRSCDF[y]=0: Writing '0’ has no effect CLRSCDF[y]=1: Writing '1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0).

JCHGR [3]

Offset: 0x290, size: 32, reset: 0x00000001, access: Unspecified

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored..

FCR [3]

Offset: 0x294, size: 32, reset: 0x00000000, access: Unspecified

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw
FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: Integrator oversampling ratio (averaging length) from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). 0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples.

FOSR

Bits 16-25: Sinc filter oversampling ratio (decimation rate) number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If FOSR = 0, then the filter has no effect (filter bypass). 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This.

FORD

Bits 29-31: Sinc filter order 2: Sinc2 filter type 3: Sinc3 filter type 4: Sinc4 filter type 5: Sinc5 filter type 6-7: Reserved Sincx filter type transfer function: FastSinc filter type transfer function: This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)..

JDATAR [3]

Offset: 0x298, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
JDATACH
r
Toggle fields

JDATACH

Bits 0-2: Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0]..

JDATA

Bits 8-31: Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF..

RDATAR [3]

Offset: 0x29c, size: 32, reset: 0x00000000, access: Unspecified

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
RPEND
r
RDATACH
r
Toggle fields

RDATACH

Bits 0-2: Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0]..

RPEND

Bit 4: Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion.

RDATA

Bits 8-31: Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF..

AWHTR [3]

Offset: 0x2a0, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw
BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: Break signal assignment to analog watchdog high threshold event BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event.

AWHT

Bits 8-31: Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case..

AWLTR [3]

Offset: 0x2a4, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw
BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: Break signal assignment to analog watchdog low threshold event BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event.

AWLT

Bits 8-31: Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case..

AWSR [3]

Offset: 0x2a8, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r
AWLTF
r
Toggle fields

AWLTF

Bits 0-7: Analog watchdog low threshold flag AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register..

AWHTF

Bits 8-15: Analog watchdog high threshold flag AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register..

AWCFR [3]

Offset: 0x2ac, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw
CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing '0’ has no effect CLRAWLTF[y]=1: Writing '1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register.

CLRAWHTF

Bits 8-15: Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing '0’ has no effect CLRAWHTF[y]=1: Writing '1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register.

EXMAX [3]

Offset: 0x2b0, size: 32, reset: 0x80000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
rs
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
rs
EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: Extremes detector maximum data channel. These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register..

EXMAX

Bits 8-31: Extremes detector maximum value These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register..

EXMIN [3]

Offset: 0x2b4, size: 32, reset: 0x7FFFFF00, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
rc/w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
rc/w
EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: Extremes detector minimum data channel These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register..

EXMIN

Bits 8-31: Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register..

CNVTIMR [3]

Offset: 0x2b8, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time..

CR1 [4]

Offset: 0x300, size: 32, reset: 0x00000000, access: Unspecified

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw
FAST
rw
RCH
rw
RDMAEN
rw
RSYNC
rw
RCONT
rw
RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw
JEXTSEL
rw
JDMAEN
rw
JSCAN
rw
JSYNC
rw
JSWSTART
rw
DFEN
rw
Toggle fields

DFEN

Bit 0: DFSDM_FLTx enable Data which are cleared by setting DFEN=0: register DFSDM_FLTxISR is set to the reset state register DFSDM_FLTxAWSR is set to the reset state.

JSWSTART

Bit 1: Start a conversion of the injected group of channels This bit is always read as '0’..

JSYNC

Bit 3: Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

JSCAN

Bit 4: Scanning conversion mode for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel..

JDMAEN

Bit 5: DMA channel enabled to read data for the injected channel group This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

JEXTSEL

Bits 8-12: Trigger signal selection for launching injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). DFSDM_FLTx 0x00 dfsdm_jtrg0 0x01 dfsdm_jtrg1 ... 0x1E dfsdm_jtrg30 0x1F dfsdm_jtrg31 Refer to . 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger)..

JEXTEN

Bits 13-14: Trigger enable and trigger edge selection for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RSWSTART

Bit 17: Software start of a conversion on the regular channel This bit is always read as '0’..

RCONT

Bit 18: Continuous mode selection for regular conversions Writing '0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately..

RSYNC

Bit 19: Launch regular conversion synchronously with DFSDM_FLT0 This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RDMAEN

Bit 21: DMA channel enabled to read data for the regular conversion This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RCH

Bits 24-26: Regular channel selection ... 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion)..

FAST

Bit 29: Fast conversion mode selection for regular conversions When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (... but CNVCNT=0) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input..

AWFSEL

Bit 30: Analog watchdog fast mode select.

CR2 [4]

Offset: 0x304, size: 32, reset: 0x00000000, access: Unspecified

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw
CKABIE
rw
SCDIE
rw
AWDIE
rw
ROVRIE
rw
JOVRIE
rw
REOCIE
rw
JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: Injected end of conversion interrupt enable Please see the explanation of JEOCF in DFSDM_FLTxISR..

REOCIE

Bit 1: Regular end of conversion interrupt enable Please see the explanation of REOCF in DFSDM_FLTxISR..

JOVRIE

Bit 2: Injected data overrun interrupt enable Please see the explanation of JOVRF in DFSDM_FLTxISR..

ROVRIE

Bit 3: Regular data overrun interrupt enable Please see the explanation of ROVRF in DFSDM_FLTxISR..

AWDIE

Bit 4: Analog watchdog interrupt enable Please see the explanation of AWDF in DFSDM_FLTxISR..

SCDIE

Bit 5: Short-circuit detector interrupt enable Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR. Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0).

CKABIE

Bit 6: Clock absence interrupt enable Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR. Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0).

EXCH

Bits 8-15: Extremes detector channel selection These bits select the input channels to be taken by the Extremes detector. EXCH[y] = 0: Extremes detector does not accept data from channel y EXCH[y] = 1: Extremes detector accepts data from channel y.

AWDCH

Bits 16-23: Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog. AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y.

ISR [4]

Offset: 0x308, size: 32, reset: 0x00FF0000, access: Unspecified

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r
CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r
JCIP
r
AWDF
r
ROVRF
r
JOVRF
r
REOCF
r
JEOCF
r
Toggle fields

JEOCF

Bit 0: End of injected conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR..

REOCF

Bit 1: End of regular conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR..

JOVRF

Bit 2: Injected conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register..

ROVRF

Bit 3: Regular conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register..

AWDF

Bit 4: Analog watchdog This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1’ into the clear bits in DFSDM_FLTxAWCFR register)..

JCIP

Bit 13: Injected conversion in progress status A request to start an injected conversion is ignored when JCIP=1..

RCIP

Bit 14: Regular conversion in progress status A request to start a regular conversion is ignored when RCIP=1..

CKABF

Bits 16-23: Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0).

SCDF

Bits 24-31: short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0).

ICR [4]

Offset: 0x30c, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw
CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw
CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: Clear the injected conversion overrun flag.

CLRROVRF

Bit 3: Clear the regular conversion overrun flag.

CLRCKABF

Bits 16-23: Clear the clock absence flag CLRCKABF[y]=0: Writing '0’ has no effect CLRCKABF[y]=1: Writing '1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0).

CLRSCDF

Bits 24-31: Clear the short-circuit detector flag CLRSCDF[y]=0: Writing '0’ has no effect CLRSCDF[y]=1: Writing '1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0).

JCHGR [4]

Offset: 0x310, size: 32, reset: 0x00000001, access: Unspecified

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored..

FCR [4]

Offset: 0x314, size: 32, reset: 0x00000000, access: Unspecified

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw
FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: Integrator oversampling ratio (averaging length) from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). 0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples.

FOSR

Bits 16-25: Sinc filter oversampling ratio (decimation rate) number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If FOSR = 0, then the filter has no effect (filter bypass). 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This.

FORD

Bits 29-31: Sinc filter order 2: Sinc2 filter type 3: Sinc3 filter type 4: Sinc4 filter type 5: Sinc5 filter type 6-7: Reserved Sincx filter type transfer function: FastSinc filter type transfer function: This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)..

JDATAR [4]

Offset: 0x318, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
JDATACH
r
Toggle fields

JDATACH

Bits 0-2: Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0]..

JDATA

Bits 8-31: Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF..

RDATAR [4]

Offset: 0x31c, size: 32, reset: 0x00000000, access: Unspecified

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
RPEND
r
RDATACH
r
Toggle fields

RDATACH

Bits 0-2: Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0]..

RPEND

Bit 4: Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion.

RDATA

Bits 8-31: Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF..

AWHTR [4]

Offset: 0x320, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw
BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: Break signal assignment to analog watchdog high threshold event BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event.

AWHT

Bits 8-31: Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case..

AWLTR [4]

Offset: 0x324, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw
BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: Break signal assignment to analog watchdog low threshold event BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event.

AWLT

Bits 8-31: Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case..

AWSR [4]

Offset: 0x328, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r
AWLTF
r
Toggle fields

AWLTF

Bits 0-7: Analog watchdog low threshold flag AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register..

AWHTF

Bits 8-15: Analog watchdog high threshold flag AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register..

AWCFR [4]

Offset: 0x32c, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw
CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing '0’ has no effect CLRAWLTF[y]=1: Writing '1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register.

CLRAWHTF

Bits 8-15: Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing '0’ has no effect CLRAWHTF[y]=1: Writing '1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register.

EXMAX [4]

Offset: 0x330, size: 32, reset: 0x80000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
rs
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
rs
EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: Extremes detector maximum data channel. These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register..

EXMAX

Bits 8-31: Extremes detector maximum value These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register..

EXMIN [4]

Offset: 0x334, size: 32, reset: 0x7FFFFF00, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
rc/w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
rc/w
EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: Extremes detector minimum data channel These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register..

EXMIN

Bits 8-31: Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register..

CNVTIMR [4]

Offset: 0x338, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time..

CR1 [5]

Offset: 0x380, size: 32, reset: 0x00000000, access: Unspecified

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw
FAST
rw
RCH
rw
RDMAEN
rw
RSYNC
rw
RCONT
rw
RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw
JEXTSEL
rw
JDMAEN
rw
JSCAN
rw
JSYNC
rw
JSWSTART
rw
DFEN
rw
Toggle fields

DFEN

Bit 0: DFSDM_FLTx enable Data which are cleared by setting DFEN=0: register DFSDM_FLTxISR is set to the reset state register DFSDM_FLTxAWSR is set to the reset state.

JSWSTART

Bit 1: Start a conversion of the injected group of channels This bit is always read as '0’..

JSYNC

Bit 3: Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

JSCAN

Bit 4: Scanning conversion mode for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel..

JDMAEN

Bit 5: DMA channel enabled to read data for the injected channel group This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

JEXTSEL

Bits 8-12: Trigger signal selection for launching injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). DFSDM_FLTx 0x00 dfsdm_jtrg0 0x01 dfsdm_jtrg1 ... 0x1E dfsdm_jtrg30 0x1F dfsdm_jtrg31 Refer to . 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger)..

JEXTEN

Bits 13-14: Trigger enable and trigger edge selection for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RSWSTART

Bit 17: Software start of a conversion on the regular channel This bit is always read as '0’..

RCONT

Bit 18: Continuous mode selection for regular conversions Writing '0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately..

RSYNC

Bit 19: Launch regular conversion synchronously with DFSDM_FLT0 This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RDMAEN

Bit 21: DMA channel enabled to read data for the regular conversion This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RCH

Bits 24-26: Regular channel selection ... 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion)..

FAST

Bit 29: Fast conversion mode selection for regular conversions When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (... but CNVCNT=0) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input..

AWFSEL

Bit 30: Analog watchdog fast mode select.

CR2 [5]

Offset: 0x384, size: 32, reset: 0x00000000, access: Unspecified

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw
CKABIE
rw
SCDIE
rw
AWDIE
rw
ROVRIE
rw
JOVRIE
rw
REOCIE
rw
JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: Injected end of conversion interrupt enable Please see the explanation of JEOCF in DFSDM_FLTxISR..

REOCIE

Bit 1: Regular end of conversion interrupt enable Please see the explanation of REOCF in DFSDM_FLTxISR..

JOVRIE

Bit 2: Injected data overrun interrupt enable Please see the explanation of JOVRF in DFSDM_FLTxISR..

ROVRIE

Bit 3: Regular data overrun interrupt enable Please see the explanation of ROVRF in DFSDM_FLTxISR..

AWDIE

Bit 4: Analog watchdog interrupt enable Please see the explanation of AWDF in DFSDM_FLTxISR..

SCDIE

Bit 5: Short-circuit detector interrupt enable Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR. Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0).

CKABIE

Bit 6: Clock absence interrupt enable Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR. Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0).

EXCH

Bits 8-15: Extremes detector channel selection These bits select the input channels to be taken by the Extremes detector. EXCH[y] = 0: Extremes detector does not accept data from channel y EXCH[y] = 1: Extremes detector accepts data from channel y.

AWDCH

Bits 16-23: Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog. AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y.

ISR [5]

Offset: 0x388, size: 32, reset: 0x00FF0000, access: Unspecified

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r
CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r
JCIP
r
AWDF
r
ROVRF
r
JOVRF
r
REOCF
r
JEOCF
r
Toggle fields

JEOCF

Bit 0: End of injected conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR..

REOCF

Bit 1: End of regular conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR..

JOVRF

Bit 2: Injected conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register..

ROVRF

Bit 3: Regular conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register..

AWDF

Bit 4: Analog watchdog This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1’ into the clear bits in DFSDM_FLTxAWCFR register)..

JCIP

Bit 13: Injected conversion in progress status A request to start an injected conversion is ignored when JCIP=1..

RCIP

Bit 14: Regular conversion in progress status A request to start a regular conversion is ignored when RCIP=1..

CKABF

Bits 16-23: Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0).

SCDF

Bits 24-31: short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0).

ICR [5]

Offset: 0x38c, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw
CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw
CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: Clear the injected conversion overrun flag.

CLRROVRF

Bit 3: Clear the regular conversion overrun flag.

CLRCKABF

Bits 16-23: Clear the clock absence flag CLRCKABF[y]=0: Writing '0’ has no effect CLRCKABF[y]=1: Writing '1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0).

CLRSCDF

Bits 24-31: Clear the short-circuit detector flag CLRSCDF[y]=0: Writing '0’ has no effect CLRSCDF[y]=1: Writing '1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0).

JCHGR [5]

Offset: 0x390, size: 32, reset: 0x00000001, access: Unspecified

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored..

FCR [5]

Offset: 0x394, size: 32, reset: 0x00000000, access: Unspecified

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw
FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: Integrator oversampling ratio (averaging length) from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). 0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples.

FOSR

Bits 16-25: Sinc filter oversampling ratio (decimation rate) number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If FOSR = 0, then the filter has no effect (filter bypass). 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This.

FORD

Bits 29-31: Sinc filter order 2: Sinc2 filter type 3: Sinc3 filter type 4: Sinc4 filter type 5: Sinc5 filter type 6-7: Reserved Sincx filter type transfer function: FastSinc filter type transfer function: This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)..

JDATAR [5]

Offset: 0x398, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
JDATACH
r
Toggle fields

JDATACH

Bits 0-2: Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0]..

JDATA

Bits 8-31: Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF..

RDATAR [5]

Offset: 0x39c, size: 32, reset: 0x00000000, access: Unspecified

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
RPEND
r
RDATACH
r
Toggle fields

RDATACH

Bits 0-2: Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0]..

RPEND

Bit 4: Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion.

RDATA

Bits 8-31: Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF..

AWHTR [5]

Offset: 0x3a0, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw
BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: Break signal assignment to analog watchdog high threshold event BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event.

AWHT

Bits 8-31: Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case..

AWLTR [5]

Offset: 0x3a4, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw
BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: Break signal assignment to analog watchdog low threshold event BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event.

AWLT

Bits 8-31: Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case..

AWSR [5]

Offset: 0x3a8, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r
AWLTF
r
Toggle fields

AWLTF

Bits 0-7: Analog watchdog low threshold flag AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register..

AWHTF

Bits 8-15: Analog watchdog high threshold flag AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register..

AWCFR [5]

Offset: 0x3ac, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw
CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing '0’ has no effect CLRAWLTF[y]=1: Writing '1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register.

CLRAWHTF

Bits 8-15: Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing '0’ has no effect CLRAWHTF[y]=1: Writing '1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register.

EXMAX [5]

Offset: 0x3b0, size: 32, reset: 0x80000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
rs
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
rs
EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: Extremes detector maximum data channel. These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register..

EXMAX

Bits 8-31: Extremes detector maximum value These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register..

EXMIN [5]

Offset: 0x3b4, size: 32, reset: 0x7FFFFF00, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
rc/w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
rc/w
EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: Extremes detector minimum data channel These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register..

EXMIN

Bits 8-31: Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register..

CNVTIMR [5]

Offset: 0x3b8, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time..

CR1 [6]

Offset: 0x400, size: 32, reset: 0x00000000, access: Unspecified

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw
FAST
rw
RCH
rw
RDMAEN
rw
RSYNC
rw
RCONT
rw
RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw
JEXTSEL
rw
JDMAEN
rw
JSCAN
rw
JSYNC
rw
JSWSTART
rw
DFEN
rw
Toggle fields

DFEN

Bit 0: DFSDM_FLTx enable Data which are cleared by setting DFEN=0: register DFSDM_FLTxISR is set to the reset state register DFSDM_FLTxAWSR is set to the reset state.

JSWSTART

Bit 1: Start a conversion of the injected group of channels This bit is always read as '0’..

JSYNC

Bit 3: Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

JSCAN

Bit 4: Scanning conversion mode for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel..

JDMAEN

Bit 5: DMA channel enabled to read data for the injected channel group This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

JEXTSEL

Bits 8-12: Trigger signal selection for launching injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). DFSDM_FLTx 0x00 dfsdm_jtrg0 0x01 dfsdm_jtrg1 ... 0x1E dfsdm_jtrg30 0x1F dfsdm_jtrg31 Refer to . 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger)..

JEXTEN

Bits 13-14: Trigger enable and trigger edge selection for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RSWSTART

Bit 17: Software start of a conversion on the regular channel This bit is always read as '0’..

RCONT

Bit 18: Continuous mode selection for regular conversions Writing '0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately..

RSYNC

Bit 19: Launch regular conversion synchronously with DFSDM_FLT0 This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RDMAEN

Bit 21: DMA channel enabled to read data for the regular conversion This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RCH

Bits 24-26: Regular channel selection ... 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion)..

FAST

Bit 29: Fast conversion mode selection for regular conversions When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (... but CNVCNT=0) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input..

AWFSEL

Bit 30: Analog watchdog fast mode select.

CR2 [6]

Offset: 0x404, size: 32, reset: 0x00000000, access: Unspecified

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw
CKABIE
rw
SCDIE
rw
AWDIE
rw
ROVRIE
rw
JOVRIE
rw
REOCIE
rw
JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: Injected end of conversion interrupt enable Please see the explanation of JEOCF in DFSDM_FLTxISR..

REOCIE

Bit 1: Regular end of conversion interrupt enable Please see the explanation of REOCF in DFSDM_FLTxISR..

JOVRIE

Bit 2: Injected data overrun interrupt enable Please see the explanation of JOVRF in DFSDM_FLTxISR..

ROVRIE

Bit 3: Regular data overrun interrupt enable Please see the explanation of ROVRF in DFSDM_FLTxISR..

AWDIE

Bit 4: Analog watchdog interrupt enable Please see the explanation of AWDF in DFSDM_FLTxISR..

SCDIE

Bit 5: Short-circuit detector interrupt enable Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR. Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0).

CKABIE

Bit 6: Clock absence interrupt enable Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR. Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0).

EXCH

Bits 8-15: Extremes detector channel selection These bits select the input channels to be taken by the Extremes detector. EXCH[y] = 0: Extremes detector does not accept data from channel y EXCH[y] = 1: Extremes detector accepts data from channel y.

AWDCH

Bits 16-23: Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog. AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y.

ISR [6]

Offset: 0x408, size: 32, reset: 0x00FF0000, access: Unspecified

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r
CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r
JCIP
r
AWDF
r
ROVRF
r
JOVRF
r
REOCF
r
JEOCF
r
Toggle fields

JEOCF

Bit 0: End of injected conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR..

REOCF

Bit 1: End of regular conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR..

JOVRF

Bit 2: Injected conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register..

ROVRF

Bit 3: Regular conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register..

AWDF

Bit 4: Analog watchdog This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1’ into the clear bits in DFSDM_FLTxAWCFR register)..

JCIP

Bit 13: Injected conversion in progress status A request to start an injected conversion is ignored when JCIP=1..

RCIP

Bit 14: Regular conversion in progress status A request to start a regular conversion is ignored when RCIP=1..

CKABF

Bits 16-23: Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0).

SCDF

Bits 24-31: short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0).

ICR [6]

Offset: 0x40c, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw
CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw
CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: Clear the injected conversion overrun flag.

CLRROVRF

Bit 3: Clear the regular conversion overrun flag.

CLRCKABF

Bits 16-23: Clear the clock absence flag CLRCKABF[y]=0: Writing '0’ has no effect CLRCKABF[y]=1: Writing '1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0).

CLRSCDF

Bits 24-31: Clear the short-circuit detector flag CLRSCDF[y]=0: Writing '0’ has no effect CLRSCDF[y]=1: Writing '1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0).

JCHGR [6]

Offset: 0x410, size: 32, reset: 0x00000001, access: Unspecified

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored..

FCR [6]

Offset: 0x414, size: 32, reset: 0x00000000, access: Unspecified

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw
FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: Integrator oversampling ratio (averaging length) from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). 0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples.

FOSR

Bits 16-25: Sinc filter oversampling ratio (decimation rate) number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If FOSR = 0, then the filter has no effect (filter bypass). 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This.

FORD

Bits 29-31: Sinc filter order 2: Sinc2 filter type 3: Sinc3 filter type 4: Sinc4 filter type 5: Sinc5 filter type 6-7: Reserved Sincx filter type transfer function: FastSinc filter type transfer function: This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)..

JDATAR [6]

Offset: 0x418, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
JDATACH
r
Toggle fields

JDATACH

Bits 0-2: Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0]..

JDATA

Bits 8-31: Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF..

RDATAR [6]

Offset: 0x41c, size: 32, reset: 0x00000000, access: Unspecified

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
RPEND
r
RDATACH
r
Toggle fields

RDATACH

Bits 0-2: Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0]..

RPEND

Bit 4: Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion.

RDATA

Bits 8-31: Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF..

AWHTR [6]

Offset: 0x420, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw
BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: Break signal assignment to analog watchdog high threshold event BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event.

AWHT

Bits 8-31: Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case..

AWLTR [6]

Offset: 0x424, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw
BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: Break signal assignment to analog watchdog low threshold event BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event.

AWLT

Bits 8-31: Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case..

AWSR [6]

Offset: 0x428, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r
AWLTF
r
Toggle fields

AWLTF

Bits 0-7: Analog watchdog low threshold flag AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register..

AWHTF

Bits 8-15: Analog watchdog high threshold flag AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register..

AWCFR [6]

Offset: 0x42c, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw
CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing '0’ has no effect CLRAWLTF[y]=1: Writing '1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register.

CLRAWHTF

Bits 8-15: Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing '0’ has no effect CLRAWHTF[y]=1: Writing '1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register.

EXMAX [6]

Offset: 0x430, size: 32, reset: 0x80000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
rs
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
rs
EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: Extremes detector maximum data channel. These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register..

EXMAX

Bits 8-31: Extremes detector maximum value These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register..

EXMIN [6]

Offset: 0x434, size: 32, reset: 0x7FFFFF00, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
rc/w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
rc/w
EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: Extremes detector minimum data channel These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register..

EXMIN

Bits 8-31: Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register..

CNVTIMR [6]

Offset: 0x438, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time..

CR1 [7]

Offset: 0x480, size: 32, reset: 0x00000000, access: Unspecified

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw
FAST
rw
RCH
rw
RDMAEN
rw
RSYNC
rw
RCONT
rw
RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw
JEXTSEL
rw
JDMAEN
rw
JSCAN
rw
JSYNC
rw
JSWSTART
rw
DFEN
rw
Toggle fields

DFEN

Bit 0: DFSDM_FLTx enable Data which are cleared by setting DFEN=0: register DFSDM_FLTxISR is set to the reset state register DFSDM_FLTxAWSR is set to the reset state.

JSWSTART

Bit 1: Start a conversion of the injected group of channels This bit is always read as '0’..

JSYNC

Bit 3: Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

JSCAN

Bit 4: Scanning conversion mode for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel..

JDMAEN

Bit 5: DMA channel enabled to read data for the injected channel group This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

JEXTSEL

Bits 8-12: Trigger signal selection for launching injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). DFSDM_FLTx 0x00 dfsdm_jtrg0 0x01 dfsdm_jtrg1 ... 0x1E dfsdm_jtrg30 0x1F dfsdm_jtrg31 Refer to . 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger)..

JEXTEN

Bits 13-14: Trigger enable and trigger edge selection for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RSWSTART

Bit 17: Software start of a conversion on the regular channel This bit is always read as '0’..

RCONT

Bit 18: Continuous mode selection for regular conversions Writing '0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately..

RSYNC

Bit 19: Launch regular conversion synchronously with DFSDM_FLT0 This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RDMAEN

Bit 21: DMA channel enabled to read data for the regular conversion This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1)..

RCH

Bits 24-26: Regular channel selection ... 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion)..

FAST

Bit 29: Fast conversion mode selection for regular conversions When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (... but CNVCNT=0) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input..

AWFSEL

Bit 30: Analog watchdog fast mode select.

CR2 [7]

Offset: 0x484, size: 32, reset: 0x00000000, access: Unspecified

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw
CKABIE
rw
SCDIE
rw
AWDIE
rw
ROVRIE
rw
JOVRIE
rw
REOCIE
rw
JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: Injected end of conversion interrupt enable Please see the explanation of JEOCF in DFSDM_FLTxISR..

REOCIE

Bit 1: Regular end of conversion interrupt enable Please see the explanation of REOCF in DFSDM_FLTxISR..

JOVRIE

Bit 2: Injected data overrun interrupt enable Please see the explanation of JOVRF in DFSDM_FLTxISR..

ROVRIE

Bit 3: Regular data overrun interrupt enable Please see the explanation of ROVRF in DFSDM_FLTxISR..

AWDIE

Bit 4: Analog watchdog interrupt enable Please see the explanation of AWDF in DFSDM_FLTxISR..

SCDIE

Bit 5: Short-circuit detector interrupt enable Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR. Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0).

CKABIE

Bit 6: Clock absence interrupt enable Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR. Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0).

EXCH

Bits 8-15: Extremes detector channel selection These bits select the input channels to be taken by the Extremes detector. EXCH[y] = 0: Extremes detector does not accept data from channel y EXCH[y] = 1: Extremes detector accepts data from channel y.

AWDCH

Bits 16-23: Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog. AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y.

ISR [7]

Offset: 0x488, size: 32, reset: 0x00FF0000, access: Unspecified

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r
CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r
JCIP
r
AWDF
r
ROVRF
r
JOVRF
r
REOCF
r
JEOCF
r
Toggle fields

JEOCF

Bit 0: End of injected conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR..

REOCF

Bit 1: End of regular conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR..

JOVRF

Bit 2: Injected conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register..

ROVRF

Bit 3: Regular conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register..

AWDF

Bit 4: Analog watchdog This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1’ into the clear bits in DFSDM_FLTxAWCFR register)..

JCIP

Bit 13: Injected conversion in progress status A request to start an injected conversion is ignored when JCIP=1..

RCIP

Bit 14: Regular conversion in progress status A request to start a regular conversion is ignored when RCIP=1..

CKABF

Bits 16-23: Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0).

SCDF

Bits 24-31: short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0).

ICR [7]

Offset: 0x48c, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw
CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw
CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: Clear the injected conversion overrun flag.

CLRROVRF

Bit 3: Clear the regular conversion overrun flag.

CLRCKABF

Bits 16-23: Clear the clock absence flag CLRCKABF[y]=0: Writing '0’ has no effect CLRCKABF[y]=1: Writing '1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0).

CLRSCDF

Bits 24-31: Clear the short-circuit detector flag CLRSCDF[y]=0: Writing '0’ has no effect CLRSCDF[y]=1: Writing '1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0).

JCHGR [7]

Offset: 0x490, size: 32, reset: 0x00000001, access: Unspecified

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored..

FCR [7]

Offset: 0x494, size: 32, reset: 0x00000000, access: Unspecified

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw
FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: Integrator oversampling ratio (averaging length) from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). 0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples.

FOSR

Bits 16-25: Sinc filter oversampling ratio (decimation rate) number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If FOSR = 0, then the filter has no effect (filter bypass). 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This.

FORD

Bits 29-31: Sinc filter order 2: Sinc2 filter type 3: Sinc3 filter type 4: Sinc4 filter type 5: Sinc5 filter type 6-7: Reserved Sincx filter type transfer function: FastSinc filter type transfer function: This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)..

JDATAR [7]

Offset: 0x498, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
JDATACH
r
Toggle fields

JDATACH

Bits 0-2: Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0]..

JDATA

Bits 8-31: Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF..

RDATAR [7]

Offset: 0x49c, size: 32, reset: 0x00000000, access: Unspecified

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
RPEND
r
RDATACH
r
Toggle fields

RDATACH

Bits 0-2: Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0]..

RPEND

Bit 4: Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion.

RDATA

Bits 8-31: Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF..

AWHTR [7]

Offset: 0x4a0, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw
BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: Break signal assignment to analog watchdog high threshold event BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event.

AWHT

Bits 8-31: Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case..

AWLTR [7]

Offset: 0x4a4, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw
BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: Break signal assignment to analog watchdog low threshold event BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event.

AWLT

Bits 8-31: Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case..

AWSR [7]

Offset: 0x4a8, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r
AWLTF
r
Toggle fields

AWLTF

Bits 0-7: Analog watchdog low threshold flag AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register..

AWHTF

Bits 8-15: Analog watchdog high threshold flag AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register..

AWCFR [7]

Offset: 0x4ac, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw
CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing '0’ has no effect CLRAWLTF[y]=1: Writing '1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register.

CLRAWHTF

Bits 8-15: Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing '0’ has no effect CLRAWHTF[y]=1: Writing '1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register.

EXMAX [7]

Offset: 0x4b0, size: 32, reset: 0x80000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
rs
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
rs
EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: Extremes detector maximum data channel. These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register..

EXMAX

Bits 8-31: Extremes detector maximum value These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register..

EXMIN [7]

Offset: 0x4b4, size: 32, reset: 0x7FFFFF00, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
rc/w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
rc/w
EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: Extremes detector minimum data channel These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register..

EXMIN

Bits 8-31: Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register..

CNVTIMR [7]

Offset: 0x4b8, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time..

DMA1

0x40020000: DMA controller

272/296 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 LISR
0x4 HISR
0x8 LIFCR
0xc HIFCR
0x10 CR [0]
0x14 NDTR [0]
0x18 PAR [0]
0x1c M0AR [0]
0x20 M1AR [0]
0x24 FCR [0]
0x28 CR [1]
0x2c NDTR [1]
0x30 PAR [1]
0x34 M0AR [1]
0x38 M1AR [1]
0x3c FCR [1]
0x40 CR [2]
0x44 NDTR [2]
0x48 PAR [2]
0x4c M0AR [2]
0x50 M1AR [2]
0x54 FCR [2]
0x58 CR [3]
0x5c NDTR [3]
0x60 PAR [3]
0x64 M0AR [3]
0x68 M1AR [3]
0x6c FCR [3]
0x70 CR [4]
0x74 NDTR [4]
0x78 PAR [4]
0x7c M0AR [4]
0x80 M1AR [4]
0x84 FCR [4]
0x88 CR [5]
0x8c NDTR [5]
0x90 PAR [5]
0x94 M0AR [5]
0x98 M1AR [5]
0x9c FCR [5]
0xa0 CR [6]
0xa4 NDTR [6]
0xa8 PAR [6]
0xac M0AR [6]
0xb0 M1AR [6]
0xb4 FCR [6]
0xb8 CR [7]
0xbc NDTR [7]
0xc0 PAR [7]
0xc4 M0AR [7]
0xc8 M1AR [7]
0xcc FCR [7]
Toggle registers

LISR

low interrupt status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCIF3
r
HTIF3
r
TEIF3
r
DMEIF3
r
FEIF3
r
TCIF2
r
HTIF2
r
TEIF2
r
DMEIF2
r
FEIF2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF1
r
HTIF1
r
TEIF1
r
DMEIF1
r
FEIF1
r
TCIF0
r
HTIF0
r
TEIF0
r
DMEIF0
r
FEIF0
r
Toggle fields

FEIF0

Bit 0: Stream x FIFO error interrupt flag (x=3..0).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF0

Bit 2: Stream x direct mode error interrupt flag (x=3..0).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF0

Bit 3: Stream x transfer error interrupt flag (x=3..0).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF0

Bit 4: Stream x half transfer interrupt flag (x=3..0).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF0

Bit 5: Stream x transfer complete interrupt flag (x = 3..0).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

FEIF1

Bit 6: Stream x FIFO error interrupt flag (x=3..0).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF1

Bit 8: Stream x direct mode error interrupt flag (x=3..0).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF1

Bit 9: Stream x transfer error interrupt flag (x=3..0).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF1

Bit 10: Stream x half transfer interrupt flag (x=3..0).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF1

Bit 11: Stream x transfer complete interrupt flag (x = 3..0).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

FEIF2

Bit 16: Stream x FIFO error interrupt flag (x=3..0).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF2

Bit 18: Stream x direct mode error interrupt flag (x=3..0).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF2

Bit 19: Stream x transfer error interrupt flag (x=3..0).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF2

Bit 20: Stream x half transfer interrupt flag (x=3..0).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF2

Bit 21: Stream x transfer complete interrupt flag (x = 3..0).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

FEIF3

Bit 22: Stream x FIFO error interrupt flag (x=3..0).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF3

Bit 24: Stream x direct mode error interrupt flag (x=3..0).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF3

Bit 25: Stream x transfer error interrupt flag (x=3..0).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF3

Bit 26: Stream x half transfer interrupt flag (x=3..0).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF3

Bit 27: Stream x transfer complete interrupt flag (x = 3..0).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

HISR

high interrupt status register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCIF7
r
HTIF7
r
TEIF7
r
DMEIF7
r
FEIF7
r
TCIF6
r
HTIF6
r
TEIF6
r
DMEIF6
r
FEIF6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF5
r
HTIF5
r
TEIF5
r
DMEIF5
r
FEIF5
r
TCIF4
r
HTIF4
r
TEIF4
r
DMEIF4
r
FEIF4
r
Toggle fields

FEIF4

Bit 0: Stream x FIFO error interrupt flag (x=7..4).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF4

Bit 2: Stream x direct mode error interrupt flag (x=7..4).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF4

Bit 3: Stream x transfer error interrupt flag (x=7..4).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF4

Bit 4: Stream x half transfer interrupt flag (x=7..4).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF4

Bit 5: Stream x transfer complete interrupt flag (x=7..4).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

FEIF5

Bit 6: Stream x FIFO error interrupt flag (x=7..4).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF5

Bit 8: Stream x direct mode error interrupt flag (x=7..4).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF5

Bit 9: Stream x transfer error interrupt flag (x=7..4).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF5

Bit 10: Stream x half transfer interrupt flag (x=7..4).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF5

Bit 11: Stream x transfer complete interrupt flag (x=7..4).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

FEIF6

Bit 16: Stream x FIFO error interrupt flag (x=7..4).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF6

Bit 18: Stream x direct mode error interrupt flag (x=7..4).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF6

Bit 19: Stream x transfer error interrupt flag (x=7..4).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF6

Bit 20: Stream x half transfer interrupt flag (x=7..4).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF6

Bit 21: Stream x transfer complete interrupt flag (x=7..4).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

FEIF7

Bit 22: Stream x FIFO error interrupt flag (x=7..4).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF7

Bit 24: Stream x direct mode error interrupt flag (x=7..4).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF7

Bit 25: Stream x transfer error interrupt flag (x=7..4).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF7

Bit 26: Stream x half transfer interrupt flag (x=7..4).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF7

Bit 27: Stream x transfer complete interrupt flag (x=7..4).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

LIFCR

low interrupt flag clear register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

20/20 fields covered.

Toggle fields

CFEIF0

Bit 0: Stream x clear FIFO error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF0

Bit 2: Stream x clear direct mode error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF0

Bit 3: Stream x clear transfer error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF0

Bit 4: Stream x clear half transfer interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF0

Bit 5: Stream x clear transfer complete interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CFEIF1

Bit 6: Stream x clear FIFO error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF1

Bit 8: Stream x clear direct mode error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF1

Bit 9: Stream x clear transfer error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF1

Bit 10: Stream x clear half transfer interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF1

Bit 11: Stream x clear transfer complete interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CFEIF2

Bit 16: Stream x clear FIFO error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF2

Bit 18: Stream x clear direct mode error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF2

Bit 19: Stream x clear transfer error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF2

Bit 20: Stream x clear half transfer interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF2

Bit 21: Stream x clear transfer complete interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CFEIF3

Bit 22: Stream x clear FIFO error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF3

Bit 24: Stream x clear direct mode error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF3

Bit 25: Stream x clear transfer error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF3

Bit 26: Stream x clear half transfer interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF3

Bit 27: Stream x clear transfer complete interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

HIFCR

high interrupt flag clear register

Offset: 0xc, size: 32, reset: 0x00000000, access: write-only

20/20 fields covered.

Toggle fields

CFEIF4

Bit 0: Stream x clear FIFO error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF4

Bit 2: Stream x clear direct mode error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF4

Bit 3: Stream x clear transfer error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF4

Bit 4: Stream x clear half transfer interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF4

Bit 5: Stream x clear transfer complete interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CFEIF5

Bit 6: Stream x clear FIFO error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF5

Bit 8: Stream x clear direct mode error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF5

Bit 9: Stream x clear transfer error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF5

Bit 10: Stream x clear half transfer interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF5

Bit 11: Stream x clear transfer complete interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CFEIF6

Bit 16: Stream x clear FIFO error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF6

Bit 18: Stream x clear direct mode error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF6

Bit 19: Stream x clear transfer error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF6

Bit 20: Stream x clear half transfer interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF6

Bit 21: Stream x clear transfer complete interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CFEIF7

Bit 22: Stream x clear FIFO error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF7

Bit 24: Stream x clear direct mode error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF7

Bit 25: Stream x clear transfer error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF7

Bit 26: Stream x clear half transfer interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF7

Bit 27: Stream x clear transfer complete interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CR [0]

stream x configuration register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBURST
rw
PBURST
rw
TRBUFF
rw
CT
rw
DBM
rw
PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
PFCTRL
rw
TCIE
rw
HTIE
rw
TEIE
rw
DMEIE
rw
EN
rw
Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

DMEIE

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

TEIE

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

HTIE

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TCIE

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

PFCTRL

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

DIR

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

CIRC

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PINCOS

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

PL

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

DBM

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

TRBUFF

Bit 20: Enable the DMA to handle bufferable transfers.

Allowed values:
0: Disabled: Bufferable transfers not enabled
1: Enabled: Bufferable transfers enabled

PBURST

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

MBURST

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

NDTR [0]

stream x number of data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

PAR [0]

stream x peripheral address register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [0]

stream x memory 0 address register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: Memory 0 address.

M1AR [0]

stream x memory 1 address register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

FCR [0]

stream x FIFO control register

Offset: 0x24, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw
FS
r
DMDIS
rw
FTH
rw
Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

DMDIS

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

FS

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

FEIE

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

CR [1]

stream x configuration register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBURST
rw
PBURST
rw
TRBUFF
rw
CT
rw
DBM
rw
PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
PFCTRL
rw
TCIE
rw
HTIE
rw
TEIE
rw
DMEIE
rw
EN
rw
Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

DMEIE

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

TEIE

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

HTIE

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TCIE

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

PFCTRL

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

DIR

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

CIRC

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PINCOS

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

PL

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

DBM

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

TRBUFF

Bit 20: Enable the DMA to handle bufferable transfers.

Allowed values:
0: Disabled: Bufferable transfers not enabled
1: Enabled: Bufferable transfers enabled

PBURST

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

MBURST

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

NDTR [1]

stream x number of data register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

PAR [1]

stream x peripheral address register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [1]

stream x memory 0 address register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: Memory 0 address.

M1AR [1]

stream x memory 1 address register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

FCR [1]

stream x FIFO control register

Offset: 0x3c, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw
FS
r
DMDIS
rw
FTH
rw
Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

DMDIS

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

FS

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

FEIE

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

CR [2]

stream x configuration register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBURST
rw
PBURST
rw
TRBUFF
rw
CT
rw
DBM
rw
PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
PFCTRL
rw
TCIE
rw
HTIE
rw
TEIE
rw
DMEIE
rw
EN
rw
Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

DMEIE

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

TEIE

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

HTIE

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TCIE

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

PFCTRL

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

DIR

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

CIRC

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PINCOS

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

PL

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

DBM

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

TRBUFF

Bit 20: Enable the DMA to handle bufferable transfers.

Allowed values:
0: Disabled: Bufferable transfers not enabled
1: Enabled: Bufferable transfers enabled

PBURST

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

MBURST

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

NDTR [2]

stream x number of data register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

PAR [2]

stream x peripheral address register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [2]

stream x memory 0 address register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: Memory 0 address.

M1AR [2]

stream x memory 1 address register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

FCR [2]

stream x FIFO control register

Offset: 0x54, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw
FS
r
DMDIS
rw
FTH
rw
Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

DMDIS

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

FS

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

FEIE

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

CR [3]

stream x configuration register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBURST
rw
PBURST
rw
TRBUFF
rw
CT
rw
DBM
rw
PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
PFCTRL
rw
TCIE
rw
HTIE
rw
TEIE
rw
DMEIE
rw
EN
rw
Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

DMEIE

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

TEIE

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

HTIE

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TCIE

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

PFCTRL

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

DIR

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

CIRC

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PINCOS

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

PL

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

DBM

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

TRBUFF

Bit 20: Enable the DMA to handle bufferable transfers.

Allowed values:
0: Disabled: Bufferable transfers not enabled
1: Enabled: Bufferable transfers enabled

PBURST

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

MBURST

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

NDTR [3]

stream x number of data register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

PAR [3]

stream x peripheral address register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [3]

stream x memory 0 address register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: Memory 0 address.

M1AR [3]

stream x memory 1 address register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

FCR [3]

stream x FIFO control register

Offset: 0x6c, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw
FS
r
DMDIS
rw
FTH
rw
Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

DMDIS

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

FS

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

FEIE

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

CR [4]

stream x configuration register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBURST
rw
PBURST
rw
TRBUFF
rw
CT
rw
DBM
rw
PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
PFCTRL
rw
TCIE
rw
HTIE
rw
TEIE
rw
DMEIE
rw
EN
rw
Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

DMEIE

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

TEIE

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

HTIE

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TCIE

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

PFCTRL

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

DIR

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

CIRC

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PINCOS

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

PL

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

DBM

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

TRBUFF

Bit 20: Enable the DMA to handle bufferable transfers.

Allowed values:
0: Disabled: Bufferable transfers not enabled
1: Enabled: Bufferable transfers enabled

PBURST

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

MBURST

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

NDTR [4]

stream x number of data register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

PAR [4]

stream x peripheral address register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [4]

stream x memory 0 address register

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: Memory 0 address.

M1AR [4]

stream x memory 1 address register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

FCR [4]

stream x FIFO control register

Offset: 0x84, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw
FS
r
DMDIS
rw
FTH
rw
Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

DMDIS

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

FS

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

FEIE

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

CR [5]

stream x configuration register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBURST
rw
PBURST
rw
TRBUFF
rw
CT
rw
DBM
rw
PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
PFCTRL
rw
TCIE
rw
HTIE
rw
TEIE
rw
DMEIE
rw
EN
rw
Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

DMEIE

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

TEIE

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

HTIE

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TCIE

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

PFCTRL

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

DIR

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

CIRC

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PINCOS

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

PL

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

DBM

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

TRBUFF

Bit 20: Enable the DMA to handle bufferable transfers.

Allowed values:
0: Disabled: Bufferable transfers not enabled
1: Enabled: Bufferable transfers enabled

PBURST

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

MBURST

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

NDTR [5]

stream x number of data register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

PAR [5]

stream x peripheral address register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [5]

stream x memory 0 address register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: Memory 0 address.

M1AR [5]

stream x memory 1 address register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

FCR [5]

stream x FIFO control register

Offset: 0x9c, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw
FS
r
DMDIS
rw
FTH
rw
Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

DMDIS

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

FS

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

FEIE

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

CR [6]

stream x configuration register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBURST
rw
PBURST
rw
TRBUFF
rw
CT
rw
DBM
rw
PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
PFCTRL
rw
TCIE
rw
HTIE
rw
TEIE
rw
DMEIE
rw
EN
rw
Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

DMEIE

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

TEIE

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

HTIE

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TCIE

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

PFCTRL

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

DIR

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

CIRC

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PINCOS

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

PL

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

DBM

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

TRBUFF

Bit 20: Enable the DMA to handle bufferable transfers.

Allowed values:
0: Disabled: Bufferable transfers not enabled
1: Enabled: Bufferable transfers enabled

PBURST

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

MBURST

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

NDTR [6]

stream x number of data register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

PAR [6]

stream x peripheral address register

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [6]

stream x memory 0 address register

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: Memory 0 address.

M1AR [6]

stream x memory 1 address register

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

FCR [6]

stream x FIFO control register

Offset: 0xb4, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw
FS
r
DMDIS
rw
FTH
rw
Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

DMDIS

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

FS

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

FEIE

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

CR [7]

stream x configuration register

Offset: 0xb8, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBURST
rw
PBURST
rw
TRBUFF
rw
CT
rw
DBM
rw
PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
PFCTRL
rw
TCIE
rw
HTIE
rw
TEIE
rw
DMEIE
rw
EN
rw
Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

DMEIE

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

TEIE

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

HTIE

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TCIE

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

PFCTRL

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

DIR

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

CIRC

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PINCOS

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

PL

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

DBM

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

TRBUFF

Bit 20: Enable the DMA to handle bufferable transfers.

Allowed values:
0: Disabled: Bufferable transfers not enabled
1: Enabled: Bufferable transfers enabled

PBURST

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

MBURST

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

NDTR [7]

stream x number of data register

Offset: 0xbc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

PAR [7]

stream x peripheral address register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [7]

stream x memory 0 address register

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: Memory 0 address.

M1AR [7]

stream x memory 1 address register

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

FCR [7]

stream x FIFO control register

Offset: 0xcc, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw
FS
r
DMDIS
rw
FTH
rw
Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

DMDIS

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

FS

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

FEIE

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

DMA2

0x40020400: DMA controller

272/296 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 LISR
0x4 HISR
0x8 LIFCR
0xc HIFCR
0x10 CR [0]
0x14 NDTR [0]
0x18 PAR [0]
0x1c M0AR [0]
0x20 M1AR [0]
0x24 FCR [0]
0x28 CR [1]
0x2c NDTR [1]
0x30 PAR [1]
0x34 M0AR [1]
0x38 M1AR [1]
0x3c FCR [1]
0x40 CR [2]
0x44 NDTR [2]
0x48 PAR [2]
0x4c M0AR [2]
0x50 M1AR [2]
0x54 FCR [2]
0x58 CR [3]
0x5c NDTR [3]
0x60 PAR [3]
0x64 M0AR [3]
0x68 M1AR [3]
0x6c FCR [3]
0x70 CR [4]
0x74 NDTR [4]
0x78 PAR [4]
0x7c M0AR [4]
0x80 M1AR [4]
0x84 FCR [4]
0x88 CR [5]
0x8c NDTR [5]
0x90 PAR [5]
0x94 M0AR [5]
0x98 M1AR [5]
0x9c FCR [5]
0xa0 CR [6]
0xa4 NDTR [6]
0xa8 PAR [6]
0xac M0AR [6]
0xb0 M1AR [6]
0xb4 FCR [6]
0xb8 CR [7]
0xbc NDTR [7]
0xc0 PAR [7]
0xc4 M0AR [7]
0xc8 M1AR [7]
0xcc FCR [7]
Toggle registers

LISR

low interrupt status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCIF3
r
HTIF3
r
TEIF3
r
DMEIF3
r
FEIF3
r
TCIF2
r
HTIF2
r
TEIF2
r
DMEIF2
r
FEIF2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF1
r
HTIF1
r
TEIF1
r
DMEIF1
r
FEIF1
r
TCIF0
r
HTIF0
r
TEIF0
r
DMEIF0
r
FEIF0
r
Toggle fields

FEIF0

Bit 0: Stream x FIFO error interrupt flag (x=3..0).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF0

Bit 2: Stream x direct mode error interrupt flag (x=3..0).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF0

Bit 3: Stream x transfer error interrupt flag (x=3..0).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF0

Bit 4: Stream x half transfer interrupt flag (x=3..0).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF0

Bit 5: Stream x transfer complete interrupt flag (x = 3..0).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

FEIF1

Bit 6: Stream x FIFO error interrupt flag (x=3..0).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF1

Bit 8: Stream x direct mode error interrupt flag (x=3..0).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF1

Bit 9: Stream x transfer error interrupt flag (x=3..0).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF1

Bit 10: Stream x half transfer interrupt flag (x=3..0).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF1

Bit 11: Stream x transfer complete interrupt flag (x = 3..0).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

FEIF2

Bit 16: Stream x FIFO error interrupt flag (x=3..0).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF2

Bit 18: Stream x direct mode error interrupt flag (x=3..0).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF2

Bit 19: Stream x transfer error interrupt flag (x=3..0).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF2

Bit 20: Stream x half transfer interrupt flag (x=3..0).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF2

Bit 21: Stream x transfer complete interrupt flag (x = 3..0).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

FEIF3

Bit 22: Stream x FIFO error interrupt flag (x=3..0).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF3

Bit 24: Stream x direct mode error interrupt flag (x=3..0).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF3

Bit 25: Stream x transfer error interrupt flag (x=3..0).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF3

Bit 26: Stream x half transfer interrupt flag (x=3..0).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF3

Bit 27: Stream x transfer complete interrupt flag (x = 3..0).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

HISR

high interrupt status register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCIF7
r
HTIF7
r
TEIF7
r
DMEIF7
r
FEIF7
r
TCIF6
r
HTIF6
r
TEIF6
r
DMEIF6
r
FEIF6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF5
r
HTIF5
r
TEIF5
r
DMEIF5
r
FEIF5
r
TCIF4
r
HTIF4
r
TEIF4
r
DMEIF4
r
FEIF4
r
Toggle fields

FEIF4

Bit 0: Stream x FIFO error interrupt flag (x=7..4).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF4

Bit 2: Stream x direct mode error interrupt flag (x=7..4).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF4

Bit 3: Stream x transfer error interrupt flag (x=7..4).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF4

Bit 4: Stream x half transfer interrupt flag (x=7..4).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF4

Bit 5: Stream x transfer complete interrupt flag (x=7..4).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

FEIF5

Bit 6: Stream x FIFO error interrupt flag (x=7..4).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF5

Bit 8: Stream x direct mode error interrupt flag (x=7..4).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF5

Bit 9: Stream x transfer error interrupt flag (x=7..4).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF5

Bit 10: Stream x half transfer interrupt flag (x=7..4).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF5

Bit 11: Stream x transfer complete interrupt flag (x=7..4).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

FEIF6

Bit 16: Stream x FIFO error interrupt flag (x=7..4).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF6

Bit 18: Stream x direct mode error interrupt flag (x=7..4).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF6

Bit 19: Stream x transfer error interrupt flag (x=7..4).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF6

Bit 20: Stream x half transfer interrupt flag (x=7..4).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF6

Bit 21: Stream x transfer complete interrupt flag (x=7..4).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

FEIF7

Bit 22: Stream x FIFO error interrupt flag (x=7..4).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF7

Bit 24: Stream x direct mode error interrupt flag (x=7..4).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF7

Bit 25: Stream x transfer error interrupt flag (x=7..4).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF7

Bit 26: Stream x half transfer interrupt flag (x=7..4).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF7

Bit 27: Stream x transfer complete interrupt flag (x=7..4).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

LIFCR

low interrupt flag clear register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

20/20 fields covered.

Toggle fields

CFEIF0

Bit 0: Stream x clear FIFO error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF0

Bit 2: Stream x clear direct mode error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF0

Bit 3: Stream x clear transfer error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF0

Bit 4: Stream x clear half transfer interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF0

Bit 5: Stream x clear transfer complete interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CFEIF1

Bit 6: Stream x clear FIFO error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF1

Bit 8: Stream x clear direct mode error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF1

Bit 9: Stream x clear transfer error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF1

Bit 10: Stream x clear half transfer interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF1

Bit 11: Stream x clear transfer complete interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CFEIF2

Bit 16: Stream x clear FIFO error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF2

Bit 18: Stream x clear direct mode error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF2

Bit 19: Stream x clear transfer error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF2

Bit 20: Stream x clear half transfer interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF2

Bit 21: Stream x clear transfer complete interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CFEIF3

Bit 22: Stream x clear FIFO error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF3

Bit 24: Stream x clear direct mode error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF3

Bit 25: Stream x clear transfer error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF3

Bit 26: Stream x clear half transfer interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF3

Bit 27: Stream x clear transfer complete interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

HIFCR

high interrupt flag clear register

Offset: 0xc, size: 32, reset: 0x00000000, access: write-only

20/20 fields covered.

Toggle fields

CFEIF4

Bit 0: Stream x clear FIFO error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF4

Bit 2: Stream x clear direct mode error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF4

Bit 3: Stream x clear transfer error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF4

Bit 4: Stream x clear half transfer interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF4

Bit 5: Stream x clear transfer complete interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CFEIF5

Bit 6: Stream x clear FIFO error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF5

Bit 8: Stream x clear direct mode error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF5

Bit 9: Stream x clear transfer error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF5

Bit 10: Stream x clear half transfer interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF5

Bit 11: Stream x clear transfer complete interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CFEIF6

Bit 16: Stream x clear FIFO error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF6

Bit 18: Stream x clear direct mode error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF6

Bit 19: Stream x clear transfer error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF6

Bit 20: Stream x clear half transfer interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF6

Bit 21: Stream x clear transfer complete interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CFEIF7

Bit 22: Stream x clear FIFO error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF7

Bit 24: Stream x clear direct mode error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF7

Bit 25: Stream x clear transfer error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF7

Bit 26: Stream x clear half transfer interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF7

Bit 27: Stream x clear transfer complete interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CR [0]

stream x configuration register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBURST
rw
PBURST
rw
TRBUFF
rw
CT
rw
DBM
rw
PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
PFCTRL
rw
TCIE
rw
HTIE
rw
TEIE
rw
DMEIE
rw
EN
rw
Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

DMEIE

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

TEIE

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

HTIE

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TCIE

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

PFCTRL

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

DIR

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

CIRC

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PINCOS

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

PL

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

DBM

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

TRBUFF

Bit 20: Enable the DMA to handle bufferable transfers.

Allowed values:
0: Disabled: Bufferable transfers not enabled
1: Enabled: Bufferable transfers enabled

PBURST

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

MBURST

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

NDTR [0]

stream x number of data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

PAR [0]

stream x peripheral address register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [0]

stream x memory 0 address register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: Memory 0 address.

M1AR [0]

stream x memory 1 address register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

FCR [0]

stream x FIFO control register

Offset: 0x24, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw
FS
r
DMDIS
rw
FTH
rw
Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

DMDIS

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

FS

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

FEIE

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

CR [1]

stream x configuration register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBURST
rw
PBURST
rw
TRBUFF
rw
CT
rw
DBM
rw
PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
PFCTRL
rw
TCIE
rw
HTIE
rw
TEIE
rw
DMEIE
rw
EN
rw
Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

DMEIE

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

TEIE

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

HTIE

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TCIE

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

PFCTRL

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

DIR

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

CIRC

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PINCOS

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

PL

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

DBM

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

TRBUFF

Bit 20: Enable the DMA to handle bufferable transfers.

Allowed values:
0: Disabled: Bufferable transfers not enabled
1: Enabled: Bufferable transfers enabled

PBURST

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

MBURST

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

NDTR [1]

stream x number of data register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

PAR [1]

stream x peripheral address register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [1]

stream x memory 0 address register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: Memory 0 address.

M1AR [1]

stream x memory 1 address register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

FCR [1]

stream x FIFO control register

Offset: 0x3c, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw
FS
r
DMDIS
rw
FTH
rw
Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

DMDIS

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

FS

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

FEIE

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

CR [2]

stream x configuration register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBURST
rw
PBURST
rw
TRBUFF
rw
CT
rw
DBM
rw
PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
PFCTRL
rw
TCIE
rw
HTIE
rw
TEIE
rw
DMEIE
rw
EN
rw
Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

DMEIE

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

TEIE

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

HTIE

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TCIE

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

PFCTRL

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

DIR

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

CIRC

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PINCOS

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

PL

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

DBM

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

TRBUFF

Bit 20: Enable the DMA to handle bufferable transfers.

Allowed values:
0: Disabled: Bufferable transfers not enabled
1: Enabled: Bufferable transfers enabled

PBURST

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

MBURST

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

NDTR [2]

stream x number of data register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

PAR [2]

stream x peripheral address register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [2]

stream x memory 0 address register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: Memory 0 address.

M1AR [2]

stream x memory 1 address register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

FCR [2]

stream x FIFO control register

Offset: 0x54, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw
FS
r
DMDIS
rw
FTH
rw
Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

DMDIS

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

FS

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

FEIE

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

CR [3]

stream x configuration register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBURST
rw
PBURST
rw
TRBUFF
rw
CT
rw
DBM
rw
PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
PFCTRL
rw
TCIE
rw
HTIE
rw
TEIE
rw
DMEIE
rw
EN
rw
Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

DMEIE

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

TEIE

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

HTIE

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TCIE

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

PFCTRL

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

DIR

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

CIRC

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PINCOS

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

PL

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

DBM

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

TRBUFF

Bit 20: Enable the DMA to handle bufferable transfers.

Allowed values:
0: Disabled: Bufferable transfers not enabled
1: Enabled: Bufferable transfers enabled

PBURST

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

MBURST

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

NDTR [3]

stream x number of data register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

PAR [3]

stream x peripheral address register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [3]

stream x memory 0 address register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: Memory 0 address.

M1AR [3]

stream x memory 1 address register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

FCR [3]

stream x FIFO control register

Offset: 0x6c, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw
FS
r
DMDIS
rw
FTH
rw
Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

DMDIS

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

FS

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

FEIE

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

CR [4]

stream x configuration register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBURST
rw
PBURST
rw
TRBUFF
rw
CT
rw
DBM
rw
PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
PFCTRL
rw
TCIE
rw
HTIE
rw
TEIE
rw
DMEIE
rw
EN
rw
Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

DMEIE

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

TEIE

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

HTIE

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TCIE

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

PFCTRL

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

DIR

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

CIRC

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PINCOS

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

PL

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

DBM

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

TRBUFF

Bit 20: Enable the DMA to handle bufferable transfers.

Allowed values:
0: Disabled: Bufferable transfers not enabled
1: Enabled: Bufferable transfers enabled

PBURST

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

MBURST

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

NDTR [4]

stream x number of data register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

PAR [4]

stream x peripheral address register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [4]

stream x memory 0 address register

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: Memory 0 address.

M1AR [4]

stream x memory 1 address register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

FCR [4]

stream x FIFO control register

Offset: 0x84, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw
FS
r
DMDIS
rw
FTH
rw
Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

DMDIS

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

FS

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

FEIE

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

CR [5]

stream x configuration register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBURST
rw
PBURST
rw
TRBUFF
rw
CT
rw
DBM
rw
PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
PFCTRL
rw
TCIE
rw
HTIE
rw
TEIE
rw
DMEIE
rw
EN
rw
Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

DMEIE

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

TEIE

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

HTIE

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TCIE

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

PFCTRL

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

DIR

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

CIRC

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PINCOS

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

PL

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

DBM

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

TRBUFF

Bit 20: Enable the DMA to handle bufferable transfers.

Allowed values:
0: Disabled: Bufferable transfers not enabled
1: Enabled: Bufferable transfers enabled

PBURST

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

MBURST

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

NDTR [5]

stream x number of data register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

PAR [5]

stream x peripheral address register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [5]

stream x memory 0 address register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: Memory 0 address.

M1AR [5]

stream x memory 1 address register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

FCR [5]

stream x FIFO control register

Offset: 0x9c, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw
FS
r
DMDIS
rw
FTH
rw
Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

DMDIS

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

FS

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

FEIE

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

CR [6]

stream x configuration register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBURST
rw
PBURST
rw
TRBUFF
rw
CT
rw
DBM
rw
PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
PFCTRL
rw
TCIE
rw
HTIE
rw
TEIE
rw
DMEIE
rw
EN
rw
Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

DMEIE

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

TEIE

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

HTIE

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TCIE

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

PFCTRL

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

DIR

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

CIRC

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PINCOS

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

PL

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

DBM

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

TRBUFF

Bit 20: Enable the DMA to handle bufferable transfers.

Allowed values:
0: Disabled: Bufferable transfers not enabled
1: Enabled: Bufferable transfers enabled

PBURST

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

MBURST

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

NDTR [6]

stream x number of data register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

PAR [6]

stream x peripheral address register

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [6]

stream x memory 0 address register

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: Memory 0 address.

M1AR [6]

stream x memory 1 address register

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

FCR [6]

stream x FIFO control register

Offset: 0xb4, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw
FS
r
DMDIS
rw
FTH
rw
Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

DMDIS

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

FS

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

FEIE

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

CR [7]

stream x configuration register

Offset: 0xb8, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBURST
rw
PBURST
rw
TRBUFF
rw
CT
rw
DBM
rw
PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
PFCTRL
rw
TCIE
rw
HTIE
rw
TEIE
rw
DMEIE
rw
EN
rw
Toggle fields

EN

Bit 0: Stream enable / flag stream ready when read low.

Allowed values:
0: Disabled: Stream disabled
1: Enabled: Stream enabled

DMEIE

Bit 1: Direct mode error interrupt enable.

Allowed values:
0: Disabled: DME interrupt disabled
1: Enabled: DME interrupt enabled

TEIE

Bit 2: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

HTIE

Bit 3: Half transfer interrupt enable.

Allowed values:
0: Disabled: HT interrupt disabled
1: Enabled: HT interrupt enabled

TCIE

Bit 4: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

PFCTRL

Bit 5: Peripheral flow controller.

Allowed values:
0: DMA: The DMA is the flow controller
1: Peripheral: The peripheral is the flow controller

DIR

Bits 6-7: Data transfer direction.

Allowed values:
0: PeripheralToMemory: Peripheral-to-memory
1: MemoryToPeripheral: Memory-to-peripheral
2: MemoryToMemory: Memory-to-memory

CIRC

Bit 8: Circular mode.

Allowed values:
0: Disabled: Circular mode disabled
1: Enabled: Circular mode enabled

PINC

Bit 9: Peripheral increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

MINC

Bit 10: Memory increment mode.

Allowed values:
0: Fixed: Address pointer is fixed
1: Incremented: Address pointer is incremented after each data transfer

PSIZE

Bits 11-12: Peripheral data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

MSIZE

Bits 13-14: Memory data size.

Allowed values:
0: Bits8: Byte (8-bit)
1: Bits16: Half-word (16-bit)
2: Bits32: Word (32-bit)

PINCOS

Bit 15: Peripheral increment offset size.

Allowed values:
0: PSIZE: The offset size for the peripheral address calculation is linked to the PSIZE
1: Fixed4: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)

PL

Bits 16-17: Priority level.

Allowed values:
0: Low: Low
1: Medium: Medium
2: High: High
3: VeryHigh: Very high

DBM

Bit 18: Double buffer mode.

Allowed values:
0: Disabled: No buffer switching at the end of transfer
1: Enabled: Memory target switched at the end of the DMA transfer

CT

Bit 19: Current target (only in double buffer mode).

Allowed values:
0: Memory0: The current target memory is Memory 0
1: Memory1: The current target memory is Memory 1

TRBUFF

Bit 20: Enable the DMA to handle bufferable transfers.

Allowed values:
0: Disabled: Bufferable transfers not enabled
1: Enabled: Bufferable transfers enabled

PBURST

Bits 21-22: Peripheral burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

MBURST

Bits 23-24: Memory burst transfer configuration.

Allowed values:
0: Single: Single transfer
1: INCR4: Incremental burst of 4 beats
2: INCR8: Incremental burst of 8 beats
3: INCR16: Incremental burst of 16 beats

NDTR [7]

stream x number of data register

Offset: 0xbc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data items to transfer.

Allowed values: 0x0-0xffff

PAR [7]

stream x peripheral address register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [7]

stream x memory 0 address register

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: Memory 0 address.

M1AR [7]

stream x memory 1 address register

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

FCR [7]

stream x FIFO control register

Offset: 0xcc, size: 32, reset: 0x00000021, access: Unspecified

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw
FS
r
DMDIS
rw
FTH
rw
Toggle fields

FTH

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

DMDIS

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

FS

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

FEIE

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

DMA2D

0x52001000: DMA2D

55/66 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 ISR
0x8 IFCR
0xc FGMAR
0x10 FGOR
0x14 BGMAR
0x18 BGOR
0x1c FGPFCCR
0x20 FGCOLR
0x24 BGPFCCR
0x28 BGCOLR
0x2c FGCMAR
0x30 BGCMAR
0x34 OPFCCR
0x38 OCOLR
0x3c OMAR
0x40 OOR
0x44 NLR
0x48 LWR
0x4c AMTCR
Toggle registers

CR

DMA2D control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CEIE
rw
CTCIE
rw
CAEIE
rw
TWIE
rw
TCIE
rw
TEIE
rw
ABORT
rw
SUSP
rw
START
rw
Toggle fields

START

Bit 0: Start This bit can be used to launch the DMA2D according to the parameters loaded in the various configuration registers.

Allowed values:
1: Start: Launch the DMA2D

SUSP

Bit 1: Suspend This bit can be used to suspend the current transfer. This bit is set and reset by software. It is automatically reset by hardware when the START bit is reset..

Allowed values:
0: NotSuspended: Transfer not suspended
1: Suspended: Transfer suspended

ABORT

Bit 2: Abort This bit can be used to abort the current transfer. This bit is set by software and is automatically reset by hardware when the START bit is reset..

Allowed values:
1: AbortRequest: Transfer abort requested

TEIE

Bit 8: Transfer error interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

TCIE

Bit 9: Transfer complete interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

TWIE

Bit 10: Transfer watermark interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: TW interrupt disabled
1: Enabled: TW interrupt enabled

CAEIE

Bit 11: CLUT access error interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: CAE interrupt disabled
1: Enabled: CAE interrupt enabled

CTCIE

Bit 12: CLUT transfer complete interrupt enable This bit is set and cleared by software..

Allowed values:
0: Disabled: CTC interrupt disabled
1: Enabled: CTC interrupt enabled

CEIE

Bit 13: Configuration Error Interrupt Enable This bit is set and cleared by software..

Allowed values:
0: Disabled: CE interrupt disabled
1: Enabled: CE interrupt enabled

MODE

Bits 16-17: DMA2D mode This bit is set and cleared by software. It cannot be modified while a transfer is ongoing..

Allowed values:
0: MemoryToMemory: Memory-to-memory (FG fetch only)
1: MemoryToMemoryPFC: Memory-to-memory with PFC (FG fetch only with FG PFC active)
2: MemoryToMemoryPFCBlending: Memory-to-memory with blending (FG and BG fetch with PFC and blending)
3: RegisterToMemory: Register-to-memory

ISR

DMA2D Interrupt Status Register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CEIF
r
CTCIF
r
CAEIF
r
TWIF
r
TCIF
r
TEIF
r
Toggle fields

TEIF

Bit 0: Transfer error interrupt flag This bit is set when an error occurs during a DMA transfer (data transfer or automatic CLUT loading)..

TCIF

Bit 1: Transfer complete interrupt flag This bit is set when a DMA2D transfer operation is complete (data transfer only)..

TWIF

Bit 2: Transfer watermark interrupt flag This bit is set when the last pixel of the watermarked line has been transferred..

CAEIF

Bit 3: CLUT access error interrupt flag This bit is set when the CPU accesses the CLUT while the CLUT is being automatically copied from a system memory to the internal DMA2D..

CTCIF

Bit 4: CLUT transfer complete interrupt flag This bit is set when the CLUT copy from a system memory area to the internal DMA2D memory is complete..

CEIF

Bit 5: Configuration error interrupt flag This bit is set when the START bit of DMA2D_CR, DMA2DFGPFCCR or DMA2D_BGPFCCR is set and a wrong configuration has been programmed..

IFCR

DMA2D interrupt flag clear register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCEIF
rw
CCTCIF
rw
CAECIF
rw
CTWIF
rw
CTCIF
rw
CTEIF
rw
Toggle fields

CTEIF

Bit 0: Clear Transfer error interrupt flag Programming this bit to 1 clears the TEIF flag in the DMA2D_ISR register.

Allowed values:
1: Clear: Clear the TEIF flag in the ISR register

CTCIF

Bit 1: Clear transfer complete interrupt flag Programming this bit to 1 clears the TCIF flag in the DMA2D_ISR register.

Allowed values:
1: Clear: Clear the TCIF flag in the ISR register

CTWIF

Bit 2: Clear transfer watermark interrupt flag Programming this bit to 1 clears the TWIF flag in the DMA2D_ISR register.

Allowed values:
1: Clear: Clear the TWIF flag in the ISR register

CAECIF

Bit 3: Clear CLUT access error interrupt flag Programming this bit to 1 clears the CAEIF flag in the DMA2D_ISR register.

Allowed values:
1: Clear: Clear the CAEIF flag in the ISR register

CCTCIF

Bit 4: Clear CLUT transfer complete interrupt flag Programming this bit to 1 clears the CTCIF flag in the DMA2D_ISR register.

Allowed values:
1: Clear: Clear the CTCIF flag in the ISR register

CCEIF

Bit 5: Clear configuration error interrupt flag Programming this bit to 1 clears the CEIF flag in the DMA2D_ISR register.

Allowed values:
1: Clear: Clear the CEIF flag in the ISR register

FGMAR

DMA2D foreground memory address register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address Address of the data used for the foreground image. This register can only be written when data transfers are disabled. Once the data transfer has started, this register is read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit per pixel format must be 8-bit aligned..

FGOR

DMA2D foreground offset register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 0-15: Line offset Line offset used for the foreground expressed in pixel. This value is used to generate the address. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once a data transfer has started, they become read-only. If the image format is 4-bit per pixel, the line offset must be even..

Allowed values: 0x0-0xffff

BGMAR

DMA2D background memory address register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address Address of the data used for the background image. This register can only be written when data transfers are disabled. Once a data transfer has started, this register is read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit per pixel format must be 8-bit aligned..

BGOR

DMA2D background offset register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 0-15: Line offset Line offset used for the background image (expressed in pixel). This value is used for the address generation. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once data transfer has started, they become read-only. If the image format is 4-bit per pixel, the line offset must be even..

Allowed values: 0x0-0xffff

FGPFCCR

DMA2D foreground PFC control register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

8/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALPHA
rw
RBS
rw
AI
rw
CSS
rw
AM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS
rw
START
rw
CCM
rw
CM
rw
Toggle fields

CM

Bits 0-3: Color mode These bits defines the color format of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless.

Allowed values:
0: ARGB8888: Color mode ARGB8888
1: RGB888: Color mode RGB888
2: RGB565: Color mode RGB565
3: ARGB1555: Color mode ARGB1555
4: ARGB4444: Color mode ARGB4444
5: L8: Color mode L8
6: AL44: Color mode AL44
7: AL88: Color mode AL88
8: L4: Color mode L4
9: A8: Color mode A8
10: A4: Color mode A4
11: YCbCr: Color mode YCbCr

CCM

Bit 4: CLUT color mode This bit defines the color format of the CLUT. It can only be written when the transfer is disabled. Once the CLUT transfer has started, this bit is read-only..

Allowed values:
0: ARGB8888: CLUT color format ARGB8888
1: RGB888: CLUT color format RGB888

START

Bit 5: Start This bit can be set to start the automatic loading of the CLUT. It is automatically reset: ** at the end of the transfer ** when the transfer is aborted by the user application by setting the ABORT bit in DMA2D_CR ** when a transfer error occurs ** when the transfer has not started due to a configuration error or another transfer operation already ongoing (data transfer or automatic background CLUT transfer)..

Allowed values:
1: Start: Start the automatic loading of the CLUT

CS

Bits 8-15: CLUT size These bits define the size of the CLUT used for the foreground image. Once the CLUT transfer has started, this field is read-only. The number of CLUT entries is equal to CS[7:0] + 1..

Allowed values: 0x0-0xff

AM

Bits 16-17: Alpha mode These bits select the alpha channel value to be used for the foreground image. They can only be written data the transfer are disabled. Once the transfer has started, they become read-only. other configurations are meaningless.

Allowed values:
0: NoModify: No modification of alpha channel
1: Replace: Replace with value in ALPHA[7:0]
2: Multiply: Multiply with value in ALPHA[7:0]

CSS

Bits 18-19: Chroma Sub-Sampling These bits define the chroma sub-sampling mode for YCbCr color mode. Once the transfer has started, these bits are read-only. others: meaningless.

AI

Bit 20: Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only..

Allowed values:
0: RegularAlpha: Regular alpha
1: InvertedAlpha: Inverted alpha

RBS

Bit 21: Red Blue Swap This bit allows to swap the R &amp; B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only..

Allowed values:
0: Regular: No Red Blue Swap (RGB or ARGB)
1: Swap: Red Blue Swap (BGR or ABGR)

ALPHA

Bits 24-31: Alpha value These bits define a fixed alpha channel value which can replace the original alpha value or be multiplied by the original alpha value according to the alpha mode selected through the AM[1:0] bits. These bits can only be written when data transfers are disabled. Once a transfer has started, they become read-only..

Allowed values: 0x0-0xff

FGCOLR

DMA2D foreground color register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GREEN
rw
BLUE
rw
Toggle fields

BLUE

Bits 0-7: Blue Value These bits defines the blue value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, They are read-only..

Allowed values: 0x0-0xff

GREEN

Bits 8-15: Green Value These bits defines the green value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, They are read-only..

Allowed values: 0x0-0xff

RED

Bits 16-23: Red Value These bits defines the red value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, they are read-only..

Allowed values: 0x0-0xff

BGPFCCR

DMA2D background PFC control register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALPHA
rw
RBS
rw
AI
rw
AM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS
rw
START
rw
CCM
rw
CM
rw
Toggle fields

CM

Bits 0-3: Color mode These bits define the color format of the foreground image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless.

Allowed values:
0: ARGB8888: Color mode ARGB8888
1: RGB888: Color mode RGB888
2: RGB565: Color mode RGB565
3: ARGB1555: Color mode ARGB1555
4: ARGB4444: Color mode ARGB4444
5: L8: Color mode L8
6: AL44: Color mode AL44
7: AL88: Color mode AL88
8: L4: Color mode L4
9: A8: Color mode A8
10: A4: Color mode A4

CCM

Bit 4: CLUT Color mode These bits define the color format of the CLUT. This register can only be written when the transfer is disabled. Once the CLUT transfer has started, this bit is read-only..

Allowed values:
0: ARGB8888: CLUT color format ARGB8888
1: RGB888: CLUT color format RGB888

START

Bit 5: Start This bit is set to start the automatic loading of the CLUT. This bit is automatically reset: ** at the end of the transfer ** when the transfer is aborted by the user application by setting the ABORT bit in the DMA2D_CR ** when a transfer error occurs ** when the transfer has not started due to a configuration error or another transfer operation already on going (data transfer or automatic BackGround CLUT transfer)..

Allowed values:
1: Start: Start the automatic loading of the CLUT

CS

Bits 8-15: CLUT size These bits define the size of the CLUT used for the BG. Once the CLUT transfer has started, this field is read-only. The number of CLUT entries is equal to CS[7:0] + 1..

Allowed values: 0x0-0xff

AM

Bits 16-17: Alpha mode These bits define which alpha channel value to be used for the background image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless.

Allowed values:
0: NoModify: No modification of alpha channel
1: Replace: Replace with value in ALPHA[7:0]
2: Multiply: Multiply with value in ALPHA[7:0]

AI

Bit 20: Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only..

Allowed values:
0: RegularAlpha: Regular alpha
1: InvertedAlpha: Inverted alpha

RBS

Bit 21: Red Blue Swap This bit allows to swap the R &amp; B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only..

Allowed values:
0: Regular: No Red Blue Swap (RGB or ARGB)
1: Swap: Red Blue Swap (BGR or ABGR)

ALPHA

Bits 24-31: Alpha value These bits define a fixed alpha channel value which can replace the original alpha value or be multiplied with the original alpha value according to the alpha mode selected with bits AM[1: 0]. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only..

Allowed values: 0x0-0xff

BGCOLR

DMA2D background color register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GREEN
rw
BLUE
rw
Toggle fields

BLUE

Bits 0-7: Blue Value These bits define the blue value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only..

Allowed values: 0x0-0xff

GREEN

Bits 8-15: Green Value These bits define the green value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only..

Allowed values: 0x0-0xff

RED

Bits 16-23: Red Value These bits define the red value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only..

Allowed values: 0x0-0xff

FGCMAR

DMA2D foreground CLUT memory address register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory Address Address of the data used for the CLUT address dedicated to the foreground image. This register can only be written when no transfer is ongoing. Once the CLUT transfer has started, this register is read-only. If the foreground CLUT format is 32-bit, the address must be 32-bit aligned..

BGCMAR

DMA2D background CLUT memory address register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address Address of the data used for the CLUT address dedicated to the background image. This register can only be written when no transfer is on going. Once the CLUT transfer has started, this register is read-only. If the background CLUT format is 32-bit, the address must be 32-bit aligned..

OPFCCR

DMA2D output PFC control register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RBS
rw
AI
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SB
rw
CM
rw
Toggle fields

CM

Bits 0-2: Color mode These bits define the color format of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless.

Allowed values:
0: ARGB8888: ARGB8888
1: RGB888: RGB888
2: RGB565: RGB565
3: ARGB1555: ARGB1555
4: ARGB4444: ARGB4444

SB

Bit 8: Swap Bytes.

Allowed values:
0: Regular: Regular byte order
1: SwapBytes: Bytes are swapped two by two

AI

Bit 20: Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only..

Allowed values:
0: RegularAlpha: Regular alpha
1: InvertedAlpha: Inverted alpha

RBS

Bit 21: Red Blue Swap This bit allows to swap the R &amp; B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only..

Allowed values:
0: Regular: No Red Blue Swap (RGB or ARGB)
1: Swap: Red Blue Swap (BGR or ABGR)

OCOLR

DMA2D output color register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALPHA
rw
RED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GREEN
rw
BLUE
rw
Toggle fields

BLUE

Bits 0-7: Blue Value These bits define the blue value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only..

GREEN

Bits 8-15: Green Value These bits define the green value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only..

RED

Bits 16-23: Red Value These bits define the red value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only..

ALPHA

Bits 24-31: Alpha Channel Value These bits define the alpha channel of the output color. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only..

OMAR

DMA2D output memory address register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory Address Address of the data used for the output FIFO. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned and a 16-bit per pixel format must be 16-bit aligned..

OOR

DMA2D output offset register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 0-15: Line Offset Line offset used for the output (expressed in pixels). This value is used for the address generation. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only..

Allowed values: 0x0-0xffff

NLR

DMA2D number of line register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NL
rw
Toggle fields

NL

Bits 0-15: Number of lines Number of lines of the area to be transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only..

Allowed values: 0x0-0xffff

PL

Bits 16-29: Pixel per lines Number of pixels per lines of the area to be transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. If any of the input image format is 4-bit per pixel, pixel per lines must be even..

Allowed values: 0x0-0x3fff

LWR

DMA2D line watermark register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LW
rw
Toggle fields

LW

Bits 0-15: Line watermark These bits allow to configure the line watermark for interrupt generation. An interrupt is raised when the last pixel of the watermarked line has been transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only..

AMTCR

DMA2D AXI master timer configuration register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DT
rw
EN
rw
Toggle fields

EN

Bit 0: Enable Enables the dead time functionality..

Allowed values:
0: Disabled: Disabled AHB/AXI dead-time functionality
1: Enabled: Enabled AHB/AXI dead-time functionality

DT

Bits 8-15: Dead Time Dead time value in the AXI clock cycle inserted between two consecutive accesses on the AXI master port. These bits represent the minimum guaranteed number of cycles between two consecutive AXI accesses..

Allowed values: 0x0-0xff

DMAMUX1

0x40020800: DMAMUX

200/200 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 C[0]CR
0x4 C[1]CR
0x8 C[2]CR
0xc C[3]CR
0x10 C[4]CR
0x14 C[5]CR
0x18 C[6]CR
0x1c C[7]CR
0x20 C[8]CR
0x24 C[9]CR
0x28 C[10]CR
0x2c C[11]CR
0x30 C[12]CR
0x34 C[13]CR
0x38 C[14]CR
0x3c C[15]CR
0x80 CSR
0x84 CFR
0x100 RG[0]CR
0x104 RG[1]CR
0x108 RG[2]CR
0x10c RG[3]CR
0x110 RG[4]CR
0x114 RG[5]CR
0x118 RG[6]CR
0x11c RG[7]CR
0x140 RGSR
0x144 RGCFR
Toggle registers

C[0]CR

DMAMux - DMA request line multiplexer channel x control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-7: Input DMA request line selected.

Allowed values:
0: none: No signal selected as request input
1: dmamux1_req_gen0: Signal `dmamux1_req_gen0` selected as request input
2: dmamux1_req_gen1: Signal `dmamux1_req_gen1` selected as request input
3: dmamux1_req_gen2: Signal `dmamux1_req_gen2` selected as request input
4: dmamux1_req_gen3: Signal `dmamux1_req_gen3` selected as request input
5: dmamux1_req_gen4: Signal `dmamux1_req_gen4` selected as request input
6: dmamux1_req_gen5: Signal `dmamux1_req_gen5` selected as request input
7: dmamux1_req_gen6: Signal `dmamux1_req_gen6` selected as request input
8: dmamux1_req_gen7: Signal `dmamux1_req_gen7` selected as request input
9: adc1_dma: Signal `adc1_dma` selected as request input
10: adc2_dma: Signal `adc2_dma` selected as request input
11: tim1_ch1: Signal `tim1_ch1` selected as request input
12: tim1_ch2: Signal `tim1_ch2` selected as request input
13: tim1_ch3: Signal `tim1_ch3` selected as request input
14: tim1_ch4: Signal `tim1_ch4` selected as request input
15: tim1_up: Signal `tim1_up` selected as request input
16: tim1_trig: Signal `tim1_trig` selected as request input
17: tim1_com: Signal `tim1_com` selected as request input
18: tim2_ch1: Signal `tim2_ch1` selected as request input
19: tim2_ch2: Signal `tim2_ch2` selected as request input
20: tim2_ch3: Signal `tim2_ch3` selected as request input
21: tim2_ch4: Signal `tim2_ch4` selected as request input
22: tim2_up: Signal `tim2_up` selected as request input
23: tim3_ch1: Signal `tim3_ch1` selected as request input
24: tim3_ch2: Signal `tim3_ch2` selected as request input
25: tim3_ch3: Signal `tim3_ch3` selected as request input
26: tim3_ch4: Signal `tim3_ch4` selected as request input
27: tim3_up: Signal `tim3_up` selected as request input
28: tim3_trig: Signal `tim3_trig` selected as request input
29: tim4_ch1: Signal `tim4_ch1` selected as request input
30: tim4_ch2: Signal `tim4_ch2` selected as request input
31: tim4_ch3: Signal `tim4_ch3` selected as request input
32: tim4_up: Signal `tim4_up` selected as request input
33: i2c1_rx_dma: Signal `i2c1_rx_dma` selected as request input
34: i2c1_tx_dma: Signal `i2c1_tx_dma` selected as request input
35: i2c2_rx_dma: Signal `i2c2_rx_dma` selected as request input
36: i2c2_tx_dma: Signal `i2c2_tx_dma` selected as request input
37: spi1_rx_dma: Signal `spi1_rx_dma` selected as request input
38: spi1_tx_dma: Signal `spi1_tx_dma` selected as request input
39: spi2_rx_dma: Signal `spi2_rx_dma` selected as request input
40: spi2_tx_dma: Signal `spi2_tx_dma` selected as request input
41: usart1_rx_dma: Signal `usart1_rx_dma` selected as request input
42: usart1_tx_dma: Signal `usart1_tx_dma` selected as request input
43: usart2_rx_dma: Signal `usart2_rx_dma` selected as request input
44: usart2_tx_dma: Signal `usart2_tx_dma` selected as request input
45: usart3_rx_dma: Signal `usart3_rx_dma` selected as request input
46: usart3_tx_dma: Signal `usart3_tx_dma` selected as request input
47: tim8_ch1: Signal `tim8_ch1` selected as request input
48: tim8_ch2: Signal `tim8_ch2` selected as request input
49: tim8_ch3: Signal `tim8_ch3` selected as request input
50: tim8_ch4: Signal `tim8_ch4` selected as request input
51: tim8_up: Signal `tim8_up` selected as request input
52: tim8_trig: Signal `tim8_trig` selected as request input
53: tim8_com: Signal `tim8_com` selected as request input
55: tim5_ch1: Signal `tim5_ch1` selected as request input
56: tim5_ch2: Signal `tim5_ch2` selected as request input
57: tim5_ch3: Signal `tim5_ch3` selected as request input
58: tim5_ch4: Signal `tim5_ch4` selected as request input
59: tim5_up: Signal `tim5_up` selected as request input
60: tim5_trig: Signal `tim5_trig` selected as request input
61: spi3_rx_dma: Signal `spi3_rx_dma` selected as request input
62: spi3_tx_dma: Signal `spi3_tx_dma` selected as request input
63: uart4_rx_dma: Signal `uart4_rx_dma` selected as request input
64: uart4_tx_dma: Signal `uart4_tx_dma` selected as request input
65: uart5_rx_dma: Signal `uart5_rx_dma` selected as request input
66: uart5_tx_dma: Signal `uart5_tx_dma` selected as request input
67: dac_ch1_dma: Signal `dac_ch1_dma` selected as request input
68: dac_ch2_dma: Signal `dac_ch2_dma` selected as request input
69: tim6_up: Signal `tim6_up` selected as request input
70: tim7_up: Signal `tim7_up` selected as request input
71: usart6_rx_dma: Signal `usart6_rx_dma` selected as request input
72: usart6_tx_dma: Signal `usart6_tx_dma` selected as request input
73: i2c3_rx_dma: Signal `i2c3_rx_dma` selected as request input
74: i2c3_tx_dma: Signal `i2c3_tx_dma` selected as request input
75: dcmi_dma: Signal `dcmi_dma` selected as request input
76: cryp_in_dma: Signal `cryp_in_dma` selected as request input
77: cryp_out_dma: Signal `cryp_out_dma` selected as request input
78: hash_in_dma: Signal `hash_in_dma` selected as request input
79: uart7_rx_dma: Signal `uart7_rx_dma` selected as request input
80: uart7_tx_dma: Signal `uart7_tx_dma` selected as request input
81: uart8_rx_dma: Signal `uart8_rx_dma` selected as request input
82: uart8_tx_dma: Signal `uart8_tx_dma` selected as request input
83: spi4_rx_dma: Signal `spi4_rx_dma` selected as request input
84: spi4_tx_dma: Signal `spi4_tx_dma` selected as request input
85: spi5_rx_dma: Signal `spi5_rx_dma` selected as request input
86: spi5_tx_dma: Signal `spi5_tx_dma` selected as request input
87: sai1a_dma: Signal `sai1a_dma` selected as request input
88: sai1b_dma: Signal `sai1b_dma` selected as request input
89: sai2a_dma: Signal `sai2a_dma` selected as request input
90: sai2b_dma: Signal `sai2b_dma` selected as request input
91: swpmi_rx_dma: Signal `swpmi_rx_dma` selected as request input
92: swpmi_tx_dma: Signal `swpmi_tx_dma` selected as request input
93: spdifrx_dat_dma: Signal `spdifrx_dat_dma` selected as request input
94: spdifrx_ctrl_dma: Signal `spdifrx_ctrl_dma` selected as request input
95: hr_req1: Signal `hr_req(1)` selected as request input
96: hr_req2: Signal `hr_req(2)` selected as request input
97: hr_req3: Signal `hr_req(3)` selected as request input
98: hr_req4: Signal `hr_req(4)` selected as request input
99: hr_req5: Signal `hr_req(5)` selected as request input
100: hr_req6: Signal `hr_req(6)` selected as request input
101: dfsdm1_dma0: Signal `dfsdm1_dma0` selected as request input
102: dfsdm1_dma1: Signal `dfsdm1_dma1` selected as request input
103: dfsdm1_dma2: Signal `dfsdm1_dma2` selected as request input
104: dfsdm1_dma3: Signal `dfsdm1_dma3` selected as request input
105: tim15_ch1: Signal `tim15_ch1` selected as request input
106: tim15_up: Signal `tim15_up` selected as request input
107: tim15_trig: Signal `tim15_trig` selected as request input
108: tim15_com: Signal `tim15_com` selected as request input
109: tim16_ch1: Signal `tim16_ch1` selected as request input
110: tim16_up: Signal `tim16_up` selected as request input
111: tim17_ch1: Signal `tim17_ch1` selected as request input
112: tim17_up: Signal `tim17_up` selected as request input
113: sai3_a_dma: Signal `sai3_a_dma` selected as request input
114: sai3_b_dma: Signal `sai3_b_dma` selected as request input
115: adc3_dma: Signal `adc3_dma` selected as request input

SOIE

Bit 8: Interrupt enable at synchronization event overrun.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable/disable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronous operating mode enable/disable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization event type selector Defines the synchronization event on the selected synchronization input:.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset..

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization input selected.

Allowed values:
0: dmamux1_evt0: Signal `dmamux1_evt0` selected as synchronization input
1: dmamux1_evt1: Signal `dmamux1_evt1` selected as synchronization input
2: dmamux1_evt2: Signal `dmamux1_evt2` selected as synchronization input
3: lptim1_out: Signal `lptim1_out` selected as synchronization input
4: lptim2_out: Signal `lptim2_out` selected as synchronization input
5: lptim3_out: Signal `lptim3_out` selected as synchronization input
6: extit0: Signal `extit0` selected as synchronization input
7: tim12_trgo: Signal `tim12_trgo` selected as synchronization input

C[1]CR

DMAMux - DMA request line multiplexer channel x control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-7: Input DMA request line selected.

Allowed values:
0: none: No signal selected as request input
1: dmamux1_req_gen0: Signal `dmamux1_req_gen0` selected as request input
2: dmamux1_req_gen1: Signal `dmamux1_req_gen1` selected as request input
3: dmamux1_req_gen2: Signal `dmamux1_req_gen2` selected as request input
4: dmamux1_req_gen3: Signal `dmamux1_req_gen3` selected as request input
5: dmamux1_req_gen4: Signal `dmamux1_req_gen4` selected as request input
6: dmamux1_req_gen5: Signal `dmamux1_req_gen5` selected as request input
7: dmamux1_req_gen6: Signal `dmamux1_req_gen6` selected as request input
8: dmamux1_req_gen7: Signal `dmamux1_req_gen7` selected as request input
9: adc1_dma: Signal `adc1_dma` selected as request input
10: adc2_dma: Signal `adc2_dma` selected as request input
11: tim1_ch1: Signal `tim1_ch1` selected as request input
12: tim1_ch2: Signal `tim1_ch2` selected as request input
13: tim1_ch3: Signal `tim1_ch3` selected as request input
14: tim1_ch4: Signal `tim1_ch4` selected as request input
15: tim1_up: Signal `tim1_up` selected as request input
16: tim1_trig: Signal `tim1_trig` selected as request input
17: tim1_com: Signal `tim1_com` selected as request input
18: tim2_ch1: Signal `tim2_ch1` selected as request input
19: tim2_ch2: Signal `tim2_ch2` selected as request input
20: tim2_ch3: Signal `tim2_ch3` selected as request input
21: tim2_ch4: Signal `tim2_ch4` selected as request input
22: tim2_up: Signal `tim2_up` selected as request input
23: tim3_ch1: Signal `tim3_ch1` selected as request input
24: tim3_ch2: Signal `tim3_ch2` selected as request input
25: tim3_ch3: Signal `tim3_ch3` selected as request input
26: tim3_ch4: Signal `tim3_ch4` selected as request input
27: tim3_up: Signal `tim3_up` selected as request input
28: tim3_trig: Signal `tim3_trig` selected as request input
29: tim4_ch1: Signal `tim4_ch1` selected as request input
30: tim4_ch2: Signal `tim4_ch2` selected as request input
31: tim4_ch3: Signal `tim4_ch3` selected as request input
32: tim4_up: Signal `tim4_up` selected as request input
33: i2c1_rx_dma: Signal `i2c1_rx_dma` selected as request input
34: i2c1_tx_dma: Signal `i2c1_tx_dma` selected as request input
35: i2c2_rx_dma: Signal `i2c2_rx_dma` selected as request input
36: i2c2_tx_dma: Signal `i2c2_tx_dma` selected as request input
37: spi1_rx_dma: Signal `spi1_rx_dma` selected as request input
38: spi1_tx_dma: Signal `spi1_tx_dma` selected as request input
39: spi2_rx_dma: Signal `spi2_rx_dma` selected as request input
40: spi2_tx_dma: Signal `spi2_tx_dma` selected as request input
41: usart1_rx_dma: Signal `usart1_rx_dma` selected as request input
42: usart1_tx_dma: Signal `usart1_tx_dma` selected as request input
43: usart2_rx_dma: Signal `usart2_rx_dma` selected as request input
44: usart2_tx_dma: Signal `usart2_tx_dma` selected as request input
45: usart3_rx_dma: Signal `usart3_rx_dma` selected as request input
46: usart3_tx_dma: Signal `usart3_tx_dma` selected as request input
47: tim8_ch1: Signal `tim8_ch1` selected as request input
48: tim8_ch2: Signal `tim8_ch2` selected as request input
49: tim8_ch3: Signal `tim8_ch3` selected as request input
50: tim8_ch4: Signal `tim8_ch4` selected as request input
51: tim8_up: Signal `tim8_up` selected as request input
52: tim8_trig: Signal `tim8_trig` selected as request input
53: tim8_com: Signal `tim8_com` selected as request input
55: tim5_ch1: Signal `tim5_ch1` selected as request input
56: tim5_ch2: Signal `tim5_ch2` selected as request input
57: tim5_ch3: Signal `tim5_ch3` selected as request input
58: tim5_ch4: Signal `tim5_ch4` selected as request input
59: tim5_up: Signal `tim5_up` selected as request input
60: tim5_trig: Signal `tim5_trig` selected as request input
61: spi3_rx_dma: Signal `spi3_rx_dma` selected as request input
62: spi3_tx_dma: Signal `spi3_tx_dma` selected as request input
63: uart4_rx_dma: Signal `uart4_rx_dma` selected as request input
64: uart4_tx_dma: Signal `uart4_tx_dma` selected as request input
65: uart5_rx_dma: Signal `uart5_rx_dma` selected as request input
66: uart5_tx_dma: Signal `uart5_tx_dma` selected as request input
67: dac_ch1_dma: Signal `dac_ch1_dma` selected as request input
68: dac_ch2_dma: Signal `dac_ch2_dma` selected as request input
69: tim6_up: Signal `tim6_up` selected as request input
70: tim7_up: Signal `tim7_up` selected as request input
71: usart6_rx_dma: Signal `usart6_rx_dma` selected as request input
72: usart6_tx_dma: Signal `usart6_tx_dma` selected as request input
73: i2c3_rx_dma: Signal `i2c3_rx_dma` selected as request input
74: i2c3_tx_dma: Signal `i2c3_tx_dma` selected as request input
75: dcmi_dma: Signal `dcmi_dma` selected as request input
76: cryp_in_dma: Signal `cryp_in_dma` selected as request input
77: cryp_out_dma: Signal `cryp_out_dma` selected as request input
78: hash_in_dma: Signal `hash_in_dma` selected as request input
79: uart7_rx_dma: Signal `uart7_rx_dma` selected as request input
80: uart7_tx_dma: Signal `uart7_tx_dma` selected as request input
81: uart8_rx_dma: Signal `uart8_rx_dma` selected as request input
82: uart8_tx_dma: Signal `uart8_tx_dma` selected as request input
83: spi4_rx_dma: Signal `spi4_rx_dma` selected as request input
84: spi4_tx_dma: Signal `spi4_tx_dma` selected as request input
85: spi5_rx_dma: Signal `spi5_rx_dma` selected as request input
86: spi5_tx_dma: Signal `spi5_tx_dma` selected as request input
87: sai1a_dma: Signal `sai1a_dma` selected as request input
88: sai1b_dma: Signal `sai1b_dma` selected as request input
89: sai2a_dma: Signal `sai2a_dma` selected as request input
90: sai2b_dma: Signal `sai2b_dma` selected as request input
91: swpmi_rx_dma: Signal `swpmi_rx_dma` selected as request input
92: swpmi_tx_dma: Signal `swpmi_tx_dma` selected as request input
93: spdifrx_dat_dma: Signal `spdifrx_dat_dma` selected as request input
94: spdifrx_ctrl_dma: Signal `spdifrx_ctrl_dma` selected as request input
95: hr_req1: Signal `hr_req(1)` selected as request input
96: hr_req2: Signal `hr_req(2)` selected as request input
97: hr_req3: Signal `hr_req(3)` selected as request input
98: hr_req4: Signal `hr_req(4)` selected as request input
99: hr_req5: Signal `hr_req(5)` selected as request input
100: hr_req6: Signal `hr_req(6)` selected as request input
101: dfsdm1_dma0: Signal `dfsdm1_dma0` selected as request input
102: dfsdm1_dma1: Signal `dfsdm1_dma1` selected as request input
103: dfsdm1_dma2: Signal `dfsdm1_dma2` selected as request input
104: dfsdm1_dma3: Signal `dfsdm1_dma3` selected as request input
105: tim15_ch1: Signal `tim15_ch1` selected as request input
106: tim15_up: Signal `tim15_up` selected as request input
107: tim15_trig: Signal `tim15_trig` selected as request input
108: tim15_com: Signal `tim15_com` selected as request input
109: tim16_ch1: Signal `tim16_ch1` selected as request input
110: tim16_up: Signal `tim16_up` selected as request input
111: tim17_ch1: Signal `tim17_ch1` selected as request input
112: tim17_up: Signal `tim17_up` selected as request input
113: sai3_a_dma: Signal `sai3_a_dma` selected as request input
114: sai3_b_dma: Signal `sai3_b_dma` selected as request input
115: adc3_dma: Signal `adc3_dma` selected as request input

SOIE

Bit 8: Interrupt enable at synchronization event overrun.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable/disable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronous operating mode enable/disable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization event type selector Defines the synchronization event on the selected synchronization input:.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset..

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization input selected.

Allowed values:
0: dmamux1_evt0: Signal `dmamux1_evt0` selected as synchronization input
1: dmamux1_evt1: Signal `dmamux1_evt1` selected as synchronization input
2: dmamux1_evt2: Signal `dmamux1_evt2` selected as synchronization input
3: lptim1_out: Signal `lptim1_out` selected as synchronization input
4: lptim2_out: Signal `lptim2_out` selected as synchronization input
5: lptim3_out: Signal `lptim3_out` selected as synchronization input
6: extit0: Signal `extit0` selected as synchronization input
7: tim12_trgo: Signal `tim12_trgo` selected as synchronization input

C[2]CR

DMAMux - DMA request line multiplexer channel x control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-7: Input DMA request line selected.

Allowed values:
0: none: No signal selected as request input
1: dmamux1_req_gen0: Signal `dmamux1_req_gen0` selected as request input
2: dmamux1_req_gen1: Signal `dmamux1_req_gen1` selected as request input
3: dmamux1_req_gen2: Signal `dmamux1_req_gen2` selected as request input
4: dmamux1_req_gen3: Signal `dmamux1_req_gen3` selected as request input
5: dmamux1_req_gen4: Signal `dmamux1_req_gen4` selected as request input
6: dmamux1_req_gen5: Signal `dmamux1_req_gen5` selected as request input
7: dmamux1_req_gen6: Signal `dmamux1_req_gen6` selected as request input
8: dmamux1_req_gen7: Signal `dmamux1_req_gen7` selected as request input
9: adc1_dma: Signal `adc1_dma` selected as request input
10: adc2_dma: Signal `adc2_dma` selected as request input
11: tim1_ch1: Signal `tim1_ch1` selected as request input
12: tim1_ch2: Signal `tim1_ch2` selected as request input
13: tim1_ch3: Signal `tim1_ch3` selected as request input
14: tim1_ch4: Signal `tim1_ch4` selected as request input
15: tim1_up: Signal `tim1_up` selected as request input
16: tim1_trig: Signal `tim1_trig` selected as request input
17: tim1_com: Signal `tim1_com` selected as request input
18: tim2_ch1: Signal `tim2_ch1` selected as request input
19: tim2_ch2: Signal `tim2_ch2` selected as request input
20: tim2_ch3: Signal `tim2_ch3` selected as request input
21: tim2_ch4: Signal `tim2_ch4` selected as request input
22: tim2_up: Signal `tim2_up` selected as request input
23: tim3_ch1: Signal `tim3_ch1` selected as request input
24: tim3_ch2: Signal `tim3_ch2` selected as request input
25: tim3_ch3: Signal `tim3_ch3` selected as request input
26: tim3_ch4: Signal `tim3_ch4` selected as request input
27: tim3_up: Signal `tim3_up` selected as request input
28: tim3_trig: Signal `tim3_trig` selected as request input
29: tim4_ch1: Signal `tim4_ch1` selected as request input
30: tim4_ch2: Signal `tim4_ch2` selected as request input
31: tim4_ch3: Signal `tim4_ch3` selected as request input
32: tim4_up: Signal `tim4_up` selected as request input
33: i2c1_rx_dma: Signal `i2c1_rx_dma` selected as request input
34: i2c1_tx_dma: Signal `i2c1_tx_dma` selected as request input
35: i2c2_rx_dma: Signal `i2c2_rx_dma` selected as request input
36: i2c2_tx_dma: Signal `i2c2_tx_dma` selected as request input
37: spi1_rx_dma: Signal `spi1_rx_dma` selected as request input
38: spi1_tx_dma: Signal `spi1_tx_dma` selected as request input
39: spi2_rx_dma: Signal `spi2_rx_dma` selected as request input
40: spi2_tx_dma: Signal `spi2_tx_dma` selected as request input
41: usart1_rx_dma: Signal `usart1_rx_dma` selected as request input
42: usart1_tx_dma: Signal `usart1_tx_dma` selected as request input
43: usart2_rx_dma: Signal `usart2_rx_dma` selected as request input
44: usart2_tx_dma: Signal `usart2_tx_dma` selected as request input
45: usart3_rx_dma: Signal `usart3_rx_dma` selected as request input
46: usart3_tx_dma: Signal `usart3_tx_dma` selected as request input
47: tim8_ch1: Signal `tim8_ch1` selected as request input
48: tim8_ch2: Signal `tim8_ch2` selected as request input
49: tim8_ch3: Signal `tim8_ch3` selected as request input
50: tim8_ch4: Signal `tim8_ch4` selected as request input
51: tim8_up: Signal `tim8_up` selected as request input
52: tim8_trig: Signal `tim8_trig` selected as request input
53: tim8_com: Signal `tim8_com` selected as request input
55: tim5_ch1: Signal `tim5_ch1` selected as request input
56: tim5_ch2: Signal `tim5_ch2` selected as request input
57: tim5_ch3: Signal `tim5_ch3` selected as request input
58: tim5_ch4: Signal `tim5_ch4` selected as request input
59: tim5_up: Signal `tim5_up` selected as request input
60: tim5_trig: Signal `tim5_trig` selected as request input
61: spi3_rx_dma: Signal `spi3_rx_dma` selected as request input
62: spi3_tx_dma: Signal `spi3_tx_dma` selected as request input
63: uart4_rx_dma: Signal `uart4_rx_dma` selected as request input
64: uart4_tx_dma: Signal `uart4_tx_dma` selected as request input
65: uart5_rx_dma: Signal `uart5_rx_dma` selected as request input
66: uart5_tx_dma: Signal `uart5_tx_dma` selected as request input
67: dac_ch1_dma: Signal `dac_ch1_dma` selected as request input
68: dac_ch2_dma: Signal `dac_ch2_dma` selected as request input
69: tim6_up: Signal `tim6_up` selected as request input
70: tim7_up: Signal `tim7_up` selected as request input
71: usart6_rx_dma: Signal `usart6_rx_dma` selected as request input
72: usart6_tx_dma: Signal `usart6_tx_dma` selected as request input
73: i2c3_rx_dma: Signal `i2c3_rx_dma` selected as request input
74: i2c3_tx_dma: Signal `i2c3_tx_dma` selected as request input
75: dcmi_dma: Signal `dcmi_dma` selected as request input
76: cryp_in_dma: Signal `cryp_in_dma` selected as request input
77: cryp_out_dma: Signal `cryp_out_dma` selected as request input
78: hash_in_dma: Signal `hash_in_dma` selected as request input
79: uart7_rx_dma: Signal `uart7_rx_dma` selected as request input
80: uart7_tx_dma: Signal `uart7_tx_dma` selected as request input
81: uart8_rx_dma: Signal `uart8_rx_dma` selected as request input
82: uart8_tx_dma: Signal `uart8_tx_dma` selected as request input
83: spi4_rx_dma: Signal `spi4_rx_dma` selected as request input
84: spi4_tx_dma: Signal `spi4_tx_dma` selected as request input
85: spi5_rx_dma: Signal `spi5_rx_dma` selected as request input
86: spi5_tx_dma: Signal `spi5_tx_dma` selected as request input
87: sai1a_dma: Signal `sai1a_dma` selected as request input
88: sai1b_dma: Signal `sai1b_dma` selected as request input
89: sai2a_dma: Signal `sai2a_dma` selected as request input
90: sai2b_dma: Signal `sai2b_dma` selected as request input
91: swpmi_rx_dma: Signal `swpmi_rx_dma` selected as request input
92: swpmi_tx_dma: Signal `swpmi_tx_dma` selected as request input
93: spdifrx_dat_dma: Signal `spdifrx_dat_dma` selected as request input
94: spdifrx_ctrl_dma: Signal `spdifrx_ctrl_dma` selected as request input
95: hr_req1: Signal `hr_req(1)` selected as request input
96: hr_req2: Signal `hr_req(2)` selected as request input
97: hr_req3: Signal `hr_req(3)` selected as request input
98: hr_req4: Signal `hr_req(4)` selected as request input
99: hr_req5: Signal `hr_req(5)` selected as request input
100: hr_req6: Signal `hr_req(6)` selected as request input
101: dfsdm1_dma0: Signal `dfsdm1_dma0` selected as request input
102: dfsdm1_dma1: Signal `dfsdm1_dma1` selected as request input
103: dfsdm1_dma2: Signal `dfsdm1_dma2` selected as request input
104: dfsdm1_dma3: Signal `dfsdm1_dma3` selected as request input
105: tim15_ch1: Signal `tim15_ch1` selected as request input
106: tim15_up: Signal `tim15_up` selected as request input
107: tim15_trig: Signal `tim15_trig` selected as request input
108: tim15_com: Signal `tim15_com` selected as request input
109: tim16_ch1: Signal `tim16_ch1` selected as request input
110: tim16_up: Signal `tim16_up` selected as request input
111: tim17_ch1: Signal `tim17_ch1` selected as request input
112: tim17_up: Signal `tim17_up` selected as request input
113: sai3_a_dma: Signal `sai3_a_dma` selected as request input
114: sai3_b_dma: Signal `sai3_b_dma` selected as request input
115: adc3_dma: Signal `adc3_dma` selected as request input

SOIE

Bit 8: Interrupt enable at synchronization event overrun.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable/disable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronous operating mode enable/disable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization event type selector Defines the synchronization event on the selected synchronization input:.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset..

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization input selected.

Allowed values:
0: dmamux1_evt0: Signal `dmamux1_evt0` selected as synchronization input
1: dmamux1_evt1: Signal `dmamux1_evt1` selected as synchronization input
2: dmamux1_evt2: Signal `dmamux1_evt2` selected as synchronization input
3: lptim1_out: Signal `lptim1_out` selected as synchronization input
4: lptim2_out: Signal `lptim2_out` selected as synchronization input
5: lptim3_out: Signal `lptim3_out` selected as synchronization input
6: extit0: Signal `extit0` selected as synchronization input
7: tim12_trgo: Signal `tim12_trgo` selected as synchronization input

C[3]CR

DMAMux - DMA request line multiplexer channel x control register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-7: Input DMA request line selected.

Allowed values:
0: none: No signal selected as request input
1: dmamux1_req_gen0: Signal `dmamux1_req_gen0` selected as request input
2: dmamux1_req_gen1: Signal `dmamux1_req_gen1` selected as request input
3: dmamux1_req_gen2: Signal `dmamux1_req_gen2` selected as request input
4: dmamux1_req_gen3: Signal `dmamux1_req_gen3` selected as request input
5: dmamux1_req_gen4: Signal `dmamux1_req_gen4` selected as request input
6: dmamux1_req_gen5: Signal `dmamux1_req_gen5` selected as request input
7: dmamux1_req_gen6: Signal `dmamux1_req_gen6` selected as request input
8: dmamux1_req_gen7: Signal `dmamux1_req_gen7` selected as request input
9: adc1_dma: Signal `adc1_dma` selected as request input
10: adc2_dma: Signal `adc2_dma` selected as request input
11: tim1_ch1: Signal `tim1_ch1` selected as request input
12: tim1_ch2: Signal `tim1_ch2` selected as request input
13: tim1_ch3: Signal `tim1_ch3` selected as request input
14: tim1_ch4: Signal `tim1_ch4` selected as request input
15: tim1_up: Signal `tim1_up` selected as request input
16: tim1_trig: Signal `tim1_trig` selected as request input
17: tim1_com: Signal `tim1_com` selected as request input
18: tim2_ch1: Signal `tim2_ch1` selected as request input
19: tim2_ch2: Signal `tim2_ch2` selected as request input
20: tim2_ch3: Signal `tim2_ch3` selected as request input
21: tim2_ch4: Signal `tim2_ch4` selected as request input
22: tim2_up: Signal `tim2_up` selected as request input
23: tim3_ch1: Signal `tim3_ch1` selected as request input
24: tim3_ch2: Signal `tim3_ch2` selected as request input
25: tim3_ch3: Signal `tim3_ch3` selected as request input
26: tim3_ch4: Signal `tim3_ch4` selected as request input
27: tim3_up: Signal `tim3_up` selected as request input
28: tim3_trig: Signal `tim3_trig` selected as request input
29: tim4_ch1: Signal `tim4_ch1` selected as request input
30: tim4_ch2: Signal `tim4_ch2` selected as request input
31: tim4_ch3: Signal `tim4_ch3` selected as request input
32: tim4_up: Signal `tim4_up` selected as request input
33: i2c1_rx_dma: Signal `i2c1_rx_dma` selected as request input
34: i2c1_tx_dma: Signal `i2c1_tx_dma` selected as request input
35: i2c2_rx_dma: Signal `i2c2_rx_dma` selected as request input
36: i2c2_tx_dma: Signal `i2c2_tx_dma` selected as request input
37: spi1_rx_dma: Signal `spi1_rx_dma` selected as request input
38: spi1_tx_dma: Signal `spi1_tx_dma` selected as request input
39: spi2_rx_dma: Signal `spi2_rx_dma` selected as request input
40: spi2_tx_dma: Signal `spi2_tx_dma` selected as request input
41: usart1_rx_dma: Signal `usart1_rx_dma` selected as request input
42: usart1_tx_dma: Signal `usart1_tx_dma` selected as request input
43: usart2_rx_dma: Signal `usart2_rx_dma` selected as request input
44: usart2_tx_dma: Signal `usart2_tx_dma` selected as request input
45: usart3_rx_dma: Signal `usart3_rx_dma` selected as request input
46: usart3_tx_dma: Signal `usart3_tx_dma` selected as request input
47: tim8_ch1: Signal `tim8_ch1` selected as request input
48: tim8_ch2: Signal `tim8_ch2` selected as request input
49: tim8_ch3: Signal `tim8_ch3` selected as request input
50: tim8_ch4: Signal `tim8_ch4` selected as request input
51: tim8_up: Signal `tim8_up` selected as request input
52: tim8_trig: Signal `tim8_trig` selected as request input
53: tim8_com: Signal `tim8_com` selected as request input
55: tim5_ch1: Signal `tim5_ch1` selected as request input
56: tim5_ch2: Signal `tim5_ch2` selected as request input
57: tim5_ch3: Signal `tim5_ch3` selected as request input
58: tim5_ch4: Signal `tim5_ch4` selected as request input
59: tim5_up: Signal `tim5_up` selected as request input
60: tim5_trig: Signal `tim5_trig` selected as request input
61: spi3_rx_dma: Signal `spi3_rx_dma` selected as request input
62: spi3_tx_dma: Signal `spi3_tx_dma` selected as request input
63: uart4_rx_dma: Signal `uart4_rx_dma` selected as request input
64: uart4_tx_dma: Signal `uart4_tx_dma` selected as request input
65: uart5_rx_dma: Signal `uart5_rx_dma` selected as request input
66: uart5_tx_dma: Signal `uart5_tx_dma` selected as request input
67: dac_ch1_dma: Signal `dac_ch1_dma` selected as request input
68: dac_ch2_dma: Signal `dac_ch2_dma` selected as request input
69: tim6_up: Signal `tim6_up` selected as request input
70: tim7_up: Signal `tim7_up` selected as request input
71: usart6_rx_dma: Signal `usart6_rx_dma` selected as request input
72: usart6_tx_dma: Signal `usart6_tx_dma` selected as request input
73: i2c3_rx_dma: Signal `i2c3_rx_dma` selected as request input
74: i2c3_tx_dma: Signal `i2c3_tx_dma` selected as request input
75: dcmi_dma: Signal `dcmi_dma` selected as request input
76: cryp_in_dma: Signal `cryp_in_dma` selected as request input
77: cryp_out_dma: Signal `cryp_out_dma` selected as request input
78: hash_in_dma: Signal `hash_in_dma` selected as request input
79: uart7_rx_dma: Signal `uart7_rx_dma` selected as request input
80: uart7_tx_dma: Signal `uart7_tx_dma` selected as request input
81: uart8_rx_dma: Signal `uart8_rx_dma` selected as request input
82: uart8_tx_dma: Signal `uart8_tx_dma` selected as request input
83: spi4_rx_dma: Signal `spi4_rx_dma` selected as request input
84: spi4_tx_dma: Signal `spi4_tx_dma` selected as request input
85: spi5_rx_dma: Signal `spi5_rx_dma` selected as request input
86: spi5_tx_dma: Signal `spi5_tx_dma` selected as request input
87: sai1a_dma: Signal `sai1a_dma` selected as request input
88: sai1b_dma: Signal `sai1b_dma` selected as request input
89: sai2a_dma: Signal `sai2a_dma` selected as request input
90: sai2b_dma: Signal `sai2b_dma` selected as request input
91: swpmi_rx_dma: Signal `swpmi_rx_dma` selected as request input
92: swpmi_tx_dma: Signal `swpmi_tx_dma` selected as request input
93: spdifrx_dat_dma: Signal `spdifrx_dat_dma` selected as request input
94: spdifrx_ctrl_dma: Signal `spdifrx_ctrl_dma` selected as request input
95: hr_req1: Signal `hr_req(1)` selected as request input
96: hr_req2: Signal `hr_req(2)` selected as request input
97: hr_req3: Signal `hr_req(3)` selected as request input
98: hr_req4: Signal `hr_req(4)` selected as request input
99: hr_req5: Signal `hr_req(5)` selected as request input
100: hr_req6: Signal `hr_req(6)` selected as request input
101: dfsdm1_dma0: Signal `dfsdm1_dma0` selected as request input
102: dfsdm1_dma1: Signal `dfsdm1_dma1` selected as request input
103: dfsdm1_dma2: Signal `dfsdm1_dma2` selected as request input
104: dfsdm1_dma3: Signal `dfsdm1_dma3` selected as request input
105: tim15_ch1: Signal `tim15_ch1` selected as request input
106: tim15_up: Signal `tim15_up` selected as request input
107: tim15_trig: Signal `tim15_trig` selected as request input
108: tim15_com: Signal `tim15_com` selected as request input
109: tim16_ch1: Signal `tim16_ch1` selected as request input
110: tim16_up: Signal `tim16_up` selected as request input
111: tim17_ch1: Signal `tim17_ch1` selected as request input
112: tim17_up: Signal `tim17_up` selected as request input
113: sai3_a_dma: Signal `sai3_a_dma` selected as request input
114: sai3_b_dma: Signal `sai3_b_dma` selected as request input
115: adc3_dma: Signal `adc3_dma` selected as request input

SOIE

Bit 8: Interrupt enable at synchronization event overrun.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable/disable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronous operating mode enable/disable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization event type selector Defines the synchronization event on the selected synchronization input:.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset..

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization input selected.

Allowed values:
0: dmamux1_evt0: Signal `dmamux1_evt0` selected as synchronization input
1: dmamux1_evt1: Signal `dmamux1_evt1` selected as synchronization input
2: dmamux1_evt2: Signal `dmamux1_evt2` selected as synchronization input
3: lptim1_out: Signal `lptim1_out` selected as synchronization input
4: lptim2_out: Signal `lptim2_out` selected as synchronization input
5: lptim3_out: Signal `lptim3_out` selected as synchronization input
6: extit0: Signal `extit0` selected as synchronization input
7: tim12_trgo: Signal `tim12_trgo` selected as synchronization input

C[4]CR

DMAMux - DMA request line multiplexer channel x control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-7: Input DMA request line selected.

Allowed values:
0: none: No signal selected as request input
1: dmamux1_req_gen0: Signal `dmamux1_req_gen0` selected as request input
2: dmamux1_req_gen1: Signal `dmamux1_req_gen1` selected as request input
3: dmamux1_req_gen2: Signal `dmamux1_req_gen2` selected as request input
4: dmamux1_req_gen3: Signal `dmamux1_req_gen3` selected as request input
5: dmamux1_req_gen4: Signal `dmamux1_req_gen4` selected as request input
6: dmamux1_req_gen5: Signal `dmamux1_req_gen5` selected as request input
7: dmamux1_req_gen6: Signal `dmamux1_req_gen6` selected as request input
8: dmamux1_req_gen7: Signal `dmamux1_req_gen7` selected as request input
9: adc1_dma: Signal `adc1_dma` selected as request input
10: adc2_dma: Signal `adc2_dma` selected as request input
11: tim1_ch1: Signal `tim1_ch1` selected as request input
12: tim1_ch2: Signal `tim1_ch2` selected as request input
13: tim1_ch3: Signal `tim1_ch3` selected as request input
14: tim1_ch4: Signal `tim1_ch4` selected as request input
15: tim1_up: Signal `tim1_up` selected as request input
16: tim1_trig: Signal `tim1_trig` selected as request input
17: tim1_com: Signal `tim1_com` selected as request input
18: tim2_ch1: Signal `tim2_ch1` selected as request input
19: tim2_ch2: Signal `tim2_ch2` selected as request input
20: tim2_ch3: Signal `tim2_ch3` selected as request input
21: tim2_ch4: Signal `tim2_ch4` selected as request input
22: tim2_up: Signal `tim2_up` selected as request input
23: tim3_ch1: Signal `tim3_ch1` selected as request input
24: tim3_ch2: Signal `tim3_ch2` selected as request input
25: tim3_ch3: Signal `tim3_ch3` selected as request input
26: tim3_ch4: Signal `tim3_ch4` selected as request input
27: tim3_up: Signal `tim3_up` selected as request input
28: tim3_trig: Signal `tim3_trig` selected as request input
29: tim4_ch1: Signal `tim4_ch1` selected as request input
30: tim4_ch2: Signal `tim4_ch2` selected as request input
31: tim4_ch3: Signal `tim4_ch3` selected as request input
32: tim4_up: Signal `tim4_up` selected as request input
33: i2c1_rx_dma: Signal `i2c1_rx_dma` selected as request input
34: i2c1_tx_dma: Signal `i2c1_tx_dma` selected as request input
35: i2c2_rx_dma: Signal `i2c2_rx_dma` selected as request input
36: i2c2_tx_dma: Signal `i2c2_tx_dma` selected as request input
37: spi1_rx_dma: Signal `spi1_rx_dma` selected as request input
38: spi1_tx_dma: Signal `spi1_tx_dma` selected as request input
39: spi2_rx_dma: Signal `spi2_rx_dma` selected as request input
40: spi2_tx_dma: Signal `spi2_tx_dma` selected as request input
41: usart1_rx_dma: Signal `usart1_rx_dma` selected as request input
42: usart1_tx_dma: Signal `usart1_tx_dma` selected as request input
43: usart2_rx_dma: Signal `usart2_rx_dma` selected as request input
44: usart2_tx_dma: Signal `usart2_tx_dma` selected as request input
45: usart3_rx_dma: Signal `usart3_rx_dma` selected as request input
46: usart3_tx_dma: Signal `usart3_tx_dma` selected as request input
47: tim8_ch1: Signal `tim8_ch1` selected as request input
48: tim8_ch2: Signal `tim8_ch2` selected as request input
49: tim8_ch3: Signal `tim8_ch3` selected as request input
50: tim8_ch4: Signal `tim8_ch4` selected as request input
51: tim8_up: Signal `tim8_up` selected as request input
52: tim8_trig: Signal `tim8_trig` selected as request input
53: tim8_com: Signal `tim8_com` selected as request input
55: tim5_ch1: Signal `tim5_ch1` selected as request input
56: tim5_ch2: Signal `tim5_ch2` selected as request input
57: tim5_ch3: Signal `tim5_ch3` selected as request input
58: tim5_ch4: Signal `tim5_ch4` selected as request input
59: tim5_up: Signal `tim5_up` selected as request input
60: tim5_trig: Signal `tim5_trig` selected as request input
61: spi3_rx_dma: Signal `spi3_rx_dma` selected as request input
62: spi3_tx_dma: Signal `spi3_tx_dma` selected as request input
63: uart4_rx_dma: Signal `uart4_rx_dma` selected as request input
64: uart4_tx_dma: Signal `uart4_tx_dma` selected as request input
65: uart5_rx_dma: Signal `uart5_rx_dma` selected as request input
66: uart5_tx_dma: Signal `uart5_tx_dma` selected as request input
67: dac_ch1_dma: Signal `dac_ch1_dma` selected as request input
68: dac_ch2_dma: Signal `dac_ch2_dma` selected as request input
69: tim6_up: Signal `tim6_up` selected as request input
70: tim7_up: Signal `tim7_up` selected as request input
71: usart6_rx_dma: Signal `usart6_rx_dma` selected as request input
72: usart6_tx_dma: Signal `usart6_tx_dma` selected as request input
73: i2c3_rx_dma: Signal `i2c3_rx_dma` selected as request input
74: i2c3_tx_dma: Signal `i2c3_tx_dma` selected as request input
75: dcmi_dma: Signal `dcmi_dma` selected as request input
76: cryp_in_dma: Signal `cryp_in_dma` selected as request input
77: cryp_out_dma: Signal `cryp_out_dma` selected as request input
78: hash_in_dma: Signal `hash_in_dma` selected as request input
79: uart7_rx_dma: Signal `uart7_rx_dma` selected as request input
80: uart7_tx_dma: Signal `uart7_tx_dma` selected as request input
81: uart8_rx_dma: Signal `uart8_rx_dma` selected as request input
82: uart8_tx_dma: Signal `uart8_tx_dma` selected as request input
83: spi4_rx_dma: Signal `spi4_rx_dma` selected as request input
84: spi4_tx_dma: Signal `spi4_tx_dma` selected as request input
85: spi5_rx_dma: Signal `spi5_rx_dma` selected as request input
86: spi5_tx_dma: Signal `spi5_tx_dma` selected as request input
87: sai1a_dma: Signal `sai1a_dma` selected as request input
88: sai1b_dma: Signal `sai1b_dma` selected as request input
89: sai2a_dma: Signal `sai2a_dma` selected as request input
90: sai2b_dma: Signal `sai2b_dma` selected as request input
91: swpmi_rx_dma: Signal `swpmi_rx_dma` selected as request input
92: swpmi_tx_dma: Signal `swpmi_tx_dma` selected as request input
93: spdifrx_dat_dma: Signal `spdifrx_dat_dma` selected as request input
94: spdifrx_ctrl_dma: Signal `spdifrx_ctrl_dma` selected as request input
95: hr_req1: Signal `hr_req(1)` selected as request input
96: hr_req2: Signal `hr_req(2)` selected as request input
97: hr_req3: Signal `hr_req(3)` selected as request input
98: hr_req4: Signal `hr_req(4)` selected as request input
99: hr_req5: Signal `hr_req(5)` selected as request input
100: hr_req6: Signal `hr_req(6)` selected as request input
101: dfsdm1_dma0: Signal `dfsdm1_dma0` selected as request input
102: dfsdm1_dma1: Signal `dfsdm1_dma1` selected as request input
103: dfsdm1_dma2: Signal `dfsdm1_dma2` selected as request input
104: dfsdm1_dma3: Signal `dfsdm1_dma3` selected as request input
105: tim15_ch1: Signal `tim15_ch1` selected as request input
106: tim15_up: Signal `tim15_up` selected as request input
107: tim15_trig: Signal `tim15_trig` selected as request input
108: tim15_com: Signal `tim15_com` selected as request input
109: tim16_ch1: Signal `tim16_ch1` selected as request input
110: tim16_up: Signal `tim16_up` selected as request input
111: tim17_ch1: Signal `tim17_ch1` selected as request input
112: tim17_up: Signal `tim17_up` selected as request input
113: sai3_a_dma: Signal `sai3_a_dma` selected as request input
114: sai3_b_dma: Signal `sai3_b_dma` selected as request input
115: adc3_dma: Signal `adc3_dma` selected as request input

SOIE

Bit 8: Interrupt enable at synchronization event overrun.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable/disable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronous operating mode enable/disable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization event type selector Defines the synchronization event on the selected synchronization input:.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset..

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization input selected.

Allowed values:
0: dmamux1_evt0: Signal `dmamux1_evt0` selected as synchronization input
1: dmamux1_evt1: Signal `dmamux1_evt1` selected as synchronization input
2: dmamux1_evt2: Signal `dmamux1_evt2` selected as synchronization input
3: lptim1_out: Signal `lptim1_out` selected as synchronization input
4: lptim2_out: Signal `lptim2_out` selected as synchronization input
5: lptim3_out: Signal `lptim3_out` selected as synchronization input
6: extit0: Signal `extit0` selected as synchronization input
7: tim12_trgo: Signal `tim12_trgo` selected as synchronization input

C[5]CR

DMAMux - DMA request line multiplexer channel x control register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-7: Input DMA request line selected.

Allowed values:
0: none: No signal selected as request input
1: dmamux1_req_gen0: Signal `dmamux1_req_gen0` selected as request input
2: dmamux1_req_gen1: Signal `dmamux1_req_gen1` selected as request input
3: dmamux1_req_gen2: Signal `dmamux1_req_gen2` selected as request input
4: dmamux1_req_gen3: Signal `dmamux1_req_gen3` selected as request input
5: dmamux1_req_gen4: Signal `dmamux1_req_gen4` selected as request input
6: dmamux1_req_gen5: Signal `dmamux1_req_gen5` selected as request input
7: dmamux1_req_gen6: Signal `dmamux1_req_gen6` selected as request input
8: dmamux1_req_gen7: Signal `dmamux1_req_gen7` selected as request input
9: adc1_dma: Signal `adc1_dma` selected as request input
10: adc2_dma: Signal `adc2_dma` selected as request input
11: tim1_ch1: Signal `tim1_ch1` selected as request input
12: tim1_ch2: Signal `tim1_ch2` selected as request input
13: tim1_ch3: Signal `tim1_ch3` selected as request input
14: tim1_ch4: Signal `tim1_ch4` selected as request input
15: tim1_up: Signal `tim1_up` selected as request input
16: tim1_trig: Signal `tim1_trig` selected as request input
17: tim1_com: Signal `tim1_com` selected as request input
18: tim2_ch1: Signal `tim2_ch1` selected as request input
19: tim2_ch2: Signal `tim2_ch2` selected as request input
20: tim2_ch3: Signal `tim2_ch3` selected as request input
21: tim2_ch4: Signal `tim2_ch4` selected as request input
22: tim2_up: Signal `tim2_up` selected as request input
23: tim3_ch1: Signal `tim3_ch1` selected as request input
24: tim3_ch2: Signal `tim3_ch2` selected as request input
25: tim3_ch3: Signal `tim3_ch3` selected as request input
26: tim3_ch4: Signal `tim3_ch4` selected as request input
27: tim3_up: Signal `tim3_up` selected as request input
28: tim3_trig: Signal `tim3_trig` selected as request input
29: tim4_ch1: Signal `tim4_ch1` selected as request input
30: tim4_ch2: Signal `tim4_ch2` selected as request input
31: tim4_ch3: Signal `tim4_ch3` selected as request input
32: tim4_up: Signal `tim4_up` selected as request input
33: i2c1_rx_dma: Signal `i2c1_rx_dma` selected as request input
34: i2c1_tx_dma: Signal `i2c1_tx_dma` selected as request input
35: i2c2_rx_dma: Signal `i2c2_rx_dma` selected as request input
36: i2c2_tx_dma: Signal `i2c2_tx_dma` selected as request input
37: spi1_rx_dma: Signal `spi1_rx_dma` selected as request input
38: spi1_tx_dma: Signal `spi1_tx_dma` selected as request input
39: spi2_rx_dma: Signal `spi2_rx_dma` selected as request input
40: spi2_tx_dma: Signal `spi2_tx_dma` selected as request input
41: usart1_rx_dma: Signal `usart1_rx_dma` selected as request input
42: usart1_tx_dma: Signal `usart1_tx_dma` selected as request input
43: usart2_rx_dma: Signal `usart2_rx_dma` selected as request input
44: usart2_tx_dma: Signal `usart2_tx_dma` selected as request input
45: usart3_rx_dma: Signal `usart3_rx_dma` selected as request input
46: usart3_tx_dma: Signal `usart3_tx_dma` selected as request input
47: tim8_ch1: Signal `tim8_ch1` selected as request input
48: tim8_ch2: Signal `tim8_ch2` selected as request input
49: tim8_ch3: Signal `tim8_ch3` selected as request input
50: tim8_ch4: Signal `tim8_ch4` selected as request input
51: tim8_up: Signal `tim8_up` selected as request input
52: tim8_trig: Signal `tim8_trig` selected as request input
53: tim8_com: Signal `tim8_com` selected as request input
55: tim5_ch1: Signal `tim5_ch1` selected as request input
56: tim5_ch2: Signal `tim5_ch2` selected as request input
57: tim5_ch3: Signal `tim5_ch3` selected as request input
58: tim5_ch4: Signal `tim5_ch4` selected as request input
59: tim5_up: Signal `tim5_up` selected as request input
60: tim5_trig: Signal `tim5_trig` selected as request input
61: spi3_rx_dma: Signal `spi3_rx_dma` selected as request input
62: spi3_tx_dma: Signal `spi3_tx_dma` selected as request input
63: uart4_rx_dma: Signal `uart4_rx_dma` selected as request input
64: uart4_tx_dma: Signal `uart4_tx_dma` selected as request input
65: uart5_rx_dma: Signal `uart5_rx_dma` selected as request input
66: uart5_tx_dma: Signal `uart5_tx_dma` selected as request input
67: dac_ch1_dma: Signal `dac_ch1_dma` selected as request input
68: dac_ch2_dma: Signal `dac_ch2_dma` selected as request input
69: tim6_up: Signal `tim6_up` selected as request input
70: tim7_up: Signal `tim7_up` selected as request input
71: usart6_rx_dma: Signal `usart6_rx_dma` selected as request input
72: usart6_tx_dma: Signal `usart6_tx_dma` selected as request input
73: i2c3_rx_dma: Signal `i2c3_rx_dma` selected as request input
74: i2c3_tx_dma: Signal `i2c3_tx_dma` selected as request input
75: dcmi_dma: Signal `dcmi_dma` selected as request input
76: cryp_in_dma: Signal `cryp_in_dma` selected as request input
77: cryp_out_dma: Signal `cryp_out_dma` selected as request input
78: hash_in_dma: Signal `hash_in_dma` selected as request input
79: uart7_rx_dma: Signal `uart7_rx_dma` selected as request input
80: uart7_tx_dma: Signal `uart7_tx_dma` selected as request input
81: uart8_rx_dma: Signal `uart8_rx_dma` selected as request input
82: uart8_tx_dma: Signal `uart8_tx_dma` selected as request input
83: spi4_rx_dma: Signal `spi4_rx_dma` selected as request input
84: spi4_tx_dma: Signal `spi4_tx_dma` selected as request input
85: spi5_rx_dma: Signal `spi5_rx_dma` selected as request input
86: spi5_tx_dma: Signal `spi5_tx_dma` selected as request input
87: sai1a_dma: Signal `sai1a_dma` selected as request input
88: sai1b_dma: Signal `sai1b_dma` selected as request input
89: sai2a_dma: Signal `sai2a_dma` selected as request input
90: sai2b_dma: Signal `sai2b_dma` selected as request input
91: swpmi_rx_dma: Signal `swpmi_rx_dma` selected as request input
92: swpmi_tx_dma: Signal `swpmi_tx_dma` selected as request input
93: spdifrx_dat_dma: Signal `spdifrx_dat_dma` selected as request input
94: spdifrx_ctrl_dma: Signal `spdifrx_ctrl_dma` selected as request input
95: hr_req1: Signal `hr_req(1)` selected as request input
96: hr_req2: Signal `hr_req(2)` selected as request input
97: hr_req3: Signal `hr_req(3)` selected as request input
98: hr_req4: Signal `hr_req(4)` selected as request input
99: hr_req5: Signal `hr_req(5)` selected as request input
100: hr_req6: Signal `hr_req(6)` selected as request input
101: dfsdm1_dma0: Signal `dfsdm1_dma0` selected as request input
102: dfsdm1_dma1: Signal `dfsdm1_dma1` selected as request input
103: dfsdm1_dma2: Signal `dfsdm1_dma2` selected as request input
104: dfsdm1_dma3: Signal `dfsdm1_dma3` selected as request input
105: tim15_ch1: Signal `tim15_ch1` selected as request input
106: tim15_up: Signal `tim15_up` selected as request input
107: tim15_trig: Signal `tim15_trig` selected as request input
108: tim15_com: Signal `tim15_com` selected as request input
109: tim16_ch1: Signal `tim16_ch1` selected as request input
110: tim16_up: Signal `tim16_up` selected as request input
111: tim17_ch1: Signal `tim17_ch1` selected as request input
112: tim17_up: Signal `tim17_up` selected as request input
113: sai3_a_dma: Signal `sai3_a_dma` selected as request input
114: sai3_b_dma: Signal `sai3_b_dma` selected as request input
115: adc3_dma: Signal `adc3_dma` selected as request input

SOIE

Bit 8: Interrupt enable at synchronization event overrun.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable/disable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronous operating mode enable/disable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization event type selector Defines the synchronization event on the selected synchronization input:.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset..

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization input selected.

Allowed values:
0: dmamux1_evt0: Signal `dmamux1_evt0` selected as synchronization input
1: dmamux1_evt1: Signal `dmamux1_evt1` selected as synchronization input
2: dmamux1_evt2: Signal `dmamux1_evt2` selected as synchronization input
3: lptim1_out: Signal `lptim1_out` selected as synchronization input
4: lptim2_out: Signal `lptim2_out` selected as synchronization input
5: lptim3_out: Signal `lptim3_out` selected as synchronization input
6: extit0: Signal `extit0` selected as synchronization input
7: tim12_trgo: Signal `tim12_trgo` selected as synchronization input

C[6]CR

DMAMux - DMA request line multiplexer channel x control register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-7: Input DMA request line selected.

Allowed values:
0: none: No signal selected as request input
1: dmamux1_req_gen0: Signal `dmamux1_req_gen0` selected as request input
2: dmamux1_req_gen1: Signal `dmamux1_req_gen1` selected as request input
3: dmamux1_req_gen2: Signal `dmamux1_req_gen2` selected as request input
4: dmamux1_req_gen3: Signal `dmamux1_req_gen3` selected as request input
5: dmamux1_req_gen4: Signal `dmamux1_req_gen4` selected as request input
6: dmamux1_req_gen5: Signal `dmamux1_req_gen5` selected as request input
7: dmamux1_req_gen6: Signal `dmamux1_req_gen6` selected as request input
8: dmamux1_req_gen7: Signal `dmamux1_req_gen7` selected as request input
9: adc1_dma: Signal `adc1_dma` selected as request input
10: adc2_dma: Signal `adc2_dma` selected as request input
11: tim1_ch1: Signal `tim1_ch1` selected as request input
12: tim1_ch2: Signal `tim1_ch2` selected as request input
13: tim1_ch3: Signal `tim1_ch3` selected as request input
14: tim1_ch4: Signal `tim1_ch4` selected as request input
15: tim1_up: Signal `tim1_up` selected as request input
16: tim1_trig: Signal `tim1_trig` selected as request input
17: tim1_com: Signal `tim1_com` selected as request input
18: tim2_ch1: Signal `tim2_ch1` selected as request input
19: tim2_ch2: Signal `tim2_ch2` selected as request input
20: tim2_ch3: Signal `tim2_ch3` selected as request input
21: tim2_ch4: Signal `tim2_ch4` selected as request input
22: tim2_up: Signal `tim2_up` selected as request input
23: tim3_ch1: Signal `tim3_ch1` selected as request input
24: tim3_ch2: Signal `tim3_ch2` selected as request input
25: tim3_ch3: Signal `tim3_ch3` selected as request input
26: tim3_ch4: Signal `tim3_ch4` selected as request input
27: tim3_up: Signal `tim3_up` selected as request input
28: tim3_trig: Signal `tim3_trig` selected as request input
29: tim4_ch1: Signal `tim4_ch1` selected as request input
30: tim4_ch2: Signal `tim4_ch2` selected as request input
31: tim4_ch3: Signal `tim4_ch3` selected as request input
32: tim4_up: Signal `tim4_up` selected as request input
33: i2c1_rx_dma: Signal `i2c1_rx_dma` selected as request input
34: i2c1_tx_dma: Signal `i2c1_tx_dma` selected as request input
35: i2c2_rx_dma: Signal `i2c2_rx_dma` selected as request input
36: i2c2_tx_dma: Signal `i2c2_tx_dma` selected as request input
37: spi1_rx_dma: Signal `spi1_rx_dma` selected as request input
38: spi1_tx_dma: Signal `spi1_tx_dma` selected as request input
39: spi2_rx_dma: Signal `spi2_rx_dma` selected as request input
40: spi2_tx_dma: Signal `spi2_tx_dma` selected as request input
41: usart1_rx_dma: Signal `usart1_rx_dma` selected as request input
42: usart1_tx_dma: Signal `usart1_tx_dma` selected as request input
43: usart2_rx_dma: Signal `usart2_rx_dma` selected as request input
44: usart2_tx_dma: Signal `usart2_tx_dma` selected as request input
45: usart3_rx_dma: Signal `usart3_rx_dma` selected as request input
46: usart3_tx_dma: Signal `usart3_tx_dma` selected as request input
47: tim8_ch1: Signal `tim8_ch1` selected as request input
48: tim8_ch2: Signal `tim8_ch2` selected as request input
49: tim8_ch3: Signal `tim8_ch3` selected as request input
50: tim8_ch4: Signal `tim8_ch4` selected as request input
51: tim8_up: Signal `tim8_up` selected as request input
52: tim8_trig: Signal `tim8_trig` selected as request input
53: tim8_com: Signal `tim8_com` selected as request input
55: tim5_ch1: Signal `tim5_ch1` selected as request input
56: tim5_ch2: Signal `tim5_ch2` selected as request input
57: tim5_ch3: Signal `tim5_ch3` selected as request input
58: tim5_ch4: Signal `tim5_ch4` selected as request input
59: tim5_up: Signal `tim5_up` selected as request input
60: tim5_trig: Signal `tim5_trig` selected as request input
61: spi3_rx_dma: Signal `spi3_rx_dma` selected as request input
62: spi3_tx_dma: Signal `spi3_tx_dma` selected as request input
63: uart4_rx_dma: Signal `uart4_rx_dma` selected as request input
64: uart4_tx_dma: Signal `uart4_tx_dma` selected as request input
65: uart5_rx_dma: Signal `uart5_rx_dma` selected as request input
66: uart5_tx_dma: Signal `uart5_tx_dma` selected as request input
67: dac_ch1_dma: Signal `dac_ch1_dma` selected as request input
68: dac_ch2_dma: Signal `dac_ch2_dma` selected as request input
69: tim6_up: Signal `tim6_up` selected as request input
70: tim7_up: Signal `tim7_up` selected as request input
71: usart6_rx_dma: Signal `usart6_rx_dma` selected as request input
72: usart6_tx_dma: Signal `usart6_tx_dma` selected as request input
73: i2c3_rx_dma: Signal `i2c3_rx_dma` selected as request input
74: i2c3_tx_dma: Signal `i2c3_tx_dma` selected as request input
75: dcmi_dma: Signal `dcmi_dma` selected as request input
76: cryp_in_dma: Signal `cryp_in_dma` selected as request input
77: cryp_out_dma: Signal `cryp_out_dma` selected as request input
78: hash_in_dma: Signal `hash_in_dma` selected as request input
79: uart7_rx_dma: Signal `uart7_rx_dma` selected as request input
80: uart7_tx_dma: Signal `uart7_tx_dma` selected as request input
81: uart8_rx_dma: Signal `uart8_rx_dma` selected as request input
82: uart8_tx_dma: Signal `uart8_tx_dma` selected as request input
83: spi4_rx_dma: Signal `spi4_rx_dma` selected as request input
84: spi4_tx_dma: Signal `spi4_tx_dma` selected as request input
85: spi5_rx_dma: Signal `spi5_rx_dma` selected as request input
86: spi5_tx_dma: Signal `spi5_tx_dma` selected as request input
87: sai1a_dma: Signal `sai1a_dma` selected as request input
88: sai1b_dma: Signal `sai1b_dma` selected as request input
89: sai2a_dma: Signal `sai2a_dma` selected as request input
90: sai2b_dma: Signal `sai2b_dma` selected as request input
91: swpmi_rx_dma: Signal `swpmi_rx_dma` selected as request input
92: swpmi_tx_dma: Signal `swpmi_tx_dma` selected as request input
93: spdifrx_dat_dma: Signal `spdifrx_dat_dma` selected as request input
94: spdifrx_ctrl_dma: Signal `spdifrx_ctrl_dma` selected as request input
95: hr_req1: Signal `hr_req(1)` selected as request input
96: hr_req2: Signal `hr_req(2)` selected as request input
97: hr_req3: Signal `hr_req(3)` selected as request input
98: hr_req4: Signal `hr_req(4)` selected as request input
99: hr_req5: Signal `hr_req(5)` selected as request input
100: hr_req6: Signal `hr_req(6)` selected as request input
101: dfsdm1_dma0: Signal `dfsdm1_dma0` selected as request input
102: dfsdm1_dma1: Signal `dfsdm1_dma1` selected as request input
103: dfsdm1_dma2: Signal `dfsdm1_dma2` selected as request input
104: dfsdm1_dma3: Signal `dfsdm1_dma3` selected as request input
105: tim15_ch1: Signal `tim15_ch1` selected as request input
106: tim15_up: Signal `tim15_up` selected as request input
107: tim15_trig: Signal `tim15_trig` selected as request input
108: tim15_com: Signal `tim15_com` selected as request input
109: tim16_ch1: Signal `tim16_ch1` selected as request input
110: tim16_up: Signal `tim16_up` selected as request input
111: tim17_ch1: Signal `tim17_ch1` selected as request input
112: tim17_up: Signal `tim17_up` selected as request input
113: sai3_a_dma: Signal `sai3_a_dma` selected as request input
114: sai3_b_dma: Signal `sai3_b_dma` selected as request input
115: adc3_dma: Signal `adc3_dma` selected as request input

SOIE

Bit 8: Interrupt enable at synchronization event overrun.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable/disable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronous operating mode enable/disable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization event type selector Defines the synchronization event on the selected synchronization input:.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset..

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization input selected.

Allowed values:
0: dmamux1_evt0: Signal `dmamux1_evt0` selected as synchronization input
1: dmamux1_evt1: Signal `dmamux1_evt1` selected as synchronization input
2: dmamux1_evt2: Signal `dmamux1_evt2` selected as synchronization input
3: lptim1_out: Signal `lptim1_out` selected as synchronization input
4: lptim2_out: Signal `lptim2_out` selected as synchronization input
5: lptim3_out: Signal `lptim3_out` selected as synchronization input
6: extit0: Signal `extit0` selected as synchronization input
7: tim12_trgo: Signal `tim12_trgo` selected as synchronization input

C[7]CR

DMAMux - DMA request line multiplexer channel x control register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-7: Input DMA request line selected.

Allowed values:
0: none: No signal selected as request input
1: dmamux1_req_gen0: Signal `dmamux1_req_gen0` selected as request input
2: dmamux1_req_gen1: Signal `dmamux1_req_gen1` selected as request input
3: dmamux1_req_gen2: Signal `dmamux1_req_gen2` selected as request input
4: dmamux1_req_gen3: Signal `dmamux1_req_gen3` selected as request input
5: dmamux1_req_gen4: Signal `dmamux1_req_gen4` selected as request input
6: dmamux1_req_gen5: Signal `dmamux1_req_gen5` selected as request input
7: dmamux1_req_gen6: Signal `dmamux1_req_gen6` selected as request input
8: dmamux1_req_gen7: Signal `dmamux1_req_gen7` selected as request input
9: adc1_dma: Signal `adc1_dma` selected as request input
10: adc2_dma: Signal `adc2_dma` selected as request input
11: tim1_ch1: Signal `tim1_ch1` selected as request input
12: tim1_ch2: Signal `tim1_ch2` selected as request input
13: tim1_ch3: Signal `tim1_ch3` selected as request input
14: tim1_ch4: Signal `tim1_ch4` selected as request input
15: tim1_up: Signal `tim1_up` selected as request input
16: tim1_trig: Signal `tim1_trig` selected as request input
17: tim1_com: Signal `tim1_com` selected as request input
18: tim2_ch1: Signal `tim2_ch1` selected as request input
19: tim2_ch2: Signal `tim2_ch2` selected as request input
20: tim2_ch3: Signal `tim2_ch3` selected as request input
21: tim2_ch4: Signal `tim2_ch4` selected as request input
22: tim2_up: Signal `tim2_up` selected as request input
23: tim3_ch1: Signal `tim3_ch1` selected as request input
24: tim3_ch2: Signal `tim3_ch2` selected as request input
25: tim3_ch3: Signal `tim3_ch3` selected as request input
26: tim3_ch4: Signal `tim3_ch4` selected as request input
27: tim3_up: Signal `tim3_up` selected as request input
28: tim3_trig: Signal `tim3_trig` selected as request input
29: tim4_ch1: Signal `tim4_ch1` selected as request input
30: tim4_ch2: Signal `tim4_ch2` selected as request input
31: tim4_ch3: Signal `tim4_ch3` selected as request input
32: tim4_up: Signal `tim4_up` selected as request input
33: i2c1_rx_dma: Signal `i2c1_rx_dma` selected as request input
34: i2c1_tx_dma: Signal `i2c1_tx_dma` selected as request input
35: i2c2_rx_dma: Signal `i2c2_rx_dma` selected as request input
36: i2c2_tx_dma: Signal `i2c2_tx_dma` selected as request input
37: spi1_rx_dma: Signal `spi1_rx_dma` selected as request input
38: spi1_tx_dma: Signal `spi1_tx_dma` selected as request input
39: spi2_rx_dma: Signal `spi2_rx_dma` selected as request input
40: spi2_tx_dma: Signal `spi2_tx_dma` selected as request input
41: usart1_rx_dma: Signal `usart1_rx_dma` selected as request input
42: usart1_tx_dma: Signal `usart1_tx_dma` selected as request input
43: usart2_rx_dma: Signal `usart2_rx_dma` selected as request input
44: usart2_tx_dma: Signal `usart2_tx_dma` selected as request input
45: usart3_rx_dma: Signal `usart3_rx_dma` selected as request input
46: usart3_tx_dma: Signal `usart3_tx_dma` selected as request input
47: tim8_ch1: Signal `tim8_ch1` selected as request input
48: tim8_ch2: Signal `tim8_ch2` selected as request input
49: tim8_ch3: Signal `tim8_ch3` selected as request input
50: tim8_ch4: Signal `tim8_ch4` selected as request input
51: tim8_up: Signal `tim8_up` selected as request input
52: tim8_trig: Signal `tim8_trig` selected as request input
53: tim8_com: Signal `tim8_com` selected as request input
55: tim5_ch1: Signal `tim5_ch1` selected as request input
56: tim5_ch2: Signal `tim5_ch2` selected as request input
57: tim5_ch3: Signal `tim5_ch3` selected as request input
58: tim5_ch4: Signal `tim5_ch4` selected as request input
59: tim5_up: Signal `tim5_up` selected as request input
60: tim5_trig: Signal `tim5_trig` selected as request input
61: spi3_rx_dma: Signal `spi3_rx_dma` selected as request input
62: spi3_tx_dma: Signal `spi3_tx_dma` selected as request input
63: uart4_rx_dma: Signal `uart4_rx_dma` selected as request input
64: uart4_tx_dma: Signal `uart4_tx_dma` selected as request input
65: uart5_rx_dma: Signal `uart5_rx_dma` selected as request input
66: uart5_tx_dma: Signal `uart5_tx_dma` selected as request input
67: dac_ch1_dma: Signal `dac_ch1_dma` selected as request input
68: dac_ch2_dma: Signal `dac_ch2_dma` selected as request input
69: tim6_up: Signal `tim6_up` selected as request input
70: tim7_up: Signal `tim7_up` selected as request input
71: usart6_rx_dma: Signal `usart6_rx_dma` selected as request input
72: usart6_tx_dma: Signal `usart6_tx_dma` selected as request input
73: i2c3_rx_dma: Signal `i2c3_rx_dma` selected as request input
74: i2c3_tx_dma: Signal `i2c3_tx_dma` selected as request input
75: dcmi_dma: Signal `dcmi_dma` selected as request input
76: cryp_in_dma: Signal `cryp_in_dma` selected as request input
77: cryp_out_dma: Signal `cryp_out_dma` selected as request input
78: hash_in_dma: Signal `hash_in_dma` selected as request input
79: uart7_rx_dma: Signal `uart7_rx_dma` selected as request input
80: uart7_tx_dma: Signal `uart7_tx_dma` selected as request input
81: uart8_rx_dma: Signal `uart8_rx_dma` selected as request input
82: uart8_tx_dma: Signal `uart8_tx_dma` selected as request input
83: spi4_rx_dma: Signal `spi4_rx_dma` selected as request input
84: spi4_tx_dma: Signal `spi4_tx_dma` selected as request input
85: spi5_rx_dma: Signal `spi5_rx_dma` selected as request input
86: spi5_tx_dma: Signal `spi5_tx_dma` selected as request input
87: sai1a_dma: Signal `sai1a_dma` selected as request input
88: sai1b_dma: Signal `sai1b_dma` selected as request input
89: sai2a_dma: Signal `sai2a_dma` selected as request input
90: sai2b_dma: Signal `sai2b_dma` selected as request input
91: swpmi_rx_dma: Signal `swpmi_rx_dma` selected as request input
92: swpmi_tx_dma: Signal `swpmi_tx_dma` selected as request input
93: spdifrx_dat_dma: Signal `spdifrx_dat_dma` selected as request input
94: spdifrx_ctrl_dma: Signal `spdifrx_ctrl_dma` selected as request input
95: hr_req1: Signal `hr_req(1)` selected as request input
96: hr_req2: Signal `hr_req(2)` selected as request input
97: hr_req3: Signal `hr_req(3)` selected as request input
98: hr_req4: Signal `hr_req(4)` selected as request input
99: hr_req5: Signal `hr_req(5)` selected as request input
100: hr_req6: Signal `hr_req(6)` selected as request input
101: dfsdm1_dma0: Signal `dfsdm1_dma0` selected as request input
102: dfsdm1_dma1: Signal `dfsdm1_dma1` selected as request input
103: dfsdm1_dma2: Signal `dfsdm1_dma2` selected as request input
104: dfsdm1_dma3: Signal `dfsdm1_dma3` selected as request input
105: tim15_ch1: Signal `tim15_ch1` selected as request input
106: tim15_up: Signal `tim15_up` selected as request input
107: tim15_trig: Signal `tim15_trig` selected as request input
108: tim15_com: Signal `tim15_com` selected as request input
109: tim16_ch1: Signal `tim16_ch1` selected as request input
110: tim16_up: Signal `tim16_up` selected as request input
111: tim17_ch1: Signal `tim17_ch1` selected as request input
112: tim17_up: Signal `tim17_up` selected as request input
113: sai3_a_dma: Signal `sai3_a_dma` selected as request input
114: sai3_b_dma: Signal `sai3_b_dma` selected as request input
115: adc3_dma: Signal `adc3_dma` selected as request input

SOIE

Bit 8: Interrupt enable at synchronization event overrun.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable/disable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronous operating mode enable/disable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization event type selector Defines the synchronization event on the selected synchronization input:.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset..

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization input selected.

Allowed values:
0: dmamux1_evt0: Signal `dmamux1_evt0` selected as synchronization input
1: dmamux1_evt1: Signal `dmamux1_evt1` selected as synchronization input
2: dmamux1_evt2: Signal `dmamux1_evt2` selected as synchronization input
3: lptim1_out: Signal `lptim1_out` selected as synchronization input
4: lptim2_out: Signal `lptim2_out` selected as synchronization input
5: lptim3_out: Signal `lptim3_out` selected as synchronization input
6: extit0: Signal `extit0` selected as synchronization input
7: tim12_trgo: Signal `tim12_trgo` selected as synchronization input

C[8]CR

DMAMux - DMA request line multiplexer channel x control register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-7: Input DMA request line selected.

Allowed values:
0: none: No signal selected as request input
1: dmamux1_req_gen0: Signal `dmamux1_req_gen0` selected as request input
2: dmamux1_req_gen1: Signal `dmamux1_req_gen1` selected as request input
3: dmamux1_req_gen2: Signal `dmamux1_req_gen2` selected as request input
4: dmamux1_req_gen3: Signal `dmamux1_req_gen3` selected as request input
5: dmamux1_req_gen4: Signal `dmamux1_req_gen4` selected as request input
6: dmamux1_req_gen5: Signal `dmamux1_req_gen5` selected as request input
7: dmamux1_req_gen6: Signal `dmamux1_req_gen6` selected as request input
8: dmamux1_req_gen7: Signal `dmamux1_req_gen7` selected as request input
9: adc1_dma: Signal `adc1_dma` selected as request input
10: adc2_dma: Signal `adc2_dma` selected as request input
11: tim1_ch1: Signal `tim1_ch1` selected as request input
12: tim1_ch2: Signal `tim1_ch2` selected as request input
13: tim1_ch3: Signal `tim1_ch3` selected as request input
14: tim1_ch4: Signal `tim1_ch4` selected as request input
15: tim1_up: Signal `tim1_up` selected as request input
16: tim1_trig: Signal `tim1_trig` selected as request input
17: tim1_com: Signal `tim1_com` selected as request input
18: tim2_ch1: Signal `tim2_ch1` selected as request input
19: tim2_ch2: Signal `tim2_ch2` selected as request input
20: tim2_ch3: Signal `tim2_ch3` selected as request input
21: tim2_ch4: Signal `tim2_ch4` selected as request input
22: tim2_up: Signal `tim2_up` selected as request input
23: tim3_ch1: Signal `tim3_ch1` selected as request input
24: tim3_ch2: Signal `tim3_ch2` selected as request input
25: tim3_ch3: Signal `tim3_ch3` selected as request input
26: tim3_ch4: Signal `tim3_ch4` selected as request input
27: tim3_up: Signal `tim3_up` selected as request input
28: tim3_trig: Signal `tim3_trig` selected as request input
29: tim4_ch1: Signal `tim4_ch1` selected as request input
30: tim4_ch2: Signal `tim4_ch2` selected as request input
31: tim4_ch3: Signal `tim4_ch3` selected as request input
32: tim4_up: Signal `tim4_up` selected as request input
33: i2c1_rx_dma: Signal `i2c1_rx_dma` selected as request input
34: i2c1_tx_dma: Signal `i2c1_tx_dma` selected as request input
35: i2c2_rx_dma: Signal `i2c2_rx_dma` selected as request input
36: i2c2_tx_dma: Signal `i2c2_tx_dma` selected as request input
37: spi1_rx_dma: Signal `spi1_rx_dma` selected as request input
38: spi1_tx_dma: Signal `spi1_tx_dma` selected as request input
39: spi2_rx_dma: Signal `spi2_rx_dma` selected as request input
40: spi2_tx_dma: Signal `spi2_tx_dma` selected as request input
41: usart1_rx_dma: Signal `usart1_rx_dma` selected as request input
42: usart1_tx_dma: Signal `usart1_tx_dma` selected as request input
43: usart2_rx_dma: Signal `usart2_rx_dma` selected as request input
44: usart2_tx_dma: Signal `usart2_tx_dma` selected as request input
45: usart3_rx_dma: Signal `usart3_rx_dma` selected as request input
46: usart3_tx_dma: Signal `usart3_tx_dma` selected as request input
47: tim8_ch1: Signal `tim8_ch1` selected as request input
48: tim8_ch2: Signal `tim8_ch2` selected as request input
49: tim8_ch3: Signal `tim8_ch3` selected as request input
50: tim8_ch4: Signal `tim8_ch4` selected as request input
51: tim8_up: Signal `tim8_up` selected as request input
52: tim8_trig: Signal `tim8_trig` selected as request input
53: tim8_com: Signal `tim8_com` selected as request input
55: tim5_ch1: Signal `tim5_ch1` selected as request input
56: tim5_ch2: Signal `tim5_ch2` selected as request input
57: tim5_ch3: Signal `tim5_ch3` selected as request input
58: tim5_ch4: Signal `tim5_ch4` selected as request input
59: tim5_up: Signal `tim5_up` selected as request input
60: tim5_trig: Signal `tim5_trig` selected as request input
61: spi3_rx_dma: Signal `spi3_rx_dma` selected as request input
62: spi3_tx_dma: Signal `spi3_tx_dma` selected as request input
63: uart4_rx_dma: Signal `uart4_rx_dma` selected as request input
64: uart4_tx_dma: Signal `uart4_tx_dma` selected as request input
65: uart5_rx_dma: Signal `uart5_rx_dma` selected as request input
66: uart5_tx_dma: Signal `uart5_tx_dma` selected as request input
67: dac_ch1_dma: Signal `dac_ch1_dma` selected as request input
68: dac_ch2_dma: Signal `dac_ch2_dma` selected as request input
69: tim6_up: Signal `tim6_up` selected as request input
70: tim7_up: Signal `tim7_up` selected as request input
71: usart6_rx_dma: Signal `usart6_rx_dma` selected as request input
72: usart6_tx_dma: Signal `usart6_tx_dma` selected as request input
73: i2c3_rx_dma: Signal `i2c3_rx_dma` selected as request input
74: i2c3_tx_dma: Signal `i2c3_tx_dma` selected as request input
75: dcmi_dma: Signal `dcmi_dma` selected as request input
76: cryp_in_dma: Signal `cryp_in_dma` selected as request input
77: cryp_out_dma: Signal `cryp_out_dma` selected as request input
78: hash_in_dma: Signal `hash_in_dma` selected as request input
79: uart7_rx_dma: Signal `uart7_rx_dma` selected as request input
80: uart7_tx_dma: Signal `uart7_tx_dma` selected as request input
81: uart8_rx_dma: Signal `uart8_rx_dma` selected as request input
82: uart8_tx_dma: Signal `uart8_tx_dma` selected as request input
83: spi4_rx_dma: Signal `spi4_rx_dma` selected as request input
84: spi4_tx_dma: Signal `spi4_tx_dma` selected as request input
85: spi5_rx_dma: Signal `spi5_rx_dma` selected as request input
86: spi5_tx_dma: Signal `spi5_tx_dma` selected as request input
87: sai1a_dma: Signal `sai1a_dma` selected as request input
88: sai1b_dma: Signal `sai1b_dma` selected as request input
89: sai2a_dma: Signal `sai2a_dma` selected as request input
90: sai2b_dma: Signal `sai2b_dma` selected as request input
91: swpmi_rx_dma: Signal `swpmi_rx_dma` selected as request input
92: swpmi_tx_dma: Signal `swpmi_tx_dma` selected as request input
93: spdifrx_dat_dma: Signal `spdifrx_dat_dma` selected as request input
94: spdifrx_ctrl_dma: Signal `spdifrx_ctrl_dma` selected as request input
95: hr_req1: Signal `hr_req(1)` selected as request input
96: hr_req2: Signal `hr_req(2)` selected as request input
97: hr_req3: Signal `hr_req(3)` selected as request input
98: hr_req4: Signal `hr_req(4)` selected as request input
99: hr_req5: Signal `hr_req(5)` selected as request input
100: hr_req6: Signal `hr_req(6)` selected as request input
101: dfsdm1_dma0: Signal `dfsdm1_dma0` selected as request input
102: dfsdm1_dma1: Signal `dfsdm1_dma1` selected as request input
103: dfsdm1_dma2: Signal `dfsdm1_dma2` selected as request input
104: dfsdm1_dma3: Signal `dfsdm1_dma3` selected as request input
105: tim15_ch1: Signal `tim15_ch1` selected as request input
106: tim15_up: Signal `tim15_up` selected as request input
107: tim15_trig: Signal `tim15_trig` selected as request input
108: tim15_com: Signal `tim15_com` selected as request input
109: tim16_ch1: Signal `tim16_ch1` selected as request input
110: tim16_up: Signal `tim16_up` selected as request input
111: tim17_ch1: Signal `tim17_ch1` selected as request input
112: tim17_up: Signal `tim17_up` selected as request input
113: sai3_a_dma: Signal `sai3_a_dma` selected as request input
114: sai3_b_dma: Signal `sai3_b_dma` selected as request input
115: adc3_dma: Signal `adc3_dma` selected as request input

SOIE

Bit 8: Interrupt enable at synchronization event overrun.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable/disable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronous operating mode enable/disable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization event type selector Defines the synchronization event on the selected synchronization input:.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset..

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization input selected.

Allowed values:
0: dmamux1_evt0: Signal `dmamux1_evt0` selected as synchronization input
1: dmamux1_evt1: Signal `dmamux1_evt1` selected as synchronization input
2: dmamux1_evt2: Signal `dmamux1_evt2` selected as synchronization input
3: lptim1_out: Signal `lptim1_out` selected as synchronization input
4: lptim2_out: Signal `lptim2_out` selected as synchronization input
5: lptim3_out: Signal `lptim3_out` selected as synchronization input
6: extit0: Signal `extit0` selected as synchronization input
7: tim12_trgo: Signal `tim12_trgo` selected as synchronization input

C[9]CR

DMAMux - DMA request line multiplexer channel x control register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-7: Input DMA request line selected.

Allowed values:
0: none: No signal selected as request input
1: dmamux1_req_gen0: Signal `dmamux1_req_gen0` selected as request input
2: dmamux1_req_gen1: Signal `dmamux1_req_gen1` selected as request input
3: dmamux1_req_gen2: Signal `dmamux1_req_gen2` selected as request input
4: dmamux1_req_gen3: Signal `dmamux1_req_gen3` selected as request input
5: dmamux1_req_gen4: Signal `dmamux1_req_gen4` selected as request input
6: dmamux1_req_gen5: Signal `dmamux1_req_gen5` selected as request input
7: dmamux1_req_gen6: Signal `dmamux1_req_gen6` selected as request input
8: dmamux1_req_gen7: Signal `dmamux1_req_gen7` selected as request input
9: adc1_dma: Signal `adc1_dma` selected as request input
10: adc2_dma: Signal `adc2_dma` selected as request input
11: tim1_ch1: Signal `tim1_ch1` selected as request input
12: tim1_ch2: Signal `tim1_ch2` selected as request input
13: tim1_ch3: Signal `tim1_ch3` selected as request input
14: tim1_ch4: Signal `tim1_ch4` selected as request input
15: tim1_up: Signal `tim1_up` selected as request input
16: tim1_trig: Signal `tim1_trig` selected as request input
17: tim1_com: Signal `tim1_com` selected as request input
18: tim2_ch1: Signal `tim2_ch1` selected as request input
19: tim2_ch2: Signal `tim2_ch2` selected as request input
20: tim2_ch3: Signal `tim2_ch3` selected as request input
21: tim2_ch4: Signal `tim2_ch4` selected as request input
22: tim2_up: Signal `tim2_up` selected as request input
23: tim3_ch1: Signal `tim3_ch1` selected as request input
24: tim3_ch2: Signal `tim3_ch2` selected as request input
25: tim3_ch3: Signal `tim3_ch3` selected as request input
26: tim3_ch4: Signal `tim3_ch4` selected as request input
27: tim3_up: Signal `tim3_up` selected as request input
28: tim3_trig: Signal `tim3_trig` selected as request input
29: tim4_ch1: Signal `tim4_ch1` selected as request input
30: tim4_ch2: Signal `tim4_ch2` selected as request input
31: tim4_ch3: Signal `tim4_ch3` selected as request input
32: tim4_up: Signal `tim4_up` selected as request input
33: i2c1_rx_dma: Signal `i2c1_rx_dma` selected as request input
34: i2c1_tx_dma: Signal `i2c1_tx_dma` selected as request input
35: i2c2_rx_dma: Signal `i2c2_rx_dma` selected as request input
36: i2c2_tx_dma: Signal `i2c2_tx_dma` selected as request input
37: spi1_rx_dma: Signal `spi1_rx_dma` selected as request input
38: spi1_tx_dma: Signal `spi1_tx_dma` selected as request input
39: spi2_rx_dma: Signal `spi2_rx_dma` selected as request input
40: spi2_tx_dma: Signal `spi2_tx_dma` selected as request input
41: usart1_rx_dma: Signal `usart1_rx_dma` selected as request input
42: usart1_tx_dma: Signal `usart1_tx_dma` selected as request input
43: usart2_rx_dma: Signal `usart2_rx_dma` selected as request input
44: usart2_tx_dma: Signal `usart2_tx_dma` selected as request input
45: usart3_rx_dma: Signal `usart3_rx_dma` selected as request input
46: usart3_tx_dma: Signal `usart3_tx_dma` selected as request input
47: tim8_ch1: Signal `tim8_ch1` selected as request input
48: tim8_ch2: Signal `tim8_ch2` selected as request input
49: tim8_ch3: Signal `tim8_ch3` selected as request input
50: tim8_ch4: Signal `tim8_ch4` selected as request input
51: tim8_up: Signal `tim8_up` selected as request input
52: tim8_trig: Signal `tim8_trig` selected as request input
53: tim8_com: Signal `tim8_com` selected as request input
55: tim5_ch1: Signal `tim5_ch1` selected as request input
56: tim5_ch2: Signal `tim5_ch2` selected as request input
57: tim5_ch3: Signal `tim5_ch3` selected as request input
58: tim5_ch4: Signal `tim5_ch4` selected as request input
59: tim5_up: Signal `tim5_up` selected as request input
60: tim5_trig: Signal `tim5_trig` selected as request input
61: spi3_rx_dma: Signal `spi3_rx_dma` selected as request input
62: spi3_tx_dma: Signal `spi3_tx_dma` selected as request input
63: uart4_rx_dma: Signal `uart4_rx_dma` selected as request input
64: uart4_tx_dma: Signal `uart4_tx_dma` selected as request input
65: uart5_rx_dma: Signal `uart5_rx_dma` selected as request input
66: uart5_tx_dma: Signal `uart5_tx_dma` selected as request input
67: dac_ch1_dma: Signal `dac_ch1_dma` selected as request input
68: dac_ch2_dma: Signal `dac_ch2_dma` selected as request input
69: tim6_up: Signal `tim6_up` selected as request input
70: tim7_up: Signal `tim7_up` selected as request input
71: usart6_rx_dma: Signal `usart6_rx_dma` selected as request input
72: usart6_tx_dma: Signal `usart6_tx_dma` selected as request input
73: i2c3_rx_dma: Signal `i2c3_rx_dma` selected as request input
74: i2c3_tx_dma: Signal `i2c3_tx_dma` selected as request input
75: dcmi_dma: Signal `dcmi_dma` selected as request input
76: cryp_in_dma: Signal `cryp_in_dma` selected as request input
77: cryp_out_dma: Signal `cryp_out_dma` selected as request input
78: hash_in_dma: Signal `hash_in_dma` selected as request input
79: uart7_rx_dma: Signal `uart7_rx_dma` selected as request input
80: uart7_tx_dma: Signal `uart7_tx_dma` selected as request input
81: uart8_rx_dma: Signal `uart8_rx_dma` selected as request input
82: uart8_tx_dma: Signal `uart8_tx_dma` selected as request input
83: spi4_rx_dma: Signal `spi4_rx_dma` selected as request input
84: spi4_tx_dma: Signal `spi4_tx_dma` selected as request input
85: spi5_rx_dma: Signal `spi5_rx_dma` selected as request input
86: spi5_tx_dma: Signal `spi5_tx_dma` selected as request input
87: sai1a_dma: Signal `sai1a_dma` selected as request input
88: sai1b_dma: Signal `sai1b_dma` selected as request input
89: sai2a_dma: Signal `sai2a_dma` selected as request input
90: sai2b_dma: Signal `sai2b_dma` selected as request input
91: swpmi_rx_dma: Signal `swpmi_rx_dma` selected as request input
92: swpmi_tx_dma: Signal `swpmi_tx_dma` selected as request input
93: spdifrx_dat_dma: Signal `spdifrx_dat_dma` selected as request input
94: spdifrx_ctrl_dma: Signal `spdifrx_ctrl_dma` selected as request input
95: hr_req1: Signal `hr_req(1)` selected as request input
96: hr_req2: Signal `hr_req(2)` selected as request input
97: hr_req3: Signal `hr_req(3)` selected as request input
98: hr_req4: Signal `hr_req(4)` selected as request input
99: hr_req5: Signal `hr_req(5)` selected as request input
100: hr_req6: Signal `hr_req(6)` selected as request input
101: dfsdm1_dma0: Signal `dfsdm1_dma0` selected as request input
102: dfsdm1_dma1: Signal `dfsdm1_dma1` selected as request input
103: dfsdm1_dma2: Signal `dfsdm1_dma2` selected as request input
104: dfsdm1_dma3: Signal `dfsdm1_dma3` selected as request input
105: tim15_ch1: Signal `tim15_ch1` selected as request input
106: tim15_up: Signal `tim15_up` selected as request input
107: tim15_trig: Signal `tim15_trig` selected as request input
108: tim15_com: Signal `tim15_com` selected as request input
109: tim16_ch1: Signal `tim16_ch1` selected as request input
110: tim16_up: Signal `tim16_up` selected as request input
111: tim17_ch1: Signal `tim17_ch1` selected as request input
112: tim17_up: Signal `tim17_up` selected as request input
113: sai3_a_dma: Signal `sai3_a_dma` selected as request input
114: sai3_b_dma: Signal `sai3_b_dma` selected as request input
115: adc3_dma: Signal `adc3_dma` selected as request input

SOIE

Bit 8: Interrupt enable at synchronization event overrun.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable/disable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronous operating mode enable/disable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization event type selector Defines the synchronization event on the selected synchronization input:.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset..

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization input selected.

Allowed values:
0: dmamux1_evt0: Signal `dmamux1_evt0` selected as synchronization input
1: dmamux1_evt1: Signal `dmamux1_evt1` selected as synchronization input
2: dmamux1_evt2: Signal `dmamux1_evt2` selected as synchronization input
3: lptim1_out: Signal `lptim1_out` selected as synchronization input
4: lptim2_out: Signal `lptim2_out` selected as synchronization input
5: lptim3_out: Signal `lptim3_out` selected as synchronization input
6: extit0: Signal `extit0` selected as synchronization input
7: tim12_trgo: Signal `tim12_trgo` selected as synchronization input

C[10]CR

DMAMux - DMA request line multiplexer channel x control register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-7: Input DMA request line selected.

Allowed values:
0: none: No signal selected as request input
1: dmamux1_req_gen0: Signal `dmamux1_req_gen0` selected as request input
2: dmamux1_req_gen1: Signal `dmamux1_req_gen1` selected as request input
3: dmamux1_req_gen2: Signal `dmamux1_req_gen2` selected as request input
4: dmamux1_req_gen3: Signal `dmamux1_req_gen3` selected as request input
5: dmamux1_req_gen4: Signal `dmamux1_req_gen4` selected as request input
6: dmamux1_req_gen5: Signal `dmamux1_req_gen5` selected as request input
7: dmamux1_req_gen6: Signal `dmamux1_req_gen6` selected as request input
8: dmamux1_req_gen7: Signal `dmamux1_req_gen7` selected as request input
9: adc1_dma: Signal `adc1_dma` selected as request input
10: adc2_dma: Signal `adc2_dma` selected as request input
11: tim1_ch1: Signal `tim1_ch1` selected as request input
12: tim1_ch2: Signal `tim1_ch2` selected as request input
13: tim1_ch3: Signal `tim1_ch3` selected as request input
14: tim1_ch4: Signal `tim1_ch4` selected as request input
15: tim1_up: Signal `tim1_up` selected as request input
16: tim1_trig: Signal `tim1_trig` selected as request input
17: tim1_com: Signal `tim1_com` selected as request input
18: tim2_ch1: Signal `tim2_ch1` selected as request input
19: tim2_ch2: Signal `tim2_ch2` selected as request input
20: tim2_ch3: Signal `tim2_ch3` selected as request input
21: tim2_ch4: Signal `tim2_ch4` selected as request input
22: tim2_up: Signal `tim2_up` selected as request input
23: tim3_ch1: Signal `tim3_ch1` selected as request input
24: tim3_ch2: Signal `tim3_ch2` selected as request input
25: tim3_ch3: Signal `tim3_ch3` selected as request input
26: tim3_ch4: Signal `tim3_ch4` selected as request input
27: tim3_up: Signal `tim3_up` selected as request input
28: tim3_trig: Signal `tim3_trig` selected as request input
29: tim4_ch1: Signal `tim4_ch1` selected as request input
30: tim4_ch2: Signal `tim4_ch2` selected as request input
31: tim4_ch3: Signal `tim4_ch3` selected as request input
32: tim4_up: Signal `tim4_up` selected as request input
33: i2c1_rx_dma: Signal `i2c1_rx_dma` selected as request input
34: i2c1_tx_dma: Signal `i2c1_tx_dma` selected as request input
35: i2c2_rx_dma: Signal `i2c2_rx_dma` selected as request input
36: i2c2_tx_dma: Signal `i2c2_tx_dma` selected as request input
37: spi1_rx_dma: Signal `spi1_rx_dma` selected as request input
38: spi1_tx_dma: Signal `spi1_tx_dma` selected as request input
39: spi2_rx_dma: Signal `spi2_rx_dma` selected as request input
40: spi2_tx_dma: Signal `spi2_tx_dma` selected as request input
41: usart1_rx_dma: Signal `usart1_rx_dma` selected as request input
42: usart1_tx_dma: Signal `usart1_tx_dma` selected as request input
43: usart2_rx_dma: Signal `usart2_rx_dma` selected as request input
44: usart2_tx_dma: Signal `usart2_tx_dma` selected as request input
45: usart3_rx_dma: Signal `usart3_rx_dma` selected as request input
46: usart3_tx_dma: Signal `usart3_tx_dma` selected as request input
47: tim8_ch1: Signal `tim8_ch1` selected as request input
48: tim8_ch2: Signal `tim8_ch2` selected as request input
49: tim8_ch3: Signal `tim8_ch3` selected as request input
50: tim8_ch4: Signal `tim8_ch4` selected as request input
51: tim8_up: Signal `tim8_up` selected as request input
52: tim8_trig: Signal `tim8_trig` selected as request input
53: tim8_com: Signal `tim8_com` selected as request input
55: tim5_ch1: Signal `tim5_ch1` selected as request input
56: tim5_ch2: Signal `tim5_ch2` selected as request input
57: tim5_ch3: Signal `tim5_ch3` selected as request input
58: tim5_ch4: Signal `tim5_ch4` selected as request input
59: tim5_up: Signal `tim5_up` selected as request input
60: tim5_trig: Signal `tim5_trig` selected as request input
61: spi3_rx_dma: Signal `spi3_rx_dma` selected as request input
62: spi3_tx_dma: Signal `spi3_tx_dma` selected as request input
63: uart4_rx_dma: Signal `uart4_rx_dma` selected as request input
64: uart4_tx_dma: Signal `uart4_tx_dma` selected as request input
65: uart5_rx_dma: Signal `uart5_rx_dma` selected as request input
66: uart5_tx_dma: Signal `uart5_tx_dma` selected as request input
67: dac_ch1_dma: Signal `dac_ch1_dma` selected as request input
68: dac_ch2_dma: Signal `dac_ch2_dma` selected as request input
69: tim6_up: Signal `tim6_up` selected as request input
70: tim7_up: Signal `tim7_up` selected as request input
71: usart6_rx_dma: Signal `usart6_rx_dma` selected as request input
72: usart6_tx_dma: Signal `usart6_tx_dma` selected as request input
73: i2c3_rx_dma: Signal `i2c3_rx_dma` selected as request input
74: i2c3_tx_dma: Signal `i2c3_tx_dma` selected as request input
75: dcmi_dma: Signal `dcmi_dma` selected as request input
76: cryp_in_dma: Signal `cryp_in_dma` selected as request input
77: cryp_out_dma: Signal `cryp_out_dma` selected as request input
78: hash_in_dma: Signal `hash_in_dma` selected as request input
79: uart7_rx_dma: Signal `uart7_rx_dma` selected as request input
80: uart7_tx_dma: Signal `uart7_tx_dma` selected as request input
81: uart8_rx_dma: Signal `uart8_rx_dma` selected as request input
82: uart8_tx_dma: Signal `uart8_tx_dma` selected as request input
83: spi4_rx_dma: Signal `spi4_rx_dma` selected as request input
84: spi4_tx_dma: Signal `spi4_tx_dma` selected as request input
85: spi5_rx_dma: Signal `spi5_rx_dma` selected as request input
86: spi5_tx_dma: Signal `spi5_tx_dma` selected as request input
87: sai1a_dma: Signal `sai1a_dma` selected as request input
88: sai1b_dma: Signal `sai1b_dma` selected as request input
89: sai2a_dma: Signal `sai2a_dma` selected as request input
90: sai2b_dma: Signal `sai2b_dma` selected as request input
91: swpmi_rx_dma: Signal `swpmi_rx_dma` selected as request input
92: swpmi_tx_dma: Signal `swpmi_tx_dma` selected as request input
93: spdifrx_dat_dma: Signal `spdifrx_dat_dma` selected as request input
94: spdifrx_ctrl_dma: Signal `spdifrx_ctrl_dma` selected as request input
95: hr_req1: Signal `hr_req(1)` selected as request input
96: hr_req2: Signal `hr_req(2)` selected as request input
97: hr_req3: Signal `hr_req(3)` selected as request input
98: hr_req4: Signal `hr_req(4)` selected as request input
99: hr_req5: Signal `hr_req(5)` selected as request input
100: hr_req6: Signal `hr_req(6)` selected as request input
101: dfsdm1_dma0: Signal `dfsdm1_dma0` selected as request input
102: dfsdm1_dma1: Signal `dfsdm1_dma1` selected as request input
103: dfsdm1_dma2: Signal `dfsdm1_dma2` selected as request input
104: dfsdm1_dma3: Signal `dfsdm1_dma3` selected as request input
105: tim15_ch1: Signal `tim15_ch1` selected as request input
106: tim15_up: Signal `tim15_up` selected as request input
107: tim15_trig: Signal `tim15_trig` selected as request input
108: tim15_com: Signal `tim15_com` selected as request input
109: tim16_ch1: Signal `tim16_ch1` selected as request input
110: tim16_up: Signal `tim16_up` selected as request input
111: tim17_ch1: Signal `tim17_ch1` selected as request input
112: tim17_up: Signal `tim17_up` selected as request input
113: sai3_a_dma: Signal `sai3_a_dma` selected as request input
114: sai3_b_dma: Signal `sai3_b_dma` selected as request input
115: adc3_dma: Signal `adc3_dma` selected as request input

SOIE

Bit 8: Interrupt enable at synchronization event overrun.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable/disable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronous operating mode enable/disable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization event type selector Defines the synchronization event on the selected synchronization input:.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset..

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization input selected.

Allowed values:
0: dmamux1_evt0: Signal `dmamux1_evt0` selected as synchronization input
1: dmamux1_evt1: Signal `dmamux1_evt1` selected as synchronization input
2: dmamux1_evt2: Signal `dmamux1_evt2` selected as synchronization input
3: lptim1_out: Signal `lptim1_out` selected as synchronization input
4: lptim2_out: Signal `lptim2_out` selected as synchronization input
5: lptim3_out: Signal `lptim3_out` selected as synchronization input
6: extit0: Signal `extit0` selected as synchronization input
7: tim12_trgo: Signal `tim12_trgo` selected as synchronization input

C[11]CR

DMAMux - DMA request line multiplexer channel x control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-7: Input DMA request line selected.

Allowed values:
0: none: No signal selected as request input
1: dmamux1_req_gen0: Signal `dmamux1_req_gen0` selected as request input
2: dmamux1_req_gen1: Signal `dmamux1_req_gen1` selected as request input
3: dmamux1_req_gen2: Signal `dmamux1_req_gen2` selected as request input
4: dmamux1_req_gen3: Signal `dmamux1_req_gen3` selected as request input
5: dmamux1_req_gen4: Signal `dmamux1_req_gen4` selected as request input
6: dmamux1_req_gen5: Signal `dmamux1_req_gen5` selected as request input
7: dmamux1_req_gen6: Signal `dmamux1_req_gen6` selected as request input
8: dmamux1_req_gen7: Signal `dmamux1_req_gen7` selected as request input
9: adc1_dma: Signal `adc1_dma` selected as request input
10: adc2_dma: Signal `adc2_dma` selected as request input
11: tim1_ch1: Signal `tim1_ch1` selected as request input
12: tim1_ch2: Signal `tim1_ch2` selected as request input
13: tim1_ch3: Signal `tim1_ch3` selected as request input
14: tim1_ch4: Signal `tim1_ch4` selected as request input
15: tim1_up: Signal `tim1_up` selected as request input
16: tim1_trig: Signal `tim1_trig` selected as request input
17: tim1_com: Signal `tim1_com` selected as request input
18: tim2_ch1: Signal `tim2_ch1` selected as request input
19: tim2_ch2: Signal `tim2_ch2` selected as request input
20: tim2_ch3: Signal `tim2_ch3` selected as request input
21: tim2_ch4: Signal `tim2_ch4` selected as request input
22: tim2_up: Signal `tim2_up` selected as request input
23: tim3_ch1: Signal `tim3_ch1` selected as request input
24: tim3_ch2: Signal `tim3_ch2` selected as request input
25: tim3_ch3: Signal `tim3_ch3` selected as request input
26: tim3_ch4: Signal `tim3_ch4` selected as request input
27: tim3_up: Signal `tim3_up` selected as request input
28: tim3_trig: Signal `tim3_trig` selected as request input
29: tim4_ch1: Signal `tim4_ch1` selected as request input
30: tim4_ch2: Signal `tim4_ch2` selected as request input
31: tim4_ch3: Signal `tim4_ch3` selected as request input
32: tim4_up: Signal `tim4_up` selected as request input
33: i2c1_rx_dma: Signal `i2c1_rx_dma` selected as request input
34: i2c1_tx_dma: Signal `i2c1_tx_dma` selected as request input
35: i2c2_rx_dma: Signal `i2c2_rx_dma` selected as request input
36: i2c2_tx_dma: Signal `i2c2_tx_dma` selected as request input
37: spi1_rx_dma: Signal `spi1_rx_dma` selected as request input
38: spi1_tx_dma: Signal `spi1_tx_dma` selected as request input
39: spi2_rx_dma: Signal `spi2_rx_dma` selected as request input
40: spi2_tx_dma: Signal `spi2_tx_dma` selected as request input
41: usart1_rx_dma: Signal `usart1_rx_dma` selected as request input
42: usart1_tx_dma: Signal `usart1_tx_dma` selected as request input
43: usart2_rx_dma: Signal `usart2_rx_dma` selected as request input
44: usart2_tx_dma: Signal `usart2_tx_dma` selected as request input
45: usart3_rx_dma: Signal `usart3_rx_dma` selected as request input
46: usart3_tx_dma: Signal `usart3_tx_dma` selected as request input
47: tim8_ch1: Signal `tim8_ch1` selected as request input
48: tim8_ch2: Signal `tim8_ch2` selected as request input
49: tim8_ch3: Signal `tim8_ch3` selected as request input
50: tim8_ch4: Signal `tim8_ch4` selected as request input
51: tim8_up: Signal `tim8_up` selected as request input
52: tim8_trig: Signal `tim8_trig` selected as request input
53: tim8_com: Signal `tim8_com` selected as request input
55: tim5_ch1: Signal `tim5_ch1` selected as request input
56: tim5_ch2: Signal `tim5_ch2` selected as request input
57: tim5_ch3: Signal `tim5_ch3` selected as request input
58: tim5_ch4: Signal `tim5_ch4` selected as request input
59: tim5_up: Signal `tim5_up` selected as request input
60: tim5_trig: Signal `tim5_trig` selected as request input
61: spi3_rx_dma: Signal `spi3_rx_dma` selected as request input
62: spi3_tx_dma: Signal `spi3_tx_dma` selected as request input
63: uart4_rx_dma: Signal `uart4_rx_dma` selected as request input
64: uart4_tx_dma: Signal `uart4_tx_dma` selected as request input
65: uart5_rx_dma: Signal `uart5_rx_dma` selected as request input
66: uart5_tx_dma: Signal `uart5_tx_dma` selected as request input
67: dac_ch1_dma: Signal `dac_ch1_dma` selected as request input
68: dac_ch2_dma: Signal `dac_ch2_dma` selected as request input
69: tim6_up: Signal `tim6_up` selected as request input
70: tim7_up: Signal `tim7_up` selected as request input
71: usart6_rx_dma: Signal `usart6_rx_dma` selected as request input
72: usart6_tx_dma: Signal `usart6_tx_dma` selected as request input
73: i2c3_rx_dma: Signal `i2c3_rx_dma` selected as request input
74: i2c3_tx_dma: Signal `i2c3_tx_dma` selected as request input
75: dcmi_dma: Signal `dcmi_dma` selected as request input
76: cryp_in_dma: Signal `cryp_in_dma` selected as request input
77: cryp_out_dma: Signal `cryp_out_dma` selected as request input
78: hash_in_dma: Signal `hash_in_dma` selected as request input
79: uart7_rx_dma: Signal `uart7_rx_dma` selected as request input
80: uart7_tx_dma: Signal `uart7_tx_dma` selected as request input
81: uart8_rx_dma: Signal `uart8_rx_dma` selected as request input
82: uart8_tx_dma: Signal `uart8_tx_dma` selected as request input
83: spi4_rx_dma: Signal `spi4_rx_dma` selected as request input
84: spi4_tx_dma: Signal `spi4_tx_dma` selected as request input
85: spi5_rx_dma: Signal `spi5_rx_dma` selected as request input
86: spi5_tx_dma: Signal `spi5_tx_dma` selected as request input
87: sai1a_dma: Signal `sai1a_dma` selected as request input
88: sai1b_dma: Signal `sai1b_dma` selected as request input
89: sai2a_dma: Signal `sai2a_dma` selected as request input
90: sai2b_dma: Signal `sai2b_dma` selected as request input
91: swpmi_rx_dma: Signal `swpmi_rx_dma` selected as request input
92: swpmi_tx_dma: Signal `swpmi_tx_dma` selected as request input
93: spdifrx_dat_dma: Signal `spdifrx_dat_dma` selected as request input
94: spdifrx_ctrl_dma: Signal `spdifrx_ctrl_dma` selected as request input
95: hr_req1: Signal `hr_req(1)` selected as request input
96: hr_req2: Signal `hr_req(2)` selected as request input
97: hr_req3: Signal `hr_req(3)` selected as request input
98: hr_req4: Signal `hr_req(4)` selected as request input
99: hr_req5: Signal `hr_req(5)` selected as request input
100: hr_req6: Signal `hr_req(6)` selected as request input
101: dfsdm1_dma0: Signal `dfsdm1_dma0` selected as request input
102: dfsdm1_dma1: Signal `dfsdm1_dma1` selected as request input
103: dfsdm1_dma2: Signal `dfsdm1_dma2` selected as request input
104: dfsdm1_dma3: Signal `dfsdm1_dma3` selected as request input
105: tim15_ch1: Signal `tim15_ch1` selected as request input
106: tim15_up: Signal `tim15_up` selected as request input
107: tim15_trig: Signal `tim15_trig` selected as request input
108: tim15_com: Signal `tim15_com` selected as request input
109: tim16_ch1: Signal `tim16_ch1` selected as request input
110: tim16_up: Signal `tim16_up` selected as request input
111: tim17_ch1: Signal `tim17_ch1` selected as request input
112: tim17_up: Signal `tim17_up` selected as request input
113: sai3_a_dma: Signal `sai3_a_dma` selected as request input
114: sai3_b_dma: Signal `sai3_b_dma` selected as request input
115: adc3_dma: Signal `adc3_dma` selected as request input

SOIE

Bit 8: Interrupt enable at synchronization event overrun.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable/disable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronous operating mode enable/disable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization event type selector Defines the synchronization event on the selected synchronization input:.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset..

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization input selected.

Allowed values:
0: dmamux1_evt0: Signal `dmamux1_evt0` selected as synchronization input
1: dmamux1_evt1: Signal `dmamux1_evt1` selected as synchronization input
2: dmamux1_evt2: Signal `dmamux1_evt2` selected as synchronization input
3: lptim1_out: Signal `lptim1_out` selected as synchronization input
4: lptim2_out: Signal `lptim2_out` selected as synchronization input
5: lptim3_out: Signal `lptim3_out` selected as synchronization input
6: extit0: Signal `extit0` selected as synchronization input
7: tim12_trgo: Signal `tim12_trgo` selected as synchronization input

C[12]CR

DMAMux - DMA request line multiplexer channel x control register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-7: Input DMA request line selected.

Allowed values:
0: none: No signal selected as request input
1: dmamux1_req_gen0: Signal `dmamux1_req_gen0` selected as request input
2: dmamux1_req_gen1: Signal `dmamux1_req_gen1` selected as request input
3: dmamux1_req_gen2: Signal `dmamux1_req_gen2` selected as request input
4: dmamux1_req_gen3: Signal `dmamux1_req_gen3` selected as request input
5: dmamux1_req_gen4: Signal `dmamux1_req_gen4` selected as request input
6: dmamux1_req_gen5: Signal `dmamux1_req_gen5` selected as request input
7: dmamux1_req_gen6: Signal `dmamux1_req_gen6` selected as request input
8: dmamux1_req_gen7: Signal `dmamux1_req_gen7` selected as request input
9: adc1_dma: Signal `adc1_dma` selected as request input
10: adc2_dma: Signal `adc2_dma` selected as request input
11: tim1_ch1: Signal `tim1_ch1` selected as request input
12: tim1_ch2: Signal `tim1_ch2` selected as request input
13: tim1_ch3: Signal `tim1_ch3` selected as request input
14: tim1_ch4: Signal `tim1_ch4` selected as request input
15: tim1_up: Signal `tim1_up` selected as request input
16: tim1_trig: Signal `tim1_trig` selected as request input
17: tim1_com: Signal `tim1_com` selected as request input
18: tim2_ch1: Signal `tim2_ch1` selected as request input
19: tim2_ch2: Signal `tim2_ch2` selected as request input
20: tim2_ch3: Signal `tim2_ch3` selected as request input
21: tim2_ch4: Signal `tim2_ch4` selected as request input
22: tim2_up: Signal `tim2_up` selected as request input
23: tim3_ch1: Signal `tim3_ch1` selected as request input
24: tim3_ch2: Signal `tim3_ch2` selected as request input
25: tim3_ch3: Signal `tim3_ch3` selected as request input
26: tim3_ch4: Signal `tim3_ch4` selected as request input
27: tim3_up: Signal `tim3_up` selected as request input
28: tim3_trig: Signal `tim3_trig` selected as request input
29: tim4_ch1: Signal `tim4_ch1` selected as request input
30: tim4_ch2: Signal `tim4_ch2` selected as request input
31: tim4_ch3: Signal `tim4_ch3` selected as request input
32: tim4_up: Signal `tim4_up` selected as request input
33: i2c1_rx_dma: Signal `i2c1_rx_dma` selected as request input
34: i2c1_tx_dma: Signal `i2c1_tx_dma` selected as request input
35: i2c2_rx_dma: Signal `i2c2_rx_dma` selected as request input
36: i2c2_tx_dma: Signal `i2c2_tx_dma` selected as request input
37: spi1_rx_dma: Signal `spi1_rx_dma` selected as request input
38: spi1_tx_dma: Signal `spi1_tx_dma` selected as request input
39: spi2_rx_dma: Signal `spi2_rx_dma` selected as request input
40: spi2_tx_dma: Signal `spi2_tx_dma` selected as request input
41: usart1_rx_dma: Signal `usart1_rx_dma` selected as request input
42: usart1_tx_dma: Signal `usart1_tx_dma` selected as request input
43: usart2_rx_dma: Signal `usart2_rx_dma` selected as request input
44: usart2_tx_dma: Signal `usart2_tx_dma` selected as request input
45: usart3_rx_dma: Signal `usart3_rx_dma` selected as request input
46: usart3_tx_dma: Signal `usart3_tx_dma` selected as request input
47: tim8_ch1: Signal `tim8_ch1` selected as request input
48: tim8_ch2: Signal `tim8_ch2` selected as request input
49: tim8_ch3: Signal `tim8_ch3` selected as request input
50: tim8_ch4: Signal `tim8_ch4` selected as request input
51: tim8_up: Signal `tim8_up` selected as request input
52: tim8_trig: Signal `tim8_trig` selected as request input
53: tim8_com: Signal `tim8_com` selected as request input
55: tim5_ch1: Signal `tim5_ch1` selected as request input
56: tim5_ch2: Signal `tim5_ch2` selected as request input
57: tim5_ch3: Signal `tim5_ch3` selected as request input
58: tim5_ch4: Signal `tim5_ch4` selected as request input
59: tim5_up: Signal `tim5_up` selected as request input
60: tim5_trig: Signal `tim5_trig` selected as request input
61: spi3_rx_dma: Signal `spi3_rx_dma` selected as request input
62: spi3_tx_dma: Signal `spi3_tx_dma` selected as request input
63: uart4_rx_dma: Signal `uart4_rx_dma` selected as request input
64: uart4_tx_dma: Signal `uart4_tx_dma` selected as request input
65: uart5_rx_dma: Signal `uart5_rx_dma` selected as request input
66: uart5_tx_dma: Signal `uart5_tx_dma` selected as request input
67: dac_ch1_dma: Signal `dac_ch1_dma` selected as request input
68: dac_ch2_dma: Signal `dac_ch2_dma` selected as request input
69: tim6_up: Signal `tim6_up` selected as request input
70: tim7_up: Signal `tim7_up` selected as request input
71: usart6_rx_dma: Signal `usart6_rx_dma` selected as request input
72: usart6_tx_dma: Signal `usart6_tx_dma` selected as request input
73: i2c3_rx_dma: Signal `i2c3_rx_dma` selected as request input
74: i2c3_tx_dma: Signal `i2c3_tx_dma` selected as request input
75: dcmi_dma: Signal `dcmi_dma` selected as request input
76: cryp_in_dma: Signal `cryp_in_dma` selected as request input
77: cryp_out_dma: Signal `cryp_out_dma` selected as request input
78: hash_in_dma: Signal `hash_in_dma` selected as request input
79: uart7_rx_dma: Signal `uart7_rx_dma` selected as request input
80: uart7_tx_dma: Signal `uart7_tx_dma` selected as request input
81: uart8_rx_dma: Signal `uart8_rx_dma` selected as request input
82: uart8_tx_dma: Signal `uart8_tx_dma` selected as request input
83: spi4_rx_dma: Signal `spi4_rx_dma` selected as request input
84: spi4_tx_dma: Signal `spi4_tx_dma` selected as request input
85: spi5_rx_dma: Signal `spi5_rx_dma` selected as request input
86: spi5_tx_dma: Signal `spi5_tx_dma` selected as request input
87: sai1a_dma: Signal `sai1a_dma` selected as request input
88: sai1b_dma: Signal `sai1b_dma` selected as request input
89: sai2a_dma: Signal `sai2a_dma` selected as request input
90: sai2b_dma: Signal `sai2b_dma` selected as request input
91: swpmi_rx_dma: Signal `swpmi_rx_dma` selected as request input
92: swpmi_tx_dma: Signal `swpmi_tx_dma` selected as request input
93: spdifrx_dat_dma: Signal `spdifrx_dat_dma` selected as request input
94: spdifrx_ctrl_dma: Signal `spdifrx_ctrl_dma` selected as request input
95: hr_req1: Signal `hr_req(1)` selected as request input
96: hr_req2: Signal `hr_req(2)` selected as request input
97: hr_req3: Signal `hr_req(3)` selected as request input
98: hr_req4: Signal `hr_req(4)` selected as request input
99: hr_req5: Signal `hr_req(5)` selected as request input
100: hr_req6: Signal `hr_req(6)` selected as request input
101: dfsdm1_dma0: Signal `dfsdm1_dma0` selected as request input
102: dfsdm1_dma1: Signal `dfsdm1_dma1` selected as request input
103: dfsdm1_dma2: Signal `dfsdm1_dma2` selected as request input
104: dfsdm1_dma3: Signal `dfsdm1_dma3` selected as request input
105: tim15_ch1: Signal `tim15_ch1` selected as request input
106: tim15_up: Signal `tim15_up` selected as request input
107: tim15_trig: Signal `tim15_trig` selected as request input
108: tim15_com: Signal `tim15_com` selected as request input
109: tim16_ch1: Signal `tim16_ch1` selected as request input
110: tim16_up: Signal `tim16_up` selected as request input
111: tim17_ch1: Signal `tim17_ch1` selected as request input
112: tim17_up: Signal `tim17_up` selected as request input
113: sai3_a_dma: Signal `sai3_a_dma` selected as request input
114: sai3_b_dma: Signal `sai3_b_dma` selected as request input
115: adc3_dma: Signal `adc3_dma` selected as request input

SOIE

Bit 8: Interrupt enable at synchronization event overrun.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable/disable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronous operating mode enable/disable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization event type selector Defines the synchronization event on the selected synchronization input:.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset..

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization input selected.

Allowed values:
0: dmamux1_evt0: Signal `dmamux1_evt0` selected as synchronization input
1: dmamux1_evt1: Signal `dmamux1_evt1` selected as synchronization input
2: dmamux1_evt2: Signal `dmamux1_evt2` selected as synchronization input
3: lptim1_out: Signal `lptim1_out` selected as synchronization input
4: lptim2_out: Signal `lptim2_out` selected as synchronization input
5: lptim3_out: Signal `lptim3_out` selected as synchronization input
6: extit0: Signal `extit0` selected as synchronization input
7: tim12_trgo: Signal `tim12_trgo` selected as synchronization input

C[13]CR

DMAMux - DMA request line multiplexer channel x control register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-7: Input DMA request line selected.

Allowed values:
0: none: No signal selected as request input
1: dmamux1_req_gen0: Signal `dmamux1_req_gen0` selected as request input
2: dmamux1_req_gen1: Signal `dmamux1_req_gen1` selected as request input
3: dmamux1_req_gen2: Signal `dmamux1_req_gen2` selected as request input
4: dmamux1_req_gen3: Signal `dmamux1_req_gen3` selected as request input
5: dmamux1_req_gen4: Signal `dmamux1_req_gen4` selected as request input
6: dmamux1_req_gen5: Signal `dmamux1_req_gen5` selected as request input
7: dmamux1_req_gen6: Signal `dmamux1_req_gen6` selected as request input
8: dmamux1_req_gen7: Signal `dmamux1_req_gen7` selected as request input
9: adc1_dma: Signal `adc1_dma` selected as request input
10: adc2_dma: Signal `adc2_dma` selected as request input
11: tim1_ch1: Signal `tim1_ch1` selected as request input
12: tim1_ch2: Signal `tim1_ch2` selected as request input
13: tim1_ch3: Signal `tim1_ch3` selected as request input
14: tim1_ch4: Signal `tim1_ch4` selected as request input
15: tim1_up: Signal `tim1_up` selected as request input
16: tim1_trig: Signal `tim1_trig` selected as request input
17: tim1_com: Signal `tim1_com` selected as request input
18: tim2_ch1: Signal `tim2_ch1` selected as request input
19: tim2_ch2: Signal `tim2_ch2` selected as request input
20: tim2_ch3: Signal `tim2_ch3` selected as request input
21: tim2_ch4: Signal `tim2_ch4` selected as request input
22: tim2_up: Signal `tim2_up` selected as request input
23: tim3_ch1: Signal `tim3_ch1` selected as request input
24: tim3_ch2: Signal `tim3_ch2` selected as request input
25: tim3_ch3: Signal `tim3_ch3` selected as request input
26: tim3_ch4: Signal `tim3_ch4` selected as request input
27: tim3_up: Signal `tim3_up` selected as request input
28: tim3_trig: Signal `tim3_trig` selected as request input
29: tim4_ch1: Signal `tim4_ch1` selected as request input
30: tim4_ch2: Signal `tim4_ch2` selected as request input
31: tim4_ch3: Signal `tim4_ch3` selected as request input
32: tim4_up: Signal `tim4_up` selected as request input
33: i2c1_rx_dma: Signal `i2c1_rx_dma` selected as request input
34: i2c1_tx_dma: Signal `i2c1_tx_dma` selected as request input
35: i2c2_rx_dma: Signal `i2c2_rx_dma` selected as request input
36: i2c2_tx_dma: Signal `i2c2_tx_dma` selected as request input
37: spi1_rx_dma: Signal `spi1_rx_dma` selected as request input
38: spi1_tx_dma: Signal `spi1_tx_dma` selected as request input
39: spi2_rx_dma: Signal `spi2_rx_dma` selected as request input
40: spi2_tx_dma: Signal `spi2_tx_dma` selected as request input
41: usart1_rx_dma: Signal `usart1_rx_dma` selected as request input
42: usart1_tx_dma: Signal `usart1_tx_dma` selected as request input
43: usart2_rx_dma: Signal `usart2_rx_dma` selected as request input
44: usart2_tx_dma: Signal `usart2_tx_dma` selected as request input
45: usart3_rx_dma: Signal `usart3_rx_dma` selected as request input
46: usart3_tx_dma: Signal `usart3_tx_dma` selected as request input
47: tim8_ch1: Signal `tim8_ch1` selected as request input
48: tim8_ch2: Signal `tim8_ch2` selected as request input
49: tim8_ch3: Signal `tim8_ch3` selected as request input
50: tim8_ch4: Signal `tim8_ch4` selected as request input
51: tim8_up: Signal `tim8_up` selected as request input
52: tim8_trig: Signal `tim8_trig` selected as request input
53: tim8_com: Signal `tim8_com` selected as request input
55: tim5_ch1: Signal `tim5_ch1` selected as request input
56: tim5_ch2: Signal `tim5_ch2` selected as request input
57: tim5_ch3: Signal `tim5_ch3` selected as request input
58: tim5_ch4: Signal `tim5_ch4` selected as request input
59: tim5_up: Signal `tim5_up` selected as request input
60: tim5_trig: Signal `tim5_trig` selected as request input
61: spi3_rx_dma: Signal `spi3_rx_dma` selected as request input
62: spi3_tx_dma: Signal `spi3_tx_dma` selected as request input
63: uart4_rx_dma: Signal `uart4_rx_dma` selected as request input
64: uart4_tx_dma: Signal `uart4_tx_dma` selected as request input
65: uart5_rx_dma: Signal `uart5_rx_dma` selected as request input
66: uart5_tx_dma: Signal `uart5_tx_dma` selected as request input
67: dac_ch1_dma: Signal `dac_ch1_dma` selected as request input
68: dac_ch2_dma: Signal `dac_ch2_dma` selected as request input
69: tim6_up: Signal `tim6_up` selected as request input
70: tim7_up: Signal `tim7_up` selected as request input
71: usart6_rx_dma: Signal `usart6_rx_dma` selected as request input
72: usart6_tx_dma: Signal `usart6_tx_dma` selected as request input
73: i2c3_rx_dma: Signal `i2c3_rx_dma` selected as request input
74: i2c3_tx_dma: Signal `i2c3_tx_dma` selected as request input
75: dcmi_dma: Signal `dcmi_dma` selected as request input
76: cryp_in_dma: Signal `cryp_in_dma` selected as request input
77: cryp_out_dma: Signal `cryp_out_dma` selected as request input
78: hash_in_dma: Signal `hash_in_dma` selected as request input
79: uart7_rx_dma: Signal `uart7_rx_dma` selected as request input
80: uart7_tx_dma: Signal `uart7_tx_dma` selected as request input
81: uart8_rx_dma: Signal `uart8_rx_dma` selected as request input
82: uart8_tx_dma: Signal `uart8_tx_dma` selected as request input
83: spi4_rx_dma: Signal `spi4_rx_dma` selected as request input
84: spi4_tx_dma: Signal `spi4_tx_dma` selected as request input
85: spi5_rx_dma: Signal `spi5_rx_dma` selected as request input
86: spi5_tx_dma: Signal `spi5_tx_dma` selected as request input
87: sai1a_dma: Signal `sai1a_dma` selected as request input
88: sai1b_dma: Signal `sai1b_dma` selected as request input
89: sai2a_dma: Signal `sai2a_dma` selected as request input
90: sai2b_dma: Signal `sai2b_dma` selected as request input
91: swpmi_rx_dma: Signal `swpmi_rx_dma` selected as request input
92: swpmi_tx_dma: Signal `swpmi_tx_dma` selected as request input
93: spdifrx_dat_dma: Signal `spdifrx_dat_dma` selected as request input
94: spdifrx_ctrl_dma: Signal `spdifrx_ctrl_dma` selected as request input
95: hr_req1: Signal `hr_req(1)` selected as request input
96: hr_req2: Signal `hr_req(2)` selected as request input
97: hr_req3: Signal `hr_req(3)` selected as request input
98: hr_req4: Signal `hr_req(4)` selected as request input
99: hr_req5: Signal `hr_req(5)` selected as request input
100: hr_req6: Signal `hr_req(6)` selected as request input
101: dfsdm1_dma0: Signal `dfsdm1_dma0` selected as request input
102: dfsdm1_dma1: Signal `dfsdm1_dma1` selected as request input
103: dfsdm1_dma2: Signal `dfsdm1_dma2` selected as request input
104: dfsdm1_dma3: Signal `dfsdm1_dma3` selected as request input
105: tim15_ch1: Signal `tim15_ch1` selected as request input
106: tim15_up: Signal `tim15_up` selected as request input
107: tim15_trig: Signal `tim15_trig` selected as request input
108: tim15_com: Signal `tim15_com` selected as request input
109: tim16_ch1: Signal `tim16_ch1` selected as request input
110: tim16_up: Signal `tim16_up` selected as request input
111: tim17_ch1: Signal `tim17_ch1` selected as request input
112: tim17_up: Signal `tim17_up` selected as request input
113: sai3_a_dma: Signal `sai3_a_dma` selected as request input
114: sai3_b_dma: Signal `sai3_b_dma` selected as request input
115: adc3_dma: Signal `adc3_dma` selected as request input

SOIE

Bit 8: Interrupt enable at synchronization event overrun.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable/disable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronous operating mode enable/disable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization event type selector Defines the synchronization event on the selected synchronization input:.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset..

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization input selected.

Allowed values:
0: dmamux1_evt0: Signal `dmamux1_evt0` selected as synchronization input
1: dmamux1_evt1: Signal `dmamux1_evt1` selected as synchronization input
2: dmamux1_evt2: Signal `dmamux1_evt2` selected as synchronization input
3: lptim1_out: Signal `lptim1_out` selected as synchronization input
4: lptim2_out: Signal `lptim2_out` selected as synchronization input
5: lptim3_out: Signal `lptim3_out` selected as synchronization input
6: extit0: Signal `extit0` selected as synchronization input
7: tim12_trgo: Signal `tim12_trgo` selected as synchronization input

C[14]CR

DMAMux - DMA request line multiplexer channel x control register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-7: Input DMA request line selected.

Allowed values:
0: none: No signal selected as request input
1: dmamux1_req_gen0: Signal `dmamux1_req_gen0` selected as request input
2: dmamux1_req_gen1: Signal `dmamux1_req_gen1` selected as request input
3: dmamux1_req_gen2: Signal `dmamux1_req_gen2` selected as request input
4: dmamux1_req_gen3: Signal `dmamux1_req_gen3` selected as request input
5: dmamux1_req_gen4: Signal `dmamux1_req_gen4` selected as request input
6: dmamux1_req_gen5: Signal `dmamux1_req_gen5` selected as request input
7: dmamux1_req_gen6: Signal `dmamux1_req_gen6` selected as request input
8: dmamux1_req_gen7: Signal `dmamux1_req_gen7` selected as request input
9: adc1_dma: Signal `adc1_dma` selected as request input
10: adc2_dma: Signal `adc2_dma` selected as request input
11: tim1_ch1: Signal `tim1_ch1` selected as request input
12: tim1_ch2: Signal `tim1_ch2` selected as request input
13: tim1_ch3: Signal `tim1_ch3` selected as request input
14: tim1_ch4: Signal `tim1_ch4` selected as request input
15: tim1_up: Signal `tim1_up` selected as request input
16: tim1_trig: Signal `tim1_trig` selected as request input
17: tim1_com: Signal `tim1_com` selected as request input
18: tim2_ch1: Signal `tim2_ch1` selected as request input
19: tim2_ch2: Signal `tim2_ch2` selected as request input
20: tim2_ch3: Signal `tim2_ch3` selected as request input
21: tim2_ch4: Signal `tim2_ch4` selected as request input
22: tim2_up: Signal `tim2_up` selected as request input
23: tim3_ch1: Signal `tim3_ch1` selected as request input
24: tim3_ch2: Signal `tim3_ch2` selected as request input
25: tim3_ch3: Signal `tim3_ch3` selected as request input
26: tim3_ch4: Signal `tim3_ch4` selected as request input
27: tim3_up: Signal `tim3_up` selected as request input
28: tim3_trig: Signal `tim3_trig` selected as request input
29: tim4_ch1: Signal `tim4_ch1` selected as request input
30: tim4_ch2: Signal `tim4_ch2` selected as request input
31: tim4_ch3: Signal `tim4_ch3` selected as request input
32: tim4_up: Signal `tim4_up` selected as request input
33: i2c1_rx_dma: Signal `i2c1_rx_dma` selected as request input
34: i2c1_tx_dma: Signal `i2c1_tx_dma` selected as request input
35: i2c2_rx_dma: Signal `i2c2_rx_dma` selected as request input
36: i2c2_tx_dma: Signal `i2c2_tx_dma` selected as request input
37: spi1_rx_dma: Signal `spi1_rx_dma` selected as request input
38: spi1_tx_dma: Signal `spi1_tx_dma` selected as request input
39: spi2_rx_dma: Signal `spi2_rx_dma` selected as request input
40: spi2_tx_dma: Signal `spi2_tx_dma` selected as request input
41: usart1_rx_dma: Signal `usart1_rx_dma` selected as request input
42: usart1_tx_dma: Signal `usart1_tx_dma` selected as request input
43: usart2_rx_dma: Signal `usart2_rx_dma` selected as request input
44: usart2_tx_dma: Signal `usart2_tx_dma` selected as request input
45: usart3_rx_dma: Signal `usart3_rx_dma` selected as request input
46: usart3_tx_dma: Signal `usart3_tx_dma` selected as request input
47: tim8_ch1: Signal `tim8_ch1` selected as request input
48: tim8_ch2: Signal `tim8_ch2` selected as request input
49: tim8_ch3: Signal `tim8_ch3` selected as request input
50: tim8_ch4: Signal `tim8_ch4` selected as request input
51: tim8_up: Signal `tim8_up` selected as request input
52: tim8_trig: Signal `tim8_trig` selected as request input
53: tim8_com: Signal `tim8_com` selected as request input
55: tim5_ch1: Signal `tim5_ch1` selected as request input
56: tim5_ch2: Signal `tim5_ch2` selected as request input
57: tim5_ch3: Signal `tim5_ch3` selected as request input
58: tim5_ch4: Signal `tim5_ch4` selected as request input
59: tim5_up: Signal `tim5_up` selected as request input
60: tim5_trig: Signal `tim5_trig` selected as request input
61: spi3_rx_dma: Signal `spi3_rx_dma` selected as request input
62: spi3_tx_dma: Signal `spi3_tx_dma` selected as request input
63: uart4_rx_dma: Signal `uart4_rx_dma` selected as request input
64: uart4_tx_dma: Signal `uart4_tx_dma` selected as request input
65: uart5_rx_dma: Signal `uart5_rx_dma` selected as request input
66: uart5_tx_dma: Signal `uart5_tx_dma` selected as request input
67: dac_ch1_dma: Signal `dac_ch1_dma` selected as request input
68: dac_ch2_dma: Signal `dac_ch2_dma` selected as request input
69: tim6_up: Signal `tim6_up` selected as request input
70: tim7_up: Signal `tim7_up` selected as request input
71: usart6_rx_dma: Signal `usart6_rx_dma` selected as request input
72: usart6_tx_dma: Signal `usart6_tx_dma` selected as request input
73: i2c3_rx_dma: Signal `i2c3_rx_dma` selected as request input
74: i2c3_tx_dma: Signal `i2c3_tx_dma` selected as request input
75: dcmi_dma: Signal `dcmi_dma` selected as request input
76: cryp_in_dma: Signal `cryp_in_dma` selected as request input
77: cryp_out_dma: Signal `cryp_out_dma` selected as request input
78: hash_in_dma: Signal `hash_in_dma` selected as request input
79: uart7_rx_dma: Signal `uart7_rx_dma` selected as request input
80: uart7_tx_dma: Signal `uart7_tx_dma` selected as request input
81: uart8_rx_dma: Signal `uart8_rx_dma` selected as request input
82: uart8_tx_dma: Signal `uart8_tx_dma` selected as request input
83: spi4_rx_dma: Signal `spi4_rx_dma` selected as request input
84: spi4_tx_dma: Signal `spi4_tx_dma` selected as request input
85: spi5_rx_dma: Signal `spi5_rx_dma` selected as request input
86: spi5_tx_dma: Signal `spi5_tx_dma` selected as request input
87: sai1a_dma: Signal `sai1a_dma` selected as request input
88: sai1b_dma: Signal `sai1b_dma` selected as request input
89: sai2a_dma: Signal `sai2a_dma` selected as request input
90: sai2b_dma: Signal `sai2b_dma` selected as request input
91: swpmi_rx_dma: Signal `swpmi_rx_dma` selected as request input
92: swpmi_tx_dma: Signal `swpmi_tx_dma` selected as request input
93: spdifrx_dat_dma: Signal `spdifrx_dat_dma` selected as request input
94: spdifrx_ctrl_dma: Signal `spdifrx_ctrl_dma` selected as request input
95: hr_req1: Signal `hr_req(1)` selected as request input
96: hr_req2: Signal `hr_req(2)` selected as request input
97: hr_req3: Signal `hr_req(3)` selected as request input
98: hr_req4: Signal `hr_req(4)` selected as request input
99: hr_req5: Signal `hr_req(5)` selected as request input
100: hr_req6: Signal `hr_req(6)` selected as request input
101: dfsdm1_dma0: Signal `dfsdm1_dma0` selected as request input
102: dfsdm1_dma1: Signal `dfsdm1_dma1` selected as request input
103: dfsdm1_dma2: Signal `dfsdm1_dma2` selected as request input
104: dfsdm1_dma3: Signal `dfsdm1_dma3` selected as request input
105: tim15_ch1: Signal `tim15_ch1` selected as request input
106: tim15_up: Signal `tim15_up` selected as request input
107: tim15_trig: Signal `tim15_trig` selected as request input
108: tim15_com: Signal `tim15_com` selected as request input
109: tim16_ch1: Signal `tim16_ch1` selected as request input
110: tim16_up: Signal `tim16_up` selected as request input
111: tim17_ch1: Signal `tim17_ch1` selected as request input
112: tim17_up: Signal `tim17_up` selected as request input
113: sai3_a_dma: Signal `sai3_a_dma` selected as request input
114: sai3_b_dma: Signal `sai3_b_dma` selected as request input
115: adc3_dma: Signal `adc3_dma` selected as request input

SOIE

Bit 8: Interrupt enable at synchronization event overrun.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable/disable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronous operating mode enable/disable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization event type selector Defines the synchronization event on the selected synchronization input:.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset..

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization input selected.

Allowed values:
0: dmamux1_evt0: Signal `dmamux1_evt0` selected as synchronization input
1: dmamux1_evt1: Signal `dmamux1_evt1` selected as synchronization input
2: dmamux1_evt2: Signal `dmamux1_evt2` selected as synchronization input
3: lptim1_out: Signal `lptim1_out` selected as synchronization input
4: lptim2_out: Signal `lptim2_out` selected as synchronization input
5: lptim3_out: Signal `lptim3_out` selected as synchronization input
6: extit0: Signal `extit0` selected as synchronization input
7: tim12_trgo: Signal `tim12_trgo` selected as synchronization input

C[15]CR

DMAMux - DMA request line multiplexer channel x control register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-7: Input DMA request line selected.

Allowed values:
0: none: No signal selected as request input
1: dmamux1_req_gen0: Signal `dmamux1_req_gen0` selected as request input
2: dmamux1_req_gen1: Signal `dmamux1_req_gen1` selected as request input
3: dmamux1_req_gen2: Signal `dmamux1_req_gen2` selected as request input
4: dmamux1_req_gen3: Signal `dmamux1_req_gen3` selected as request input
5: dmamux1_req_gen4: Signal `dmamux1_req_gen4` selected as request input
6: dmamux1_req_gen5: Signal `dmamux1_req_gen5` selected as request input
7: dmamux1_req_gen6: Signal `dmamux1_req_gen6` selected as request input
8: dmamux1_req_gen7: Signal `dmamux1_req_gen7` selected as request input
9: adc1_dma: Signal `adc1_dma` selected as request input
10: adc2_dma: Signal `adc2_dma` selected as request input
11: tim1_ch1: Signal `tim1_ch1` selected as request input
12: tim1_ch2: Signal `tim1_ch2` selected as request input
13: tim1_ch3: Signal `tim1_ch3` selected as request input
14: tim1_ch4: Signal `tim1_ch4` selected as request input
15: tim1_up: Signal `tim1_up` selected as request input
16: tim1_trig: Signal `tim1_trig` selected as request input
17: tim1_com: Signal `tim1_com` selected as request input
18: tim2_ch1: Signal `tim2_ch1` selected as request input
19: tim2_ch2: Signal `tim2_ch2` selected as request input
20: tim2_ch3: Signal `tim2_ch3` selected as request input
21: tim2_ch4: Signal `tim2_ch4` selected as request input
22: tim2_up: Signal `tim2_up` selected as request input
23: tim3_ch1: Signal `tim3_ch1` selected as request input
24: tim3_ch2: Signal `tim3_ch2` selected as request input
25: tim3_ch3: Signal `tim3_ch3` selected as request input
26: tim3_ch4: Signal `tim3_ch4` selected as request input
27: tim3_up: Signal `tim3_up` selected as request input
28: tim3_trig: Signal `tim3_trig` selected as request input
29: tim4_ch1: Signal `tim4_ch1` selected as request input
30: tim4_ch2: Signal `tim4_ch2` selected as request input
31: tim4_ch3: Signal `tim4_ch3` selected as request input
32: tim4_up: Signal `tim4_up` selected as request input
33: i2c1_rx_dma: Signal `i2c1_rx_dma` selected as request input
34: i2c1_tx_dma: Signal `i2c1_tx_dma` selected as request input
35: i2c2_rx_dma: Signal `i2c2_rx_dma` selected as request input
36: i2c2_tx_dma: Signal `i2c2_tx_dma` selected as request input
37: spi1_rx_dma: Signal `spi1_rx_dma` selected as request input
38: spi1_tx_dma: Signal `spi1_tx_dma` selected as request input
39: spi2_rx_dma: Signal `spi2_rx_dma` selected as request input
40: spi2_tx_dma: Signal `spi2_tx_dma` selected as request input
41: usart1_rx_dma: Signal `usart1_rx_dma` selected as request input
42: usart1_tx_dma: Signal `usart1_tx_dma` selected as request input
43: usart2_rx_dma: Signal `usart2_rx_dma` selected as request input
44: usart2_tx_dma: Signal `usart2_tx_dma` selected as request input
45: usart3_rx_dma: Signal `usart3_rx_dma` selected as request input
46: usart3_tx_dma: Signal `usart3_tx_dma` selected as request input
47: tim8_ch1: Signal `tim8_ch1` selected as request input
48: tim8_ch2: Signal `tim8_ch2` selected as request input
49: tim8_ch3: Signal `tim8_ch3` selected as request input
50: tim8_ch4: Signal `tim8_ch4` selected as request input
51: tim8_up: Signal `tim8_up` selected as request input
52: tim8_trig: Signal `tim8_trig` selected as request input
53: tim8_com: Signal `tim8_com` selected as request input
55: tim5_ch1: Signal `tim5_ch1` selected as request input
56: tim5_ch2: Signal `tim5_ch2` selected as request input
57: tim5_ch3: Signal `tim5_ch3` selected as request input
58: tim5_ch4: Signal `tim5_ch4` selected as request input
59: tim5_up: Signal `tim5_up` selected as request input
60: tim5_trig: Signal `tim5_trig` selected as request input
61: spi3_rx_dma: Signal `spi3_rx_dma` selected as request input
62: spi3_tx_dma: Signal `spi3_tx_dma` selected as request input
63: uart4_rx_dma: Signal `uart4_rx_dma` selected as request input
64: uart4_tx_dma: Signal `uart4_tx_dma` selected as request input
65: uart5_rx_dma: Signal `uart5_rx_dma` selected as request input
66: uart5_tx_dma: Signal `uart5_tx_dma` selected as request input
67: dac_ch1_dma: Signal `dac_ch1_dma` selected as request input
68: dac_ch2_dma: Signal `dac_ch2_dma` selected as request input
69: tim6_up: Signal `tim6_up` selected as request input
70: tim7_up: Signal `tim7_up` selected as request input
71: usart6_rx_dma: Signal `usart6_rx_dma` selected as request input
72: usart6_tx_dma: Signal `usart6_tx_dma` selected as request input
73: i2c3_rx_dma: Signal `i2c3_rx_dma` selected as request input
74: i2c3_tx_dma: Signal `i2c3_tx_dma` selected as request input
75: dcmi_dma: Signal `dcmi_dma` selected as request input
76: cryp_in_dma: Signal `cryp_in_dma` selected as request input
77: cryp_out_dma: Signal `cryp_out_dma` selected as request input
78: hash_in_dma: Signal `hash_in_dma` selected as request input
79: uart7_rx_dma: Signal `uart7_rx_dma` selected as request input
80: uart7_tx_dma: Signal `uart7_tx_dma` selected as request input
81: uart8_rx_dma: Signal `uart8_rx_dma` selected as request input
82: uart8_tx_dma: Signal `uart8_tx_dma` selected as request input
83: spi4_rx_dma: Signal `spi4_rx_dma` selected as request input
84: spi4_tx_dma: Signal `spi4_tx_dma` selected as request input
85: spi5_rx_dma: Signal `spi5_rx_dma` selected as request input
86: spi5_tx_dma: Signal `spi5_tx_dma` selected as request input
87: sai1a_dma: Signal `sai1a_dma` selected as request input
88: sai1b_dma: Signal `sai1b_dma` selected as request input
89: sai2a_dma: Signal `sai2a_dma` selected as request input
90: sai2b_dma: Signal `sai2b_dma` selected as request input
91: swpmi_rx_dma: Signal `swpmi_rx_dma` selected as request input
92: swpmi_tx_dma: Signal `swpmi_tx_dma` selected as request input
93: spdifrx_dat_dma: Signal `spdifrx_dat_dma` selected as request input
94: spdifrx_ctrl_dma: Signal `spdifrx_ctrl_dma` selected as request input
95: hr_req1: Signal `hr_req(1)` selected as request input
96: hr_req2: Signal `hr_req(2)` selected as request input
97: hr_req3: Signal `hr_req(3)` selected as request input
98: hr_req4: Signal `hr_req(4)` selected as request input
99: hr_req5: Signal `hr_req(5)` selected as request input
100: hr_req6: Signal `hr_req(6)` selected as request input
101: dfsdm1_dma0: Signal `dfsdm1_dma0` selected as request input
102: dfsdm1_dma1: Signal `dfsdm1_dma1` selected as request input
103: dfsdm1_dma2: Signal `dfsdm1_dma2` selected as request input
104: dfsdm1_dma3: Signal `dfsdm1_dma3` selected as request input
105: tim15_ch1: Signal `tim15_ch1` selected as request input
106: tim15_up: Signal `tim15_up` selected as request input
107: tim15_trig: Signal `tim15_trig` selected as request input
108: tim15_com: Signal `tim15_com` selected as request input
109: tim16_ch1: Signal `tim16_ch1` selected as request input
110: tim16_up: Signal `tim16_up` selected as request input
111: tim17_ch1: Signal `tim17_ch1` selected as request input
112: tim17_up: Signal `tim17_up` selected as request input
113: sai3_a_dma: Signal `sai3_a_dma` selected as request input
114: sai3_b_dma: Signal `sai3_b_dma` selected as request input
115: adc3_dma: Signal `adc3_dma` selected as request input

SOIE

Bit 8: Interrupt enable at synchronization event overrun.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable/disable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronous operating mode enable/disable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization event type selector Defines the synchronization event on the selected synchronization input:.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset..

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization input selected.

Allowed values:
0: dmamux1_evt0: Signal `dmamux1_evt0` selected as synchronization input
1: dmamux1_evt1: Signal `dmamux1_evt1` selected as synchronization input
2: dmamux1_evt2: Signal `dmamux1_evt2` selected as synchronization input
3: lptim1_out: Signal `lptim1_out` selected as synchronization input
4: lptim2_out: Signal `lptim2_out` selected as synchronization input
5: lptim3_out: Signal `lptim3_out` selected as synchronization input
6: extit0: Signal `extit0` selected as synchronization input
7: tim12_trgo: Signal `tim12_trgo` selected as synchronization input

CSR

DMAMUX request line multiplexer interrupt channel status register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

Toggle fields

SOF[0]

Bit 0: Synchronization overrun event flag.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[1]

Bit 1: Synchronization overrun event flag.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[2]

Bit 2: Synchronization overrun event flag.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[3]

Bit 3: Synchronization overrun event flag.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[4]

Bit 4: Synchronization overrun event flag.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[5]

Bit 5: Synchronization overrun event flag.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[6]

Bit 6: Synchronization overrun event flag.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[7]

Bit 7: Synchronization overrun event flag.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[8]

Bit 8: Synchronization overrun event flag.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[9]

Bit 9: Synchronization overrun event flag.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[10]

Bit 10: Synchronization overrun event flag.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[11]

Bit 11: Synchronization overrun event flag.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[12]

Bit 12: Synchronization overrun event flag.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[13]

Bit 13: Synchronization overrun event flag.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[14]

Bit 14: Synchronization overrun event flag.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[15]

Bit 15: Synchronization overrun event flag.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

CFR

DMAMUX request line multiplexer interrupt clear flag register

Offset: 0x84, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

Toggle fields

CSOF[0]

Bit 0: Clear synchronization overrun event flag.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[1]

Bit 1: Clear synchronization overrun event flag.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[2]

Bit 2: Clear synchronization overrun event flag.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[3]

Bit 3: Clear synchronization overrun event flag.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[4]

Bit 4: Clear synchronization overrun event flag.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[5]

Bit 5: Clear synchronization overrun event flag.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[6]

Bit 6: Clear synchronization overrun event flag.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[7]

Bit 7: Clear synchronization overrun event flag.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[8]

Bit 8: Clear synchronization overrun event flag.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[9]

Bit 9: Clear synchronization overrun event flag.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[10]

Bit 10: Clear synchronization overrun event flag.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[11]

Bit 11: Clear synchronization overrun event flag.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[12]

Bit 12: Clear synchronization overrun event flag.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[13]

Bit 13: Clear synchronization overrun event flag.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[14]

Bit 14: Clear synchronization overrun event flag.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[15]

Bit 15: Clear synchronization overrun event flag.

Allowed values:
1: Clear: Clear synchronization flag

RG[0]CR

DMAMux - DMA request generator channel x control register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw
GPOL
rw
GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw
SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: DMA request trigger input selected.

Allowed values:
0: dmamux1_evt0: Signal `dmamux1_evt0` selected as trigger input
1: dmamux1_evt1: Signal `dmamux1_evt1` selected as trigger input
2: dmamux1_evt2: Signal `dmamux1_evt2` selected as trigger input
3: lptim1_out: Signal `lptim1_out` selected as trigger input
4: lptim2_out: Signal `lptim2_out` selected as trigger input
5: lptim3_out: Signal `lptim3_out` selected as trigger input
6: extit0: Signal `extit0` selected as trigger input
7: tim12_trgo: Signal `tim12_trgo` selected as trigger input

OIE

Bit 8: Interrupt enable at trigger event overrun.

Allowed values:
0: Disabled: Trigger overrun interrupt disabled
1: Enabled: Trigger overrun interrupt enabled

GE

Bit 16: DMA request generator channel enable/disable.

Allowed values:
0: Disabled: DMA request generation disabled
1: Enabled: DMA request enabled

GPOL

Bits 17-18: DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input.

Allowed values:
0: NoEdge: No event, i.e. no detection nor generation
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

GNBREQ

Bits 19-23: Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset..

Allowed values: 0x0-0x1f

RG[1]CR

DMAMux - DMA request generator channel x control register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw
GPOL
rw
GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw
SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: DMA request trigger input selected.

Allowed values:
0: dmamux1_evt0: Signal `dmamux1_evt0` selected as trigger input
1: dmamux1_evt1: Signal `dmamux1_evt1` selected as trigger input
2: dmamux1_evt2: Signal `dmamux1_evt2` selected as trigger input
3: lptim1_out: Signal `lptim1_out` selected as trigger input
4: lptim2_out: Signal `lptim2_out` selected as trigger input
5: lptim3_out: Signal `lptim3_out` selected as trigger input
6: extit0: Signal `extit0` selected as trigger input
7: tim12_trgo: Signal `tim12_trgo` selected as trigger input

OIE

Bit 8: Interrupt enable at trigger event overrun.

Allowed values:
0: Disabled: Trigger overrun interrupt disabled
1: Enabled: Trigger overrun interrupt enabled

GE

Bit 16: DMA request generator channel enable/disable.

Allowed values:
0: Disabled: DMA request generation disabled
1: Enabled: DMA request enabled

GPOL

Bits 17-18: DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input.

Allowed values:
0: NoEdge: No event, i.e. no detection nor generation
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

GNBREQ

Bits 19-23: Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset..

Allowed values: 0x0-0x1f

RG[2]CR

DMAMux - DMA request generator channel x control register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw
GPOL
rw
GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw
SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: DMA request trigger input selected.

Allowed values:
0: dmamux1_evt0: Signal `dmamux1_evt0` selected as trigger input
1: dmamux1_evt1: Signal `dmamux1_evt1` selected as trigger input
2: dmamux1_evt2: Signal `dmamux1_evt2` selected as trigger input
3: lptim1_out: Signal `lptim1_out` selected as trigger input
4: lptim2_out: Signal `lptim2_out` selected as trigger input
5: lptim3_out: Signal `lptim3_out` selected as trigger input
6: extit0: Signal `extit0` selected as trigger input
7: tim12_trgo: Signal `tim12_trgo` selected as trigger input

OIE

Bit 8: Interrupt enable at trigger event overrun.

Allowed values:
0: Disabled: Trigger overrun interrupt disabled
1: Enabled: Trigger overrun interrupt enabled

GE

Bit 16: DMA request generator channel enable/disable.

Allowed values:
0: Disabled: DMA request generation disabled
1: Enabled: DMA request enabled

GPOL

Bits 17-18: DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input.

Allowed values:
0: NoEdge: No event, i.e. no detection nor generation
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

GNBREQ

Bits 19-23: Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset..

Allowed values: 0x0-0x1f

RG[3]CR

DMAMux - DMA request generator channel x control register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw
GPOL
rw
GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw
SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: DMA request trigger input selected.

Allowed values:
0: dmamux1_evt0: Signal `dmamux1_evt0` selected as trigger input
1: dmamux1_evt1: Signal `dmamux1_evt1` selected as trigger input
2: dmamux1_evt2: Signal `dmamux1_evt2` selected as trigger input
3: lptim1_out: Signal `lptim1_out` selected as trigger input
4: lptim2_out: Signal `lptim2_out` selected as trigger input
5: lptim3_out: Signal `lptim3_out` selected as trigger input
6: extit0: Signal `extit0` selected as trigger input
7: tim12_trgo: Signal `tim12_trgo` selected as trigger input

OIE

Bit 8: Interrupt enable at trigger event overrun.

Allowed values:
0: Disabled: Trigger overrun interrupt disabled
1: Enabled: Trigger overrun interrupt enabled

GE

Bit 16: DMA request generator channel enable/disable.

Allowed values:
0: Disabled: DMA request generation disabled
1: Enabled: DMA request enabled

GPOL

Bits 17-18: DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input.

Allowed values:
0: NoEdge: No event, i.e. no detection nor generation
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

GNBREQ

Bits 19-23: Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset..

Allowed values: 0x0-0x1f

RG[4]CR

DMAMux - DMA request generator channel x control register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw
GPOL
rw
GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw
SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: DMA request trigger input selected.

Allowed values:
0: dmamux1_evt0: Signal `dmamux1_evt0` selected as trigger input
1: dmamux1_evt1: Signal `dmamux1_evt1` selected as trigger input
2: dmamux1_evt2: Signal `dmamux1_evt2` selected as trigger input
3: lptim1_out: Signal `lptim1_out` selected as trigger input
4: lptim2_out: Signal `lptim2_out` selected as trigger input
5: lptim3_out: Signal `lptim3_out` selected as trigger input
6: extit0: Signal `extit0` selected as trigger input
7: tim12_trgo: Signal `tim12_trgo` selected as trigger input

OIE

Bit 8: Interrupt enable at trigger event overrun.

Allowed values:
0: Disabled: Trigger overrun interrupt disabled
1: Enabled: Trigger overrun interrupt enabled

GE

Bit 16: DMA request generator channel enable/disable.

Allowed values:
0: Disabled: DMA request generation disabled
1: Enabled: DMA request enabled

GPOL

Bits 17-18: DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input.

Allowed values:
0: NoEdge: No event, i.e. no detection nor generation
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

GNBREQ

Bits 19-23: Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset..

Allowed values: 0x0-0x1f

RG[5]CR

DMAMux - DMA request generator channel x control register

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw
GPOL
rw
GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw
SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: DMA request trigger input selected.

Allowed values:
0: dmamux1_evt0: Signal `dmamux1_evt0` selected as trigger input
1: dmamux1_evt1: Signal `dmamux1_evt1` selected as trigger input
2: dmamux1_evt2: Signal `dmamux1_evt2` selected as trigger input
3: lptim1_out: Signal `lptim1_out` selected as trigger input
4: lptim2_out: Signal `lptim2_out` selected as trigger input
5: lptim3_out: Signal `lptim3_out` selected as trigger input
6: extit0: Signal `extit0` selected as trigger input
7: tim12_trgo: Signal `tim12_trgo` selected as trigger input

OIE

Bit 8: Interrupt enable at trigger event overrun.

Allowed values:
0: Disabled: Trigger overrun interrupt disabled
1: Enabled: Trigger overrun interrupt enabled

GE

Bit 16: DMA request generator channel enable/disable.

Allowed values:
0: Disabled: DMA request generation disabled
1: Enabled: DMA request enabled

GPOL

Bits 17-18: DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input.

Allowed values:
0: NoEdge: No event, i.e. no detection nor generation
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

GNBREQ

Bits 19-23: Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset..

Allowed values: 0x0-0x1f

RG[6]CR

DMAMux - DMA request generator channel x control register

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw
GPOL
rw
GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw
SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: DMA request trigger input selected.

Allowed values:
0: dmamux1_evt0: Signal `dmamux1_evt0` selected as trigger input
1: dmamux1_evt1: Signal `dmamux1_evt1` selected as trigger input
2: dmamux1_evt2: Signal `dmamux1_evt2` selected as trigger input
3: lptim1_out: Signal `lptim1_out` selected as trigger input
4: lptim2_out: Signal `lptim2_out` selected as trigger input
5: lptim3_out: Signal `lptim3_out` selected as trigger input
6: extit0: Signal `extit0` selected as trigger input
7: tim12_trgo: Signal `tim12_trgo` selected as trigger input

OIE

Bit 8: Interrupt enable at trigger event overrun.

Allowed values:
0: Disabled: Trigger overrun interrupt disabled
1: Enabled: Trigger overrun interrupt enabled

GE

Bit 16: DMA request generator channel enable/disable.

Allowed values:
0: Disabled: DMA request generation disabled
1: Enabled: DMA request enabled

GPOL

Bits 17-18: DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input.

Allowed values:
0: NoEdge: No event, i.e. no detection nor generation
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

GNBREQ

Bits 19-23: Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset..

Allowed values: 0x0-0x1f

RG[7]CR

DMAMux - DMA request generator channel x control register

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw
GPOL
rw
GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw
SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: DMA request trigger input selected.

Allowed values:
0: dmamux1_evt0: Signal `dmamux1_evt0` selected as trigger input
1: dmamux1_evt1: Signal `dmamux1_evt1` selected as trigger input
2: dmamux1_evt2: Signal `dmamux1_evt2` selected as trigger input
3: lptim1_out: Signal `lptim1_out` selected as trigger input
4: lptim2_out: Signal `lptim2_out` selected as trigger input
5: lptim3_out: Signal `lptim3_out` selected as trigger input
6: extit0: Signal `extit0` selected as trigger input
7: tim12_trgo: Signal `tim12_trgo` selected as trigger input

OIE

Bit 8: Interrupt enable at trigger event overrun.

Allowed values:
0: Disabled: Trigger overrun interrupt disabled
1: Enabled: Trigger overrun interrupt enabled

GE

Bit 16: DMA request generator channel enable/disable.

Allowed values:
0: Disabled: DMA request generation disabled
1: Enabled: DMA request enabled

GPOL

Bits 17-18: DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input.

Allowed values:
0: NoEdge: No event, i.e. no detection nor generation
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

GNBREQ

Bits 19-23: Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset..

Allowed values: 0x0-0x1f

RGSR

DMAMux - DMA request generator status register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF[7]
r
OF[6]
r
OF[5]
r
OF[4]
r
OF[3]
r
OF[2]
r
OF[1]
r
OF[0]
r
Toggle fields

OF[0]

Bit 0: Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register..

Allowed values:
0: NoTrigger: No new trigger event occured on DMA request generator channel x, before the request counter underrun
1: Trigger: New trigger event occured on DMA request generator channel x, before the request counter underrun

OF[1]

Bit 1: Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register..

Allowed values:
0: NoTrigger: No new trigger event occured on DMA request generator channel x, before the request counter underrun
1: Trigger: New trigger event occured on DMA request generator channel x, before the request counter underrun

OF[2]

Bit 2: Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register..

Allowed values:
0: NoTrigger: No new trigger event occured on DMA request generator channel x, before the request counter underrun
1: Trigger: New trigger event occured on DMA request generator channel x, before the request counter underrun

OF[3]

Bit 3: Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register..

Allowed values:
0: NoTrigger: No new trigger event occured on DMA request generator channel x, before the request counter underrun
1: Trigger: New trigger event occured on DMA request generator channel x, before the request counter underrun

OF[4]

Bit 4: Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register..

Allowed values:
0: NoTrigger: No new trigger event occured on DMA request generator channel x, before the request counter underrun
1: Trigger: New trigger event occured on DMA request generator channel x, before the request counter underrun

OF[5]

Bit 5: Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register..

Allowed values:
0: NoTrigger: No new trigger event occured on DMA request generator channel x, before the request counter underrun
1: Trigger: New trigger event occured on DMA request generator channel x, before the request counter underrun

OF[6]

Bit 6: Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register..

Allowed values:
0: NoTrigger: No new trigger event occured on DMA request generator channel x, before the request counter underrun
1: Trigger: New trigger event occured on DMA request generator channel x, before the request counter underrun

OF[7]

Bit 7: Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register..

Allowed values:
0: NoTrigger: No new trigger event occured on DMA request generator channel x, before the request counter underrun
1: Trigger: New trigger event occured on DMA request generator channel x, before the request counter underrun

RGCFR

DMAMux - DMA request generator clear flag register

Offset: 0x144, size: 32, reset: 0x00000000, access: write-only

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COF[7]
w1c
COF[6]
w1c
COF[5]
w1c
COF[4]
w1c
COF[3]
w1c
COF[2]
w1c
COF[1]
w1c
COF[0]
w1c
Toggle fields

COF[0]

Bit 0: Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register..

Allowed values:
1: Clear: Clear overrun flag

COF[1]

Bit 1: Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register..

Allowed values:
1: Clear: Clear overrun flag

COF[2]

Bit 2: Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register..

Allowed values:
1: Clear: Clear overrun flag

COF[3]

Bit 3: Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register..

Allowed values:
1: Clear: Clear overrun flag

COF[4]

Bit 4: Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register..

Allowed values:
1: Clear: Clear overrun flag

COF[5]

Bit 5: Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register..

Allowed values:
1: Clear: Clear overrun flag

COF[6]

Bit 6: Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register..

Allowed values:
1: Clear: Clear overrun flag

COF[7]

Bit 7: Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register..

Allowed values:
1: Clear: Clear overrun flag

DMAMUX2

0x58025800: DMAMUX

144/144 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 C[0]CR
0x4 C[1]CR
0x8 C[2]CR
0xc C[3]CR
0x10 C[4]CR
0x14 C[5]CR
0x18 C[6]CR
0x1c C[7]CR
0x80 CSR
0x84 CFR
0x100 RG[0]CR
0x104 RG[1]CR
0x108 RG[2]CR
0x10c RG[3]CR
0x110 RG[4]CR
0x114 RG[5]CR
0x118 RG[6]CR
0x11c RG[7]CR
0x140 RGSR
0x144 RGCFR
Toggle registers

C[0]CR

DMAMux - DMA request line multiplexer channel x control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-7: Input DMA request line selected.

Allowed values:
0: none: No signal selected as request input
1: dmamux2_req_gen0: Signal `dmamux2_req_gen0` selected as request input
2: dmamux2_req_gen1: Signal `dmamux2_req_gen1` selected as request input
3: dmamux2_req_gen2: Signal `dmamux2_req_gen2` selected as request input
4: dmamux2_req_gen3: Signal `dmamux2_req_gen3` selected as request input
5: dmamux2_req_gen4: Signal `dmamux2_req_gen4` selected as request input
6: dmamux2_req_gen5: Signal `dmamux2_req_gen5` selected as request input
7: dmamux2_req_gen6: Signal `dmamux2_req_gen6` selected as request input
8: dmamux2_req_gen7: Signal `dmamux2_req_gen7` selected as request input
9: lpuart1_rx_dma: Signal `lpuart1_rx_dma` selected as request input
10: lpuart1_tx_dma: Signal `lpuart1_tx_dma` selected as request input
11: spi6_rx_dma: Signal `spi6_rx_dma` selected as request input
12: spi6_tx_dma: Signal `spi6_tx_dma` selected as request input
13: i2c4_rx_dma: Signal `i2c4_rx_dma` selected as request input
14: i2c4_tx_dma: Signal `i2c4_tx_dma` selected as request input
15: sai4_a_dma: Signal `sai4_a_dma` selected as request input
16: sai4_b_dma: Signal `sai4_b_dma` selected as request input
17: adc3_dma: Signal `adc3_dma` selected as request input

SOIE

Bit 8: Interrupt enable at synchronization event overrun.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable/disable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronous operating mode enable/disable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization event type selector Defines the synchronization event on the selected synchronization input:.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset..

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization input selected.

Allowed values:
0: dmamux2_evt0: Signal `dmamux2_evt0` selected as synchronization input
1: dmamux2_evt1: Signal `dmamux2_evt1` selected as synchronization input
2: dmamux2_evt2: Signal `dmamux2_evt2` selected as synchronization input
3: dmamux2_evt3: Signal `dmamux2_evt3` selected as synchronization input
4: dmamux2_evt4: Signal `dmamux2_evt4` selected as synchronization input
5: dmamux2_evt5: Signal `dmamux2_evt5` selected as synchronization input
6: lpuart1_rx_wkup: Signal `lpuart1_rx_wkup` selected as synchronization input
7: lpuart1_tx_wkup: Signal `lpuart1_tx_wkup` selected as synchronization input
8: lptim2_out: Signal `lptim2_out` selected as synchronization input
9: lptim3_out: Signal `lptim3_out` selected as synchronization input
10: i2c4_wkup: Signal `i2c4_wkup` selected as synchronization input
11: spi6_wkup: Signal `spi6_wkup` selected as synchronization input
12: comp1_out: Signal `comp1_out` selected as synchronization input
13: rtc_wkup: Signal `rtc_wkup` selected as synchronization input
14: syscfg_exti0_mux: Signal `syscfg_exti0_mux` selected as synchronization input
15: syscfg_exti2_mux: Signal `syscfg_exti2_mux` selected as synchronization input

C[1]CR

DMAMux - DMA request line multiplexer channel x control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-7: Input DMA request line selected.

Allowed values:
0: none: No signal selected as request input
1: dmamux2_req_gen0: Signal `dmamux2_req_gen0` selected as request input
2: dmamux2_req_gen1: Signal `dmamux2_req_gen1` selected as request input
3: dmamux2_req_gen2: Signal `dmamux2_req_gen2` selected as request input
4: dmamux2_req_gen3: Signal `dmamux2_req_gen3` selected as request input
5: dmamux2_req_gen4: Signal `dmamux2_req_gen4` selected as request input
6: dmamux2_req_gen5: Signal `dmamux2_req_gen5` selected as request input
7: dmamux2_req_gen6: Signal `dmamux2_req_gen6` selected as request input
8: dmamux2_req_gen7: Signal `dmamux2_req_gen7` selected as request input
9: lpuart1_rx_dma: Signal `lpuart1_rx_dma` selected as request input
10: lpuart1_tx_dma: Signal `lpuart1_tx_dma` selected as request input
11: spi6_rx_dma: Signal `spi6_rx_dma` selected as request input
12: spi6_tx_dma: Signal `spi6_tx_dma` selected as request input
13: i2c4_rx_dma: Signal `i2c4_rx_dma` selected as request input
14: i2c4_tx_dma: Signal `i2c4_tx_dma` selected as request input
15: sai4_a_dma: Signal `sai4_a_dma` selected as request input
16: sai4_b_dma: Signal `sai4_b_dma` selected as request input
17: adc3_dma: Signal `adc3_dma` selected as request input

SOIE

Bit 8: Interrupt enable at synchronization event overrun.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable/disable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronous operating mode enable/disable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization event type selector Defines the synchronization event on the selected synchronization input:.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset..

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization input selected.

Allowed values:
0: dmamux2_evt0: Signal `dmamux2_evt0` selected as synchronization input
1: dmamux2_evt1: Signal `dmamux2_evt1` selected as synchronization input
2: dmamux2_evt2: Signal `dmamux2_evt2` selected as synchronization input
3: dmamux2_evt3: Signal `dmamux2_evt3` selected as synchronization input
4: dmamux2_evt4: Signal `dmamux2_evt4` selected as synchronization input
5: dmamux2_evt5: Signal `dmamux2_evt5` selected as synchronization input
6: lpuart1_rx_wkup: Signal `lpuart1_rx_wkup` selected as synchronization input
7: lpuart1_tx_wkup: Signal `lpuart1_tx_wkup` selected as synchronization input
8: lptim2_out: Signal `lptim2_out` selected as synchronization input
9: lptim3_out: Signal `lptim3_out` selected as synchronization input
10: i2c4_wkup: Signal `i2c4_wkup` selected as synchronization input
11: spi6_wkup: Signal `spi6_wkup` selected as synchronization input
12: comp1_out: Signal `comp1_out` selected as synchronization input
13: rtc_wkup: Signal `rtc_wkup` selected as synchronization input
14: syscfg_exti0_mux: Signal `syscfg_exti0_mux` selected as synchronization input
15: syscfg_exti2_mux: Signal `syscfg_exti2_mux` selected as synchronization input

C[2]CR

DMAMux - DMA request line multiplexer channel x control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-7: Input DMA request line selected.

Allowed values:
0: none: No signal selected as request input
1: dmamux2_req_gen0: Signal `dmamux2_req_gen0` selected as request input
2: dmamux2_req_gen1: Signal `dmamux2_req_gen1` selected as request input
3: dmamux2_req_gen2: Signal `dmamux2_req_gen2` selected as request input
4: dmamux2_req_gen3: Signal `dmamux2_req_gen3` selected as request input
5: dmamux2_req_gen4: Signal `dmamux2_req_gen4` selected as request input
6: dmamux2_req_gen5: Signal `dmamux2_req_gen5` selected as request input
7: dmamux2_req_gen6: Signal `dmamux2_req_gen6` selected as request input
8: dmamux2_req_gen7: Signal `dmamux2_req_gen7` selected as request input
9: lpuart1_rx_dma: Signal `lpuart1_rx_dma` selected as request input
10: lpuart1_tx_dma: Signal `lpuart1_tx_dma` selected as request input
11: spi6_rx_dma: Signal `spi6_rx_dma` selected as request input
12: spi6_tx_dma: Signal `spi6_tx_dma` selected as request input
13: i2c4_rx_dma: Signal `i2c4_rx_dma` selected as request input
14: i2c4_tx_dma: Signal `i2c4_tx_dma` selected as request input
15: sai4_a_dma: Signal `sai4_a_dma` selected as request input
16: sai4_b_dma: Signal `sai4_b_dma` selected as request input
17: adc3_dma: Signal `adc3_dma` selected as request input

SOIE

Bit 8: Interrupt enable at synchronization event overrun.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable/disable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronous operating mode enable/disable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization event type selector Defines the synchronization event on the selected synchronization input:.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset..

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization input selected.

Allowed values:
0: dmamux2_evt0: Signal `dmamux2_evt0` selected as synchronization input
1: dmamux2_evt1: Signal `dmamux2_evt1` selected as synchronization input
2: dmamux2_evt2: Signal `dmamux2_evt2` selected as synchronization input
3: dmamux2_evt3: Signal `dmamux2_evt3` selected as synchronization input
4: dmamux2_evt4: Signal `dmamux2_evt4` selected as synchronization input
5: dmamux2_evt5: Signal `dmamux2_evt5` selected as synchronization input
6: lpuart1_rx_wkup: Signal `lpuart1_rx_wkup` selected as synchronization input
7: lpuart1_tx_wkup: Signal `lpuart1_tx_wkup` selected as synchronization input
8: lptim2_out: Signal `lptim2_out` selected as synchronization input
9: lptim3_out: Signal `lptim3_out` selected as synchronization input
10: i2c4_wkup: Signal `i2c4_wkup` selected as synchronization input
11: spi6_wkup: Signal `spi6_wkup` selected as synchronization input
12: comp1_out: Signal `comp1_out` selected as synchronization input
13: rtc_wkup: Signal `rtc_wkup` selected as synchronization input
14: syscfg_exti0_mux: Signal `syscfg_exti0_mux` selected as synchronization input
15: syscfg_exti2_mux: Signal `syscfg_exti2_mux` selected as synchronization input

C[3]CR

DMAMux - DMA request line multiplexer channel x control register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-7: Input DMA request line selected.

Allowed values:
0: none: No signal selected as request input
1: dmamux2_req_gen0: Signal `dmamux2_req_gen0` selected as request input
2: dmamux2_req_gen1: Signal `dmamux2_req_gen1` selected as request input
3: dmamux2_req_gen2: Signal `dmamux2_req_gen2` selected as request input
4: dmamux2_req_gen3: Signal `dmamux2_req_gen3` selected as request input
5: dmamux2_req_gen4: Signal `dmamux2_req_gen4` selected as request input
6: dmamux2_req_gen5: Signal `dmamux2_req_gen5` selected as request input
7: dmamux2_req_gen6: Signal `dmamux2_req_gen6` selected as request input
8: dmamux2_req_gen7: Signal `dmamux2_req_gen7` selected as request input
9: lpuart1_rx_dma: Signal `lpuart1_rx_dma` selected as request input
10: lpuart1_tx_dma: Signal `lpuart1_tx_dma` selected as request input
11: spi6_rx_dma: Signal `spi6_rx_dma` selected as request input
12: spi6_tx_dma: Signal `spi6_tx_dma` selected as request input
13: i2c4_rx_dma: Signal `i2c4_rx_dma` selected as request input
14: i2c4_tx_dma: Signal `i2c4_tx_dma` selected as request input
15: sai4_a_dma: Signal `sai4_a_dma` selected as request input
16: sai4_b_dma: Signal `sai4_b_dma` selected as request input
17: adc3_dma: Signal `adc3_dma` selected as request input

SOIE

Bit 8: Interrupt enable at synchronization event overrun.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable/disable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronous operating mode enable/disable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization event type selector Defines the synchronization event on the selected synchronization input:.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset..

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization input selected.

Allowed values:
0: dmamux2_evt0: Signal `dmamux2_evt0` selected as synchronization input
1: dmamux2_evt1: Signal `dmamux2_evt1` selected as synchronization input
2: dmamux2_evt2: Signal `dmamux2_evt2` selected as synchronization input
3: dmamux2_evt3: Signal `dmamux2_evt3` selected as synchronization input
4: dmamux2_evt4: Signal `dmamux2_evt4` selected as synchronization input
5: dmamux2_evt5: Signal `dmamux2_evt5` selected as synchronization input
6: lpuart1_rx_wkup: Signal `lpuart1_rx_wkup` selected as synchronization input
7: lpuart1_tx_wkup: Signal `lpuart1_tx_wkup` selected as synchronization input
8: lptim2_out: Signal `lptim2_out` selected as synchronization input
9: lptim3_out: Signal `lptim3_out` selected as synchronization input
10: i2c4_wkup: Signal `i2c4_wkup` selected as synchronization input
11: spi6_wkup: Signal `spi6_wkup` selected as synchronization input
12: comp1_out: Signal `comp1_out` selected as synchronization input
13: rtc_wkup: Signal `rtc_wkup` selected as synchronization input
14: syscfg_exti0_mux: Signal `syscfg_exti0_mux` selected as synchronization input
15: syscfg_exti2_mux: Signal `syscfg_exti2_mux` selected as synchronization input

C[4]CR

DMAMux - DMA request line multiplexer channel x control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-7: Input DMA request line selected.

Allowed values:
0: none: No signal selected as request input
1: dmamux2_req_gen0: Signal `dmamux2_req_gen0` selected as request input
2: dmamux2_req_gen1: Signal `dmamux2_req_gen1` selected as request input
3: dmamux2_req_gen2: Signal `dmamux2_req_gen2` selected as request input
4: dmamux2_req_gen3: Signal `dmamux2_req_gen3` selected as request input
5: dmamux2_req_gen4: Signal `dmamux2_req_gen4` selected as request input
6: dmamux2_req_gen5: Signal `dmamux2_req_gen5` selected as request input
7: dmamux2_req_gen6: Signal `dmamux2_req_gen6` selected as request input
8: dmamux2_req_gen7: Signal `dmamux2_req_gen7` selected as request input
9: lpuart1_rx_dma: Signal `lpuart1_rx_dma` selected as request input
10: lpuart1_tx_dma: Signal `lpuart1_tx_dma` selected as request input
11: spi6_rx_dma: Signal `spi6_rx_dma` selected as request input
12: spi6_tx_dma: Signal `spi6_tx_dma` selected as request input
13: i2c4_rx_dma: Signal `i2c4_rx_dma` selected as request input
14: i2c4_tx_dma: Signal `i2c4_tx_dma` selected as request input
15: sai4_a_dma: Signal `sai4_a_dma` selected as request input
16: sai4_b_dma: Signal `sai4_b_dma` selected as request input
17: adc3_dma: Signal `adc3_dma` selected as request input

SOIE

Bit 8: Interrupt enable at synchronization event overrun.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable/disable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronous operating mode enable/disable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization event type selector Defines the synchronization event on the selected synchronization input:.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset..

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization input selected.

Allowed values:
0: dmamux2_evt0: Signal `dmamux2_evt0` selected as synchronization input
1: dmamux2_evt1: Signal `dmamux2_evt1` selected as synchronization input
2: dmamux2_evt2: Signal `dmamux2_evt2` selected as synchronization input
3: dmamux2_evt3: Signal `dmamux2_evt3` selected as synchronization input
4: dmamux2_evt4: Signal `dmamux2_evt4` selected as synchronization input
5: dmamux2_evt5: Signal `dmamux2_evt5` selected as synchronization input
6: lpuart1_rx_wkup: Signal `lpuart1_rx_wkup` selected as synchronization input
7: lpuart1_tx_wkup: Signal `lpuart1_tx_wkup` selected as synchronization input
8: lptim2_out: Signal `lptim2_out` selected as synchronization input
9: lptim3_out: Signal `lptim3_out` selected as synchronization input
10: i2c4_wkup: Signal `i2c4_wkup` selected as synchronization input
11: spi6_wkup: Signal `spi6_wkup` selected as synchronization input
12: comp1_out: Signal `comp1_out` selected as synchronization input
13: rtc_wkup: Signal `rtc_wkup` selected as synchronization input
14: syscfg_exti0_mux: Signal `syscfg_exti0_mux` selected as synchronization input
15: syscfg_exti2_mux: Signal `syscfg_exti2_mux` selected as synchronization input

C[5]CR

DMAMux - DMA request line multiplexer channel x control register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-7: Input DMA request line selected.

Allowed values:
0: none: No signal selected as request input
1: dmamux2_req_gen0: Signal `dmamux2_req_gen0` selected as request input
2: dmamux2_req_gen1: Signal `dmamux2_req_gen1` selected as request input
3: dmamux2_req_gen2: Signal `dmamux2_req_gen2` selected as request input
4: dmamux2_req_gen3: Signal `dmamux2_req_gen3` selected as request input
5: dmamux2_req_gen4: Signal `dmamux2_req_gen4` selected as request input
6: dmamux2_req_gen5: Signal `dmamux2_req_gen5` selected as request input
7: dmamux2_req_gen6: Signal `dmamux2_req_gen6` selected as request input
8: dmamux2_req_gen7: Signal `dmamux2_req_gen7` selected as request input
9: lpuart1_rx_dma: Signal `lpuart1_rx_dma` selected as request input
10: lpuart1_tx_dma: Signal `lpuart1_tx_dma` selected as request input
11: spi6_rx_dma: Signal `spi6_rx_dma` selected as request input
12: spi6_tx_dma: Signal `spi6_tx_dma` selected as request input
13: i2c4_rx_dma: Signal `i2c4_rx_dma` selected as request input
14: i2c4_tx_dma: Signal `i2c4_tx_dma` selected as request input
15: sai4_a_dma: Signal `sai4_a_dma` selected as request input
16: sai4_b_dma: Signal `sai4_b_dma` selected as request input
17: adc3_dma: Signal `adc3_dma` selected as request input

SOIE

Bit 8: Interrupt enable at synchronization event overrun.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable/disable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronous operating mode enable/disable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization event type selector Defines the synchronization event on the selected synchronization input:.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset..

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization input selected.

Allowed values:
0: dmamux2_evt0: Signal `dmamux2_evt0` selected as synchronization input
1: dmamux2_evt1: Signal `dmamux2_evt1` selected as synchronization input
2: dmamux2_evt2: Signal `dmamux2_evt2` selected as synchronization input
3: dmamux2_evt3: Signal `dmamux2_evt3` selected as synchronization input
4: dmamux2_evt4: Signal `dmamux2_evt4` selected as synchronization input
5: dmamux2_evt5: Signal `dmamux2_evt5` selected as synchronization input
6: lpuart1_rx_wkup: Signal `lpuart1_rx_wkup` selected as synchronization input
7: lpuart1_tx_wkup: Signal `lpuart1_tx_wkup` selected as synchronization input
8: lptim2_out: Signal `lptim2_out` selected as synchronization input
9: lptim3_out: Signal `lptim3_out` selected as synchronization input
10: i2c4_wkup: Signal `i2c4_wkup` selected as synchronization input
11: spi6_wkup: Signal `spi6_wkup` selected as synchronization input
12: comp1_out: Signal `comp1_out` selected as synchronization input
13: rtc_wkup: Signal `rtc_wkup` selected as synchronization input
14: syscfg_exti0_mux: Signal `syscfg_exti0_mux` selected as synchronization input
15: syscfg_exti2_mux: Signal `syscfg_exti2_mux` selected as synchronization input

C[6]CR

DMAMux - DMA request line multiplexer channel x control register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-7: Input DMA request line selected.

Allowed values:
0: none: No signal selected as request input
1: dmamux2_req_gen0: Signal `dmamux2_req_gen0` selected as request input
2: dmamux2_req_gen1: Signal `dmamux2_req_gen1` selected as request input
3: dmamux2_req_gen2: Signal `dmamux2_req_gen2` selected as request input
4: dmamux2_req_gen3: Signal `dmamux2_req_gen3` selected as request input
5: dmamux2_req_gen4: Signal `dmamux2_req_gen4` selected as request input
6: dmamux2_req_gen5: Signal `dmamux2_req_gen5` selected as request input
7: dmamux2_req_gen6: Signal `dmamux2_req_gen6` selected as request input
8: dmamux2_req_gen7: Signal `dmamux2_req_gen7` selected as request input
9: lpuart1_rx_dma: Signal `lpuart1_rx_dma` selected as request input
10: lpuart1_tx_dma: Signal `lpuart1_tx_dma` selected as request input
11: spi6_rx_dma: Signal `spi6_rx_dma` selected as request input
12: spi6_tx_dma: Signal `spi6_tx_dma` selected as request input
13: i2c4_rx_dma: Signal `i2c4_rx_dma` selected as request input
14: i2c4_tx_dma: Signal `i2c4_tx_dma` selected as request input
15: sai4_a_dma: Signal `sai4_a_dma` selected as request input
16: sai4_b_dma: Signal `sai4_b_dma` selected as request input
17: adc3_dma: Signal `adc3_dma` selected as request input

SOIE

Bit 8: Interrupt enable at synchronization event overrun.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable/disable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronous operating mode enable/disable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization event type selector Defines the synchronization event on the selected synchronization input:.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset..

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization input selected.

Allowed values:
0: dmamux2_evt0: Signal `dmamux2_evt0` selected as synchronization input
1: dmamux2_evt1: Signal `dmamux2_evt1` selected as synchronization input
2: dmamux2_evt2: Signal `dmamux2_evt2` selected as synchronization input
3: dmamux2_evt3: Signal `dmamux2_evt3` selected as synchronization input
4: dmamux2_evt4: Signal `dmamux2_evt4` selected as synchronization input
5: dmamux2_evt5: Signal `dmamux2_evt5` selected as synchronization input
6: lpuart1_rx_wkup: Signal `lpuart1_rx_wkup` selected as synchronization input
7: lpuart1_tx_wkup: Signal `lpuart1_tx_wkup` selected as synchronization input
8: lptim2_out: Signal `lptim2_out` selected as synchronization input
9: lptim3_out: Signal `lptim3_out` selected as synchronization input
10: i2c4_wkup: Signal `i2c4_wkup` selected as synchronization input
11: spi6_wkup: Signal `spi6_wkup` selected as synchronization input
12: comp1_out: Signal `comp1_out` selected as synchronization input
13: rtc_wkup: Signal `rtc_wkup` selected as synchronization input
14: syscfg_exti0_mux: Signal `syscfg_exti0_mux` selected as synchronization input
15: syscfg_exti2_mux: Signal `syscfg_exti2_mux` selected as synchronization input

C[7]CR

DMAMux - DMA request line multiplexer channel x control register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-7: Input DMA request line selected.

Allowed values:
0: none: No signal selected as request input
1: dmamux2_req_gen0: Signal `dmamux2_req_gen0` selected as request input
2: dmamux2_req_gen1: Signal `dmamux2_req_gen1` selected as request input
3: dmamux2_req_gen2: Signal `dmamux2_req_gen2` selected as request input
4: dmamux2_req_gen3: Signal `dmamux2_req_gen3` selected as request input
5: dmamux2_req_gen4: Signal `dmamux2_req_gen4` selected as request input
6: dmamux2_req_gen5: Signal `dmamux2_req_gen5` selected as request input
7: dmamux2_req_gen6: Signal `dmamux2_req_gen6` selected as request input
8: dmamux2_req_gen7: Signal `dmamux2_req_gen7` selected as request input
9: lpuart1_rx_dma: Signal `lpuart1_rx_dma` selected as request input
10: lpuart1_tx_dma: Signal `lpuart1_tx_dma` selected as request input
11: spi6_rx_dma: Signal `spi6_rx_dma` selected as request input
12: spi6_tx_dma: Signal `spi6_tx_dma` selected as request input
13: i2c4_rx_dma: Signal `i2c4_rx_dma` selected as request input
14: i2c4_tx_dma: Signal `i2c4_tx_dma` selected as request input
15: sai4_a_dma: Signal `sai4_a_dma` selected as request input
16: sai4_b_dma: Signal `sai4_b_dma` selected as request input
17: adc3_dma: Signal `adc3_dma` selected as request input

SOIE

Bit 8: Interrupt enable at synchronization event overrun.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event generation enable/disable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronous operating mode enable/disable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Synchronization event type selector Defines the synchronization event on the selected synchronization input:.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset..

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: Synchronization input selected.

Allowed values:
0: dmamux2_evt0: Signal `dmamux2_evt0` selected as synchronization input
1: dmamux2_evt1: Signal `dmamux2_evt1` selected as synchronization input
2: dmamux2_evt2: Signal `dmamux2_evt2` selected as synchronization input
3: dmamux2_evt3: Signal `dmamux2_evt3` selected as synchronization input
4: dmamux2_evt4: Signal `dmamux2_evt4` selected as synchronization input
5: dmamux2_evt5: Signal `dmamux2_evt5` selected as synchronization input
6: lpuart1_rx_wkup: Signal `lpuart1_rx_wkup` selected as synchronization input
7: lpuart1_tx_wkup: Signal `lpuart1_tx_wkup` selected as synchronization input
8: lptim2_out: Signal `lptim2_out` selected as synchronization input
9: lptim3_out: Signal `lptim3_out` selected as synchronization input
10: i2c4_wkup: Signal `i2c4_wkup` selected as synchronization input
11: spi6_wkup: Signal `spi6_wkup` selected as synchronization input
12: comp1_out: Signal `comp1_out` selected as synchronization input
13: rtc_wkup: Signal `rtc_wkup` selected as synchronization input
14: syscfg_exti0_mux: Signal `syscfg_exti0_mux` selected as synchronization input
15: syscfg_exti2_mux: Signal `syscfg_exti2_mux` selected as synchronization input

CSR

DMAMUX request line multiplexer interrupt channel status register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

Toggle fields

SOF[0]

Bit 0: Synchronization overrun event flag.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[1]

Bit 1: Synchronization overrun event flag.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[2]

Bit 2: Synchronization overrun event flag.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[3]

Bit 3: Synchronization overrun event flag.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[4]

Bit 4: Synchronization overrun event flag.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[5]

Bit 5: Synchronization overrun event flag.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[6]

Bit 6: Synchronization overrun event flag.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[7]

Bit 7: Synchronization overrun event flag.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[8]

Bit 8: Synchronization overrun event flag.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[9]

Bit 9: Synchronization overrun event flag.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[10]

Bit 10: Synchronization overrun event flag.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[11]

Bit 11: Synchronization overrun event flag.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[12]

Bit 12: Synchronization overrun event flag.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[13]

Bit 13: Synchronization overrun event flag.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[14]

Bit 14: Synchronization overrun event flag.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[15]

Bit 15: Synchronization overrun event flag.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

CFR

DMAMUX request line multiplexer interrupt clear flag register

Offset: 0x84, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

Toggle fields

CSOF[0]

Bit 0: Clear synchronization overrun event flag.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[1]

Bit 1: Clear synchronization overrun event flag.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[2]

Bit 2: Clear synchronization overrun event flag.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[3]

Bit 3: Clear synchronization overrun event flag.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[4]

Bit 4: Clear synchronization overrun event flag.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[5]

Bit 5: Clear synchronization overrun event flag.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[6]

Bit 6: Clear synchronization overrun event flag.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[7]

Bit 7: Clear synchronization overrun event flag.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[8]

Bit 8: Clear synchronization overrun event flag.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[9]

Bit 9: Clear synchronization overrun event flag.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[10]

Bit 10: Clear synchronization overrun event flag.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[11]

Bit 11: Clear synchronization overrun event flag.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[12]

Bit 12: Clear synchronization overrun event flag.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[13]

Bit 13: Clear synchronization overrun event flag.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[14]

Bit 14: Clear synchronization overrun event flag.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[15]

Bit 15: Clear synchronization overrun event flag.

Allowed values:
1: Clear: Clear synchronization flag

RG[0]CR

DMAMux - DMA request generator channel x control register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw
GPOL
rw
GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw
SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: DMA request trigger input selected.

Allowed values:
0: dmamux2_evt0: Signal `dmamux2_evt0` selected as trigger input
1: dmamux2_evt1: Signal `dmamux2_evt1` selected as trigger input
2: dmamux2_evt2: Signal `dmamux2_evt2` selected as trigger input
3: dmamux2_evt3: Signal `dmamux2_evt3` selected as trigger input
4: dmamux2_evt4: Signal `dmamux2_evt4` selected as trigger input
5: dmamux2_evt5: Signal `dmamux2_evt5` selected as trigger input
6: dmamux2_evt6: Signal `dmamux2_evt6` selected as trigger input
7: lpuart_rx_wkup: Signal `lpuart_rx_wkup` selected as trigger input
8: lpuart_tx_wkup: Signal `lpuart_tx_wkup` selected as trigger input
9: lptim2_wkup: Signal `lptim2_wkup` selected as trigger input
10: lptim2_out: Signal `lptim2_out` selected as trigger input
11: lptim3_wkup: Signal `lptim3_wkup` selected as trigger input
12: lptim3_out: Signal `lptim3_out` selected as trigger input
13: lptim4_ait: Signal `lptim4_ait` selected as trigger input
14: lptim5_ait: Signal `lptim5_ait` selected as trigger input
15: i2c4_wkup: Signal `i2c4_wkup` selected as trigger input
16: spi6_wkup: Signal `spi6_wkup` selected as trigger input
17: comp1_out: Signal `comp1_out` selected as trigger input
18: comp2_out: Signal `comp2_out` selected as trigger input
19: rtc_wkup: Signal `rtc_wkup` selected as trigger input
20: syscfg_exti0_mux: Signal `syscfg_exti0_mux` selected as trigger input
21: syscfg_exti2_mux: Signal `syscfg_exti2_mux` selected as trigger input
22: i2c4_event_it: Signal `i2c4_event_it` selected as trigger input
23: spi6_it: Signal `spi6_it` selected as trigger input
24: lpuart1_it_t: Signal `lpuart1_it_t` selected as trigger input
25: lpuart1_it_r: Signal `lpuart1_it_r` selected as trigger input
26: adc3_it: Signal `adc3_it` selected as trigger input
27: adc3_awd1: Signal `adc3_awd1` selected as trigger input
28: bdma_ch0_it: Signal `bdma_ch0_it` selected as trigger input
29: bdma_ch1_it: Signal `bdma_ch1_it` selected as trigger input

OIE

Bit 8: Interrupt enable at trigger event overrun.

Allowed values:
0: Disabled: Trigger overrun interrupt disabled
1: Enabled: Trigger overrun interrupt enabled

GE

Bit 16: DMA request generator channel enable/disable.

Allowed values:
0: Disabled: DMA request generation disabled
1: Enabled: DMA request enabled

GPOL

Bits 17-18: DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input.

Allowed values:
0: NoEdge: No event, i.e. no detection nor generation
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

GNBREQ

Bits 19-23: Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset..

Allowed values: 0x0-0x1f

RG[1]CR

DMAMux - DMA request generator channel x control register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw
GPOL
rw
GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw
SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: DMA request trigger input selected.

Allowed values:
0: dmamux2_evt0: Signal `dmamux2_evt0` selected as trigger input
1: dmamux2_evt1: Signal `dmamux2_evt1` selected as trigger input
2: dmamux2_evt2: Signal `dmamux2_evt2` selected as trigger input
3: dmamux2_evt3: Signal `dmamux2_evt3` selected as trigger input
4: dmamux2_evt4: Signal `dmamux2_evt4` selected as trigger input
5: dmamux2_evt5: Signal `dmamux2_evt5` selected as trigger input
6: dmamux2_evt6: Signal `dmamux2_evt6` selected as trigger input
7: lpuart_rx_wkup: Signal `lpuart_rx_wkup` selected as trigger input
8: lpuart_tx_wkup: Signal `lpuart_tx_wkup` selected as trigger input
9: lptim2_wkup: Signal `lptim2_wkup` selected as trigger input
10: lptim2_out: Signal `lptim2_out` selected as trigger input
11: lptim3_wkup: Signal `lptim3_wkup` selected as trigger input
12: lptim3_out: Signal `lptim3_out` selected as trigger input
13: lptim4_ait: Signal `lptim4_ait` selected as trigger input
14: lptim5_ait: Signal `lptim5_ait` selected as trigger input
15: i2c4_wkup: Signal `i2c4_wkup` selected as trigger input
16: spi6_wkup: Signal `spi6_wkup` selected as trigger input
17: comp1_out: Signal `comp1_out` selected as trigger input
18: comp2_out: Signal `comp2_out` selected as trigger input
19: rtc_wkup: Signal `rtc_wkup` selected as trigger input
20: syscfg_exti0_mux: Signal `syscfg_exti0_mux` selected as trigger input
21: syscfg_exti2_mux: Signal `syscfg_exti2_mux` selected as trigger input
22: i2c4_event_it: Signal `i2c4_event_it` selected as trigger input
23: spi6_it: Signal `spi6_it` selected as trigger input
24: lpuart1_it_t: Signal `lpuart1_it_t` selected as trigger input
25: lpuart1_it_r: Signal `lpuart1_it_r` selected as trigger input
26: adc3_it: Signal `adc3_it` selected as trigger input
27: adc3_awd1: Signal `adc3_awd1` selected as trigger input
28: bdma_ch0_it: Signal `bdma_ch0_it` selected as trigger input
29: bdma_ch1_it: Signal `bdma_ch1_it` selected as trigger input

OIE

Bit 8: Interrupt enable at trigger event overrun.

Allowed values:
0: Disabled: Trigger overrun interrupt disabled
1: Enabled: Trigger overrun interrupt enabled

GE

Bit 16: DMA request generator channel enable/disable.

Allowed values:
0: Disabled: DMA request generation disabled
1: Enabled: DMA request enabled

GPOL

Bits 17-18: DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input.

Allowed values:
0: NoEdge: No event, i.e. no detection nor generation
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

GNBREQ

Bits 19-23: Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset..

Allowed values: 0x0-0x1f

RG[2]CR

DMAMux - DMA request generator channel x control register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw
GPOL
rw
GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw
SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: DMA request trigger input selected.

Allowed values:
0: dmamux2_evt0: Signal `dmamux2_evt0` selected as trigger input
1: dmamux2_evt1: Signal `dmamux2_evt1` selected as trigger input
2: dmamux2_evt2: Signal `dmamux2_evt2` selected as trigger input
3: dmamux2_evt3: Signal `dmamux2_evt3` selected as trigger input
4: dmamux2_evt4: Signal `dmamux2_evt4` selected as trigger input
5: dmamux2_evt5: Signal `dmamux2_evt5` selected as trigger input
6: dmamux2_evt6: Signal `dmamux2_evt6` selected as trigger input
7: lpuart_rx_wkup: Signal `lpuart_rx_wkup` selected as trigger input
8: lpuart_tx_wkup: Signal `lpuart_tx_wkup` selected as trigger input
9: lptim2_wkup: Signal `lptim2_wkup` selected as trigger input
10: lptim2_out: Signal `lptim2_out` selected as trigger input
11: lptim3_wkup: Signal `lptim3_wkup` selected as trigger input
12: lptim3_out: Signal `lptim3_out` selected as trigger input
13: lptim4_ait: Signal `lptim4_ait` selected as trigger input
14: lptim5_ait: Signal `lptim5_ait` selected as trigger input
15: i2c4_wkup: Signal `i2c4_wkup` selected as trigger input
16: spi6_wkup: Signal `spi6_wkup` selected as trigger input
17: comp1_out: Signal `comp1_out` selected as trigger input
18: comp2_out: Signal `comp2_out` selected as trigger input
19: rtc_wkup: Signal `rtc_wkup` selected as trigger input
20: syscfg_exti0_mux: Signal `syscfg_exti0_mux` selected as trigger input
21: syscfg_exti2_mux: Signal `syscfg_exti2_mux` selected as trigger input
22: i2c4_event_it: Signal `i2c4_event_it` selected as trigger input
23: spi6_it: Signal `spi6_it` selected as trigger input
24: lpuart1_it_t: Signal `lpuart1_it_t` selected as trigger input
25: lpuart1_it_r: Signal `lpuart1_it_r` selected as trigger input
26: adc3_it: Signal `adc3_it` selected as trigger input
27: adc3_awd1: Signal `adc3_awd1` selected as trigger input
28: bdma_ch0_it: Signal `bdma_ch0_it` selected as trigger input
29: bdma_ch1_it: Signal `bdma_ch1_it` selected as trigger input

OIE

Bit 8: Interrupt enable at trigger event overrun.

Allowed values:
0: Disabled: Trigger overrun interrupt disabled
1: Enabled: Trigger overrun interrupt enabled

GE

Bit 16: DMA request generator channel enable/disable.

Allowed values:
0: Disabled: DMA request generation disabled
1: Enabled: DMA request enabled

GPOL

Bits 17-18: DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input.

Allowed values:
0: NoEdge: No event, i.e. no detection nor generation
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

GNBREQ

Bits 19-23: Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset..

Allowed values: 0x0-0x1f

RG[3]CR

DMAMux - DMA request generator channel x control register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw
GPOL
rw
GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw
SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: DMA request trigger input selected.

Allowed values:
0: dmamux2_evt0: Signal `dmamux2_evt0` selected as trigger input
1: dmamux2_evt1: Signal `dmamux2_evt1` selected as trigger input
2: dmamux2_evt2: Signal `dmamux2_evt2` selected as trigger input
3: dmamux2_evt3: Signal `dmamux2_evt3` selected as trigger input
4: dmamux2_evt4: Signal `dmamux2_evt4` selected as trigger input
5: dmamux2_evt5: Signal `dmamux2_evt5` selected as trigger input
6: dmamux2_evt6: Signal `dmamux2_evt6` selected as trigger input
7: lpuart_rx_wkup: Signal `lpuart_rx_wkup` selected as trigger input
8: lpuart_tx_wkup: Signal `lpuart_tx_wkup` selected as trigger input
9: lptim2_wkup: Signal `lptim2_wkup` selected as trigger input
10: lptim2_out: Signal `lptim2_out` selected as trigger input
11: lptim3_wkup: Signal `lptim3_wkup` selected as trigger input
12: lptim3_out: Signal `lptim3_out` selected as trigger input
13: lptim4_ait: Signal `lptim4_ait` selected as trigger input
14: lptim5_ait: Signal `lptim5_ait` selected as trigger input
15: i2c4_wkup: Signal `i2c4_wkup` selected as trigger input
16: spi6_wkup: Signal `spi6_wkup` selected as trigger input
17: comp1_out: Signal `comp1_out` selected as trigger input
18: comp2_out: Signal `comp2_out` selected as trigger input
19: rtc_wkup: Signal `rtc_wkup` selected as trigger input
20: syscfg_exti0_mux: Signal `syscfg_exti0_mux` selected as trigger input
21: syscfg_exti2_mux: Signal `syscfg_exti2_mux` selected as trigger input
22: i2c4_event_it: Signal `i2c4_event_it` selected as trigger input
23: spi6_it: Signal `spi6_it` selected as trigger input
24: lpuart1_it_t: Signal `lpuart1_it_t` selected as trigger input
25: lpuart1_it_r: Signal `lpuart1_it_r` selected as trigger input
26: adc3_it: Signal `adc3_it` selected as trigger input
27: adc3_awd1: Signal `adc3_awd1` selected as trigger input
28: bdma_ch0_it: Signal `bdma_ch0_it` selected as trigger input
29: bdma_ch1_it: Signal `bdma_ch1_it` selected as trigger input

OIE

Bit 8: Interrupt enable at trigger event overrun.

Allowed values:
0: Disabled: Trigger overrun interrupt disabled
1: Enabled: Trigger overrun interrupt enabled

GE

Bit 16: DMA request generator channel enable/disable.

Allowed values:
0: Disabled: DMA request generation disabled
1: Enabled: DMA request enabled

GPOL

Bits 17-18: DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input.

Allowed values:
0: NoEdge: No event, i.e. no detection nor generation
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

GNBREQ

Bits 19-23: Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset..

Allowed values: 0x0-0x1f

RG[4]CR

DMAMux - DMA request generator channel x control register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw
GPOL
rw
GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw
SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: DMA request trigger input selected.

Allowed values:
0: dmamux2_evt0: Signal `dmamux2_evt0` selected as trigger input
1: dmamux2_evt1: Signal `dmamux2_evt1` selected as trigger input
2: dmamux2_evt2: Signal `dmamux2_evt2` selected as trigger input
3: dmamux2_evt3: Signal `dmamux2_evt3` selected as trigger input
4: dmamux2_evt4: Signal `dmamux2_evt4` selected as trigger input
5: dmamux2_evt5: Signal `dmamux2_evt5` selected as trigger input
6: dmamux2_evt6: Signal `dmamux2_evt6` selected as trigger input
7: lpuart_rx_wkup: Signal `lpuart_rx_wkup` selected as trigger input
8: lpuart_tx_wkup: Signal `lpuart_tx_wkup` selected as trigger input
9: lptim2_wkup: Signal `lptim2_wkup` selected as trigger input
10: lptim2_out: Signal `lptim2_out` selected as trigger input
11: lptim3_wkup: Signal `lptim3_wkup` selected as trigger input
12: lptim3_out: Signal `lptim3_out` selected as trigger input
13: lptim4_ait: Signal `lptim4_ait` selected as trigger input
14: lptim5_ait: Signal `lptim5_ait` selected as trigger input
15: i2c4_wkup: Signal `i2c4_wkup` selected as trigger input
16: spi6_wkup: Signal `spi6_wkup` selected as trigger input
17: comp1_out: Signal `comp1_out` selected as trigger input
18: comp2_out: Signal `comp2_out` selected as trigger input
19: rtc_wkup: Signal `rtc_wkup` selected as trigger input
20: syscfg_exti0_mux: Signal `syscfg_exti0_mux` selected as trigger input
21: syscfg_exti2_mux: Signal `syscfg_exti2_mux` selected as trigger input
22: i2c4_event_it: Signal `i2c4_event_it` selected as trigger input
23: spi6_it: Signal `spi6_it` selected as trigger input
24: lpuart1_it_t: Signal `lpuart1_it_t` selected as trigger input
25: lpuart1_it_r: Signal `lpuart1_it_r` selected as trigger input
26: adc3_it: Signal `adc3_it` selected as trigger input
27: adc3_awd1: Signal `adc3_awd1` selected as trigger input
28: bdma_ch0_it: Signal `bdma_ch0_it` selected as trigger input
29: bdma_ch1_it: Signal `bdma_ch1_it` selected as trigger input

OIE

Bit 8: Interrupt enable at trigger event overrun.

Allowed values:
0: Disabled: Trigger overrun interrupt disabled
1: Enabled: Trigger overrun interrupt enabled

GE

Bit 16: DMA request generator channel enable/disable.

Allowed values:
0: Disabled: DMA request generation disabled
1: Enabled: DMA request enabled

GPOL

Bits 17-18: DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input.

Allowed values:
0: NoEdge: No event, i.e. no detection nor generation
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

GNBREQ

Bits 19-23: Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset..

Allowed values: 0x0-0x1f

RG[5]CR

DMAMux - DMA request generator channel x control register

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw
GPOL
rw
GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw
SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: DMA request trigger input selected.

Allowed values:
0: dmamux2_evt0: Signal `dmamux2_evt0` selected as trigger input
1: dmamux2_evt1: Signal `dmamux2_evt1` selected as trigger input
2: dmamux2_evt2: Signal `dmamux2_evt2` selected as trigger input
3: dmamux2_evt3: Signal `dmamux2_evt3` selected as trigger input
4: dmamux2_evt4: Signal `dmamux2_evt4` selected as trigger input
5: dmamux2_evt5: Signal `dmamux2_evt5` selected as trigger input
6: dmamux2_evt6: Signal `dmamux2_evt6` selected as trigger input
7: lpuart_rx_wkup: Signal `lpuart_rx_wkup` selected as trigger input
8: lpuart_tx_wkup: Signal `lpuart_tx_wkup` selected as trigger input
9: lptim2_wkup: Signal `lptim2_wkup` selected as trigger input
10: lptim2_out: Signal `lptim2_out` selected as trigger input
11: lptim3_wkup: Signal `lptim3_wkup` selected as trigger input
12: lptim3_out: Signal `lptim3_out` selected as trigger input
13: lptim4_ait: Signal `lptim4_ait` selected as trigger input
14: lptim5_ait: Signal `lptim5_ait` selected as trigger input
15: i2c4_wkup: Signal `i2c4_wkup` selected as trigger input
16: spi6_wkup: Signal `spi6_wkup` selected as trigger input
17: comp1_out: Signal `comp1_out` selected as trigger input
18: comp2_out: Signal `comp2_out` selected as trigger input
19: rtc_wkup: Signal `rtc_wkup` selected as trigger input
20: syscfg_exti0_mux: Signal `syscfg_exti0_mux` selected as trigger input
21: syscfg_exti2_mux: Signal `syscfg_exti2_mux` selected as trigger input
22: i2c4_event_it: Signal `i2c4_event_it` selected as trigger input
23: spi6_it: Signal `spi6_it` selected as trigger input
24: lpuart1_it_t: Signal `lpuart1_it_t` selected as trigger input
25: lpuart1_it_r: Signal `lpuart1_it_r` selected as trigger input
26: adc3_it: Signal `adc3_it` selected as trigger input
27: adc3_awd1: Signal `adc3_awd1` selected as trigger input
28: bdma_ch0_it: Signal `bdma_ch0_it` selected as trigger input
29: bdma_ch1_it: Signal `bdma_ch1_it` selected as trigger input

OIE

Bit 8: Interrupt enable at trigger event overrun.

Allowed values:
0: Disabled: Trigger overrun interrupt disabled
1: Enabled: Trigger overrun interrupt enabled

GE

Bit 16: DMA request generator channel enable/disable.

Allowed values:
0: Disabled: DMA request generation disabled
1: Enabled: DMA request enabled

GPOL

Bits 17-18: DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input.

Allowed values:
0: NoEdge: No event, i.e. no detection nor generation
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

GNBREQ

Bits 19-23: Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset..

Allowed values: 0x0-0x1f

RG[6]CR

DMAMux - DMA request generator channel x control register

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw
GPOL
rw
GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw
SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: DMA request trigger input selected.

Allowed values:
0: dmamux2_evt0: Signal `dmamux2_evt0` selected as trigger input
1: dmamux2_evt1: Signal `dmamux2_evt1` selected as trigger input
2: dmamux2_evt2: Signal `dmamux2_evt2` selected as trigger input
3: dmamux2_evt3: Signal `dmamux2_evt3` selected as trigger input
4: dmamux2_evt4: Signal `dmamux2_evt4` selected as trigger input
5: dmamux2_evt5: Signal `dmamux2_evt5` selected as trigger input
6: dmamux2_evt6: Signal `dmamux2_evt6` selected as trigger input
7: lpuart_rx_wkup: Signal `lpuart_rx_wkup` selected as trigger input
8: lpuart_tx_wkup: Signal `lpuart_tx_wkup` selected as trigger input
9: lptim2_wkup: Signal `lptim2_wkup` selected as trigger input
10: lptim2_out: Signal `lptim2_out` selected as trigger input
11: lptim3_wkup: Signal `lptim3_wkup` selected as trigger input
12: lptim3_out: Signal `lptim3_out` selected as trigger input
13: lptim4_ait: Signal `lptim4_ait` selected as trigger input
14: lptim5_ait: Signal `lptim5_ait` selected as trigger input
15: i2c4_wkup: Signal `i2c4_wkup` selected as trigger input
16: spi6_wkup: Signal `spi6_wkup` selected as trigger input
17: comp1_out: Signal `comp1_out` selected as trigger input
18: comp2_out: Signal `comp2_out` selected as trigger input
19: rtc_wkup: Signal `rtc_wkup` selected as trigger input
20: syscfg_exti0_mux: Signal `syscfg_exti0_mux` selected as trigger input
21: syscfg_exti2_mux: Signal `syscfg_exti2_mux` selected as trigger input
22: i2c4_event_it: Signal `i2c4_event_it` selected as trigger input
23: spi6_it: Signal `spi6_it` selected as trigger input
24: lpuart1_it_t: Signal `lpuart1_it_t` selected as trigger input
25: lpuart1_it_r: Signal `lpuart1_it_r` selected as trigger input
26: adc3_it: Signal `adc3_it` selected as trigger input
27: adc3_awd1: Signal `adc3_awd1` selected as trigger input
28: bdma_ch0_it: Signal `bdma_ch0_it` selected as trigger input
29: bdma_ch1_it: Signal `bdma_ch1_it` selected as trigger input

OIE

Bit 8: Interrupt enable at trigger event overrun.

Allowed values:
0: Disabled: Trigger overrun interrupt disabled
1: Enabled: Trigger overrun interrupt enabled

GE

Bit 16: DMA request generator channel enable/disable.

Allowed values:
0: Disabled: DMA request generation disabled
1: Enabled: DMA request enabled

GPOL

Bits 17-18: DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input.

Allowed values:
0: NoEdge: No event, i.e. no detection nor generation
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

GNBREQ

Bits 19-23: Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset..

Allowed values: 0x0-0x1f

RG[7]CR

DMAMux - DMA request generator channel x control register

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw
GPOL
rw
GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw
SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: DMA request trigger input selected.

Allowed values:
0: dmamux2_evt0: Signal `dmamux2_evt0` selected as trigger input
1: dmamux2_evt1: Signal `dmamux2_evt1` selected as trigger input
2: dmamux2_evt2: Signal `dmamux2_evt2` selected as trigger input
3: dmamux2_evt3: Signal `dmamux2_evt3` selected as trigger input
4: dmamux2_evt4: Signal `dmamux2_evt4` selected as trigger input
5: dmamux2_evt5: Signal `dmamux2_evt5` selected as trigger input
6: dmamux2_evt6: Signal `dmamux2_evt6` selected as trigger input
7: lpuart_rx_wkup: Signal `lpuart_rx_wkup` selected as trigger input
8: lpuart_tx_wkup: Signal `lpuart_tx_wkup` selected as trigger input
9: lptim2_wkup: Signal `lptim2_wkup` selected as trigger input
10: lptim2_out: Signal `lptim2_out` selected as trigger input
11: lptim3_wkup: Signal `lptim3_wkup` selected as trigger input
12: lptim3_out: Signal `lptim3_out` selected as trigger input
13: lptim4_ait: Signal `lptim4_ait` selected as trigger input
14: lptim5_ait: Signal `lptim5_ait` selected as trigger input
15: i2c4_wkup: Signal `i2c4_wkup` selected as trigger input
16: spi6_wkup: Signal `spi6_wkup` selected as trigger input
17: comp1_out: Signal `comp1_out` selected as trigger input
18: comp2_out: Signal `comp2_out` selected as trigger input
19: rtc_wkup: Signal `rtc_wkup` selected as trigger input
20: syscfg_exti0_mux: Signal `syscfg_exti0_mux` selected as trigger input
21: syscfg_exti2_mux: Signal `syscfg_exti2_mux` selected as trigger input
22: i2c4_event_it: Signal `i2c4_event_it` selected as trigger input
23: spi6_it: Signal `spi6_it` selected as trigger input
24: lpuart1_it_t: Signal `lpuart1_it_t` selected as trigger input
25: lpuart1_it_r: Signal `lpuart1_it_r` selected as trigger input
26: adc3_it: Signal `adc3_it` selected as trigger input
27: adc3_awd1: Signal `adc3_awd1` selected as trigger input
28: bdma_ch0_it: Signal `bdma_ch0_it` selected as trigger input
29: bdma_ch1_it: Signal `bdma_ch1_it` selected as trigger input

OIE

Bit 8: Interrupt enable at trigger event overrun.

Allowed values:
0: Disabled: Trigger overrun interrupt disabled
1: Enabled: Trigger overrun interrupt enabled

GE

Bit 16: DMA request generator channel enable/disable.

Allowed values:
0: Disabled: DMA request generation disabled
1: Enabled: DMA request enabled

GPOL

Bits 17-18: DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input.

Allowed values:
0: NoEdge: No event, i.e. no detection nor generation
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

GNBREQ

Bits 19-23: Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset..

Allowed values: 0x0-0x1f

RGSR

DMAMux - DMA request generator status register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF[7]
r
OF[6]
r
OF[5]
r
OF[4]
r
OF[3]
r
OF[2]
r
OF[1]
r
OF[0]
r
Toggle fields

OF[0]

Bit 0: Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register..

Allowed values:
0: NoTrigger: No new trigger event occured on DMA request generator channel x, before the request counter underrun
1: Trigger: New trigger event occured on DMA request generator channel x, before the request counter underrun

OF[1]

Bit 1: Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register..

Allowed values:
0: NoTrigger: No new trigger event occured on DMA request generator channel x, before the request counter underrun
1: Trigger: New trigger event occured on DMA request generator channel x, before the request counter underrun

OF[2]

Bit 2: Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register..

Allowed values:
0: NoTrigger: No new trigger event occured on DMA request generator channel x, before the request counter underrun
1: Trigger: New trigger event occured on DMA request generator channel x, before the request counter underrun

OF[3]

Bit 3: Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register..

Allowed values:
0: NoTrigger: No new trigger event occured on DMA request generator channel x, before the request counter underrun
1: Trigger: New trigger event occured on DMA request generator channel x, before the request counter underrun

OF[4]

Bit 4: Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register..

Allowed values:
0: NoTrigger: No new trigger event occured on DMA request generator channel x, before the request counter underrun
1: Trigger: New trigger event occured on DMA request generator channel x, before the request counter underrun

OF[5]

Bit 5: Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register..

Allowed values:
0: NoTrigger: No new trigger event occured on DMA request generator channel x, before the request counter underrun
1: Trigger: New trigger event occured on DMA request generator channel x, before the request counter underrun

OF[6]

Bit 6: Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register..

Allowed values:
0: NoTrigger: No new trigger event occured on DMA request generator channel x, before the request counter underrun
1: Trigger: New trigger event occured on DMA request generator channel x, before the request counter underrun

OF[7]

Bit 7: Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register..

Allowed values:
0: NoTrigger: No new trigger event occured on DMA request generator channel x, before the request counter underrun
1: Trigger: New trigger event occured on DMA request generator channel x, before the request counter underrun

RGCFR

DMAMux - DMA request generator clear flag register

Offset: 0x144, size: 32, reset: 0x00000000, access: write-only

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COF[7]
w1c
COF[6]
w1c
COF[5]
w1c
COF[4]
w1c
COF[3]
w1c
COF[2]
w1c
COF[1]
w1c
COF[0]
w1c
Toggle fields

COF[0]

Bit 0: Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register..

Allowed values:
1: Clear: Clear overrun flag

COF[1]

Bit 1: Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register..

Allowed values:
1: Clear: Clear overrun flag

COF[2]

Bit 2: Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register..

Allowed values:
1: Clear: Clear overrun flag

COF[3]

Bit 3: Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register..

Allowed values:
1: Clear: Clear overrun flag

COF[4]

Bit 4: Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register..

Allowed values:
1: Clear: Clear overrun flag

COF[5]

Bit 5: Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register..

Allowed values:
1: Clear: Clear overrun flag

COF[6]

Bit 6: Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register..

Allowed values:
1: Clear: Clear overrun flag

COF[7]

Bit 7: Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register..

Allowed values:
1: Clear: Clear overrun flag

EXTI

0x58000000: External interrupt/event controller

344/344 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 RTSR1
0x4 FTSR1
0x8 SWIER1
0xc D3PMR1
0x10 D3PCR1L
0x14 D3PCR1H
0x20 RTSR2
0x24 FTSR2
0x28 SWIER2
0x2c D3PMR2
0x30 D3PCR2L
0x34 D3PCR2H
0x40 RTSR3
0x44 FTSR3
0x48 SWIER3
0x4c D3PMR3
0x54 D3PCR3H
0x80 CPUIMR1
0x84 CPUEMR1
0x88 CPUPR1
0x90 CPUIMR2
0x94 CPUEMR2
0x98 CPUPR2
0xa0 CPUIMR3
0xa4 CPUEMR3
0xa8 CPUPR3
Toggle registers

RTSR1

EXTI rising trigger selection register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TR21
rw
TR20
rw
TR19
rw
TR18
rw
TR17
rw
TR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TR15
rw
TR14
rw
TR13
rw
TR12
rw
TR11
rw
TR10
rw
TR9
rw
TR8
rw
TR7
rw
TR6
rw
TR5
rw
TR4
rw
TR3
rw
TR2
rw
TR1
rw
TR0
rw
Toggle fields

TR0

Bit 0: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR1

Bit 1: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR2

Bit 2: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR3

Bit 3: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR4

Bit 4: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR5

Bit 5: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR6

Bit 6: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR7

Bit 7: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR8

Bit 8: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR9

Bit 9: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR10

Bit 10: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR11

Bit 11: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR12

Bit 12: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR13

Bit 13: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR14

Bit 14: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR15

Bit 15: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR16

Bit 16: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR17

Bit 17: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR18

Bit 18: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR19

Bit 19: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR20

Bit 20: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR21

Bit 21: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

FTSR1

EXTI falling trigger selection register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TR21
rw
TR20
rw
TR19
rw
TR18
rw
TR17
rw
TR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TR15
rw
TR14
rw
TR13
rw
TR12
rw
TR11
rw
TR10
rw
TR9
rw
TR8
rw
TR7
rw
TR6
rw
TR5
rw
TR4
rw
TR3
rw
TR2
rw
TR1
rw
TR0
rw
Toggle fields

TR0

Bit 0: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR1

Bit 1: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR2

Bit 2: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR3

Bit 3: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR4

Bit 4: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR5

Bit 5: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR6

Bit 6: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR7

Bit 7: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR8

Bit 8: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR9

Bit 9: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR10

Bit 10: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR11

Bit 11: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR12

Bit 12: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR13

Bit 13: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR14

Bit 14: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR15

Bit 15: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR16

Bit 16: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR17

Bit 17: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR18

Bit 18: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR19

Bit 19: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR20

Bit 20: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR21

Bit 21: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

SWIER1

EXTI software interrupt event register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWIER21
rw
SWIER20
rw
SWIER19
rw
SWIER18
rw
SWIER17
rw
SWIER16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWIER15
rw
SWIER14
rw
SWIER13
rw
SWIER12
rw
SWIER11
rw
SWIER10
rw
SWIER9
rw
SWIER8
rw
SWIER7
rw
SWIER6
rw
SWIER5
rw
SWIER4
rw
SWIER3
rw
SWIER2
rw
SWIER1
rw
SWIER0
rw
Toggle fields

SWIER0

Bit 0: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER1

Bit 1: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER2

Bit 2: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER3

Bit 3: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER4

Bit 4: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER5

Bit 5: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER6

Bit 6: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER7

Bit 7: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER8

Bit 8: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER9

Bit 9: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER10

Bit 10: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER11

Bit 11: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER12

Bit 12: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER13

Bit 13: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER14

Bit 14: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER15

Bit 15: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER16

Bit 16: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER17

Bit 17: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER18

Bit 18: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER19

Bit 19: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER20

Bit 20: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

SWIER21

Bit 21: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
1: Pend: Generates an interrupt request

D3PMR1

EXTI D3 pending mask register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MR25
rw
MR21
rw
MR20
rw
MR19
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR15
rw
MR14
rw
MR13
rw
MR12
rw
MR11
rw
MR10
rw
MR9
rw
MR8
rw
MR7
rw
MR6
rw
MR5
rw
MR4
rw
MR3
rw
MR2
rw
MR1
rw
MR0
rw
Toggle fields

MR0

Bit 0: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR1

Bit 1: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR2

Bit 2: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR3

Bit 3: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR4

Bit 4: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR5

Bit 5: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR6

Bit 6: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR7

Bit 7: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR8

Bit 8: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR9

Bit 9: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR10

Bit 10: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR11

Bit 11: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR12

Bit 12: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR13

Bit 13: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR14

Bit 14: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR15

Bit 15: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR19

Bit 19: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR20

Bit 20: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR21

Bit 21: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR25

Bit 25: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

D3PCR1L

EXTI D3 pending clear selection register low

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCS15
rw
PCS14
rw
PCS13
rw
PCS12
rw
PCS11
rw
PCS10
rw
PCS9
rw
PCS8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCS7
rw
PCS6
rw
PCS5
rw
PCS4
rw
PCS3
rw
PCS2
rw
PCS1
rw
PCS0
rw
Toggle fields

PCS0

Bits 0-1: D3 Pending request clear input signal selection on Event input x = truncate (n/2).

Allowed values:
0: DMA_CH6: DMA ch6 event selected as D3 domain pendclear source
1: DMA_CH7: DMA ch7 event selected as D3 domain pendclear source
2: LPTIM4: LPTIM4 out selected as D3 domain pendclear source
3: LPTIM5: LPTIM5 out selected as D3 domain pendclear source

PCS1

Bits 2-3: D3 Pending request clear input signal selection on Event input x = truncate (n/2).

Allowed values:
0: DMA_CH6: DMA ch6 event selected as D3 domain pendclear source
1: DMA_CH7: DMA ch7 event selected as D3 domain pendclear source
2: LPTIM4: LPTIM4 out selected as D3 domain pendclear source
3: LPTIM5: LPTIM5 out selected as D3 domain pendclear source

PCS2

Bits 4-5: D3 Pending request clear input signal selection on Event input x = truncate (n/2).

Allowed values:
0: DMA_CH6: DMA ch6 event selected as D3 domain pendclear source
1: DMA_CH7: DMA ch7 event selected as D3 domain pendclear source
2: LPTIM4: LPTIM4 out selected as D3 domain pendclear source
3: LPTIM5: LPTIM5 out selected as D3 domain pendclear source

PCS3

Bits 6-7: D3 Pending request clear input signal selection on Event input x = truncate (n/2).

Allowed values:
0: DMA_CH6: DMA ch6 event selected as D3 domain pendclear source
1: DMA_CH7: DMA ch7 event selected as D3 domain pendclear source
2: LPTIM4: LPTIM4 out selected as D3 domain pendclear source
3: LPTIM5: LPTIM5 out selected as D3 domain pendclear source

PCS4

Bits 8-9: D3 Pending request clear input signal selection on Event input x = truncate (n/2).

Allowed values:
0: DMA_CH6: DMA ch6 event selected as D3 domain pendclear source
1: DMA_CH7: DMA ch7 event selected as D3 domain pendclear source
2: LPTIM4: LPTIM4 out selected as D3 domain pendclear source
3: LPTIM5: LPTIM5 out selected as D3 domain pendclear source

PCS5

Bits 10-11: D3 Pending request clear input signal selection on Event input x = truncate (n/2).

Allowed values:
0: DMA_CH6: DMA ch6 event selected as D3 domain pendclear source
1: DMA_CH7: DMA ch7 event selected as D3 domain pendclear source
2: LPTIM4: LPTIM4 out selected as D3 domain pendclear source
3: LPTIM5: LPTIM5 out selected as D3 domain pendclear source

PCS6

Bits 12-13: D3 Pending request clear input signal selection on Event input x = truncate (n/2).

Allowed values:
0: DMA_CH6: DMA ch6 event selected as D3 domain pendclear source
1: DMA_CH7: DMA ch7 event selected as D3 domain pendclear source
2: LPTIM4: LPTIM4 out selected as D3 domain pendclear source
3: LPTIM5: LPTIM5 out selected as D3 domain pendclear source

PCS7

Bits 14-15: D3 Pending request clear input signal selection on Event input x = truncate (n/2).

Allowed values:
0: DMA_CH6: DMA ch6 event selected as D3 domain pendclear source
1: DMA_CH7: DMA ch7 event selected as D3 domain pendclear source
2: LPTIM4: LPTIM4 out selected as D3 domain pendclear source
3: LPTIM5: LPTIM5 out selected as D3 domain pendclear source

PCS8

Bits 16-17: D3 Pending request clear input signal selection on Event input x = truncate (n/2).

Allowed values:
0: DMA_CH6: DMA ch6 event selected as D3 domain pendclear source
1: DMA_CH7: DMA ch7 event selected as D3 domain pendclear source
2: LPTIM4: LPTIM4 out selected as D3 domain pendclear source
3: LPTIM5: LPTIM5 out selected as D3 domain pendclear source

PCS9

Bits 18-19: D3 Pending request clear input signal selection on Event input x = truncate (n/2).

Allowed values:
0: DMA_CH6: DMA ch6 event selected as D3 domain pendclear source
1: DMA_CH7: DMA ch7 event selected as D3 domain pendclear source
2: LPTIM4: LPTIM4 out selected as D3 domain pendclear source
3: LPTIM5: LPTIM5 out selected as D3 domain pendclear source

PCS10

Bits 20-21: D3 Pending request clear input signal selection on Event input x = truncate (n/2).

Allowed values:
0: DMA_CH6: DMA ch6 event selected as D3 domain pendclear source
1: DMA_CH7: DMA ch7 event selected as D3 domain pendclear source
2: LPTIM4: LPTIM4 out selected as D3 domain pendclear source
3: LPTIM5: LPTIM5 out selected as D3 domain pendclear source

PCS11

Bits 22-23: D3 Pending request clear input signal selection on Event input x = truncate (n/2).

Allowed values:
0: DMA_CH6: DMA ch6 event selected as D3 domain pendclear source
1: DMA_CH7: DMA ch7 event selected as D3 domain pendclear source
2: LPTIM4: LPTIM4 out selected as D3 domain pendclear source
3: LPTIM5: LPTIM5 out selected as D3 domain pendclear source

PCS12

Bits 24-25: D3 Pending request clear input signal selection on Event input x = truncate (n/2).

Allowed values:
0: DMA_CH6: DMA ch6 event selected as D3 domain pendclear source
1: DMA_CH7: DMA ch7 event selected as D3 domain pendclear source
2: LPTIM4: LPTIM4 out selected as D3 domain pendclear source
3: LPTIM5: LPTIM5 out selected as D3 domain pendclear source

PCS13

Bits 26-27: D3 Pending request clear input signal selection on Event input x = truncate (n/2).

Allowed values:
0: DMA_CH6: DMA ch6 event selected as D3 domain pendclear source
1: DMA_CH7: DMA ch7 event selected as D3 domain pendclear source
2: LPTIM4: LPTIM4 out selected as D3 domain pendclear source
3: LPTIM5: LPTIM5 out selected as D3 domain pendclear source

PCS14

Bits 28-29: D3 Pending request clear input signal selection on Event input x = truncate (n/2).

Allowed values:
0: DMA_CH6: DMA ch6 event selected as D3 domain pendclear source
1: DMA_CH7: DMA ch7 event selected as D3 domain pendclear source
2: LPTIM4: LPTIM4 out selected as D3 domain pendclear source
3: LPTIM5: LPTIM5 out selected as D3 domain pendclear source

PCS15

Bits 30-31: D3 Pending request clear input signal selection on Event input x = truncate (n/2).

Allowed values:
0: DMA_CH6: DMA ch6 event selected as D3 domain pendclear source
1: DMA_CH7: DMA ch7 event selected as D3 domain pendclear source
2: LPTIM4: LPTIM4 out selected as D3 domain pendclear source
3: LPTIM5: LPTIM5 out selected as D3 domain pendclear source

D3PCR1H

EXTI D3 pending clear selection register high

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCS25
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCS21
rw
PCS20
rw
PCS19
rw
Toggle fields

PCS19

Bits 6-7: D3 Pending request clear input signal selection on Event input x = truncate ((n+32)/2).

Allowed values:
0: DMA_CH6: DMA ch6 event selected as D3 domain pendclear source
1: DMA_CH7: DMA ch7 event selected as D3 domain pendclear source
2: LPTIM4: LPTIM4 out selected as D3 domain pendclear source
3: LPTIM5: LPTIM5 out selected as D3 domain pendclear source

PCS20

Bits 8-9: D3 Pending request clear input signal selection on Event input x = truncate ((n+32)/2).

Allowed values:
0: DMA_CH6: DMA ch6 event selected as D3 domain pendclear source
1: DMA_CH7: DMA ch7 event selected as D3 domain pendclear source
2: LPTIM4: LPTIM4 out selected as D3 domain pendclear source
3: LPTIM5: LPTIM5 out selected as D3 domain pendclear source

PCS21

Bits 10-11: D3 Pending request clear input signal selection on Event input x = truncate ((n+32)/2).

Allowed values:
0: DMA_CH6: DMA ch6 event selected as D3 domain pendclear source
1: DMA_CH7: DMA ch7 event selected as D3 domain pendclear source
2: LPTIM4: LPTIM4 out selected as D3 domain pendclear source
3: LPTIM5: LPTIM5 out selected as D3 domain pendclear source

PCS25

Bits 18-19: D3 Pending request clear input signal selection on Event input x = truncate ((n+32)/2).

Allowed values:
0: DMA_CH6: DMA ch6 event selected as D3 domain pendclear source
1: DMA_CH7: DMA ch7 event selected as D3 domain pendclear source
2: LPTIM4: LPTIM4 out selected as D3 domain pendclear source
3: LPTIM5: LPTIM5 out selected as D3 domain pendclear source

RTSR2

EXTI rising trigger selection register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TR51
rw
TR49
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

TR49

Bit 17: Rising trigger event configuration bit of Configurable Event input x+32.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR51

Bit 19: Rising trigger event configuration bit of Configurable Event input x+32.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

FTSR2

EXTI falling trigger selection register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TR51
rw
TR49
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

TR49

Bit 17: Falling trigger event configuration bit of Configurable Event input x+32.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR51

Bit 19: Falling trigger event configuration bit of Configurable Event input x+32.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

SWIER2

EXTI software interrupt event register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWIER51
rw
SWIER49
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

SWIER49

Bit 17: Software interrupt on line x+32.

Allowed values:
1: Pend: Generates an interrupt request

SWIER51

Bit 19: Software interrupt on line x+32.

Allowed values:
1: Pend: Generates an interrupt request

D3PMR2

EXTI D3 pending mask register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MR53
rw
MR52
rw
MR51
rw
MR50
rw
MR49
rw
MR48
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR41
rw
MR35
rw
MR34
rw
Toggle fields

MR34

Bit 2: D3 Pending Mask on Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR35

Bit 3: D3 Pending Mask on Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR41

Bit 9: D3 Pending Mask on Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR48

Bit 16: D3 Pending Mask on Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR49

Bit 17: D3 Pending Mask on Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR50

Bit 18: D3 Pending Mask on Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR51

Bit 19: D3 Pending Mask on Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR52

Bit 20: D3 Pending Mask on Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR53

Bit 21: D3 Pending Mask on Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

D3PCR2L

EXTI D3 pending clear selection register low

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCS41
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCS35
rw
PCS34
rw
Toggle fields

PCS34

Bits 4-5: D3 Pending request clear input signal selection on Event input x = truncate ((n+64)/2).

Allowed values:
0: DMA_CH6: DMA ch6 event selected as D3 domain pendclear source
1: DMA_CH7: DMA ch7 event selected as D3 domain pendclear source
2: LPTIM4: LPTIM4 out selected as D3 domain pendclear source
3: LPTIM5: LPTIM5 out selected as D3 domain pendclear source

PCS35

Bits 6-7: D3 Pending request clear input signal selection on Event input x = truncate ((n+64)/2).

Allowed values:
0: DMA_CH6: DMA ch6 event selected as D3 domain pendclear source
1: DMA_CH7: DMA ch7 event selected as D3 domain pendclear source
2: LPTIM4: LPTIM4 out selected as D3 domain pendclear source
3: LPTIM5: LPTIM5 out selected as D3 domain pendclear source

PCS41

Bits 18-19: D3 Pending request clear input signal selection on Event input x = truncate ((n+64)/2).

Allowed values:
0: DMA_CH6: DMA ch6 event selected as D3 domain pendclear source
1: DMA_CH7: DMA ch7 event selected as D3 domain pendclear source
2: LPTIM4: LPTIM4 out selected as D3 domain pendclear source
3: LPTIM5: LPTIM5 out selected as D3 domain pendclear source

D3PCR2H

EXTI D3 pending clear selection register high

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCS53
rw
PCS52
rw
PCS51
rw
PCS50
rw
PCS49
rw
PCS48
rw
Toggle fields

PCS48

Bits 0-1: Pending request clear input signal selection on Event input x= truncate ((n+96)/2).

Allowed values:
0: DMA_CH6: DMA ch6 event selected as D3 domain pendclear source
1: DMA_CH7: DMA ch7 event selected as D3 domain pendclear source
2: LPTIM4: LPTIM4 out selected as D3 domain pendclear source
3: LPTIM5: LPTIM5 out selected as D3 domain pendclear source

PCS49

Bits 2-3: Pending request clear input signal selection on Event input x= truncate ((n+96)/2).

Allowed values:
0: DMA_CH6: DMA ch6 event selected as D3 domain pendclear source
1: DMA_CH7: DMA ch7 event selected as D3 domain pendclear source
2: LPTIM4: LPTIM4 out selected as D3 domain pendclear source
3: LPTIM5: LPTIM5 out selected as D3 domain pendclear source

PCS50

Bits 4-5: Pending request clear input signal selection on Event input x= truncate ((n+96)/2).

Allowed values:
0: DMA_CH6: DMA ch6 event selected as D3 domain pendclear source
1: DMA_CH7: DMA ch7 event selected as D3 domain pendclear source
2: LPTIM4: LPTIM4 out selected as D3 domain pendclear source
3: LPTIM5: LPTIM5 out selected as D3 domain pendclear source

PCS51

Bits 6-7: Pending request clear input signal selection on Event input x= truncate ((n+96)/2).

Allowed values:
0: DMA_CH6: DMA ch6 event selected as D3 domain pendclear source
1: DMA_CH7: DMA ch7 event selected as D3 domain pendclear source
2: LPTIM4: LPTIM4 out selected as D3 domain pendclear source
3: LPTIM5: LPTIM5 out selected as D3 domain pendclear source

PCS52

Bits 8-9: Pending request clear input signal selection on Event input x= truncate ((n+96)/2).

Allowed values:
0: DMA_CH6: DMA ch6 event selected as D3 domain pendclear source
1: DMA_CH7: DMA ch7 event selected as D3 domain pendclear source
2: LPTIM4: LPTIM4 out selected as D3 domain pendclear source
3: LPTIM5: LPTIM5 out selected as D3 domain pendclear source

PCS53

Bits 10-11: Pending request clear input signal selection on Event input x= truncate ((n+96)/2).

Allowed values:
0: DMA_CH6: DMA ch6 event selected as D3 domain pendclear source
1: DMA_CH7: DMA ch7 event selected as D3 domain pendclear source
2: LPTIM4: LPTIM4 out selected as D3 domain pendclear source
3: LPTIM5: LPTIM5 out selected as D3 domain pendclear source

RTSR3

EXTI rising trigger selection register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TR86
rw
TR85
rw
TR84
rw
TR82
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

TR82

Bit 18: Rising trigger event configuration bit of Configurable Event input x+64.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR84

Bit 20: Rising trigger event configuration bit of Configurable Event input x+64.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR85

Bit 21: Rising trigger event configuration bit of Configurable Event input x+64.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR86

Bit 22: Rising trigger event configuration bit of Configurable Event input x+64.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

FTSR3

EXTI falling trigger selection register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TR86
rw
TR85
rw
TR84
rw
TR82
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

TR82

Bit 18: Falling trigger event configuration bit of Configurable Event input x+64.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR84

Bit 20: Falling trigger event configuration bit of Configurable Event input x+64.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR85

Bit 21: Falling trigger event configuration bit of Configurable Event input x+64.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR86

Bit 22: Falling trigger event configuration bit of Configurable Event input x+64.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

SWIER3

EXTI software interrupt event register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWIER86
rw
SWIER85
rw
SWIER84
rw
SWIER82
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

SWIER82

Bit 18: Software interrupt on line x+64.

Allowed values:
1: Pend: Generates an interrupt request

SWIER84

Bit 20: Software interrupt on line x+64.

Allowed values:
1: Pend: Generates an interrupt request

SWIER85

Bit 21: Software interrupt on line x+64.

Allowed values:
1: Pend: Generates an interrupt request

SWIER86

Bit 22: Software interrupt on line x+64.

Allowed values:
1: Pend: Generates an interrupt request

D3PMR3

EXTI D3 pending mask register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MR88
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

MR88

Bit 24: D3 Pending Mask on Event input x+64.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

D3PCR3H

EXTI D3 pending clear selection register high

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCS88
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

PCS88

Bits 18-19: D3 Pending request clear input signal selection on Event input x= truncate N+160/2.

Allowed values:
0: DMA_CH6: DMA ch6 event selected as D3 domain pendclear source
1: DMA_CH7: DMA ch7 event selected as D3 domain pendclear source
2: LPTIM4: LPTIM4 out selected as D3 domain pendclear source
3: LPTIM5: LPTIM5 out selected as D3 domain pendclear source

CPUIMR1

EXTI interrupt mask register

Offset: 0x80, size: 32, reset: 0xFFC00000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MR31
rw
MR30
rw
MR29
rw
MR28
rw
MR27
rw
MR26
rw
MR25
rw
MR24
rw
MR23
rw
MR22
rw
MR21
rw
MR20
rw
MR19
rw
MR18
rw
MR17
rw
MR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR15
rw
MR14
rw
MR13
rw
MR12
rw
MR11
rw
MR10
rw
MR9
rw
MR8
rw
MR7
rw
MR6
rw
MR5
rw
MR4
rw
MR3
rw
MR2
rw
MR1
rw
MR0
rw
Toggle fields

MR0

Bit 0: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR1

Bit 1: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR2

Bit 2: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR3

Bit 3: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR4

Bit 4: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR5

Bit 5: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR6

Bit 6: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR7

Bit 7: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR8

Bit 8: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR9

Bit 9: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR10

Bit 10: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR11

Bit 11: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR12

Bit 12: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR13

Bit 13: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR14

Bit 14: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR15

Bit 15: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR16

Bit 16: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR17

Bit 17: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR18

Bit 18: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR19

Bit 19: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR20

Bit 20: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR21

Bit 21: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR22

Bit 22: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR23

Bit 23: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR24

Bit 24: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR25

Bit 25: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR26

Bit 26: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR27

Bit 27: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR28

Bit 28: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR29

Bit 29: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR30

Bit 30: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR31

Bit 31: Rising trigger event configuration bit of Configurable Event input.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

CPUEMR1

EXTI event mask register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MR31
rw
MR30
rw
MR29
rw
MR28
rw
MR27
rw
MR26
rw
MR25
rw
MR24
rw
MR23
rw
MR22
rw
MR21
rw
MR20
rw
MR19
rw
MR18
rw
MR17
rw
MR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR15
rw
MR14
rw
MR13
rw
MR12
rw
MR11
rw
MR10
rw
MR9
rw
MR8
rw
MR7
rw
MR6
rw
MR5
rw
MR4
rw
MR3
rw
MR2
rw
MR1
rw
MR0
rw
Toggle fields

MR0

Bit 0: CPU Event mask on Event input x.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR1

Bit 1: CPU Event mask on Event input x.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR2

Bit 2: CPU Event mask on Event input x.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR3

Bit 3: CPU Event mask on Event input x.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR4

Bit 4: CPU Event mask on Event input x.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR5

Bit 5: CPU Event mask on Event input x.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR6

Bit 6: CPU Event mask on Event input x.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR7

Bit 7: CPU Event mask on Event input x.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR8

Bit 8: CPU Event mask on Event input x.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR9

Bit 9: CPU Event mask on Event input x.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR10

Bit 10: CPU Event mask on Event input x.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR11

Bit 11: CPU Event mask on Event input x.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR12

Bit 12: CPU Event mask on Event input x.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR13

Bit 13: CPU Event mask on Event input x.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR14

Bit 14: CPU Event mask on Event input x.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR15

Bit 15: CPU Event mask on Event input x.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR16

Bit 16: CPU Event mask on Event input x.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR17

Bit 17: CPU Event mask on Event input x.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR18

Bit 18: CPU Event mask on Event input x.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR19

Bit 19: CPU Event mask on Event input x.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR20

Bit 20: CPU Event mask on Event input x.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR21

Bit 21: CPU Event mask on Event input x.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR22

Bit 22: CPU Event mask on Event input x.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR23

Bit 23: CPU Event mask on Event input x.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR24

Bit 24: CPU Event mask on Event input x.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR25

Bit 25: CPU Event mask on Event input x.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR26

Bit 26: CPU Event mask on Event input x.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR27

Bit 27: CPU Event mask on Event input x.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR28

Bit 28: CPU Event mask on Event input x.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR29

Bit 29: CPU Event mask on Event input x.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR30

Bit 30: CPU Event mask on Event input x.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR31

Bit 31: CPU Event mask on Event input x.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

CPUPR1

EXTI pending register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PR21
r/w1c
PR20
r/w1c
PR19
r/w1c
PR18
r/w1c
PR17
r/w1c
PR16
r/w1c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PR15
r/w1c
PR14
r/w1c
PR13
r/w1c
PR12
r/w1c
PR11
r/w1c
PR10
r/w1c
PR9
r/w1c
PR8
r/w1c
PR7
r/w1c
PR6
r/w1c
PR5
r/w1c
PR4
r/w1c
PR3
r/w1c
PR2
r/w1c
PR1
r/w1c
PR0
r/w1c
Toggle fields

PR0

Bit 0: CPU Event mask on Event input x.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR1

Bit 1: CPU Event mask on Event input x.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR2

Bit 2: CPU Event mask on Event input x.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR3

Bit 3: CPU Event mask on Event input x.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR4

Bit 4: CPU Event mask on Event input x.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR5

Bit 5: CPU Event mask on Event input x.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR6

Bit 6: CPU Event mask on Event input x.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR7

Bit 7: CPU Event mask on Event input x.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR8

Bit 8: CPU Event mask on Event input x.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR9

Bit 9: CPU Event mask on Event input x.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR10

Bit 10: CPU Event mask on Event input x.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR11

Bit 11: CPU Event mask on Event input x.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR12

Bit 12: CPU Event mask on Event input x.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR13

Bit 13: CPU Event mask on Event input x.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR14

Bit 14: CPU Event mask on Event input x.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR15

Bit 15: CPU Event mask on Event input x.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR16

Bit 16: CPU Event mask on Event input x.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR17

Bit 17: CPU Event mask on Event input x.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR18

Bit 18: CPU Event mask on Event input x.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR19

Bit 19: CPU Event mask on Event input x.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR20

Bit 20: CPU Event mask on Event input x.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR21

Bit 21: CPU Event mask on Event input x.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

CPUIMR2

EXTI interrupt mask register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

31/31 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MR31
rw
MR30
rw
MR29
rw
MR28
rw
MR27
rw
MR26
rw
MR25
rw
MR24
rw
MR23
rw
MR22
rw
MR21
rw
MR20
rw
MR19
rw
MR18
rw
MR17
rw
MR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR15
rw
MR14
rw
MR12
rw
MR11
rw
MR10
rw
MR9
rw
MR8
rw
MR7
rw
MR6
rw
MR5
rw
MR4
rw
MR3
rw
MR2
rw
MR1
rw
MR0
rw
Toggle fields

MR0

Bit 0: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR1

Bit 1: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR2

Bit 2: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR3

Bit 3: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR4

Bit 4: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR5

Bit 5: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR6

Bit 6: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR7

Bit 7: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR8

Bit 8: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR9

Bit 9: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR10

Bit 10: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR11

Bit 11: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR12

Bit 12: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR14

Bit 14: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR15

Bit 15: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR16

Bit 16: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR17

Bit 17: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR18

Bit 18: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR19

Bit 19: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR20

Bit 20: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR21

Bit 21: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR22

Bit 22: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR23

Bit 23: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR24

Bit 24: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR25

Bit 25: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR26

Bit 26: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR27

Bit 27: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR28

Bit 28: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR29

Bit 29: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR30

Bit 30: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR31

Bit 31: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

CPUEMR2

EXTI event mask register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

31/31 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MR63
rw
MR62
rw
MR61
rw
MR60
rw
MR59
rw
MR58
rw
MR57
rw
MR56
rw
MR55
rw
MR54
rw
MR53
rw
MR52
rw
MR51
rw
MR50
rw
MR49
rw
MR48
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR47
rw
MR46
rw
MR44
rw
MR43
rw
MR42
rw
MR41
rw
MR40
rw
MR39
rw
MR38
rw
MR37
rw
MR36
rw
MR35
rw
MR34
rw
MR33
rw
MR32
rw
Toggle fields

MR32

Bit 0: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR33

Bit 1: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR34

Bit 2: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR35

Bit 3: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR36

Bit 4: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR37

Bit 5: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR38

Bit 6: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR39

Bit 7: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR40

Bit 8: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR41

Bit 9: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR42

Bit 10: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR43

Bit 11: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR44

Bit 12: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR46

Bit 14: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR47

Bit 15: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR48

Bit 16: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR49

Bit 17: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR50

Bit 18: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR51

Bit 19: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR52

Bit 20: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR53

Bit 21: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR54

Bit 22: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR55

Bit 23: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR56

Bit 24: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR57

Bit 25: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR58

Bit 26: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR59

Bit 27: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR60

Bit 28: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR61

Bit 29: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR62

Bit 30: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR63

Bit 31: CPU Interrupt Mask on Direct Event input x+32.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

CPUPR2

EXTI pending register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PR51
r/w1c
PR49
r/w1c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

PR49

Bit 17: Configurable event inputs x+32 Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR51

Bit 19: Configurable event inputs x+32 Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

CPUIMR3

EXTI interrupt mask register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

23/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MR88
rw
MR87
rw
MR86
rw
MR85
rw
MR84
rw
MR82
rw
MR80
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR79
rw
MR78
rw
MR77
rw
MR76
rw
MR75
rw
MR74
rw
MR73
rw
MR72
rw
MR71
rw
MR70
rw
MR69
rw
MR68
rw
MR67
rw
MR66
rw
MR65
rw
MR64
rw
Toggle fields

MR64

Bit 0: CPU Interrupt Mask on Direct Event input x+64.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR65

Bit 1: CPU Interrupt Mask on Direct Event input x+64.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR66

Bit 2: CPU Interrupt Mask on Direct Event input x+64.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR67

Bit 3: CPU Interrupt Mask on Direct Event input x+64.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR68

Bit 4: CPU Interrupt Mask on Direct Event input x+64.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR69

Bit 5: CPU Interrupt Mask on Direct Event input x+64.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR70

Bit 6: CPU Interrupt Mask on Direct Event input x+64.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR71

Bit 7: CPU Interrupt Mask on Direct Event input x+64.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR72

Bit 8: CPU Interrupt Mask on Direct Event input x+64.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR73

Bit 9: CPU Interrupt Mask on Direct Event input x+64.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR74

Bit 10: CPU Interrupt Mask on Direct Event input x+64.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR75

Bit 11: CPU Interrupt Mask on Direct Event input x+64.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR76

Bit 12: CPU Interrupt Mask on Direct Event input x+64.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR77

Bit 13: CPU Interrupt Mask on Direct Event input x+64.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR78

Bit 14: CPU Interrupt Mask on Direct Event input x+64.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR79

Bit 15: CPU Interrupt Mask on Direct Event input x+64.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR80

Bit 16: CPU Interrupt Mask on Direct Event input x+64.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR82

Bit 18: CPU Interrupt Mask on Direct Event input x+64.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR84

Bit 20: CPU Interrupt Mask on Direct Event input x+64.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR85

Bit 21: CPU Interrupt Mask on Direct Event input x+64.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR86

Bit 22: CPU Interrupt Mask on Direct Event input x+64.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR87

Bit 23: CPU Interrupt Mask on Direct Event input x+64.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR88

Bit 24: CPU Interrupt Mask on Direct Event input x+64.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

CPUEMR3

EXTI event mask register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

23/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MR88
rw
MR87
rw
MR86
rw
MR85
rw
MR84
rw
MR82
rw
MR80
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR79
rw
MR78
rw
MR77
rw
MR76
rw
MR75
rw
MR74
rw
MR73
rw
MR72
rw
MR71
rw
MR70
rw
MR69
rw
MR68
rw
MR67
rw
MR66
rw
MR65
rw
MR64
rw
Toggle fields

MR64

Bit 0: CPU Event mask on Event input x+64.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR65

Bit 1: CPU Event mask on Event input x+64.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR66

Bit 2: CPU Event mask on Event input x+64.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR67

Bit 3: CPU Event mask on Event input x+64.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR68

Bit 4: CPU Event mask on Event input x+64.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR69

Bit 5: CPU Event mask on Event input x+64.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR70

Bit 6: CPU Event mask on Event input x+64.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR71

Bit 7: CPU Event mask on Event input x+64.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR72

Bit 8: CPU Event mask on Event input x+64.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR73

Bit 9: CPU Event mask on Event input x+64.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR74

Bit 10: CPU Event mask on Event input x+64.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR75

Bit 11: CPU Event mask on Event input x+64.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR76

Bit 12: CPU Event mask on Event input x+64.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR77

Bit 13: CPU Event mask on Event input x+64.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR78

Bit 14: CPU Event mask on Event input x+64.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR79

Bit 15: CPU Event mask on Event input x+64.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR80

Bit 16: CPU Event mask on Event input x+64.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR82

Bit 18: CPU Event mask on Event input x+64.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR84

Bit 20: CPU Event mask on Event input x+64.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR85

Bit 21: CPU Event mask on Event input x+64.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR86

Bit 22: CPU Event mask on Event input x+64.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR87

Bit 23: CPU Event mask on Event input x+64.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

MR88

Bit 24: CPU Event mask on Event input x+64.

Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked

CPUPR3

EXTI pending register

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PR86
r/w1c
PR85
r/w1c
PR84
r/w1c
PR82
r/w1c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

PR82

Bit 18: Configurable event inputs x+64 Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR84

Bit 20: Configurable event inputs x+64 Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR85

Bit 21: Configurable event inputs x+64 Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR86

Bit 22: Configurable event inputs x+64 Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

FDCAN1

0x4000a000: FDCAN1

40/397 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CREL
0x4 ENDN
0xc DBTP
0x10 TEST
0x14 RWD
0x18 CCCR
0x1c NBTP
0x20 TSCC
0x24 TSCV
0x28 TOCC
0x2c TOCV
0x40 ECR
0x44 PSR
0x48 TDCR
0x50 IR
0x54 IE
0x58 ILS
0x5c ILE
0x80 GFC
0x84 SIDFC
0x88 XIDFC
0x90 XIDAM
0x94 HPMS
0x98 NDAT1
0x9c NDAT2
0xa0 RXF0C
0xa4 RXF0S
0xa8 RXF0A
0xac RXBC
0xb0 RXF1C
0xb4 RXF1S
0xb8 RXF1A
0xbc RXESC
0xc0 TXBC
0xc4 TXFQS
0xc8 TXESC
0xcc TXBRP
0xd0 TXBAR
0xd4 TXBCR
0xd8 TXBTO
0xdc TXBCF
0xe0 TXBTIE
0xe4 TXBCIE
0xf0 TXEFC
0xf4 TXEFS
0xf8 TXEFA
0x100 TTTMC
0x104 TTRMC
0x108 TTOCF
0x10c TTMLM
0x110 TURCF
0x114 TTOCN
0x118 TTGTP
0x11c TTTMK
0x120 TTIR
0x124 TTIE
0x128 TTILS
0x12c TTOST
0x130 TURNA
0x134 TTLGT
0x138 TTCTC
0x13c TTCPT
0x140 TTCSM
0x300 TTTS
Toggle registers

CREL

FDCAN Core Release Register

Offset: 0x0, size: 32, reset: 0x32141218, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REL
r
STEP
r
SUBSTEP
r
YEAR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MON
r
DAY
r
Toggle fields

DAY

Bits 0-7: Timestamp Day.

MON

Bits 8-15: Timestamp Month.

YEAR

Bits 16-19: Timestamp Year.

SUBSTEP

Bits 20-23: Sub-step of Core release.

STEP

Bits 24-27: Step of Core release.

REL

Bits 28-31: Core release.

ENDN

FDCAN Core Release Register

Offset: 0x4, size: 32, reset: 0x87654321, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETV
r
Toggle fields

ETV

Bits 0-31: Endiannes Test Value.

DBTP

FDCAN Data Bit Timing and Prescaler Register

Offset: 0xc, size: 32, reset: 0x00000A33, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDC
rw
DBRP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTSEG1
rw
DTSEG2
rw
DSJW
rw
Toggle fields

DSJW

Bits 0-3: Synchronization Jump Width.

DTSEG2

Bits 4-7: Data time segment after sample point.

DTSEG1

Bits 8-12: Data time segment after sample point.

DBRP

Bits 16-20: Data BIt Rate Prescaler.

TDC

Bit 23: Transceiver Delay Compensation.

TEST

FDCAN Test Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX
rw
TX
rw
LBCK
rw
Toggle fields

LBCK

Bit 4: Loop Back mode.

TX

Bits 5-6: Loop Back mode.

RX

Bit 7: Control of Transmit Pin.

RWD

FDCAN RAM Watchdog Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDV
r
WDC
rw
Toggle fields

WDC

Bits 0-7: Watchdog configuration.

WDV

Bits 8-15: Watchdog value.

CCCR

FDCAN CC Control Register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NISO
rw
TXP
rw
EFBI
rw
PXHD
rw
BSE
rw
FDOE
rw
TEST
rw
DAR
rw
MON
rw
CSR
rw
CSA
rw
ASM
rw
CCE
rw
INIT
rw
Toggle fields

INIT

Bit 0: Initialization.

CCE

Bit 1: Configuration Change Enable.

ASM

Bit 2: ASM Restricted Operation Mode.

CSA

Bit 3: Clock Stop Acknowledge.

CSR

Bit 4: Clock Stop Request.

MON

Bit 5: Bus Monitoring Mode.

DAR

Bit 6: Disable Automatic Retransmission.

TEST

Bit 7: Test Mode Enable.

FDOE

Bit 8: FD Operation Enable.

BSE

Bit 9: FDCAN Bit Rate Switching.

PXHD

Bit 12: Protocol Exception Handling Disable.

EFBI

Bit 13: Edge Filtering during Bus Integration.

TXP

Bit 14: TXP.

NISO

Bit 15: Non ISO Operation.

NBTP

FDCAN Nominal Bit Timing and Prescaler Register

Offset: 0x1c, size: 32, reset: 0x00000A33, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSJW
rw
NBRP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NTSEG1
rw
NTSEG2
rw
Toggle fields

NTSEG2

Bits 0-6: Nominal Time segment after sample point.

NTSEG1

Bits 8-15: Nominal Time segment before sample point.

NBRP

Bits 16-24: Bit Rate Prescaler.

NSJW

Bits 25-31: NSJW: Nominal (Re)Synchronization Jump Width.

TSCC

FDCAN Timestamp Counter Configuration Register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSS
rw
Toggle fields

TSS

Bits 0-1: Timestamp Select.

TCP

Bits 16-19: Timestamp Counter Prescaler.

TSCV

FDCAN Timestamp Counter Value Register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSC
rw
Toggle fields

TSC

Bits 0-15: Timestamp Counter.

TOCC

FDCAN Timeout Counter Configuration Register

Offset: 0x28, size: 32, reset: 0xFFFF0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TOP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOS
rw
ETOC
rw
Toggle fields

ETOC

Bit 0: Enable Timeout Counter.

TOS

Bits 1-2: Timeout Select.

TOP

Bits 16-31: Timeout Period.

TOCV

FDCAN Timeout Counter Value Register

Offset: 0x2c, size: 32, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOC
rw
Toggle fields

TOC

Bits 0-15: Timeout Counter.

ECR

FDCAN Error Counter Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RP
rw
REC
rw
TEC
rw
Toggle fields

TEC

Bits 0-7: Transmit Error Counter.

REC

Bits 8-14: Receive Error Counter.

RP

Bit 15: Receive Error Passive.

CEL

Bits 16-23: AN Error Logging.

PSR

FDCAN Protocol Status Register

Offset: 0x44, size: 32, reset: 0x00000707, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDCV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PXE
rw
REDL
rw
RBRS
rw
RESI
rw
DLEC
rw
BO
rw
EW
rw
EP
rw
ACT
rw
LEC
rw
Toggle fields

LEC

Bits 0-2: Last Error Code.

ACT

Bits 3-4: Activity.

EP

Bit 5: Error Passive.

EW

Bit 6: Warning Status.

BO

Bit 7: Bus_Off Status.

DLEC

Bits 8-10: Data Last Error Code.

RESI

Bit 11: ESI flag of last received FDCAN Message.

RBRS

Bit 12: BRS flag of last received FDCAN Message.

REDL

Bit 13: Received FDCAN Message.

PXE

Bit 14: Protocol Exception Event.

TDCV

Bits 16-22: Transmitter Delay Compensation Value.

TDCR

FDCAN Transmitter Delay Compensation Register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDCO
rw
TDCF
rw
Toggle fields

TDCF

Bits 0-6: Transmitter Delay Compensation Filter Window Length.

TDCO

Bits 8-14: Transmitter Delay Compensation Offset.

IR

FDCAN Interrupt Register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARA
rw
PED
rw
PEA
rw
WDI
rw
BO
rw
EW
rw
EP
rw
ELO
rw
DRX
rw
TOO
rw
MRAF
rw
TSW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEFL
rw
TEFF
rw
TEFW
rw
TEFN
rw
TEF
rw
TCF
rw
TC
rw
HPM
rw
RF1L
rw
RF1F
rw
RF1W
rw
RF1N
rw
RF0L
rw
RF0F
rw
RF0W
rw
RF0N
rw
Toggle fields

RF0N

Bit 0: Rx FIFO 0 New Message.

RF0W

Bit 1: Rx FIFO 0 Full.

RF0F

Bit 2: Rx FIFO 0 Full.

RF0L

Bit 3: Rx FIFO 0 Message Lost.

RF1N

Bit 4: Rx FIFO 1 New Message.

RF1W

Bit 5: Rx FIFO 1 Watermark Reached.

RF1F

Bit 6: Rx FIFO 1 Watermark Reached.

RF1L

Bit 7: Rx FIFO 1 Message Lost.

HPM

Bit 8: High Priority Message.

TC

Bit 9: Transmission Completed.

TCF

Bit 10: Transmission Cancellation Finished.

TEF

Bit 11: Tx FIFO Empty.

TEFN

Bit 12: Tx Event FIFO New Entry.

TEFW

Bit 13: Tx Event FIFO Watermark Reached.

TEFF

Bit 14: Tx Event FIFO Full.

TEFL

Bit 15: Tx Event FIFO Element Lost.

TSW

Bit 16: Timestamp Wraparound.

MRAF

Bit 17: Message RAM Access Failure.

TOO

Bit 18: Timeout Occurred.

DRX

Bit 19: Message stored to Dedicated Rx Buffer.

ELO

Bit 22: Error Logging Overflow.

EP

Bit 23: Error Passive.

EW

Bit 24: Warning Status.

BO

Bit 25: Bus_Off Status.

WDI

Bit 26: Watchdog Interrupt.

PEA

Bit 27: Protocol Error in Arbitration Phase (Nominal Bit Time is used).

PED

Bit 28: Protocol Error in Data Phase (Data Bit Time is used).

ARA

Bit 29: Access to Reserved Address.

IE

FDCAN Interrupt Enable Register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/30 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARAE
rw
PEDE
rw
PEAE
rw
WDIE
rw
BOE
rw
EWE
rw
EPE
rw
ELOE
rw
BEUE
rw
BECE
rw
DRXE
rw
TOOE
rw
MRAFE
rw
TSWE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEFLE
rw
TEFFE
rw
TEFWE
rw
TEFNE
rw
TEFE
rw
TCFE
rw
TCE
rw
HPME
rw
RF1LE
rw
RF1FE
rw
RF1WE
rw
RF1NE
rw
RF0LE
rw
RF0FE
rw
RF0WE
rw
RF0NE
rw
Toggle fields

RF0NE

Bit 0: Rx FIFO 0 New Message Enable.

RF0WE

Bit 1: Rx FIFO 0 Full Enable.

RF0FE

Bit 2: Rx FIFO 0 Full Enable.

RF0LE

Bit 3: Rx FIFO 0 Message Lost Enable.

RF1NE

Bit 4: Rx FIFO 1 New Message Enable.

RF1WE

Bit 5: Rx FIFO 1 Watermark Reached Enable.

RF1FE

Bit 6: Rx FIFO 1 Watermark Reached Enable.

RF1LE

Bit 7: Rx FIFO 1 Message Lost Enable.

HPME

Bit 8: High Priority Message Enable.

TCE

Bit 9: Transmission Completed Enable.

TCFE

Bit 10: Transmission Cancellation Finished Enable.

TEFE

Bit 11: Tx FIFO Empty Enable.

TEFNE

Bit 12: Tx Event FIFO New Entry Enable.

TEFWE

Bit 13: Tx Event FIFO Watermark Reached Enable.

TEFFE

Bit 14: Tx Event FIFO Full Enable.

TEFLE

Bit 15: Tx Event FIFO Element Lost Enable.

TSWE

Bit 16: Timestamp Wraparound Enable.

MRAFE

Bit 17: Message RAM Access Failure Enable.

TOOE

Bit 18: Timeout Occurred Enable.

DRXE

Bit 19: Message stored to Dedicated Rx Buffer Enable.

BECE

Bit 20: Bit Error Corrected Interrupt Enable.

BEUE

Bit 21: Bit Error Uncorrected Interrupt Enable.

ELOE

Bit 22: Error Logging Overflow Enable.

EPE

Bit 23: Error Passive Enable.

EWE

Bit 24: Warning Status Enable.

BOE

Bit 25: Bus_Off Status Enable.

WDIE

Bit 26: Watchdog Interrupt Enable.

PEAE

Bit 27: Protocol Error in Arbitration Phase Enable.

PEDE

Bit 28: Protocol Error in Data Phase Enable.

ARAE

Bit 29: Access to Reserved Address Enable.

ILS

FDCAN Interrupt Line Select Register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/30 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARAL
rw
PEDL
rw
PEAL
rw
WDIL
rw
BOL
rw
EWL
rw
EPL
rw
ELOL
rw
BEUL
rw
BECL
rw
DRXL
rw
TOOL
rw
MRAFL
rw
TSWL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEFLL
rw
TEFFL
rw
TEFWL
rw
TEFNL
rw
TEFL
rw
TCFL
rw
TCL
rw
HPML
rw
RF1LL
rw
RF1FL
rw
RF1WL
rw
RF1NL
rw
RF0LL
rw
RF0FL
rw
RF0WL
rw
RF0NL
rw
Toggle fields

RF0NL

Bit 0: Rx FIFO 0 New Message Interrupt Line.

RF0WL

Bit 1: Rx FIFO 0 Watermark Reached Interrupt Line.

RF0FL

Bit 2: Rx FIFO 0 Full Interrupt Line.

RF0LL

Bit 3: Rx FIFO 0 Message Lost Interrupt Line.

RF1NL

Bit 4: Rx FIFO 1 New Message Interrupt Line.

RF1WL

Bit 5: Rx FIFO 1 Watermark Reached Interrupt Line.

RF1FL

Bit 6: Rx FIFO 1 Full Interrupt Line.

RF1LL

Bit 7: Rx FIFO 1 Message Lost Interrupt Line.

HPML

Bit 8: High Priority Message Interrupt Line.

TCL

Bit 9: Transmission Completed Interrupt Line.

TCFL

Bit 10: Transmission Cancellation Finished Interrupt Line.

TEFL

Bit 11: Tx FIFO Empty Interrupt Line.

TEFNL

Bit 12: Tx Event FIFO New Entry Interrupt Line.

TEFWL

Bit 13: Tx Event FIFO Watermark Reached Interrupt Line.

TEFFL

Bit 14: Tx Event FIFO Full Interrupt Line.

TEFLL

Bit 15: Tx Event FIFO Element Lost Interrupt Line.

TSWL

Bit 16: Timestamp Wraparound Interrupt Line.

MRAFL

Bit 17: Message RAM Access Failure Interrupt Line.

TOOL

Bit 18: Timeout Occurred Interrupt Line.

DRXL

Bit 19: Message stored to Dedicated Rx Buffer Interrupt Line.

BECL

Bit 20: Bit Error Corrected Interrupt Line.

BEUL

Bit 21: Bit Error Uncorrected Interrupt Line.

ELOL

Bit 22: Error Logging Overflow Interrupt Line.

EPL

Bit 23: Error Passive Interrupt Line.

EWL

Bit 24: Warning Status Interrupt Line.

BOL

Bit 25: Bus_Off Status.

WDIL

Bit 26: Watchdog Interrupt Line.

PEAL

Bit 27: Protocol Error in Arbitration Phase Line.

PEDL

Bit 28: Protocol Error in Data Phase Line.

ARAL

Bit 29: Access to Reserved Address Line.

ILE

FDCAN Interrupt Line Enable Register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EINT1
rw
EINT0
rw
Toggle fields

EINT0

Bit 0: Enable Interrupt Line 0.

EINT1

Bit 1: Enable Interrupt Line 1.

GFC

FDCAN Global Filter Configuration Register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ANFS
rw
ANFE
rw
RRFS
rw
RRFE
rw
Toggle fields

RRFE

Bit 0: Reject Remote Frames Extended.

RRFS

Bit 1: Reject Remote Frames Standard.

ANFE

Bits 2-3: Accept Non-matching Frames Extended.

ANFS

Bits 4-5: Accept Non-matching Frames Standard.

SIDFC

FDCAN Standard ID Filter Configuration Register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLSSA
rw
Toggle fields

FLSSA

Bits 2-15: Filter List Standard Start Address.

LSS

Bits 16-23: List Size Standard.

XIDFC

FDCAN Extended ID Filter Configuration Register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LSE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLESA
rw
Toggle fields

FLESA

Bits 2-15: Filter List Standard Start Address.

LSE

Bits 16-23: List Size Extended.

XIDAM

FDCAN Extended ID and Mask Register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EIDM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EIDM
rw
Toggle fields

EIDM

Bits 0-28: Extended ID Mask.

HPMS

FDCAN High Priority Message Status Register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLST
r
FIDX
r
MSI
r
BIDX
r
Toggle fields

BIDX

Bits 0-5: Buffer Index.

MSI

Bits 6-7: Message Storage Indicator.

FIDX

Bits 8-14: Filter Index.

FLST

Bit 15: Filter List.

NDAT1

FDCAN New Data 1 Register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ND31
rw
ND30
rw
ND29
rw
ND28
rw
ND27
rw
ND26
rw
ND25
rw
ND24
rw
ND23
rw
ND22
rw
ND21
rw
ND20
rw
ND19
rw
ND18
rw
ND17
rw
ND16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ND15
rw
ND14
rw
ND13
rw
ND12
rw
ND11
rw
ND10
rw
ND9
rw
ND8
rw
ND7
rw
ND6
rw
ND5
rw
ND4
rw
ND3
rw
ND2
rw
ND1
rw
ND0
rw
Toggle fields

ND0

Bit 0: New data.

ND1

Bit 1: New data.

ND2

Bit 2: New data.

ND3

Bit 3: New data.

ND4

Bit 4: New data.

ND5

Bit 5: New data.

ND6

Bit 6: New data.

ND7

Bit 7: New data.

ND8

Bit 8: New data.

ND9

Bit 9: New data.

ND10

Bit 10: New data.

ND11

Bit 11: New data.

ND12

Bit 12: New data.

ND13

Bit 13: New data.

ND14

Bit 14: New data.

ND15

Bit 15: New data.

ND16

Bit 16: New data.

ND17

Bit 17: New data.

ND18

Bit 18: New data.

ND19

Bit 19: New data.

ND20

Bit 20: New data.

ND21

Bit 21: New data.

ND22

Bit 22: New data.

ND23

Bit 23: New data.

ND24

Bit 24: New data.

ND25

Bit 25: New data.

ND26

Bit 26: New data.

ND27

Bit 27: New data.

ND28

Bit 28: New data.

ND29

Bit 29: New data.

ND30

Bit 30: New data.

ND31

Bit 31: New data.

NDAT2

FDCAN New Data 2 Register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ND63
rw
ND62
rw
ND61
rw
ND60
rw
ND59
rw
ND58
rw
ND57
rw
ND56
rw
ND55
rw
ND54
rw
ND53
rw
ND52
rw
ND51
rw
ND50
rw
ND49
rw
ND48
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ND47
rw
ND46
rw
ND45
rw
ND44
rw
ND43
rw
ND42
rw
ND41
rw
ND40
rw
ND39
rw
ND38
rw
ND37
rw
ND36
rw
ND35
rw
ND34
rw
ND33
rw
ND32
rw
Toggle fields

ND32

Bit 0: New data.

ND33

Bit 1: New data.

ND34

Bit 2: New data.

ND35

Bit 3: New data.

ND36

Bit 4: New data.

ND37

Bit 5: New data.

ND38

Bit 6: New data.

ND39

Bit 7: New data.

ND40

Bit 8: New data.

ND41

Bit 9: New data.

ND42

Bit 10: New data.

ND43

Bit 11: New data.

ND44

Bit 12: New data.

ND45

Bit 13: New data.

ND46

Bit 14: New data.

ND47

Bit 15: New data.

ND48

Bit 16: New data.

ND49

Bit 17: New data.

ND50

Bit 18: New data.

ND51

Bit 19: New data.

ND52

Bit 20: New data.

ND53

Bit 21: New data.

ND54

Bit 22: New data.

ND55

Bit 23: New data.

ND56

Bit 24: New data.

ND57

Bit 25: New data.

ND58

Bit 26: New data.

ND59

Bit 27: New data.

ND60

Bit 28: New data.

ND61

Bit 29: New data.

ND62

Bit 30: New data.

ND63

Bit 31: New data.

RXF0C

FDCAN Rx FIFO 0 Configuration Register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
F0OM
rw
F0WM
rw
F0S
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F0SA
rw
Toggle fields

F0SA

Bits 2-15: Rx FIFO 0 Start Address.

F0S

Bits 16-22: Rx FIFO 0 Size.

F0WM

Bits 24-30: FIFO 0 Watermark.

F0OM

Bit 31: FIFO 0 operation mode.

RXF0S

FDCAN Rx FIFO 0 Status Register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RF0L
rw
F0F
rw
F0PI
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F0GI
rw
F0FL
rw
Toggle fields

F0FL

Bits 0-6: Rx FIFO 0 Fill Level.

F0GI

Bits 8-13: Rx FIFO 0 Get Index.

F0PI

Bits 16-21: Rx FIFO 0 Put Index.

F0F

Bit 24: Rx FIFO 0 Full.

RF0L

Bit 25: Rx FIFO 0 Message Lost.

RXF0A

CAN Rx FIFO 0 Acknowledge Register

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F0AI
rw
Toggle fields

F0AI

Bits 0-5: Rx FIFO 0 Acknowledge Index.

RXBC

FDCAN Rx Buffer Configuration Register

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RBSA
rw
Toggle fields

RBSA

Bits 2-15: Rx Buffer Start Address.

RXF1C

FDCAN Rx FIFO 1 Configuration Register

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
F1OM
rw
F1WM
rw
F1S
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F1SA
rw
Toggle fields

F1SA

Bits 2-15: Rx FIFO 1 Start Address.

F1S

Bits 16-22: Rx FIFO 1 Size.

F1WM

Bits 24-30: Rx FIFO 1 Watermark.

F1OM

Bit 31: FIFO 1 operation mode.

RXF1S

FDCAN Rx FIFO 1 Status Register

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMS
rw
RF1L
rw
F1F
rw
F1PI
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F1GI
rw
F1FL
rw
Toggle fields

F1FL

Bits 0-6: Rx FIFO 1 Fill Level.

F1GI

Bits 8-14: Rx FIFO 1 Get Index.

F1PI

Bits 16-22: Rx FIFO 1 Put Index.

F1F

Bit 24: Rx FIFO 1 Full.

RF1L

Bit 25: Rx FIFO 1 Message Lost.

DMS

Bits 30-31: Debug Message Status.

RXF1A

FDCAN Rx FIFO 1 Acknowledge Register

Offset: 0xb8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F1AI
rw
Toggle fields

F1AI

Bits 0-5: Rx FIFO 1 Acknowledge Index.

RXESC

FDCAN Rx Buffer Element Size Configuration Register

Offset: 0xbc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RBDS
rw
F1DS
rw
F0DS
rw
Toggle fields

F0DS

Bits 0-2: Rx FIFO 1 Data Field Size:.

F1DS

Bits 4-6: Rx FIFO 0 Data Field Size:.

RBDS

Bits 8-10: Rx Buffer Data Field Size:.

TXBC

FDCAN Tx Buffer Configuration Register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TFQM
rw
TFQS
rw
NDTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBSA
rw
Toggle fields

TBSA

Bits 2-15: Tx Buffers Start Address.

NDTB

Bits 16-21: Number of Dedicated Transmit Buffers.

TFQS

Bits 24-29: Transmit FIFO/Queue Size.

TFQM

Bit 30: Tx FIFO/Queue Mode.

TXFQS

FDCAN Tx FIFO/Queue Status Register

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TFQF
r
TFQPI
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TFGI
r
TFFL
r
Toggle fields

TFFL

Bits 0-5: Tx FIFO Free Level.

TFGI

Bits 8-12: TFGI.

TFQPI

Bits 16-20: Tx FIFO/Queue Put Index.

TFQF

Bit 21: Tx FIFO/Queue Full.

TXESC

FDCAN Tx Buffer Element Size Configuration Register

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBDS
rw
Toggle fields

TBDS

Bits 0-2: Tx Buffer Data Field Size:.

TXBRP

FDCAN Tx Buffer Request Pending Register

Offset: 0xcc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TRP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRP
r
Toggle fields

TRP

Bits 0-31: Transmission Request Pending.

TXBAR

FDCAN Tx Buffer Add Request Register

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AR
rw
Toggle fields

AR

Bits 0-31: Add Request.

TXBCR

FDCAN Tx Buffer Cancellation Request Register

Offset: 0xd4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR
rw
Toggle fields

CR

Bits 0-31: Cancellation Request.

TXBTO

FDCAN Tx Buffer Transmission Occurred Register

Offset: 0xd8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TO
rw
Toggle fields

TO

Bits 0-31: Transmission Occurred..

TXBCF

FDCAN Tx Buffer Cancellation Finished Register

Offset: 0xdc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CF
r
Toggle fields

CF

Bits 0-31: Cancellation Finished.

TXBTIE

FDCAN Tx Buffer Transmission Interrupt Enable Register

Offset: 0xe0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIE
rw
Toggle fields

TIE

Bits 0-31: Transmission Interrupt Enable.

TXBCIE

FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register

Offset: 0xe4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CF
rw
Toggle fields

CF

Bits 0-31: Cancellation Finished Interrupt Enable.

TXEFC

FDCAN Tx Event FIFO Configuration Register

Offset: 0xf0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EFWM
rw
EFS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFSA
rw
Toggle fields

EFSA

Bits 2-15: Event FIFO Start Address.

EFS

Bits 16-21: Event FIFO Size.

EFWM

Bits 24-29: Event FIFO Watermark.

TXEFS

FDCAN Tx Event FIFO Status Register

Offset: 0xf4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEFL
rw
EFF
rw
EFPI
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFGI
rw
EFFL
rw
Toggle fields

EFFL

Bits 0-5: Event FIFO Fill Level.

EFGI

Bits 8-12: Event FIFO Get Index..

EFPI

Bits 16-20: Event FIFO put index..

EFF

Bit 24: Event FIFO Full..

TEFL

Bit 25: Tx Event FIFO Element Lost..

TXEFA

FDCAN Tx Event FIFO Acknowledge Register

Offset: 0xf8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFAI
rw
Toggle fields

EFAI

Bits 0-4: Event FIFO Acknowledge Index.

TTTMC

FDCAN TT Trigger Memory Configuration Register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMSA
rw
Toggle fields

TMSA

Bits 2-15: Trigger Memory Start Address.

TME

Bits 16-22: Trigger Memory Elements.

TTRMC

FDCAN TT Reference Message Configuration Register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RMPS
rw
XTD
rw
RID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RID
rw
Toggle fields

RID

Bits 0-28: Reference Identifier..

XTD

Bit 30: Extended Identifier.

RMPS

Bit 31: Reference Message Payload Select.

TTOCF

FDCAN TT Operation Configuration Register

Offset: 0x108, size: 32, reset: 0x00010000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EVTP
rw
ECC
rw
EGTF
rw
AWL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EECS
rw
IRTO
rw
LDSDL
rw
TM
rw
GEN
rw
OM
rw
Toggle fields

OM

Bits 0-1: Operation Mode.

GEN

Bit 3: Gap Enable.

TM

Bit 4: Time Master.

LDSDL

Bits 5-7: LD of Synchronization Deviation Limit.

IRTO

Bits 8-14: Initial Reference Trigger Offset.

EECS

Bit 15: Enable External Clock Synchronization.

AWL

Bits 16-23: Application Watchdog Limit.

EGTF

Bit 24: Enable Global Time Filtering.

ECC

Bit 25: Enable Clock Calibration.

EVTP

Bit 26: Event Trigger Polarity.

TTMLM

FDCAN TT Matrix Limits Register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENTT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXEW
rw
CSS
rw
CCM
rw
Toggle fields

CCM

Bits 0-5: Cycle Count Max.

CSS

Bits 6-7: Cycle Start Synchronization.

TXEW

Bits 8-11: Tx Enable Window.

ENTT

Bits 16-27: Expected Number of Tx Triggers.

TURCF

FDCAN TUR Configuration Register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ELT
rw
DC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NCL
rw
Toggle fields

NCL

Bits 0-15: Numerator Configuration Low..

DC

Bits 16-29: Denominator Configuration..

ELT

Bit 31: Enable Local Time.

TTOCN

FDCAN TT Operation Control Register

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCKC
rw
ESCN
rw
NIG
rw
TMG
rw
FGP
rw
GCS
rw
TTIE
rw
TMC
rw
RTIE
rw
SWS
rw
SWP
rw
ECS
rw
SGT
rw
Toggle fields

SGT

Bit 0: Set Global time.

ECS

Bit 1: External Clock Synchronization.

SWP

Bit 2: Stop Watch Polarity.

SWS

Bits 3-4: Stop Watch Source..

RTIE

Bit 5: Register Time Mark Interrupt Pulse Enable.

TMC

Bits 6-7: Register Time Mark Compare.

TTIE

Bit 8: Trigger Time Mark Interrupt Pulse Enable.

GCS

Bit 9: Gap Control Select.

FGP

Bit 10: Finish Gap..

TMG

Bit 11: Time Mark Gap.

NIG

Bit 12: Next is Gap.

ESCN

Bit 13: External Synchronization Control.

LCKC

Bit 15: TT Operation Control Register Locked.

TTGTP

FDCAN TT Global Time Preset Register

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NCL
rw
Toggle fields

NCL

Bits 0-15: Time Preset.

CTP

Bits 16-31: Cycle Time Target Phase.

TTTMK

FDCAN TT Time Mark Register

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKM
rw
TICC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TM
rw
Toggle fields

TM

Bits 0-15: Time Mark.

TICC

Bits 16-22: Time Mark Cycle Code.

LCKM

Bit 31: TT Time Mark Register Locked.

TTIR

FDCAN TT Interrupt Register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CER
rw
AW
rw
WT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IWTG
rw
ELC
rw
SE2
rw
SE1
rw
TXO
rw
TXU
rw
GTE
rw
GTD
rw
GTW
rw
SWE
rw
TTMI
rw
RTMI
rw
SOG
rw
CSM
rw
SMC
rw
SBC
rw
Toggle fields

SBC

Bit 0: Start of Basic Cycle.

SMC

Bit 1: Start of Matrix Cycle.

CSM

Bit 2: Change of Synchronization Mode.

SOG

Bit 3: Start of Gap.

RTMI

Bit 4: Register Time Mark Interrupt..

TTMI

Bit 5: Trigger Time Mark Event Internal.

SWE

Bit 6: Stop Watch Event.

GTW

Bit 7: Global Time Wrap.

GTD

Bit 8: Global Time Discontinuity.

GTE

Bit 9: Global Time Error.

TXU

Bit 10: Tx Count Underflow.

TXO

Bit 11: Tx Count Overflow.

SE1

Bit 12: Scheduling Error 1.

SE2

Bit 13: Scheduling Error 2.

ELC

Bit 14: Error Level Changed..

IWTG

Bit 15: Initialization Watch Trigger.

WT

Bit 16: Watch Trigger.

AW

Bit 17: Application Watchdog.

CER

Bit 18: Configuration Error.

TTIE

FDCAN TT Interrupt Enable Register

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CERE
rw
AWE
rw
WTE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IWTGE
rw
ELCE
rw
SE2E
rw
SE1E
rw
TXOE
rw
TXUE
rw
GTEE
rw
GTDE
rw
GTWE
rw
SWEE
rw
TTMIE
rw
RTMIE
rw
SOGE
rw
CSME
rw
SMCE
rw
SBCE
rw
Toggle fields

SBCE

Bit 0: Start of Basic Cycle Interrupt Enable.

SMCE

Bit 1: Start of Matrix Cycle Interrupt Enable.

CSME

Bit 2: Change of Synchronization Mode Interrupt Enable.

SOGE

Bit 3: Start of Gap Interrupt Enable.

RTMIE

Bit 4: Register Time Mark Interrupt Enable.

TTMIE

Bit 5: Trigger Time Mark Event Internal Interrupt Enable.

SWEE

Bit 6: Stop Watch Event Interrupt Enable.

GTWE

Bit 7: Global Time Wrap Interrupt Enable.

GTDE

Bit 8: Global Time Discontinuity Interrupt Enable.

GTEE

Bit 9: Global Time Error Interrupt Enable.

TXUE

Bit 10: Tx Count Underflow Interrupt Enable.

TXOE

Bit 11: Tx Count Overflow Interrupt Enable.

SE1E

Bit 12: Scheduling Error 1 Interrupt Enable.

SE2E

Bit 13: Scheduling Error 2 Interrupt Enable.

ELCE

Bit 14: Change Error Level Interrupt Enable.

IWTGE

Bit 15: Initialization Watch Trigger Interrupt Enable.

WTE

Bit 16: Watch Trigger Interrupt Enable.

AWE

Bit 17: Application Watchdog Interrupt Enable.

CERE

Bit 18: Configuration Error Interrupt Enable.

TTILS

FDCAN TT Interrupt Line Select Register

Offset: 0x128, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CERL
rw
AWL
rw
WTL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IWTGL
rw
ELCL
rw
SE2L
rw
SE1L
rw
TXOL
rw
TXUL
rw
GTEL
rw
GTDL
rw
GTWL
rw
SWEL
rw
TTMIL
rw
RTMIL
rw
SOGL
rw
CSML
rw
SMCL
rw
SBCL
rw
Toggle fields

SBCL

Bit 0: Start of Basic Cycle Interrupt Line.

SMCL

Bit 1: Start of Matrix Cycle Interrupt Line.

CSML

Bit 2: Change of Synchronization Mode Interrupt Line.

SOGL

Bit 3: Start of Gap Interrupt Line.

RTMIL

Bit 4: Register Time Mark Interrupt Line.

TTMIL

Bit 5: Trigger Time Mark Event Internal Interrupt Line.

SWEL

Bit 6: Stop Watch Event Interrupt Line.

GTWL

Bit 7: Global Time Wrap Interrupt Line.

GTDL

Bit 8: Global Time Discontinuity Interrupt Line.

GTEL

Bit 9: Global Time Error Interrupt Line.

TXUL

Bit 10: Tx Count Underflow Interrupt Line.

TXOL

Bit 11: Tx Count Overflow Interrupt Line.

SE1L

Bit 12: Scheduling Error 1 Interrupt Line.

SE2L

Bit 13: Scheduling Error 2 Interrupt Line.

ELCL

Bit 14: Change Error Level Interrupt Line.

IWTGL

Bit 15: Initialization Watch Trigger Interrupt Line.

WTL

Bit 16: Watch Trigger Interrupt Line.

AWL

Bit 17: Application Watchdog Interrupt Line.

CERL

Bit 18: Configuration Error Interrupt Line.

TTOST

FDCAN TT Operation Status Register

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-only

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPL
r
WECS
r
AWE
r
WFE
r
GSI
r
TMP
r
GFI
r
WGTD
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
r
QCS
r
QGTP
r
SYS
r
MS
r
EL
r
Toggle fields

EL

Bits 0-1: Error Level.

MS

Bits 2-3: Master State..

SYS

Bits 4-5: Synchronization State.

QGTP

Bit 6: Quality of Global Time Phase.

QCS

Bit 7: Quality of Clock Speed.

RTO

Bits 8-15: Reference Trigger Offset.

WGTD

Bit 22: Wait for Global Time Discontinuity.

GFI

Bit 23: Gap Finished Indicator..

TMP

Bits 24-26: Time Master Priority.

GSI

Bit 27: Gap Started Indicator..

WFE

Bit 28: Wait for Event.

AWE

Bit 29: Application Watchdog Event.

WECS

Bit 30: Wait for External Clock Synchronization.

SPL

Bit 31: Schedule Phase Lock.

TURNA

FDCAN TUR Numerator Actual Register

Offset: 0x130, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NAV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAV
r
Toggle fields

NAV

Bits 0-17: Numerator Actual Value.

TTLGT

FDCAN TT Local and Global Time Register

Offset: 0x134, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT
r
Toggle fields

LT

Bits 0-15: Local Time.

GT

Bits 16-31: Global Time.

TTCTC

FDCAN TT Cycle Time and Count Register

Offset: 0x138, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CT
r
Toggle fields

CT

Bits 0-15: Cycle Time.

CC

Bits 16-21: Cycle Count.

TTCPT

FDCAN TT Capture Time Register

Offset: 0x13c, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCV
r
Toggle fields

CCV

Bits 0-5: Cycle Count Value.

SWV

Bits 16-31: Stop Watch Value.

TTCSM

FDCAN TT Cycle Sync Mark Register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSM
r
Toggle fields

CSM

Bits 0-15: Cycle Sync Mark.

TTTS

FDCAN TT Trigger Select Register

Offset: 0x300, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EVTSEL
rw
SWTDEL
rw
Toggle fields

SWTDEL

Bits 0-1: Stop watch trigger input selection.

EVTSEL

Bits 4-5: Event trigger input selection.

FDCAN2

0x4000a400: FDCAN1

40/397 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CREL
0x4 ENDN
0xc DBTP
0x10 TEST
0x14 RWD
0x18 CCCR
0x1c NBTP
0x20 TSCC
0x24 TSCV
0x28 TOCC
0x2c TOCV
0x40 ECR
0x44 PSR
0x48 TDCR
0x50 IR
0x54 IE
0x58 ILS
0x5c ILE
0x80 GFC
0x84 SIDFC
0x88 XIDFC
0x90 XIDAM
0x94 HPMS
0x98 NDAT1
0x9c NDAT2
0xa0 RXF0C
0xa4 RXF0S
0xa8 RXF0A
0xac RXBC
0xb0 RXF1C
0xb4 RXF1S
0xb8 RXF1A
0xbc RXESC
0xc0 TXBC
0xc4 TXFQS
0xc8 TXESC
0xcc TXBRP
0xd0 TXBAR
0xd4 TXBCR
0xd8 TXBTO
0xdc TXBCF
0xe0 TXBTIE
0xe4 TXBCIE
0xf0 TXEFC
0xf4 TXEFS
0xf8 TXEFA
0x100 TTTMC
0x104 TTRMC
0x108 TTOCF
0x10c TTMLM
0x110 TURCF
0x114 TTOCN
0x118 TTGTP
0x11c TTTMK
0x120 TTIR
0x124 TTIE
0x128 TTILS
0x12c TTOST
0x130 TURNA
0x134 TTLGT
0x138 TTCTC
0x13c TTCPT
0x140 TTCSM
0x300 TTTS
Toggle registers

CREL

FDCAN Core Release Register

Offset: 0x0, size: 32, reset: 0x32141218, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REL
r
STEP
r
SUBSTEP
r
YEAR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MON
r
DAY
r
Toggle fields

DAY

Bits 0-7: Timestamp Day.

MON

Bits 8-15: Timestamp Month.

YEAR

Bits 16-19: Timestamp Year.

SUBSTEP

Bits 20-23: Sub-step of Core release.

STEP

Bits 24-27: Step of Core release.

REL

Bits 28-31: Core release.

ENDN

FDCAN Core Release Register

Offset: 0x4, size: 32, reset: 0x87654321, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETV
r
Toggle fields

ETV

Bits 0-31: Endiannes Test Value.

DBTP

FDCAN Data Bit Timing and Prescaler Register

Offset: 0xc, size: 32, reset: 0x00000A33, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDC
rw
DBRP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTSEG1
rw
DTSEG2
rw
DSJW
rw
Toggle fields

DSJW

Bits 0-3: Synchronization Jump Width.

DTSEG2

Bits 4-7: Data time segment after sample point.

DTSEG1

Bits 8-12: Data time segment after sample point.

DBRP

Bits 16-20: Data BIt Rate Prescaler.

TDC

Bit 23: Transceiver Delay Compensation.

TEST

FDCAN Test Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX
rw
TX
rw
LBCK
rw
Toggle fields

LBCK

Bit 4: Loop Back mode.

TX

Bits 5-6: Loop Back mode.

RX

Bit 7: Control of Transmit Pin.

RWD

FDCAN RAM Watchdog Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDV
r
WDC
rw
Toggle fields

WDC

Bits 0-7: Watchdog configuration.

WDV

Bits 8-15: Watchdog value.

CCCR

FDCAN CC Control Register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NISO
rw
TXP
rw
EFBI
rw
PXHD
rw
BSE
rw
FDOE
rw
TEST
rw
DAR
rw
MON
rw
CSR
rw
CSA
rw
ASM
rw
CCE
rw
INIT
rw
Toggle fields

INIT

Bit 0: Initialization.

CCE

Bit 1: Configuration Change Enable.

ASM

Bit 2: ASM Restricted Operation Mode.

CSA

Bit 3: Clock Stop Acknowledge.

CSR

Bit 4: Clock Stop Request.

MON

Bit 5: Bus Monitoring Mode.

DAR

Bit 6: Disable Automatic Retransmission.

TEST

Bit 7: Test Mode Enable.

FDOE

Bit 8: FD Operation Enable.

BSE

Bit 9: FDCAN Bit Rate Switching.

PXHD

Bit 12: Protocol Exception Handling Disable.

EFBI

Bit 13: Edge Filtering during Bus Integration.

TXP

Bit 14: TXP.

NISO

Bit 15: Non ISO Operation.

NBTP

FDCAN Nominal Bit Timing and Prescaler Register

Offset: 0x1c, size: 32, reset: 0x00000A33, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSJW
rw
NBRP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NTSEG1
rw
NTSEG2
rw
Toggle fields

NTSEG2

Bits 0-6: Nominal Time segment after sample point.

NTSEG1

Bits 8-15: Nominal Time segment before sample point.

NBRP

Bits 16-24: Bit Rate Prescaler.

NSJW

Bits 25-31: NSJW: Nominal (Re)Synchronization Jump Width.

TSCC

FDCAN Timestamp Counter Configuration Register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSS
rw
Toggle fields

TSS

Bits 0-1: Timestamp Select.

TCP

Bits 16-19: Timestamp Counter Prescaler.

TSCV

FDCAN Timestamp Counter Value Register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSC
rw
Toggle fields

TSC

Bits 0-15: Timestamp Counter.

TOCC

FDCAN Timeout Counter Configuration Register

Offset: 0x28, size: 32, reset: 0xFFFF0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TOP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOS
rw
ETOC
rw
Toggle fields

ETOC

Bit 0: Enable Timeout Counter.

TOS

Bits 1-2: Timeout Select.

TOP

Bits 16-31: Timeout Period.

TOCV

FDCAN Timeout Counter Value Register

Offset: 0x2c, size: 32, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOC
rw
Toggle fields

TOC

Bits 0-15: Timeout Counter.

ECR

FDCAN Error Counter Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RP
rw
REC
rw
TEC
rw
Toggle fields

TEC

Bits 0-7: Transmit Error Counter.

REC

Bits 8-14: Receive Error Counter.

RP

Bit 15: Receive Error Passive.

CEL

Bits 16-23: AN Error Logging.

PSR

FDCAN Protocol Status Register

Offset: 0x44, size: 32, reset: 0x00000707, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDCV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PXE
rw
REDL
rw
RBRS
rw
RESI
rw
DLEC
rw
BO
rw
EW
rw
EP
rw
ACT
rw
LEC
rw
Toggle fields

LEC

Bits 0-2: Last Error Code.

ACT

Bits 3-4: Activity.

EP

Bit 5: Error Passive.

EW

Bit 6: Warning Status.

BO

Bit 7: Bus_Off Status.

DLEC

Bits 8-10: Data Last Error Code.

RESI

Bit 11: ESI flag of last received FDCAN Message.

RBRS

Bit 12: BRS flag of last received FDCAN Message.

REDL

Bit 13: Received FDCAN Message.

PXE

Bit 14: Protocol Exception Event.

TDCV

Bits 16-22: Transmitter Delay Compensation Value.

TDCR

FDCAN Transmitter Delay Compensation Register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDCO
rw
TDCF
rw
Toggle fields

TDCF

Bits 0-6: Transmitter Delay Compensation Filter Window Length.

TDCO

Bits 8-14: Transmitter Delay Compensation Offset.

IR

FDCAN Interrupt Register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARA
rw
PED
rw
PEA
rw
WDI
rw
BO
rw
EW
rw
EP
rw
ELO
rw
DRX
rw
TOO
rw
MRAF
rw
TSW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEFL
rw
TEFF
rw
TEFW
rw
TEFN
rw
TEF
rw
TCF
rw
TC
rw
HPM
rw
RF1L
rw
RF1F
rw
RF1W
rw
RF1N
rw
RF0L
rw
RF0F
rw
RF0W
rw
RF0N
rw
Toggle fields

RF0N

Bit 0: Rx FIFO 0 New Message.

RF0W

Bit 1: Rx FIFO 0 Full.

RF0F

Bit 2: Rx FIFO 0 Full.

RF0L

Bit 3: Rx FIFO 0 Message Lost.

RF1N

Bit 4: Rx FIFO 1 New Message.

RF1W

Bit 5: Rx FIFO 1 Watermark Reached.

RF1F

Bit 6: Rx FIFO 1 Watermark Reached.

RF1L

Bit 7: Rx FIFO 1 Message Lost.

HPM

Bit 8: High Priority Message.

TC

Bit 9: Transmission Completed.

TCF

Bit 10: Transmission Cancellation Finished.

TEF

Bit 11: Tx FIFO Empty.

TEFN

Bit 12: Tx Event FIFO New Entry.

TEFW

Bit 13: Tx Event FIFO Watermark Reached.

TEFF

Bit 14: Tx Event FIFO Full.

TEFL

Bit 15: Tx Event FIFO Element Lost.

TSW

Bit 16: Timestamp Wraparound.

MRAF

Bit 17: Message RAM Access Failure.

TOO

Bit 18: Timeout Occurred.

DRX

Bit 19: Message stored to Dedicated Rx Buffer.

ELO

Bit 22: Error Logging Overflow.

EP

Bit 23: Error Passive.

EW

Bit 24: Warning Status.

BO

Bit 25: Bus_Off Status.

WDI

Bit 26: Watchdog Interrupt.

PEA

Bit 27: Protocol Error in Arbitration Phase (Nominal Bit Time is used).

PED

Bit 28: Protocol Error in Data Phase (Data Bit Time is used).

ARA

Bit 29: Access to Reserved Address.

IE

FDCAN Interrupt Enable Register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/30 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARAE
rw
PEDE
rw
PEAE
rw
WDIE
rw
BOE
rw
EWE
rw
EPE
rw
ELOE
rw
BEUE
rw
BECE
rw
DRXE
rw
TOOE
rw
MRAFE
rw
TSWE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEFLE
rw
TEFFE
rw
TEFWE
rw
TEFNE
rw
TEFE
rw
TCFE
rw
TCE
rw
HPME
rw
RF1LE
rw
RF1FE
rw
RF1WE
rw
RF1NE
rw
RF0LE
rw
RF0FE
rw
RF0WE
rw
RF0NE
rw
Toggle fields

RF0NE

Bit 0: Rx FIFO 0 New Message Enable.

RF0WE

Bit 1: Rx FIFO 0 Full Enable.

RF0FE

Bit 2: Rx FIFO 0 Full Enable.

RF0LE

Bit 3: Rx FIFO 0 Message Lost Enable.

RF1NE

Bit 4: Rx FIFO 1 New Message Enable.

RF1WE

Bit 5: Rx FIFO 1 Watermark Reached Enable.

RF1FE

Bit 6: Rx FIFO 1 Watermark Reached Enable.

RF1LE

Bit 7: Rx FIFO 1 Message Lost Enable.

HPME

Bit 8: High Priority Message Enable.

TCE

Bit 9: Transmission Completed Enable.

TCFE

Bit 10: Transmission Cancellation Finished Enable.

TEFE

Bit 11: Tx FIFO Empty Enable.

TEFNE

Bit 12: Tx Event FIFO New Entry Enable.

TEFWE

Bit 13: Tx Event FIFO Watermark Reached Enable.

TEFFE

Bit 14: Tx Event FIFO Full Enable.

TEFLE

Bit 15: Tx Event FIFO Element Lost Enable.

TSWE

Bit 16: Timestamp Wraparound Enable.

MRAFE

Bit 17: Message RAM Access Failure Enable.

TOOE

Bit 18: Timeout Occurred Enable.

DRXE

Bit 19: Message stored to Dedicated Rx Buffer Enable.

BECE

Bit 20: Bit Error Corrected Interrupt Enable.

BEUE

Bit 21: Bit Error Uncorrected Interrupt Enable.

ELOE

Bit 22: Error Logging Overflow Enable.

EPE

Bit 23: Error Passive Enable.

EWE

Bit 24: Warning Status Enable.

BOE

Bit 25: Bus_Off Status Enable.

WDIE

Bit 26: Watchdog Interrupt Enable.

PEAE

Bit 27: Protocol Error in Arbitration Phase Enable.

PEDE

Bit 28: Protocol Error in Data Phase Enable.

ARAE

Bit 29: Access to Reserved Address Enable.

ILS

FDCAN Interrupt Line Select Register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/30 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARAL
rw
PEDL
rw
PEAL
rw
WDIL
rw
BOL
rw
EWL
rw
EPL
rw
ELOL
rw
BEUL
rw
BECL
rw
DRXL
rw
TOOL
rw
MRAFL
rw
TSWL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEFLL
rw
TEFFL
rw
TEFWL
rw
TEFNL
rw
TEFL
rw
TCFL
rw
TCL
rw
HPML
rw
RF1LL
rw
RF1FL
rw
RF1WL
rw
RF1NL
rw
RF0LL
rw
RF0FL
rw
RF0WL
rw
RF0NL
rw
Toggle fields

RF0NL

Bit 0: Rx FIFO 0 New Message Interrupt Line.

RF0WL

Bit 1: Rx FIFO 0 Watermark Reached Interrupt Line.

RF0FL

Bit 2: Rx FIFO 0 Full Interrupt Line.

RF0LL

Bit 3: Rx FIFO 0 Message Lost Interrupt Line.

RF1NL

Bit 4: Rx FIFO 1 New Message Interrupt Line.

RF1WL

Bit 5: Rx FIFO 1 Watermark Reached Interrupt Line.

RF1FL

Bit 6: Rx FIFO 1 Full Interrupt Line.

RF1LL

Bit 7: Rx FIFO 1 Message Lost Interrupt Line.

HPML

Bit 8: High Priority Message Interrupt Line.

TCL

Bit 9: Transmission Completed Interrupt Line.

TCFL

Bit 10: Transmission Cancellation Finished Interrupt Line.

TEFL

Bit 11: Tx FIFO Empty Interrupt Line.

TEFNL

Bit 12: Tx Event FIFO New Entry Interrupt Line.

TEFWL

Bit 13: Tx Event FIFO Watermark Reached Interrupt Line.

TEFFL

Bit 14: Tx Event FIFO Full Interrupt Line.

TEFLL

Bit 15: Tx Event FIFO Element Lost Interrupt Line.

TSWL

Bit 16: Timestamp Wraparound Interrupt Line.

MRAFL

Bit 17: Message RAM Access Failure Interrupt Line.

TOOL

Bit 18: Timeout Occurred Interrupt Line.

DRXL

Bit 19: Message stored to Dedicated Rx Buffer Interrupt Line.

BECL

Bit 20: Bit Error Corrected Interrupt Line.

BEUL

Bit 21: Bit Error Uncorrected Interrupt Line.

ELOL

Bit 22: Error Logging Overflow Interrupt Line.

EPL

Bit 23: Error Passive Interrupt Line.

EWL

Bit 24: Warning Status Interrupt Line.

BOL

Bit 25: Bus_Off Status.

WDIL

Bit 26: Watchdog Interrupt Line.

PEAL

Bit 27: Protocol Error in Arbitration Phase Line.

PEDL

Bit 28: Protocol Error in Data Phase Line.

ARAL

Bit 29: Access to Reserved Address Line.

ILE

FDCAN Interrupt Line Enable Register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EINT1
rw
EINT0
rw
Toggle fields

EINT0

Bit 0: Enable Interrupt Line 0.

EINT1

Bit 1: Enable Interrupt Line 1.

GFC

FDCAN Global Filter Configuration Register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ANFS
rw
ANFE
rw
RRFS
rw
RRFE
rw
Toggle fields

RRFE

Bit 0: Reject Remote Frames Extended.

RRFS

Bit 1: Reject Remote Frames Standard.

ANFE

Bits 2-3: Accept Non-matching Frames Extended.

ANFS

Bits 4-5: Accept Non-matching Frames Standard.

SIDFC

FDCAN Standard ID Filter Configuration Register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLSSA
rw
Toggle fields

FLSSA

Bits 2-15: Filter List Standard Start Address.

LSS

Bits 16-23: List Size Standard.

XIDFC

FDCAN Extended ID Filter Configuration Register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LSE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLESA
rw
Toggle fields

FLESA

Bits 2-15: Filter List Standard Start Address.

LSE

Bits 16-23: List Size Extended.

XIDAM

FDCAN Extended ID and Mask Register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EIDM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EIDM
rw
Toggle fields

EIDM

Bits 0-28: Extended ID Mask.

HPMS

FDCAN High Priority Message Status Register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLST
r
FIDX
r
MSI
r
BIDX
r
Toggle fields

BIDX

Bits 0-5: Buffer Index.

MSI

Bits 6-7: Message Storage Indicator.

FIDX

Bits 8-14: Filter Index.

FLST

Bit 15: Filter List.

NDAT1

FDCAN New Data 1 Register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ND31
rw
ND30
rw
ND29
rw
ND28
rw
ND27
rw
ND26
rw
ND25
rw
ND24
rw
ND23
rw
ND22
rw
ND21
rw
ND20
rw
ND19
rw
ND18
rw
ND17
rw
ND16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ND15
rw
ND14
rw
ND13
rw
ND12
rw
ND11
rw
ND10
rw
ND9
rw
ND8
rw
ND7
rw
ND6
rw
ND5
rw
ND4
rw
ND3
rw
ND2
rw
ND1
rw
ND0
rw
Toggle fields

ND0

Bit 0: New data.

ND1

Bit 1: New data.

ND2

Bit 2: New data.

ND3

Bit 3: New data.

ND4

Bit 4: New data.

ND5

Bit 5: New data.

ND6

Bit 6: New data.

ND7

Bit 7: New data.

ND8

Bit 8: New data.

ND9

Bit 9: New data.

ND10

Bit 10: New data.

ND11

Bit 11: New data.

ND12

Bit 12: New data.

ND13

Bit 13: New data.

ND14

Bit 14: New data.

ND15

Bit 15: New data.

ND16

Bit 16: New data.

ND17

Bit 17: New data.

ND18

Bit 18: New data.

ND19

Bit 19: New data.

ND20

Bit 20: New data.

ND21

Bit 21: New data.

ND22

Bit 22: New data.

ND23

Bit 23: New data.

ND24

Bit 24: New data.

ND25

Bit 25: New data.

ND26

Bit 26: New data.

ND27

Bit 27: New data.

ND28

Bit 28: New data.

ND29

Bit 29: New data.

ND30

Bit 30: New data.

ND31

Bit 31: New data.

NDAT2

FDCAN New Data 2 Register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ND63
rw
ND62
rw
ND61
rw
ND60
rw
ND59
rw
ND58
rw
ND57
rw
ND56
rw
ND55
rw
ND54
rw
ND53
rw
ND52
rw
ND51
rw
ND50
rw
ND49
rw
ND48
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ND47
rw
ND46
rw
ND45
rw
ND44
rw
ND43
rw
ND42
rw
ND41
rw
ND40
rw
ND39
rw
ND38
rw
ND37
rw
ND36
rw
ND35
rw
ND34
rw
ND33
rw
ND32
rw
Toggle fields

ND32

Bit 0: New data.

ND33

Bit 1: New data.

ND34

Bit 2: New data.

ND35

Bit 3: New data.

ND36

Bit 4: New data.

ND37

Bit 5: New data.

ND38

Bit 6: New data.

ND39

Bit 7: New data.

ND40

Bit 8: New data.

ND41

Bit 9: New data.

ND42

Bit 10: New data.

ND43

Bit 11: New data.

ND44

Bit 12: New data.

ND45

Bit 13: New data.

ND46

Bit 14: New data.

ND47

Bit 15: New data.

ND48

Bit 16: New data.

ND49

Bit 17: New data.

ND50

Bit 18: New data.

ND51

Bit 19: New data.

ND52

Bit 20: New data.

ND53

Bit 21: New data.

ND54

Bit 22: New data.

ND55

Bit 23: New data.

ND56

Bit 24: New data.

ND57

Bit 25: New data.

ND58

Bit 26: New data.

ND59

Bit 27: New data.

ND60

Bit 28: New data.

ND61

Bit 29: New data.

ND62

Bit 30: New data.

ND63

Bit 31: New data.

RXF0C

FDCAN Rx FIFO 0 Configuration Register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
F0OM
rw
F0WM
rw
F0S
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F0SA
rw
Toggle fields

F0SA

Bits 2-15: Rx FIFO 0 Start Address.

F0S

Bits 16-22: Rx FIFO 0 Size.

F0WM

Bits 24-30: FIFO 0 Watermark.

F0OM

Bit 31: FIFO 0 operation mode.

RXF0S

FDCAN Rx FIFO 0 Status Register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RF0L
rw
F0F
rw
F0PI
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F0GI
rw
F0FL
rw
Toggle fields

F0FL

Bits 0-6: Rx FIFO 0 Fill Level.

F0GI

Bits 8-13: Rx FIFO 0 Get Index.

F0PI

Bits 16-21: Rx FIFO 0 Put Index.

F0F

Bit 24: Rx FIFO 0 Full.

RF0L

Bit 25: Rx FIFO 0 Message Lost.

RXF0A

CAN Rx FIFO 0 Acknowledge Register

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F0AI
rw
Toggle fields

F0AI

Bits 0-5: Rx FIFO 0 Acknowledge Index.

RXBC

FDCAN Rx Buffer Configuration Register

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RBSA
rw
Toggle fields

RBSA

Bits 2-15: Rx Buffer Start Address.

RXF1C

FDCAN Rx FIFO 1 Configuration Register

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
F1OM
rw
F1WM
rw
F1S
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F1SA
rw
Toggle fields

F1SA

Bits 2-15: Rx FIFO 1 Start Address.

F1S

Bits 16-22: Rx FIFO 1 Size.

F1WM

Bits 24-30: Rx FIFO 1 Watermark.

F1OM

Bit 31: FIFO 1 operation mode.

RXF1S

FDCAN Rx FIFO 1 Status Register

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMS
rw
RF1L
rw
F1F
rw
F1PI
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F1GI
rw
F1FL
rw
Toggle fields

F1FL

Bits 0-6: Rx FIFO 1 Fill Level.

F1GI

Bits 8-14: Rx FIFO 1 Get Index.

F1PI

Bits 16-22: Rx FIFO 1 Put Index.

F1F

Bit 24: Rx FIFO 1 Full.

RF1L

Bit 25: Rx FIFO 1 Message Lost.

DMS

Bits 30-31: Debug Message Status.

RXF1A

FDCAN Rx FIFO 1 Acknowledge Register

Offset: 0xb8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F1AI
rw
Toggle fields

F1AI

Bits 0-5: Rx FIFO 1 Acknowledge Index.

RXESC

FDCAN Rx Buffer Element Size Configuration Register

Offset: 0xbc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RBDS
rw
F1DS
rw
F0DS
rw
Toggle fields

F0DS

Bits 0-2: Rx FIFO 1 Data Field Size:.

F1DS

Bits 4-6: Rx FIFO 0 Data Field Size:.

RBDS

Bits 8-10: Rx Buffer Data Field Size:.

TXBC

FDCAN Tx Buffer Configuration Register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TFQM
rw
TFQS
rw
NDTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBSA
rw
Toggle fields

TBSA

Bits 2-15: Tx Buffers Start Address.

NDTB

Bits 16-21: Number of Dedicated Transmit Buffers.

TFQS

Bits 24-29: Transmit FIFO/Queue Size.

TFQM

Bit 30: Tx FIFO/Queue Mode.

TXFQS

FDCAN Tx FIFO/Queue Status Register

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TFQF
r
TFQPI
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TFGI
r
TFFL
r
Toggle fields

TFFL

Bits 0-5: Tx FIFO Free Level.

TFGI

Bits 8-12: TFGI.

TFQPI

Bits 16-20: Tx FIFO/Queue Put Index.

TFQF

Bit 21: Tx FIFO/Queue Full.

TXESC

FDCAN Tx Buffer Element Size Configuration Register

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBDS
rw
Toggle fields

TBDS

Bits 0-2: Tx Buffer Data Field Size:.

TXBRP

FDCAN Tx Buffer Request Pending Register

Offset: 0xcc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TRP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRP
r
Toggle fields

TRP

Bits 0-31: Transmission Request Pending.

TXBAR

FDCAN Tx Buffer Add Request Register

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AR
rw
Toggle fields

AR

Bits 0-31: Add Request.

TXBCR

FDCAN Tx Buffer Cancellation Request Register

Offset: 0xd4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR
rw
Toggle fields

CR

Bits 0-31: Cancellation Request.

TXBTO

FDCAN Tx Buffer Transmission Occurred Register

Offset: 0xd8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TO
rw
Toggle fields

TO

Bits 0-31: Transmission Occurred..

TXBCF

FDCAN Tx Buffer Cancellation Finished Register

Offset: 0xdc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CF
r
Toggle fields

CF

Bits 0-31: Cancellation Finished.

TXBTIE

FDCAN Tx Buffer Transmission Interrupt Enable Register

Offset: 0xe0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIE
rw
Toggle fields

TIE

Bits 0-31: Transmission Interrupt Enable.

TXBCIE

FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register

Offset: 0xe4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CF
rw
Toggle fields

CF

Bits 0-31: Cancellation Finished Interrupt Enable.

TXEFC

FDCAN Tx Event FIFO Configuration Register

Offset: 0xf0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EFWM
rw
EFS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFSA
rw
Toggle fields

EFSA

Bits 2-15: Event FIFO Start Address.

EFS

Bits 16-21: Event FIFO Size.

EFWM

Bits 24-29: Event FIFO Watermark.

TXEFS

FDCAN Tx Event FIFO Status Register

Offset: 0xf4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEFL
rw
EFF
rw
EFPI
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFGI
rw
EFFL
rw
Toggle fields

EFFL

Bits 0-5: Event FIFO Fill Level.

EFGI

Bits 8-12: Event FIFO Get Index..

EFPI

Bits 16-20: Event FIFO put index..

EFF

Bit 24: Event FIFO Full..

TEFL

Bit 25: Tx Event FIFO Element Lost..

TXEFA

FDCAN Tx Event FIFO Acknowledge Register

Offset: 0xf8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFAI
rw
Toggle fields

EFAI

Bits 0-4: Event FIFO Acknowledge Index.

TTTMC

FDCAN TT Trigger Memory Configuration Register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMSA
rw
Toggle fields

TMSA

Bits 2-15: Trigger Memory Start Address.

TME

Bits 16-22: Trigger Memory Elements.

TTRMC

FDCAN TT Reference Message Configuration Register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RMPS
rw
XTD
rw
RID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RID
rw
Toggle fields

RID

Bits 0-28: Reference Identifier..

XTD

Bit 30: Extended Identifier.

RMPS

Bit 31: Reference Message Payload Select.

TTOCF

FDCAN TT Operation Configuration Register

Offset: 0x108, size: 32, reset: 0x00010000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EVTP
rw
ECC
rw
EGTF
rw
AWL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EECS
rw
IRTO
rw
LDSDL
rw
TM
rw
GEN
rw
OM
rw
Toggle fields

OM

Bits 0-1: Operation Mode.

GEN

Bit 3: Gap Enable.

TM

Bit 4: Time Master.

LDSDL

Bits 5-7: LD of Synchronization Deviation Limit.

IRTO

Bits 8-14: Initial Reference Trigger Offset.

EECS

Bit 15: Enable External Clock Synchronization.

AWL

Bits 16-23: Application Watchdog Limit.

EGTF

Bit 24: Enable Global Time Filtering.

ECC

Bit 25: Enable Clock Calibration.

EVTP

Bit 26: Event Trigger Polarity.

TTMLM

FDCAN TT Matrix Limits Register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENTT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXEW
rw
CSS
rw
CCM
rw
Toggle fields

CCM

Bits 0-5: Cycle Count Max.

CSS

Bits 6-7: Cycle Start Synchronization.

TXEW

Bits 8-11: Tx Enable Window.

ENTT

Bits 16-27: Expected Number of Tx Triggers.

TURCF

FDCAN TUR Configuration Register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ELT
rw
DC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NCL
rw
Toggle fields

NCL

Bits 0-15: Numerator Configuration Low..

DC

Bits 16-29: Denominator Configuration..

ELT

Bit 31: Enable Local Time.

TTOCN

FDCAN TT Operation Control Register

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCKC
rw
ESCN
rw
NIG
rw
TMG
rw
FGP
rw
GCS
rw
TTIE
rw
TMC
rw
RTIE
rw
SWS
rw
SWP
rw
ECS
rw
SGT
rw
Toggle fields

SGT

Bit 0: Set Global time.

ECS

Bit 1: External Clock Synchronization.

SWP

Bit 2: Stop Watch Polarity.

SWS

Bits 3-4: Stop Watch Source..

RTIE

Bit 5: Register Time Mark Interrupt Pulse Enable.

TMC

Bits 6-7: Register Time Mark Compare.

TTIE

Bit 8: Trigger Time Mark Interrupt Pulse Enable.

GCS

Bit 9: Gap Control Select.

FGP

Bit 10: Finish Gap..

TMG

Bit 11: Time Mark Gap.

NIG

Bit 12: Next is Gap.

ESCN

Bit 13: External Synchronization Control.

LCKC

Bit 15: TT Operation Control Register Locked.

TTGTP

FDCAN TT Global Time Preset Register

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NCL
rw
Toggle fields

NCL

Bits 0-15: Time Preset.

CTP

Bits 16-31: Cycle Time Target Phase.

TTTMK

FDCAN TT Time Mark Register

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKM
rw
TICC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TM
rw
Toggle fields

TM

Bits 0-15: Time Mark.

TICC

Bits 16-22: Time Mark Cycle Code.

LCKM

Bit 31: TT Time Mark Register Locked.

TTIR

FDCAN TT Interrupt Register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CER
rw
AW
rw
WT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IWTG
rw
ELC
rw
SE2
rw
SE1
rw
TXO
rw
TXU
rw
GTE
rw
GTD
rw
GTW
rw
SWE
rw
TTMI
rw
RTMI
rw
SOG
rw
CSM
rw
SMC
rw
SBC
rw
Toggle fields

SBC

Bit 0: Start of Basic Cycle.

SMC

Bit 1: Start of Matrix Cycle.

CSM

Bit 2: Change of Synchronization Mode.

SOG

Bit 3: Start of Gap.

RTMI

Bit 4: Register Time Mark Interrupt..

TTMI

Bit 5: Trigger Time Mark Event Internal.

SWE

Bit 6: Stop Watch Event.

GTW

Bit 7: Global Time Wrap.

GTD

Bit 8: Global Time Discontinuity.

GTE

Bit 9: Global Time Error.

TXU

Bit 10: Tx Count Underflow.

TXO

Bit 11: Tx Count Overflow.

SE1

Bit 12: Scheduling Error 1.

SE2

Bit 13: Scheduling Error 2.

ELC

Bit 14: Error Level Changed..

IWTG

Bit 15: Initialization Watch Trigger.

WT

Bit 16: Watch Trigger.

AW

Bit 17: Application Watchdog.

CER

Bit 18: Configuration Error.

TTIE

FDCAN TT Interrupt Enable Register

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CERE
rw
AWE
rw
WTE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IWTGE
rw
ELCE
rw
SE2E
rw
SE1E
rw
TXOE
rw
TXUE
rw
GTEE
rw
GTDE
rw
GTWE
rw
SWEE
rw
TTMIE
rw
RTMIE
rw
SOGE
rw
CSME
rw
SMCE
rw
SBCE
rw
Toggle fields

SBCE

Bit 0: Start of Basic Cycle Interrupt Enable.

SMCE

Bit 1: Start of Matrix Cycle Interrupt Enable.

CSME

Bit 2: Change of Synchronization Mode Interrupt Enable.

SOGE

Bit 3: Start of Gap Interrupt Enable.

RTMIE

Bit 4: Register Time Mark Interrupt Enable.

TTMIE

Bit 5: Trigger Time Mark Event Internal Interrupt Enable.

SWEE

Bit 6: Stop Watch Event Interrupt Enable.

GTWE

Bit 7: Global Time Wrap Interrupt Enable.

GTDE

Bit 8: Global Time Discontinuity Interrupt Enable.

GTEE

Bit 9: Global Time Error Interrupt Enable.

TXUE

Bit 10: Tx Count Underflow Interrupt Enable.

TXOE

Bit 11: Tx Count Overflow Interrupt Enable.

SE1E

Bit 12: Scheduling Error 1 Interrupt Enable.

SE2E

Bit 13: Scheduling Error 2 Interrupt Enable.

ELCE

Bit 14: Change Error Level Interrupt Enable.

IWTGE

Bit 15: Initialization Watch Trigger Interrupt Enable.

WTE

Bit 16: Watch Trigger Interrupt Enable.

AWE

Bit 17: Application Watchdog Interrupt Enable.

CERE

Bit 18: Configuration Error Interrupt Enable.

TTILS

FDCAN TT Interrupt Line Select Register

Offset: 0x128, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CERL
rw
AWL
rw
WTL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IWTGL
rw
ELCL
rw
SE2L
rw
SE1L
rw
TXOL
rw
TXUL
rw
GTEL
rw
GTDL
rw
GTWL
rw
SWEL
rw
TTMIL
rw
RTMIL
rw
SOGL
rw
CSML
rw
SMCL
rw
SBCL
rw
Toggle fields

SBCL

Bit 0: Start of Basic Cycle Interrupt Line.

SMCL

Bit 1: Start of Matrix Cycle Interrupt Line.

CSML

Bit 2: Change of Synchronization Mode Interrupt Line.

SOGL

Bit 3: Start of Gap Interrupt Line.

RTMIL

Bit 4: Register Time Mark Interrupt Line.

TTMIL

Bit 5: Trigger Time Mark Event Internal Interrupt Line.

SWEL

Bit 6: Stop Watch Event Interrupt Line.

GTWL

Bit 7: Global Time Wrap Interrupt Line.

GTDL

Bit 8: Global Time Discontinuity Interrupt Line.

GTEL

Bit 9: Global Time Error Interrupt Line.

TXUL

Bit 10: Tx Count Underflow Interrupt Line.

TXOL

Bit 11: Tx Count Overflow Interrupt Line.

SE1L

Bit 12: Scheduling Error 1 Interrupt Line.

SE2L

Bit 13: Scheduling Error 2 Interrupt Line.

ELCL

Bit 14: Change Error Level Interrupt Line.

IWTGL

Bit 15: Initialization Watch Trigger Interrupt Line.

WTL

Bit 16: Watch Trigger Interrupt Line.

AWL

Bit 17: Application Watchdog Interrupt Line.

CERL

Bit 18: Configuration Error Interrupt Line.

TTOST

FDCAN TT Operation Status Register

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-only

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPL
r
WECS
r
AWE
r
WFE
r
GSI
r
TMP
r
GFI
r
WGTD
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
r
QCS
r
QGTP
r
SYS
r
MS
r
EL
r
Toggle fields

EL

Bits 0-1: Error Level.

MS

Bits 2-3: Master State..

SYS

Bits 4-5: Synchronization State.

QGTP

Bit 6: Quality of Global Time Phase.

QCS

Bit 7: Quality of Clock Speed.

RTO

Bits 8-15: Reference Trigger Offset.

WGTD

Bit 22: Wait for Global Time Discontinuity.

GFI

Bit 23: Gap Finished Indicator..

TMP

Bits 24-26: Time Master Priority.

GSI

Bit 27: Gap Started Indicator..

WFE

Bit 28: Wait for Event.

AWE

Bit 29: Application Watchdog Event.

WECS

Bit 30: Wait for External Clock Synchronization.

SPL

Bit 31: Schedule Phase Lock.

TURNA

FDCAN TUR Numerator Actual Register

Offset: 0x130, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NAV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAV
r
Toggle fields

NAV

Bits 0-17: Numerator Actual Value.

TTLGT

FDCAN TT Local and Global Time Register

Offset: 0x134, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT
r
Toggle fields

LT

Bits 0-15: Local Time.

GT

Bits 16-31: Global Time.

TTCTC

FDCAN TT Cycle Time and Count Register

Offset: 0x138, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CT
r
Toggle fields

CT

Bits 0-15: Cycle Time.

CC

Bits 16-21: Cycle Count.

TTCPT

FDCAN TT Capture Time Register

Offset: 0x13c, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCV
r
Toggle fields

CCV

Bits 0-5: Cycle Count Value.

SWV

Bits 16-31: Stop Watch Value.

TTCSM

FDCAN TT Cycle Sync Mark Register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSM
r
Toggle fields

CSM

Bits 0-15: Cycle Sync Mark.

TTTS

FDCAN TT Trigger Select Register

Offset: 0x300, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EVTSEL
rw
SWTDEL
rw
Toggle fields

SWTDEL

Bits 0-1: Stop watch trigger input selection.

EVTSEL

Bits 4-5: Event trigger input selection.

FLASH

0x52002000: Embedded Flash memory

59/227 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ACR
0x4 KEYR [1]
0x8 OPTKEYR
0xc CR [1]
0x10 SR [1]
0x14 CCR [1]
0x18 OPTCR
0x1c OPTSR_CUR
0x20 OPTSR_PRG
0x24 OPTCCR
0x28 PRAR_CUR [1]
0x2c PRAR_PRG [1]
0x30 SCAR_CUR [1]
0x34 SCAR_PRG [1]
0x38 WPSN_CURR [1]
0x3c WPSN_PRGR [1]
0x40 BOOT_CURR
0x44 BOOT_PRGR
0x50 CRCCR [1]
0x54 CRCSADDR [1]
0x58 CRCEADDR [1]
0x5c CRCDATAR
0x60 FAR [1]
0x68 OTPBL_CUR
0x6c OTPBL_PRG
0x100 ACR_
0x104 KEYR [2]
0x108 OPTKEYR_
0x10c CR [2]
0x110 SR [2]
0x114 CCR [2]
0x118 OPTCR_
0x11c OPTSR_CUR_
0x120 OPTSR_PRG_
0x124 OPTCCR_
0x128 PRAR_CUR [2]
0x12c PRAR_PRG [2]
0x130 SCAR_CUR [2]
0x134 SCAR_PRG [2]
0x138 WPSN_CURR [2]
0x13c WPSN_PRGR [2]
0x140 BOOT_CURR_
0x144 BOOT_PRGR_
0x150 CRCCR [2]
0x154 CRCSADDR [2]
0x158 CRCEADDR [2]
0x160 FAR [2]
Toggle registers

ACR

Access control register

Offset: 0x0, size: 32, reset: 0x00000013, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRHIGHFREQ
rw
LATENCY
rw
Toggle fields

LATENCY

Bits 0-3: Read latency.

WRHIGHFREQ

Bits 4-5: Flash signal delay.

KEYR [1]

FLASH key register for bank 1

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY1R
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY1R
w
Toggle fields

KEY1R

Bits 0-31: Non-volatile memory bank 1 configuration access unlock key.

OPTKEYR

FLASH option key register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPTKEYR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPTKEYR
w
Toggle fields

OPTKEYR

Bits 0-31: Unlock key option bytes.

CR [1]

Offset: 0xc, size: 32, reset: 0x00000001, access: Unspecified

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRCRDERRIE
rw
CRCENDIE
rw
DBECCERRIE
rw
SNECCERRIE
rw
RDSERRIE
rw
RDPERRIE
rw
INCERRIE
rw
STRBERRIE
rw
PGSERRIE
rw
WRPERRIE
rw
EOPIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRC_EN
rw
SSN
rw
START
rw
FW
rw
BER
rw
SER
rw
PG
rw
LOCK
rw
Toggle fields

LOCK

Bit 0: Bank 1 configuration lock bit This bit locks the FLASH_CR1 register. The correct write sequence to FLASH_KEYR1 register unlocks this bit. If a wrong sequence is executed, or if the unlock sequence to FLASH_KEYR1 is performed twice, this bit remains locked until the next system reset. LOCK1 can be set by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When LOCK1 changes from 0 to 1, the other bits of FLASH_CR1 register do not change..

PG

Bit 1: Bank 1 internal buffer control bit Setting PG1 bit to 1 enables internal buffer for write operations to bank 1. This allows preparing program operations even if a sector or bank erase is ongoing. PG1 can be programmed only when LOCK1 is cleared to 0. When PG1 is reset, the internal buffer is disabled for write operations to bank 1, and all the data stored in the buffer but not sent to the operation queue are lost..

SER

Bit 2: Bank 1 sector erase request Setting SER1 bit to 1 requests a sector erase on bank 1. SER1 can be programmed only when LOCK1 is cleared to 0. BER1 has a higher priority than SER1: if both bits are set, the embedded Flash memory executes a bank erase. Note: Write protection error is triggered when a sector erase is required on a protected sector..

BER

Bit 3: Bank 1 erase request Setting BER1 bit to 1 requests a bank erase operation on bank 1 (user Flash memory only). BER1 can be programmed only when LOCK1 is cleared to 0. BER1 has a higher priority than SER1: if both are set, the embedded Flash memory executes a bank erase. Note: Write protection error is triggered when a bank erase is required and some sectors are protected..

FW

Bit 4: Bank 1 write forcing control bit FW1 forces a write operation even if the write buffer is not full. In this case all bits not written are set to 1 by hardware. FW1 can be programmed only when LOCK1 is cleared to 0. The embedded Flash memory resets FW1 when the corresponding operation has been acknowledged. Note: Using a force-write operation prevents the application from updating later the missing bits with something else than 1, because it is likely that it will lead to permanent ECC error. Write forcing is effective only if the write buffer is not empty (in particular, FW1 does not start several write operations when the force-write operations are performed consecutively)..

START

Bit 5: Bank 1 erase start control bit START1 bit is used to start a sector erase or a bank erase operation. START1 can be programmed only when LOCK1 is cleared to 0. The embedded Flash memory resets START1 when the corresponding operation has been acknowledged. The user application cannot access any embedded Flash memory register until the operation is acknowledged..

SSN

Bits 6-12: Bank 1 sector erase selection number These bits are used to select the target sector for an erase operation (they are unused otherwise). SSN1 can be programmed only when LOCK1 is cleared to 0. .. ... ... Note: Bank 1 is limited to 16 and 64 sectors on STM32H7B0 and STM32H7A3xG devices, respectively..

CRC_EN

Bit 15: Bank 1 CRC control bit Setting CRC_EN bit to 1 enables the CRC calculation on bank 1. CRC_EN does not start CRC calculation but enables CRC configuration through FLASH_CRCCR1 register. When CRC calculation is performed on bank 1, it can only be disabled by setting CRC_EN bit to 0. Resetting CRC_EN clears CRC configuration and resets the content of FLASH_CRCDATAR register. Clearing CRC_EN to 0 sets CRCDATA to 0x0. CRC_EN can be programmed only when LOCK1 is cleared to 0..

EOPIE

Bit 16: Bank 1 end-of-program interrupt control bit Setting EOPIE1 bit to 1 enables the generation of an interrupt at the end of a program operation to bank 1. EOPIE1 can be programmed only when LOCK1 is cleared to 0..

WRPERRIE

Bit 17: Bank 1 write protection error interrupt enable bit When WRPERRIE1 bit is set to 1, an interrupt is generated when a protection error occurs during a program operation to bank 1. WRPERRIE1 can be programmed only when LOCK1 is cleared to 0..

PGSERRIE

Bit 18: Bank 1 programming sequence error interrupt enable bit When PGSERRIE1 bit is set to 1, an interrupt is generated when a sequence error occurs during a program operation to bank 1. PGSERRIE1 can be programmed only when LOCK1 is cleared to 0..

STRBERRIE

Bit 19: Bank 1 strobe error interrupt enable bit When STRBERRIE1 bit is set to 1, an interrupt is generated when a strobe error occurs (the master programs several times the same byte in the write buffer) during a write operation to bank 1. STRBERRIE1 can be programmed only when LOCK1 is cleared to 0..

INCERRIE

Bit 21: Bank 1 inconsistency error interrupt enable bit When INCERRIE1 bit is set to 1, an interrupt is generated when an inconsistency error occurs during a write operation to bank 1. INCERRIE1 can be programmed only when LOCK1 is cleared to 0..

RDPERRIE

Bit 23: Bank 1 read protection error interrupt enable bit When RDPERRIE1 bit is set to 1, an interrupt is generated when a read protection error occurs (access to an address protected by PCROP or by RDP level 1) during a read operation from bank 1. RDPERRIE1 can be programmed only when LOCK1 is cleared to 0..

RDSERRIE

Bit 24: Bank 1 secure error interrupt enable bit When RDSERRIE1 bit is set to 1, an interrupt is generated when a secure error (access to a secure-only protected address) occurs during a read operation from bank 1. RDSERRIE1 can be programmed only when LOCK1 is cleared to 0..

SNECCERRIE

Bit 25: Bank 1 ECC single correction error interrupt enable bit When SNECCERRIE1 bit is set to 1, an interrupt is generated when an ECC single correction error occurs during a read operation from bank 1. SNECCERRIE1 can be programmed only when LOCK1 is cleared to 0..

DBECCERRIE

Bit 26: Bank 1 ECC double detection error interrupt enable bit When DBECCERRIE1 bit is set to 1, an interrupt is generated when an ECC double detection error occurs during a read operation from bank 1. DBECCERRIE1 can be programmed only when LOCK1 is cleared to 0..

CRCENDIE

Bit 27: Bank 1 CRC end of calculation interrupt enable bit When CRCENDIE1 bit is set to 1, an interrupt is generated when the CRC computation has completed on bank 1. CRCENDIE1 can be programmed only when LOCK1 is cleared to 0..

CRCRDERRIE

Bit 28: Bank 1 CRC read error interrupt enable bit When CRCRDERRIE1 bit is set to 1, an interrupt is generated when a protected area (PCROP or secure-only) has been detected during the last CRC computation on bank 1. CRCRDERRIE1 can be programmed only when LOCK1 is cleared to 0..

SR [1]

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRCRDERR
r
CRCEND
r
DBECCERR
r
SNECCERR
r
RDSERR
r
RDPERR
r
INCERR
r
STRBERR
r
PGSERR
r
WRPERR
r
EOP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRC_BUSY
r
QW
r
WBNE
r
BSY
r
Toggle fields

BSY

Bit 0: Bank 1 busy flag BSY1 flag is set when an effective write, erase or option byte change operation is ongoing on bank 1. It is not possible to know what type of operation is being executed. BSY1 cannot be forced to 0. It is automatically reset by hardware every time a step in a write, erase or option byte change operation completes..

WBNE

Bit 1: Bank 1 write buffer not empty flag WBNE1 flag is set when the embedded Flash memory is waiting for new data to complete the write buffer. In this state, the write buffer is not empty. WBNE1 is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below: the application software forces the write operation using FW1 bit in FLASH_CR1 the embedded Flash memory detects an error that involves data loss the application software has disabled write operations in this bank This bit cannot be forced to 0. To reset it, clear the write buffer by performing any of the above listed actions, or send the missing data..

QW

Bit 2: Bank 1 wait queue flag QW1 flag is set when a write, erase or option byte change operation is pending in the command queue buffer of bank 1. It is not possible to know what type of programming operation is present in the queue. This flag is reset by hardware when all write, erase or option byte change operations have been executed and thus removed from the waiting queue(s). This bit cannot be forced to 0. It is reset after a deterministic time if no other operations are requested..

CRC_BUSY

Bit 3: Bank 1 CRC busy flag CRC_BUSY1 flag is set when a CRC calculation is ongoing on bank 1. This bit cannot be forced to 0. The user must wait until the CRC calculation has completed or disable CRC computation on bank 1..

EOP

Bit 16: Bank 1 end-of-program flag EOP1 flag is set when a programming operation to bank 1 completes. An interrupt is generated if the EOPIE1 is set to 1. It is not necessary to reset EOP1 before starting a new operation. EOP1 bit is cleared by writing 1 to CLR_EOP1 bit in FLASH_CCR1 register..

WRPERR

Bit 17: Bank 1 write protection error flag WRPERR1 flag is raised when a protection error occurs during a program operation to bank 1. An interrupt is also generated if the WRPERRIE1 is set to 1. Writing 1 to CLR_WRPERR1 bit in FLASH_CCR1 register clears WRPERR1..

PGSERR

Bit 18: Bank 1 programming sequence error flag PGSERR1 flag is raised when a sequence error occurs on bank 1. An interrupt is generated if the PGSERRIE1 bit is set to 1. Writing 1 to CLR_PGSERR1 bit in FLASH_CCR1 register clears PGSERR1..

STRBERR

Bit 19: Bank 1 strobe error flag STRBERR1 flag is raised when a strobe error occurs on bank 1 (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE1 bit is set to 1. Writing 1 to CLR_STRBERR1 bit in FLASH_CCR1 register clears STRBERR1..

INCERR

Bit 21: Bank 1 inconsistency error flag INCERR1 flag is raised when a inconsistency error occurs on bank 1. An interrupt is generated if INCERRIE1 is set to 1. Writing 1 to CLR_INCERR1 bit in the FLASH_CCR1 register clears INCERR1..

RDPERR

Bit 23: Bank 1 read protection error flag RDPERR1 flag is raised when an read protection error (read access to a PCROP-protected or a RDP-protected area) occurs on bank 1. An interrupt is generated if RDPERRIE1 is set to 1. Writing 1 to CLR_RDPERR1 bit in FLASH_CCR1 register clears RDPERR1..

RDSERR

Bit 24: Bank 1 secure error flag RDSERR1 flag is raised when a read secure error (read access to a secure-only protected word) occurs on bank 1. An interrupt is generated if RDSERRIE1 is set to 1. Writing 1 to CLR_RDSERR1 bit in FLASH_CCR1 register clears RDSERR1..

SNECCERR

Bit 25: Bank 1 single correction error flag SNECCERR1 flag is raised when an ECC single correction error occurs during a read operation from bank 1. An interrupt is generated if SNECCERRIE1 is set to 1. Writing 1 to CLR_SNECCERR1 bit in FLASH_CCR1 register clears SNECCERR1..

DBECCERR

Bit 26: Bank 1 ECC double detection error flag DBECCERR1 flag is raised when an ECC double detection error occurs during a read operation from bank 1. An interrupt is generated if DBECCERRIE1 is set to 1. Writing 1 to CLR_DBECCERR1 bit in FLASH_CCR1 register clears DBECCERR1..

CRCEND

Bit 27: Bank 1 CRC end of calculation flag CRCEND1 bit is raised when the CRC computation has completed on bank 1. An interrupt is generated if CRCENDIE1 is set to 1. It is not necessary to reset CRCEND1 before restarting CRC computation. Writing 1 to CLR_CRCEND1 bit in FLASH_CCR1 register clears CRCEND1..

CRCRDERR

Bit 28: Bank 1 CRC read error flag CRCRDERR1 flag is raised when a word is found read protected during a CRC operation on bank 1. An interrupt is generated if CRCRDIE1 and CRCEND1 are set to 1. Writing 1 to CLR_CRCRDERR1 bit in FLASH_CCR1 register clears CRCRDERR1. Note: This flag is valid only when CRCEND1 bit is set to 1.

CCR [1]

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLR_CRCRDERR
w
CLR_CRCEND
w
CLR_DBECCERR
w
CLR_SNECCERR
w
CLR_RDSERR
w
CLR_RDPERR
w
CLR_INCERR
w
CLR_STRBERR
w
CLR_PGSERR
w
CLR_WRPERR
w
CLR_EOP
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

CLR_EOP

Bit 16: Bank 1 EOP1 flag clear bit Setting this bit to 1 resets to 0 EOP1 flag in FLASH_SR1 register..

CLR_WRPERR

Bit 17: Bank 1 WRPERR1 flag clear bit Setting this bit to 1 resets to 0 WRPERR1 flag in FLASH_SR1 register..

CLR_PGSERR

Bit 18: Bank 1 PGSERR1 flag clear bit Setting this bit to 1 resets to 0 PGSERR1 flag in FLASH_SR1 register..

CLR_STRBERR

Bit 19: Bank 1 STRBERR1 flag clear bit Setting this bit to 1 resets to 0 STRBERR1 flag in FLASH_SR1 register..

CLR_INCERR

Bit 21: Bank 1 INCERR1 flag clear bit Setting this bit to 1 resets to 0 INCERR1 flag in FLASH_SR1 register..

CLR_RDPERR

Bit 23: Bank 1 RDPERR1 flag clear bit Setting this bit to 1 resets to 0 RDPERR1 flag in FLASH_SR1 register..

CLR_RDSERR

Bit 24: Bank 1 RDSERR1 flag clear bit Setting this bit to 1 resets to 0 RDSERR1 flag in FLASH_SR1 register..

CLR_SNECCERR

Bit 25: Bank 1 SNECCERR1 flag clear bit Setting this bit to 1 resets to 0 SNECCERR1 flag in FLASH_SR1 register. If the DBECCERR1 flag of FLASH_SR1 register is cleared to 0, FLASH_ECC_FA1R register is reset to 0 as well..

CLR_DBECCERR

Bit 26: Bank 1 DBECCERR1 flag clear bit Setting this bit to 1 resets to 0 DBECCERR1 flag in FLASH_SR1 register. If the SNECCERR1 flag of FLASH_SR1 register is cleared to 0, FLASH_ECC_FA1R register is reset to 0 as well..

CLR_CRCEND

Bit 27: Bank 1 CRCEND1 flag clear bit Setting this bit to 1 resets to 0 CRCEND1 flag in FLASH_SR1 register..

CLR_CRCRDERR

Bit 28: Bank 1 CRCRDERR1 flag clear bit Setting this bit to 1 resets to 0 CRCRDERR1 flag in FLASH_SR1 register..

OPTCR

FLASH option control register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWAP_BANK
r
OPTCHANGEERRIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PG_OTP
rw
MER
w
OPTSTART
w
OPTLOCK
rw
Toggle fields

OPTLOCK

Bit 0: FLASH_OPTCR lock option configuration bit.

OPTSTART

Bit 1: Option byte start change option configuration bit.

MER

Bit 4: Flash mass erase enable bit.

PG_OTP

Bit 5: OTP program control bit.

OPTCHANGEERRIE

Bit 30: Option byte change error interrupt enable bit.

SWAP_BANK

Bit 31: Bank swapping configuration bit.

OPTSR_CUR

FLASH option status register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWAP_BANK_OPT
rw
OPTCHANGEERR
rw
VDDIO_HSLV
rw
SECURITY
rw
ST_RAM_SIZE
rw
IWDG_FZ_SDBY
rw
WDG_FZ_STOP
rw
VDDMMC_HSLV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDP
rw
NRST_STDY
rw
NRST_STOP
rw
IWDG_SW
rw
BOR_LEV
rw
OPT_BUSY
rw
Toggle fields

OPT_BUSY

Bit 0: Option byte change ongoing flag.

BOR_LEV

Bits 2-3: Brownout level option status bit.

IWDG_SW

Bit 4: IWDG1 control option status bit.

NRST_STOP

Bit 6: D1 DStop entry reset option status bit.

NRST_STDY

Bit 7: D1 DStandby entry reset option status bit.

RDP

Bits 8-15: Readout protection level option status byte.

VDDMMC_HSLV

Bit 16: IWDG Stop mode freeze option status bit.

WDG_FZ_STOP

Bit 17: IWDG Stop mode freeze option status bit.

IWDG_FZ_SDBY

Bit 18: IWDG Standby mode freeze option status bit.

ST_RAM_SIZE

Bits 19-20: DTCM RAM size option status.

SECURITY

Bit 21: Security enable option status bit.

VDDIO_HSLV

Bit 29: I/O high-speed at low-voltage status bit (PRODUCT_BELOW_25V).

OPTCHANGEERR

Bit 30: Option byte change error flag.

SWAP_BANK_OPT

Bit 31: Bank swapping option status bit.

OPTSR_PRG

FLASH option status register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWAP_BANK_OPT
rw
VDDIO_HSLV
rw
SECURITY
rw
ST_RAM_SIZE
rw
IWDG_FZ_SDBY
rw
WDG_FZ_STOP
rw
VDDMMC_HSLV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDP
rw
NRST_STDY
rw
NRST_STOP
rw
IWDG_SW
rw
BOR_LEV
rw
Toggle fields

BOR_LEV

Bits 2-3: BOR reset level option configuration bits.

IWDG_SW

Bit 4: IWDG1 option configuration bit.

NRST_STOP

Bit 6: Option byte erase after D1 DStop option configuration bit.

NRST_STDY

Bit 7: Option byte erase after D1 DStandby option configuration bit.

RDP

Bits 8-15: Readout protection level option configuration byte.

VDDMMC_HSLV

Bit 16: VDDMMC_HSLV.

WDG_FZ_STOP

Bit 17: IWDG Stop mode freeze option configuration bit.

IWDG_FZ_SDBY

Bit 18: IWDG Standby mode freeze option configuration bit.

ST_RAM_SIZE

Bits 19-20: DTCM size select option configuration bits.

SECURITY

Bit 21: Security option configuration bit.

VDDIO_HSLV

Bit 29: VDDIO_HSLV.

SWAP_BANK_OPT

Bit 31: Bank swapping option configuration bit.

OPTCCR

FLASH option clear control register

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLR_OPTCHANGEERR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

CLR_OPTCHANGEERR

Bit 30: OPTCHANGEERR reset bit.

PRAR_CUR [1]

FLASH protection address for bank 1

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMEP
r
PROT_AREA_END
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PROT_AREA_START
r
Toggle fields

PROT_AREA_START

Bits 0-11: Bank 1 PCROP area start status bits These bits contain the first 256-byte block of the PCROP area in bank 1. If this address is equal to PROT_AREA_END1, the whole bank 1 is PCROP protected. If this address is higher than PROT_AREA_END1, no protection is set on bank 1..

PROT_AREA_END

Bits 16-27: Bank 1 PCROP area end status bits These bits contain the last 256-byte block of the PCROP area in bank 1. If this address is equal to PROT_AREA_START1, the whole bank 1 is PCROP protected. If this address is lower than PROT_AREA_START1, no protection is set on bank 1..

DMEP

Bit 31: Bank 1 PCROP protected erase enable option status bit If DMEP1 is set to 1, the PCROP protected area in bank 1 is erased when a protection level regression (change from level 1 to 0) or a bank erase with protection removal occurs..

PRAR_PRG [1]

FLASH protection address for bank 1

Offset: 0x2c, size: 32, reset: 0x00000000, access: Unspecified

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMEP
rw
PROT_AREA_END
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PROT_AREA_START
rw
Toggle fields

PROT_AREA_START

Bits 0-11: Bank 1 PCROP area start configuration bits These bits contain the first 256-byte block of the PCROP area in bank 1. If this address is equal to PROT_AREA_END1, the whole bank 1 is PCROP protected. If this address is higher than PROT_AREA_END1, no protection is set on bank 1..

PROT_AREA_END

Bits 16-27: Bank 1 PCROP area end configuration bits These bits contain the last 256-byte block of the PCROP area in bank 1. If this address is equal to PROT_AREA_START1, the whole bank 1 is PCROP protected. If this address is lower than PROT_AREA_START1, no protection is set on bank 1..

DMEP

Bit 31: Bank 1 PCROP protected erase enable option configuration bit If DMEP1 is set to 1, the PCROP protected area in bank 1 is erased when a protection level regression (change from level 1 to 0) or a bank erase with protection removal occurs..

SCAR_CUR [1]

FLASH secure address for bank 1

Offset: 0x30, size: 32, reset: 0x00000000, access: Unspecified

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMES
r
SEC_AREA_END
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEC_AREA_START
r
Toggle fields

SEC_AREA_START

Bits 0-11: Bank 1 secure-only area start status bits These bits contain the first 256 bytes of block of the secure-only area in bank 1. If this address is equal to SEC_AREA_END1, the whole bank 1 is secure access only. If this address is higher than SEC_AREA_END1, no protection is set on bank 1..

SEC_AREA_END

Bits 16-27: Bank 1 secure-only area end status bits These bits contain the last 256-byte block of the secure-only area in bank 1. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure access only. If this address is lower than SEC_AREA_START1, no protection is set on bank 1..

DMES

Bit 31: Bank 1 secure access protected erase enable option status bit If DMES1 is set to 1, the secure access only area in bank 1 is erased when a protection level regression (change from level 1 to 0) or a bank erase with protection removal occurs..

SCAR_PRG [1]

FLASH secure address for bank 1

Offset: 0x34, size: 32, reset: 0x00000000, access: Unspecified

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMES
rw
SEC_AREA_END
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEC_AREA_START
rw
Toggle fields

SEC_AREA_START

Bits 0-11: Bank 1 secure-only area start configuration bits These bits contain the first block of 256 bytes of the secure-only area in bank 1. If this address is equal to SEC_AREA_END1, the whole bank 1 is secure access only. If this address is higher than SEC_AREA_END1, no protection is set on bank 1..

SEC_AREA_END

Bits 16-27: Bank 1 secure-only area end configuration bits These bits contain the last block of 256 bytes of the secure-only area in bank 1. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure access only. If this address is lower than SEC_AREA_START1, no protection is set on bank 1..

DMES

Bit 31: Bank 1 secure access protected erase enable option configuration bit If DMES1 is set to 1, the secure access only area in bank 1 is erased when a protection level regression (change from level 1 to 0) or a bank erase with protection removal occurs..

WPSN_CURR [1]

FLASH write sector group protection for bank 1

Offset: 0x38, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRPSGn
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRPSGn
r
Toggle fields

WRPSGn

Bits 0-31: Bank 1 sector group protection option status byte Each FLASH_WPSGN_CUR1R bit reflects the write protection status of the corresponding group of four consecutive sectors in bank 1 (0: the group is write protected; 1: the group is not write protected) Bit 0: Group embedding sectors 0 to 3 Bit 1: Group embedding sectors 4 to 7 Bit N: Group embedding sectors 4 x N to 4 x N + 3 Bit 31: Group embedding sectors 124 to 127 Note: Bank 1 is limited to 16 and 64 sectors on STM32H7B0 and STM32H7A3xG devices, respectively..

WPSN_PRGR [1]

FLASH write sector group protection for bank 1

Offset: 0x3c, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRPSGn
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRPSGn
rw
Toggle fields

WRPSGn

Bits 0-31: Bank 1 sector group protection option status byte Setting WRPSGn1 bits to 0 write protects the corresponding group of four consecutive sectors in bank 1 (0: the group is write protected; 1: the group is not write protected) Bit 0: Group embedding sectors 0 to 3 Bit 1: Group embedding sectors 4 to 7 Bit N: Group embedding sectors 4 x N to 4 x N + 3 Bit 31: Group embedding sectors 124 to 127 Note: Bank 1 is limited to 16 and 64 sectors on STM32H7B0 and STM32H7A3xG devices, respectively..

BOOT_CURR

FLASH register with boot address

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BOOT_ADD1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOT_ADD0
r
Toggle fields

BOOT_ADD0

Bits 0-15: Boot address 0.

BOOT_ADD1

Bits 16-31: Boot address 1.

BOOT_PRGR

FLASH register with boot address

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BOOT_ADD1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOT_ADD0
r
Toggle fields

BOOT_ADD0

Bits 0-15: Boot address 0.

BOOT_ADD1

Bits 16-31: Boot address 1.

CRCCR [1]

FLASH CRC control register for bank 1

Offset: 0x50, size: 32, reset: 0x001C0000, access: Unspecified

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALL_BANK
w
CRC_BURST
rw
CLEAN_CRC
w
START_CRC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLEAN_SECT
w
ADD_SECT
w
CRC_BY_SECT
rw
CRC_SECT
rw
Toggle fields

CRC_SECT

Bits 0-6: Bank 1 CRC sector number CRC_SECT is used to select one user Flash sectors to be added to the list of sectors on which the CRC is calculated. The CRC can be computed either between two addresses (using registers FLASH_CRCSADD1R and FLASH_CRCEADD1R) or on a list of sectors using this register. If this latter option is selected, it is possible to add a sector to the list of sectors by programming the sector number in CRC_SECT and then setting to 1 ADD_SECT. The list of sectors can be erased either by setting CLEAN_SECT bit or by disabling the CRC computation. CRC_SECT can be set only when CRC_EN of FLASH_CR register is set to 1. ... ... ... Note: Bank 1 is limited to 16 and 64 sectors on STM32H7B0 and STM32H7AxG devices, respectively..

CRC_BY_SECT

Bit 8: Bank 1 CRC sector mode select bit When CRC_BY_SECT is set to 1, the CRC calculation is performed at sector level, on the sectors present in the list of sectors. To add a sector to this list, use ADD_SECT and CRC_SECT bits. To clean the list, use CLEAN_SECT bit. When CRC_BY_SECT is reset to 0, the CRC calculation is performed on all addresses between CRC_START_ADDR and CRC_END_ADDR..

ADD_SECT

Bit 9: Bank 1 CRC sector select bit Setting ADD_SECT to 1 adds the sector whose number is CRC_SECT to the list of sectors on which the CRC is calculated..

CLEAN_SECT

Bit 10: Bank 1 CRC sector list clear bit Setting CLEAN_SECT to 1 clears the list of sectors on which the CRC is calculated..

START_CRC

Bit 16: Bank 1 CRC start bit START_CRC bit triggers a CRC calculation on bank 1 using the current configuration. No CRC calculation can launched when an option byte change operation is ongoing because all write accesses to embedded Flash memory registers are put on hold until the option byte change operation has completed..

CLEAN_CRC

Bit 17: Bank 1 CRC clear bit Setting CLEAN_CRC to 1 clears the current CRC result stored in the FLASH_CRCDATAR register..

CRC_BURST

Bits 20-21: Bank 1 CRC burst size CRC_BURST bits set the size of the bursts that are generated by the CRC calculation unit..

ALL_BANK

Bit 22: Bank 1 CRC select bit When ALL_BANK is set to 1, all bank 1 user sectors are added to list of sectors on which the CRC is calculated..

CRCSADDR [1]

Offset: 0x54, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRC_START_ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRC_START_ADDR
rw
Toggle fields

CRC_START_ADDR

Bits 2-19: CRC start address on bank 1 CRC_START_ADDR is used when CRC_BY_SECT is cleared to 0. It must be programmed to the start address of the bank 1 memory area on which the CRC calculation is performed..

CRCEADDR [1]

Offset: 0x58, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRC_END_ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRC_END_ADDR
rw
Toggle fields

CRC_END_ADDR

Bits 2-19: CRC end address on bank 1 CRC_END_ADDR is used when CRC_BY_SECT is cleared to 0. It must be programmed to the end address of the bank 1 memory area on which the CRC calculation is performed.

CRCDATAR

FLASH CRC data register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRC_DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRC_DATA
rw
Toggle fields

CRC_DATA

Bits 0-31: CRC result.

FAR [1]

Offset: 0x60, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTP_FAIL_ECC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FAIL_ECC_ADDR
r
Toggle fields

FAIL_ECC_ADDR

Bits 0-15: Bank 1 ECC error address When an ECC error occurs (both for single correction or double detection) during a read operation from bank 1, the FAIL_ECC_ADDR1 bitfield contains the address that generated the error. FAIL_ECC_ADDR1 is reset when the flag error in the FLASH_SR1 register (CLR_SNECCERR1 or CLR_DBECCERR1) is reset. The embedded Flash memory programs the address in this register only when no ECC error flags are set. This means that only the first address that generated an ECC error is saved. The address in FAIL_ECC_ADDR1 is relative to the Flash memory area where the error occurred (user Flash memory, system Flash memory, read-only/OTP area)..

OTP_FAIL_ECC

Bit 31: OTP ECC error bit This bit is set to 1 when one single ECC correction or double ECC detection occurred during the last successful read operation from the read-only/ OTP area. The address of the ECC error is available in FAIL_ECC_ADDR1 bitfield..

OTPBL_CUR

FLASH OTP block lock

Offset: 0x68, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCKBL
r
Toggle fields

LOCKBL

Bits 0-15: OTP Block Lock Block n corresponds to OTP 16-bit word 32 x n to 32 x n + 31. LOCKBL[n] = 1 indicates that all OTP 16-bit words in OTP Block n are locked and can no longer be programmed. LOCKBL[n] = 0 indicates that all OTP 16-bit words in OTP Block n are not locked and can still be modified..

OTPBL_PRG

FLASH OTP block lock

Offset: 0x6c, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCKBL
rw
Toggle fields

LOCKBL

Bits 0-15: OTP Block Lock Block n corresponds to OTP 16-bit word 32 x n to 32 x n + 31. LOCKBL[n] = 1 indicates that all OTP 16-bit words in OTP Block n are locked and can no longer be programmed. LOCKBL[n] = 0 indicates that all OTP 16-bit words in OTP Block n are not locked and can still be modified. LOCKBL bits can be set if the corresponding bit in FLASH_OTPBL_CUR is cleared..

ACR_

Access control register

Offset: 0x100, size: 32, reset: 0x00000013, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRHIGHFREQ
rw
LATENCY
rw
Toggle fields

LATENCY

Bits 0-3: Read latency.

WRHIGHFREQ

Bits 4-5: Flash signal delay.

KEYR [2]

FLASH key register for bank 1

Offset: 0x104, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY1R
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY1R
w
Toggle fields

KEY1R

Bits 0-31: Non-volatile memory bank 1 configuration access unlock key.

OPTKEYR_

FLASH option key register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPTKEYR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPTKEYR
rw
Toggle fields

OPTKEYR

Bits 0-31: Unlock key option bytes.

CR [2]

Offset: 0x10c, size: 32, reset: 0x00000001, access: Unspecified

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRCRDERRIE
rw
CRCENDIE
rw
DBECCERRIE
rw
SNECCERRIE
rw
RDSERRIE
rw
RDPERRIE
rw
INCERRIE
rw
STRBERRIE
rw
PGSERRIE
rw
WRPERRIE
rw
EOPIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRC_EN
rw
SSN
rw
START
rw
FW
rw
BER
rw
SER
rw
PG
rw
LOCK
rw
Toggle fields

LOCK

Bit 0: Bank 1 configuration lock bit This bit locks the FLASH_CR1 register. The correct write sequence to FLASH_KEYR1 register unlocks this bit. If a wrong sequence is executed, or if the unlock sequence to FLASH_KEYR1 is performed twice, this bit remains locked until the next system reset. LOCK1 can be set by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When LOCK1 changes from 0 to 1, the other bits of FLASH_CR1 register do not change..

PG

Bit 1: Bank 1 internal buffer control bit Setting PG1 bit to 1 enables internal buffer for write operations to bank 1. This allows preparing program operations even if a sector or bank erase is ongoing. PG1 can be programmed only when LOCK1 is cleared to 0. When PG1 is reset, the internal buffer is disabled for write operations to bank 1, and all the data stored in the buffer but not sent to the operation queue are lost..

SER

Bit 2: Bank 1 sector erase request Setting SER1 bit to 1 requests a sector erase on bank 1. SER1 can be programmed only when LOCK1 is cleared to 0. BER1 has a higher priority than SER1: if both bits are set, the embedded Flash memory executes a bank erase. Note: Write protection error is triggered when a sector erase is required on a protected sector..

BER

Bit 3: Bank 1 erase request Setting BER1 bit to 1 requests a bank erase operation on bank 1 (user Flash memory only). BER1 can be programmed only when LOCK1 is cleared to 0. BER1 has a higher priority than SER1: if both are set, the embedded Flash memory executes a bank erase. Note: Write protection error is triggered when a bank erase is required and some sectors are protected..

FW

Bit 4: Bank 1 write forcing control bit FW1 forces a write operation even if the write buffer is not full. In this case all bits not written are set to 1 by hardware. FW1 can be programmed only when LOCK1 is cleared to 0. The embedded Flash memory resets FW1 when the corresponding operation has been acknowledged. Note: Using a force-write operation prevents the application from updating later the missing bits with something else than 1, because it is likely that it will lead to permanent ECC error. Write forcing is effective only if the write buffer is not empty (in particular, FW1 does not start several write operations when the force-write operations are performed consecutively)..

START

Bit 5: Bank 1 erase start control bit START1 bit is used to start a sector erase or a bank erase operation. START1 can be programmed only when LOCK1 is cleared to 0. The embedded Flash memory resets START1 when the corresponding operation has been acknowledged. The user application cannot access any embedded Flash memory register until the operation is acknowledged..

SSN

Bits 6-12: Bank 1 sector erase selection number These bits are used to select the target sector for an erase operation (they are unused otherwise). SSN1 can be programmed only when LOCK1 is cleared to 0. .. ... ... Note: Bank 1 is limited to 16 and 64 sectors on STM32H7B0 and STM32H7A3xG devices, respectively..

CRC_EN

Bit 15: Bank 1 CRC control bit Setting CRC_EN bit to 1 enables the CRC calculation on bank 1. CRC_EN does not start CRC calculation but enables CRC configuration through FLASH_CRCCR1 register. When CRC calculation is performed on bank 1, it can only be disabled by setting CRC_EN bit to 0. Resetting CRC_EN clears CRC configuration and resets the content of FLASH_CRCDATAR register. Clearing CRC_EN to 0 sets CRCDATA to 0x0. CRC_EN can be programmed only when LOCK1 is cleared to 0..

EOPIE

Bit 16: Bank 1 end-of-program interrupt control bit Setting EOPIE1 bit to 1 enables the generation of an interrupt at the end of a program operation to bank 1. EOPIE1 can be programmed only when LOCK1 is cleared to 0..

WRPERRIE

Bit 17: Bank 1 write protection error interrupt enable bit When WRPERRIE1 bit is set to 1, an interrupt is generated when a protection error occurs during a program operation to bank 1. WRPERRIE1 can be programmed only when LOCK1 is cleared to 0..

PGSERRIE

Bit 18: Bank 1 programming sequence error interrupt enable bit When PGSERRIE1 bit is set to 1, an interrupt is generated when a sequence error occurs during a program operation to bank 1. PGSERRIE1 can be programmed only when LOCK1 is cleared to 0..

STRBERRIE

Bit 19: Bank 1 strobe error interrupt enable bit When STRBERRIE1 bit is set to 1, an interrupt is generated when a strobe error occurs (the master programs several times the same byte in the write buffer) during a write operation to bank 1. STRBERRIE1 can be programmed only when LOCK1 is cleared to 0..

INCERRIE

Bit 21: Bank 1 inconsistency error interrupt enable bit When INCERRIE1 bit is set to 1, an interrupt is generated when an inconsistency error occurs during a write operation to bank 1. INCERRIE1 can be programmed only when LOCK1 is cleared to 0..

RDPERRIE

Bit 23: Bank 1 read protection error interrupt enable bit When RDPERRIE1 bit is set to 1, an interrupt is generated when a read protection error occurs (access to an address protected by PCROP or by RDP level 1) during a read operation from bank 1. RDPERRIE1 can be programmed only when LOCK1 is cleared to 0..

RDSERRIE

Bit 24: Bank 1 secure error interrupt enable bit When RDSERRIE1 bit is set to 1, an interrupt is generated when a secure error (access to a secure-only protected address) occurs during a read operation from bank 1. RDSERRIE1 can be programmed only when LOCK1 is cleared to 0..

SNECCERRIE

Bit 25: Bank 1 ECC single correction error interrupt enable bit When SNECCERRIE1 bit is set to 1, an interrupt is generated when an ECC single correction error occurs during a read operation from bank 1. SNECCERRIE1 can be programmed only when LOCK1 is cleared to 0..

DBECCERRIE

Bit 26: Bank 1 ECC double detection error interrupt enable bit When DBECCERRIE1 bit is set to 1, an interrupt is generated when an ECC double detection error occurs during a read operation from bank 1. DBECCERRIE1 can be programmed only when LOCK1 is cleared to 0..

CRCENDIE

Bit 27: Bank 1 CRC end of calculation interrupt enable bit When CRCENDIE1 bit is set to 1, an interrupt is generated when the CRC computation has completed on bank 1. CRCENDIE1 can be programmed only when LOCK1 is cleared to 0..

CRCRDERRIE

Bit 28: Bank 1 CRC read error interrupt enable bit When CRCRDERRIE1 bit is set to 1, an interrupt is generated when a protected area (PCROP or secure-only) has been detected during the last CRC computation on bank 1. CRCRDERRIE1 can be programmed only when LOCK1 is cleared to 0..

SR [2]

Offset: 0x110, size: 32, reset: 0x00000000, access: Unspecified

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRCRDERR
r
CRCEND
r
DBECCERR
r
SNECCERR
r
RDSERR
r
RDPERR
r
INCERR
r
STRBERR
r
PGSERR
r
WRPERR
r
EOP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRC_BUSY
r
QW
r
WBNE
r
BSY
r
Toggle fields

BSY

Bit 0: Bank 1 busy flag BSY1 flag is set when an effective write, erase or option byte change operation is ongoing on bank 1. It is not possible to know what type of operation is being executed. BSY1 cannot be forced to 0. It is automatically reset by hardware every time a step in a write, erase or option byte change operation completes..

WBNE

Bit 1: Bank 1 write buffer not empty flag WBNE1 flag is set when the embedded Flash memory is waiting for new data to complete the write buffer. In this state, the write buffer is not empty. WBNE1 is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below: the application software forces the write operation using FW1 bit in FLASH_CR1 the embedded Flash memory detects an error that involves data loss the application software has disabled write operations in this bank This bit cannot be forced to 0. To reset it, clear the write buffer by performing any of the above listed actions, or send the missing data..

QW

Bit 2: Bank 1 wait queue flag QW1 flag is set when a write, erase or option byte change operation is pending in the command queue buffer of bank 1. It is not possible to know what type of programming operation is present in the queue. This flag is reset by hardware when all write, erase or option byte change operations have been executed and thus removed from the waiting queue(s). This bit cannot be forced to 0. It is reset after a deterministic time if no other operations are requested..

CRC_BUSY

Bit 3: Bank 1 CRC busy flag CRC_BUSY1 flag is set when a CRC calculation is ongoing on bank 1. This bit cannot be forced to 0. The user must wait until the CRC calculation has completed or disable CRC computation on bank 1..

EOP

Bit 16: Bank 1 end-of-program flag EOP1 flag is set when a programming operation to bank 1 completes. An interrupt is generated if the EOPIE1 is set to 1. It is not necessary to reset EOP1 before starting a new operation. EOP1 bit is cleared by writing 1 to CLR_EOP1 bit in FLASH_CCR1 register..

WRPERR

Bit 17: Bank 1 write protection error flag WRPERR1 flag is raised when a protection error occurs during a program operation to bank 1. An interrupt is also generated if the WRPERRIE1 is set to 1. Writing 1 to CLR_WRPERR1 bit in FLASH_CCR1 register clears WRPERR1..

PGSERR

Bit 18: Bank 1 programming sequence error flag PGSERR1 flag is raised when a sequence error occurs on bank 1. An interrupt is generated if the PGSERRIE1 bit is set to 1. Writing 1 to CLR_PGSERR1 bit in FLASH_CCR1 register clears PGSERR1..

STRBERR

Bit 19: Bank 1 strobe error flag STRBERR1 flag is raised when a strobe error occurs on bank 1 (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE1 bit is set to 1. Writing 1 to CLR_STRBERR1 bit in FLASH_CCR1 register clears STRBERR1..

INCERR

Bit 21: Bank 1 inconsistency error flag INCERR1 flag is raised when a inconsistency error occurs on bank 1. An interrupt is generated if INCERRIE1 is set to 1. Writing 1 to CLR_INCERR1 bit in the FLASH_CCR1 register clears INCERR1..

RDPERR

Bit 23: Bank 1 read protection error flag RDPERR1 flag is raised when an read protection error (read access to a PCROP-protected or a RDP-protected area) occurs on bank 1. An interrupt is generated if RDPERRIE1 is set to 1. Writing 1 to CLR_RDPERR1 bit in FLASH_CCR1 register clears RDPERR1..

RDSERR

Bit 24: Bank 1 secure error flag RDSERR1 flag is raised when a read secure error (read access to a secure-only protected word) occurs on bank 1. An interrupt is generated if RDSERRIE1 is set to 1. Writing 1 to CLR_RDSERR1 bit in FLASH_CCR1 register clears RDSERR1..

SNECCERR

Bit 25: Bank 1 single correction error flag SNECCERR1 flag is raised when an ECC single correction error occurs during a read operation from bank 1. An interrupt is generated if SNECCERRIE1 is set to 1. Writing 1 to CLR_SNECCERR1 bit in FLASH_CCR1 register clears SNECCERR1..

DBECCERR

Bit 26: Bank 1 ECC double detection error flag DBECCERR1 flag is raised when an ECC double detection error occurs during a read operation from bank 1. An interrupt is generated if DBECCERRIE1 is set to 1. Writing 1 to CLR_DBECCERR1 bit in FLASH_CCR1 register clears DBECCERR1..

CRCEND

Bit 27: Bank 1 CRC end of calculation flag CRCEND1 bit is raised when the CRC computation has completed on bank 1. An interrupt is generated if CRCENDIE1 is set to 1. It is not necessary to reset CRCEND1 before restarting CRC computation. Writing 1 to CLR_CRCEND1 bit in FLASH_CCR1 register clears CRCEND1..

CRCRDERR

Bit 28: Bank 1 CRC read error flag CRCRDERR1 flag is raised when a word is found read protected during a CRC operation on bank 1. An interrupt is generated if CRCRDIE1 and CRCEND1 are set to 1. Writing 1 to CLR_CRCRDERR1 bit in FLASH_CCR1 register clears CRCRDERR1. Note: This flag is valid only when CRCEND1 bit is set to 1.

CCR [2]

Offset: 0x114, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLR_CRCRDERR
w
CLR_CRCEND
w
CLR_DBECCERR
w
CLR_SNECCERR
w
CLR_RDSERR
w
CLR_RDPERR
w
CLR_INCERR
w
CLR_STRBERR
w
CLR_PGSERR
w
CLR_WRPERR
w
CLR_EOP
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

CLR_EOP

Bit 16: Bank 1 EOP1 flag clear bit Setting this bit to 1 resets to 0 EOP1 flag in FLASH_SR1 register..

CLR_WRPERR

Bit 17: Bank 1 WRPERR1 flag clear bit Setting this bit to 1 resets to 0 WRPERR1 flag in FLASH_SR1 register..

CLR_PGSERR

Bit 18: Bank 1 PGSERR1 flag clear bit Setting this bit to 1 resets to 0 PGSERR1 flag in FLASH_SR1 register..

CLR_STRBERR

Bit 19: Bank 1 STRBERR1 flag clear bit Setting this bit to 1 resets to 0 STRBERR1 flag in FLASH_SR1 register..

CLR_INCERR

Bit 21: Bank 1 INCERR1 flag clear bit Setting this bit to 1 resets to 0 INCERR1 flag in FLASH_SR1 register..

CLR_RDPERR

Bit 23: Bank 1 RDPERR1 flag clear bit Setting this bit to 1 resets to 0 RDPERR1 flag in FLASH_SR1 register..

CLR_RDSERR

Bit 24: Bank 1 RDSERR1 flag clear bit Setting this bit to 1 resets to 0 RDSERR1 flag in FLASH_SR1 register..

CLR_SNECCERR

Bit 25: Bank 1 SNECCERR1 flag clear bit Setting this bit to 1 resets to 0 SNECCERR1 flag in FLASH_SR1 register. If the DBECCERR1 flag of FLASH_SR1 register is cleared to 0, FLASH_ECC_FA1R register is reset to 0 as well..

CLR_DBECCERR

Bit 26: Bank 1 DBECCERR1 flag clear bit Setting this bit to 1 resets to 0 DBECCERR1 flag in FLASH_SR1 register. If the SNECCERR1 flag of FLASH_SR1 register is cleared to 0, FLASH_ECC_FA1R register is reset to 0 as well..

CLR_CRCEND

Bit 27: Bank 1 CRCEND1 flag clear bit Setting this bit to 1 resets to 0 CRCEND1 flag in FLASH_SR1 register..

CLR_CRCRDERR

Bit 28: Bank 1 CRCRDERR1 flag clear bit Setting this bit to 1 resets to 0 CRCRDERR1 flag in FLASH_SR1 register..

OPTCR_

FLASH option control register

Offset: 0x118, size: 32, reset: 0x00000001, access: read-write

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWAP_BANK
r
OPTCHANGEERRIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PG_OTP
rw
MER
w
OPTSTART
w
OPTLOCK
rw
Toggle fields

OPTLOCK

Bit 0: FLASH_OPTCR lock option configuration bit.

OPTSTART

Bit 1: Option byte start change option configuration bit.

MER

Bit 4: Flash mass erase enable bit.

PG_OTP

Bit 5: OTP program control bit.

OPTCHANGEERRIE

Bit 30: Option byte change error interrupt enable bit.

SWAP_BANK

Bit 31: Bank swapping configuration bit.

OPTSR_CUR_

FLASH option status register

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWAP_BANK_OPT
rw
OPTCHANGEERR
rw
VDDIO_HSLV
rw
SECURITY
rw
ST_RAM_SIZE
rw
IWDG_FZ_SDBY
rw
WDG_FZ_STOP
rw
VDDMMC_HSLV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDP
rw
NRST_STDY
rw
NRST_STOP
rw
IWDG_SW
rw
BOR_LEV
rw
OPT_BUSY
rw
Toggle fields

OPT_BUSY

Bit 0: Option byte change ongoing flag.

BOR_LEV

Bits 2-3: Brownout level option status bit.

IWDG_SW

Bit 4: IWDG1 control option status bit.

NRST_STOP

Bit 6: D1 DStop entry reset option status bit.

NRST_STDY

Bit 7: D1 DStandby entry reset option status bit.

RDP

Bits 8-15: Readout protection level option status byte.

VDDMMC_HSLV

Bit 16: IWDG Stop mode freeze option status bit.

WDG_FZ_STOP

Bit 17: IWDG Stop mode freeze option status bit.

IWDG_FZ_SDBY

Bit 18: IWDG Standby mode freeze option status bit.

ST_RAM_SIZE

Bits 19-20: DTCM RAM size option status.

SECURITY

Bit 21: Security enable option status bit.

VDDIO_HSLV

Bit 29: I/O high-speed at low-voltage status bit (PRODUCT_BELOW_25V).

OPTCHANGEERR

Bit 30: Option byte change error flag.

SWAP_BANK_OPT

Bit 31: Bank swapping option status bit.

OPTSR_PRG_

FLASH option status register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWAP_BANK_OPT
rw
VDDIO_HSLV
rw
SECURITY
rw
ST_RAM_SIZE
rw
IWDG_FZ_SDBY
rw
WDG_FZ_STOP
rw
VDDMMC_HSLV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDP
rw
NRST_STDY
rw
NRST_STOP
rw
IWDG_SW
rw
BOR_LEV
rw
Toggle fields

BOR_LEV

Bits 2-3: BOR reset level option configuration bits.

IWDG_SW

Bit 4: IWDG1 option configuration bit.

NRST_STOP

Bit 6: Option byte erase after D1 DStop option configuration bit.

NRST_STDY

Bit 7: Option byte erase after D1 DStandby option configuration bit.

RDP

Bits 8-15: Readout protection level option configuration byte.

VDDMMC_HSLV

Bit 16: VDDMMC_HSLV.

WDG_FZ_STOP

Bit 17: IWDG Stop mode freeze option configuration bit.

IWDG_FZ_SDBY

Bit 18: IWDG Standby mode freeze option configuration bit.

ST_RAM_SIZE

Bits 19-20: DTCM size select option configuration bits.

SECURITY

Bit 21: Security option configuration bit.

VDDIO_HSLV

Bit 29: VDDIO_HSLV.

SWAP_BANK_OPT

Bit 31: Bank swapping option configuration bit.

OPTCCR_

FLASH option clear control register

Offset: 0x124, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLR_OPTCHANGEERR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

CLR_OPTCHANGEERR

Bit 30: OPTCHANGEERR reset bit.

PRAR_CUR [2]

FLASH protection address for bank 1

Offset: 0x128, size: 32, reset: 0x00000000, access: Unspecified

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMEP
r
PROT_AREA_END
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PROT_AREA_START
r
Toggle fields

PROT_AREA_START

Bits 0-11: Bank 1 PCROP area start status bits These bits contain the first 256-byte block of the PCROP area in bank 1. If this address is equal to PROT_AREA_END1, the whole bank 1 is PCROP protected. If this address is higher than PROT_AREA_END1, no protection is set on bank 1..

PROT_AREA_END

Bits 16-27: Bank 1 PCROP area end status bits These bits contain the last 256-byte block of the PCROP area in bank 1. If this address is equal to PROT_AREA_START1, the whole bank 1 is PCROP protected. If this address is lower than PROT_AREA_START1, no protection is set on bank 1..

DMEP

Bit 31: Bank 1 PCROP protected erase enable option status bit If DMEP1 is set to 1, the PCROP protected area in bank 1 is erased when a protection level regression (change from level 1 to 0) or a bank erase with protection removal occurs..

PRAR_PRG [2]

FLASH protection address for bank 1

Offset: 0x12c, size: 32, reset: 0x00000000, access: Unspecified

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMEP
rw
PROT_AREA_END
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PROT_AREA_START
rw
Toggle fields

PROT_AREA_START

Bits 0-11: Bank 1 PCROP area start configuration bits These bits contain the first 256-byte block of the PCROP area in bank 1. If this address is equal to PROT_AREA_END1, the whole bank 1 is PCROP protected. If this address is higher than PROT_AREA_END1, no protection is set on bank 1..

PROT_AREA_END

Bits 16-27: Bank 1 PCROP area end configuration bits These bits contain the last 256-byte block of the PCROP area in bank 1. If this address is equal to PROT_AREA_START1, the whole bank 1 is PCROP protected. If this address is lower than PROT_AREA_START1, no protection is set on bank 1..

DMEP

Bit 31: Bank 1 PCROP protected erase enable option configuration bit If DMEP1 is set to 1, the PCROP protected area in bank 1 is erased when a protection level regression (change from level 1 to 0) or a bank erase with protection removal occurs..

SCAR_CUR [2]

FLASH secure address for bank 1

Offset: 0x130, size: 32, reset: 0x00000000, access: Unspecified

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMES
r
SEC_AREA_END
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEC_AREA_START
r
Toggle fields

SEC_AREA_START

Bits 0-11: Bank 1 secure-only area start status bits These bits contain the first 256 bytes of block of the secure-only area in bank 1. If this address is equal to SEC_AREA_END1, the whole bank 1 is secure access only. If this address is higher than SEC_AREA_END1, no protection is set on bank 1..

SEC_AREA_END

Bits 16-27: Bank 1 secure-only area end status bits These bits contain the last 256-byte block of the secure-only area in bank 1. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure access only. If this address is lower than SEC_AREA_START1, no protection is set on bank 1..

DMES

Bit 31: Bank 1 secure access protected erase enable option status bit If DMES1 is set to 1, the secure access only area in bank 1 is erased when a protection level regression (change from level 1 to 0) or a bank erase with protection removal occurs..

SCAR_PRG [2]

FLASH secure address for bank 1

Offset: 0x134, size: 32, reset: 0x00000000, access: Unspecified

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMES
rw
SEC_AREA_END
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEC_AREA_START
rw
Toggle fields

SEC_AREA_START

Bits 0-11: Bank 1 secure-only area start configuration bits These bits contain the first block of 256 bytes of the secure-only area in bank 1. If this address is equal to SEC_AREA_END1, the whole bank 1 is secure access only. If this address is higher than SEC_AREA_END1, no protection is set on bank 1..

SEC_AREA_END

Bits 16-27: Bank 1 secure-only area end configuration bits These bits contain the last block of 256 bytes of the secure-only area in bank 1. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure access only. If this address is lower than SEC_AREA_START1, no protection is set on bank 1..

DMES

Bit 31: Bank 1 secure access protected erase enable option configuration bit If DMES1 is set to 1, the secure access only area in bank 1 is erased when a protection level regression (change from level 1 to 0) or a bank erase with protection removal occurs..

WPSN_CURR [2]

FLASH write sector group protection for bank 1

Offset: 0x138, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRPSGn
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRPSGn
r
Toggle fields

WRPSGn

Bits 0-31: Bank 1 sector group protection option status byte Each FLASH_WPSGN_CUR1R bit reflects the write protection status of the corresponding group of four consecutive sectors in bank 1 (0: the group is write protected; 1: the group is not write protected) Bit 0: Group embedding sectors 0 to 3 Bit 1: Group embedding sectors 4 to 7 Bit N: Group embedding sectors 4 x N to 4 x N + 3 Bit 31: Group embedding sectors 124 to 127 Note: Bank 1 is limited to 16 and 64 sectors on STM32H7B0 and STM32H7A3xG devices, respectively..

WPSN_PRGR [2]

FLASH write sector group protection for bank 1

Offset: 0x13c, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRPSGn
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRPSGn
rw
Toggle fields

WRPSGn

Bits 0-31: Bank 1 sector group protection option status byte Setting WRPSGn1 bits to 0 write protects the corresponding group of four consecutive sectors in bank 1 (0: the group is write protected; 1: the group is not write protected) Bit 0: Group embedding sectors 0 to 3 Bit 1: Group embedding sectors 4 to 7 Bit N: Group embedding sectors 4 x N to 4 x N + 3 Bit 31: Group embedding sectors 124 to 127 Note: Bank 1 is limited to 16 and 64 sectors on STM32H7B0 and STM32H7A3xG devices, respectively..

BOOT_CURR_

FLASH register with boot address

Offset: 0x140, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BOOT_ADD1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOT_ADD0
r
Toggle fields

BOOT_ADD0

Bits 0-15: Boot address 0.

BOOT_ADD1

Bits 16-31: Boot address 1.

BOOT_PRGR_

FLASH register with boot address

Offset: 0x144, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BOOT_ADD1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOT_ADD0
r
Toggle fields

BOOT_ADD0

Bits 0-15: Boot address 0.

BOOT_ADD1

Bits 16-31: Boot address 1.

CRCCR [2]

FLASH CRC control register for bank 1

Offset: 0x150, size: 32, reset: 0x001C0000, access: Unspecified

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALL_BANK
w
CRC_BURST
rw
CLEAN_CRC
w
START_CRC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLEAN_SECT
w
ADD_SECT
w
CRC_BY_SECT
rw
CRC_SECT
rw
Toggle fields

CRC_SECT

Bits 0-6: Bank 1 CRC sector number CRC_SECT is used to select one user Flash sectors to be added to the list of sectors on which the CRC is calculated. The CRC can be computed either between two addresses (using registers FLASH_CRCSADD1R and FLASH_CRCEADD1R) or on a list of sectors using this register. If this latter option is selected, it is possible to add a sector to the list of sectors by programming the sector number in CRC_SECT and then setting to 1 ADD_SECT. The list of sectors can be erased either by setting CLEAN_SECT bit or by disabling the CRC computation. CRC_SECT can be set only when CRC_EN of FLASH_CR register is set to 1. ... ... ... Note: Bank 1 is limited to 16 and 64 sectors on STM32H7B0 and STM32H7AxG devices, respectively..

CRC_BY_SECT

Bit 8: Bank 1 CRC sector mode select bit When CRC_BY_SECT is set to 1, the CRC calculation is performed at sector level, on the sectors present in the list of sectors. To add a sector to this list, use ADD_SECT and CRC_SECT bits. To clean the list, use CLEAN_SECT bit. When CRC_BY_SECT is reset to 0, the CRC calculation is performed on all addresses between CRC_START_ADDR and CRC_END_ADDR..

ADD_SECT

Bit 9: Bank 1 CRC sector select bit Setting ADD_SECT to 1 adds the sector whose number is CRC_SECT to the list of sectors on which the CRC is calculated..

CLEAN_SECT

Bit 10: Bank 1 CRC sector list clear bit Setting CLEAN_SECT to 1 clears the list of sectors on which the CRC is calculated..

START_CRC

Bit 16: Bank 1 CRC start bit START_CRC bit triggers a CRC calculation on bank 1 using the current configuration. No CRC calculation can launched when an option byte change operation is ongoing because all write accesses to embedded Flash memory registers are put on hold until the option byte change operation has completed..

CLEAN_CRC

Bit 17: Bank 1 CRC clear bit Setting CLEAN_CRC to 1 clears the current CRC result stored in the FLASH_CRCDATAR register..

CRC_BURST

Bits 20-21: Bank 1 CRC burst size CRC_BURST bits set the size of the bursts that are generated by the CRC calculation unit..

ALL_BANK

Bit 22: Bank 1 CRC select bit When ALL_BANK is set to 1, all bank 1 user sectors are added to list of sectors on which the CRC is calculated..

CRCSADDR [2]

Offset: 0x154, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRC_START_ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRC_START_ADDR
rw
Toggle fields

CRC_START_ADDR

Bits 2-19: CRC start address on bank 1 CRC_START_ADDR is used when CRC_BY_SECT is cleared to 0. It must be programmed to the start address of the bank 1 memory area on which the CRC calculation is performed..

CRCEADDR [2]

Offset: 0x158, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRC_END_ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRC_END_ADDR
rw
Toggle fields

CRC_END_ADDR

Bits 2-19: CRC end address on bank 1 CRC_END_ADDR is used when CRC_BY_SECT is cleared to 0. It must be programmed to the end address of the bank 1 memory area on which the CRC calculation is performed.

FAR [2]

Offset: 0x160, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTP_FAIL_ECC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FAIL_ECC_ADDR
r
Toggle fields

FAIL_ECC_ADDR

Bits 0-15: Bank 1 ECC error address When an ECC error occurs (both for single correction or double detection) during a read operation from bank 1, the FAIL_ECC_ADDR1 bitfield contains the address that generated the error. FAIL_ECC_ADDR1 is reset when the flag error in the FLASH_SR1 register (CLR_SNECCERR1 or CLR_DBECCERR1) is reset. The embedded Flash memory programs the address in this register only when no ECC error flags are set. This means that only the first address that generated an ECC error is saved. The address in FAIL_ECC_ADDR1 is relative to the Flash memory area where the error occurred (user Flash memory, system Flash memory, read-only/OTP area)..

OTP_FAIL_ECC

Bit 31: OTP ECC error bit This bit is set to 1 when one single ECC correction or double ECC detection occurred during the last successful read operation from the read-only/ OTP area. The address of the ECC error is available in FAIL_ECC_ADDR1 bitfield..

FMC

0x52004000: FMC

174/174 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 BCR1
0x4 BTR[1]
0x8 BCR[2]
0xc BTR[2]
0x10 BCR[3]
0x14 BTR[3]
0x18 BCR[4]
0x1c BTR[4]
0x80 PCR
0x84 SR
0x88 PMEM
0x8c PATT
0x94 ECCR
0x104 BWTR[1]
0x10c BWTR[2]
0x114 BWTR[3]
0x11c BWTR[4]
0x140 SDCR1
0x144 SDCR2
0x148 SDTR[1]
0x14c SDTR[2]
0x150 SDCMR
0x154 SDRTR
0x158 SDSR
Toggle registers

BCR1

This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.

Offset: 0x0, size: 32, reset: 0x000030DB, access: read-write

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FMCEN
rw
BMAP
rw
WFDIS
rw
CCLKEN
rw
CBURSTRW
rw
CPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw
EXTMOD
rw
WAITEN
rw
WREN
rw
WAITCFG
rw
WAITPOL
rw
BURSTEN
rw
FACCEN
rw
MWID
rw
MTYP
rw
MUXEN
rw
MBKEN
rw
Toggle fields

MBKEN

Bit 0: Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus..

Allowed values:
0: Disabled: Corresponding memory bank is disabled
1: Enabled: Corresponding memory bank is enabled

MUXEN

Bit 1: Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:.

Allowed values:
0: Disabled: Address/Data non-multiplexed
1: Enabled: Address/Data multiplexed on databus

MTYP

Bits 2-3: Memory type These bits define the type of external memory attached to the corresponding memory bank:.

Allowed values:
0: SRAM: SRAM memory type
1: PSRAM: PSRAM (CRAM) memory type
2: Flash: NOR Flash/OneNAND Flash

MWID

Bits 4-5: Memory data bus width Defines the external memory device width, valid for all type of memories..

Allowed values:
0: Bits8: Memory data bus width 8 bits
1: Bits16: Memory data bus width 16 bits
2: Bits32: Memory data bus width 32 bits

FACCEN

Bit 6: Flash access enable This bit enables NOR Flash memory access operations..

Allowed values:
0: Disabled: Corresponding NOR Flash memory access is disabled
1: Enabled: Corresponding NOR Flash memory access is enabled

BURSTEN

Bit 8: Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode:.

Allowed values:
0: Disabled: Burst mode disabled
1: Enabled: Burst mode enabled

WAITPOL

Bit 9: Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode:.

Allowed values:
0: ActiveLow: NWAIT active low
1: ActiveHigh: NWAIT active high

WAITCFG

Bit 11: Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:.

Allowed values:
0: BeforeWaitState: NWAIT signal is active one data cycle before wait state
1: DuringWaitState: NWAIT signal is active during wait state

WREN

Bit 12: Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC:.

Allowed values:
0: Disabled: Write operations disabled for the bank by the FMC
1: Enabled: Write operations enabled for the bank by the FMC

WAITEN

Bit 13: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode..

Allowed values:
0: Disabled: Values inside the FMC_BWTR are taken into account
1: Enabled: NWAIT signal enabled

EXTMOD

Bit 14: Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10)..

Allowed values:
0: Disabled: Values inside the FMC_BWTR are not taken into account
1: Enabled: Values inside the FMC_BWTR are taken into account

ASYNCWAIT

Bit 15: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol..

Allowed values:
0: Disabled: Wait signal not used in asynchronous mode
1: Enabled: Wait signal used even in asynchronous mode

CPSIZE

Bits 16-18: CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved..

Allowed values:
0: NoBurstSplit: No burst split when crossing page boundary
1: Bytes128: 128 bytes CRAM page size
2: Bytes256: 256 bytes CRAM page size
3: Bytes512: 512 bytes CRAM page size
4: Bytes1024: 1024 bytes CRAM page size

CBURSTRW

Bit 19: Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register..

Allowed values:
0: Disabled: Write operations are always performed in asynchronous mode
1: Enabled: Write operations are performed in synchronous mode

CCLKEN

Bit 20: Continuous Clock Enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in synchronous mode to generate the FMC_CLK continuous clock. If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.).

Allowed values:
0: Disabled: The FMC_CLK is generated continuously during asynchronous and synchronous access. The FMC_CLK clock is activated when the CCLKEN is set
1: Enabled: The FMC_CLK is only generated during the synchronous memory access (read/write transaction)

WFDIS

Bit 21: Write FIFO Disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register..

Allowed values:
0: Enabled: Write FIFO enabled
1: Disabled: Write FIFO disabled

BMAP

Bits 24-25: FMC bank mapping These bits allows different to remap SDRAM bank2 or swap the FMC NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note: The BMAP bits of the FMC_BCR2..4 registers are dont care. It is only enabled through the FMC_BCR1 register..

Allowed values:
0: Default: Default mapping
1: Swapped: NOR/PSRAM bank and SDRAM bank 1/bank2 are swapped
2: Remapped: SDRAM Bank2 remapped on FMC bank2 and still accessible at default mapping

FMCEN

Bit 31: FMC controller Enable This bit enables/disables the FMC controller. Note: The FMCEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register..

Allowed values:
0: Disabled: Disable the FMC controller
1: Enabled: Enable the FMC controller

BTR[1]

This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).

Offset: 0x4, size: 32, reset: 0x0FFFFFFF, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw
DATLAT
rw
CLKDIV
rw
BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw
ADDHLD
rw
ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1..

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration..

Allowed values: 0x1-0xf

DATAST

Bits 8-15: Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care..

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period &#8805; tEHELmin and (BUSTRUN + 2)KCK_FMC period &#8805; tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period &#8805; max (tEHELmin, tEHQZmax) if EXTMOD = 126. ....

Allowed values: 0x0-0xf

CLKDIV

Bits 20-23: Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula).

Allowed values: 0x1-0xf

DATLAT

Bits 24-27: Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles.

Allowed values: 0x0-0xf

ACCMOD

Bits 28-29: Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

BCR[2]

This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.

Offset: 0x8, size: 32, reset: 0x000030D2, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CBURSTRW
rw
CPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw
EXTMOD
rw
WAITEN
rw
WREN
rw
WAITCFG
rw
WAITPOL
rw
BURSTEN
rw
FACCEN
rw
MWID
rw
MTYP
rw
MUXEN
rw
MBKEN
rw
Toggle fields

MBKEN

Bit 0: Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus..

Allowed values:
0: Disabled: Corresponding memory bank is disabled
1: Enabled: Corresponding memory bank is enabled

MUXEN

Bit 1: Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:.

Allowed values:
0: Disabled: Address/Data non-multiplexed
1: Enabled: Address/Data multiplexed on databus

MTYP

Bits 2-3: Memory type These bits define the type of external memory attached to the corresponding memory bank:.

Allowed values:
0: SRAM: SRAM memory type
1: PSRAM: PSRAM (CRAM) memory type
2: Flash: NOR Flash/OneNAND Flash

MWID

Bits 4-5: Memory data bus width Defines the external memory device width, valid for all type of memories..

Allowed values:
0: Bits8: Memory data bus width 8 bits
1: Bits16: Memory data bus width 16 bits
2: Bits32: Memory data bus width 32 bits

FACCEN

Bit 6: Flash access enable This bit enables NOR Flash memory access operations..

Allowed values:
0: Disabled: Corresponding NOR Flash memory access is disabled
1: Enabled: Corresponding NOR Flash memory access is enabled

BURSTEN

Bit 8: Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode:.

Allowed values:
0: Disabled: Burst mode disabled
1: Enabled: Burst mode enabled

WAITPOL

Bit 9: Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode:.

Allowed values:
0: ActiveLow: NWAIT active low
1: ActiveHigh: NWAIT active high

WAITCFG

Bit 11: Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:.

Allowed values:
0: BeforeWaitState: NWAIT signal is active one data cycle before wait state
1: DuringWaitState: NWAIT signal is active during wait state

WREN

Bit 12: Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC:.

Allowed values:
0: Disabled: Write operations disabled for the bank by the FMC
1: Enabled: Write operations enabled for the bank by the FMC

WAITEN

Bit 13: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode..

Allowed values:
0: Disabled: Values inside the FMC_BWTR are taken into account
1: Enabled: NWAIT signal enabled

EXTMOD

Bit 14: Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10)..

Allowed values:
0: Disabled: Values inside the FMC_BWTR are not taken into account
1: Enabled: Values inside the FMC_BWTR are taken into account

ASYNCWAIT

Bit 15: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol..

Allowed values:
0: Disabled: Wait signal not used in asynchronous mode
1: Enabled: Wait signal used even in asynchronous mode

CPSIZE

Bits 16-18: CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved..

Allowed values:
0: NoBurstSplit: No burst split when crossing page boundary
1: Bytes128: 128 bytes CRAM page size
2: Bytes256: 256 bytes CRAM page size
3: Bytes512: 512 bytes CRAM page size
4: Bytes1024: 1024 bytes CRAM page size

CBURSTRW

Bit 19: Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register..

Allowed values:
0: Disabled: Write operations are always performed in asynchronous mode
1: Enabled: Write operations are performed in synchronous mode

BTR[2]

This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).

Offset: 0xc, size: 32, reset: 0x0FFFFFFF, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw
DATLAT
rw
CLKDIV
rw
BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw
ADDHLD
rw
ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1..

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration..

Allowed values: 0x1-0xf

DATAST

Bits 8-15: Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care..

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period &#8805; tEHELmin and (BUSTRUN + 2)KCK_FMC period &#8805; tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period &#8805; max (tEHELmin, tEHQZmax) if EXTMOD = 126. ....

Allowed values: 0x0-0xf

CLKDIV

Bits 20-23: Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula).

Allowed values: 0x1-0xf

DATLAT

Bits 24-27: Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles.

Allowed values: 0x0-0xf

ACCMOD

Bits 28-29: Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

BCR[3]

This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.

Offset: 0x10, size: 32, reset: 0x000030D2, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CBURSTRW
rw
CPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw
EXTMOD
rw
WAITEN
rw
WREN
rw
WAITCFG
rw
WAITPOL
rw
BURSTEN
rw
FACCEN
rw
MWID
rw
MTYP
rw
MUXEN
rw
MBKEN
rw
Toggle fields

MBKEN

Bit 0: Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus..

Allowed values:
0: Disabled: Corresponding memory bank is disabled
1: Enabled: Corresponding memory bank is enabled

MUXEN

Bit 1: Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:.

Allowed values:
0: Disabled: Address/Data non-multiplexed
1: Enabled: Address/Data multiplexed on databus

MTYP

Bits 2-3: Memory type These bits define the type of external memory attached to the corresponding memory bank:.

Allowed values:
0: SRAM: SRAM memory type
1: PSRAM: PSRAM (CRAM) memory type
2: Flash: NOR Flash/OneNAND Flash

MWID

Bits 4-5: Memory data bus width Defines the external memory device width, valid for all type of memories..

Allowed values:
0: Bits8: Memory data bus width 8 bits
1: Bits16: Memory data bus width 16 bits
2: Bits32: Memory data bus width 32 bits

FACCEN

Bit 6: Flash access enable This bit enables NOR Flash memory access operations..

Allowed values:
0: Disabled: Corresponding NOR Flash memory access is disabled
1: Enabled: Corresponding NOR Flash memory access is enabled

BURSTEN

Bit 8: Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode:.

Allowed values:
0: Disabled: Burst mode disabled
1: Enabled: Burst mode enabled

WAITPOL

Bit 9: Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode:.

Allowed values:
0: ActiveLow: NWAIT active low
1: ActiveHigh: NWAIT active high

WAITCFG

Bit 11: Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:.

Allowed values:
0: BeforeWaitState: NWAIT signal is active one data cycle before wait state
1: DuringWaitState: NWAIT signal is active during wait state

WREN

Bit 12: Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC:.

Allowed values:
0: Disabled: Write operations disabled for the bank by the FMC
1: Enabled: Write operations enabled for the bank by the FMC

WAITEN

Bit 13: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode..

Allowed values:
0: Disabled: Values inside the FMC_BWTR are taken into account
1: Enabled: NWAIT signal enabled

EXTMOD

Bit 14: Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10)..

Allowed values:
0: Disabled: Values inside the FMC_BWTR are not taken into account
1: Enabled: Values inside the FMC_BWTR are taken into account

ASYNCWAIT

Bit 15: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol..

Allowed values:
0: Disabled: Wait signal not used in asynchronous mode
1: Enabled: Wait signal used even in asynchronous mode

CPSIZE

Bits 16-18: CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved..

Allowed values:
0: NoBurstSplit: No burst split when crossing page boundary
1: Bytes128: 128 bytes CRAM page size
2: Bytes256: 256 bytes CRAM page size
3: Bytes512: 512 bytes CRAM page size
4: Bytes1024: 1024 bytes CRAM page size

CBURSTRW

Bit 19: Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register..

Allowed values:
0: Disabled: Write operations are always performed in asynchronous mode
1: Enabled: Write operations are performed in synchronous mode

BTR[3]

This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).

Offset: 0x14, size: 32, reset: 0x0FFFFFFF, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw
DATLAT
rw
CLKDIV
rw
BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw
ADDHLD
rw
ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1..

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration..

Allowed values: 0x1-0xf

DATAST

Bits 8-15: Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care..

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period &#8805; tEHELmin and (BUSTRUN + 2)KCK_FMC period &#8805; tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period &#8805; max (tEHELmin, tEHQZmax) if EXTMOD = 126. ....

Allowed values: 0x0-0xf

CLKDIV

Bits 20-23: Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula).

Allowed values: 0x1-0xf

DATLAT

Bits 24-27: Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles.

Allowed values: 0x0-0xf

ACCMOD

Bits 28-29: Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

BCR[4]

This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.

Offset: 0x18, size: 32, reset: 0x000030D2, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CBURSTRW
rw
CPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw
EXTMOD
rw
WAITEN
rw
WREN
rw
WAITCFG
rw
WAITPOL
rw
BURSTEN
rw
FACCEN
rw
MWID
rw
MTYP
rw
MUXEN
rw
MBKEN
rw
Toggle fields

MBKEN

Bit 0: Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus..

Allowed values:
0: Disabled: Corresponding memory bank is disabled
1: Enabled: Corresponding memory bank is enabled

MUXEN

Bit 1: Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:.

Allowed values:
0: Disabled: Address/Data non-multiplexed
1: Enabled: Address/Data multiplexed on databus

MTYP

Bits 2-3: Memory type These bits define the type of external memory attached to the corresponding memory bank:.

Allowed values:
0: SRAM: SRAM memory type
1: PSRAM: PSRAM (CRAM) memory type
2: Flash: NOR Flash/OneNAND Flash

MWID

Bits 4-5: Memory data bus width Defines the external memory device width, valid for all type of memories..

Allowed values:
0: Bits8: Memory data bus width 8 bits
1: Bits16: Memory data bus width 16 bits
2: Bits32: Memory data bus width 32 bits

FACCEN

Bit 6: Flash access enable This bit enables NOR Flash memory access operations..

Allowed values:
0: Disabled: Corresponding NOR Flash memory access is disabled
1: Enabled: Corresponding NOR Flash memory access is enabled

BURSTEN

Bit 8: Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode:.

Allowed values:
0: Disabled: Burst mode disabled
1: Enabled: Burst mode enabled

WAITPOL

Bit 9: Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode:.

Allowed values:
0: ActiveLow: NWAIT active low
1: ActiveHigh: NWAIT active high

WAITCFG

Bit 11: Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:.

Allowed values:
0: BeforeWaitState: NWAIT signal is active one data cycle before wait state
1: DuringWaitState: NWAIT signal is active during wait state

WREN

Bit 12: Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC:.

Allowed values:
0: Disabled: Write operations disabled for the bank by the FMC
1: Enabled: Write operations enabled for the bank by the FMC

WAITEN

Bit 13: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode..

Allowed values:
0: Disabled: Values inside the FMC_BWTR are taken into account
1: Enabled: NWAIT signal enabled

EXTMOD

Bit 14: Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10)..

Allowed values:
0: Disabled: Values inside the FMC_BWTR are not taken into account
1: Enabled: Values inside the FMC_BWTR are taken into account

ASYNCWAIT

Bit 15: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol..

Allowed values:
0: Disabled: Wait signal not used in asynchronous mode
1: Enabled: Wait signal used even in asynchronous mode

CPSIZE

Bits 16-18: CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved..

Allowed values:
0: NoBurstSplit: No burst split when crossing page boundary
1: Bytes128: 128 bytes CRAM page size
2: Bytes256: 256 bytes CRAM page size
3: Bytes512: 512 bytes CRAM page size
4: Bytes1024: 1024 bytes CRAM page size

CBURSTRW

Bit 19: Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register..

Allowed values:
0: Disabled: Write operations are always performed in asynchronous mode
1: Enabled: Write operations are performed in synchronous mode

BTR[4]

This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).

Offset: 0x1c, size: 32, reset: 0x0FFFFFFF, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw
DATLAT
rw
CLKDIV
rw
BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw
ADDHLD
rw
ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1..

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration..

Allowed values: 0x1-0xf

DATAST

Bits 8-15: Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care..

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period &#8805; tEHELmin and (BUSTRUN + 2)KCK_FMC period &#8805; tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period &#8805; max (tEHELmin, tEHQZmax) if EXTMOD = 126. ....

Allowed values: 0x0-0xf

CLKDIV

Bits 20-23: Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula).

Allowed values: 0x1-0xf

DATLAT

Bits 24-27: Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles.

Allowed values: 0x0-0xf

ACCMOD

Bits 28-29: Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

PCR

NAND Flash control registers

Offset: 0x80, size: 32, reset: 0x00000018, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCPS
rw
TAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAR
rw
TCLR
rw
ECCEN
rw
PWID
rw
PBKEN
rw
PWAITEN
rw
Toggle fields

PWAITEN

Bit 1: Wait feature enable bit. This bit enables the Wait feature for the NAND Flash memory bank:.

Allowed values:
0: Disabled: Wait feature disabled
1: Enabled: Wait feature enabled

PBKEN

Bit 2: NAND Flash memory bank enable bit. This bit enables the memory bank. Accessing a disabled memory bank causes an ERROR on AXI bus.

Allowed values:
0: Disabled: Corresponding memory bank is disabled
1: Enabled: Corresponding memory bank is enabled

PWID

Bits 4-5: Data bus width. These bits define the external memory device width..

Allowed values:
0: Bits8: External memory device width 8 bits
1: Bits16: External memory device width 16 bits

ECCEN

Bit 6: ECC computation logic enable bit.

Allowed values:
0: Disabled: ECC logic is disabled and reset
1: Enabled: ECC logic is enabled

TCLR

Bits 9-12: CLE to RE delay. These bits set time from CLE low to RE low in number of KCK_FMC clock cycles. The time is give by the following formula: t_clr = (TCLR + SET + 2) TKCK_FMC where TKCK_FMC is the KCK_FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space..

Allowed values: 0x0-0xf

TAR

Bits 13-16: ALE to RE delay. These bits set time from ALE low to RE low in number of KCK_FMC clock cycles. Time is: t_ar = (TAR + SET + 2) TKCK_FMC where TKCK_FMC is the FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space..

Allowed values: 0x0-0xf

ECCPS

Bits 17-19: ECC page size. These bits define the page size for the extended ECC:.

Allowed values:
0: Bytes256: ECC page size 256 bytes
1: Bytes512: ECC page size 512 bytes
2: Bytes1024: ECC page size 1024 bytes
3: Bytes2048: ECC page size 2048 bytes
4: Bytes4096: ECC page size 4096 bytes
5: Bytes8192: ECC page size 8192 bytes

SR

This register contains information about the FIFO status and interrupt. The FMC features a FIFO that is used when writing to memories to transfer up to 16 words of data.This is used to quickly write to the FIFO and free the AXI bus for transactions to peripherals other than the FMC, while the FMC is draining its FIFO into the memory. One of these register bits indicates the status of the FIFO, for ECC purposes.The ECC is calculated while the data are written to the memory. To read the correct ECC, the software must consequently wait until the FIFO is empty.

Offset: 0x84, size: 32, reset: 0x00000040, access: Unspecified

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEMPT
r
IFEN
rw
ILEN
rw
IREN
rw
IFS
rw
ILS
rw
IRS
rw
Toggle fields

IRS

Bit 0: Interrupt rising edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set..

Allowed values:
0: DidNotOccur: Interrupt rising edge did not occur
1: Occurred: Interrupt rising edge occurred

ILS

Bit 1: Interrupt high-level status The flag is set by hardware and reset by software..

Allowed values:
0: DidNotOccur: Interrupt high-level did not occur
1: Occurred: Interrupt high-level occurred

IFS

Bit 2: Interrupt falling edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set..

Allowed values:
0: DidNotOccur: Interrupt falling edge did not occur
1: Occurred: Interrupt falling edge occurred

IREN

Bit 3: Interrupt rising edge detection enable bit.

Allowed values:
0: Disabled: Interrupt rising edge detection request disabled
1: Enabled: Interrupt rising edge detection request enabled

ILEN

Bit 4: Interrupt high-level detection enable bit.

Allowed values:
0: Disabled: Interrupt high-level detection request disabled
1: Enabled: Interrupt high-level detection request enabled

IFEN

Bit 5: Interrupt falling edge detection enable bit.

Allowed values:
0: Disabled: Interrupt falling edge detection request disabled
1: Enabled: Interrupt falling edge detection request enabled

FEMPT

Bit 6: FIFO empty. Read-only bit that provides the status of the FIFO.

Allowed values:
0: NotEmpty: FIFO not empty
1: Empty: FIFO empty

PMEM

The FMC_PMEM read/write register contains the timing information for NAND Flash memory bank. This information is used to access either the common memory space of the NAND Flash for command, address write access and data read/write access.

Offset: 0x88, size: 32, reset: 0xFCFCFCFC, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MEMHIZ
rw
MEMHOLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEMWAIT
rw
MEMSET
rw
Toggle fields

MEMSET

Bits 0-7: Common memory x setup time These bits define the number of KCK_FMC (+1) clock cycles to set up the address before the command assertion (NWE, NOE), for NAND Flash read or write access to common memory space:.

Allowed values: 0x0-0xfe

MEMWAIT

Bits 8-15: Common memory wait time These bits define the minimum number of KCK_FMC (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to common memory space. The duration of command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of KCK_FMC:.

Allowed values: 0x1-0xfe

MEMHOLD

Bits 16-23: Common memory hold time These bits define the number of KCK_FMC clock cycles for write accesses and KCK_FMC+1 clock cycles for read accesses during which the address is held (and data for write accesses) after the command is de-asserted (NWE, NOE), for NAND Flash read or write access to common memory space:.

Allowed values: 0x1-0xfe

MEMHIZ

Bits 24-31: Common memory x data bus Hi-Z time These bits define the number of KCK_FMC clock cycles during which the data bus is kept Hi-Z after the start of a NAND Flash write access to common memory space. This is only valid for write transactions:.

Allowed values: 0x0-0xfe

PATT

The FMC_PATT read/write register contains the timing information for NAND Flash memory bank. It is used for 8-bit accesses to the attribute memory space of the NAND Flash for the last address write access if the timing must differ from that of previous accesses (for Ready/Busy management, refer to Section20.8.5: NAND Flash prewait feature).

Offset: 0x8c, size: 32, reset: 0xFCFCFCFC, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATTHIZ
rw
ATTHOLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATTWAIT
rw
ATTSET
rw
Toggle fields

ATTSET

Bits 0-7: Attribute memory setup time These bits define the number of KCK_FMC (+1) clock cycles to set up address before the command assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space:.

Allowed values: 0x0-0xfe

ATTWAIT

Bits 8-15: Attribute memory wait time These bits define the minimum number of x KCK_FMC (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to attribute memory space. The duration for command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of KCK_FMC:.

Allowed values: 0x1-0xfe

ATTHOLD

Bits 16-23: Attribute memory hold time These bits define the number of KCK_FMC clock cycles during which the address is held (and data for write access) after the command de-assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space:.

Allowed values: 0x1-0xfe

ATTHIZ

Bits 24-31: Attribute memory data bus Hi-Z time These bits define the number of KCK_FMC clock cycles during which the data bus is kept in Hi-Z after the start of a NAND Flash write access to attribute memory space on socket. Only valid for writ transaction:.

Allowed values: 0x0-0xfe

ECCR

This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads/writes the data from a NAND Flash memory page at the correct address (refer to Section20.8.6: Computation of the error correction code (ECC) in NAND Flash memory), the data read/written from/to the NAND Flash memory are processed automatically by the ECC computation module. When X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU must read the computed ECC value from the FMC_ECC registers. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1.

Offset: 0x94, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECC
r
Toggle fields

ECC

Bits 0-31: ECC result This field contains the value computed by the ECC computation logic. Table167 describes the contents of these bit fields..

Allowed values: 0x0-0xffffffff

BWTR[1]

This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.

Offset: 0x104, size: 32, reset: 0x0FFFFFFF, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw
BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw
ADDHLD
rw
ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1..

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration..

Allowed values: 0x1-0xf

DATAST

Bits 8-15: Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:.

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period &#8805; tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ....

Allowed values: 0x0-0xf

ACCMOD

Bits 28-29: Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

BWTR[2]

This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.

Offset: 0x10c, size: 32, reset: 0x0FFFFFFF, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw
BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw
ADDHLD
rw
ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1..

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration..

Allowed values: 0x1-0xf

DATAST

Bits 8-15: Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:.

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period &#8805; tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ....

Allowed values: 0x0-0xf

ACCMOD

Bits 28-29: Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

BWTR[3]

This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.

Offset: 0x114, size: 32, reset: 0x0FFFFFFF, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw
BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw
ADDHLD
rw
ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1..

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration..

Allowed values: 0x1-0xf

DATAST

Bits 8-15: Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:.

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period &#8805; tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ....

Allowed values: 0x0-0xf

ACCMOD

Bits 28-29: Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

BWTR[4]

This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.

Offset: 0x11c, size: 32, reset: 0x0FFFFFFF, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw
BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw
ADDHLD
rw
ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1..

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration..

Allowed values: 0x1-0xf

DATAST

Bits 8-15: Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:.

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period &#8805; tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ....

Allowed values: 0x0-0xf

ACCMOD

Bits 28-29: Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

SDCR1

This register contains the control parameters for each SDRAM memory bank

Offset: 0x140, size: 32, reset: 0x000002D0, access: read-write

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RPIPE
rw
RBURST
rw
SDCLK
rw
WP
rw
CAS
rw
NB
rw
MWID
rw
NR
rw
NC
rw
Toggle fields

NC

Bits 0-1: Number of column address bits These bits define the number of bits of a column address..

Allowed values:
0: Bits8: 8 bits
1: Bits9: 9 bits
2: Bits10: 10 bits
3: Bits11: 11 bits

NR

Bits 2-3: Number of row address bits These bits define the number of bits of a row address..

Allowed values:
0: Bits11: 11 bits
1: Bits12: 12 bits
2: Bits13: 13 bits

MWID

Bits 4-5: Memory data bus width. These bits define the memory device width..

Allowed values:
0: Bits8: Memory data bus width 8 bits
1: Bits16: Memory data bus width 16 bits
2: Bits32: Memory data bus width 32 bits

NB

Bit 6: Number of internal banks This bit sets the number of internal banks..

Allowed values:
0: NB2: Two internal Banks
1: NB4: Four internal Banks

CAS

Bits 7-8: CAS Latency This bits sets the SDRAM CAS latency in number of memory clock cycles.

Allowed values:
1: Clocks1: 1 cycle
2: Clocks2: 2 cycles
3: Clocks3: 3 cycles

WP

Bit 9: Write protection This bit enables write mode access to the SDRAM bank..

Allowed values:
0: Disabled: Write accesses allowed
1: Enabled: Write accesses ignored

SDCLK

Bits 10-11: SDRAM clock configuration These bits define the SDRAM clock period for both SDRAM banks and allow disabling the clock before changing the frequency. In this case the SDRAM must be re-initialized. Note: The corresponding bits in the FMC_SDCR2 register is read only..

Allowed values:
0: Disabled: SDCLK clock disabled
2: Div2: SDCLK period = 2 x HCLK period
3: Div3: SDCLK period = 3 x HCLK period

RBURST

Bit 12: Burst read This bit enables burst read mode. The SDRAM controller anticipates the next read commands during the CAS latency and stores data in the Read FIFO. Note: The corresponding bit in the FMC_SDCR2 register is read only..

Allowed values:
0: Disabled: Single read requests are not managed as bursts
1: Enabled: Single read requests are always managed as bursts

RPIPE

Bits 13-14: Read pipe These bits define the delay, in KCK_FMC clock cycles, for reading data after CAS latency. Note: The corresponding bits in the FMC_SDCR2 register is read only..

Allowed values:
0: NoDelay: No clock cycle delay
1: Clocks1: One clock cycle delay
2: Clocks2: Two clock cycles delay

SDCR2

This register contains the control parameters for each SDRAM memory bank

Offset: 0x144, size: 32, reset: 0x000002D0, access: read-write

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RPIPE
rw
RBURST
rw
SDCLK
rw
WP
rw
CAS
rw
NB
rw
MWID
rw
NR
rw
NC
rw
Toggle fields

NC

Bits 0-1: Number of column address bits These bits define the number of bits of a column address..

Allowed values:
0: Bits8: 8 bits
1: Bits9: 9 bits
2: Bits10: 10 bits
3: Bits11: 11 bits

NR

Bits 2-3: Number of row address bits These bits define the number of bits of a row address..

Allowed values:
0: Bits11: 11 bits
1: Bits12: 12 bits
2: Bits13: 13 bits

MWID

Bits 4-5: Memory data bus width. These bits define the memory device width..

Allowed values:
0: Bits8: Memory data bus width 8 bits
1: Bits16: Memory data bus width 16 bits
2: Bits32: Memory data bus width 32 bits

NB

Bit 6: Number of internal banks This bit sets the number of internal banks..

Allowed values:
0: NB2: Two internal Banks
1: NB4: Four internal Banks

CAS

Bits 7-8: CAS Latency This bits sets the SDRAM CAS latency in number of memory clock cycles.

Allowed values:
1: Clocks1: 1 cycle
2: Clocks2: 2 cycles
3: Clocks3: 3 cycles

WP

Bit 9: Write protection This bit enables write mode access to the SDRAM bank..

Allowed values:
0: Disabled: Write accesses allowed
1: Enabled: Write accesses ignored

SDCLK

Bits 10-11: SDRAM clock configuration These bits define the SDRAM clock period for both SDRAM banks and allow disabling the clock before changing the frequency. In this case the SDRAM must be re-initialized. Note: The corresponding bits in the FMC_SDCR2 register is read only..

Allowed values:
0: Disabled: SDCLK clock disabled
2: Div2: SDCLK period = 2 x HCLK period
3: Div3: SDCLK period = 3 x HCLK period

RBURST

Bit 12: Burst read This bit enables burst read mode. The SDRAM controller anticipates the next read commands during the CAS latency and stores data in the Read FIFO. Note: The corresponding bit in the FMC_SDCR2 register is read only..

Allowed values:
0: Disabled: Single read requests are not managed as bursts
1: Enabled: Single read requests are always managed as bursts

RPIPE

Bits 13-14: Read pipe These bits define the delay, in KCK_FMC clock cycles, for reading data after CAS latency. Note: The corresponding bits in the FMC_SDCR2 register is read only..

Allowed values:
0: NoDelay: No clock cycle delay
1: Clocks1: One clock cycle delay
2: Clocks2: Two clock cycles delay

SDTR[1]

This register contains the timing parameters of each SDRAM bank

Offset: 0x148, size: 32, reset: 0x0FFFFFFF, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TRCD
rw
TRP
rw
TWR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRC
rw
TRAS
rw
TXSR
rw
TMRD
rw
Toggle fields

TMRD

Bits 0-3: Load Mode Register to Active These bits define the delay between a Load Mode Register command and an Active or Refresh command in number of memory clock cycles. .....

Allowed values: 0x0-0xf

TXSR

Bits 4-7: Exit Self-refresh delay These bits define the delay from releasing the Self-refresh command to issuing the Activate command in number of memory clock cycles. .... Note: If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TXSR timing corresponding to the slowest SDRAM device..

Allowed values: 0x0-0xf

TRAS

Bits 8-11: Self refresh time These bits define the minimum Self-refresh period in number of memory clock cycles. .....

Allowed values: 0x0-0xf

TRC

Bits 12-15: Row cycle delay These bits define the delay between the Refresh command and the Activate command, as well as the delay between two consecutive Refresh commands. It is expressed in number of memory clock cycles. The TRC timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRC must be programmed with the timings of the slowest device. .... Note: TRC must match the TRC and TRFC (Auto Refresh period) timings defined in the SDRAM device datasheet. Note: The corresponding bits in the FMC_SDTR2 register are dont care..

Allowed values: 0x0-0xf

TWR

Bits 16-19: Recovery delay These bits define the delay between a Write and a Precharge command in number of memory clock cycles. .... Note: TWR must be programmed to match the write recovery time (tWR) defined in the SDRAM datasheet, and to guarantee that: TWR &#8805; TRAS - TRCD and TWR &#8805;TRC - TRCD - TRP Example: TRAS= 4 cycles, TRCD= 2 cycles. So, TWR &gt;= 2 cycles. TWR must be programmed to 0x1. If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TWR timing corresponding to the slowest SDRAM device..

Allowed values: 0x0-0xf

TRP

Bits 20-23: Row precharge delay These bits define the delay between a Precharge command and another command in number of memory clock cycles. The TRP timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRP must be programmed with the timing of the slowest device. .... Note: The corresponding bits in the FMC_SDTR2 register are dont care..

Allowed values: 0x0-0xf

TRCD

Bits 24-27: Row to column delay These bits define the delay between the Activate command and a Read/Write command in number of memory clock cycles. .....

Allowed values: 0x0-0xf

SDTR[2]

This register contains the timing parameters of each SDRAM bank

Offset: 0x14c, size: 32, reset: 0x0FFFFFFF, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TRCD
rw
TRP
rw
TWR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRC
rw
TRAS
rw
TXSR
rw
TMRD
rw
Toggle fields

TMRD

Bits 0-3: Load Mode Register to Active These bits define the delay between a Load Mode Register command and an Active or Refresh command in number of memory clock cycles. .....

Allowed values: 0x0-0xf

TXSR

Bits 4-7: Exit Self-refresh delay These bits define the delay from releasing the Self-refresh command to issuing the Activate command in number of memory clock cycles. .... Note: If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TXSR timing corresponding to the slowest SDRAM device..

Allowed values: 0x0-0xf

TRAS

Bits 8-11: Self refresh time These bits define the minimum Self-refresh period in number of memory clock cycles. .....

Allowed values: 0x0-0xf

TRC

Bits 12-15: Row cycle delay These bits define the delay between the Refresh command and the Activate command, as well as the delay between two consecutive Refresh commands. It is expressed in number of memory clock cycles. The TRC timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRC must be programmed with the timings of the slowest device. .... Note: TRC must match the TRC and TRFC (Auto Refresh period) timings defined in the SDRAM device datasheet. Note: The corresponding bits in the FMC_SDTR2 register are dont care..

Allowed values: 0x0-0xf

TWR

Bits 16-19: Recovery delay These bits define the delay between a Write and a Precharge command in number of memory clock cycles. .... Note: TWR must be programmed to match the write recovery time (tWR) defined in the SDRAM datasheet, and to guarantee that: TWR &#8805; TRAS - TRCD and TWR &#8805;TRC - TRCD - TRP Example: TRAS= 4 cycles, TRCD= 2 cycles. So, TWR &gt;= 2 cycles. TWR must be programmed to 0x1. If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TWR timing corresponding to the slowest SDRAM device..

Allowed values: 0x0-0xf

TRP

Bits 20-23: Row precharge delay These bits define the delay between a Precharge command and another command in number of memory clock cycles. The TRP timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRP must be programmed with the timing of the slowest device. .... Note: The corresponding bits in the FMC_SDTR2 register are dont care..

Allowed values: 0x0-0xf

TRCD

Bits 24-27: Row to column delay These bits define the delay between the Activate command and a Read/Write command in number of memory clock cycles. .....

Allowed values: 0x0-0xf

SDCMR

This register contains the command issued when the SDRAM device is accessed. This register is used to initialize the SDRAM device, and to activate the Self-refresh and the Power-down modes. As soon as the MODE field is written, the command will be issued only to one or to both SDRAM banks according to CTB1 and CTB2 command bits. This register is the same for both SDRAM banks.

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MRD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MRD
rw
NRFS
rw
CTB1
rw
CTB2
rw
MODE
rw
Toggle fields

MODE

Bits 0-2: Command mode These bits define the command issued to the SDRAM device. Note: When a command is issued, at least one Command Target Bank bit ( CTB1 or CTB2) must be set otherwise the command will be ignored. Note: If two SDRAM banks are used, the Auto-refresh and PALL command must be issued simultaneously to the two devices with CTB1 and CTB2 bits set otherwise the command will be ignored. Note: If only one SDRAM bank is used and a command is issued with its associated CTB bit set, the other CTB bit of the unused bank must be kept to 0..

Allowed values:
0: Normal: Normal Mode
1: ClockConfigurationEnable: Clock Configuration Enable
2: PALL: PALL (All Bank Precharge) command
3: AutoRefreshCommand: Auto-refresh command
4: LoadModeRegister: Load Mode Resgier
5: SelfRefreshCommand: Self-refresh command
6: PowerDownCommand: Power-down command

CTB2

Bit 3: Command Target Bank 2 This bit indicates whether the command will be issued to SDRAM Bank 2 or not..

Allowed values:
0: NotIssued: Command not issued to SDRAM Bank 1
1: Issued: Command issued to SDRAM Bank 1

CTB1

Bit 4: Command Target Bank 1 This bit indicates whether the command will be issued to SDRAM Bank 1 or not..

Allowed values:
0: NotIssued: Command not issued to SDRAM Bank 1
1: Issued: Command issued to SDRAM Bank 1

NRFS

Bits 5-8: Number of Auto-refresh These bits define the number of consecutive Auto-refresh commands issued when MODE = 011. .....

Allowed values: 0x0-0xf

MRD

Bits 9-22: Mode Register definition This 14-bit field defines the SDRAM Mode Register content. The Mode Register is programmed using the Load Mode Register command. The MRD[13:0] bits are also used to program the extended mode register for mobile SDRAM..

Allowed values: 0x0-0x1fff

SDRTR

This register sets the refresh rate in number of SDCLK clock cycles between the refresh cycles by configuring the Refresh Timer Count value.Examplewhere 64 ms is the SDRAM refresh period.The refresh rate must be increased by 20 SDRAM clock cycles (as in the above example) to obtain a safe margin if an internal refresh request occurs when a read request has been accepted. It corresponds to a COUNT value of 0000111000000 (448). This 13-bit field is loaded into a timer which is decremented using the SDRAM clock. This timer generates a refresh pulse when zero is reached. The COUNT value must be set at least to 41 SDRAM clock cycles.As soon as the FMC_SDRTR register is programmed, the timer starts counting. If the value programmed in the register is 0, no refresh is carried out. This register must not be reprogrammed after the initialization procedure to avoid modifying the refresh rate.Each time a refresh pulse is generated, this 13-bit COUNT field is reloaded into the counter.If a memory access is in progress, the Auto-refresh request is delayed. However, if the memory access and Auto-refresh requests are generated simultaneously, the Auto-refresh takes precedence. If the memory access occurs during a refresh operation, the request is buffered to be processed when the refresh is complete.This register is common to SDRAM bank 1 and bank 2.

Offset: 0x154, size: 32, reset: 0x00000000, access: Unspecified

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REIE
rw
COUNT
rw
CRE
w
Toggle fields

CRE

Bit 0: Clear Refresh error flag This bit is used to clear the Refresh Error Flag (RE) in the Status Register..

Allowed values:
1: Clear: Refresh Error Flag is cleared

COUNT

Bits 1-13: Refresh Timer Count This 13-bit field defines the refresh rate of the SDRAM device. It is expressed in number of memory clock cycles. It must be set at least to 41 SDRAM clock cycles (0x29). Refresh rate = (COUNT + 1) x SDRAM frequency clock COUNT = (SDRAM refresh period / Number of rows) - 20.

Allowed values: 0x0-0x1fff

REIE

Bit 14: RES Interrupt Enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated if RE = 1

SDSR

SDRAM Status register

Offset: 0x158, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODES2
r
MODES1
r
RE
r
Toggle fields

RE

Bit 0: Refresh error flag An interrupt is generated if REIE = 1 and RE = 1.

Allowed values:
0: NoError: No refresh error has been detected
1: Error: A refresh error has been detected

MODES1

Bits 1-2: Status Mode for Bank 1 These bits define the Status Mode of SDRAM Bank 1..

Allowed values:
0: Normal: Normal Mode
1: SelfRefresh: Self-refresh mode
2: PowerDown: Power-down mode

MODES2

Bits 3-4: Status Mode for Bank 2 These bits define the Status Mode of SDRAM Bank 2..

Allowed values:
0: Normal: Normal Mode
1: SelfRefresh: Self-refresh mode
2: PowerDown: Power-down mode

GPIOA

0x58020000: GPIO

161/161 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xABFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw
MODER[14]
rw
MODER[13]
rw
MODER[12]
rw
MODER[11]
rw
MODER[10]
rw
MODER[9]
rw
MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw
MODER[6]
rw
MODER[5]
rw
MODER[4]
rw
MODER[3]
rw
MODER[2]
rw
MODER[1]
rw
MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x0C000000, access: read-write

16/16 fields covered.

Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x64000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw
PUPDR[14]
rw
PUPDR[13]
rw
PUPDR[12]
rw
PUPDR[11]
rw
PUPDR[10]
rw
PUPDR[9]
rw
PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw
PUPDR[6]
rw
PUPDR[5]
rw
PUPDR[4]
rw
PUPDR[3]
rw
PUPDR[2]
rw
PUPDR[1]
rw
PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset.A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence.Each lock bit freezes a specific configuration register (control and alternate function registers).

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw
LCK[14]
rw
LCK[13]
rw
LCK[12]
rw
LCK[11]
rw
LCK[10]
rw
LCK[9]
rw
LCK[8]
rw
LCK[7]
rw
LCK[6]
rw
LCK[5]
rw
LCK[4]
rw
LCK[3]
rw
LCK[2]
rw
LCK[1]
rw
LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit will return 1 until the next MCU reset or peripheral reset..

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[7]
rw
AFR[6]
rw
AFR[5]
rw
AFR[4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[3]
rw
AFR[2]
rw
AFR[1]
rw
AFR[0]
rw
Toggle fields

AFR[0]

Bits 0-3: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[1]

Bits 4-7: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[2]

Bits 8-11: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[3]

Bits 12-15: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[4]

Bits 16-19: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[5]

Bits 20-23: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[6]

Bits 24-27: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[7]

Bits 28-31: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[15]
rw
AFR[14]
rw
AFR[13]
rw
AFR[12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[11]
rw
AFR[10]
rw
AFR[9]
rw
AFR[8]
rw
Toggle fields

AFR[8]

Bits 0-3: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[9]

Bits 4-7: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[10]

Bits 8-11: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[11]

Bits 12-15: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[12]

Bits 16-19: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[13]

Bits 20-23: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[14]

Bits 24-27: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[15]

Bits 28-31: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

GPIOB

0x58020400: GPIO

161/161 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFEBF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw
MODER[14]
rw
MODER[13]
rw
MODER[12]
rw
MODER[11]
rw
MODER[10]
rw
MODER[9]
rw
MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw
MODER[6]
rw
MODER[5]
rw
MODER[4]
rw
MODER[3]
rw
MODER[2]
rw
MODER[1]
rw
MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x000000C0, access: read-write

16/16 fields covered.

Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000100, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw
PUPDR[14]
rw
PUPDR[13]
rw
PUPDR[12]
rw
PUPDR[11]
rw
PUPDR[10]
rw
PUPDR[9]
rw
PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw
PUPDR[6]
rw
PUPDR[5]
rw
PUPDR[4]
rw
PUPDR[3]
rw
PUPDR[2]
rw
PUPDR[1]
rw
PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset.A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence.Each lock bit freezes a specific configuration register (control and alternate function registers).

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw
LCK[14]
rw
LCK[13]
rw
LCK[12]
rw
LCK[11]
rw
LCK[10]
rw
LCK[9]
rw
LCK[8]
rw
LCK[7]
rw
LCK[6]
rw
LCK[5]
rw
LCK[4]
rw
LCK[3]
rw
LCK[2]
rw
LCK[1]
rw
LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit will return 1 until the next MCU reset or peripheral reset..

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[7]
rw
AFR[6]
rw
AFR[5]
rw
AFR[4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[3]
rw
AFR[2]
rw
AFR[1]
rw
AFR[0]
rw
Toggle fields

AFR[0]

Bits 0-3: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[1]

Bits 4-7: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[2]

Bits 8-11: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[3]

Bits 12-15: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[4]

Bits 16-19: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[5]

Bits 20-23: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[6]

Bits 24-27: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[7]

Bits 28-31: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[15]
rw
AFR[14]
rw
AFR[13]
rw
AFR[12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[11]
rw
AFR[10]
rw
AFR[9]
rw
AFR[8]
rw
Toggle fields

AFR[8]

Bits 0-3: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[9]

Bits 4-7: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[10]

Bits 8-11: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[11]

Bits 12-15: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[12]

Bits 16-19: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[13]

Bits 20-23: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[14]

Bits 24-27: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[15]

Bits 28-31: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

GPIOC

0x58020800: GPIO

161/161 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw
MODER[14]
rw
MODER[13]
rw
MODER[12]
rw
MODER[11]
rw
MODER[10]
rw
MODER[9]
rw
MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw
MODER[6]
rw
MODER[5]
rw
MODER[4]
rw
MODER[3]
rw
MODER[2]
rw
MODER[1]
rw
MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw
PUPDR[14]
rw
PUPDR[13]
rw
PUPDR[12]
rw
PUPDR[11]
rw
PUPDR[10]
rw
PUPDR[9]
rw
PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw
PUPDR[6]
rw
PUPDR[5]
rw
PUPDR[4]
rw
PUPDR[3]
rw
PUPDR[2]
rw
PUPDR[1]
rw
PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset.A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence.Each lock bit freezes a specific configuration register (control and alternate function registers).

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw
LCK[14]
rw
LCK[13]
rw
LCK[12]
rw
LCK[11]
rw
LCK[10]
rw
LCK[9]
rw
LCK[8]
rw
LCK[7]
rw
LCK[6]
rw
LCK[5]
rw
LCK[4]
rw
LCK[3]
rw
LCK[2]
rw
LCK[1]
rw
LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit will return 1 until the next MCU reset or peripheral reset..

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[7]
rw
AFR[6]
rw
AFR[5]
rw
AFR[4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[3]
rw
AFR[2]
rw
AFR[1]
rw
AFR[0]
rw
Toggle fields

AFR[0]

Bits 0-3: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[1]

Bits 4-7: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[2]

Bits 8-11: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[3]

Bits 12-15: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[4]

Bits 16-19: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[5]

Bits 20-23: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[6]

Bits 24-27: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[7]

Bits 28-31: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[15]
rw
AFR[14]
rw
AFR[13]
rw
AFR[12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[11]
rw
AFR[10]
rw
AFR[9]
rw
AFR[8]
rw
Toggle fields

AFR[8]

Bits 0-3: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[9]

Bits 4-7: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[10]

Bits 8-11: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[11]

Bits 12-15: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[12]

Bits 16-19: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[13]

Bits 20-23: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[14]

Bits 24-27: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[15]

Bits 28-31: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

GPIOD

0x58020c00: GPIO

161/161 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw
MODER[14]
rw
MODER[13]
rw
MODER[12]
rw
MODER[11]
rw
MODER[10]
rw
MODER[9]
rw
MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw
MODER[6]
rw
MODER[5]
rw
MODER[4]
rw
MODER[3]
rw
MODER[2]
rw
MODER[1]
rw
MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw
PUPDR[14]
rw
PUPDR[13]
rw
PUPDR[12]
rw
PUPDR[11]
rw
PUPDR[10]
rw
PUPDR[9]
rw
PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw
PUPDR[6]
rw
PUPDR[5]
rw
PUPDR[4]
rw
PUPDR[3]
rw
PUPDR[2]
rw
PUPDR[1]
rw
PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset.A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence.Each lock bit freezes a specific configuration register (control and alternate function registers).

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw
LCK[14]
rw
LCK[13]
rw
LCK[12]
rw
LCK[11]
rw
LCK[10]
rw
LCK[9]
rw
LCK[8]
rw
LCK[7]
rw
LCK[6]
rw
LCK[5]
rw
LCK[4]
rw
LCK[3]
rw
LCK[2]
rw
LCK[1]
rw
LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit will return 1 until the next MCU reset or peripheral reset..

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[7]
rw
AFR[6]
rw
AFR[5]
rw
AFR[4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[3]
rw
AFR[2]
rw
AFR[1]
rw
AFR[0]
rw
Toggle fields

AFR[0]

Bits 0-3: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[1]

Bits 4-7: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[2]

Bits 8-11: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[3]

Bits 12-15: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[4]

Bits 16-19: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[5]

Bits 20-23: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[6]

Bits 24-27: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[7]

Bits 28-31: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[15]
rw
AFR[14]
rw
AFR[13]
rw
AFR[12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[11]
rw
AFR[10]
rw
AFR[9]
rw
AFR[8]
rw
Toggle fields

AFR[8]

Bits 0-3: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[9]

Bits 4-7: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[10]

Bits 8-11: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[11]

Bits 12-15: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[12]

Bits 16-19: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[13]

Bits 20-23: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[14]

Bits 24-27: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[15]

Bits 28-31: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

GPIOE

0x58021000: GPIO

161/161 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw
MODER[14]
rw
MODER[13]
rw
MODER[12]
rw
MODER[11]
rw
MODER[10]
rw
MODER[9]
rw
MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw
MODER[6]
rw
MODER[5]
rw
MODER[4]
rw
MODER[3]
rw
MODER[2]
rw
MODER[1]
rw
MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw
PUPDR[14]
rw
PUPDR[13]
rw
PUPDR[12]
rw
PUPDR[11]
rw
PUPDR[10]
rw
PUPDR[9]
rw
PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw
PUPDR[6]
rw
PUPDR[5]
rw
PUPDR[4]
rw
PUPDR[3]
rw
PUPDR[2]
rw
PUPDR[1]
rw
PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset.A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence.Each lock bit freezes a specific configuration register (control and alternate function registers).

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw
LCK[14]
rw
LCK[13]
rw
LCK[12]
rw
LCK[11]
rw
LCK[10]
rw
LCK[9]
rw
LCK[8]
rw
LCK[7]
rw
LCK[6]
rw
LCK[5]
rw
LCK[4]
rw
LCK[3]
rw
LCK[2]
rw
LCK[1]
rw
LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit will return 1 until the next MCU reset or peripheral reset..

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[7]
rw
AFR[6]
rw
AFR[5]
rw
AFR[4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[3]
rw
AFR[2]
rw
AFR[1]
rw
AFR[0]
rw
Toggle fields

AFR[0]

Bits 0-3: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[1]

Bits 4-7: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[2]

Bits 8-11: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[3]

Bits 12-15: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[4]

Bits 16-19: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[5]

Bits 20-23: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[6]

Bits 24-27: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[7]

Bits 28-31: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[15]
rw
AFR[14]
rw
AFR[13]
rw
AFR[12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[11]
rw
AFR[10]
rw
AFR[9]
rw
AFR[8]
rw
Toggle fields

AFR[8]

Bits 0-3: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[9]

Bits 4-7: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[10]

Bits 8-11: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[11]

Bits 12-15: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[12]

Bits 16-19: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[13]

Bits 20-23: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[14]

Bits 24-27: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[15]

Bits 28-31: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

GPIOF

0x58021400: GPIO

161/161 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw
MODER[14]
rw
MODER[13]
rw
MODER[12]
rw
MODER[11]
rw
MODER[10]
rw
MODER[9]
rw
MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw
MODER[6]
rw
MODER[5]
rw
MODER[4]
rw
MODER[3]
rw
MODER[2]
rw
MODER[1]
rw
MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw
PUPDR[14]
rw
PUPDR[13]
rw
PUPDR[12]
rw
PUPDR[11]
rw
PUPDR[10]
rw
PUPDR[9]
rw
PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw
PUPDR[6]
rw
PUPDR[5]
rw
PUPDR[4]
rw
PUPDR[3]
rw
PUPDR[2]
rw
PUPDR[1]
rw
PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset.A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence.Each lock bit freezes a specific configuration register (control and alternate function registers).

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw
LCK[14]
rw
LCK[13]
rw
LCK[12]
rw
LCK[11]
rw
LCK[10]
rw
LCK[9]
rw
LCK[8]
rw
LCK[7]
rw
LCK[6]
rw
LCK[5]
rw
LCK[4]
rw
LCK[3]
rw
LCK[2]
rw
LCK[1]
rw
LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit will return 1 until the next MCU reset or peripheral reset..

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[7]
rw
AFR[6]
rw
AFR[5]
rw
AFR[4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[3]
rw
AFR[2]
rw
AFR[1]
rw
AFR[0]
rw
Toggle fields

AFR[0]

Bits 0-3: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[1]

Bits 4-7: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[2]

Bits 8-11: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[3]

Bits 12-15: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[4]

Bits 16-19: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[5]

Bits 20-23: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[6]

Bits 24-27: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[7]

Bits 28-31: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[15]
rw
AFR[14]
rw
AFR[13]
rw
AFR[12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[11]
rw
AFR[10]
rw
AFR[9]
rw
AFR[8]
rw
Toggle fields

AFR[8]

Bits 0-3: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[9]

Bits 4-7: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[10]

Bits 8-11: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[11]

Bits 12-15: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[12]

Bits 16-19: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[13]

Bits 20-23: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[14]

Bits 24-27: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[15]

Bits 28-31: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

GPIOG

0x58021800: GPIO

161/161 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw
MODER[14]
rw
MODER[13]
rw
MODER[12]
rw
MODER[11]
rw
MODER[10]
rw
MODER[9]
rw
MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw
MODER[6]
rw
MODER[5]
rw
MODER[4]
rw
MODER[3]
rw
MODER[2]
rw
MODER[1]
rw
MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw
PUPDR[14]
rw
PUPDR[13]
rw
PUPDR[12]
rw
PUPDR[11]
rw
PUPDR[10]
rw
PUPDR[9]
rw
PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw
PUPDR[6]
rw
PUPDR[5]
rw
PUPDR[4]
rw
PUPDR[3]
rw
PUPDR[2]
rw
PUPDR[1]
rw
PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset.A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence.Each lock bit freezes a specific configuration register (control and alternate function registers).

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw
LCK[14]
rw
LCK[13]
rw
LCK[12]
rw
LCK[11]
rw
LCK[10]
rw
LCK[9]
rw
LCK[8]
rw
LCK[7]
rw
LCK[6]
rw
LCK[5]
rw
LCK[4]
rw
LCK[3]
rw
LCK[2]
rw
LCK[1]
rw
LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit will return 1 until the next MCU reset or peripheral reset..

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[7]
rw
AFR[6]
rw
AFR[5]
rw
AFR[4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[3]
rw
AFR[2]
rw
AFR[1]
rw
AFR[0]
rw
Toggle fields

AFR[0]

Bits 0-3: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[1]

Bits 4-7: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[2]

Bits 8-11: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[3]

Bits 12-15: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[4]

Bits 16-19: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[5]

Bits 20-23: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[6]

Bits 24-27: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[7]

Bits 28-31: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[15]
rw
AFR[14]
rw
AFR[13]
rw
AFR[12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[11]
rw
AFR[10]
rw
AFR[9]
rw
AFR[8]
rw
Toggle fields

AFR[8]

Bits 0-3: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[9]

Bits 4-7: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[10]

Bits 8-11: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[11]

Bits 12-15: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[12]

Bits 16-19: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[13]

Bits 20-23: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[14]

Bits 24-27: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[15]

Bits 28-31: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

GPIOH

0x58021c00: GPIO

161/161 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw
MODER[14]
rw
MODER[13]
rw
MODER[12]
rw
MODER[11]
rw
MODER[10]
rw
MODER[9]
rw
MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw
MODER[6]
rw
MODER[5]
rw
MODER[4]
rw
MODER[3]
rw
MODER[2]
rw
MODER[1]
rw
MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw
PUPDR[14]
rw
PUPDR[13]
rw
PUPDR[12]
rw
PUPDR[11]
rw
PUPDR[10]
rw
PUPDR[9]
rw
PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw
PUPDR[6]
rw
PUPDR[5]
rw
PUPDR[4]
rw
PUPDR[3]
rw
PUPDR[2]
rw
PUPDR[1]
rw
PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset.A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence.Each lock bit freezes a specific configuration register (control and alternate function registers).

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw
LCK[14]
rw
LCK[13]
rw
LCK[12]
rw
LCK[11]
rw
LCK[10]
rw
LCK[9]
rw
LCK[8]
rw
LCK[7]
rw
LCK[6]
rw
LCK[5]
rw
LCK[4]
rw
LCK[3]
rw
LCK[2]
rw
LCK[1]
rw
LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit will return 1 until the next MCU reset or peripheral reset..

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[7]
rw
AFR[6]
rw
AFR[5]
rw
AFR[4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[3]
rw
AFR[2]
rw
AFR[1]
rw
AFR[0]
rw
Toggle fields

AFR[0]

Bits 0-3: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[1]

Bits 4-7: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[2]

Bits 8-11: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[3]

Bits 12-15: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[4]

Bits 16-19: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[5]

Bits 20-23: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[6]

Bits 24-27: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[7]

Bits 28-31: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[15]
rw
AFR[14]
rw
AFR[13]
rw
AFR[12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[11]
rw
AFR[10]
rw
AFR[9]
rw
AFR[8]
rw
Toggle fields

AFR[8]

Bits 0-3: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[9]

Bits 4-7: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[10]

Bits 8-11: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[11]

Bits 12-15: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[12]

Bits 16-19: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[13]

Bits 20-23: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[14]

Bits 24-27: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[15]

Bits 28-31: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

GPIOI

0x58022000: GPIO

161/161 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw
MODER[14]
rw
MODER[13]
rw
MODER[12]
rw
MODER[11]
rw
MODER[10]
rw
MODER[9]
rw
MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw
MODER[6]
rw
MODER[5]
rw
MODER[4]
rw
MODER[3]
rw
MODER[2]
rw
MODER[1]
rw
MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw
PUPDR[14]
rw
PUPDR[13]
rw
PUPDR[12]
rw
PUPDR[11]
rw
PUPDR[10]
rw
PUPDR[9]
rw
PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw
PUPDR[6]
rw
PUPDR[5]
rw
PUPDR[4]
rw
PUPDR[3]
rw
PUPDR[2]
rw
PUPDR[1]
rw
PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset.A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence.Each lock bit freezes a specific configuration register (control and alternate function registers).

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw
LCK[14]
rw
LCK[13]
rw
LCK[12]
rw
LCK[11]
rw
LCK[10]
rw
LCK[9]
rw
LCK[8]
rw
LCK[7]
rw
LCK[6]
rw
LCK[5]
rw
LCK[4]
rw
LCK[3]
rw
LCK[2]
rw
LCK[1]
rw
LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit will return 1 until the next MCU reset or peripheral reset..

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[7]
rw
AFR[6]
rw
AFR[5]
rw
AFR[4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[3]
rw
AFR[2]
rw
AFR[1]
rw
AFR[0]
rw
Toggle fields

AFR[0]

Bits 0-3: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[1]

Bits 4-7: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[2]

Bits 8-11: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[3]

Bits 12-15: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[4]

Bits 16-19: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[5]

Bits 20-23: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[6]

Bits 24-27: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[7]

Bits 28-31: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[15]
rw
AFR[14]
rw
AFR[13]
rw
AFR[12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[11]
rw
AFR[10]
rw
AFR[9]
rw
AFR[8]
rw
Toggle fields

AFR[8]

Bits 0-3: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[9]

Bits 4-7: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[10]

Bits 8-11: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[11]

Bits 12-15: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[12]

Bits 16-19: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[13]

Bits 20-23: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[14]

Bits 24-27: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[15]

Bits 28-31: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

GPIOJ

0x58022400: GPIO

161/161 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw
MODER[14]
rw
MODER[13]
rw
MODER[12]
rw
MODER[11]
rw
MODER[10]
rw
MODER[9]
rw
MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw
MODER[6]
rw
MODER[5]
rw
MODER[4]
rw
MODER[3]
rw
MODER[2]
rw
MODER[1]
rw
MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw
PUPDR[14]
rw
PUPDR[13]
rw
PUPDR[12]
rw
PUPDR[11]
rw
PUPDR[10]
rw
PUPDR[9]
rw
PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw
PUPDR[6]
rw
PUPDR[5]
rw
PUPDR[4]
rw
PUPDR[3]
rw
PUPDR[2]
rw
PUPDR[1]
rw
PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset.A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence.Each lock bit freezes a specific configuration register (control and alternate function registers).

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw
LCK[14]
rw
LCK[13]
rw
LCK[12]
rw
LCK[11]
rw
LCK[10]
rw
LCK[9]
rw
LCK[8]
rw
LCK[7]
rw
LCK[6]
rw
LCK[5]
rw
LCK[4]
rw
LCK[3]
rw
LCK[2]
rw
LCK[1]
rw
LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit will return 1 until the next MCU reset or peripheral reset..

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[7]
rw
AFR[6]
rw
AFR[5]
rw
AFR[4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[3]
rw
AFR[2]
rw
AFR[1]
rw
AFR[0]
rw
Toggle fields

AFR[0]

Bits 0-3: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[1]

Bits 4-7: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[2]

Bits 8-11: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[3]

Bits 12-15: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[4]

Bits 16-19: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[5]

Bits 20-23: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[6]

Bits 24-27: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[7]

Bits 28-31: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[15]
rw
AFR[14]
rw
AFR[13]
rw
AFR[12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[11]
rw
AFR[10]
rw
AFR[9]
rw
AFR[8]
rw
Toggle fields

AFR[8]

Bits 0-3: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[9]

Bits 4-7: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[10]

Bits 8-11: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[11]

Bits 12-15: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[12]

Bits 16-19: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[13]

Bits 20-23: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[14]

Bits 24-27: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[15]

Bits 28-31: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

GPIOK

0x58022800: GPIO

161/161 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw
MODER[14]
rw
MODER[13]
rw
MODER[12]
rw
MODER[11]
rw
MODER[10]
rw
MODER[9]
rw
MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw
MODER[6]
rw
MODER[5]
rw
MODER[4]
rw
MODER[3]
rw
MODER[2]
rw
MODER[1]
rw
MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw
PUPDR[14]
rw
PUPDR[13]
rw
PUPDR[12]
rw
PUPDR[11]
rw
PUPDR[10]
rw
PUPDR[9]
rw
PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw
PUPDR[6]
rw
PUPDR[5]
rw
PUPDR[4]
rw
PUPDR[3]
rw
PUPDR[2]
rw
PUPDR[1]
rw
PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset.A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence.Each lock bit freezes a specific configuration register (control and alternate function registers).

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw
LCK[14]
rw
LCK[13]
rw
LCK[12]
rw
LCK[11]
rw
LCK[10]
rw
LCK[9]
rw
LCK[8]
rw
LCK[7]
rw
LCK[6]
rw
LCK[5]
rw
LCK[4]
rw
LCK[3]
rw
LCK[2]
rw
LCK[1]
rw
LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit will return 1 until the next MCU reset or peripheral reset..

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[7]
rw
AFR[6]
rw
AFR[5]
rw
AFR[4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[3]
rw
AFR[2]
rw
AFR[1]
rw
AFR[0]
rw
Toggle fields

AFR[0]

Bits 0-3: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[1]

Bits 4-7: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[2]

Bits 8-11: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[3]

Bits 12-15: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[4]

Bits 16-19: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[5]

Bits 20-23: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[6]

Bits 24-27: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[7]

Bits 28-31: [3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[15]
rw
AFR[14]
rw
AFR[13]
rw
AFR[12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[11]
rw
AFR[10]
rw
AFR[9]
rw
AFR[8]
rw
Toggle fields

AFR[8]

Bits 0-3: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[9]

Bits 4-7: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[10]

Bits 8-11: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[11]

Bits 12-15: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[12]

Bits 16-19: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[13]

Bits 20-23: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[14]

Bits 24-27: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[15]

Bits 28-31: [3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os.

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

HASH

0x48021400: Hash processor

17/86 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 DIN
0x8 STR
0xc HR[0]
0x10 HR[1]
0x14 HR[2]
0x18 HR[3]
0x1c HR[4]
0x20 IMR
0x24 SR
0xf8 CSR[0]
0xfc CSR[1]
0x100 CSR[2]
0x104 CSR[3]
0x108 CSR[4]
0x10c CSR[5]
0x110 CSR[6]
0x114 CSR[7]
0x118 CSR[8]
0x11c CSR[9]
0x120 CSR[10]
0x124 CSR[11]
0x128 CSR[12]
0x12c CSR[13]
0x130 CSR[14]
0x134 CSR[15]
0x138 CSR[16]
0x13c CSR[17]
0x140 CSR[18]
0x144 CSR[19]
0x148 CSR[20]
0x14c CSR[21]
0x150 CSR[22]
0x154 CSR[23]
0x158 CSR[24]
0x15c CSR[25]
0x160 CSR[26]
0x164 CSR[27]
0x168 CSR[28]
0x16c CSR[29]
0x170 CSR[30]
0x174 CSR[31]
0x178 CSR[32]
0x17c CSR[33]
0x180 CSR[34]
0x184 CSR[35]
0x188 CSR[36]
0x18c CSR[37]
0x190 CSR[38]
0x194 CSR[39]
0x198 CSR[40]
0x19c CSR[41]
0x1a0 CSR[42]
0x1a4 CSR[43]
0x1a8 CSR[44]
0x1ac CSR[45]
0x1b0 CSR[46]
0x1b4 CSR[47]
0x1b8 CSR[48]
0x1bc CSR[49]
0x1c0 CSR[50]
0x1c4 CSR[51]
0x1c8 CSR[52]
0x1cc CSR[53]
0x310 HASH_HR[0]
0x314 HASH_HR[1]
0x318 HASH_HR[2]
0x31c HASH_HR[3]
0x320 HASH_HR[4]
0x324 HASH_HR[5]
0x328 HASH_HR[6]
0x32c HASH_HR[7]
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

2/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALGO1
rw
LKEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDMAT
rw
DINNE
r
NBW
r
ALGO0
rw
MODE
rw
DATATYPE
rw
DMAE
rw
INIT
w
Toggle fields

INIT

Bit 2: Initialize message digest calculation.

DMAE

Bit 3: DMA enable.

DATATYPE

Bits 4-5: Data type selection.

MODE

Bit 6: Mode selection.

ALGO0

Bit 7: Algorithm selection.

NBW

Bits 8-11: Number of words already pushed.

DINNE

Bit 12: DIN not empty.

MDMAT

Bit 13: Multiple DMA Transfers.

LKEY

Bit 16: Long key selection.

ALGO1

Bit 18: ALGO.

DIN

data input register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAIN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAIN
rw
Toggle fields

DATAIN

Bits 0-31: Data input.

STR

start register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCAL
w
NBLW
rw
Toggle fields

NBLW

Bits 0-4: Number of valid bits in the last word of the message.

DCAL

Bit 8: Digest calculation.

HR[0]

digest registers

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H
r
Toggle fields

H

Bits 0-31: H0.

HR[1]

digest registers

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H
r
Toggle fields

H

Bits 0-31: H0.

HR[2]

digest registers

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H
r
Toggle fields

H

Bits 0-31: H0.

HR[3]

digest registers

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H
r
Toggle fields

H

Bits 0-31: H0.

HR[4]

digest registers

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H
r
Toggle fields

H

Bits 0-31: H0.

IMR

interrupt enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCIE
rw
DINIE
rw
Toggle fields

DINIE

Bit 0: Data input interrupt enable.

DCIE

Bit 1: Digest calculation completion interrupt enable.

SR

status register

Offset: 0x24, size: 32, reset: 0x00000001, access: Unspecified

2/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r
DMAS
r
DCIS
rw
DINIS
rw
Toggle fields

DINIS

Bit 0: Data input interrupt status.

DCIS

Bit 1: Digest calculation completion interrupt status.

DMAS

Bit 2: DMA Status.

BUSY

Bit 3: Busy bit.

CSR[0]

context swap registers

Offset: 0xf8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[1]

context swap registers

Offset: 0xfc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[2]

context swap registers

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[3]

context swap registers

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[4]

context swap registers

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[5]

context swap registers

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[6]

context swap registers

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[7]

context swap registers

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[8]

context swap registers

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[9]

context swap registers

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[10]

context swap registers

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[11]

context swap registers

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[12]

context swap registers

Offset: 0x128, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[13]

context swap registers

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[14]

context swap registers

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[15]

context swap registers

Offset: 0x134, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[16]

context swap registers

Offset: 0x138, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[17]

context swap registers

Offset: 0x13c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[18]

context swap registers

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[19]

context swap registers

Offset: 0x144, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[20]

context swap registers

Offset: 0x148, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[21]

context swap registers

Offset: 0x14c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[22]

context swap registers

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[23]

context swap registers

Offset: 0x154, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[24]

context swap registers

Offset: 0x158, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[25]

context swap registers

Offset: 0x15c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[26]

context swap registers

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[27]

context swap registers

Offset: 0x164, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[28]

context swap registers

Offset: 0x168, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[29]

context swap registers

Offset: 0x16c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[30]

context swap registers

Offset: 0x170, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[31]

context swap registers

Offset: 0x174, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[32]

context swap registers

Offset: 0x178, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[33]

context swap registers

Offset: 0x17c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[34]

context swap registers

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[35]

context swap registers

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[36]

context swap registers

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[37]

context swap registers

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[38]

context swap registers

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[39]

context swap registers

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[40]

context swap registers

Offset: 0x198, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[41]

context swap registers

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[42]

context swap registers

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[43]

context swap registers

Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[44]

context swap registers

Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[45]

context swap registers

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[46]

context swap registers

Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[47]

context swap registers

Offset: 0x1b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[48]

context swap registers

Offset: 0x1b8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[49]

context swap registers

Offset: 0x1bc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[50]

context swap registers

Offset: 0x1c0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[51]

context swap registers

Offset: 0x1c4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[52]

context swap registers

Offset: 0x1c8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[53]

context swap registers

Offset: 0x1cc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

HASH_HR[0]

HASH digest register 0

Offset: 0x310, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H
r
Toggle fields

H

Bits 0-31: H0.

HASH_HR[1]

HASH digest register 1

Offset: 0x314, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H
r
Toggle fields

H

Bits 0-31: H0.

HASH_HR[2]

HASH digest register 2

Offset: 0x318, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H
r
Toggle fields

H

Bits 0-31: H0.

HASH_HR[3]

HASH digest register 3

Offset: 0x31c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H
r
Toggle fields

H

Bits 0-31: H0.

HASH_HR[4]

HASH digest register 4

Offset: 0x320, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H
r
Toggle fields

H

Bits 0-31: H0.

HASH_HR[5]

HASH digest register 5

Offset: 0x324, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H
r
Toggle fields

H

Bits 0-31: H0.

HASH_HR[6]

HASH digest register 6

Offset: 0x328, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H
r
Toggle fields

H

Bits 0-31: H0.

HASH_HR[7]

HASH digest register 7

Offset: 0x32c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H
r
Toggle fields

H

Bits 0-31: H0.

HRTIM_Common

0x40017780: High Resolution Timer: Common functions

426/430 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 ISR
0xc ICR
0x10 IER
0x14 OENR
0x18 ODISR
0x1c ODSR
0x20 BMCR
0x24 BMTRGR
0x28 BMCMPR
0x2c BMPER
0x30 EECR1
0x34 EECR2
0x38 EECR3
0x3c ADC1R
0x40 ADC2R
0x44 ADC3R
0x48 ADC4R
0x50 FLTINR1
0x54 FLTINR2
0x58 BDMUPR
0x5c BDTAUPR
0x60 BDTBUPR
0x64 BDTCUPR
0x68 BDTDUPR
0x6c BDTEUPR
0x70 BDMADR
Toggle registers

CR1

Control Register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AD[4]USRC
rw
AD[3]USRC
rw
AD[2]USRC
rw
AD[1]USRC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T[E]UDIS
rw
T[D]UDIS
rw
T[C]UDIS
rw
T[B]UDIS
rw
T[A]UDIS
rw
MUDIS
rw
Toggle fields

MUDIS

Bit 0: Master Update Disable.

Allowed values:
0: Enabled: Timer update enabled
1: Disabled: Timer update disabled

T[A]UDIS

Bit 1: Timer A Update Disable.

Allowed values:
0: Enabled: Timer update enabled
1: Disabled: Timer update disabled

T[B]UDIS

Bit 2: Timer B Update Disable.

Allowed values:
0: Enabled: Timer update enabled
1: Disabled: Timer update disabled

T[C]UDIS

Bit 3: Timer C Update Disable.

Allowed values:
0: Enabled: Timer update enabled
1: Disabled: Timer update disabled

T[D]UDIS

Bit 4: Timer D Update Disable.

Allowed values:
0: Enabled: Timer update enabled
1: Disabled: Timer update disabled

T[E]UDIS

Bit 5: Timer E Update Disable.

Allowed values:
0: Enabled: Timer update enabled
1: Disabled: Timer update disabled

AD[1]USRC

Bits 16-18: ADC Trigger 1 Update Source.

Allowed values:
0: Master: ADC trigger update from master timer
1: TimerA: ADC trigger update from timer A
2: TimerB: ADC trigger update from timer B
3: TimerC: ADC trigger update from timer C
4: TimerD: ADC trigger update from timer D
5: TimerE: ADC trigger update from timer E

AD[2]USRC

Bits 19-21: ADC Trigger 2 Update Source.

Allowed values:
0: Master: ADC trigger update from master timer
1: TimerA: ADC trigger update from timer A
2: TimerB: ADC trigger update from timer B
3: TimerC: ADC trigger update from timer C
4: TimerD: ADC trigger update from timer D
5: TimerE: ADC trigger update from timer E

AD[3]USRC

Bits 22-24: ADC Trigger 3 Update Source.

Allowed values:
0: Master: ADC trigger update from master timer
1: TimerA: ADC trigger update from timer A
2: TimerB: ADC trigger update from timer B
3: TimerC: ADC trigger update from timer C
4: TimerD: ADC trigger update from timer D
5: TimerE: ADC trigger update from timer E

AD[4]USRC

Bits 25-27: ADC Trigger 4 Update Source.

Allowed values:
0: Master: ADC trigger update from master timer
1: TimerA: ADC trigger update from timer A
2: TimerB: ADC trigger update from timer B
3: TimerC: ADC trigger update from timer C
4: TimerD: ADC trigger update from timer D
5: TimerE: ADC trigger update from timer E

CR2

Control Register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

Toggle fields

MSWU

Bit 0: Master Timer Software update.

Allowed values:
1: Update: Force immediate update

T[A]SWU

Bit 1: Timer A Software Update.

Allowed values:
1: Update: Force immediate update

T[B]SWU

Bit 2: Timer B Software Update.

Allowed values:
1: Update: Force immediate update

T[C]SWU

Bit 3: Timer C Software Update.

Allowed values:
1: Update: Force immediate update

T[D]SWU

Bit 4: Timer D Software Update.

Allowed values:
1: Update: Force immediate update

T[E]SWU

Bit 5: Timer E Software Update.

Allowed values:
1: Update: Force immediate update

MRST

Bit 8: Master Counter software reset.

Allowed values:
1: Reset: Reset timer

T[A]RST

Bit 9: Timer A counter software reset.

Allowed values:
1: Reset: Reset timer

T[B]RST

Bit 10: Timer B counter software reset.

Allowed values:
1: Reset: Reset timer

T[C]RST

Bit 11: Timer C counter software reset.

Allowed values:
1: Reset: Reset timer

T[D]RST

Bit 12: Timer D counter software reset.

Allowed values:
1: Reset: Reset timer

T[E]RST

Bit 13: Timer E counter software reset.

Allowed values:
1: Reset: Reset timer

ISR

Interrupt Status Register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BMPER
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYSFLT
rw
FLT5
r
FLT4
r
FLT3
r
FLT2
r
FLT1
r
Toggle fields

FLT1

Bit 0: Fault 1 Interrupt Flag.

Allowed values:
0: NoEvent: No fault interrupt occurred
1: Event: Fault interrupt occurred

FLT2

Bit 1: Fault 2 Interrupt Flag.

Allowed values:
0: NoEvent: No fault interrupt occurred
1: Event: Fault interrupt occurred

FLT3

Bit 2: Fault 3 Interrupt Flag.

Allowed values:
0: NoEvent: No fault interrupt occurred
1: Event: Fault interrupt occurred

FLT4

Bit 3: Fault 4 Interrupt Flag.

Allowed values:
0: NoEvent: No fault interrupt occurred
1: Event: Fault interrupt occurred

FLT5

Bit 4: Fault 5 Interrupt Flag.

Allowed values:
0: NoEvent: No fault interrupt occurred
1: Event: Fault interrupt occurred

SYSFLT

Bit 5: System Fault Interrupt Flag.

Allowed values:
0: NoEvent: No fault interrupt occurred
1: Event: Fault interrupt occurred

BMPER

Bit 17: Burst mode Period Interrupt Flag.

Allowed values:
0: NoEvent: No burst mode period interrupt occurred
1: Event: Burst mode period interrupt occured

ICR

Interrupt Clear Register

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BMPERC
w1c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYSFLTC
w1c
FLT5C
w1c
FLT4C
w1c
FLT3C
w1c
FLT2C
w1c
FLT1C
w1c
Toggle fields

FLT1C

Bit 0: Fault 1 Interrupt Flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

FLT2C

Bit 1: Fault 2 Interrupt Flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

FLT3C

Bit 2: Fault 3 Interrupt Flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

FLT4C

Bit 3: Fault 4 Interrupt Flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

FLT5C

Bit 4: Fault 5 Interrupt Flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

SYSFLTC

Bit 5: System Fault Interrupt Flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

BMPERC

Bit 17: Burst mode period flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

IER

Interrupt Enable Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BMPERIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYSFLTIE
rw
FLT5IE
rw
FLT4IE
rw
FLT3IE
rw
FLT2IE
rw
FLT1IE
rw
Toggle fields

FLT1IE

Bit 0: Fault 1 Interrupt Enable.

Allowed values:
0: Disabled: Fault interrupt disabled
1: Enabled: Fault interrupt enabled

FLT2IE

Bit 1: Fault 2 Interrupt Enable.

Allowed values:
0: Disabled: Fault interrupt disabled
1: Enabled: Fault interrupt enabled

FLT3IE

Bit 2: Fault 3 Interrupt Enable.

Allowed values:
0: Disabled: Fault interrupt disabled
1: Enabled: Fault interrupt enabled

FLT4IE

Bit 3: Fault 4 Interrupt Enable.

Allowed values:
0: Disabled: Fault interrupt disabled
1: Enabled: Fault interrupt enabled

FLT5IE

Bit 4: Fault 5 Interrupt Enable.

Allowed values:
0: Disabled: Fault interrupt disabled
1: Enabled: Fault interrupt enabled

SYSFLTIE

Bit 5: System Fault Interrupt Enable.

Allowed values:
0: Disabled: Fault interrupt disabled
1: Enabled: Fault interrupt enabled

BMPERIE

Bit 17: Burst mode period Interrupt Enable.

Allowed values:
0: Disabled: Burst mode period interrupt disabled
1: Enabled: Burst mode period interrupt enabled

OENR

Output Enable Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T[E]2OEN
r/w1s
T[E]1OEN
r/w1s
T[D]2OEN
r/w1s
T[D]1OEN
r/w1s
T[C]2OEN
r/w1s
T[C]1OEN
r/w1s
T[B]2OEN
r/w1s
T[B]1OEN
r/w1s
T[A]2OEN
r/w1s
T[A]1OEN
r/w1s
Toggle fields

T[A]1OEN

Bit 0: Timer A Output 1 Enable.

Allowed values:
0: Disabled: Output disabled
1: Enabled: Output enabled

T[A]2OEN

Bit 1: Timer A Output 2 Enable.

Allowed values:
0: Disabled: Output disabled
1: Enabled: Output enabled

T[B]1OEN

Bit 2: Timer B Output 1 Enable.

Allowed values:
0: Disabled: Output disabled
1: Enabled: Output enabled

T[B]2OEN

Bit 3: Timer B Output 2 Enable.

Allowed values:
0: Disabled: Output disabled
1: Enabled: Output enabled

T[C]1OEN

Bit 4: Timer C Output 1 Enable.

Allowed values:
0: Disabled: Output disabled
1: Enabled: Output enabled

T[C]2OEN

Bit 5: Timer C Output 2 Enable.

Allowed values:
0: Disabled: Output disabled
1: Enabled: Output enabled

T[D]1OEN

Bit 6: Timer D Output 1 Enable.

Allowed values:
0: Disabled: Output disabled
1: Enabled: Output enabled

T[D]2OEN

Bit 7: Timer D Output 2 Enable.

Allowed values:
0: Disabled: Output disabled
1: Enabled: Output enabled

T[E]1OEN

Bit 8: Timer E Output 1 Enable.

Allowed values:
0: Disabled: Output disabled
1: Enabled: Output enabled

T[E]2OEN

Bit 9: Timer E Output 2 Enable.

Allowed values:
0: Disabled: Output disabled
1: Enabled: Output enabled

ODISR

DISR

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

10/10 fields covered.

Toggle fields

T[A]1ODIS

Bit 0: TA1ODIS.

Allowed values:
1: Disable: Disable output

T[A]2ODIS

Bit 1: TA2ODIS.

Allowed values:
1: Disable: Disable output

T[B]1ODIS

Bit 2: TB1ODIS.

Allowed values:
1: Disable: Disable output

T[B]2ODIS

Bit 3: TB2ODIS.

Allowed values:
1: Disable: Disable output

T[C]1ODIS

Bit 4: TC1ODIS.

Allowed values:
1: Disable: Disable output

T[C]2ODIS

Bit 5: TC2ODIS.

Allowed values:
1: Disable: Disable output

T[D]1ODIS

Bit 6: TD1ODIS.

Allowed values:
1: Disable: Disable output

T[D]2ODIS

Bit 7: TD2ODIS.

Allowed values:
1: Disable: Disable output

T[E]1ODIS

Bit 8: TE1ODIS.

Allowed values:
1: Disable: Disable output

T[E]2ODIS

Bit 9: TE2ODIS.

Allowed values:
1: Disable: Disable output

ODSR

Output Disable Status Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

10/10 fields covered.

Toggle fields

T[A]1ODS

Bit 0: Timer A Output 1 disable status.

Allowed values:
0: Idle: Output disabled in idle state
1: Fault: Output disabled in fault state

T[A]2ODS

Bit 1: Timer A Output 2 disable status.

Allowed values:
0: Idle: Output disabled in idle state
1: Fault: Output disabled in fault state

T[B]1ODS

Bit 2: Timer B Output 1 disable status.

Allowed values:
0: Idle: Output disabled in idle state
1: Fault: Output disabled in fault state

T[B]2ODS

Bit 3: Timer B Output 2 disable status.

Allowed values:
0: Idle: Output disabled in idle state
1: Fault: Output disabled in fault state

T[C]1ODS

Bit 4: Timer C Output 1 disable status.

Allowed values:
0: Idle: Output disabled in idle state
1: Fault: Output disabled in fault state

T[C]2ODS

Bit 5: Timer C Output 2 disable status.

Allowed values:
0: Idle: Output disabled in idle state
1: Fault: Output disabled in fault state

T[D]1ODS

Bit 6: Timer D Output 1 disable status.

Allowed values:
0: Idle: Output disabled in idle state
1: Fault: Output disabled in fault state

T[D]2ODS

Bit 7: Timer D Output 2 disable status.

Allowed values:
0: Idle: Output disabled in idle state
1: Fault: Output disabled in fault state

T[E]1ODS

Bit 8: Timer E Output 1 disable status.

Allowed values:
0: Idle: Output disabled in idle state
1: Fault: Output disabled in fault state

T[E]2ODS

Bit 9: Timer E Output 2 disable status.

Allowed values:
0: Idle: Output disabled in idle state
1: Fault: Output disabled in fault state

BMCR

Burst Mode Control Register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BMSTAT
r/w0c
T[E]BM
rw
T[D]BM
rw
T[C]BM
rw
T[B]BM
rw
T[A]BM
rw
MTBM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BMPREN
rw
BMPRSC
rw
BMCLK
rw
BMOM
rw
BME
rw
Toggle fields

BME

Bit 0: Burst Mode enable.

Allowed values:
0: Disabled: Burst mode disabled
1: Enabled: Burst mode enabled

BMOM

Bit 1: Burst Mode operating mode.

Allowed values:
0: SingleShot: Single-shot mode
1: Continuous: Continuous operation

BMCLK

Bits 2-5: Burst Mode Clock source.

Allowed values:
0: Master: Master timer reset/roll-over
1: TimerA: Timer A counter reset/roll-over
2: TimerB: Timer B counter reset/roll-over
3: TimerC: Timer C counter reset/roll-over
4: TimerD: Timer D counter reset/roll-over
5: TimerE: Timer E counter reset/roll-over
6: Event1: On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock
7: Event2: On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock
8: Event3: On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock
9: Event4: On-chip Event 4 (BMClk[4]), acting as a burst mode counter clock
10: Clock: Prescaled f_HRTIM clock (as per BMPRSC[3:0] setting

BMPRSC

Bits 6-9: Burst Mode Prescaler.

Allowed values:
0: Div1: Clock not divided
1: Div2: Division by 2
2: Div4: Division by 4
3: Div8: Division by 8
4: Div16: Division by 16
5: Div32: Division by 32
6: Div64: Division by 64
7: Div128: Division by 128
8: Div256: Division by 256
9: Div512: Division by 512
10: Div1024: Division by 1024
11: Div2048: Division by 2048
12: Div4096: Division by 4096
13: Div8192: Division by 8192
14: Div16384: Division by 16384
15: Div32768: Division by 32768

BMPREN

Bit 10: Burst Mode Preload Enable.

Allowed values:
0: Disabled: Preload disabled: the write access is directly done into active registers
1: Enabled: Preload enabled: the write access is done into preload registers

MTBM

Bit 16: Master Timer Burst Mode.

Allowed values:
0: Normal: Counter clock is maintained and timer operates normally
1: Stopped: Counter clock is stopped and counter is reset

T[A]BM

Bit 17: Timer A Burst Mode.

Allowed values:
0: Normal: Counter clock is maintained and timer operates normally
1: Stopped: Counter clock is stopped and counter is reset

T[B]BM

Bit 18: Timer B Burst Mode.

Allowed values:
0: Normal: Counter clock is maintained and timer operates normally
1: Stopped: Counter clock is stopped and counter is reset

T[C]BM

Bit 19: Timer C Burst Mode.

Allowed values:
0: Normal: Counter clock is maintained and timer operates normally
1: Stopped: Counter clock is stopped and counter is reset

T[D]BM

Bit 20: Timer D Burst Mode.

Allowed values:
0: Normal: Counter clock is maintained and timer operates normally
1: Stopped: Counter clock is stopped and counter is reset

T[E]BM

Bit 21: Timer E Burst Mode.

Allowed values:
0: Normal: Counter clock is maintained and timer operates normally
1: Stopped: Counter clock is stopped and counter is reset

BMSTAT

Bit 31: Burst Mode Status.

Allowed values:
0: Normal: Normal operation
1: Burst: Burst operation ongoing

BMTRGR

BMTRG

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

28/32 fields covered.

Toggle fields

SW

Bit 0: SW.

Allowed values:
0: NoEffect: No effect
1: Trigger: Trigger immediate burst mode operation

MSTRST

Bit 1: MSTRST.

Allowed values:
0: NoEffect: Master timer reset/roll-over event has no effect
1: Trigger: Master timer reset/roll-over event triggers a burst mode entry

MSTREP

Bit 2: MSTREP.

Allowed values:
0: NoEffect: Master timer repetition event has no effect
1: Trigger: Master timer repetition event triggers a burst mode entry

MSTCMP1

Bit 3: MSTCMP1.

Allowed values:
0: NoEffect: Master timer compare X event has no effect
1: Trigger: Master timer compare X event triggers a burst mode entry

MSTCMP2

Bit 4: MSTCMP2.

Allowed values:
0: NoEffect: Master timer compare X event has no effect
1: Trigger: Master timer compare X event triggers a burst mode entry

MSTCMP3

Bit 5: MSTCMP3.

Allowed values:
0: NoEffect: Master timer compare X event has no effect
1: Trigger: Master timer compare X event triggers a burst mode entry

MSTCMP4

Bit 6: MSTCMP4.

Allowed values:
0: NoEffect: Master timer compare X event has no effect
1: Trigger: Master timer compare X event triggers a burst mode entry

TARST

Bit 7: TARST.

Allowed values:
0: NoEffect: Timer X reset/roll-over event has no effect
1: Trigger: Timer X reset/roll-over event triggers a burst mode entry

TAREP

Bit 8: TAREP.

Allowed values:
0: NoEffect: Timer X repetition event has no effect
1: Trigger: Timer X repetition event triggers a burst mode entry

TACMP1

Bit 9: TACMP1.

Allowed values:
0: NoEffect: Timer X compare Y event has no effect
1: Trigger: Timer X compare Y event triggers a burst mode entry

TACMP2

Bit 10: TACMP2.

Allowed values:
0: NoEffect: Timer X compare Y event has no effect
1: Trigger: Timer X compare Y event triggers a burst mode entry

TBRST

Bit 11: TBRST.

Allowed values:
0: NoEffect: Timer X reset/roll-over event has no effect
1: Trigger: Timer X reset/roll-over event triggers a burst mode entry

TBREP

Bit 12: TBREP.

Allowed values:
0: NoEffect: Timer X repetition event has no effect
1: Trigger: Timer X repetition event triggers a burst mode entry

TBCMP1

Bit 13: TBCMP1.

Allowed values:
0: NoEffect: Timer X compare Y event has no effect
1: Trigger: Timer X compare Y event triggers a burst mode entry

TBCMP2

Bit 14: TBCMP2.

Allowed values:
0: NoEffect: Timer X compare Y event has no effect
1: Trigger: Timer X compare Y event triggers a burst mode entry

TCRST

Bit 15: TCRST.

Allowed values:
0: NoEffect: Timer X reset/roll-over event has no effect
1: Trigger: Timer X reset/roll-over event triggers a burst mode entry

TCREP

Bit 16: TCREP.

Allowed values:
0: NoEffect: Timer X repetition event has no effect
1: Trigger: Timer X repetition event triggers a burst mode entry

TCCMP1

Bit 17: TCCMP1.

Allowed values:
0: NoEffect: Timer X compare Y event has no effect
1: Trigger: Timer X compare Y event triggers a burst mode entry

TCCMP2

Bit 18: TCCMP2.

Allowed values:
0: NoEffect: Timer X compare Y event has no effect
1: Trigger: Timer X compare Y event triggers a burst mode entry

TDRST

Bit 19: TDRST.

Allowed values:
0: NoEffect: Timer X reset/roll-over event has no effect
1: Trigger: Timer X reset/roll-over event triggers a burst mode entry

TDREP

Bit 20: TDREP.

Allowed values:
0: NoEffect: Timer X repetition event has no effect
1: Trigger: Timer X repetition event triggers a burst mode entry

TDCMP1

Bit 21: TDCMP1.

Allowed values:
0: NoEffect: Timer X compare Y event has no effect
1: Trigger: Timer X compare Y event triggers a burst mode entry

TDCMP2

Bit 22: TDCMP2.

Allowed values:
0: NoEffect: Timer X compare Y event has no effect
1: Trigger: Timer X compare Y event triggers a burst mode entry

TERST

Bit 23: TERST.

Allowed values:
0: NoEffect: Timer X reset/roll-over event has no effect
1: Trigger: Timer X reset/roll-over event triggers a burst mode entry

TEREP

Bit 24: TEREP.

Allowed values:
0: NoEffect: Timer X repetition event has no effect
1: Trigger: Timer X repetition event triggers a burst mode entry

TECMP1

Bit 25: TECMP1.

Allowed values:
0: NoEffect: Timer X compare Y event has no effect
1: Trigger: Timer X compare Y event triggers a burst mode entry

TECMP2

Bit 26: TECMP2.

Allowed values:
0: NoEffect: Timer X compare Y event has no effect
1: Trigger: Timer X compare Y event triggers a burst mode entry

TAEEV7

Bit 27: Timer A period following External Event 7.

TDEEV8

Bit 28: Timer D period following External Event 8.

EEV7

Bit 29: External Event 7 (TIMA filters applied).

EEV8

Bit 30: External Event 8 (TIMD filters applied).

OCHPEV

Bit 31: OCHPEV.

Allowed values:
0: NoEffect: Rising edge on an on-chip event has no effect
1: Trigger: Rising edge on an on-chip event triggers a burst mode entry

BMCMPR

BMCMPR6

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BMCMP
rw
Toggle fields

BMCMP

Bits 0-15: BMCMP.

Allowed values: 0x0-0xffff

BMPER

Burst Mode Period Register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BMPER
rw
Toggle fields

BMPER

Bits 0-15: Burst mode Period.

Allowed values: 0x0-0xffff

EECR1

Timer External Event Control Register 1

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

Toggle fields

EE[1]SRC

Bits 0-1: External Event 1 Source.

Allowed values:
0: Src1: Source 1
1: Src2: Source 2
2: Src3: Source 3
3: Src4: Source 4

EE[1]POL

Bit 2: External Event 1 Polarity.

Allowed values:
0: ActiveHigh: External event is active high
1: ActiveLow: External event is active low

EE[1]SNS

Bits 3-4: External Event 1 Sensitivity.

Allowed values:
0: Active: On active level defined by EExPOL bit
1: Rising: Rising edge
2: Falling: Falling edge
3: Both: Both edges

EE[1]FAST

Bit 5: External Event 1 Fast mode.

Allowed values:
0: Resynchronized: External event is re-synchronised by the HRTIM logic before acting on outputs
1: Asynchronous: External event is acting asynchronously on outputs (low-latency mode)

EE[2]SRC

Bits 6-7: External Event 2 Source.

Allowed values:
0: Src1: Source 1
1: Src2: Source 2
2: Src3: Source 3
3: Src4: Source 4

EE[2]POL

Bit 8: External Event 2 Polarity.

Allowed values:
0: ActiveHigh: External event is active high
1: ActiveLow: External event is active low

EE[2]SNS

Bits 9-10: External Event 2 Sensitivity.

Allowed values:
0: Active: On active level defined by EExPOL bit
1: Rising: Rising edge
2: Falling: Falling edge
3: Both: Both edges

EE[2]FAST

Bit 11: External Event 2 Fast mode.

Allowed values:
0: Resynchronized: External event is re-synchronised by the HRTIM logic before acting on outputs
1: Asynchronous: External event is acting asynchronously on outputs (low-latency mode)

EE[3]SRC

Bits 12-13: External Event 3 Source.

Allowed values:
0: Src1: Source 1
1: Src2: Source 2
2: Src3: Source 3
3: Src4: Source 4

EE[3]POL

Bit 14: External Event 3 Polarity.

Allowed values:
0: ActiveHigh: External event is active high
1: ActiveLow: External event is active low

EE[3]SNS

Bits 15-16: External Event 3 Sensitivity.

Allowed values:
0: Active: On active level defined by EExPOL bit
1: Rising: Rising edge
2: Falling: Falling edge
3: Both: Both edges

EE[3]FAST

Bit 17: External Event 3 Fast mode.

Allowed values:
0: Resynchronized: External event is re-synchronised by the HRTIM logic before acting on outputs
1: Asynchronous: External event is acting asynchronously on outputs (low-latency mode)

EE[4]SRC

Bits 18-19: External Event 4 Source.

Allowed values:
0: Src1: Source 1
1: Src2: Source 2
2: Src3: Source 3
3: Src4: Source 4

EE[4]POL

Bit 20: External Event 4 Polarity.

Allowed values:
0: ActiveHigh: External event is active high
1: ActiveLow: External event is active low

EE[4]SNS

Bits 21-22: External Event 4 Sensitivity.

Allowed values:
0: Active: On active level defined by EExPOL bit
1: Rising: Rising edge
2: Falling: Falling edge
3: Both: Both edges

EE[4]FAST

Bit 23: External Event 4 Fast mode.

Allowed values:
0: Resynchronized: External event is re-synchronised by the HRTIM logic before acting on outputs
1: Asynchronous: External event is acting asynchronously on outputs (low-latency mode)

EE[5]SRC

Bits 24-25: External Event 5 Source.

Allowed values:
0: Src1: Source 1
1: Src2: Source 2
2: Src3: Source 3
3: Src4: Source 4

EE[5]POL

Bit 26: External Event 5 Polarity.

Allowed values:
0: ActiveHigh: External event is active high
1: ActiveLow: External event is active low

EE[5]SNS

Bits 27-28: External Event 5 Sensitivity.

Allowed values:
0: Active: On active level defined by EExPOL bit
1: Rising: Rising edge
2: Falling: Falling edge
3: Both: Both edges

EE[5]FAST

Bit 29: External Event 5 Fast mode.

Allowed values:
0: Resynchronized: External event is re-synchronised by the HRTIM logic before acting on outputs
1: Asynchronous: External event is acting asynchronously on outputs (low-latency mode)

EECR2

Timer External Event Control Register 2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EE[10]SNS
rw
EE[10]POL
rw
EE[10]SRC
rw
EE[9]SNS
rw
EE[9]POL
rw
EE[9]SRC
rw
EE[8]SNS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EE[8]SNS
rw
EE[8]POL
rw
EE[8]SRC
rw
EE[7]SNS
rw
EE[7]POL
rw
EE[7]SRC
rw
EE[6]SNS
rw
EE[6]POL
rw
EE[6]SRC
rw
Toggle fields

EE[6]SRC

Bits 0-1: External Event 6 Source.

Allowed values:
0: Src1: Source 1
1: Src2: Source 2
2: Src3: Source 3
3: Src4: Source 4

EE[6]POL

Bit 2: External Event 6 Polarity.

Allowed values:
0: ActiveHigh: External event is active high
1: ActiveLow: External event is active low

EE[6]SNS

Bits 3-4: External Event 6 Sensitivity.

Allowed values:
0: Active: On active level defined by EExPOL bit
1: Rising: Rising edge
2: Falling: Falling edge
3: Both: Both edges

EE[7]SRC

Bits 6-7: External Event 7 Source.

Allowed values:
0: Src1: Source 1
1: Src2: Source 2
2: Src3: Source 3
3: Src4: Source 4

EE[7]POL

Bit 8: External Event 7 Polarity.

Allowed values:
0: ActiveHigh: External event is active high
1: ActiveLow: External event is active low

EE[7]SNS

Bits 9-10: External Event 7 Sensitivity.

Allowed values:
0: Active: On active level defined by EExPOL bit
1: Rising: Rising edge
2: Falling: Falling edge
3: Both: Both edges

EE[8]SRC

Bits 12-13: External Event 8 Source.

Allowed values:
0: Src1: Source 1
1: Src2: Source 2
2: Src3: Source 3
3: Src4: Source 4

EE[8]POL

Bit 14: External Event 8 Polarity.

Allowed values:
0: ActiveHigh: External event is active high
1: ActiveLow: External event is active low

EE[8]SNS

Bits 15-16: External Event 8 Sensitivity.

Allowed values:
0: Active: On active level defined by EExPOL bit
1: Rising: Rising edge
2: Falling: Falling edge
3: Both: Both edges

EE[9]SRC

Bits 18-19: External Event 9 Source.

Allowed values:
0: Src1: Source 1
1: Src2: Source 2
2: Src3: Source 3
3: Src4: Source 4

EE[9]POL

Bit 20: External Event 9 Polarity.

Allowed values:
0: ActiveHigh: External event is active high
1: ActiveLow: External event is active low

EE[9]SNS

Bits 21-22: External Event 9 Sensitivity.

Allowed values:
0: Active: On active level defined by EExPOL bit
1: Rising: Rising edge
2: Falling: Falling edge
3: Both: Both edges

EE[10]SRC

Bits 24-25: External Event 10 Source.

Allowed values:
0: Src1: Source 1
1: Src2: Source 2
2: Src3: Source 3
3: Src4: Source 4

EE[10]POL

Bit 26: External Event 10 Polarity.

Allowed values:
0: ActiveHigh: External event is active high
1: ActiveLow: External event is active low

EE[10]SNS

Bits 27-28: External Event 10 Sensitivity.

Allowed values:
0: Active: On active level defined by EExPOL bit
1: Rising: Rising edge
2: Falling: Falling edge
3: Both: Both edges

EECR3

Timer External Event Control Register 3

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EEVSD
rw
EE10F
rw
EE9F
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EE8F
rw
EE7F
rw
EE6F
rw
Toggle fields

EE6F

Bits 0-3: External event 6 filter.

Allowed values:
0: Disabled: Filter disabled
1: Div1_N2: f_SAMPLING=f_HRTIM, N=2
2: Div1_N4: f_SAMPLING=f_HRTIM, N=4
3: Div1_N8: f_SAMPLING=f_HRTIM, N=8
4: Div2_N6: f_SAMPLING=f_EEVS/2, N=6
5: Div2_N8: f_SAMPLING=f_EEVS/2, N=8
6: Div4_N6: f_SAMPLING=f_EEVS/4, N=6
7: Div4_N8: f_SAMPLING=f_EEVS/4, N=8
8: Div8_N6: f_SAMPLING=f_EEVS/8, N=6
9: Div8_N8: f_SAMPLING=f_EEVS/8, N=8
10: Div16_N5: f_SAMPLING=f_EEVS/16, N=5
11: Div16_N6: f_SAMPLING=f_EEVS/16, N=6
12: Div16_N8: f_SAMPLING=f_EEVS/16, N=8
13: Div32_N5: f_SAMPLING=f_EEVS/32, N=5
14: Div32_N6: f_SAMPLING=f_EEVS/32, N=6
15: Div32_N8: f_SAMPLING=f_EEVS/32, N=8

EE7F

Bits 6-9: External event 7 filter.

Allowed values:
0: Disabled: Filter disabled
1: Div1_N2: f_SAMPLING=f_HRTIM, N=2
2: Div1_N4: f_SAMPLING=f_HRTIM, N=4
3: Div1_N8: f_SAMPLING=f_HRTIM, N=8
4: Div2_N6: f_SAMPLING=f_EEVS/2, N=6
5: Div2_N8: f_SAMPLING=f_EEVS/2, N=8
6: Div4_N6: f_SAMPLING=f_EEVS/4, N=6
7: Div4_N8: f_SAMPLING=f_EEVS/4, N=8
8: Div8_N6: f_SAMPLING=f_EEVS/8, N=6
9: Div8_N8: f_SAMPLING=f_EEVS/8, N=8
10: Div16_N5: f_SAMPLING=f_EEVS/16, N=5
11: Div16_N6: f_SAMPLING=f_EEVS/16, N=6
12: Div16_N8: f_SAMPLING=f_EEVS/16, N=8
13: Div32_N5: f_SAMPLING=f_EEVS/32, N=5
14: Div32_N6: f_SAMPLING=f_EEVS/32, N=6
15: Div32_N8: f_SAMPLING=f_EEVS/32, N=8

EE8F

Bits 12-15: External event 8 filter.

Allowed values:
0: Disabled: Filter disabled
1: Div1_N2: f_SAMPLING=f_HRTIM, N=2
2: Div1_N4: f_SAMPLING=f_HRTIM, N=4
3: Div1_N8: f_SAMPLING=f_HRTIM, N=8
4: Div2_N6: f_SAMPLING=f_EEVS/2, N=6
5: Div2_N8: f_SAMPLING=f_EEVS/2, N=8
6: Div4_N6: f_SAMPLING=f_EEVS/4, N=6
7: Div4_N8: f_SAMPLING=f_EEVS/4, N=8
8: Div8_N6: f_SAMPLING=f_EEVS/8, N=6
9: Div8_N8: f_SAMPLING=f_EEVS/8, N=8
10: Div16_N5: f_SAMPLING=f_EEVS/16, N=5
11: Div16_N6: f_SAMPLING=f_EEVS/16, N=6
12: Div16_N8: f_SAMPLING=f_EEVS/16, N=8
13: Div32_N5: f_SAMPLING=f_EEVS/32, N=5
14: Div32_N6: f_SAMPLING=f_EEVS/32, N=6
15: Div32_N8: f_SAMPLING=f_EEVS/32, N=8

EE9F

Bits 18-21: External event 9 filter.

Allowed values:
0: Disabled: Filter disabled
1: Div1_N2: f_SAMPLING=f_HRTIM, N=2
2: Div1_N4: f_SAMPLING=f_HRTIM, N=4
3: Div1_N8: f_SAMPLING=f_HRTIM, N=8
4: Div2_N6: f_SAMPLING=f_EEVS/2, N=6
5: Div2_N8: f_SAMPLING=f_EEVS/2, N=8
6: Div4_N6: f_SAMPLING=f_EEVS/4, N=6
7: Div4_N8: f_SAMPLING=f_EEVS/4, N=8
8: Div8_N6: f_SAMPLING=f_EEVS/8, N=6
9: Div8_N8: f_SAMPLING=f_EEVS/8, N=8
10: Div16_N5: f_SAMPLING=f_EEVS/16, N=5
11: Div16_N6: f_SAMPLING=f_EEVS/16, N=6
12: Div16_N8: f_SAMPLING=f_EEVS/16, N=8
13: Div32_N5: f_SAMPLING=f_EEVS/32, N=5
14: Div32_N6: f_SAMPLING=f_EEVS/32, N=6
15: Div32_N8: f_SAMPLING=f_EEVS/32, N=8

EE10F

Bits 24-27: External event 10 filter.

Allowed values:
0: Disabled: Filter disabled
1: Div1_N2: f_SAMPLING=f_HRTIM, N=2
2: Div1_N4: f_SAMPLING=f_HRTIM, N=4
3: Div1_N8: f_SAMPLING=f_HRTIM, N=8
4: Div2_N6: f_SAMPLING=f_EEVS/2, N=6
5: Div2_N8: f_SAMPLING=f_EEVS/2, N=8
6: Div4_N6: f_SAMPLING=f_EEVS/4, N=6
7: Div4_N8: f_SAMPLING=f_EEVS/4, N=8
8: Div8_N6: f_SAMPLING=f_EEVS/8, N=6
9: Div8_N8: f_SAMPLING=f_EEVS/8, N=8
10: Div16_N5: f_SAMPLING=f_EEVS/16, N=5
11: Div16_N6: f_SAMPLING=f_EEVS/16, N=6
12: Div16_N8: f_SAMPLING=f_EEVS/16, N=8
13: Div32_N5: f_SAMPLING=f_EEVS/32, N=5
14: Div32_N6: f_SAMPLING=f_EEVS/32, N=6
15: Div32_N8: f_SAMPLING=f_EEVS/32, N=8

EEVSD

Bits 30-31: External event sampling clock division.

Allowed values:
0: Div1: f_EEVS=f_HRTIM
1: Div2: f_EEVS=f_HRTIM/2
2: Div4: f_EEVS=f_HRTIM/4
3: Div8: f_EEVS=f_HRTIM/8

ADC1R

ADC Trigger 1 Register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPER
rw
EC4
rw
EC3
rw
EC2
rw
DPER
rw
DC4
rw
DC3
rw
DC2
rw
CPER
rw
CC4
rw
CC3
rw
CC2
rw
BRST
rw
BPER
rw
BC4
rw
BC3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BC2
rw
ARST
rw
APER
rw
AC4
rw
AC3
rw
AC2
rw
EEV[5]
rw
EEV[4]
rw
EEV[3]
rw
EEV[2]
rw
EEV[1]
rw
MPER
rw
MC[4]
rw
MC[3]
rw
MC[2]
rw
MC[1]
rw
Toggle fields

MC[1]

Bit 0: ADC trigger 1 on Master Compare 1.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MC[2]

Bit 1: ADC trigger 1 on Master Compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MC[3]

Bit 2: ADC trigger 1 on Master Compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MC[4]

Bit 3: ADC trigger 1 on Master Compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MPER

Bit 4: ADC trigger 1 on Master Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

EEV[1]

Bit 5: ADC trigger 1 on External Event 1.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[2]

Bit 6: ADC trigger 1 on External Event 2.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[3]

Bit 7: ADC trigger 1 on External Event 3.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[4]

Bit 8: ADC trigger 1 on External Event 4.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[5]

Bit 9: ADC trigger 1 on External Event 5.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

AC2

Bit 10: ADC trigger 1 on Timer A compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

AC3

Bit 11: ADC trigger 1 on Timer A compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

AC4

Bit 12: ADC trigger 1 on Timer A compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

APER

Bit 13: ADC trigger 1 on Timer A Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

ARST

Bit 14: ADC trigger 1 on Timer A Reset.

Allowed values:
0: Disabled: No generation of ADC trigger on timer reset and roll-over
1: Enabled: Generation of ADC trigger on timer reset and roll-over

BC2

Bit 15: ADC trigger 1 on Timer B compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

BC3

Bit 16: ADC trigger 1 on Timer B compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

BC4

Bit 17: ADC trigger 1 on Timer B compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

BPER

Bit 18: ADC trigger 1 on Timer B Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

BRST

Bit 19: ADC trigger 1 on Timer B Reset.

Allowed values:
0: Disabled: No generation of ADC trigger on timer reset and roll-over
1: Enabled: Generation of ADC trigger on timer reset and roll-over

CC2

Bit 20: ADC trigger 1 on Timer C compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

CC3

Bit 21: ADC trigger 1 on Timer C compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

CC4

Bit 22: ADC trigger 1 on Timer C compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

CPER

Bit 23: ADC trigger 1 on Timer C Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

DC2

Bit 24: ADC trigger 1 on Timer D compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

DC3

Bit 25: ADC trigger 1 on Timer D compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

DC4

Bit 26: ADC trigger 1 on Timer D compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

DPER

Bit 27: ADC trigger 1 on Timer D Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

EC2

Bit 28: ADC trigger 1 on Timer E compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

EC3

Bit 29: ADC trigger 1 on Timer E compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

EC4

Bit 30: ADC trigger 1 on Timer E compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

EPER

Bit 31: ADC trigger 1 on Timer E Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

ADC2R

ADC Trigger 2 Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ERST
rw
EC4
rw
EC3
rw
EC2
rw
DRST
rw
DPER
rw
DC4
rw
DC3
rw
DC2
rw
CRST
rw
CPER
rw
CC4
rw
CC3
rw
CC2
rw
BPER
rw
BC4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BC3
rw
BC2
rw
APER
rw
AC4
rw
AC3
rw
AC2
rw
EEV[10]
rw
EEV[9]
rw
EEV[8]
rw
EEV[7]
rw
EEV[6]
rw
MPER
rw
MC[4]
rw
MC[3]
rw
MC[2]
rw
MC[1]
rw
Toggle fields

MC[1]

Bit 0: ADC trigger 2 on Master Compare 1.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MC[2]

Bit 1: ADC trigger 2 on Master Compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MC[3]

Bit 2: ADC trigger 2 on Master Compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MC[4]

Bit 3: ADC trigger 2 on Master Compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MPER

Bit 4: ADC trigger 2 on Master Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

EEV[6]

Bit 5: ADC trigger 2 on External Event 6.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[7]

Bit 6: ADC trigger 2 on External Event 7.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[8]

Bit 7: ADC trigger 2 on External Event 8.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[9]

Bit 8: ADC trigger 2 on External Event 9.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[10]

Bit 9: ADC trigger 2 on External Event 10.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

AC2

Bit 10: ADC trigger 2 on Timer A compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

AC3

Bit 11: ADC trigger 2 on Timer A compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

AC4

Bit 12: ADC trigger 2 on Timer A compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

APER

Bit 13: ADC trigger 2 on Timer A Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

BC2

Bit 14: ADC trigger 2 on Timer B compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

BC3

Bit 15: ADC trigger 2 on Timer B compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

BC4

Bit 16: ADC trigger 2 on Timer B compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

BPER

Bit 17: ADC trigger 2 on Timer B Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

CC2

Bit 18: ADC trigger 2 on Timer C compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

CC3

Bit 19: ADC trigger 2 on Timer C compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

CC4

Bit 20: ADC trigger 2 on Timer C compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

CPER

Bit 21: ADC trigger 2 on Timer C Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

CRST

Bit 22: ADC trigger 2 on Timer C Reset.

Allowed values:
0: Disabled: No generation of ADC trigger on timer reset and roll-over
1: Enabled: Generation of ADC trigger on timer reset and roll-over

DC2

Bit 23: ADC trigger 2 on Timer D compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

DC3

Bit 24: ADC trigger 2 on Timer D compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

DC4

Bit 25: ADC trigger 2 on Timer D compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

DPER

Bit 26: ADC trigger 2 on Timer D Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

DRST

Bit 27: ADC trigger 2 on Timer D Reset.

Allowed values:
0: Disabled: No generation of ADC trigger on timer reset and roll-over
1: Enabled: Generation of ADC trigger on timer reset and roll-over

EC2

Bit 28: ADC trigger 2 on Timer E compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

EC3

Bit 29: ADC trigger 2 on Timer E compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

EC4

Bit 30: ADC trigger 2 on Timer E compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

ERST

Bit 31: ADC trigger 2 on Timer E Reset.

Allowed values:
0: Disabled: No generation of ADC trigger on timer reset and roll-over
1: Enabled: Generation of ADC trigger on timer reset and roll-over

ADC3R

ADC Trigger 3 Register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPER
rw
EC4
rw
EC3
rw
EC2
rw
DPER
rw
DC4
rw
DC3
rw
DC2
rw
CPER
rw
CC4
rw
CC3
rw
CC2
rw
BRST
rw
BPER
rw
BC4
rw
BC3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BC2
rw
ARST
rw
APER
rw
AC4
rw
AC3
rw
AC2
rw
EEV[5]
rw
EEV[4]
rw
EEV[3]
rw
EEV[2]
rw
EEV[1]
rw
MPER
rw
MC[4]
rw
MC[3]
rw
MC[2]
rw
MC[1]
rw
Toggle fields

MC[1]

Bit 0: ADC trigger 1 on Master Compare 1.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MC[2]

Bit 1: ADC trigger 1 on Master Compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MC[3]

Bit 2: ADC trigger 1 on Master Compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MC[4]

Bit 3: ADC trigger 1 on Master Compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MPER

Bit 4: ADC trigger 1 on Master Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

EEV[1]

Bit 5: ADC trigger 1 on External Event 1.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[2]

Bit 6: ADC trigger 1 on External Event 2.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[3]

Bit 7: ADC trigger 1 on External Event 3.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[4]

Bit 8: ADC trigger 1 on External Event 4.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[5]

Bit 9: ADC trigger 1 on External Event 5.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

AC2

Bit 10: ADC trigger 1 on Timer A compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

AC3

Bit 11: ADC trigger 1 on Timer A compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

AC4

Bit 12: ADC trigger 1 on Timer A compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

APER

Bit 13: ADC trigger 1 on Timer A Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

ARST

Bit 14: ADC trigger 1 on Timer A Reset.

Allowed values:
0: Disabled: No generation of ADC trigger on timer reset and roll-over
1: Enabled: Generation of ADC trigger on timer reset and roll-over

BC2

Bit 15: ADC trigger 1 on Timer B compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

BC3

Bit 16: ADC trigger 1 on Timer B compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

BC4

Bit 17: ADC trigger 1 on Timer B compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

BPER

Bit 18: ADC trigger 1 on Timer B Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

BRST

Bit 19: ADC trigger 1 on Timer B Reset.

Allowed values:
0: Disabled: No generation of ADC trigger on timer reset and roll-over
1: Enabled: Generation of ADC trigger on timer reset and roll-over

CC2

Bit 20: ADC trigger 1 on Timer C compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

CC3

Bit 21: ADC trigger 1 on Timer C compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

CC4

Bit 22: ADC trigger 1 on Timer C compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

CPER

Bit 23: ADC trigger 1 on Timer C Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

DC2

Bit 24: ADC trigger 1 on Timer D compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

DC3

Bit 25: ADC trigger 1 on Timer D compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

DC4

Bit 26: ADC trigger 1 on Timer D compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

DPER

Bit 27: ADC trigger 1 on Timer D Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

EC2

Bit 28: ADC trigger 1 on Timer E compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

EC3

Bit 29: ADC trigger 1 on Timer E compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

EC4

Bit 30: ADC trigger 1 on Timer E compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

EPER

Bit 31: ADC trigger 1 on Timer E Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

ADC4R

ADC Trigger 4 Register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ERST
rw
EC4
rw
EC3
rw
EC2
rw
DRST
rw
DPER
rw
DC4
rw
DC3
rw
DC2
rw
CRST
rw
CPER
rw
CC4
rw
CC3
rw
CC2
rw
BPER
rw
BC4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BC3
rw
BC2
rw
APER
rw
AC4
rw
AC3
rw
AC2
rw
EEV[10]
rw
EEV[9]
rw
EEV[8]
rw
EEV[7]
rw
EEV[6]
rw
MPER
rw
MC[4]
rw
MC[3]
rw
MC[2]
rw
MC[1]
rw
Toggle fields

MC[1]

Bit 0: ADC trigger 2 on Master Compare 1.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MC[2]

Bit 1: ADC trigger 2 on Master Compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MC[3]

Bit 2: ADC trigger 2 on Master Compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MC[4]

Bit 3: ADC trigger 2 on Master Compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on master compare event
1: Enabled: Generation of ADC trigger on master compare event

MPER

Bit 4: ADC trigger 2 on Master Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

EEV[6]

Bit 5: ADC trigger 2 on External Event 6.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[7]

Bit 6: ADC trigger 2 on External Event 7.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[8]

Bit 7: ADC trigger 2 on External Event 8.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[9]

Bit 8: ADC trigger 2 on External Event 9.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

EEV[10]

Bit 9: ADC trigger 2 on External Event 10.

Allowed values:
0: Disabled: No generation of ADC trigger on external event
1: Enabled: Generation of ADC trigger on external event

AC2

Bit 10: ADC trigger 2 on Timer A compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

AC3

Bit 11: ADC trigger 2 on Timer A compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

AC4

Bit 12: ADC trigger 2 on Timer A compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

APER

Bit 13: ADC trigger 2 on Timer A Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

BC2

Bit 14: ADC trigger 2 on Timer B compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

BC3

Bit 15: ADC trigger 2 on Timer B compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

BC4

Bit 16: ADC trigger 2 on Timer B compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

BPER

Bit 17: ADC trigger 2 on Timer B Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

CC2

Bit 18: ADC trigger 2 on Timer C compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

CC3

Bit 19: ADC trigger 2 on Timer C compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

CC4

Bit 20: ADC trigger 2 on Timer C compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

CPER

Bit 21: ADC trigger 2 on Timer C Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

CRST

Bit 22: ADC trigger 2 on Timer C Reset.

Allowed values:
0: Disabled: No generation of ADC trigger on timer reset and roll-over
1: Enabled: Generation of ADC trigger on timer reset and roll-over

DC2

Bit 23: ADC trigger 2 on Timer D compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

DC3

Bit 24: ADC trigger 2 on Timer D compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

DC4

Bit 25: ADC trigger 2 on Timer D compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

DPER

Bit 26: ADC trigger 2 on Timer D Period.

Allowed values:
0: Disabled: No generation of ADC trigger on timer period event
1: Enabled: Generation of ADC trigger on timer period event

DRST

Bit 27: ADC trigger 2 on Timer D Reset.

Allowed values:
0: Disabled: No generation of ADC trigger on timer reset and roll-over
1: Enabled: Generation of ADC trigger on timer reset and roll-over

EC2

Bit 28: ADC trigger 2 on Timer E compare 2.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

EC3

Bit 29: ADC trigger 2 on Timer E compare 3.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

EC4

Bit 30: ADC trigger 2 on Timer E compare 4.

Allowed values:
0: Disabled: No generation of ADC trigger on timer compare event
1: Enabled: Generation of ADC trigger on timer compare event

ERST

Bit 31: ADC trigger 2 on Timer E Reset.

Allowed values:
0: Disabled: No generation of ADC trigger on timer reset and roll-over
1: Enabled: Generation of ADC trigger on timer reset and roll-over

FLTINR1

HRTIM Fault Input Register 1

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLT4LCK
rw
FLT[4]F
rw
FLT[4]SRC
rw
FLT[4]P
rw
FLT[4]E
rw
FLT3LCK
rw
FLT[3]F
rw
FLT[3]SRC
rw
FLT[3]P
rw
FLT[3]E
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLT2LCK
rw
FLT[2]F
rw
FLT[2]SRC
rw
FLT[2]P
rw
FLT[2]E
rw
FLT1LCK
rw
FLT[1]F
rw
FLT[1]SRC
rw
FLT[1]P
rw
FLT[1]E
rw
Toggle fields

FLT[1]E

Bit 0: FLT1E.

Allowed values:
0: Disabled: Fault input disabled
1: Enabled: Fault input enabled

FLT[1]P

Bit 1: FLT1P.

Allowed values:
0: ActiveLow: Fault input is active low
1: ActiveHigh: Fault input is active high

FLT[1]SRC

Bit 2: Fault 1 source.

Allowed values:
0: Input: Fault input is FLTx input pin
1: Internal: Fault input is FLTn_Int signal

FLT[1]F

Bits 3-6: FLT1F.

Allowed values:
0: Disabled: No filter, FLTx acts asynchronously
1: Div1_N2: f_SAMPLING=f_HRTIM, N=2
2: Div1_N4: f_SAMPLING=f_HRTIM, N=4
3: Div1_N8: f_SAMPLING=f_HRTIM, N=8
4: Div2_N6: f_SAMPLING=f_HRTIM/2, N=6
5: Div2_N8: f_SAMPLING=f_HRTIM/2, N=8
6: Div4_N6: f_SAMPLING=f_HRTIM/4, N=6
7: Div4_N8: f_SAMPLING=f_HRTIM/4, N=8
8: Div8_N6: f_SAMPLING=f_HRTIM/8, N=6
9: Div8_N8: f_SAMPLING=f_HRTIM/8, N=8
10: Div16_N5: f_SAMPLING=f_HRTIM/16, N=5
11: Div16_N6: f_SAMPLING=f_HRTIM/16, N=6
12: Div16_N8: f_SAMPLING=f_HRTIM/16, N=8
13: Div32_N5: f_SAMPLING=f_HRTIM/32, N=5
14: Div32_N6: f_SAMPLING=f_HRTIM/32, N=6
15: Div32_N8: f_SAMPLING=f_HRTIM/32, N=8

FLT1LCK

Bit 7: FLT1LCK.

Allowed values:
0: Unlocked: Fault bits are read/write
1: Locked: Fault bits are read-only

FLT[2]E

Bit 8: FLT2E.

Allowed values:
0: Disabled: Fault input disabled
1: Enabled: Fault input enabled

FLT[2]P

Bit 9: FLT2P.

Allowed values:
0: ActiveLow: Fault input is active low
1: ActiveHigh: Fault input is active high

FLT[2]SRC

Bit 10: Fault 2 source.

Allowed values:
0: Input: Fault input is FLTx input pin
1: Internal: Fault input is FLTn_Int signal

FLT[2]F

Bits 11-14: FLT2F.

Allowed values:
0: Disabled: No filter, FLTx acts asynchronously
1: Div1_N2: f_SAMPLING=f_HRTIM, N=2
2: Div1_N4: f_SAMPLING=f_HRTIM, N=4
3: Div1_N8: f_SAMPLING=f_HRTIM, N=8
4: Div2_N6: f_SAMPLING=f_HRTIM/2, N=6
5: Div2_N8: f_SAMPLING=f_HRTIM/2, N=8
6: Div4_N6: f_SAMPLING=f_HRTIM/4, N=6
7: Div4_N8: f_SAMPLING=f_HRTIM/4, N=8
8: Div8_N6: f_SAMPLING=f_HRTIM/8, N=6
9: Div8_N8: f_SAMPLING=f_HRTIM/8, N=8
10: Div16_N5: f_SAMPLING=f_HRTIM/16, N=5
11: Div16_N6: f_SAMPLING=f_HRTIM/16, N=6
12: Div16_N8: f_SAMPLING=f_HRTIM/16, N=8
13: Div32_N5: f_SAMPLING=f_HRTIM/32, N=5
14: Div32_N6: f_SAMPLING=f_HRTIM/32, N=6
15: Div32_N8: f_SAMPLING=f_HRTIM/32, N=8

FLT2LCK

Bit 15: FLT2LCK.

Allowed values:
0: Unlocked: Fault bits are read/write
1: Locked: Fault bits are read-only

FLT[3]E

Bit 16: FLT3E.

Allowed values:
0: Disabled: Fault input disabled
1: Enabled: Fault input enabled

FLT[3]P

Bit 17: FLT3P.

Allowed values:
0: ActiveLow: Fault input is active low
1: ActiveHigh: Fault input is active high

FLT[3]SRC

Bit 18: Fault 3 source.

Allowed values:
0: Input: Fault input is FLTx input pin
1: Internal: Fault input is FLTn_Int signal

FLT[3]F

Bits 19-22: FLT3F.

Allowed values:
0: Disabled: No filter, FLTx acts asynchronously
1: Div1_N2: f_SAMPLING=f_HRTIM, N=2
2: Div1_N4: f_SAMPLING=f_HRTIM, N=4
3: Div1_N8: f_SAMPLING=f_HRTIM, N=8
4: Div2_N6: f_SAMPLING=f_HRTIM/2, N=6
5: Div2_N8: f_SAMPLING=f_HRTIM/2, N=8
6: Div4_N6: f_SAMPLING=f_HRTIM/4, N=6
7: Div4_N8: f_SAMPLING=f_HRTIM/4, N=8
8: Div8_N6: f_SAMPLING=f_HRTIM/8, N=6
9: Div8_N8: f_SAMPLING=f_HRTIM/8, N=8
10: Div16_N5: f_SAMPLING=f_HRTIM/16, N=5
11: Div16_N6: f_SAMPLING=f_HRTIM/16, N=6
12: Div16_N8: f_SAMPLING=f_HRTIM/16, N=8
13: Div32_N5: f_SAMPLING=f_HRTIM/32, N=5
14: Div32_N6: f_SAMPLING=f_HRTIM/32, N=6
15: Div32_N8: f_SAMPLING=f_HRTIM/32, N=8

FLT3LCK

Bit 23: FLT3LCK.

Allowed values:
0: Unlocked: Fault bits are read/write
1: Locked: Fault bits are read-only

FLT[4]E

Bit 24: FLT4E.

Allowed values:
0: Disabled: Fault input disabled
1: Enabled: Fault input enabled

FLT[4]P

Bit 25: FLT4P.

Allowed values:
0: ActiveLow: Fault input is active low
1: ActiveHigh: Fault input is active high

FLT[4]SRC

Bit 26: Fault 4 source.

Allowed values:
0: Input: Fault input is FLTx input pin
1: Internal: Fault input is FLTn_Int signal

FLT[4]F

Bits 27-30: FLT4F.

Allowed values:
0: Disabled: No filter, FLTx acts asynchronously
1: Div1_N2: f_SAMPLING=f_HRTIM, N=2
2: Div1_N4: f_SAMPLING=f_HRTIM, N=4
3: Div1_N8: f_SAMPLING=f_HRTIM, N=8
4: Div2_N6: f_SAMPLING=f_HRTIM/2, N=6
5: Div2_N8: f_SAMPLING=f_HRTIM/2, N=8
6: Div4_N6: f_SAMPLING=f_HRTIM/4, N=6
7: Div4_N8: f_SAMPLING=f_HRTIM/4, N=8
8: Div8_N6: f_SAMPLING=f_HRTIM/8, N=6
9: Div8_N8: f_SAMPLING=f_HRTIM/8, N=8
10: Div16_N5: f_SAMPLING=f_HRTIM/16, N=5
11: Div16_N6: f_SAMPLING=f_HRTIM/16, N=6
12: Div16_N8: f_SAMPLING=f_HRTIM/16, N=8
13: Div32_N5: f_SAMPLING=f_HRTIM/32, N=5
14: Div32_N6: f_SAMPLING=f_HRTIM/32, N=6
15: Div32_N8: f_SAMPLING=f_HRTIM/32, N=8

FLT4LCK

Bit 31: FLT4LCK.

Allowed values:
0: Unlocked: Fault bits are read/write
1: Locked: Fault bits are read-only

FLTINR2

HRTIM Fault Input Register 2

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLTSD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLT5LCK
rw
FLT[5]F
rw
FLT[5]SRC
rw
FLT[5]P
rw
FLT[5]E
rw
Toggle fields

FLT[5]E

Bit 0: FLT5E.

Allowed values:
0: Disabled: Fault input disabled
1: Enabled: Fault input enabled

FLT[5]P

Bit 1: FLT5P.

Allowed values:
0: ActiveLow: Fault input is active low
1: ActiveHigh: Fault input is active high

FLT[5]SRC

Bit 2: Fault 5 source.

Allowed values:
0: Input: Fault input is FLTx input pin
1: Internal: Fault input is FLTn_Int signal

FLT[5]F

Bits 3-6: FLT5F.

Allowed values:
0: Disabled: No filter, FLTx acts asynchronously
1: Div1_N2: f_SAMPLING=f_HRTIM, N=2
2: Div1_N4: f_SAMPLING=f_HRTIM, N=4
3: Div1_N8: f_SAMPLING=f_HRTIM, N=8
4: Div2_N6: f_SAMPLING=f_HRTIM/2, N=6
5: Div2_N8: f_SAMPLING=f_HRTIM/2, N=8
6: Div4_N6: f_SAMPLING=f_HRTIM/4, N=6
7: Div4_N8: f_SAMPLING=f_HRTIM/4, N=8
8: Div8_N6: f_SAMPLING=f_HRTIM/8, N=6
9: Div8_N8: f_SAMPLING=f_HRTIM/8, N=8
10: Div16_N5: f_SAMPLING=f_HRTIM/16, N=5
11: Div16_N6: f_SAMPLING=f_HRTIM/16, N=6
12: Div16_N8: f_SAMPLING=f_HRTIM/16, N=8
13: Div32_N5: f_SAMPLING=f_HRTIM/32, N=5
14: Div32_N6: f_SAMPLING=f_HRTIM/32, N=6
15: Div32_N8: f_SAMPLING=f_HRTIM/32, N=8

FLT5LCK

Bit 7: FLT5LCK.

Allowed values:
0: Unlocked: Fault bits are read/write
1: Locked: Fault bits are read-only

FLTSD

Bits 24-25: FLTSD.

Allowed values:
0: Div1: f_FLTS=f_HRTIM
1: Div2: f_FLTS=f_HRTIM/2
2: Div4: f_FLTS=f_HRTIM/4
3: Div8: f_FLTS=f_HRTIM/8

BDMUPR

BDMUPDR

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCMP4
rw
MCMP3
rw
MCMP2
rw
MCMP1
rw
MREP
rw
MPER
rw
MCNT
rw
MDIER
rw
MICR
rw
MCR
rw
Toggle fields

MCR

Bit 0: MCR.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

MICR

Bit 1: MICR.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

MDIER

Bit 2: MDIER.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

MCNT

Bit 3: MCNT.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

MPER

Bit 4: MPER.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

MREP

Bit 5: MREP.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

MCMP1

Bit 6: MCMP1.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

MCMP2

Bit 7: MCMP2.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

MCMP3

Bit 8: MCMP3.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

MCMP4

Bit 9: MCMP4.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

BDTAUPR

Burst DMA Timerx update Register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

21/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLTR
rw
OUTR
rw
CHPR
rw
RSTR
rw
EEFR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EEFR1
rw
RST2R
rw
SET2R
rw
RST1R
rw
SET1R
rw
DTR
rw
CMP4
rw
CMP3
rw
CMP2
rw
CMP1
rw
REP
rw
PER
rw
CNT
rw
DIER
rw
ICR
rw
CR
rw
Toggle fields

CR

Bit 0: HRTIM_TIMxCR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

ICR

Bit 1: HRTIM_TIMxICR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

DIER

Bit 2: HRTIM_TIMxDIER register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CNT

Bit 3: HRTIM_CNTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

PER

Bit 4: HRTIM_PERxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

REP

Bit 5: HRTIM_REPxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP1

Bit 6: HRTIM_CMP1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP2

Bit 7: HRTIM_CMP2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP3

Bit 8: HRTIM_CMP3xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP4

Bit 9: HRTIM_CMP4xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

DTR

Bit 10: HRTIM_DTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

SET1R

Bit 11: HRTIM_SET1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RST1R

Bit 12: HRTIM_RST1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

SET2R

Bit 13: HRTIM_SET2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RST2R

Bit 14: HRTIM_RST2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

EEFR1

Bit 15: HRTIM_EEFxR1 register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

EEFR2

Bit 16: HRTIM_EEFxR2 register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RSTR

Bit 17: HRTIM_RSTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CHPR

Bit 18: HRTIM_CHPxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

OUTR

Bit 19: HRTIM_OUTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

FLTR

Bit 20: HRTIM_FLTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

BDTBUPR

Burst DMA Timerx update Register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

21/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLTR
rw
OUTR
rw
CHPR
rw
RSTR
rw
EEFR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EEFR1
rw
RST2R
rw
SET2R
rw
RST1R
rw
SET1R
rw
DTR
rw
CMP4
rw
CMP3
rw
CMP2
rw
CMP1
rw
REP
rw
PER
rw
CNT
rw
DIER
rw
ICR
rw
CR
rw
Toggle fields

CR

Bit 0: HRTIM_TIMxCR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

ICR

Bit 1: HRTIM_TIMxICR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

DIER

Bit 2: HRTIM_TIMxDIER register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CNT

Bit 3: HRTIM_CNTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

PER

Bit 4: HRTIM_PERxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

REP

Bit 5: HRTIM_REPxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP1

Bit 6: HRTIM_CMP1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP2

Bit 7: HRTIM_CMP2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP3

Bit 8: HRTIM_CMP3xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP4

Bit 9: HRTIM_CMP4xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

DTR

Bit 10: HRTIM_DTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

SET1R

Bit 11: HRTIM_SET1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RST1R

Bit 12: HRTIM_RST1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

SET2R

Bit 13: HRTIM_SET2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RST2R

Bit 14: HRTIM_RST2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

EEFR1

Bit 15: HRTIM_EEFxR1 register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

EEFR2

Bit 16: HRTIM_EEFxR2 register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RSTR

Bit 17: HRTIM_RSTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CHPR

Bit 18: HRTIM_CHPxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

OUTR

Bit 19: HRTIM_OUTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

FLTR

Bit 20: HRTIM_FLTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

BDTCUPR

Burst DMA Timerx update Register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

21/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLTR
rw
OUTR
rw
CHPR
rw
RSTR
rw
EEFR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EEFR1
rw
RST2R
rw
SET2R
rw
RST1R
rw
SET1R
rw
DTR
rw
CMP4
rw
CMP3
rw
CMP2
rw
CMP1
rw
REP
rw
PER
rw
CNT
rw
DIER
rw
ICR
rw
CR
rw
Toggle fields

CR

Bit 0: HRTIM_TIMxCR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

ICR

Bit 1: HRTIM_TIMxICR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

DIER

Bit 2: HRTIM_TIMxDIER register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CNT

Bit 3: HRTIM_CNTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

PER

Bit 4: HRTIM_PERxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

REP

Bit 5: HRTIM_REPxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP1

Bit 6: HRTIM_CMP1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP2

Bit 7: HRTIM_CMP2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP3

Bit 8: HRTIM_CMP3xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP4

Bit 9: HRTIM_CMP4xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

DTR

Bit 10: HRTIM_DTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

SET1R

Bit 11: HRTIM_SET1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RST1R

Bit 12: HRTIM_RST1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

SET2R

Bit 13: HRTIM_SET2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RST2R

Bit 14: HRTIM_RST2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

EEFR1

Bit 15: HRTIM_EEFxR1 register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

EEFR2

Bit 16: HRTIM_EEFxR2 register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RSTR

Bit 17: HRTIM_RSTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CHPR

Bit 18: HRTIM_CHPxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

OUTR

Bit 19: HRTIM_OUTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

FLTR

Bit 20: HRTIM_FLTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

BDTDUPR

Burst DMA Timerx update Register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

21/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLTR
rw
OUTR
rw
CHPR
rw
RSTR
rw
EEFR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EEFR1
rw
RST2R
rw
SET2R
rw
RST1R
rw
SET1R
rw
DTR
rw
CMP4
rw
CMP3
rw
CMP2
rw
CMP1
rw
REP
rw
PER
rw
CNT
rw
DIER
rw
ICR
rw
CR
rw
Toggle fields

CR

Bit 0: HRTIM_TIMxCR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

ICR

Bit 1: HRTIM_TIMxICR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

DIER

Bit 2: HRTIM_TIMxDIER register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CNT

Bit 3: HRTIM_CNTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

PER

Bit 4: HRTIM_PERxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

REP

Bit 5: HRTIM_REPxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP1

Bit 6: HRTIM_CMP1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP2

Bit 7: HRTIM_CMP2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP3

Bit 8: HRTIM_CMP3xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP4

Bit 9: HRTIM_CMP4xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

DTR

Bit 10: HRTIM_DTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

SET1R

Bit 11: HRTIM_SET1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RST1R

Bit 12: HRTIM_RST1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

SET2R

Bit 13: HRTIM_SET2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RST2R

Bit 14: HRTIM_RST2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

EEFR1

Bit 15: HRTIM_EEFxR1 register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

EEFR2

Bit 16: HRTIM_EEFxR2 register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RSTR

Bit 17: HRTIM_RSTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CHPR

Bit 18: HRTIM_CHPxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

OUTR

Bit 19: HRTIM_OUTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

FLTR

Bit 20: HRTIM_FLTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

BDTEUPR

Burst DMA Timerx update Register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

21/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLTR
rw
OUTR
rw
CHPR
rw
RSTR
rw
EEFR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EEFR1
rw
RST2R
rw
SET2R
rw
RST1R
rw
SET1R
rw
DTR
rw
CMP4
rw
CMP3
rw
CMP2
rw
CMP1
rw
REP
rw
PER
rw
CNT
rw
DIER
rw
ICR
rw
CR
rw
Toggle fields

CR

Bit 0: HRTIM_TIMxCR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

ICR

Bit 1: HRTIM_TIMxICR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

DIER

Bit 2: HRTIM_TIMxDIER register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CNT

Bit 3: HRTIM_CNTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

PER

Bit 4: HRTIM_PERxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

REP

Bit 5: HRTIM_REPxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP1

Bit 6: HRTIM_CMP1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP2

Bit 7: HRTIM_CMP2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP3

Bit 8: HRTIM_CMP3xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CMP4

Bit 9: HRTIM_CMP4xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

DTR

Bit 10: HRTIM_DTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

SET1R

Bit 11: HRTIM_SET1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RST1R

Bit 12: HRTIM_RST1xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

SET2R

Bit 13: HRTIM_SET2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RST2R

Bit 14: HRTIM_RST2xR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

EEFR1

Bit 15: HRTIM_EEFxR1 register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

EEFR2

Bit 16: HRTIM_EEFxR2 register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

RSTR

Bit 17: HRTIM_RSTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

CHPR

Bit 18: HRTIM_CHPxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

OUTR

Bit 19: HRTIM_OUTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

FLTR

Bit 20: HRTIM_FLTxR register update enable.

Allowed values:
0: NotUpdated: Register not updated by burst DMA access
1: Updated: Register updated by burst DMA access

BDMADR

Burst DMA Data Register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BDMADR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BDMADR
rw
Toggle fields

BDMADR

Bits 0-31: Burst DMA Data register.

Allowed values: 0x0-0xffffffff

HRTIM_Master

0x40017400: High Resolution Timer: Master Timers

54/54 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 ISR
0x8 ICR
0xc DIER
0x10 CNTR
0x14 PERR
0x18 REPR
0x1c CMP1R
0x24 CMP2R
0x28 CMP3R
0x2c CMP4R
Toggle registers

CR

Master Timer Control Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRSTDMA
rw
MREPU
rw
PREEN
rw
DACSYNC
rw
T[E]CEN
rw
T[D]CEN
rw
T[C]CEN
rw
T[B]CEN
rw
T[A]CEN
rw
MCEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNCSRC
rw
SYNCOUT
rw
SYNCSTRT
rw
SYNCRST
rw
SYNCIN
rw
HALF
rw
RETRIG
rw
CONT
rw
CKPSC
rw
Toggle fields

CKPSC

Bits 0-2: HRTIM Master Clock prescaler.

Allowed values: 0x0-0x7

CONT

Bit 3: Master Continuous mode.

Allowed values:
0: SingleShot: The timer operates in single-shot mode and stops when it reaches the MPER value
1: Continuous: The timer operates in continuous (free-running) mode and rolls over to zero when it reaches the MPER value

RETRIG

Bit 4: Master Re-triggerable mode.

Allowed values:
0: Disabled: The timer is not re-triggerable: a counter reset can be done only if the counter is stopped
1: Enabled: The timer is retriggerable: a counter reset is done whatever the counter state

HALF

Bit 5: Half mode enable.

Allowed values:
0: Disabled: Half mode disabled
1: Enabled: Half mode enabled

SYNCIN

Bits 8-9: ynchronization input.

Allowed values:
0: Disabled: Disabled. HRTIM is not synchronized and runs in standalone mode
2: Internal: Internal event: the HRTIM is synchronized with the on-chip timer
3: External: External event: a positive pulse on HRTIM_SCIN input triggers the HRTIM

SYNCRST

Bit 10: Synchronization Resets Master.

Allowed values:
0: Disabled: No effect on the master timer
1: Reset: A synchroniation input event resets the master timer

SYNCSTRT

Bit 11: Synchronization Starts Master.

Allowed values:
0: Disabled: No effect on the master timer
1: Start: A synchroniation input event starts the master timer

SYNCOUT

Bits 12-13: Synchronization output.

Allowed values:
0: Disabled: Disabled
2: PositivePulse: Positive pulse on SCOUT output (16x f_HRTIM clock cycles)
3: NegativePulse: Negative pulse on SCOUT output (16x f_HRTIM clock cycles)

SYNCSRC

Bits 14-15: Synchronization source.

Allowed values:
0: MasterStart: Master timer Start
1: MasterCompare1: Master timer Compare 1 event
2: TimerAStart: Timer A start/reset
3: TimerACompare1: Timer A Compare 1 event

MCEN

Bit 16: Master Counter enable.

Allowed values:
0: Disabled: Master timer counter disabled
1: Enabled: Master timer counter enabled

T[A]CEN

Bit 17: Timer A counter enable.

Allowed values:
0: Disabled: Timer counter disabled
1: Enabled: Timer counter enabled

T[B]CEN

Bit 18: Timer B counter enable.

Allowed values:
0: Disabled: Timer counter disabled
1: Enabled: Timer counter enabled

T[C]CEN

Bit 19: Timer C counter enable.

Allowed values:
0: Disabled: Timer counter disabled
1: Enabled: Timer counter enabled

T[D]CEN

Bit 20: Timer D counter enable.

Allowed values:
0: Disabled: Timer counter disabled
1: Enabled: Timer counter enabled

T[E]CEN

Bit 21: Timer E counter enable.

Allowed values:
0: Disabled: Timer counter disabled
1: Enabled: Timer counter enabled

DACSYNC

Bits 25-26: AC Synchronization.

Allowed values:
0: Disabled: No DAC trigger generated
1: DACSync1: Trigger generated on DACSync1
2: DACSync2: Trigger generated on DACSync2
3: DACSync3: Trigger generated on DACSync3

PREEN

Bit 27: Preload enable.

Allowed values:
0: Disabled: Preload disabled: the write access is directly done into the active register
1: Enabled: Preload enabled: the write access is done into the preload register

MREPU

Bit 29: Master Timer Repetition update.

Allowed values:
0: Disabled: Update on repetition disabled
1: Enabled: Update on repetition enabled

BRSTDMA

Bits 30-31: Burst DMA Update.

Allowed values:
0: Independent: Update done independently from the DMA burst transfer completion
1: Completion: Update done when the DMA burst transfer is completed
2: Rollover: Update done on master timer roll-over following a DMA burst transfer completion

ISR

Master Timer Interrupt Status Register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPD
r
SYNC
r
REP
r
CMP[4]
r
CMP[3]
r
CMP[2]
r
CMP[1]
r
Toggle fields

CMP[1]

Bit 0: Master Compare 1 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

CMP[2]

Bit 1: Master Compare 2 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

CMP[3]

Bit 2: Master Compare 3 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

CMP[4]

Bit 3: Master Compare 4 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

REP

Bit 4: Master Repetition Interrupt Flag.

Allowed values:
0: NoEvent: No timer repetition interrupt occurred
1: Event: Timer repetition interrupt occurred

SYNC

Bit 5: Sync Input Interrupt Flag.

Allowed values:
0: NoEvent: No sync input interrupt occurred
1: Event: Sync input interrupt occurred

UPD

Bit 6: Master Update Interrupt Flag.

Allowed values:
0: NoEvent: No timer update interrupt occurred
1: Event: Timer update interrupt occurred

ICR

Master Timer Interrupt Clear Register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPDC
w1c
SYNCC
w1c
REPC
w1c
CMP[4]C
w1c
CMP[3]C
w1c
CMP[2]C
w1c
CMP[1]C
w1c
Toggle fields

CMP[1]C

Bit 0: Master Compare 1 Interrupt flag clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CMP[2]C

Bit 1: Master Compare 2 Interrupt flag clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CMP[3]C

Bit 2: Master Compare 3 Interrupt flag clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CMP[4]C

Bit 3: Master Compare 4 Interrupt flag clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

REPC

Bit 4: Repetition Interrupt flag clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

SYNCC

Bit 5: Sync Input Interrupt flag clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

UPDC

Bit 6: Master update Interrupt flag clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

DIER

MDIER4

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPDDE
rw
SYNCDE
rw
REPDE
rw
CMP[4]DE
rw
CMP[3]DE
rw
CMP[2]DE
rw
CMP[1]DE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPDIE
rw
SYNCIE
rw
REPIE
rw
CMP[4]IE
rw
CMP[3]IE
rw
CMP[2]IE
rw
CMP[1]IE
rw
Toggle fields

CMP[1]IE

Bit 0: MCMP1IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CMP[2]IE

Bit 1: MCMP2IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CMP[3]IE

Bit 2: MCMP3IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CMP[4]IE

Bit 3: MCMP4IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

REPIE

Bit 4: MREPIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

SYNCIE

Bit 5: SYNCIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

UPDIE

Bit 6: MUPDIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CMP[1]DE

Bit 16: MCMP1DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

CMP[2]DE

Bit 17: MCMP2DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

CMP[3]DE

Bit 18: MCMP3DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

CMP[4]DE

Bit 19: MCMP4DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

REPDE

Bit 20: MREPDE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

SYNCDE

Bit 21: SYNCDE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

UPDDE

Bit 22: MUPDDE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

CNTR

Master Timer Counter Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: Counter value.

Allowed values: 0x0-0xffff

PERR

Master Timer Period Register

Offset: 0x14, size: 32, reset: 0x0000FFFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PER
rw
Toggle fields

PER

Bits 0-15: Master Timer Period value.

Allowed values: 0x0-0xffff

REPR

Master Timer Repetition Register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Master Timer Repetition counter value.

Allowed values: 0x0-0xff

CMP1R

Master Timer Compare 1 Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CMP2R

Master Timer Compare 2 Register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CMP3R

Master Timer Compare 3 Register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CMP4R

Master Timer Compare 4 Register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

HRTIM_TIMA

0x40017480: High Resolution Timer: TIMA

357/357 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 ISR
0x8 ICR
0xc DIER
0x10 CNTR
0x14 PERR
0x18 REPR
0x1c CMP1R
0x20 CMP1CR
0x24 CMP2R
0x28 CMP3R
0x2c CMP4R
0x30 CPT1R
0x34 CPT2R
0x38 DTR
0x3c SET1R
0x40 RST1R
0x44 SET2R
0x48 RST2R
0x4c EEFR1
0x50 EEFR2
0x54 RSTR
0x58 CHPR
0x5c CPT1CR
0x60 CPT2CR
0x64 OUTR
0x68 FLTR
Toggle registers

CR

Timerx Control Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPDGAT
rw
PREEN
rw
DACSYNC
rw
MSTU
rw
TEU
rw
TDU
rw
TCU
rw
TBU
rw
TRSTU
rw
TREPU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DELCMP4
rw
DELCMP2
rw
SYNCSTRT
rw
SYNCRST
rw
PSHPLL
rw
HALF
rw
RETRIG
rw
CONT
rw
CKPSC
rw
Toggle fields

CKPSC

Bits 0-2: HRTIM Timer x Clock prescaler.

Allowed values: 0x0-0x7

CONT

Bit 3: Continuous mode.

Allowed values:
0: SingleShot: The timer operates in single-shot mode and stops when it reaches the MPER value
1: Continuous: The timer operates in continuous (free-running) mode and rolls over to zero when it reaches the MPER value

RETRIG

Bit 4: Re-triggerable mode.

Allowed values:
0: Disabled: The timer is not re-triggerable: a counter reset can be done only if the counter is stopped
1: Enabled: The timer is retriggerable: a counter reset is done whatever the counter state

HALF

Bit 5: Half mode enable.

Allowed values:
0: Disabled: Half mode disabled
1: Enabled: Half mode enabled

PSHPLL

Bit 6: Push-Pull mode enable.

Allowed values:
0: Disabled: Push-pull mode disabled
1: Enabled: Push-pull mode enabled

SYNCRST

Bit 10: Synchronization Resets Timer x.

Allowed values:
0: Disabled: No effect on the master timer
1: Reset: A synchroniation input event resets the master timer

SYNCSTRT

Bit 11: Synchronization Starts Timer x.

Allowed values:
0: Disabled: No effect on the master timer
1: Start: A synchroniation input event starts the master timer

DELCMP2

Bits 12-13: Delayed CMP2 mode.

Allowed values:
0: Standard: CMP2 register is always active (standard compare mode)
1: Capture1: CMP2 is recomputed and is active following a capture 1 event
2: Capture1_Compare1: CMP2 is recomputed and is active following a capture 1 event or a Compare 1 match
3: Capture1_Compare3: CMP2 is recomputed and is active following a capture 1 event or a Compare 3 match

DELCMP4

Bits 14-15: Delayed CMP4 mode.

Allowed values:
0: Standard: CMP4 register is always active (standard compare mode)
1: Capture2: CMP4 is recomputed and is active following a capture 2 event
2: Capture2_Compare1: CMP4 is recomputed and is active following a capture 2 event or a Compare 1 match
3: Capture_Compare3: CMP4 is recomputed and is active following a capture event or a Compare 3 match

TREPU

Bit 17: Timer x Repetition update.

Allowed values:
0: Disabled: Update by timer x repetition disabled
1: Enabled: Update by timer x repetition enabled

TRSTU

Bit 18: Timerx reset update.

Allowed values:
0: Disabled: Update by timer x reset/roll-over disabled
1: Enabled: Update by timer x reset/roll-over enabled

TBU

Bit 20: TBU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

TCU

Bit 21: TCU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

TDU

Bit 22: TDU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

TEU

Bit 23: TEU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

MSTU

Bit 24: Master Timer update.

Allowed values:
0: Disabled: Update by master timer disabled
1: Enabled: Update by master timer enabled

DACSYNC

Bits 25-26: AC Synchronization.

Allowed values:
0: Disabled: No DAC trigger generated
1: DACSync1: Trigger generated on DACSync1
2: DACSync2: Trigger generated on DACSync2
3: DACSync3: Trigger generated on DACSync3

PREEN

Bit 27: Preload enable.

Allowed values:
0: Disabled: Preload disabled: the write access is directly done into the active register
1: Enabled: Preload enabled: the write access is done into the preload register

UPDGAT

Bits 28-31: Update Gating.

Allowed values:
0: Independent: Update occurs independently from the DMA burst transfer
1: DMABurst: Update occurs when the DMA burst transfer is completed
2: DMABurst_Update: Update occurs on the update event following DMA burst transfer completion
3: Input1: Update occurs on a rising edge of HRTIM update enable input 1
4: Input2: Update occurs on a rising edge of HRTIM update enable input 2
5: Input3: Update occurs on a rising edge of HRTIM update enable input 3
6: Input1_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 1
7: Input2_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 2
8: Input3_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 3

ISR

Timerx Interrupt Status Register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
O2STAT
r
O1STAT
r
IPPSTAT
r
CPPSTAT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYPRT
r
RST
r
RST2
r
SET[2]
r
RST1
r
SET[1]
r
CPT[2]
r
CPT[1]
r
UPD
r
REP
r
CMP[4]
r
CMP[3]
r
CMP[2]
r
CMP[1]
r
Toggle fields

CMP[1]

Bit 0: Compare 1 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

CMP[2]

Bit 1: Compare 2 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

CMP[3]

Bit 2: Compare 3 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

CMP[4]

Bit 3: Compare 4 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

REP

Bit 4: Repetition Interrupt Flag.

Allowed values:
0: NoEvent: No timer repetition interrupt occurred
1: Event: Timer repetition interrupt occurred

UPD

Bit 6: Update Interrupt Flag.

Allowed values:
0: NoEvent: No timer update interrupt occurred
1: Event: Timer update interrupt occurred

CPT[1]

Bit 7: Capture1 Interrupt Flag.

Allowed values:
0: NoEvent: No timer x capture reset interrupt occurred
1: Event: Timer x capture reset interrupt occurred

CPT[2]

Bit 8: Capture2 Interrupt Flag.

Allowed values:
0: NoEvent: No timer x capture reset interrupt occurred
1: Event: Timer x capture reset interrupt occurred

SET[1]

Bit 9: Output 1 Set Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output set interrupt occurred
1: Event: Tx output set interrupt occurred

RST1

Bit 10: Output 1 Reset Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output reset interrupt occurred
1: Event: Tx output reset interrupt occurred

SET[2]

Bit 11: Output 2 Set Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output set interrupt occurred
1: Event: Tx output set interrupt occurred

RST2

Bit 12: Output 2 Reset Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output reset interrupt occurred
1: Event: Tx output reset interrupt occurred

RST

Bit 13: Reset Interrupt Flag.

Allowed values:
0: NoEvent: No TIMx counter reset/roll-over interrupt occurred
1: Event: TIMx counter reset/roll-over interrupt occurred

DLYPRT

Bit 14: Delayed Protection Flag.

Allowed values:
0: Inactive: Not in delayed idle or balanced idle mode
1: Active: Delayed idle or balanced idle mode entry

CPPSTAT

Bit 16: Current Push Pull Status.

Allowed values:
0: Output1Active: Signal applied on output 1 and output 2 forced inactive
1: Output2Active: Signal applied on output 2 and output 1 forced inactive

IPPSTAT

Bit 17: Idle Push Pull Status.

Allowed values:
0: Output1Active: Protection occurred when the output 1 was active and output 2 forced inactive
1: Output2Active: Protection occurred when the output 2 was active and output 1 forced inactive

O1STAT

Bit 18: Output 1 State.

Allowed values:
0: Inactive: Output was inactive
1: Active: Output was active

O2STAT

Bit 19: Output 2 State.

Allowed values:
0: Inactive: Output was inactive
1: Active: Output was active

ICR

Timerx Interrupt Clear Register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

14/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYPRTC
w1c
RSTC
w1c
RST2C
w1c
SET[2]C
w1c
RST1C
w1c
SET[1]C
w1c
CPT[2]C
w1c
CPT[1]C
w1c
UPDC
w1c
REPC
w1c
CMP[4]C
w1c
CMP[3]C
w1c
CMP[2]C
w1c
CMP[1]C
w1c
Toggle fields

CMP[1]C

Bit 0: Compare 1 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CMP[2]C

Bit 1: Compare 2 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CMP[3]C

Bit 2: Compare 3 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CMP[4]C

Bit 3: Compare 4 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

REPC

Bit 4: Repetition Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

UPDC

Bit 6: Update Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CPT[1]C

Bit 7: Capture1 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CPT[2]C

Bit 8: Capture2 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

SET[1]C

Bit 9: Output 1 Set flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

RST1C

Bit 10: Output 1 Reset flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

SET[2]C

Bit 11: Output 2 Set flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

RST2C

Bit 12: Output 2 Reset flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

RSTC

Bit 13: Reset Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

DLYPRTC

Bit 14: Delayed Protection Flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

DIER

TIMxDIER5

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

28/28 fields covered.

Toggle fields

CMP[1]IE

Bit 0: CMP1IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CMP[2]IE

Bit 1: CMP2IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CMP[3]IE

Bit 2: CMP3IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CMP[4]IE

Bit 3: CMP4IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

REPIE

Bit 4: REPIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

UPDIE

Bit 6: UPDIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CPT[1]IE

Bit 7: CPT1IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CPT[2]IE

Bit 8: CPT2IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

SET[1]IE

Bit 9: Output 1 set interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

RST1IE

Bit 10: RSTx1IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

SET[2]IE

Bit 11: Output 2 set interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

RST2IE

Bit 12: RSTx2IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

RSTIE

Bit 13: RSTIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

DLYPRTIE

Bit 14: DLYPRTIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CMP[1]DE

Bit 16: CMP1DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

CMP[2]DE

Bit 17: CMP2DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

CMP[3]DE

Bit 18: CMP3DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

CMP[4]DE

Bit 19: CMP4DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

REPDE

Bit 20: REPDE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

UPDDE

Bit 22: UPDDE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

CPT[1]DE

Bit 23: CPT1DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

CPT[2]DE

Bit 24: CPT2DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

SET[1]DE

Bit 25: Output 1 set DMA request enable.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

RST1DE

Bit 26: RSTx1DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

SET[2]DE

Bit 27: Output 2 set DMA request enable.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

RST2DE

Bit 28: RSTx2DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

RSTDE

Bit 29: RSTDE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

DLYPRTDE

Bit 30: DLYPRTDE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

CNTR

Timerx Counter Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: Counter value.

Allowed values: 0x0-0xffff

PERR

Timerx Period Register

Offset: 0x14, size: 32, reset: 0x0000FFFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PER
rw
Toggle fields

PER

Bits 0-15: Master Timer Period value.

Allowed values: 0x0-0xffff

REPR

Timerx Repetition Register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Master Timer Repetition counter value.

Allowed values: 0x0-0xff

CMP1R

Timerx Compare 1 Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CMP1CR

Timerx Compare 1 Compound Register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP1
rw
Toggle fields

CMP1

Bits 0-15: Timerx Compare 1 value.

Allowed values: 0x0-0xffff

REP

Bits 16-23: Timerx Repetition value (aliased from HRTIM_REPx register).

Allowed values: 0x0-0xff

CMP2R

Timerx Compare 2 Register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CMP3R

Timerx Compare 3 Register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CMP4R

Timerx Compare 4 Register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CPT1R

Timerx Capture 1 Register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPT
r
Toggle fields

CPT

Bits 0-15: Timerx Capture 1 value.

Allowed values: 0x0-0xffff

CPT2R

Timerx Capture 2 Register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPT
r
Toggle fields

CPT

Bits 0-15: Timerx Capture 1 value.

Allowed values: 0x0-0xffff

DTR

Timerx Deadtime Register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTFLK
rw
DTFSLK
rw
SDTF
rw
DTF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTRLK
rw
DTRSLK
rw
DTPRSC
rw
SDTR
rw
DTR
rw
Toggle fields

DTR

Bits 0-8: Deadtime Rising value.

Allowed values: 0x0-0x1ff

SDTR

Bit 9: Sign Deadtime Rising value.

Allowed values:
0: Positive: Positive deadtime on rising edge
1: Negative: Negative deadtime on rising edge

DTPRSC

Bits 10-12: Deadtime Prescaler.

Allowed values: 0x0-0x7

DTRSLK

Bit 14: Deadtime Rising Sign Lock.

Allowed values:
0: Unlocked: Deadtime rising sign is writable
1: Locked: Deadtime rising sign is read-only

DTRLK

Bit 15: Deadtime Rising Lock.

Allowed values:
0: Unlocked: Deadtime rising value and sign is writable
1: Locked: Deadtime rising value and sign is read-only

DTF

Bits 16-24: Deadtime Falling value.

Allowed values: 0x0-0x1ff

SDTF

Bit 25: Sign Deadtime Falling value.

Allowed values:
0: Positive: Positive deadtime on falling edge
1: Negative: Negative deadtime on falling edge

DTFSLK

Bit 30: Deadtime Falling Sign Lock.

Allowed values:
0: Unlocked: Deadtime falling sign is writable
1: Locked: Deadtime falling sign is read-only

DTFLK

Bit 31: Deadtime Falling Lock.

Allowed values:
0: Unlocked: Deadtime falling value and sign is writable
1: Locked: Deadtime falling value and sign is read-only

SET1R

Timerx Output1 Set Register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

Toggle fields

SST

Bit 0: Software Set trigger.

Allowed values:
0: NoEffect: No effect
1: SetActive: Force output to its active state

RESYNC

Bit 1: Timer A resynchronizaton.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetActive: Timer reset event coming solely from software or SYNC input event forces the output to its active state

PER

Bit 2: Timer A Period.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetActive: Timer period event forces the output to its active state

CMP[1]

Bit 3: Timer A compare 1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[2]

Bit 4: Timer A compare 2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[3]

Bit 5: Timer A compare 3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[4]

Bit 6: Timer A compare 4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

MSTPER

Bit 7: Master Period.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetActive: Master timer counter roll-over/reset forces the output to its active state

MSTCMP[1]

Bit 8: Master Compare 1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[2]

Bit 9: Master Compare 2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[3]

Bit 10: Master Compare 3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[4]

Bit 11: Master Compare 4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

TIMBCMP1

Bit 12: Timer B Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMBCMP2

Bit 13: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMBCMP4

Bit 14: Timer B Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMCCMP2

Bit 15: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMCCMP3

Bit 16: Timer C Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMDCMP1

Bit 17: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMDCMP2

Bit 18: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMECMP3

Bit 19: Timer E Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMECMP4

Bit 20: Timer E Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

EXTEVNT[1]

Bit 21: External Event 1.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[2]

Bit 22: External Event 2.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[3]

Bit 23: External Event 3.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[4]

Bit 24: External Event 4.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[5]

Bit 25: External Event 5.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[6]

Bit 26: External Event 6.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[7]

Bit 27: External Event 7.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[8]

Bit 28: External Event 8.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[9]

Bit 29: External Event 9.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[10]

Bit 30: External Event 10.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

UPDATE

Bit 31: Registers update (transfer preload to active).

Allowed values:
0: NoEffect: Register update event has no effect
1: SetActive: Register update event forces the output to its active state

RST1R

Timerx Output1 Reset Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

Toggle fields

SRT

Bit 0: SRT.

Allowed values:
0: NoEffect: No effect
1: SetInactive: Force output to its inactive state

RESYNC

Bit 1: RESYNC.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetInactive: Timer reset event coming solely from software or SYNC input event forces the output to its inactive state

PER

Bit 2: PER.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetInactive: Timer period event forces the output to its inactive state

CMP[1]

Bit 3: CMP1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[2]

Bit 4: CMP2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[3]

Bit 5: CMP3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[4]

Bit 6: CMP4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

MSTPER

Bit 7: MSTPER.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetInactive: Master timer counter roll-over/reset forces the output to its inactive state

MSTCMP[1]

Bit 8: MSTCMP1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[2]

Bit 9: MSTCMP2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[3]

Bit 10: MSTCMP3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[4]

Bit 11: MSTCMP4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

TIMBCMP1

Bit 12: Timer B Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMBCMP2

Bit 13: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMBCMP4

Bit 14: Timer B Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMCCMP2

Bit 15: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMCCMP3

Bit 16: Timer C Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMDCMP1

Bit 17: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMDCMP2

Bit 18: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMECMP3

Bit 19: Timer E Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMECMP4

Bit 20: Timer E Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

EXTEVNT[1]

Bit 21: EXTEVNT1.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[2]

Bit 22: EXTEVNT2.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[3]

Bit 23: EXTEVNT3.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[4]

Bit 24: EXTEVNT4.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[5]

Bit 25: EXTEVNT5.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[6]

Bit 26: EXTEVNT6.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[7]

Bit 27: EXTEVNT7.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[8]

Bit 28: EXTEVNT8.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[9]

Bit 29: EXTEVNT9.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[10]

Bit 30: EXTEVNT10.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

UPDATE

Bit 31: UPDATE.

Allowed values:
0: NoEffect: Register update event has no effect
1: SetInactive: Register update event forces the output to its inactive state

SET2R

Timerx Output2 Set Register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

Toggle fields

SST

Bit 0: Software Set trigger.

Allowed values:
0: NoEffect: No effect
1: SetActive: Force output to its active state

RESYNC

Bit 1: Timer A resynchronizaton.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetActive: Timer reset event coming solely from software or SYNC input event forces the output to its active state

PER

Bit 2: Timer A Period.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetActive: Timer period event forces the output to its active state

CMP[1]

Bit 3: Timer A compare 1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[2]

Bit 4: Timer A compare 2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[3]

Bit 5: Timer A compare 3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[4]

Bit 6: Timer A compare 4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

MSTPER

Bit 7: Master Period.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetActive: Master timer counter roll-over/reset forces the output to its active state

MSTCMP[1]

Bit 8: Master Compare 1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[2]

Bit 9: Master Compare 2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[3]

Bit 10: Master Compare 3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[4]

Bit 11: Master Compare 4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

TIMBCMP1

Bit 12: Timer B Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMBCMP2

Bit 13: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMBCMP4

Bit 14: Timer B Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMCCMP2

Bit 15: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMCCMP3

Bit 16: Timer C Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMDCMP1

Bit 17: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMDCMP2

Bit 18: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMECMP3

Bit 19: Timer E Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMECMP4

Bit 20: Timer E Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

EXTEVNT[1]

Bit 21: External Event 1.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[2]

Bit 22: External Event 2.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[3]

Bit 23: External Event 3.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[4]

Bit 24: External Event 4.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[5]

Bit 25: External Event 5.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[6]

Bit 26: External Event 6.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[7]

Bit 27: External Event 7.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[8]

Bit 28: External Event 8.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[9]

Bit 29: External Event 9.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[10]

Bit 30: External Event 10.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

UPDATE

Bit 31: Registers update (transfer preload to active).

Allowed values:
0: NoEffect: Register update event has no effect
1: SetActive: Register update event forces the output to its active state

RST2R

Timerx Output2 Reset Register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

Toggle fields

SRT

Bit 0: SRT.

Allowed values:
0: NoEffect: No effect
1: SetInactive: Force output to its inactive state

RESYNC

Bit 1: RESYNC.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetInactive: Timer reset event coming solely from software or SYNC input event forces the output to its inactive state

PER

Bit 2: PER.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetInactive: Timer period event forces the output to its inactive state

CMP[1]

Bit 3: CMP1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[2]

Bit 4: CMP2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[3]

Bit 5: CMP3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[4]

Bit 6: CMP4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

MSTPER

Bit 7: MSTPER.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetInactive: Master timer counter roll-over/reset forces the output to its inactive state

MSTCMP[1]

Bit 8: MSTCMP1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[2]

Bit 9: MSTCMP2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[3]

Bit 10: MSTCMP3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[4]

Bit 11: MSTCMP4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

TIMBCMP1

Bit 12: Timer B Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMBCMP2

Bit 13: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMBCMP4

Bit 14: Timer B Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMCCMP2

Bit 15: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMCCMP3

Bit 16: Timer C Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMDCMP1

Bit 17: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMDCMP2

Bit 18: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMECMP3

Bit 19: Timer E Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMECMP4

Bit 20: Timer E Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

EXTEVNT[1]

Bit 21: EXTEVNT1.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[2]

Bit 22: EXTEVNT2.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[3]

Bit 23: EXTEVNT3.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[4]

Bit 24: EXTEVNT4.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[5]

Bit 25: EXTEVNT5.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[6]

Bit 26: EXTEVNT6.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[7]

Bit 27: EXTEVNT7.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[8]

Bit 28: EXTEVNT8.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[9]

Bit 29: EXTEVNT9.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[10]

Bit 30: EXTEVNT10.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

UPDATE

Bit 31: UPDATE.

Allowed values:
0: NoEffect: Register update event has no effect
1: SetInactive: Register update event forces the output to its inactive state

EEFR1

Timerx External Event Filtering Register 1

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EE[5]FLTR
rw
EE[5]LTCH
rw
EE[4]FLTR
rw
EE[4]LTCH
rw
EE[3]FLTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EE[3]FLTR
rw
EE[3]LTCH
rw
EE[2]FLTR
rw
EE[2]LTCH
rw
EE[1]FLTR
rw
EE[1]LTCH
rw
Toggle fields

EE[1]LTCH

Bit 0: External Event 1 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[1]FLTR

Bits 1-4: External Event 1 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[2]LTCH

Bit 6: External Event 2 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[2]FLTR

Bits 7-10: External Event 2 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[3]LTCH

Bit 12: External Event 3 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[3]FLTR

Bits 13-16: External Event 3 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[4]LTCH

Bit 18: External Event 4 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[4]FLTR

Bits 19-22: External Event 4 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[5]LTCH

Bit 24: External Event 5 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[5]FLTR

Bits 25-28: External Event 5 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EEFR2

Timerx External Event Filtering Register 2

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EE[10]FLTR
rw
EE[10]LTCH
rw
EE[9]FLTR
rw
EE[9]LTCH
rw
EE[8]FLTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EE[8]FLTR
rw
EE[8]LTCH
rw
EE[7]FLTR
rw
EE[7]LTCH
rw
EE[6]FLTR
rw
EE[6]LTCH
rw
Toggle fields

EE[6]LTCH

Bit 0: External Event 6 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[6]FLTR

Bits 1-4: External Event 6 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[7]LTCH

Bit 6: External Event 7 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[7]FLTR

Bits 7-10: External Event 7 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[8]LTCH

Bit 12: External Event 8 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[8]FLTR

Bits 13-16: External Event 8 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[9]LTCH

Bit 18: External Event 9 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[9]FLTR

Bits 19-22: External Event 9 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[10]LTCH

Bit 24: External Event 10 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[10]FLTR

Bits 25-28: External Event 10 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

RSTR

TimerA Reset Register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

30/30 fields covered.

Toggle fields

UPDT

Bit 1: Timer A Update reset.

Allowed values:
0: NoEffect: Update event has no effect
1: ResetCounter: Timer X counter is reset upon update event

CMP2

Bit 2: Timer A compare 2 reset.

Allowed values:
0: NoEffect: Timer X compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer X compare Z event

CMP4

Bit 3: Timer A compare 4 reset.

Allowed values:
0: NoEffect: Timer X compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer X compare Z event

MSTPER

Bit 4: Master timer Period.

Allowed values:
0: NoEffect: Master timer period event has no effect
1: ResetCounter: Timer X counter is reset upon master timer period event

MSTCMP1

Bit 5: Master compare 1.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

MSTCMP2

Bit 6: Master compare 2.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

MSTCMP3

Bit 7: Master compare 3.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

MSTCMP4

Bit 8: Master compare 4.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

EXTEVNT1

Bit 9: External Event 1.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT2

Bit 10: External Event 2.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT3

Bit 11: External Event 3.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT4

Bit 12: External Event 4.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT5

Bit 13: External Event 5.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT6

Bit 14: External Event 6.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT7

Bit 15: External Event 7.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT8

Bit 16: External Event 8.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT9

Bit 17: External Event 9.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT10

Bit 18: External Event 10.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

TIMBCMP1

Bit 19: Timer B Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMBCMP2

Bit 20: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMBCMP4

Bit 21: Timer B Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMCCMP1

Bit 22: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMCCMP2

Bit 23: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMCCMP4

Bit 24: Timer C Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMDCMP1

Bit 25: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMDCMP2

Bit 26: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMDCMP4

Bit 27: Timer D Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMECMP1

Bit 28: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMECMP2

Bit 29: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMECMP4

Bit 30: Timer E Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

CHPR

Timerx Chopper Register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STRTPW
rw
CARDTY
rw
CARFRQ
rw
Toggle fields

CARFRQ

Bits 0-3: Timerx carrier frequency value.

Allowed values: 0x0-0xf

CARDTY

Bits 4-6: Timerx chopper duty cycle value.

Allowed values: 0x0-0x7

STRTPW

Bits 7-10: STRTPW.

Allowed values: 0x0-0xf

CPT1CR

Timerx Capture 2 Control Register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

28/28 fields covered.

Toggle fields

SWCPT

Bit 0: Software Capture.

Allowed values:
0: NoEffect: No effect
1: TriggerCapture: Force capture Z

UPDCPT

Bit 1: Update Capture.

Allowed values:
0: NoEffect: Update event has no effect
1: TriggerCapture: Update event triggers capture Z

EXEV[1]CPT

Bit 2: External Event 1 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[2]CPT

Bit 3: External Event 2 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[3]CPT

Bit 4: External Event 3 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[4]CPT

Bit 5: External Event 4 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[5]CPT

Bit 6: External Event 5 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[6]CPT

Bit 7: External Event 6 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[7]CPT

Bit 8: External Event 7 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[8]CPT

Bit 9: External Event 8 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[9]CPT

Bit 10: External Event 9 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[10]CPT

Bit 11: External Event 10 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

TB1SET

Bit 16: Timer B output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TB1RST

Bit 17: Timer B output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TBCMP1

Bit 18: Timer B Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TBCMP2

Bit 19: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TC1SET

Bit 20: Timer C output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TC1RST

Bit 21: Timer C output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TCCMP1

Bit 22: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TCCMP2

Bit 23: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TD1SET

Bit 24: Timer D output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TD1RST

Bit 25: Timer D output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TDCMP1

Bit 26: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TDCMP2

Bit 27: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TE1SET

Bit 28: Timer E output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TE1RST

Bit 29: Timer E output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TECMP1

Bit 30: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TECMP2

Bit 31: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

CPT2CR

CPT2xCR

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

28/28 fields covered.

Toggle fields

SWCPT

Bit 0: Software Capture.

Allowed values:
0: NoEffect: No effect
1: TriggerCapture: Force capture Z

UPDCPT

Bit 1: Update Capture.

Allowed values:
0: NoEffect: Update event has no effect
1: TriggerCapture: Update event triggers capture Z

EXEV[1]CPT

Bit 2: External Event 1 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[2]CPT

Bit 3: External Event 2 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[3]CPT

Bit 4: External Event 3 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[4]CPT

Bit 5: External Event 4 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[5]CPT

Bit 6: External Event 5 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[6]CPT

Bit 7: External Event 6 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[7]CPT

Bit 8: External Event 7 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[8]CPT

Bit 9: External Event 8 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[9]CPT

Bit 10: External Event 9 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[10]CPT

Bit 11: External Event 10 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

TB1SET

Bit 16: Timer B output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TB1RST

Bit 17: Timer B output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TBCMP1

Bit 18: Timer B Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TBCMP2

Bit 19: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TC1SET

Bit 20: Timer C output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TC1RST

Bit 21: Timer C output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TCCMP1

Bit 22: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TCCMP2

Bit 23: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TD1SET

Bit 24: Timer D output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TD1RST

Bit 25: Timer D output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TDCMP1

Bit 26: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TDCMP2

Bit 27: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TE1SET

Bit 28: Timer E output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TE1RST

Bit 29: Timer E output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TECMP1

Bit 30: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TECMP2

Bit 31: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

OUTR

Timerx Output Register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIDL2
rw
CHP2
rw
FAULT2
rw
IDLES2
rw
IDLEM2
rw
POL2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYPRT
rw
DLYPRTEN
rw
DTEN
rw
DIDL1
rw
CHP1
rw
FAULT1
rw
IDLES1
rw
IDLEM1
rw
POL1
rw
Toggle fields

POL1

Bit 1: Output 1 polarity.

Allowed values:
0: ActiveHigh: Positive polarity (output active high)
1: ActiveLow: Negative polarity (output active low)

IDLEM1

Bit 2: Output 1 Idle mode.

Allowed values:
0: NoEffect: No action: the output is not affected by the burst mode operation
1: SetIdle: The output is in idle state when requested by the burst mode controller

IDLES1

Bit 3: Output 1 Idle State.

Allowed values:
0: Inactive: Output idle state is inactive
1: Active: Output idle state is active

FAULT1

Bits 4-5: Output 1 Fault state.

Allowed values:
0: Disabled: No action: the output is not affected by the fault input and stays in run mode
1: SetActive: Output goes to active state after a fault event
2: SetInactive: Output goes to inactive state after a fault event
3: SetHighZ: Output goes to high-z state after a fault event

CHP1

Bit 6: Output 1 Chopper enable.

Allowed values:
0: Disabled: Output signal not altered
1: Enabled: Output signal is chopped by a carrier signal

DIDL1

Bit 7: Output 1 Deadtime upon burst mode Idle entry.

Allowed values:
0: Disabled: The programmed idle state is applied immediately to the output
1: Enabled: Deadtime (inactive level) is inserted on output before entering the idle mode

DTEN

Bit 8: Deadtime enable.

Allowed values:
0: Disabled: Output 1 and 2 signals are independent
1: Enabled: Deadtime is inserted between output 1 and output 2

DLYPRTEN

Bit 9: Delayed Protection Enable.

Allowed values:
0: Disabled: No action
1: Enabled: Delayed protection is enabled, as per DLYPRT bits

DLYPRT

Bits 10-12: Delayed Protection.

Allowed values:
0: Output1_EE6: Output 1 delayed idle on external event 6
1: Output2_EE6: Output 2 delayed idle on external event 6
2: Output1_2_EE6: Output 1 and 2 delayed idle on external event 6
3: Balanced_EE6: Balanced idle on external event 6
4: Output1_EE7: Output 1 delayed idle on external event 7
5: Output2_EE7: Output 2 delayed idle on external event 7
6: Output1_2_EE7: Output 1 and 2 delayed idle on external event 7
7: Balanced_EE7: Balanced idle on external event 7

POL2

Bit 17: Output 2 polarity.

Allowed values:
0: ActiveHigh: Positive polarity (output active high)
1: ActiveLow: Negative polarity (output active low)

IDLEM2

Bit 18: Output 2 Idle mode.

Allowed values:
0: NoEffect: No action: the output is not affected by the burst mode operation
1: SetIdle: The output is in idle state when requested by the burst mode controller

IDLES2

Bit 19: Output 2 Idle State.

Allowed values:
0: Inactive: Output idle state is inactive
1: Active: Output idle state is active

FAULT2

Bits 20-21: Output 2 Fault state.

Allowed values:
0: Disabled: No action: the output is not affected by the fault input and stays in run mode
1: SetActive: Output goes to active state after a fault event
2: SetInactive: Output goes to inactive state after a fault event
3: SetHighZ: Output goes to high-z state after a fault event

CHP2

Bit 22: Output 2 Chopper enable.

Allowed values:
0: Disabled: Output signal not altered
1: Enabled: Output signal is chopped by a carrier signal

DIDL2

Bit 23: Output 2 Deadtime upon burst mode Idle entry.

Allowed values:
0: Disabled: The programmed idle state is applied immediately to the output
1: Enabled: Deadtime (inactive level) is inserted on output before entering the idle mode

FLTR

Timerx Fault Register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLTLCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLT[5]EN
rw
FLT[4]EN
rw
FLT[3]EN
rw
FLT[2]EN
rw
FLT[1]EN
rw
Toggle fields

FLT[1]EN

Bit 0: Fault 1 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[2]EN

Bit 1: Fault 2 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[3]EN

Bit 2: Fault 3 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[4]EN

Bit 3: Fault 4 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[5]EN

Bit 4: Fault 5 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLTLCK

Bit 31: Fault sources Lock.

Allowed values:
0: Unlocked: FLT1EN..FLT5EN bits are read/write
1: Locked: FLT1EN..FLT5EN bits are read only

HRTIM_TIMB

0x40017500: High Resolution Timer: TIMB

357/357 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 ISR
0x8 ICR
0xc DIER
0x10 CNTR
0x14 PERR
0x18 REPR
0x1c CMP1R
0x20 CMP1CR
0x24 CMP2R
0x28 CMP3R
0x2c CMP4R
0x30 CPT1R
0x34 CPT2R
0x38 DTR
0x3c SET1R
0x40 RST1R
0x44 SET2R
0x48 RST2R
0x4c EEFR1
0x50 EEFR2
0x54 RSTR
0x58 CHPR
0x5c CPT1CR
0x60 CPT2CR
0x64 OUTR
0x68 FLTR
Toggle registers

CR

Timerx Control Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPDGAT
rw
PREEN
rw
DACSYNC
rw
MSTU
rw
TEU
rw
TDU
rw
TCU
rw
TBU
rw
TRSTU
rw
TREPU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DELCMP4
rw
DELCMP2
rw
SYNCSTRT
rw
SYNCRST
rw
PSHPLL
rw
HALF
rw
RETRIG
rw
CONT
rw
CKPSC
rw
Toggle fields

CKPSC

Bits 0-2: HRTIM Timer x Clock prescaler.

Allowed values: 0x0-0x7

CONT

Bit 3: Continuous mode.

Allowed values:
0: SingleShot: The timer operates in single-shot mode and stops when it reaches the MPER value
1: Continuous: The timer operates in continuous (free-running) mode and rolls over to zero when it reaches the MPER value

RETRIG

Bit 4: Re-triggerable mode.

Allowed values:
0: Disabled: The timer is not re-triggerable: a counter reset can be done only if the counter is stopped
1: Enabled: The timer is retriggerable: a counter reset is done whatever the counter state

HALF

Bit 5: Half mode enable.

Allowed values:
0: Disabled: Half mode disabled
1: Enabled: Half mode enabled

PSHPLL

Bit 6: Push-Pull mode enable.

Allowed values:
0: Disabled: Push-pull mode disabled
1: Enabled: Push-pull mode enabled

SYNCRST

Bit 10: Synchronization Resets Timer x.

Allowed values:
0: Disabled: No effect on the master timer
1: Reset: A synchroniation input event resets the master timer

SYNCSTRT

Bit 11: Synchronization Starts Timer x.

Allowed values:
0: Disabled: No effect on the master timer
1: Start: A synchroniation input event starts the master timer

DELCMP2

Bits 12-13: Delayed CMP2 mode.

Allowed values:
0: Standard: CMP2 register is always active (standard compare mode)
1: Capture1: CMP2 is recomputed and is active following a capture 1 event
2: Capture1_Compare1: CMP2 is recomputed and is active following a capture 1 event or a Compare 1 match
3: Capture1_Compare3: CMP2 is recomputed and is active following a capture 1 event or a Compare 3 match

DELCMP4

Bits 14-15: Delayed CMP4 mode.

Allowed values:
0: Standard: CMP4 register is always active (standard compare mode)
1: Capture2: CMP4 is recomputed and is active following a capture 2 event
2: Capture2_Compare1: CMP4 is recomputed and is active following a capture 2 event or a Compare 1 match
3: Capture_Compare3: CMP4 is recomputed and is active following a capture event or a Compare 3 match

TREPU

Bit 17: Timer x Repetition update.

Allowed values:
0: Disabled: Update by timer x repetition disabled
1: Enabled: Update by timer x repetition enabled

TRSTU

Bit 18: Timerx reset update.

Allowed values:
0: Disabled: Update by timer x reset/roll-over disabled
1: Enabled: Update by timer x reset/roll-over enabled

TBU

Bit 20: TBU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

TCU

Bit 21: TCU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

TDU

Bit 22: TDU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

TEU

Bit 23: TEU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

MSTU

Bit 24: Master Timer update.

Allowed values:
0: Disabled: Update by master timer disabled
1: Enabled: Update by master timer enabled

DACSYNC

Bits 25-26: AC Synchronization.

Allowed values:
0: Disabled: No DAC trigger generated
1: DACSync1: Trigger generated on DACSync1
2: DACSync2: Trigger generated on DACSync2
3: DACSync3: Trigger generated on DACSync3

PREEN

Bit 27: Preload enable.

Allowed values:
0: Disabled: Preload disabled: the write access is directly done into the active register
1: Enabled: Preload enabled: the write access is done into the preload register

UPDGAT

Bits 28-31: Update Gating.

Allowed values:
0: Independent: Update occurs independently from the DMA burst transfer
1: DMABurst: Update occurs when the DMA burst transfer is completed
2: DMABurst_Update: Update occurs on the update event following DMA burst transfer completion
3: Input1: Update occurs on a rising edge of HRTIM update enable input 1
4: Input2: Update occurs on a rising edge of HRTIM update enable input 2
5: Input3: Update occurs on a rising edge of HRTIM update enable input 3
6: Input1_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 1
7: Input2_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 2
8: Input3_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 3

ISR

Timerx Interrupt Status Register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
O2STAT
r
O1STAT
r
IPPSTAT
r
CPPSTAT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYPRT
r
RST
r
RST2
r
SET[2]
r
RST1
r
SET[1]
r
CPT[2]
r
CPT[1]
r
UPD
r
REP
r
CMP[4]
r
CMP[3]
r
CMP[2]
r
CMP[1]
r
Toggle fields

CMP[1]

Bit 0: Compare 1 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

CMP[2]

Bit 1: Compare 2 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

CMP[3]

Bit 2: Compare 3 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

CMP[4]

Bit 3: Compare 4 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

REP

Bit 4: Repetition Interrupt Flag.

Allowed values:
0: NoEvent: No timer repetition interrupt occurred
1: Event: Timer repetition interrupt occurred

UPD

Bit 6: Update Interrupt Flag.

Allowed values:
0: NoEvent: No timer update interrupt occurred
1: Event: Timer update interrupt occurred

CPT[1]

Bit 7: Capture1 Interrupt Flag.

Allowed values:
0: NoEvent: No timer x capture reset interrupt occurred
1: Event: Timer x capture reset interrupt occurred

CPT[2]

Bit 8: Capture2 Interrupt Flag.

Allowed values:
0: NoEvent: No timer x capture reset interrupt occurred
1: Event: Timer x capture reset interrupt occurred

SET[1]

Bit 9: Output 1 Set Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output set interrupt occurred
1: Event: Tx output set interrupt occurred

RST1

Bit 10: Output 1 Reset Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output reset interrupt occurred
1: Event: Tx output reset interrupt occurred

SET[2]

Bit 11: Output 2 Set Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output set interrupt occurred
1: Event: Tx output set interrupt occurred

RST2

Bit 12: Output 2 Reset Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output reset interrupt occurred
1: Event: Tx output reset interrupt occurred

RST

Bit 13: Reset Interrupt Flag.

Allowed values:
0: NoEvent: No TIMx counter reset/roll-over interrupt occurred
1: Event: TIMx counter reset/roll-over interrupt occurred

DLYPRT

Bit 14: Delayed Protection Flag.

Allowed values:
0: Inactive: Not in delayed idle or balanced idle mode
1: Active: Delayed idle or balanced idle mode entry

CPPSTAT

Bit 16: Current Push Pull Status.

Allowed values:
0: Output1Active: Signal applied on output 1 and output 2 forced inactive
1: Output2Active: Signal applied on output 2 and output 1 forced inactive

IPPSTAT

Bit 17: Idle Push Pull Status.

Allowed values:
0: Output1Active: Protection occurred when the output 1 was active and output 2 forced inactive
1: Output2Active: Protection occurred when the output 2 was active and output 1 forced inactive

O1STAT

Bit 18: Output 1 State.

Allowed values:
0: Inactive: Output was inactive
1: Active: Output was active

O2STAT

Bit 19: Output 2 State.

Allowed values:
0: Inactive: Output was inactive
1: Active: Output was active

ICR

Timerx Interrupt Clear Register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

14/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYPRTC
w1c
RSTC
w1c
RST2C
w1c
SET[2]C
w1c
RST1C
w1c
SET[1]C
w1c
CPT[2]C
w1c
CPT[1]C
w1c
UPDC
w1c
REPC
w1c
CMP[4]C
w1c
CMP[3]C
w1c
CMP[2]C
w1c
CMP[1]C
w1c
Toggle fields

CMP[1]C

Bit 0: Compare 1 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CMP[2]C

Bit 1: Compare 2 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CMP[3]C

Bit 2: Compare 3 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CMP[4]C

Bit 3: Compare 4 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

REPC

Bit 4: Repetition Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

UPDC

Bit 6: Update Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CPT[1]C

Bit 7: Capture1 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CPT[2]C

Bit 8: Capture2 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

SET[1]C

Bit 9: Output 1 Set flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

RST1C

Bit 10: Output 1 Reset flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

SET[2]C

Bit 11: Output 2 Set flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

RST2C

Bit 12: Output 2 Reset flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

RSTC

Bit 13: Reset Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

DLYPRTC

Bit 14: Delayed Protection Flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

DIER

TIMxDIER5

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

28/28 fields covered.

Toggle fields

CMP[1]IE

Bit 0: CMP1IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CMP[2]IE

Bit 1: CMP2IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CMP[3]IE

Bit 2: CMP3IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CMP[4]IE

Bit 3: CMP4IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

REPIE

Bit 4: REPIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

UPDIE

Bit 6: UPDIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CPT[1]IE

Bit 7: CPT1IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CPT[2]IE

Bit 8: CPT2IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

SET[1]IE

Bit 9: Output 1 set interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

RST1IE

Bit 10: RSTx1IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

SET[2]IE

Bit 11: Output 2 set interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

RST2IE

Bit 12: RSTx2IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

RSTIE

Bit 13: RSTIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

DLYPRTIE

Bit 14: DLYPRTIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CMP[1]DE

Bit 16: CMP1DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

CMP[2]DE

Bit 17: CMP2DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

CMP[3]DE

Bit 18: CMP3DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

CMP[4]DE

Bit 19: CMP4DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

REPDE

Bit 20: REPDE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

UPDDE

Bit 22: UPDDE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

CPT[1]DE

Bit 23: CPT1DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

CPT[2]DE

Bit 24: CPT2DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

SET[1]DE

Bit 25: Output 1 set DMA request enable.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

RST1DE

Bit 26: RSTx1DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

SET[2]DE

Bit 27: Output 2 set DMA request enable.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

RST2DE

Bit 28: RSTx2DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

RSTDE

Bit 29: RSTDE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

DLYPRTDE

Bit 30: DLYPRTDE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

CNTR

Timerx Counter Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: Counter value.

Allowed values: 0x0-0xffff

PERR

Timerx Period Register

Offset: 0x14, size: 32, reset: 0x0000FFFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PER
rw
Toggle fields

PER

Bits 0-15: Master Timer Period value.

Allowed values: 0x0-0xffff

REPR

Timerx Repetition Register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Master Timer Repetition counter value.

Allowed values: 0x0-0xff

CMP1R

Timerx Compare 1 Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CMP1CR

Timerx Compare 1 Compound Register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP1
rw
Toggle fields

CMP1

Bits 0-15: Timerx Compare 1 value.

Allowed values: 0x0-0xffff

REP

Bits 16-23: Timerx Repetition value (aliased from HRTIM_REPx register).

Allowed values: 0x0-0xff

CMP2R

Timerx Compare 2 Register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CMP3R

Timerx Compare 3 Register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CMP4R

Timerx Compare 4 Register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CPT1R

Timerx Capture 1 Register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPT
r
Toggle fields

CPT

Bits 0-15: Timerx Capture 1 value.

Allowed values: 0x0-0xffff

CPT2R

Timerx Capture 2 Register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPT
r
Toggle fields

CPT

Bits 0-15: Timerx Capture 1 value.

Allowed values: 0x0-0xffff

DTR

Timerx Deadtime Register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTFLK
rw
DTFSLK
rw
SDTF
rw
DTF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTRLK
rw
DTRSLK
rw
DTPRSC
rw
SDTR
rw
DTR
rw
Toggle fields

DTR

Bits 0-8: Deadtime Rising value.

Allowed values: 0x0-0x1ff

SDTR

Bit 9: Sign Deadtime Rising value.

Allowed values:
0: Positive: Positive deadtime on rising edge
1: Negative: Negative deadtime on rising edge

DTPRSC

Bits 10-12: Deadtime Prescaler.

Allowed values: 0x0-0x7

DTRSLK

Bit 14: Deadtime Rising Sign Lock.

Allowed values:
0: Unlocked: Deadtime rising sign is writable
1: Locked: Deadtime rising sign is read-only

DTRLK

Bit 15: Deadtime Rising Lock.

Allowed values:
0: Unlocked: Deadtime rising value and sign is writable
1: Locked: Deadtime rising value and sign is read-only

DTF

Bits 16-24: Deadtime Falling value.

Allowed values: 0x0-0x1ff

SDTF

Bit 25: Sign Deadtime Falling value.

Allowed values:
0: Positive: Positive deadtime on falling edge
1: Negative: Negative deadtime on falling edge

DTFSLK

Bit 30: Deadtime Falling Sign Lock.

Allowed values:
0: Unlocked: Deadtime falling sign is writable
1: Locked: Deadtime falling sign is read-only

DTFLK

Bit 31: Deadtime Falling Lock.

Allowed values:
0: Unlocked: Deadtime falling value and sign is writable
1: Locked: Deadtime falling value and sign is read-only

SET1R

Timerx Output1 Set Register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

Toggle fields

SST

Bit 0: Software Set trigger.

Allowed values:
0: NoEffect: No effect
1: SetActive: Force output to its active state

RESYNC

Bit 1: Timer A resynchronizaton.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetActive: Timer reset event coming solely from software or SYNC input event forces the output to its active state

PER

Bit 2: Timer A Period.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetActive: Timer period event forces the output to its active state

CMP[1]

Bit 3: Timer A compare 1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[2]

Bit 4: Timer A compare 2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[3]

Bit 5: Timer A compare 3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[4]

Bit 6: Timer A compare 4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

MSTPER

Bit 7: Master Period.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetActive: Master timer counter roll-over/reset forces the output to its active state

MSTCMP[1]

Bit 8: Master Compare 1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[2]

Bit 9: Master Compare 2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[3]

Bit 10: Master Compare 3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[4]

Bit 11: Master Compare 4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

TIMACMP1

Bit 12: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMACMP2

Bit 13: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMACMP4

Bit 14: Timer A Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMCCMP3

Bit 15: Timer C Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMCCMP4

Bit 16: Timer C Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMDCMP3

Bit 17: Timer D Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMDCMP4

Bit 18: Timer D Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMECMP1

Bit 19: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMECMP2

Bit 20: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

EXTEVNT[1]

Bit 21: External Event 1.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[2]

Bit 22: External Event 2.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[3]

Bit 23: External Event 3.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[4]

Bit 24: External Event 4.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[5]

Bit 25: External Event 5.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[6]

Bit 26: External Event 6.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[7]

Bit 27: External Event 7.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[8]

Bit 28: External Event 8.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[9]

Bit 29: External Event 9.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[10]

Bit 30: External Event 10.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

UPDATE

Bit 31: Registers update (transfer preload to active).

Allowed values:
0: NoEffect: Register update event has no effect
1: SetActive: Register update event forces the output to its active state

RST1R

Timerx Output1 Reset Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

Toggle fields

SRT

Bit 0: SRT.

Allowed values:
0: NoEffect: No effect
1: SetInactive: Force output to its inactive state

RESYNC

Bit 1: RESYNC.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetInactive: Timer reset event coming solely from software or SYNC input event forces the output to its inactive state

PER

Bit 2: PER.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetInactive: Timer period event forces the output to its inactive state

CMP[1]

Bit 3: CMP1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[2]

Bit 4: CMP2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[3]

Bit 5: CMP3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[4]

Bit 6: CMP4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

MSTPER

Bit 7: MSTPER.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetInactive: Master timer counter roll-over/reset forces the output to its inactive state

MSTCMP[1]

Bit 8: MSTCMP1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[2]

Bit 9: MSTCMP2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[3]

Bit 10: MSTCMP3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[4]

Bit 11: MSTCMP4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

TIMACMP1

Bit 12: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMACMP2

Bit 13: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMACMP4

Bit 14: Timer A Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMCCMP3

Bit 15: Timer C Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMCCMP4

Bit 16: Timer C Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMDCMP3

Bit 17: Timer D Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMDCMP4

Bit 18: Timer D Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMECMP1

Bit 19: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMECMP2

Bit 20: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

EXTEVNT[1]

Bit 21: EXTEVNT1.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[2]

Bit 22: EXTEVNT2.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[3]

Bit 23: EXTEVNT3.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[4]

Bit 24: EXTEVNT4.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[5]

Bit 25: EXTEVNT5.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[6]

Bit 26: EXTEVNT6.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[7]

Bit 27: EXTEVNT7.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[8]

Bit 28: EXTEVNT8.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[9]

Bit 29: EXTEVNT9.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[10]

Bit 30: EXTEVNT10.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

UPDATE

Bit 31: UPDATE.

Allowed values:
0: NoEffect: Register update event has no effect
1: SetInactive: Register update event forces the output to its inactive state

SET2R

Timerx Output2 Set Register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

Toggle fields

SST

Bit 0: Software Set trigger.

Allowed values:
0: NoEffect: No effect
1: SetActive: Force output to its active state

RESYNC

Bit 1: Timer A resynchronizaton.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetActive: Timer reset event coming solely from software or SYNC input event forces the output to its active state

PER

Bit 2: Timer A Period.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetActive: Timer period event forces the output to its active state

CMP[1]

Bit 3: Timer A compare 1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[2]

Bit 4: Timer A compare 2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[3]

Bit 5: Timer A compare 3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[4]

Bit 6: Timer A compare 4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

MSTPER

Bit 7: Master Period.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetActive: Master timer counter roll-over/reset forces the output to its active state

MSTCMP[1]

Bit 8: Master Compare 1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[2]

Bit 9: Master Compare 2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[3]

Bit 10: Master Compare 3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[4]

Bit 11: Master Compare 4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

TIMACMP1

Bit 12: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMACMP2

Bit 13: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMACMP4

Bit 14: Timer A Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMCCMP3

Bit 15: Timer C Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMCCMP4

Bit 16: Timer C Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMDCMP3

Bit 17: Timer D Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMDCMP4

Bit 18: Timer D Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMECMP1

Bit 19: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMECMP2

Bit 20: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

EXTEVNT[1]

Bit 21: External Event 1.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[2]

Bit 22: External Event 2.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[3]

Bit 23: External Event 3.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[4]

Bit 24: External Event 4.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[5]

Bit 25: External Event 5.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[6]

Bit 26: External Event 6.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[7]

Bit 27: External Event 7.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[8]

Bit 28: External Event 8.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[9]

Bit 29: External Event 9.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[10]

Bit 30: External Event 10.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

UPDATE

Bit 31: Registers update (transfer preload to active).

Allowed values:
0: NoEffect: Register update event has no effect
1: SetActive: Register update event forces the output to its active state

RST2R

Timerx Output2 Reset Register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

Toggle fields

SRT

Bit 0: SRT.

Allowed values:
0: NoEffect: No effect
1: SetInactive: Force output to its inactive state

RESYNC

Bit 1: RESYNC.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetInactive: Timer reset event coming solely from software or SYNC input event forces the output to its inactive state

PER

Bit 2: PER.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetInactive: Timer period event forces the output to its inactive state

CMP[1]

Bit 3: CMP1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[2]

Bit 4: CMP2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[3]

Bit 5: CMP3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[4]

Bit 6: CMP4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

MSTPER

Bit 7: MSTPER.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetInactive: Master timer counter roll-over/reset forces the output to its inactive state

MSTCMP[1]

Bit 8: MSTCMP1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[2]

Bit 9: MSTCMP2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[3]

Bit 10: MSTCMP3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[4]

Bit 11: MSTCMP4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

TIMACMP1

Bit 12: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMACMP2

Bit 13: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMACMP4

Bit 14: Timer A Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMCCMP3

Bit 15: Timer C Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMCCMP4

Bit 16: Timer C Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMDCMP3

Bit 17: Timer D Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMDCMP4

Bit 18: Timer D Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMECMP1

Bit 19: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMECMP2

Bit 20: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

EXTEVNT[1]

Bit 21: EXTEVNT1.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[2]

Bit 22: EXTEVNT2.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[3]

Bit 23: EXTEVNT3.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[4]

Bit 24: EXTEVNT4.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[5]

Bit 25: EXTEVNT5.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[6]

Bit 26: EXTEVNT6.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[7]

Bit 27: EXTEVNT7.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[8]

Bit 28: EXTEVNT8.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[9]

Bit 29: EXTEVNT9.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[10]

Bit 30: EXTEVNT10.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

UPDATE

Bit 31: UPDATE.

Allowed values:
0: NoEffect: Register update event has no effect
1: SetInactive: Register update event forces the output to its inactive state

EEFR1

Timerx External Event Filtering Register 1

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EE[5]FLTR
rw
EE[5]LTCH
rw
EE[4]FLTR
rw
EE[4]LTCH
rw
EE[3]FLTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EE[3]FLTR
rw
EE[3]LTCH
rw
EE[2]FLTR
rw
EE[2]LTCH
rw
EE[1]FLTR
rw
EE[1]LTCH
rw
Toggle fields

EE[1]LTCH

Bit 0: External Event 1 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[1]FLTR

Bits 1-4: External Event 1 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[2]LTCH

Bit 6: External Event 2 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[2]FLTR

Bits 7-10: External Event 2 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[3]LTCH

Bit 12: External Event 3 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[3]FLTR

Bits 13-16: External Event 3 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[4]LTCH

Bit 18: External Event 4 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[4]FLTR

Bits 19-22: External Event 4 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[5]LTCH

Bit 24: External Event 5 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[5]FLTR

Bits 25-28: External Event 5 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EEFR2

Timerx External Event Filtering Register 2

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EE[10]FLTR
rw
EE[10]LTCH
rw
EE[9]FLTR
rw
EE[9]LTCH
rw
EE[8]FLTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EE[8]FLTR
rw
EE[8]LTCH
rw
EE[7]FLTR
rw
EE[7]LTCH
rw
EE[6]FLTR
rw
EE[6]LTCH
rw
Toggle fields

EE[6]LTCH

Bit 0: External Event 6 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[6]FLTR

Bits 1-4: External Event 6 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[7]LTCH

Bit 6: External Event 7 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[7]FLTR

Bits 7-10: External Event 7 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[8]LTCH

Bit 12: External Event 8 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[8]FLTR

Bits 13-16: External Event 8 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[9]LTCH

Bit 18: External Event 9 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[9]FLTR

Bits 19-22: External Event 9 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[10]LTCH

Bit 24: External Event 10 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[10]FLTR

Bits 25-28: External Event 10 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

RSTR

TimerA Reset Register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

30/30 fields covered.

Toggle fields

UPDT

Bit 1: Timer A Update reset.

Allowed values:
0: NoEffect: Update event has no effect
1: ResetCounter: Timer X counter is reset upon update event

CMP2

Bit 2: Timer A compare 2 reset.

Allowed values:
0: NoEffect: Timer X compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer X compare Z event

CMP4

Bit 3: Timer A compare 4 reset.

Allowed values:
0: NoEffect: Timer X compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer X compare Z event

MSTPER

Bit 4: Master timer Period.

Allowed values:
0: NoEffect: Master timer period event has no effect
1: ResetCounter: Timer X counter is reset upon master timer period event

MSTCMP1

Bit 5: Master compare 1.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

MSTCMP2

Bit 6: Master compare 2.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

MSTCMP3

Bit 7: Master compare 3.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

MSTCMP4

Bit 8: Master compare 4.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

EXTEVNT1

Bit 9: External Event 1.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT2

Bit 10: External Event 2.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT3

Bit 11: External Event 3.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT4

Bit 12: External Event 4.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT5

Bit 13: External Event 5.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT6

Bit 14: External Event 6.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT7

Bit 15: External Event 7.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT8

Bit 16: External Event 8.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT9

Bit 17: External Event 9.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT10

Bit 18: External Event 10.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

TIMACMP1

Bit 19: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMACMP2

Bit 20: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMACMP4

Bit 21: Timer A Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMCCMP1

Bit 22: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMCCMP2

Bit 23: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMCCMP4

Bit 24: Timer C Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMDCMP1

Bit 25: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMDCMP2

Bit 26: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMDCMP4

Bit 27: Timer D Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMECMP1

Bit 28: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMECMP2

Bit 29: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMECMP4

Bit 30: Timer E Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

CHPR

Timerx Chopper Register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STRTPW
rw
CARDTY
rw
CARFRQ
rw
Toggle fields

CARFRQ

Bits 0-3: Timerx carrier frequency value.

Allowed values: 0x0-0xf

CARDTY

Bits 4-6: Timerx chopper duty cycle value.

Allowed values: 0x0-0x7

STRTPW

Bits 7-10: STRTPW.

Allowed values: 0x0-0xf

CPT1CR

Timerx Capture 2 Control Register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

28/28 fields covered.

Toggle fields

SWCPT

Bit 0: Software Capture.

Allowed values:
0: NoEffect: No effect
1: TriggerCapture: Force capture Z

UPDCPT

Bit 1: Update Capture.

Allowed values:
0: NoEffect: Update event has no effect
1: TriggerCapture: Update event triggers capture Z

EXEV[1]CPT

Bit 2: External Event 1 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[2]CPT

Bit 3: External Event 2 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[3]CPT

Bit 4: External Event 3 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[4]CPT

Bit 5: External Event 4 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[5]CPT

Bit 6: External Event 5 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[6]CPT

Bit 7: External Event 6 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[7]CPT

Bit 8: External Event 7 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[8]CPT

Bit 9: External Event 8 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[9]CPT

Bit 10: External Event 9 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[10]CPT

Bit 11: External Event 10 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

TA1SET

Bit 12: Timer A output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TA1RST

Bit 13: Timer A output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TACMP1

Bit 14: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TACMP2

Bit 15: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TC1SET

Bit 20: Timer C output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TC1RST

Bit 21: Timer C output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TCCMP1

Bit 22: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TCCMP2

Bit 23: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TD1SET

Bit 24: Timer D output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TD1RST

Bit 25: Timer D output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TDCMP1

Bit 26: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TDCMP2

Bit 27: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TE1SET

Bit 28: Timer E output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TE1RST

Bit 29: Timer E output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TECMP1

Bit 30: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TECMP2

Bit 31: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

CPT2CR

CPT2xCR

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

28/28 fields covered.

Toggle fields

SWCPT

Bit 0: Software Capture.

Allowed values:
0: NoEffect: No effect
1: TriggerCapture: Force capture Z

UPDCPT

Bit 1: Update Capture.

Allowed values:
0: NoEffect: Update event has no effect
1: TriggerCapture: Update event triggers capture Z

EXEV[1]CPT

Bit 2: External Event 1 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[2]CPT

Bit 3: External Event 2 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[3]CPT

Bit 4: External Event 3 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[4]CPT

Bit 5: External Event 4 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[5]CPT

Bit 6: External Event 5 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[6]CPT

Bit 7: External Event 6 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[7]CPT

Bit 8: External Event 7 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[8]CPT

Bit 9: External Event 8 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[9]CPT

Bit 10: External Event 9 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[10]CPT

Bit 11: External Event 10 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

TA1SET

Bit 12: Timer A output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TA1RST

Bit 13: Timer A output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TACMP1

Bit 14: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TACMP2

Bit 15: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TC1SET

Bit 20: Timer C output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TC1RST

Bit 21: Timer C output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TCCMP1

Bit 22: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TCCMP2

Bit 23: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TD1SET

Bit 24: Timer D output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TD1RST

Bit 25: Timer D output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TDCMP1

Bit 26: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TDCMP2

Bit 27: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TE1SET

Bit 28: Timer E output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TE1RST

Bit 29: Timer E output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TECMP1

Bit 30: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TECMP2

Bit 31: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

OUTR

Timerx Output Register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIDL2
rw
CHP2
rw
FAULT2
rw
IDLES2
rw
IDLEM2
rw
POL2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYPRT
rw
DLYPRTEN
rw
DTEN
rw
DIDL1
rw
CHP1
rw
FAULT1
rw
IDLES1
rw
IDLEM1
rw
POL1
rw
Toggle fields

POL1

Bit 1: Output 1 polarity.

Allowed values:
0: ActiveHigh: Positive polarity (output active high)
1: ActiveLow: Negative polarity (output active low)

IDLEM1

Bit 2: Output 1 Idle mode.

Allowed values:
0: NoEffect: No action: the output is not affected by the burst mode operation
1: SetIdle: The output is in idle state when requested by the burst mode controller

IDLES1

Bit 3: Output 1 Idle State.

Allowed values:
0: Inactive: Output idle state is inactive
1: Active: Output idle state is active

FAULT1

Bits 4-5: Output 1 Fault state.

Allowed values:
0: Disabled: No action: the output is not affected by the fault input and stays in run mode
1: SetActive: Output goes to active state after a fault event
2: SetInactive: Output goes to inactive state after a fault event
3: SetHighZ: Output goes to high-z state after a fault event

CHP1

Bit 6: Output 1 Chopper enable.

Allowed values:
0: Disabled: Output signal not altered
1: Enabled: Output signal is chopped by a carrier signal

DIDL1

Bit 7: Output 1 Deadtime upon burst mode Idle entry.

Allowed values:
0: Disabled: The programmed idle state is applied immediately to the output
1: Enabled: Deadtime (inactive level) is inserted on output before entering the idle mode

DTEN

Bit 8: Deadtime enable.

Allowed values:
0: Disabled: Output 1 and 2 signals are independent
1: Enabled: Deadtime is inserted between output 1 and output 2

DLYPRTEN

Bit 9: Delayed Protection Enable.

Allowed values:
0: Disabled: No action
1: Enabled: Delayed protection is enabled, as per DLYPRT bits

DLYPRT

Bits 10-12: Delayed Protection.

Allowed values:
0: Output1_EE6: Output 1 delayed idle on external event 6
1: Output2_EE6: Output 2 delayed idle on external event 6
2: Output1_2_EE6: Output 1 and 2 delayed idle on external event 6
3: Balanced_EE6: Balanced idle on external event 6
4: Output1_EE7: Output 1 delayed idle on external event 7
5: Output2_EE7: Output 2 delayed idle on external event 7
6: Output1_2_EE7: Output 1 and 2 delayed idle on external event 7
7: Balanced_EE7: Balanced idle on external event 7

POL2

Bit 17: Output 2 polarity.

Allowed values:
0: ActiveHigh: Positive polarity (output active high)
1: ActiveLow: Negative polarity (output active low)

IDLEM2

Bit 18: Output 2 Idle mode.

Allowed values:
0: NoEffect: No action: the output is not affected by the burst mode operation
1: SetIdle: The output is in idle state when requested by the burst mode controller

IDLES2

Bit 19: Output 2 Idle State.

Allowed values:
0: Inactive: Output idle state is inactive
1: Active: Output idle state is active

FAULT2

Bits 20-21: Output 2 Fault state.

Allowed values:
0: Disabled: No action: the output is not affected by the fault input and stays in run mode
1: SetActive: Output goes to active state after a fault event
2: SetInactive: Output goes to inactive state after a fault event
3: SetHighZ: Output goes to high-z state after a fault event

CHP2

Bit 22: Output 2 Chopper enable.

Allowed values:
0: Disabled: Output signal not altered
1: Enabled: Output signal is chopped by a carrier signal

DIDL2

Bit 23: Output 2 Deadtime upon burst mode Idle entry.

Allowed values:
0: Disabled: The programmed idle state is applied immediately to the output
1: Enabled: Deadtime (inactive level) is inserted on output before entering the idle mode

FLTR

Timerx Fault Register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLTLCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLT[5]EN
rw
FLT[4]EN
rw
FLT[3]EN
rw
FLT[2]EN
rw
FLT[1]EN
rw
Toggle fields

FLT[1]EN

Bit 0: Fault 1 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[2]EN

Bit 1: Fault 2 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[3]EN

Bit 2: Fault 3 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[4]EN

Bit 3: Fault 4 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[5]EN

Bit 4: Fault 5 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLTLCK

Bit 31: Fault sources Lock.

Allowed values:
0: Unlocked: FLT1EN..FLT5EN bits are read/write
1: Locked: FLT1EN..FLT5EN bits are read only

HRTIM_TIMC

0x40017580: High Resolution Timer: TIMC

357/357 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 ISR
0x8 ICR
0xc DIER
0x10 CNTR
0x14 PERR
0x18 REPR
0x1c CMP1R
0x20 CMP1CR
0x24 CMP2R
0x28 CMP3R
0x2c CMP4R
0x30 CPT1R
0x34 CPT2R
0x38 DTR
0x3c SET1R
0x40 RST1R
0x44 SET2R
0x48 RST2R
0x4c EEFR1
0x50 EEFR2
0x54 RSTR
0x58 CHPR
0x5c CPT1CR
0x60 CPT2CR
0x64 OUTR
0x68 FLTR
Toggle registers

CR

Timerx Control Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPDGAT
rw
PREEN
rw
DACSYNC
rw
MSTU
rw
TEU
rw
TDU
rw
TCU
rw
TBU
rw
TRSTU
rw
TREPU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DELCMP4
rw
DELCMP2
rw
SYNCSTRT
rw
SYNCRST
rw
PSHPLL
rw
HALF
rw
RETRIG
rw
CONT
rw
CKPSC
rw
Toggle fields

CKPSC

Bits 0-2: HRTIM Timer x Clock prescaler.

Allowed values: 0x0-0x7

CONT

Bit 3: Continuous mode.

Allowed values:
0: SingleShot: The timer operates in single-shot mode and stops when it reaches the MPER value
1: Continuous: The timer operates in continuous (free-running) mode and rolls over to zero when it reaches the MPER value

RETRIG

Bit 4: Re-triggerable mode.

Allowed values:
0: Disabled: The timer is not re-triggerable: a counter reset can be done only if the counter is stopped
1: Enabled: The timer is retriggerable: a counter reset is done whatever the counter state

HALF

Bit 5: Half mode enable.

Allowed values:
0: Disabled: Half mode disabled
1: Enabled: Half mode enabled

PSHPLL

Bit 6: Push-Pull mode enable.

Allowed values:
0: Disabled: Push-pull mode disabled
1: Enabled: Push-pull mode enabled

SYNCRST

Bit 10: Synchronization Resets Timer x.

Allowed values:
0: Disabled: No effect on the master timer
1: Reset: A synchroniation input event resets the master timer

SYNCSTRT

Bit 11: Synchronization Starts Timer x.

Allowed values:
0: Disabled: No effect on the master timer
1: Start: A synchroniation input event starts the master timer

DELCMP2

Bits 12-13: Delayed CMP2 mode.

Allowed values:
0: Standard: CMP2 register is always active (standard compare mode)
1: Capture1: CMP2 is recomputed and is active following a capture 1 event
2: Capture1_Compare1: CMP2 is recomputed and is active following a capture 1 event or a Compare 1 match
3: Capture1_Compare3: CMP2 is recomputed and is active following a capture 1 event or a Compare 3 match

DELCMP4

Bits 14-15: Delayed CMP4 mode.

Allowed values:
0: Standard: CMP4 register is always active (standard compare mode)
1: Capture2: CMP4 is recomputed and is active following a capture 2 event
2: Capture2_Compare1: CMP4 is recomputed and is active following a capture 2 event or a Compare 1 match
3: Capture_Compare3: CMP4 is recomputed and is active following a capture event or a Compare 3 match

TREPU

Bit 17: Timer x Repetition update.

Allowed values:
0: Disabled: Update by timer x repetition disabled
1: Enabled: Update by timer x repetition enabled

TRSTU

Bit 18: Timerx reset update.

Allowed values:
0: Disabled: Update by timer x reset/roll-over disabled
1: Enabled: Update by timer x reset/roll-over enabled

TBU

Bit 20: TBU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

TCU

Bit 21: TCU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

TDU

Bit 22: TDU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

TEU

Bit 23: TEU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

MSTU

Bit 24: Master Timer update.

Allowed values:
0: Disabled: Update by master timer disabled
1: Enabled: Update by master timer enabled

DACSYNC

Bits 25-26: AC Synchronization.

Allowed values:
0: Disabled: No DAC trigger generated
1: DACSync1: Trigger generated on DACSync1
2: DACSync2: Trigger generated on DACSync2
3: DACSync3: Trigger generated on DACSync3

PREEN

Bit 27: Preload enable.

Allowed values:
0: Disabled: Preload disabled: the write access is directly done into the active register
1: Enabled: Preload enabled: the write access is done into the preload register

UPDGAT

Bits 28-31: Update Gating.

Allowed values:
0: Independent: Update occurs independently from the DMA burst transfer
1: DMABurst: Update occurs when the DMA burst transfer is completed
2: DMABurst_Update: Update occurs on the update event following DMA burst transfer completion
3: Input1: Update occurs on a rising edge of HRTIM update enable input 1
4: Input2: Update occurs on a rising edge of HRTIM update enable input 2
5: Input3: Update occurs on a rising edge of HRTIM update enable input 3
6: Input1_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 1
7: Input2_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 2
8: Input3_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 3

ISR

Timerx Interrupt Status Register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
O2STAT
r
O1STAT
r
IPPSTAT
r
CPPSTAT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYPRT
r
RST
r
RST2
r
SET[2]
r
RST1
r
SET[1]
r
CPT[2]
r
CPT[1]
r
UPD
r
REP
r
CMP[4]
r
CMP[3]
r
CMP[2]
r
CMP[1]
r
Toggle fields

CMP[1]

Bit 0: Compare 1 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

CMP[2]

Bit 1: Compare 2 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

CMP[3]

Bit 2: Compare 3 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

CMP[4]

Bit 3: Compare 4 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

REP

Bit 4: Repetition Interrupt Flag.

Allowed values:
0: NoEvent: No timer repetition interrupt occurred
1: Event: Timer repetition interrupt occurred

UPD

Bit 6: Update Interrupt Flag.

Allowed values:
0: NoEvent: No timer update interrupt occurred
1: Event: Timer update interrupt occurred

CPT[1]

Bit 7: Capture1 Interrupt Flag.

Allowed values:
0: NoEvent: No timer x capture reset interrupt occurred
1: Event: Timer x capture reset interrupt occurred

CPT[2]

Bit 8: Capture2 Interrupt Flag.

Allowed values:
0: NoEvent: No timer x capture reset interrupt occurred
1: Event: Timer x capture reset interrupt occurred

SET[1]

Bit 9: Output 1 Set Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output set interrupt occurred
1: Event: Tx output set interrupt occurred

RST1

Bit 10: Output 1 Reset Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output reset interrupt occurred
1: Event: Tx output reset interrupt occurred

SET[2]

Bit 11: Output 2 Set Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output set interrupt occurred
1: Event: Tx output set interrupt occurred

RST2

Bit 12: Output 2 Reset Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output reset interrupt occurred
1: Event: Tx output reset interrupt occurred

RST

Bit 13: Reset Interrupt Flag.

Allowed values:
0: NoEvent: No TIMx counter reset/roll-over interrupt occurred
1: Event: TIMx counter reset/roll-over interrupt occurred

DLYPRT

Bit 14: Delayed Protection Flag.

Allowed values:
0: Inactive: Not in delayed idle or balanced idle mode
1: Active: Delayed idle or balanced idle mode entry

CPPSTAT

Bit 16: Current Push Pull Status.

Allowed values:
0: Output1Active: Signal applied on output 1 and output 2 forced inactive
1: Output2Active: Signal applied on output 2 and output 1 forced inactive

IPPSTAT

Bit 17: Idle Push Pull Status.

Allowed values:
0: Output1Active: Protection occurred when the output 1 was active and output 2 forced inactive
1: Output2Active: Protection occurred when the output 2 was active and output 1 forced inactive

O1STAT

Bit 18: Output 1 State.

Allowed values:
0: Inactive: Output was inactive
1: Active: Output was active

O2STAT

Bit 19: Output 2 State.

Allowed values:
0: Inactive: Output was inactive
1: Active: Output was active

ICR

Timerx Interrupt Clear Register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

14/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYPRTC
w1c
RSTC
w1c
RST2C
w1c
SET[2]C
w1c
RST1C
w1c
SET[1]C
w1c
CPT[2]C
w1c
CPT[1]C
w1c
UPDC
w1c
REPC
w1c
CMP[4]C
w1c
CMP[3]C
w1c
CMP[2]C
w1c
CMP[1]C
w1c
Toggle fields

CMP[1]C

Bit 0: Compare 1 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CMP[2]C

Bit 1: Compare 2 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CMP[3]C

Bit 2: Compare 3 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CMP[4]C

Bit 3: Compare 4 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

REPC

Bit 4: Repetition Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

UPDC

Bit 6: Update Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CPT[1]C

Bit 7: Capture1 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CPT[2]C

Bit 8: Capture2 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

SET[1]C

Bit 9: Output 1 Set flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

RST1C

Bit 10: Output 1 Reset flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

SET[2]C

Bit 11: Output 2 Set flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

RST2C

Bit 12: Output 2 Reset flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

RSTC

Bit 13: Reset Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

DLYPRTC

Bit 14: Delayed Protection Flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

DIER

TIMxDIER5

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

28/28 fields covered.

Toggle fields

CMP[1]IE

Bit 0: CMP1IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CMP[2]IE

Bit 1: CMP2IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CMP[3]IE

Bit 2: CMP3IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CMP[4]IE

Bit 3: CMP4IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

REPIE

Bit 4: REPIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

UPDIE

Bit 6: UPDIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CPT[1]IE

Bit 7: CPT1IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CPT[2]IE

Bit 8: CPT2IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

SET[1]IE

Bit 9: Output 1 set interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

RST1IE

Bit 10: RSTx1IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

SET[2]IE

Bit 11: Output 2 set interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

RST2IE

Bit 12: RSTx2IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

RSTIE

Bit 13: RSTIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

DLYPRTIE

Bit 14: DLYPRTIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CMP[1]DE

Bit 16: CMP1DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

CMP[2]DE

Bit 17: CMP2DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

CMP[3]DE

Bit 18: CMP3DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

CMP[4]DE

Bit 19: CMP4DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

REPDE

Bit 20: REPDE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

UPDDE

Bit 22: UPDDE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

CPT[1]DE

Bit 23: CPT1DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

CPT[2]DE

Bit 24: CPT2DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

SET[1]DE

Bit 25: Output 1 set DMA request enable.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

RST1DE

Bit 26: RSTx1DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

SET[2]DE

Bit 27: Output 2 set DMA request enable.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

RST2DE

Bit 28: RSTx2DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

RSTDE

Bit 29: RSTDE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

DLYPRTDE

Bit 30: DLYPRTDE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

CNTR

Timerx Counter Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: Counter value.

Allowed values: 0x0-0xffff

PERR

Timerx Period Register

Offset: 0x14, size: 32, reset: 0x0000FFFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PER
rw
Toggle fields

PER

Bits 0-15: Master Timer Period value.

Allowed values: 0x0-0xffff

REPR

Timerx Repetition Register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Master Timer Repetition counter value.

Allowed values: 0x0-0xff

CMP1R

Timerx Compare 1 Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CMP1CR

Timerx Compare 1 Compound Register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP1
rw
Toggle fields

CMP1

Bits 0-15: Timerx Compare 1 value.

Allowed values: 0x0-0xffff

REP

Bits 16-23: Timerx Repetition value (aliased from HRTIM_REPx register).

Allowed values: 0x0-0xff

CMP2R

Timerx Compare 2 Register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CMP3R

Timerx Compare 3 Register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CMP4R

Timerx Compare 4 Register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CPT1R

Timerx Capture 1 Register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPT
r
Toggle fields

CPT

Bits 0-15: Timerx Capture 1 value.

Allowed values: 0x0-0xffff

CPT2R

Timerx Capture 2 Register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPT
r
Toggle fields

CPT

Bits 0-15: Timerx Capture 1 value.

Allowed values: 0x0-0xffff

DTR

Timerx Deadtime Register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTFLK
rw
DTFSLK
rw
SDTF
rw
DTF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTRLK
rw
DTRSLK
rw
DTPRSC
rw
SDTR
rw
DTR
rw
Toggle fields

DTR

Bits 0-8: Deadtime Rising value.

Allowed values: 0x0-0x1ff

SDTR

Bit 9: Sign Deadtime Rising value.

Allowed values:
0: Positive: Positive deadtime on rising edge
1: Negative: Negative deadtime on rising edge

DTPRSC

Bits 10-12: Deadtime Prescaler.

Allowed values: 0x0-0x7

DTRSLK

Bit 14: Deadtime Rising Sign Lock.

Allowed values:
0: Unlocked: Deadtime rising sign is writable
1: Locked: Deadtime rising sign is read-only

DTRLK

Bit 15: Deadtime Rising Lock.

Allowed values:
0: Unlocked: Deadtime rising value and sign is writable
1: Locked: Deadtime rising value and sign is read-only

DTF

Bits 16-24: Deadtime Falling value.

Allowed values: 0x0-0x1ff

SDTF

Bit 25: Sign Deadtime Falling value.

Allowed values:
0: Positive: Positive deadtime on falling edge
1: Negative: Negative deadtime on falling edge

DTFSLK

Bit 30: Deadtime Falling Sign Lock.

Allowed values:
0: Unlocked: Deadtime falling sign is writable
1: Locked: Deadtime falling sign is read-only

DTFLK

Bit 31: Deadtime Falling Lock.

Allowed values:
0: Unlocked: Deadtime falling value and sign is writable
1: Locked: Deadtime falling value and sign is read-only

SET1R

Timerx Output1 Set Register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

Toggle fields

SST

Bit 0: Software Set trigger.

Allowed values:
0: NoEffect: No effect
1: SetActive: Force output to its active state

RESYNC

Bit 1: Timer A resynchronizaton.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetActive: Timer reset event coming solely from software or SYNC input event forces the output to its active state

PER

Bit 2: Timer A Period.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetActive: Timer period event forces the output to its active state

CMP[1]

Bit 3: Timer A compare 1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[2]

Bit 4: Timer A compare 2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[3]

Bit 5: Timer A compare 3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[4]

Bit 6: Timer A compare 4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

MSTPER

Bit 7: Master Period.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetActive: Master timer counter roll-over/reset forces the output to its active state

MSTCMP[1]

Bit 8: Master Compare 1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[2]

Bit 9: Master Compare 2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[3]

Bit 10: Master Compare 3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[4]

Bit 11: Master Compare 4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

TIMACMP2

Bit 12: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMACMP3

Bit 13: Timer A Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMBCMP2

Bit 14: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMBCMP3

Bit 15: Timer B Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMDCMP2

Bit 16: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMDCMP4

Bit 17: Timer D Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMECMP2

Bit 18: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMECMP3

Bit 19: Timer E Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMECMP4

Bit 20: Timer E Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

EXTEVNT[1]

Bit 21: External Event 1.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[2]

Bit 22: External Event 2.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[3]

Bit 23: External Event 3.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[4]

Bit 24: External Event 4.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[5]

Bit 25: External Event 5.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[6]

Bit 26: External Event 6.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[7]

Bit 27: External Event 7.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[8]

Bit 28: External Event 8.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[9]

Bit 29: External Event 9.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[10]

Bit 30: External Event 10.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

UPDATE

Bit 31: Registers update (transfer preload to active).

Allowed values:
0: NoEffect: Register update event has no effect
1: SetActive: Register update event forces the output to its active state

RST1R

Timerx Output1 Reset Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

Toggle fields

SRT

Bit 0: SRT.

Allowed values:
0: NoEffect: No effect
1: SetInactive: Force output to its inactive state

RESYNC

Bit 1: RESYNC.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetInactive: Timer reset event coming solely from software or SYNC input event forces the output to its inactive state

PER

Bit 2: PER.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetInactive: Timer period event forces the output to its inactive state

CMP[1]

Bit 3: CMP1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[2]

Bit 4: CMP2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[3]

Bit 5: CMP3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[4]

Bit 6: CMP4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

MSTPER

Bit 7: MSTPER.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetInactive: Master timer counter roll-over/reset forces the output to its inactive state

MSTCMP[1]

Bit 8: MSTCMP1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[2]

Bit 9: MSTCMP2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[3]

Bit 10: MSTCMP3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[4]

Bit 11: MSTCMP4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

TIMACMP2

Bit 12: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMACMP3

Bit 13: Timer A Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMBCMP2

Bit 14: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMBCMP3

Bit 15: Timer B Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMDCMP2

Bit 16: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMDCMP4

Bit 17: Timer D Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMECMP2

Bit 18: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMECMP3

Bit 19: Timer E Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMECMP4

Bit 20: Timer E Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

EXTEVNT[1]

Bit 21: EXTEVNT1.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[2]

Bit 22: EXTEVNT2.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[3]

Bit 23: EXTEVNT3.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[4]

Bit 24: EXTEVNT4.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[5]

Bit 25: EXTEVNT5.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[6]

Bit 26: EXTEVNT6.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[7]

Bit 27: EXTEVNT7.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[8]

Bit 28: EXTEVNT8.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[9]

Bit 29: EXTEVNT9.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[10]

Bit 30: EXTEVNT10.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

UPDATE

Bit 31: UPDATE.

Allowed values:
0: NoEffect: Register update event has no effect
1: SetInactive: Register update event forces the output to its inactive state

SET2R

Timerx Output2 Set Register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

Toggle fields

SST

Bit 0: Software Set trigger.

Allowed values:
0: NoEffect: No effect
1: SetActive: Force output to its active state

RESYNC

Bit 1: Timer A resynchronizaton.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetActive: Timer reset event coming solely from software or SYNC input event forces the output to its active state

PER

Bit 2: Timer A Period.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetActive: Timer period event forces the output to its active state

CMP[1]

Bit 3: Timer A compare 1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[2]

Bit 4: Timer A compare 2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[3]

Bit 5: Timer A compare 3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[4]

Bit 6: Timer A compare 4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

MSTPER

Bit 7: Master Period.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetActive: Master timer counter roll-over/reset forces the output to its active state

MSTCMP[1]

Bit 8: Master Compare 1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[2]

Bit 9: Master Compare 2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[3]

Bit 10: Master Compare 3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[4]

Bit 11: Master Compare 4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

TIMACMP2

Bit 12: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMACMP3

Bit 13: Timer A Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMBCMP2

Bit 14: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMBCMP3

Bit 15: Timer B Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMDCMP2

Bit 16: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMDCMP4

Bit 17: Timer D Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMECMP2

Bit 18: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMECMP3

Bit 19: Timer E Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMECMP4

Bit 20: Timer E Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

EXTEVNT[1]

Bit 21: External Event 1.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[2]

Bit 22: External Event 2.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[3]

Bit 23: External Event 3.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[4]

Bit 24: External Event 4.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[5]

Bit 25: External Event 5.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[6]

Bit 26: External Event 6.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[7]

Bit 27: External Event 7.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[8]

Bit 28: External Event 8.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[9]

Bit 29: External Event 9.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[10]

Bit 30: External Event 10.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

UPDATE

Bit 31: Registers update (transfer preload to active).

Allowed values:
0: NoEffect: Register update event has no effect
1: SetActive: Register update event forces the output to its active state

RST2R

Timerx Output2 Reset Register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

Toggle fields

SRT

Bit 0: SRT.

Allowed values:
0: NoEffect: No effect
1: SetInactive: Force output to its inactive state

RESYNC

Bit 1: RESYNC.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetInactive: Timer reset event coming solely from software or SYNC input event forces the output to its inactive state

PER

Bit 2: PER.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetInactive: Timer period event forces the output to its inactive state

CMP[1]

Bit 3: CMP1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[2]

Bit 4: CMP2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[3]

Bit 5: CMP3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[4]

Bit 6: CMP4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

MSTPER

Bit 7: MSTPER.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetInactive: Master timer counter roll-over/reset forces the output to its inactive state

MSTCMP[1]

Bit 8: MSTCMP1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[2]

Bit 9: MSTCMP2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[3]

Bit 10: MSTCMP3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[4]

Bit 11: MSTCMP4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

TIMACMP2

Bit 12: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMACMP3

Bit 13: Timer A Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMBCMP2

Bit 14: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMBCMP3

Bit 15: Timer B Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMDCMP2

Bit 16: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMDCMP4

Bit 17: Timer D Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMECMP2

Bit 18: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMECMP3

Bit 19: Timer E Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMECMP4

Bit 20: Timer E Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

EXTEVNT[1]

Bit 21: EXTEVNT1.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[2]

Bit 22: EXTEVNT2.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[3]

Bit 23: EXTEVNT3.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[4]

Bit 24: EXTEVNT4.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[5]

Bit 25: EXTEVNT5.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[6]

Bit 26: EXTEVNT6.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[7]

Bit 27: EXTEVNT7.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[8]

Bit 28: EXTEVNT8.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[9]

Bit 29: EXTEVNT9.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[10]

Bit 30: EXTEVNT10.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

UPDATE

Bit 31: UPDATE.

Allowed values:
0: NoEffect: Register update event has no effect
1: SetInactive: Register update event forces the output to its inactive state

EEFR1

Timerx External Event Filtering Register 1

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EE[5]FLTR
rw
EE[5]LTCH
rw
EE[4]FLTR
rw
EE[4]LTCH
rw
EE[3]FLTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EE[3]FLTR
rw
EE[3]LTCH
rw
EE[2]FLTR
rw
EE[2]LTCH
rw
EE[1]FLTR
rw
EE[1]LTCH
rw
Toggle fields

EE[1]LTCH

Bit 0: External Event 1 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[1]FLTR

Bits 1-4: External Event 1 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[2]LTCH

Bit 6: External Event 2 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[2]FLTR

Bits 7-10: External Event 2 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[3]LTCH

Bit 12: External Event 3 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[3]FLTR

Bits 13-16: External Event 3 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[4]LTCH

Bit 18: External Event 4 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[4]FLTR

Bits 19-22: External Event 4 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[5]LTCH

Bit 24: External Event 5 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[5]FLTR

Bits 25-28: External Event 5 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EEFR2

Timerx External Event Filtering Register 2

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EE[10]FLTR
rw
EE[10]LTCH
rw
EE[9]FLTR
rw
EE[9]LTCH
rw
EE[8]FLTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EE[8]FLTR
rw
EE[8]LTCH
rw
EE[7]FLTR
rw
EE[7]LTCH
rw
EE[6]FLTR
rw
EE[6]LTCH
rw
Toggle fields

EE[6]LTCH

Bit 0: External Event 6 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[6]FLTR

Bits 1-4: External Event 6 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[7]LTCH

Bit 6: External Event 7 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[7]FLTR

Bits 7-10: External Event 7 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[8]LTCH

Bit 12: External Event 8 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[8]FLTR

Bits 13-16: External Event 8 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[9]LTCH

Bit 18: External Event 9 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[9]FLTR

Bits 19-22: External Event 9 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[10]LTCH

Bit 24: External Event 10 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[10]FLTR

Bits 25-28: External Event 10 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

RSTR

TimerA Reset Register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

30/30 fields covered.

Toggle fields

UPDT

Bit 1: Timer A Update reset.

Allowed values:
0: NoEffect: Update event has no effect
1: ResetCounter: Timer X counter is reset upon update event

CMP2

Bit 2: Timer A compare 2 reset.

Allowed values:
0: NoEffect: Timer X compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer X compare Z event

CMP4

Bit 3: Timer A compare 4 reset.

Allowed values:
0: NoEffect: Timer X compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer X compare Z event

MSTPER

Bit 4: Master timer Period.

Allowed values:
0: NoEffect: Master timer period event has no effect
1: ResetCounter: Timer X counter is reset upon master timer period event

MSTCMP1

Bit 5: Master compare 1.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

MSTCMP2

Bit 6: Master compare 2.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

MSTCMP3

Bit 7: Master compare 3.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

MSTCMP4

Bit 8: Master compare 4.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

EXTEVNT1

Bit 9: External Event 1.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT2

Bit 10: External Event 2.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT3

Bit 11: External Event 3.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT4

Bit 12: External Event 4.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT5

Bit 13: External Event 5.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT6

Bit 14: External Event 6.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT7

Bit 15: External Event 7.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT8

Bit 16: External Event 8.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT9

Bit 17: External Event 9.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT10

Bit 18: External Event 10.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

TIMACMP1

Bit 19: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMACMP2

Bit 20: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMACMP4

Bit 21: Timer A Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMBCMP1

Bit 22: Timer B Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMBCMP2

Bit 23: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMBCMP4

Bit 24: Timer B Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMDCMP1

Bit 25: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMDCMP2

Bit 26: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMDCMP4

Bit 27: Timer D Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMECMP1

Bit 28: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMECMP2

Bit 29: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMECMP4

Bit 30: Timer E Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

CHPR

Timerx Chopper Register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STRTPW
rw
CARDTY
rw
CARFRQ
rw
Toggle fields

CARFRQ

Bits 0-3: Timerx carrier frequency value.

Allowed values: 0x0-0xf

CARDTY

Bits 4-6: Timerx chopper duty cycle value.

Allowed values: 0x0-0x7

STRTPW

Bits 7-10: STRTPW.

Allowed values: 0x0-0xf

CPT1CR

Timerx Capture 2 Control Register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

28/28 fields covered.

Toggle fields

SWCPT

Bit 0: Software Capture.

Allowed values:
0: NoEffect: No effect
1: TriggerCapture: Force capture Z

UPDCPT

Bit 1: Update Capture.

Allowed values:
0: NoEffect: Update event has no effect
1: TriggerCapture: Update event triggers capture Z

EXEV[1]CPT

Bit 2: External Event 1 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[2]CPT

Bit 3: External Event 2 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[3]CPT

Bit 4: External Event 3 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[4]CPT

Bit 5: External Event 4 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[5]CPT

Bit 6: External Event 5 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[6]CPT

Bit 7: External Event 6 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[7]CPT

Bit 8: External Event 7 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[8]CPT

Bit 9: External Event 8 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[9]CPT

Bit 10: External Event 9 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[10]CPT

Bit 11: External Event 10 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

TA1SET

Bit 12: Timer A output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TA1RST

Bit 13: Timer A output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TACMP1

Bit 14: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TACMP2

Bit 15: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TB1SET

Bit 16: Timer B output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TB1RST

Bit 17: Timer B output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TBCMP1

Bit 18: Timer B Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TBCMP2

Bit 19: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TD1SET

Bit 24: Timer D output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TD1RST

Bit 25: Timer D output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TDCMP1

Bit 26: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TDCMP2

Bit 27: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TE1SET

Bit 28: Timer E output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TE1RST

Bit 29: Timer E output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TECMP1

Bit 30: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TECMP2

Bit 31: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

CPT2CR

CPT2xCR

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

28/28 fields covered.

Toggle fields

SWCPT

Bit 0: Software Capture.

Allowed values:
0: NoEffect: No effect
1: TriggerCapture: Force capture Z

UPDCPT

Bit 1: Update Capture.

Allowed values:
0: NoEffect: Update event has no effect
1: TriggerCapture: Update event triggers capture Z

EXEV[1]CPT

Bit 2: External Event 1 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[2]CPT

Bit 3: External Event 2 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[3]CPT

Bit 4: External Event 3 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[4]CPT

Bit 5: External Event 4 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[5]CPT

Bit 6: External Event 5 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[6]CPT

Bit 7: External Event 6 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[7]CPT

Bit 8: External Event 7 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[8]CPT

Bit 9: External Event 8 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[9]CPT

Bit 10: External Event 9 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[10]CPT

Bit 11: External Event 10 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

TA1SET

Bit 12: Timer A output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TA1RST

Bit 13: Timer A output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TACMP1

Bit 14: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TACMP2

Bit 15: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TB1SET

Bit 16: Timer B output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TB1RST

Bit 17: Timer B output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TBCMP1

Bit 18: Timer B Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TBCMP2

Bit 19: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TD1SET

Bit 24: Timer D output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TD1RST

Bit 25: Timer D output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TDCMP1

Bit 26: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TDCMP2

Bit 27: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TE1SET

Bit 28: Timer E output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TE1RST

Bit 29: Timer E output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TECMP1

Bit 30: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TECMP2

Bit 31: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

OUTR

Timerx Output Register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIDL2
rw
CHP2
rw
FAULT2
rw
IDLES2
rw
IDLEM2
rw
POL2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYPRT
rw
DLYPRTEN
rw
DTEN
rw
DIDL1
rw
CHP1
rw
FAULT1
rw
IDLES1
rw
IDLEM1
rw
POL1
rw
Toggle fields

POL1

Bit 1: Output 1 polarity.

Allowed values:
0: ActiveHigh: Positive polarity (output active high)
1: ActiveLow: Negative polarity (output active low)

IDLEM1

Bit 2: Output 1 Idle mode.

Allowed values:
0: NoEffect: No action: the output is not affected by the burst mode operation
1: SetIdle: The output is in idle state when requested by the burst mode controller

IDLES1

Bit 3: Output 1 Idle State.

Allowed values:
0: Inactive: Output idle state is inactive
1: Active: Output idle state is active

FAULT1

Bits 4-5: Output 1 Fault state.

Allowed values:
0: Disabled: No action: the output is not affected by the fault input and stays in run mode
1: SetActive: Output goes to active state after a fault event
2: SetInactive: Output goes to inactive state after a fault event
3: SetHighZ: Output goes to high-z state after a fault event

CHP1

Bit 6: Output 1 Chopper enable.

Allowed values:
0: Disabled: Output signal not altered
1: Enabled: Output signal is chopped by a carrier signal

DIDL1

Bit 7: Output 1 Deadtime upon burst mode Idle entry.

Allowed values:
0: Disabled: The programmed idle state is applied immediately to the output
1: Enabled: Deadtime (inactive level) is inserted on output before entering the idle mode

DTEN

Bit 8: Deadtime enable.

Allowed values:
0: Disabled: Output 1 and 2 signals are independent
1: Enabled: Deadtime is inserted between output 1 and output 2

DLYPRTEN

Bit 9: Delayed Protection Enable.

Allowed values:
0: Disabled: No action
1: Enabled: Delayed protection is enabled, as per DLYPRT bits

DLYPRT

Bits 10-12: Delayed Protection.

Allowed values:
0: Output1_EE6: Output 1 delayed idle on external event 6
1: Output2_EE6: Output 2 delayed idle on external event 6
2: Output1_2_EE6: Output 1 and 2 delayed idle on external event 6
3: Balanced_EE6: Balanced idle on external event 6
4: Output1_EE7: Output 1 delayed idle on external event 7
5: Output2_EE7: Output 2 delayed idle on external event 7
6: Output1_2_EE7: Output 1 and 2 delayed idle on external event 7
7: Balanced_EE7: Balanced idle on external event 7

POL2

Bit 17: Output 2 polarity.

Allowed values:
0: ActiveHigh: Positive polarity (output active high)
1: ActiveLow: Negative polarity (output active low)

IDLEM2

Bit 18: Output 2 Idle mode.

Allowed values:
0: NoEffect: No action: the output is not affected by the burst mode operation
1: SetIdle: The output is in idle state when requested by the burst mode controller

IDLES2

Bit 19: Output 2 Idle State.

Allowed values:
0: Inactive: Output idle state is inactive
1: Active: Output idle state is active

FAULT2

Bits 20-21: Output 2 Fault state.

Allowed values:
0: Disabled: No action: the output is not affected by the fault input and stays in run mode
1: SetActive: Output goes to active state after a fault event
2: SetInactive: Output goes to inactive state after a fault event
3: SetHighZ: Output goes to high-z state after a fault event

CHP2

Bit 22: Output 2 Chopper enable.

Allowed values:
0: Disabled: Output signal not altered
1: Enabled: Output signal is chopped by a carrier signal

DIDL2

Bit 23: Output 2 Deadtime upon burst mode Idle entry.

Allowed values:
0: Disabled: The programmed idle state is applied immediately to the output
1: Enabled: Deadtime (inactive level) is inserted on output before entering the idle mode

FLTR

Timerx Fault Register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLTLCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLT[5]EN
rw
FLT[4]EN
rw
FLT[3]EN
rw
FLT[2]EN
rw
FLT[1]EN
rw
Toggle fields

FLT[1]EN

Bit 0: Fault 1 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[2]EN

Bit 1: Fault 2 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[3]EN

Bit 2: Fault 3 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[4]EN

Bit 3: Fault 4 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[5]EN

Bit 4: Fault 5 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLTLCK

Bit 31: Fault sources Lock.

Allowed values:
0: Unlocked: FLT1EN..FLT5EN bits are read/write
1: Locked: FLT1EN..FLT5EN bits are read only

HRTIM_TIMD

0x40017600: High Resolution Timer: TIMD

357/357 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 ISR
0x8 ICR
0xc DIER
0x10 CNTR
0x14 PERR
0x18 REPR
0x1c CMP1R
0x20 CMP1CR
0x24 CMP2R
0x28 CMP3R
0x2c CMP4R
0x30 CPT1R
0x34 CPT2R
0x38 DTR
0x3c SET1R
0x40 RST1R
0x44 SET2R
0x48 RST2R
0x4c EEFR1
0x50 EEFR2
0x54 RSTR
0x58 CHPR
0x5c CPT1CR
0x60 CPT2CR
0x64 OUTR
0x68 FLTR
Toggle registers

CR

Timerx Control Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPDGAT
rw
PREEN
rw
DACSYNC
rw
MSTU
rw
TEU
rw
TDU
rw
TCU
rw
TBU
rw
TRSTU
rw
TREPU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DELCMP4
rw
DELCMP2
rw
SYNCSTRT
rw
SYNCRST
rw
PSHPLL
rw
HALF
rw
RETRIG
rw
CONT
rw
CKPSC
rw
Toggle fields

CKPSC

Bits 0-2: HRTIM Timer x Clock prescaler.

Allowed values: 0x0-0x7

CONT

Bit 3: Continuous mode.

Allowed values:
0: SingleShot: The timer operates in single-shot mode and stops when it reaches the MPER value
1: Continuous: The timer operates in continuous (free-running) mode and rolls over to zero when it reaches the MPER value

RETRIG

Bit 4: Re-triggerable mode.

Allowed values:
0: Disabled: The timer is not re-triggerable: a counter reset can be done only if the counter is stopped
1: Enabled: The timer is retriggerable: a counter reset is done whatever the counter state

HALF

Bit 5: Half mode enable.

Allowed values:
0: Disabled: Half mode disabled
1: Enabled: Half mode enabled

PSHPLL

Bit 6: Push-Pull mode enable.

Allowed values:
0: Disabled: Push-pull mode disabled
1: Enabled: Push-pull mode enabled

SYNCRST

Bit 10: Synchronization Resets Timer x.

Allowed values:
0: Disabled: No effect on the master timer
1: Reset: A synchroniation input event resets the master timer

SYNCSTRT

Bit 11: Synchronization Starts Timer x.

Allowed values:
0: Disabled: No effect on the master timer
1: Start: A synchroniation input event starts the master timer

DELCMP2

Bits 12-13: Delayed CMP2 mode.

Allowed values:
0: Standard: CMP2 register is always active (standard compare mode)
1: Capture1: CMP2 is recomputed and is active following a capture 1 event
2: Capture1_Compare1: CMP2 is recomputed and is active following a capture 1 event or a Compare 1 match
3: Capture1_Compare3: CMP2 is recomputed and is active following a capture 1 event or a Compare 3 match

DELCMP4

Bits 14-15: Delayed CMP4 mode.

Allowed values:
0: Standard: CMP4 register is always active (standard compare mode)
1: Capture2: CMP4 is recomputed and is active following a capture 2 event
2: Capture2_Compare1: CMP4 is recomputed and is active following a capture 2 event or a Compare 1 match
3: Capture_Compare3: CMP4 is recomputed and is active following a capture event or a Compare 3 match

TREPU

Bit 17: Timer x Repetition update.

Allowed values:
0: Disabled: Update by timer x repetition disabled
1: Enabled: Update by timer x repetition enabled

TRSTU

Bit 18: Timerx reset update.

Allowed values:
0: Disabled: Update by timer x reset/roll-over disabled
1: Enabled: Update by timer x reset/roll-over enabled

TBU

Bit 20: TBU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

TCU

Bit 21: TCU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

TDU

Bit 22: TDU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

TEU

Bit 23: TEU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

MSTU

Bit 24: Master Timer update.

Allowed values:
0: Disabled: Update by master timer disabled
1: Enabled: Update by master timer enabled

DACSYNC

Bits 25-26: AC Synchronization.

Allowed values:
0: Disabled: No DAC trigger generated
1: DACSync1: Trigger generated on DACSync1
2: DACSync2: Trigger generated on DACSync2
3: DACSync3: Trigger generated on DACSync3

PREEN

Bit 27: Preload enable.

Allowed values:
0: Disabled: Preload disabled: the write access is directly done into the active register
1: Enabled: Preload enabled: the write access is done into the preload register

UPDGAT

Bits 28-31: Update Gating.

Allowed values:
0: Independent: Update occurs independently from the DMA burst transfer
1: DMABurst: Update occurs when the DMA burst transfer is completed
2: DMABurst_Update: Update occurs on the update event following DMA burst transfer completion
3: Input1: Update occurs on a rising edge of HRTIM update enable input 1
4: Input2: Update occurs on a rising edge of HRTIM update enable input 2
5: Input3: Update occurs on a rising edge of HRTIM update enable input 3
6: Input1_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 1
7: Input2_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 2
8: Input3_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 3

ISR

Timerx Interrupt Status Register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
O2STAT
r
O1STAT
r
IPPSTAT
r
CPPSTAT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYPRT
r
RST
r
RST2
r
SET[2]
r
RST1
r
SET[1]
r
CPT[2]
r
CPT[1]
r
UPD
r
REP
r
CMP[4]
r
CMP[3]
r
CMP[2]
r
CMP[1]
r
Toggle fields

CMP[1]

Bit 0: Compare 1 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

CMP[2]

Bit 1: Compare 2 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

CMP[3]

Bit 2: Compare 3 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

CMP[4]

Bit 3: Compare 4 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

REP

Bit 4: Repetition Interrupt Flag.

Allowed values:
0: NoEvent: No timer repetition interrupt occurred
1: Event: Timer repetition interrupt occurred

UPD

Bit 6: Update Interrupt Flag.

Allowed values:
0: NoEvent: No timer update interrupt occurred
1: Event: Timer update interrupt occurred

CPT[1]

Bit 7: Capture1 Interrupt Flag.

Allowed values:
0: NoEvent: No timer x capture reset interrupt occurred
1: Event: Timer x capture reset interrupt occurred

CPT[2]

Bit 8: Capture2 Interrupt Flag.

Allowed values:
0: NoEvent: No timer x capture reset interrupt occurred
1: Event: Timer x capture reset interrupt occurred

SET[1]

Bit 9: Output 1 Set Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output set interrupt occurred
1: Event: Tx output set interrupt occurred

RST1

Bit 10: Output 1 Reset Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output reset interrupt occurred
1: Event: Tx output reset interrupt occurred

SET[2]

Bit 11: Output 2 Set Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output set interrupt occurred
1: Event: Tx output set interrupt occurred

RST2

Bit 12: Output 2 Reset Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output reset interrupt occurred
1: Event: Tx output reset interrupt occurred

RST

Bit 13: Reset Interrupt Flag.

Allowed values:
0: NoEvent: No TIMx counter reset/roll-over interrupt occurred
1: Event: TIMx counter reset/roll-over interrupt occurred

DLYPRT

Bit 14: Delayed Protection Flag.

Allowed values:
0: Inactive: Not in delayed idle or balanced idle mode
1: Active: Delayed idle or balanced idle mode entry

CPPSTAT

Bit 16: Current Push Pull Status.

Allowed values:
0: Output1Active: Signal applied on output 1 and output 2 forced inactive
1: Output2Active: Signal applied on output 2 and output 1 forced inactive

IPPSTAT

Bit 17: Idle Push Pull Status.

Allowed values:
0: Output1Active: Protection occurred when the output 1 was active and output 2 forced inactive
1: Output2Active: Protection occurred when the output 2 was active and output 1 forced inactive

O1STAT

Bit 18: Output 1 State.

Allowed values:
0: Inactive: Output was inactive
1: Active: Output was active

O2STAT

Bit 19: Output 2 State.

Allowed values:
0: Inactive: Output was inactive
1: Active: Output was active

ICR

Timerx Interrupt Clear Register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

14/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYPRTC
w1c
RSTC
w1c
RST2C
w1c
SET[2]C
w1c
RST1C
w1c
SET[1]C
w1c
CPT[2]C
w1c
CPT[1]C
w1c
UPDC
w1c
REPC
w1c
CMP[4]C
w1c
CMP[3]C
w1c
CMP[2]C
w1c
CMP[1]C
w1c
Toggle fields

CMP[1]C

Bit 0: Compare 1 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CMP[2]C

Bit 1: Compare 2 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CMP[3]C

Bit 2: Compare 3 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CMP[4]C

Bit 3: Compare 4 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

REPC

Bit 4: Repetition Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

UPDC

Bit 6: Update Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CPT[1]C

Bit 7: Capture1 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CPT[2]C

Bit 8: Capture2 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

SET[1]C

Bit 9: Output 1 Set flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

RST1C

Bit 10: Output 1 Reset flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

SET[2]C

Bit 11: Output 2 Set flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

RST2C

Bit 12: Output 2 Reset flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

RSTC

Bit 13: Reset Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

DLYPRTC

Bit 14: Delayed Protection Flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

DIER

TIMxDIER5

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

28/28 fields covered.

Toggle fields

CMP[1]IE

Bit 0: CMP1IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CMP[2]IE

Bit 1: CMP2IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CMP[3]IE

Bit 2: CMP3IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CMP[4]IE

Bit 3: CMP4IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

REPIE

Bit 4: REPIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

UPDIE

Bit 6: UPDIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CPT[1]IE

Bit 7: CPT1IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CPT[2]IE

Bit 8: CPT2IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

SET[1]IE

Bit 9: Output 1 set interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

RST1IE

Bit 10: RSTx1IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

SET[2]IE

Bit 11: Output 2 set interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

RST2IE

Bit 12: RSTx2IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

RSTIE

Bit 13: RSTIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

DLYPRTIE

Bit 14: DLYPRTIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CMP[1]DE

Bit 16: CMP1DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

CMP[2]DE

Bit 17: CMP2DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

CMP[3]DE

Bit 18: CMP3DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

CMP[4]DE

Bit 19: CMP4DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

REPDE

Bit 20: REPDE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

UPDDE

Bit 22: UPDDE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

CPT[1]DE

Bit 23: CPT1DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

CPT[2]DE

Bit 24: CPT2DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

SET[1]DE

Bit 25: Output 1 set DMA request enable.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

RST1DE

Bit 26: RSTx1DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

SET[2]DE

Bit 27: Output 2 set DMA request enable.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

RST2DE

Bit 28: RSTx2DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

RSTDE

Bit 29: RSTDE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

DLYPRTDE

Bit 30: DLYPRTDE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

CNTR

Timerx Counter Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: Counter value.

Allowed values: 0x0-0xffff

PERR

Timerx Period Register

Offset: 0x14, size: 32, reset: 0x0000FFFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PER
rw
Toggle fields

PER

Bits 0-15: Master Timer Period value.

Allowed values: 0x0-0xffff

REPR

Timerx Repetition Register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Master Timer Repetition counter value.

Allowed values: 0x0-0xff

CMP1R

Timerx Compare 1 Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CMP1CR

Timerx Compare 1 Compound Register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP1
rw
Toggle fields

CMP1

Bits 0-15: Timerx Compare 1 value.

Allowed values: 0x0-0xffff

REP

Bits 16-23: Timerx Repetition value (aliased from HRTIM_REPx register).

Allowed values: 0x0-0xff

CMP2R

Timerx Compare 2 Register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CMP3R

Timerx Compare 3 Register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CMP4R

Timerx Compare 4 Register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CPT1R

Timerx Capture 1 Register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPT
r
Toggle fields

CPT

Bits 0-15: Timerx Capture 1 value.

Allowed values: 0x0-0xffff

CPT2R

Timerx Capture 2 Register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPT
r
Toggle fields

CPT

Bits 0-15: Timerx Capture 1 value.

Allowed values: 0x0-0xffff

DTR

Timerx Deadtime Register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTFLK
rw
DTFSLK
rw
SDTF
rw
DTF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTRLK
rw
DTRSLK
rw
DTPRSC
rw
SDTR
rw
DTR
rw
Toggle fields

DTR

Bits 0-8: Deadtime Rising value.

Allowed values: 0x0-0x1ff

SDTR

Bit 9: Sign Deadtime Rising value.

Allowed values:
0: Positive: Positive deadtime on rising edge
1: Negative: Negative deadtime on rising edge

DTPRSC

Bits 10-12: Deadtime Prescaler.

Allowed values: 0x0-0x7

DTRSLK

Bit 14: Deadtime Rising Sign Lock.

Allowed values:
0: Unlocked: Deadtime rising sign is writable
1: Locked: Deadtime rising sign is read-only

DTRLK

Bit 15: Deadtime Rising Lock.

Allowed values:
0: Unlocked: Deadtime rising value and sign is writable
1: Locked: Deadtime rising value and sign is read-only

DTF

Bits 16-24: Deadtime Falling value.

Allowed values: 0x0-0x1ff

SDTF

Bit 25: Sign Deadtime Falling value.

Allowed values:
0: Positive: Positive deadtime on falling edge
1: Negative: Negative deadtime on falling edge

DTFSLK

Bit 30: Deadtime Falling Sign Lock.

Allowed values:
0: Unlocked: Deadtime falling sign is writable
1: Locked: Deadtime falling sign is read-only

DTFLK

Bit 31: Deadtime Falling Lock.

Allowed values:
0: Unlocked: Deadtime falling value and sign is writable
1: Locked: Deadtime falling value and sign is read-only

SET1R

Timerx Output1 Set Register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

Toggle fields

SST

Bit 0: Software Set trigger.

Allowed values:
0: NoEffect: No effect
1: SetActive: Force output to its active state

RESYNC

Bit 1: Timer A resynchronizaton.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetActive: Timer reset event coming solely from software or SYNC input event forces the output to its active state

PER

Bit 2: Timer A Period.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetActive: Timer period event forces the output to its active state

CMP[1]

Bit 3: Timer A compare 1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[2]

Bit 4: Timer A compare 2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[3]

Bit 5: Timer A compare 3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[4]

Bit 6: Timer A compare 4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

MSTPER

Bit 7: Master Period.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetActive: Master timer counter roll-over/reset forces the output to its active state

MSTCMP[1]

Bit 8: Master Compare 1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[2]

Bit 9: Master Compare 2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[3]

Bit 10: Master Compare 3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[4]

Bit 11: Master Compare 4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

TIMACMP1

Bit 12: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMACMP4

Bit 13: Timer A Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMBCMP2

Bit 14: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMBCMP4

Bit 15: Timer B Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMCCMP1

Bit 16: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMCCMP3

Bit 17: Timer C Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMCCMP4

Bit 18: Timer C Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMECMP1

Bit 19: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMECMP2

Bit 20: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

EXTEVNT[1]

Bit 21: External Event 1.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[2]

Bit 22: External Event 2.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[3]

Bit 23: External Event 3.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[4]

Bit 24: External Event 4.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[5]

Bit 25: External Event 5.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[6]

Bit 26: External Event 6.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[7]

Bit 27: External Event 7.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[8]

Bit 28: External Event 8.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[9]

Bit 29: External Event 9.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[10]

Bit 30: External Event 10.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

UPDATE

Bit 31: Registers update (transfer preload to active).

Allowed values:
0: NoEffect: Register update event has no effect
1: SetActive: Register update event forces the output to its active state

RST1R

Timerx Output1 Reset Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

Toggle fields

SRT

Bit 0: SRT.

Allowed values:
0: NoEffect: No effect
1: SetInactive: Force output to its inactive state

RESYNC

Bit 1: RESYNC.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetInactive: Timer reset event coming solely from software or SYNC input event forces the output to its inactive state

PER

Bit 2: PER.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetInactive: Timer period event forces the output to its inactive state

CMP[1]

Bit 3: CMP1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[2]

Bit 4: CMP2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[3]

Bit 5: CMP3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[4]

Bit 6: CMP4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

MSTPER

Bit 7: MSTPER.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetInactive: Master timer counter roll-over/reset forces the output to its inactive state

MSTCMP[1]

Bit 8: MSTCMP1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[2]

Bit 9: MSTCMP2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[3]

Bit 10: MSTCMP3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[4]

Bit 11: MSTCMP4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

TIMACMP1

Bit 12: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMACMP4

Bit 13: Timer A Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMBCMP2

Bit 14: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMBCMP4

Bit 15: Timer B Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMCCMP1

Bit 16: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMCCMP3

Bit 17: Timer C Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMCCMP4

Bit 18: Timer C Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMECMP1

Bit 19: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMECMP2

Bit 20: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

EXTEVNT[1]

Bit 21: EXTEVNT1.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[2]

Bit 22: EXTEVNT2.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[3]

Bit 23: EXTEVNT3.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[4]

Bit 24: EXTEVNT4.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[5]

Bit 25: EXTEVNT5.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[6]

Bit 26: EXTEVNT6.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[7]

Bit 27: EXTEVNT7.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[8]

Bit 28: EXTEVNT8.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[9]

Bit 29: EXTEVNT9.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[10]

Bit 30: EXTEVNT10.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

UPDATE

Bit 31: UPDATE.

Allowed values:
0: NoEffect: Register update event has no effect
1: SetInactive: Register update event forces the output to its inactive state

SET2R

Timerx Output2 Set Register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

Toggle fields

SST

Bit 0: Software Set trigger.

Allowed values:
0: NoEffect: No effect
1: SetActive: Force output to its active state

RESYNC

Bit 1: Timer A resynchronizaton.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetActive: Timer reset event coming solely from software or SYNC input event forces the output to its active state

PER

Bit 2: Timer A Period.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetActive: Timer period event forces the output to its active state

CMP[1]

Bit 3: Timer A compare 1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[2]

Bit 4: Timer A compare 2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[3]

Bit 5: Timer A compare 3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[4]

Bit 6: Timer A compare 4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

MSTPER

Bit 7: Master Period.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetActive: Master timer counter roll-over/reset forces the output to its active state

MSTCMP[1]

Bit 8: Master Compare 1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[2]

Bit 9: Master Compare 2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[3]

Bit 10: Master Compare 3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[4]

Bit 11: Master Compare 4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

TIMACMP1

Bit 12: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMACMP4

Bit 13: Timer A Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMBCMP2

Bit 14: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMBCMP4

Bit 15: Timer B Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMCCMP1

Bit 16: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMCCMP3

Bit 17: Timer C Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMCCMP4

Bit 18: Timer C Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMECMP1

Bit 19: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMECMP2

Bit 20: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

EXTEVNT[1]

Bit 21: External Event 1.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[2]

Bit 22: External Event 2.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[3]

Bit 23: External Event 3.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[4]

Bit 24: External Event 4.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[5]

Bit 25: External Event 5.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[6]

Bit 26: External Event 6.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[7]

Bit 27: External Event 7.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[8]

Bit 28: External Event 8.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[9]

Bit 29: External Event 9.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[10]

Bit 30: External Event 10.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

UPDATE

Bit 31: Registers update (transfer preload to active).

Allowed values:
0: NoEffect: Register update event has no effect
1: SetActive: Register update event forces the output to its active state

RST2R

Timerx Output2 Reset Register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

Toggle fields

SRT

Bit 0: SRT.

Allowed values:
0: NoEffect: No effect
1: SetInactive: Force output to its inactive state

RESYNC

Bit 1: RESYNC.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetInactive: Timer reset event coming solely from software or SYNC input event forces the output to its inactive state

PER

Bit 2: PER.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetInactive: Timer period event forces the output to its inactive state

CMP[1]

Bit 3: CMP1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[2]

Bit 4: CMP2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[3]

Bit 5: CMP3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[4]

Bit 6: CMP4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

MSTPER

Bit 7: MSTPER.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetInactive: Master timer counter roll-over/reset forces the output to its inactive state

MSTCMP[1]

Bit 8: MSTCMP1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[2]

Bit 9: MSTCMP2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[3]

Bit 10: MSTCMP3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[4]

Bit 11: MSTCMP4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

TIMACMP1

Bit 12: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMACMP4

Bit 13: Timer A Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMBCMP2

Bit 14: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMBCMP4

Bit 15: Timer B Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMCCMP1

Bit 16: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMCCMP3

Bit 17: Timer C Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMCCMP4

Bit 18: Timer C Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMECMP1

Bit 19: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMECMP2

Bit 20: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

EXTEVNT[1]

Bit 21: EXTEVNT1.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[2]

Bit 22: EXTEVNT2.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[3]

Bit 23: EXTEVNT3.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[4]

Bit 24: EXTEVNT4.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[5]

Bit 25: EXTEVNT5.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[6]

Bit 26: EXTEVNT6.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[7]

Bit 27: EXTEVNT7.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[8]

Bit 28: EXTEVNT8.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[9]

Bit 29: EXTEVNT9.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[10]

Bit 30: EXTEVNT10.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

UPDATE

Bit 31: UPDATE.

Allowed values:
0: NoEffect: Register update event has no effect
1: SetInactive: Register update event forces the output to its inactive state

EEFR1

Timerx External Event Filtering Register 1

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EE[5]FLTR
rw
EE[5]LTCH
rw
EE[4]FLTR
rw
EE[4]LTCH
rw
EE[3]FLTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EE[3]FLTR
rw
EE[3]LTCH
rw
EE[2]FLTR
rw
EE[2]LTCH
rw
EE[1]FLTR
rw
EE[1]LTCH
rw
Toggle fields

EE[1]LTCH

Bit 0: External Event 1 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[1]FLTR

Bits 1-4: External Event 1 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[2]LTCH

Bit 6: External Event 2 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[2]FLTR

Bits 7-10: External Event 2 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[3]LTCH

Bit 12: External Event 3 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[3]FLTR

Bits 13-16: External Event 3 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[4]LTCH

Bit 18: External Event 4 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[4]FLTR

Bits 19-22: External Event 4 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[5]LTCH

Bit 24: External Event 5 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[5]FLTR

Bits 25-28: External Event 5 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EEFR2

Timerx External Event Filtering Register 2

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EE[10]FLTR
rw
EE[10]LTCH
rw
EE[9]FLTR
rw
EE[9]LTCH
rw
EE[8]FLTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EE[8]FLTR
rw
EE[8]LTCH
rw
EE[7]FLTR
rw
EE[7]LTCH
rw
EE[6]FLTR
rw
EE[6]LTCH
rw
Toggle fields

EE[6]LTCH

Bit 0: External Event 6 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[6]FLTR

Bits 1-4: External Event 6 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[7]LTCH

Bit 6: External Event 7 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[7]FLTR

Bits 7-10: External Event 7 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[8]LTCH

Bit 12: External Event 8 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[8]FLTR

Bits 13-16: External Event 8 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[9]LTCH

Bit 18: External Event 9 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[9]FLTR

Bits 19-22: External Event 9 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[10]LTCH

Bit 24: External Event 10 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[10]FLTR

Bits 25-28: External Event 10 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

RSTR

TimerA Reset Register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

30/30 fields covered.

Toggle fields

UPDT

Bit 1: Timer A Update reset.

Allowed values:
0: NoEffect: Update event has no effect
1: ResetCounter: Timer X counter is reset upon update event

CMP2

Bit 2: Timer A compare 2 reset.

Allowed values:
0: NoEffect: Timer X compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer X compare Z event

CMP4

Bit 3: Timer A compare 4 reset.

Allowed values:
0: NoEffect: Timer X compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer X compare Z event

MSTPER

Bit 4: Master timer Period.

Allowed values:
0: NoEffect: Master timer period event has no effect
1: ResetCounter: Timer X counter is reset upon master timer period event

MSTCMP1

Bit 5: Master compare 1.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

MSTCMP2

Bit 6: Master compare 2.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

MSTCMP3

Bit 7: Master compare 3.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

MSTCMP4

Bit 8: Master compare 4.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

EXTEVNT1

Bit 9: External Event 1.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT2

Bit 10: External Event 2.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT3

Bit 11: External Event 3.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT4

Bit 12: External Event 4.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT5

Bit 13: External Event 5.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT6

Bit 14: External Event 6.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT7

Bit 15: External Event 7.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT8

Bit 16: External Event 8.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT9

Bit 17: External Event 9.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT10

Bit 18: External Event 10.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

TIMACMP1

Bit 19: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMACMP2

Bit 20: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMACMP4

Bit 21: Timer A Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMBCMP1

Bit 22: Timer B Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMBCMP2

Bit 23: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMBCMP4

Bit 24: Timer B Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMCCMP1

Bit 25: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMCCMP2

Bit 26: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMCCMP4

Bit 27: Timer C Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMECMP1

Bit 28: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMECMP2

Bit 29: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMECMP4

Bit 30: Timer E Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

CHPR

Timerx Chopper Register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STRTPW
rw
CARDTY
rw
CARFRQ
rw
Toggle fields

CARFRQ

Bits 0-3: Timerx carrier frequency value.

Allowed values: 0x0-0xf

CARDTY

Bits 4-6: Timerx chopper duty cycle value.

Allowed values: 0x0-0x7

STRTPW

Bits 7-10: STRTPW.

Allowed values: 0x0-0xf

CPT1CR

Timerx Capture 2 Control Register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

28/28 fields covered.

Toggle fields

SWCPT

Bit 0: Software Capture.

Allowed values:
0: NoEffect: No effect
1: TriggerCapture: Force capture Z

UPDCPT

Bit 1: Update Capture.

Allowed values:
0: NoEffect: Update event has no effect
1: TriggerCapture: Update event triggers capture Z

EXEV[1]CPT

Bit 2: External Event 1 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[2]CPT

Bit 3: External Event 2 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[3]CPT

Bit 4: External Event 3 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[4]CPT

Bit 5: External Event 4 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[5]CPT

Bit 6: External Event 5 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[6]CPT

Bit 7: External Event 6 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[7]CPT

Bit 8: External Event 7 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[8]CPT

Bit 9: External Event 8 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[9]CPT

Bit 10: External Event 9 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[10]CPT

Bit 11: External Event 10 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

TA1SET

Bit 12: Timer A output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TA1RST

Bit 13: Timer A output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TACMP1

Bit 14: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TACMP2

Bit 15: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TB1SET

Bit 16: Timer B output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TB1RST

Bit 17: Timer B output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TBCMP1

Bit 18: Timer B Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TBCMP2

Bit 19: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TC1SET

Bit 20: Timer C output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TC1RST

Bit 21: Timer C output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TCCMP1

Bit 22: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TCCMP2

Bit 23: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TE1SET

Bit 28: Timer E output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TE1RST

Bit 29: Timer E output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TECMP1

Bit 30: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TECMP2

Bit 31: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

CPT2CR

CPT2xCR

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

28/28 fields covered.

Toggle fields

SWCPT

Bit 0: Software Capture.

Allowed values:
0: NoEffect: No effect
1: TriggerCapture: Force capture Z

UPDCPT

Bit 1: Update Capture.

Allowed values:
0: NoEffect: Update event has no effect
1: TriggerCapture: Update event triggers capture Z

EXEV[1]CPT

Bit 2: External Event 1 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[2]CPT

Bit 3: External Event 2 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[3]CPT

Bit 4: External Event 3 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[4]CPT

Bit 5: External Event 4 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[5]CPT

Bit 6: External Event 5 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[6]CPT

Bit 7: External Event 6 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[7]CPT

Bit 8: External Event 7 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[8]CPT

Bit 9: External Event 8 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[9]CPT

Bit 10: External Event 9 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[10]CPT

Bit 11: External Event 10 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

TA1SET

Bit 12: Timer A output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TA1RST

Bit 13: Timer A output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TACMP1

Bit 14: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TACMP2

Bit 15: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TB1SET

Bit 16: Timer B output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TB1RST

Bit 17: Timer B output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TBCMP1

Bit 18: Timer B Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TBCMP2

Bit 19: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TC1SET

Bit 20: Timer C output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TC1RST

Bit 21: Timer C output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TCCMP1

Bit 22: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TCCMP2

Bit 23: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TE1SET

Bit 28: Timer E output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TE1RST

Bit 29: Timer E output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TECMP1

Bit 30: Timer E Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TECMP2

Bit 31: Timer E Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

OUTR

Timerx Output Register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIDL2
rw
CHP2
rw
FAULT2
rw
IDLES2
rw
IDLEM2
rw
POL2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYPRT
rw
DLYPRTEN
rw
DTEN
rw
DIDL1
rw
CHP1
rw
FAULT1
rw
IDLES1
rw
IDLEM1
rw
POL1
rw
Toggle fields

POL1

Bit 1: Output 1 polarity.

Allowed values:
0: ActiveHigh: Positive polarity (output active high)
1: ActiveLow: Negative polarity (output active low)

IDLEM1

Bit 2: Output 1 Idle mode.

Allowed values:
0: NoEffect: No action: the output is not affected by the burst mode operation
1: SetIdle: The output is in idle state when requested by the burst mode controller

IDLES1

Bit 3: Output 1 Idle State.

Allowed values:
0: Inactive: Output idle state is inactive
1: Active: Output idle state is active

FAULT1

Bits 4-5: Output 1 Fault state.

Allowed values:
0: Disabled: No action: the output is not affected by the fault input and stays in run mode
1: SetActive: Output goes to active state after a fault event
2: SetInactive: Output goes to inactive state after a fault event
3: SetHighZ: Output goes to high-z state after a fault event

CHP1

Bit 6: Output 1 Chopper enable.

Allowed values:
0: Disabled: Output signal not altered
1: Enabled: Output signal is chopped by a carrier signal

DIDL1

Bit 7: Output 1 Deadtime upon burst mode Idle entry.

Allowed values:
0: Disabled: The programmed idle state is applied immediately to the output
1: Enabled: Deadtime (inactive level) is inserted on output before entering the idle mode

DTEN

Bit 8: Deadtime enable.

Allowed values:
0: Disabled: Output 1 and 2 signals are independent
1: Enabled: Deadtime is inserted between output 1 and output 2

DLYPRTEN

Bit 9: Delayed Protection Enable.

Allowed values:
0: Disabled: No action
1: Enabled: Delayed protection is enabled, as per DLYPRT bits

DLYPRT

Bits 10-12: Delayed Protection.

Allowed values:
0: Output1_EE6: Output 1 delayed idle on external event 6
1: Output2_EE6: Output 2 delayed idle on external event 6
2: Output1_2_EE6: Output 1 and 2 delayed idle on external event 6
3: Balanced_EE6: Balanced idle on external event 6
4: Output1_EE7: Output 1 delayed idle on external event 7
5: Output2_EE7: Output 2 delayed idle on external event 7
6: Output1_2_EE7: Output 1 and 2 delayed idle on external event 7
7: Balanced_EE7: Balanced idle on external event 7

POL2

Bit 17: Output 2 polarity.

Allowed values:
0: ActiveHigh: Positive polarity (output active high)
1: ActiveLow: Negative polarity (output active low)

IDLEM2

Bit 18: Output 2 Idle mode.

Allowed values:
0: NoEffect: No action: the output is not affected by the burst mode operation
1: SetIdle: The output is in idle state when requested by the burst mode controller

IDLES2

Bit 19: Output 2 Idle State.

Allowed values:
0: Inactive: Output idle state is inactive
1: Active: Output idle state is active

FAULT2

Bits 20-21: Output 2 Fault state.

Allowed values:
0: Disabled: No action: the output is not affected by the fault input and stays in run mode
1: SetActive: Output goes to active state after a fault event
2: SetInactive: Output goes to inactive state after a fault event
3: SetHighZ: Output goes to high-z state after a fault event

CHP2

Bit 22: Output 2 Chopper enable.

Allowed values:
0: Disabled: Output signal not altered
1: Enabled: Output signal is chopped by a carrier signal

DIDL2

Bit 23: Output 2 Deadtime upon burst mode Idle entry.

Allowed values:
0: Disabled: The programmed idle state is applied immediately to the output
1: Enabled: Deadtime (inactive level) is inserted on output before entering the idle mode

FLTR

Timerx Fault Register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLTLCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLT[5]EN
rw
FLT[4]EN
rw
FLT[3]EN
rw
FLT[2]EN
rw
FLT[1]EN
rw
Toggle fields

FLT[1]EN

Bit 0: Fault 1 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[2]EN

Bit 1: Fault 2 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[3]EN

Bit 2: Fault 3 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[4]EN

Bit 3: Fault 4 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[5]EN

Bit 4: Fault 5 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLTLCK

Bit 31: Fault sources Lock.

Allowed values:
0: Unlocked: FLT1EN..FLT5EN bits are read/write
1: Locked: FLT1EN..FLT5EN bits are read only

HRTIM_TIME

0x40017680: High Resolution Timer: TIME

357/357 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 ISR
0x8 ICR
0xc DIER
0x10 CNTR
0x14 PERR
0x18 REPR
0x1c CMP1R
0x20 CMP1CR
0x24 CMP2R
0x28 CMP3R
0x2c CMP4R
0x30 CPT1R
0x34 CPT2R
0x38 DTR
0x3c SET1R
0x40 RST1R
0x44 SET2R
0x48 RST2R
0x4c EEFR1
0x50 EEFR2
0x54 RSTR
0x58 CHPR
0x5c CPT1CR
0x60 CPT2CR
0x64 OUTR
0x68 FLTR
Toggle registers

CR

Timerx Control Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPDGAT
rw
PREEN
rw
DACSYNC
rw
MSTU
rw
TEU
rw
TDU
rw
TCU
rw
TBU
rw
TRSTU
rw
TREPU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DELCMP4
rw
DELCMP2
rw
SYNCSTRT
rw
SYNCRST
rw
PSHPLL
rw
HALF
rw
RETRIG
rw
CONT
rw
CKPSC
rw
Toggle fields

CKPSC

Bits 0-2: HRTIM Timer x Clock prescaler.

Allowed values: 0x0-0x7

CONT

Bit 3: Continuous mode.

Allowed values:
0: SingleShot: The timer operates in single-shot mode and stops when it reaches the MPER value
1: Continuous: The timer operates in continuous (free-running) mode and rolls over to zero when it reaches the MPER value

RETRIG

Bit 4: Re-triggerable mode.

Allowed values:
0: Disabled: The timer is not re-triggerable: a counter reset can be done only if the counter is stopped
1: Enabled: The timer is retriggerable: a counter reset is done whatever the counter state

HALF

Bit 5: Half mode enable.

Allowed values:
0: Disabled: Half mode disabled
1: Enabled: Half mode enabled

PSHPLL

Bit 6: Push-Pull mode enable.

Allowed values:
0: Disabled: Push-pull mode disabled
1: Enabled: Push-pull mode enabled

SYNCRST

Bit 10: Synchronization Resets Timer x.

Allowed values:
0: Disabled: No effect on the master timer
1: Reset: A synchroniation input event resets the master timer

SYNCSTRT

Bit 11: Synchronization Starts Timer x.

Allowed values:
0: Disabled: No effect on the master timer
1: Start: A synchroniation input event starts the master timer

DELCMP2

Bits 12-13: Delayed CMP2 mode.

Allowed values:
0: Standard: CMP2 register is always active (standard compare mode)
1: Capture1: CMP2 is recomputed and is active following a capture 1 event
2: Capture1_Compare1: CMP2 is recomputed and is active following a capture 1 event or a Compare 1 match
3: Capture1_Compare3: CMP2 is recomputed and is active following a capture 1 event or a Compare 3 match

DELCMP4

Bits 14-15: Delayed CMP4 mode.

Allowed values:
0: Standard: CMP4 register is always active (standard compare mode)
1: Capture2: CMP4 is recomputed and is active following a capture 2 event
2: Capture2_Compare1: CMP4 is recomputed and is active following a capture 2 event or a Compare 1 match
3: Capture_Compare3: CMP4 is recomputed and is active following a capture event or a Compare 3 match

TREPU

Bit 17: Timer x Repetition update.

Allowed values:
0: Disabled: Update by timer x repetition disabled
1: Enabled: Update by timer x repetition enabled

TRSTU

Bit 18: Timerx reset update.

Allowed values:
0: Disabled: Update by timer x reset/roll-over disabled
1: Enabled: Update by timer x reset/roll-over enabled

TBU

Bit 20: TBU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

TCU

Bit 21: TCU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

TDU

Bit 22: TDU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

TEU

Bit 23: TEU.

Allowed values:
0: Disabled: Update by timer x disabled
1: Enabled: Update by timer x enabled

MSTU

Bit 24: Master Timer update.

Allowed values:
0: Disabled: Update by master timer disabled
1: Enabled: Update by master timer enabled

DACSYNC

Bits 25-26: AC Synchronization.

Allowed values:
0: Disabled: No DAC trigger generated
1: DACSync1: Trigger generated on DACSync1
2: DACSync2: Trigger generated on DACSync2
3: DACSync3: Trigger generated on DACSync3

PREEN

Bit 27: Preload enable.

Allowed values:
0: Disabled: Preload disabled: the write access is directly done into the active register
1: Enabled: Preload enabled: the write access is done into the preload register

UPDGAT

Bits 28-31: Update Gating.

Allowed values:
0: Independent: Update occurs independently from the DMA burst transfer
1: DMABurst: Update occurs when the DMA burst transfer is completed
2: DMABurst_Update: Update occurs on the update event following DMA burst transfer completion
3: Input1: Update occurs on a rising edge of HRTIM update enable input 1
4: Input2: Update occurs on a rising edge of HRTIM update enable input 2
5: Input3: Update occurs on a rising edge of HRTIM update enable input 3
6: Input1_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 1
7: Input2_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 2
8: Input3_Update: Update occurs on the update event following a rising edge of HRTIM update enable input 3

ISR

Timerx Interrupt Status Register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
O2STAT
r
O1STAT
r
IPPSTAT
r
CPPSTAT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYPRT
r
RST
r
RST2
r
SET[2]
r
RST1
r
SET[1]
r
CPT[2]
r
CPT[1]
r
UPD
r
REP
r
CMP[4]
r
CMP[3]
r
CMP[2]
r
CMP[1]
r
Toggle fields

CMP[1]

Bit 0: Compare 1 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

CMP[2]

Bit 1: Compare 2 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

CMP[3]

Bit 2: Compare 3 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

CMP[4]

Bit 3: Compare 4 Interrupt Flag.

Allowed values:
0: NoEvent: No compare interrupt occurred
1: Event: Compare interrupt occurred

REP

Bit 4: Repetition Interrupt Flag.

Allowed values:
0: NoEvent: No timer repetition interrupt occurred
1: Event: Timer repetition interrupt occurred

UPD

Bit 6: Update Interrupt Flag.

Allowed values:
0: NoEvent: No timer update interrupt occurred
1: Event: Timer update interrupt occurred

CPT[1]

Bit 7: Capture1 Interrupt Flag.

Allowed values:
0: NoEvent: No timer x capture reset interrupt occurred
1: Event: Timer x capture reset interrupt occurred

CPT[2]

Bit 8: Capture2 Interrupt Flag.

Allowed values:
0: NoEvent: No timer x capture reset interrupt occurred
1: Event: Timer x capture reset interrupt occurred

SET[1]

Bit 9: Output 1 Set Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output set interrupt occurred
1: Event: Tx output set interrupt occurred

RST1

Bit 10: Output 1 Reset Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output reset interrupt occurred
1: Event: Tx output reset interrupt occurred

SET[2]

Bit 11: Output 2 Set Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output set interrupt occurred
1: Event: Tx output set interrupt occurred

RST2

Bit 12: Output 2 Reset Interrupt Flag.

Allowed values:
0: NoEvent: No Tx output reset interrupt occurred
1: Event: Tx output reset interrupt occurred

RST

Bit 13: Reset Interrupt Flag.

Allowed values:
0: NoEvent: No TIMx counter reset/roll-over interrupt occurred
1: Event: TIMx counter reset/roll-over interrupt occurred

DLYPRT

Bit 14: Delayed Protection Flag.

Allowed values:
0: Inactive: Not in delayed idle or balanced idle mode
1: Active: Delayed idle or balanced idle mode entry

CPPSTAT

Bit 16: Current Push Pull Status.

Allowed values:
0: Output1Active: Signal applied on output 1 and output 2 forced inactive
1: Output2Active: Signal applied on output 2 and output 1 forced inactive

IPPSTAT

Bit 17: Idle Push Pull Status.

Allowed values:
0: Output1Active: Protection occurred when the output 1 was active and output 2 forced inactive
1: Output2Active: Protection occurred when the output 2 was active and output 1 forced inactive

O1STAT

Bit 18: Output 1 State.

Allowed values:
0: Inactive: Output was inactive
1: Active: Output was active

O2STAT

Bit 19: Output 2 State.

Allowed values:
0: Inactive: Output was inactive
1: Active: Output was active

ICR

Timerx Interrupt Clear Register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

14/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYPRTC
w1c
RSTC
w1c
RST2C
w1c
SET[2]C
w1c
RST1C
w1c
SET[1]C
w1c
CPT[2]C
w1c
CPT[1]C
w1c
UPDC
w1c
REPC
w1c
CMP[4]C
w1c
CMP[3]C
w1c
CMP[2]C
w1c
CMP[1]C
w1c
Toggle fields

CMP[1]C

Bit 0: Compare 1 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CMP[2]C

Bit 1: Compare 2 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CMP[3]C

Bit 2: Compare 3 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CMP[4]C

Bit 3: Compare 4 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

REPC

Bit 4: Repetition Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

UPDC

Bit 6: Update Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CPT[1]C

Bit 7: Capture1 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

CPT[2]C

Bit 8: Capture2 Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

SET[1]C

Bit 9: Output 1 Set flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

RST1C

Bit 10: Output 1 Reset flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

SET[2]C

Bit 11: Output 2 Set flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

RST2C

Bit 12: Output 2 Reset flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

RSTC

Bit 13: Reset Interrupt flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

DLYPRTC

Bit 14: Delayed Protection Flag Clear.

Allowed values:
1: Clear: Clears associated flag in ISR register

DIER

TIMxDIER5

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

28/28 fields covered.

Toggle fields

CMP[1]IE

Bit 0: CMP1IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CMP[2]IE

Bit 1: CMP2IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CMP[3]IE

Bit 2: CMP3IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CMP[4]IE

Bit 3: CMP4IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

REPIE

Bit 4: REPIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

UPDIE

Bit 6: UPDIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CPT[1]IE

Bit 7: CPT1IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CPT[2]IE

Bit 8: CPT2IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

SET[1]IE

Bit 9: Output 1 set interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

RST1IE

Bit 10: RSTx1IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

SET[2]IE

Bit 11: Output 2 set interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

RST2IE

Bit 12: RSTx2IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

RSTIE

Bit 13: RSTIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

DLYPRTIE

Bit 14: DLYPRTIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CMP[1]DE

Bit 16: CMP1DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

CMP[2]DE

Bit 17: CMP2DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

CMP[3]DE

Bit 18: CMP3DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

CMP[4]DE

Bit 19: CMP4DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

REPDE

Bit 20: REPDE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

UPDDE

Bit 22: UPDDE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

CPT[1]DE

Bit 23: CPT1DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

CPT[2]DE

Bit 24: CPT2DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

SET[1]DE

Bit 25: Output 1 set DMA request enable.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

RST1DE

Bit 26: RSTx1DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

SET[2]DE

Bit 27: Output 2 set DMA request enable.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

RST2DE

Bit 28: RSTx2DE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

RSTDE

Bit 29: RSTDE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

DLYPRTDE

Bit 30: DLYPRTDE.

Allowed values:
0: Disabled: DMA request disabled
1: Enabled: DMA request enabled

CNTR

Timerx Counter Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: Counter value.

Allowed values: 0x0-0xffff

PERR

Timerx Period Register

Offset: 0x14, size: 32, reset: 0x0000FFFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PER
rw
Toggle fields

PER

Bits 0-15: Master Timer Period value.

Allowed values: 0x0-0xffff

REPR

Timerx Repetition Register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Master Timer Repetition counter value.

Allowed values: 0x0-0xff

CMP1R

Timerx Compare 1 Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CMP1CR

Timerx Compare 1 Compound Register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP1
rw
Toggle fields

CMP1

Bits 0-15: Timerx Compare 1 value.

Allowed values: 0x0-0xffff

REP

Bits 16-23: Timerx Repetition value (aliased from HRTIM_REPx register).

Allowed values: 0x0-0xff

CMP2R

Timerx Compare 2 Register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CMP3R

Timerx Compare 3 Register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CMP4R

Timerx Compare 4 Register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Master Timer Compare 1 value.

Allowed values: 0x0-0xffff

CPT1R

Timerx Capture 1 Register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPT
r
Toggle fields

CPT

Bits 0-15: Timerx Capture 1 value.

Allowed values: 0x0-0xffff

CPT2R

Timerx Capture 2 Register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPT
r
Toggle fields

CPT

Bits 0-15: Timerx Capture 1 value.

Allowed values: 0x0-0xffff

DTR

Timerx Deadtime Register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTFLK
rw
DTFSLK
rw
SDTF
rw
DTF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTRLK
rw
DTRSLK
rw
DTPRSC
rw
SDTR
rw
DTR
rw
Toggle fields

DTR

Bits 0-8: Deadtime Rising value.

Allowed values: 0x0-0x1ff

SDTR

Bit 9: Sign Deadtime Rising value.

Allowed values:
0: Positive: Positive deadtime on rising edge
1: Negative: Negative deadtime on rising edge

DTPRSC

Bits 10-12: Deadtime Prescaler.

Allowed values: 0x0-0x7

DTRSLK

Bit 14: Deadtime Rising Sign Lock.

Allowed values:
0: Unlocked: Deadtime rising sign is writable
1: Locked: Deadtime rising sign is read-only

DTRLK

Bit 15: Deadtime Rising Lock.

Allowed values:
0: Unlocked: Deadtime rising value and sign is writable
1: Locked: Deadtime rising value and sign is read-only

DTF

Bits 16-24: Deadtime Falling value.

Allowed values: 0x0-0x1ff

SDTF

Bit 25: Sign Deadtime Falling value.

Allowed values:
0: Positive: Positive deadtime on falling edge
1: Negative: Negative deadtime on falling edge

DTFSLK

Bit 30: Deadtime Falling Sign Lock.

Allowed values:
0: Unlocked: Deadtime falling sign is writable
1: Locked: Deadtime falling sign is read-only

DTFLK

Bit 31: Deadtime Falling Lock.

Allowed values:
0: Unlocked: Deadtime falling value and sign is writable
1: Locked: Deadtime falling value and sign is read-only

SET1R

Timerx Output1 Set Register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

Toggle fields

SST

Bit 0: Software Set trigger.

Allowed values:
0: NoEffect: No effect
1: SetActive: Force output to its active state

RESYNC

Bit 1: Timer A resynchronizaton.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetActive: Timer reset event coming solely from software or SYNC input event forces the output to its active state

PER

Bit 2: Timer A Period.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetActive: Timer period event forces the output to its active state

CMP[1]

Bit 3: Timer A compare 1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[2]

Bit 4: Timer A compare 2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[3]

Bit 5: Timer A compare 3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[4]

Bit 6: Timer A compare 4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

MSTPER

Bit 7: Master Period.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetActive: Master timer counter roll-over/reset forces the output to its active state

MSTCMP[1]

Bit 8: Master Compare 1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[2]

Bit 9: Master Compare 2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[3]

Bit 10: Master Compare 3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[4]

Bit 11: Master Compare 4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

TIMACMP3

Bit 12: Timer A Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMACMP4

Bit 13: Timer A Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMBCMP3

Bit 14: Timer B Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMBCMP4

Bit 15: Timer B Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMCCMP1

Bit 16: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMCCMP2

Bit 17: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMDCMP1

Bit 18: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMDCMP2

Bit 19: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMDCMP4

Bit 20: Timer D Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

EXTEVNT[1]

Bit 21: External Event 1.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[2]

Bit 22: External Event 2.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[3]

Bit 23: External Event 3.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[4]

Bit 24: External Event 4.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[5]

Bit 25: External Event 5.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[6]

Bit 26: External Event 6.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[7]

Bit 27: External Event 7.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[8]

Bit 28: External Event 8.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[9]

Bit 29: External Event 9.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[10]

Bit 30: External Event 10.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

UPDATE

Bit 31: Registers update (transfer preload to active).

Allowed values:
0: NoEffect: Register update event has no effect
1: SetActive: Register update event forces the output to its active state

RST1R

Timerx Output1 Reset Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

Toggle fields

SRT

Bit 0: SRT.

Allowed values:
0: NoEffect: No effect
1: SetInactive: Force output to its inactive state

RESYNC

Bit 1: RESYNC.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetInactive: Timer reset event coming solely from software or SYNC input event forces the output to its inactive state

PER

Bit 2: PER.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetInactive: Timer period event forces the output to its inactive state

CMP[1]

Bit 3: CMP1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[2]

Bit 4: CMP2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[3]

Bit 5: CMP3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[4]

Bit 6: CMP4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

MSTPER

Bit 7: MSTPER.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetInactive: Master timer counter roll-over/reset forces the output to its inactive state

MSTCMP[1]

Bit 8: MSTCMP1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[2]

Bit 9: MSTCMP2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[3]

Bit 10: MSTCMP3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[4]

Bit 11: MSTCMP4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

TIMACMP3

Bit 12: Timer A Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMACMP4

Bit 13: Timer A Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMBCMP3

Bit 14: Timer B Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMBCMP4

Bit 15: Timer B Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMCCMP1

Bit 16: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMCCMP2

Bit 17: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMDCMP1

Bit 18: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMDCMP2

Bit 19: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMDCMP4

Bit 20: Timer D Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

EXTEVNT[1]

Bit 21: EXTEVNT1.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[2]

Bit 22: EXTEVNT2.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[3]

Bit 23: EXTEVNT3.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[4]

Bit 24: EXTEVNT4.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[5]

Bit 25: EXTEVNT5.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[6]

Bit 26: EXTEVNT6.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[7]

Bit 27: EXTEVNT7.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[8]

Bit 28: EXTEVNT8.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[9]

Bit 29: EXTEVNT9.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[10]

Bit 30: EXTEVNT10.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

UPDATE

Bit 31: UPDATE.

Allowed values:
0: NoEffect: Register update event has no effect
1: SetInactive: Register update event forces the output to its inactive state

SET2R

Timerx Output2 Set Register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

Toggle fields

SST

Bit 0: Software Set trigger.

Allowed values:
0: NoEffect: No effect
1: SetActive: Force output to its active state

RESYNC

Bit 1: Timer A resynchronizaton.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetActive: Timer reset event coming solely from software or SYNC input event forces the output to its active state

PER

Bit 2: Timer A Period.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetActive: Timer period event forces the output to its active state

CMP[1]

Bit 3: Timer A compare 1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[2]

Bit 4: Timer A compare 2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[3]

Bit 5: Timer A compare 3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

CMP[4]

Bit 6: Timer A compare 4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetActive: Timer compare event forces the output to its active state

MSTPER

Bit 7: Master Period.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetActive: Master timer counter roll-over/reset forces the output to its active state

MSTCMP[1]

Bit 8: Master Compare 1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[2]

Bit 9: Master Compare 2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[3]

Bit 10: Master Compare 3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

MSTCMP[4]

Bit 11: Master Compare 4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetActive: Master timer compare event forces the output to its active state

TIMACMP3

Bit 12: Timer A Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMACMP4

Bit 13: Timer A Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMBCMP3

Bit 14: Timer B Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMBCMP4

Bit 15: Timer B Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMCCMP1

Bit 16: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMCCMP2

Bit 17: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMDCMP1

Bit 18: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMDCMP2

Bit 19: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

TIMDCMP4

Bit 20: Timer D Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetActive: Timer event forces the output to its active state

EXTEVNT[1]

Bit 21: External Event 1.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[2]

Bit 22: External Event 2.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[3]

Bit 23: External Event 3.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[4]

Bit 24: External Event 4.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[5]

Bit 25: External Event 5.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[6]

Bit 26: External Event 6.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[7]

Bit 27: External Event 7.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[8]

Bit 28: External Event 8.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[9]

Bit 29: External Event 9.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

EXTEVNT[10]

Bit 30: External Event 10.

Allowed values:
0: NoEffect: External event has no effect
1: SetActive: External event forces the output to its active state

UPDATE

Bit 31: Registers update (transfer preload to active).

Allowed values:
0: NoEffect: Register update event has no effect
1: SetActive: Register update event forces the output to its active state

RST2R

Timerx Output2 Reset Register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

Toggle fields

SRT

Bit 0: SRT.

Allowed values:
0: NoEffect: No effect
1: SetInactive: Force output to its inactive state

RESYNC

Bit 1: RESYNC.

Allowed values:
0: NoEffect: Timer reset event coming solely from software or SYNC input event has no effect
1: SetInactive: Timer reset event coming solely from software or SYNC input event forces the output to its inactive state

PER

Bit 2: PER.

Allowed values:
0: NoEffect: Timer period event has no effect
1: SetInactive: Timer period event forces the output to its inactive state

CMP[1]

Bit 3: CMP1.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[2]

Bit 4: CMP2.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[3]

Bit 5: CMP3.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

CMP[4]

Bit 6: CMP4.

Allowed values:
0: NoEffect: Timer compare event has no effect
1: SetInactive: Timer compare event forces the output to its inactive state

MSTPER

Bit 7: MSTPER.

Allowed values:
0: NoEffect: Master timer counter roll-over/reset has no effect
1: SetInactive: Master timer counter roll-over/reset forces the output to its inactive state

MSTCMP[1]

Bit 8: MSTCMP1.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[2]

Bit 9: MSTCMP2.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[3]

Bit 10: MSTCMP3.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

MSTCMP[4]

Bit 11: MSTCMP4.

Allowed values:
0: NoEffect: Master timer compare event has no effect
1: SetInactive: Master timer compare event forces the output to its inactive state

TIMACMP3

Bit 12: Timer A Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMACMP4

Bit 13: Timer A Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMBCMP3

Bit 14: Timer B Compare 3.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMBCMP4

Bit 15: Timer B Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMCCMP1

Bit 16: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMCCMP2

Bit 17: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMDCMP1

Bit 18: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMDCMP2

Bit 19: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

TIMDCMP4

Bit 20: Timer D Compare 4.

Allowed values:
0: NoEffect: Timer event has no effect
1: SetInactive: Timer event forces the output to its inactive state

EXTEVNT[1]

Bit 21: EXTEVNT1.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[2]

Bit 22: EXTEVNT2.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[3]

Bit 23: EXTEVNT3.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[4]

Bit 24: EXTEVNT4.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[5]

Bit 25: EXTEVNT5.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[6]

Bit 26: EXTEVNT6.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[7]

Bit 27: EXTEVNT7.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[8]

Bit 28: EXTEVNT8.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[9]

Bit 29: EXTEVNT9.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

EXTEVNT[10]

Bit 30: EXTEVNT10.

Allowed values:
0: NoEffect: External event has no effect
1: SetInactive: External event forces the output to its inactive state

UPDATE

Bit 31: UPDATE.

Allowed values:
0: NoEffect: Register update event has no effect
1: SetInactive: Register update event forces the output to its inactive state

EEFR1

Timerx External Event Filtering Register 1

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EE[5]FLTR
rw
EE[5]LTCH
rw
EE[4]FLTR
rw
EE[4]LTCH
rw
EE[3]FLTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EE[3]FLTR
rw
EE[3]LTCH
rw
EE[2]FLTR
rw
EE[2]LTCH
rw
EE[1]FLTR
rw
EE[1]LTCH
rw
Toggle fields

EE[1]LTCH

Bit 0: External Event 1 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[1]FLTR

Bits 1-4: External Event 1 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[2]LTCH

Bit 6: External Event 2 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[2]FLTR

Bits 7-10: External Event 2 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[3]LTCH

Bit 12: External Event 3 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[3]FLTR

Bits 13-16: External Event 3 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[4]LTCH

Bit 18: External Event 4 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[4]FLTR

Bits 19-22: External Event 4 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[5]LTCH

Bit 24: External Event 5 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[5]FLTR

Bits 25-28: External Event 5 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EEFR2

Timerx External Event Filtering Register 2

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EE[10]FLTR
rw
EE[10]LTCH
rw
EE[9]FLTR
rw
EE[9]LTCH
rw
EE[8]FLTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EE[8]FLTR
rw
EE[8]LTCH
rw
EE[7]FLTR
rw
EE[7]LTCH
rw
EE[6]FLTR
rw
EE[6]LTCH
rw
Toggle fields

EE[6]LTCH

Bit 0: External Event 6 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[6]FLTR

Bits 1-4: External Event 6 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[7]LTCH

Bit 6: External Event 7 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[7]FLTR

Bits 7-10: External Event 7 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[8]LTCH

Bit 12: External Event 8 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[8]FLTR

Bits 13-16: External Event 8 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[9]LTCH

Bit 18: External Event 9 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[9]FLTR

Bits 19-22: External Event 9 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

EE[10]LTCH

Bit 24: External Event 10 latch.

Allowed values:
0: Disabled: Event is ignored if it happens during a blank, or passed through during a window
1: Enabled: Event is latched and delayed till the end of the blanking or windowing period

EE[10]FLTR

Bits 25-28: External Event 10 filter.

Allowed values:
0: Disabled: No filtering
1: BlankResetToCompare1: Blanking from counter reset/roll-over to Compare 1
2: BlankResetToCompare2: Blanking from counter reset/roll-over to Compare 2
3: BlankResetToCompare3: Blanking from counter reset/roll-over to Compare 3
4: BlankResetToCompare4: Blanking from counter reset/roll-over to Compare 4
5: BlankTIMFLTR1: Blanking from another timing unit: TIMFLTR1 source
6: BlankTIMFLTR2: Blanking from another timing unit: TIMFLTR2 source
7: BlankTIMFLTR3: Blanking from another timing unit: TIMFLTR3 source
8: BlankTIMFLTR4: Blanking from another timing unit: TIMFLTR4 source
9: BlankTIMFLTR5: Blanking from another timing unit: TIMFLTR5 source
10: BlankTIMFLTR6: Blanking from another timing unit: TIMFLTR6 source
11: BlankTIMFLTR7: Blanking from another timing unit: TIMFLTR7 source
12: BlankTIMFLTR8: Blanking from another timing unit: TIMFLTR8 source
13: WindowResetToCompare2: Windowing from counter reset/roll-over to compare 2
14: WindowResetToCompare3: Windowing from counter reset/roll-over to compare 3
15: WindowTIMWIN: Windowing from another timing unit: TIMWIN source

RSTR

TimerA Reset Register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

30/30 fields covered.

Toggle fields

UPDT

Bit 1: Timer A Update reset.

Allowed values:
0: NoEffect: Update event has no effect
1: ResetCounter: Timer X counter is reset upon update event

CMP2

Bit 2: Timer A compare 2 reset.

Allowed values:
0: NoEffect: Timer X compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer X compare Z event

CMP4

Bit 3: Timer A compare 4 reset.

Allowed values:
0: NoEffect: Timer X compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer X compare Z event

MSTPER

Bit 4: Master timer Period.

Allowed values:
0: NoEffect: Master timer period event has no effect
1: ResetCounter: Timer X counter is reset upon master timer period event

MSTCMP1

Bit 5: Master compare 1.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

MSTCMP2

Bit 6: Master compare 2.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

MSTCMP3

Bit 7: Master compare 3.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

MSTCMP4

Bit 8: Master compare 4.

Allowed values:
0: NoEffect: Master timer compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon master timer compare Z event

EXTEVNT1

Bit 9: External Event 1.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT2

Bit 10: External Event 2.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT3

Bit 11: External Event 3.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT4

Bit 12: External Event 4.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT5

Bit 13: External Event 5.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT6

Bit 14: External Event 6.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT7

Bit 15: External Event 7.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT8

Bit 16: External Event 8.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT9

Bit 17: External Event 9.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

EXTEVNT10

Bit 18: External Event 10.

Allowed values:
0: NoEffect: External event Z has no effect
1: ResetCounter: Timer X counter is reset upon external event Z

TIMACMP1

Bit 19: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMACMP2

Bit 20: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMACMP4

Bit 21: Timer A Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMBCMP1

Bit 22: Timer B Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMBCMP2

Bit 23: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMBCMP4

Bit 24: Timer B Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMCCMP1

Bit 25: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMCCMP2

Bit 26: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMCCMP4

Bit 27: Timer C Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMDCMP1

Bit 28: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMDCMP2

Bit 29: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

TIMDCMP4

Bit 30: Timer D Compare 4.

Allowed values:
0: NoEffect: Timer Y compare Z event has no effect
1: ResetCounter: Timer X counter is reset upon timer Y compare Z event

CHPR

Timerx Chopper Register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STRTPW
rw
CARDTY
rw
CARFRQ
rw
Toggle fields

CARFRQ

Bits 0-3: Timerx carrier frequency value.

Allowed values: 0x0-0xf

CARDTY

Bits 4-6: Timerx chopper duty cycle value.

Allowed values: 0x0-0x7

STRTPW

Bits 7-10: STRTPW.

Allowed values: 0x0-0xf

CPT1CR

Timerx Capture 2 Control Register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

28/28 fields covered.

Toggle fields

SWCPT

Bit 0: Software Capture.

Allowed values:
0: NoEffect: No effect
1: TriggerCapture: Force capture Z

UPDCPT

Bit 1: Update Capture.

Allowed values:
0: NoEffect: Update event has no effect
1: TriggerCapture: Update event triggers capture Z

EXEV[1]CPT

Bit 2: External Event 1 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[2]CPT

Bit 3: External Event 2 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[3]CPT

Bit 4: External Event 3 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[4]CPT

Bit 5: External Event 4 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[5]CPT

Bit 6: External Event 5 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[6]CPT

Bit 7: External Event 6 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[7]CPT

Bit 8: External Event 7 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[8]CPT

Bit 9: External Event 8 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[9]CPT

Bit 10: External Event 9 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[10]CPT

Bit 11: External Event 10 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

TA1SET

Bit 12: Timer A output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TA1RST

Bit 13: Timer A output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TACMP1

Bit 14: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TACMP2

Bit 15: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TB1SET

Bit 16: Timer B output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TB1RST

Bit 17: Timer B output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TBCMP1

Bit 18: Timer B Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TBCMP2

Bit 19: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TC1SET

Bit 20: Timer C output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TC1RST

Bit 21: Timer C output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TCCMP1

Bit 22: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TCCMP2

Bit 23: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TD1SET

Bit 24: Timer D output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TD1RST

Bit 25: Timer D output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TDCMP1

Bit 26: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TDCMP2

Bit 27: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

CPT2CR

CPT2xCR

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

28/28 fields covered.

Toggle fields

SWCPT

Bit 0: Software Capture.

Allowed values:
0: NoEffect: No effect
1: TriggerCapture: Force capture Z

UPDCPT

Bit 1: Update Capture.

Allowed values:
0: NoEffect: Update event has no effect
1: TriggerCapture: Update event triggers capture Z

EXEV[1]CPT

Bit 2: External Event 1 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[2]CPT

Bit 3: External Event 2 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[3]CPT

Bit 4: External Event 3 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[4]CPT

Bit 5: External Event 4 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[5]CPT

Bit 6: External Event 5 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[6]CPT

Bit 7: External Event 6 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[7]CPT

Bit 8: External Event 7 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[8]CPT

Bit 9: External Event 8 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[9]CPT

Bit 10: External Event 9 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

EXEV[10]CPT

Bit 11: External Event 10 Capture.

Allowed values:
0: NoEffect: External event Y has no effect
1: TriggerCapture: External event Y triggers capture Z

TA1SET

Bit 12: Timer A output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TA1RST

Bit 13: Timer A output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TACMP1

Bit 14: Timer A Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TACMP2

Bit 15: Timer A Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TB1SET

Bit 16: Timer B output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TB1RST

Bit 17: Timer B output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TBCMP1

Bit 18: Timer B Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TBCMP2

Bit 19: Timer B Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TC1SET

Bit 20: Timer C output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TC1RST

Bit 21: Timer C output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TCCMP1

Bit 22: Timer C Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TCCMP2

Bit 23: Timer C Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TD1SET

Bit 24: Timer D output 1 Set.

Allowed values:
0: NoEffect: Timer X output Y inactive to active transition has no effect
1: TriggerCapture: Timer X output Y inactive to active transition triggers capture Z

TD1RST

Bit 25: Timer D output 1 Reset.

Allowed values:
0: NoEffect: Timer X output Y active to inactive transition has no effect
1: TriggerCapture: Timer X output Y active to inactive transition triggers capture Z

TDCMP1

Bit 26: Timer D Compare 1.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

TDCMP2

Bit 27: Timer D Compare 2.

Allowed values:
0: NoEffect: Timer X compare Y has no effect
1: TriggerCapture: Timer X compare Y triggers capture Z

OUTR

Timerx Output Register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIDL2
rw
CHP2
rw
FAULT2
rw
IDLES2
rw
IDLEM2
rw
POL2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYPRT
rw
DLYPRTEN
rw
DTEN
rw
DIDL1
rw
CHP1
rw
FAULT1
rw
IDLES1
rw
IDLEM1
rw
POL1
rw
Toggle fields

POL1

Bit 1: Output 1 polarity.

Allowed values:
0: ActiveHigh: Positive polarity (output active high)
1: ActiveLow: Negative polarity (output active low)

IDLEM1

Bit 2: Output 1 Idle mode.

Allowed values:
0: NoEffect: No action: the output is not affected by the burst mode operation
1: SetIdle: The output is in idle state when requested by the burst mode controller

IDLES1

Bit 3: Output 1 Idle State.

Allowed values:
0: Inactive: Output idle state is inactive
1: Active: Output idle state is active

FAULT1

Bits 4-5: Output 1 Fault state.

Allowed values:
0: Disabled: No action: the output is not affected by the fault input and stays in run mode
1: SetActive: Output goes to active state after a fault event
2: SetInactive: Output goes to inactive state after a fault event
3: SetHighZ: Output goes to high-z state after a fault event

CHP1

Bit 6: Output 1 Chopper enable.

Allowed values:
0: Disabled: Output signal not altered
1: Enabled: Output signal is chopped by a carrier signal

DIDL1

Bit 7: Output 1 Deadtime upon burst mode Idle entry.

Allowed values:
0: Disabled: The programmed idle state is applied immediately to the output
1: Enabled: Deadtime (inactive level) is inserted on output before entering the idle mode

DTEN

Bit 8: Deadtime enable.

Allowed values:
0: Disabled: Output 1 and 2 signals are independent
1: Enabled: Deadtime is inserted between output 1 and output 2

DLYPRTEN

Bit 9: Delayed Protection Enable.

Allowed values:
0: Disabled: No action
1: Enabled: Delayed protection is enabled, as per DLYPRT bits

DLYPRT

Bits 10-12: Delayed Protection.

Allowed values:
0: Output1_EE6: Output 1 delayed idle on external event 6
1: Output2_EE6: Output 2 delayed idle on external event 6
2: Output1_2_EE6: Output 1 and 2 delayed idle on external event 6
3: Balanced_EE6: Balanced idle on external event 6
4: Output1_EE7: Output 1 delayed idle on external event 7
5: Output2_EE7: Output 2 delayed idle on external event 7
6: Output1_2_EE7: Output 1 and 2 delayed idle on external event 7
7: Balanced_EE7: Balanced idle on external event 7

POL2

Bit 17: Output 2 polarity.

Allowed values:
0: ActiveHigh: Positive polarity (output active high)
1: ActiveLow: Negative polarity (output active low)

IDLEM2

Bit 18: Output 2 Idle mode.

Allowed values:
0: NoEffect: No action: the output is not affected by the burst mode operation
1: SetIdle: The output is in idle state when requested by the burst mode controller

IDLES2

Bit 19: Output 2 Idle State.

Allowed values:
0: Inactive: Output idle state is inactive
1: Active: Output idle state is active

FAULT2

Bits 20-21: Output 2 Fault state.

Allowed values:
0: Disabled: No action: the output is not affected by the fault input and stays in run mode
1: SetActive: Output goes to active state after a fault event
2: SetInactive: Output goes to inactive state after a fault event
3: SetHighZ: Output goes to high-z state after a fault event

CHP2

Bit 22: Output 2 Chopper enable.

Allowed values:
0: Disabled: Output signal not altered
1: Enabled: Output signal is chopped by a carrier signal

DIDL2

Bit 23: Output 2 Deadtime upon burst mode Idle entry.

Allowed values:
0: Disabled: The programmed idle state is applied immediately to the output
1: Enabled: Deadtime (inactive level) is inserted on output before entering the idle mode

FLTR

Timerx Fault Register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLTLCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLT[5]EN
rw
FLT[4]EN
rw
FLT[3]EN
rw
FLT[2]EN
rw
FLT[1]EN
rw
Toggle fields

FLT[1]EN

Bit 0: Fault 1 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[2]EN

Bit 1: Fault 2 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[3]EN

Bit 2: Fault 3 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[4]EN

Bit 3: Fault 4 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLT[5]EN

Bit 4: Fault 5 enable.

Allowed values:
0: Ignored: Fault input ignored
1: Active: Fault input is active and can disable HRTIM outputs

FLTLCK

Bit 31: Fault sources Lock.

Allowed values:
0: Unlocked: FLT1EN..FLT5EN bits are read/write
1: Locked: FLT1EN..FLT5EN bits are read only

HSEM

0x48020800: HSEM

323/323 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 R[0]
0x4 R[1]
0x8 R[2]
0xc R[3]
0x10 R[4]
0x14 R[5]
0x18 R[6]
0x1c R[7]
0x20 R[8]
0x24 R[9]
0x28 R[10]
0x2c R[11]
0x30 R[12]
0x34 R[13]
0x38 R[14]
0x3c R[15]
0x40 R[16]
0x44 R[17]
0x48 R[18]
0x4c R[19]
0x50 R[20]
0x54 R[21]
0x58 R[22]
0x5c R[23]
0x60 R[24]
0x64 R[25]
0x68 R[26]
0x6c R[27]
0x70 R[28]
0x74 R[29]
0x78 R[30]
0x7c R[31]
0x80 RLR[0]
0x84 RLR[1]
0x88 RLR[2]
0x8c RLR[3]
0x90 RLR[4]
0x94 RLR[5]
0x98 RLR[6]
0x9c RLR[7]
0xa0 RLR[8]
0xa4 RLR[9]
0xa8 RLR[10]
0xac RLR[11]
0xb0 RLR[12]
0xb4 RLR[13]
0xb8 RLR[14]
0xbc RLR[15]
0xc0 RLR[16]
0xc4 RLR[17]
0xc8 RLR[18]
0xcc RLR[19]
0xd0 RLR[20]
0xd4 RLR[21]
0xd8 RLR[22]
0xdc RLR[23]
0xe0 RLR[24]
0xe4 RLR[25]
0xe8 RLR[26]
0xec RLR[27]
0xf0 RLR[28]
0xf4 RLR[29]
0xf8 RLR[30]
0xfc RLR[31]
0x100 IER
0x104 ICR
0x108 ISR
0x10c MISR
0x140 CR
0x144 KEYR
Toggle registers

R[0]

HSEM register HSEM_R0

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw
PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[1]

HSEM register HSEM_R1

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw
PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[2]

HSEM register HSEM_R2

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw
PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[3]

HSEM register HSEM_R3

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw
PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[4]

HSEM register HSEM_R4

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw
PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[5]

HSEM register HSEM_R5

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw
PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[6]

HSEM register HSEM_R6

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw
PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[7]

HSEM register HSEM_R7

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw
PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[8]

HSEM register HSEM_R8

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw
PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[9]

HSEM register HSEM_R9

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw
PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[10]

HSEM register HSEM_R10

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw
PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[11]

HSEM register HSEM_R11

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw
PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[12]

HSEM register HSEM_R12

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw
PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[13]

HSEM register HSEM_R13

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw
PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[14]

HSEM register HSEM_R14

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw
PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[15]

HSEM register HSEM_R15

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw
PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[16]

HSEM register HSEM_R16

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw
PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[17]

HSEM register HSEM_R17

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw
PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[18]

HSEM register HSEM_R18

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw
PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[19]

HSEM register HSEM_R19

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw
PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[20]

HSEM register HSEM_R20

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw
PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[21]

HSEM register HSEM_R21

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw
PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[22]

HSEM register HSEM_R22

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw
PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[23]

HSEM register HSEM_R23

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw
PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[24]

HSEM register HSEM_R24

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw
PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[25]

HSEM register HSEM_R25

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw
PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[26]

HSEM register HSEM_R26

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw
PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[27]

HSEM register HSEM_R27

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw
PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[28]

HSEM register HSEM_R28

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw
PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[29]

HSEM register HSEM_R29

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw
PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[30]

HSEM register HSEM_R30

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw
PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

R[31]

HSEM register HSEM_R31

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw
PROCID
rw
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[0]

Semaphore 0 read lock register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r
PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[1]

Semaphore 1 read lock register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r
PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[2]

Semaphore 2 read lock register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r
PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[3]

Semaphore 3 read lock register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r
PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[4]

Semaphore 4 read lock register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r
PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[5]

Semaphore 5 read lock register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r
PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[6]

Semaphore 6 read lock register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r
PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[7]

Semaphore 7 read lock register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r
PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[8]

Semaphore 8 read lock register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r
PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[9]

Semaphore 9 read lock register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r
PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[10]

Semaphore 10 read lock register

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r
PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[11]

Semaphore 11 read lock register

Offset: 0xac, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r
PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[12]

Semaphore 12 read lock register

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r
PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[13]

Semaphore 13 read lock register

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r
PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[14]

Semaphore 14 read lock register

Offset: 0xb8, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r
PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[15]

Semaphore 15 read lock register

Offset: 0xbc, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r
PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[16]

Semaphore 16 read lock register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r
PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[17]

Semaphore 17 read lock register

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r
PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[18]

Semaphore 18 read lock register

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r
PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[19]

Semaphore 19 read lock register

Offset: 0xcc, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r
PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[20]

Semaphore 20 read lock register

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r
PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[21]

Semaphore 21 read lock register

Offset: 0xd4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r
PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[22]

Semaphore 22 read lock register

Offset: 0xd8, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r
PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[23]

Semaphore 23 read lock register

Offset: 0xdc, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r
PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[24]

Semaphore 24 read lock register

Offset: 0xe0, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r
PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[25]

Semaphore 25 read lock register

Offset: 0xe4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r
PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[26]

Semaphore 26 read lock register

Offset: 0xe8, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r
PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[27]

Semaphore 27 read lock register

Offset: 0xec, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r
PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[28]

Semaphore 28 read lock register

Offset: 0xf0, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r
PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[29]

Semaphore 29 read lock register

Offset: 0xf4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r
PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[30]

Semaphore 30 read lock register

Offset: 0xf8, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r
PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

RLR[31]

Semaphore 31 read lock register

Offset: 0xfc, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
r
PROCID
r
Toggle fields

PROCID

Bits 0-7: Semaphore ProcessID.

Allowed values: 0x0-0xff

MASTERID

Bits 8-15: Semaphore MasterID.

Allowed values: 0x0-0xf

LOCK

Bit 31: Lock indication.

Allowed values:
0: Free: Semaphore is free
1: Locked: Semaphore is locked

IER

HSEM Interrupt enable register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

Toggle fields

ISE[0]

Bit 0: Interrupt semaphore 0 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[1]

Bit 1: Interrupt semaphore 1 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[2]

Bit 2: Interrupt semaphore 2 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[3]

Bit 3: Interrupt semaphore 3 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[4]

Bit 4: Interrupt semaphore 4 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[5]

Bit 5: Interrupt semaphore 5 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[6]

Bit 6: Interrupt semaphore 6 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[7]

Bit 7: Interrupt semaphore 7 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[8]

Bit 8: Interrupt semaphore 8 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[9]

Bit 9: Interrupt semaphore 9 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[10]

Bit 10: Interrupt semaphore 10 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[11]

Bit 11: Interrupt semaphore 11 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[12]

Bit 12: Interrupt semaphore 12 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[13]

Bit 13: Interrupt semaphore 13 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[14]

Bit 14: Interrupt semaphore 14 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[15]

Bit 15: Interrupt semaphore 15 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[16]

Bit 16: Interrupt semaphore 16 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[17]

Bit 17: Interrupt semaphore 17 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[18]

Bit 18: Interrupt semaphore 18 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[19]

Bit 19: Interrupt semaphore 19 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[20]

Bit 20: Interrupt semaphore 20 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[21]

Bit 21: Interrupt semaphore 21 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[22]

Bit 22: Interrupt semaphore 22 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[23]

Bit 23: Interrupt semaphore 23 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[24]

Bit 24: Interrupt semaphore 24 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[25]

Bit 25: Interrupt semaphore 25 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[26]

Bit 26: Interrupt semaphore 26 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[27]

Bit 27: Interrupt semaphore 27 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[28]

Bit 28: Interrupt semaphore 28 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[29]

Bit 29: Interrupt semaphore 29 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[30]

Bit 30: Interrupt semaphore 30 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ISE[31]

Bit 31: Interrupt semaphore 31 enable bit.

Allowed values:
0: Disabled: Interrupt generation disabled
1: Enabled: Interrupt generation enabled

ICR

HSEM Interrupt clear register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

Toggle fields

ISC[0]

Bit 0: Interrupt semaphore 0 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[1]

Bit 1: Interrupt semaphore 1 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[2]

Bit 2: Interrupt semaphore 2 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[3]

Bit 3: Interrupt semaphore 3 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[4]

Bit 4: Interrupt semaphore 4 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[5]

Bit 5: Interrupt semaphore 5 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[6]

Bit 6: Interrupt semaphore 6 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[7]

Bit 7: Interrupt semaphore 7 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[8]

Bit 8: Interrupt semaphore 8 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[9]

Bit 9: Interrupt semaphore 9 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[10]

Bit 10: Interrupt semaphore 10 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[11]

Bit 11: Interrupt semaphore 11 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[12]

Bit 12: Interrupt semaphore 12 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[13]

Bit 13: Interrupt semaphore 13 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[14]

Bit 14: Interrupt semaphore 14 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[15]

Bit 15: Interrupt semaphore 15 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[16]

Bit 16: Interrupt semaphore 16 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[17]

Bit 17: Interrupt semaphore 17 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[18]

Bit 18: Interrupt semaphore 18 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[19]

Bit 19: Interrupt semaphore 19 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[20]

Bit 20: Interrupt semaphore 20 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[21]

Bit 21: Interrupt semaphore 21 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[22]

Bit 22: Interrupt semaphore 22 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[23]

Bit 23: Interrupt semaphore 23 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[24]

Bit 24: Interrupt semaphore 24 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[25]

Bit 25: Interrupt semaphore 25 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[26]

Bit 26: Interrupt semaphore 26 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[27]

Bit 27: Interrupt semaphore 27 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[28]

Bit 28: Interrupt semaphore 28 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[29]

Bit 29: Interrupt semaphore 29 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[30]

Bit 30: Interrupt semaphore 30 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISC[31]

Bit 31: Interrupt semaphore 31 clear bit.

Allowed values:
0: NoEffect: Always reads 0

ISR

HSEM Interrupt status register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-only

32/32 fields covered.

Toggle fields

ISF[0]

Bit 0: Interrupt semaphore 0 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[1]

Bit 1: Interrupt semaphore 1 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[2]

Bit 2: Interrupt semaphore 2 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[3]

Bit 3: Interrupt semaphore 3 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[4]

Bit 4: Interrupt semaphore 4 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[5]

Bit 5: Interrupt semaphore 5 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[6]

Bit 6: Interrupt semaphore 6 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[7]

Bit 7: Interrupt semaphore 7 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[8]

Bit 8: Interrupt semaphore 8 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[9]

Bit 9: Interrupt semaphore 9 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[10]

Bit 10: Interrupt semaphore 10 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[11]

Bit 11: Interrupt semaphore 11 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[12]

Bit 12: Interrupt semaphore 12 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[13]

Bit 13: Interrupt semaphore 13 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[14]

Bit 14: Interrupt semaphore 14 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[15]

Bit 15: Interrupt semaphore 15 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[16]

Bit 16: Interrupt semaphore 16 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[17]

Bit 17: Interrupt semaphore 17 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[18]

Bit 18: Interrupt semaphore 18 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[19]

Bit 19: Interrupt semaphore 19 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[20]

Bit 20: Interrupt semaphore 20 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[21]

Bit 21: Interrupt semaphore 21 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[22]

Bit 22: Interrupt semaphore 22 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[23]

Bit 23: Interrupt semaphore 23 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[24]

Bit 24: Interrupt semaphore 24 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[25]

Bit 25: Interrupt semaphore 25 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[26]

Bit 26: Interrupt semaphore 26 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[27]

Bit 27: Interrupt semaphore 27 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[28]

Bit 28: Interrupt semaphore 28 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[29]

Bit 29: Interrupt semaphore 29 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[30]

Bit 30: Interrupt semaphore 30 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

ISF[31]

Bit 31: Interrupt semaphore 31 status bit before enable (mask).

Allowed values:
0: NotPending: No interrupt pending
1: Pending: Interrupt pending

MISR

HSEM Masked interrupt status register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-only

32/32 fields covered.

Toggle fields

MISF[0]

Bit 0: Masked interrupt semaphore 0 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[1]

Bit 1: Masked interrupt semaphore 1 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[2]

Bit 2: Masked interrupt semaphore 2 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[3]

Bit 3: Masked interrupt semaphore 3 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[4]

Bit 4: Masked interrupt semaphore 4 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[5]

Bit 5: Masked interrupt semaphore 5 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[6]

Bit 6: Masked interrupt semaphore 6 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[7]

Bit 7: Masked interrupt semaphore 7 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[8]

Bit 8: Masked interrupt semaphore 8 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[9]

Bit 9: Masked interrupt semaphore 9 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[10]

Bit 10: Masked interrupt semaphore 10 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[11]

Bit 11: Masked interrupt semaphore 11 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[12]

Bit 12: Masked interrupt semaphore 12 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[13]

Bit 13: Masked interrupt semaphore 13 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[14]

Bit 14: Masked interrupt semaphore 14 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[15]

Bit 15: Masked interrupt semaphore 15 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[16]

Bit 16: Masked interrupt semaphore 16 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[17]

Bit 17: Masked interrupt semaphore 17 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[18]

Bit 18: Masked interrupt semaphore 18 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[19]

Bit 19: Masked interrupt semaphore 19 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[20]

Bit 20: Masked interrupt semaphore 20 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[21]

Bit 21: Masked interrupt semaphore 21 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[22]

Bit 22: Masked interrupt semaphore 22 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[23]

Bit 23: Masked interrupt semaphore 23 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[24]

Bit 24: Masked interrupt semaphore 24 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[25]

Bit 25: Masked interrupt semaphore 25 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[26]

Bit 26: Masked interrupt semaphore 26 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[27]

Bit 27: Masked interrupt semaphore 27 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[28]

Bit 28: Masked interrupt semaphore 28 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[29]

Bit 29: Masked interrupt semaphore 29 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[30]

Bit 30: Masked interrupt semaphore 30 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

MISF[31]

Bit 31: Masked interrupt semaphore 31 status bit after enable (mask).

Allowed values:
0: NotPending: No interrupt pending after masking
1: Pending: Interrupt pending after masking

CR

HSEM Clear register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID
rw
Toggle fields

MASTERID

Bits 8-11: MasterID of semaphores to be cleared.

Allowed values: 0x0-0xf

KEY

Bits 16-31: Semaphore clear Key.

Allowed values: 0x0-0xffff

KEYR

HSEM Interrupt clear register

Offset: 0x144, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

KEY

Bits 16-31: Semaphore Clear Key.

Allowed values: 0x0-0xffff

I2C1

0x40005400: I2C1

76/76 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 TIMINGR
0x14 TIMEOUTR
0x18 ISR
0x1c ICR
0x20 PECR
0x24 RXDR
0x28 TXDR
Toggle registers

CR1

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw
ALERTEN
rw
SMBDEN
rw
SMBHEN
rw
GCEN
rw
WUPEN
rw
NOSTRETCH
rw
SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw
TXDMAEN
rw
ANFOFF
rw
DNF
rw
ERRIE
rw
TCIE
rw
STOPIE
rw
NACKIE
rw
ADDRIE
rw
RXIE
rw
TXIE
rw
PE
rw
Toggle fields

PE

Bit 0: Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles..

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

TXIE

Bit 1: TX Interrupt enable.

Allowed values:
0: Disabled: Transmit (TXIS) interrupt disabled
1: Enabled: Transmit (TXIS) interrupt enabled

RXIE

Bit 2: RX Interrupt enable.

Allowed values:
0: Disabled: Receive (RXNE) interrupt disabled
1: Enabled: Receive (RXNE) interrupt enabled

ADDRIE

Bit 3: Address match Interrupt enable (slave only).

Allowed values:
0: Disabled: Address match (ADDR) interrupts disabled
1: Enabled: Address match (ADDR) interrupts enabled

NACKIE

Bit 4: Not acknowledge received Interrupt enable.

Allowed values:
0: Disabled: Not acknowledge (NACKF) received interrupts disabled
1: Enabled: Not acknowledge (NACKF) received interrupts enabled

STOPIE

Bit 5: STOP detection Interrupt enable.

Allowed values:
0: Disabled: Stop detection (STOPF) interrupt disabled
1: Enabled: Stop detection (STOPF) interrupt enabled

TCIE

Bit 6: Transfer Complete interrupt enable Note: Any of these events will generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR).

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

ERRIE

Bit 7: Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT).

Allowed values:
0: Disabled: Error detection interrupts disabled
1: Enabled: Error detection interrupts enabled

DNF

Bits 8-11: Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF[3:0] * tI2CCLK ... Note: If the analog filter is also enabled, the digital filter is added to the analog filter. This filter can only be programmed when the I2C is disabled (PE = 0)..

Allowed values:
0: NoFilter: Digital filter disabled
1: Filter1: Digital filter enabled and filtering capability up to 1 tI2CCLK
2: Filter2: Digital filter enabled and filtering capability up to 2 tI2CCLK
3: Filter3: Digital filter enabled and filtering capability up to 3 tI2CCLK
4: Filter4: Digital filter enabled and filtering capability up to 4 tI2CCLK
5: Filter5: Digital filter enabled and filtering capability up to 5 tI2CCLK
6: Filter6: Digital filter enabled and filtering capability up to 6 tI2CCLK
7: Filter7: Digital filter enabled and filtering capability up to 7 tI2CCLK
8: Filter8: Digital filter enabled and filtering capability up to 8 tI2CCLK
9: Filter9: Digital filter enabled and filtering capability up to 9 tI2CCLK
10: Filter10: Digital filter enabled and filtering capability up to 10 tI2CCLK
11: Filter11: Digital filter enabled and filtering capability up to 11 tI2CCLK
12: Filter12: Digital filter enabled and filtering capability up to 12 tI2CCLK
13: Filter13: Digital filter enabled and filtering capability up to 13 tI2CCLK
14: Filter14: Digital filter enabled and filtering capability up to 14 tI2CCLK
15: Filter15: Digital filter enabled and filtering capability up to 15 tI2CCLK

ANFOFF

Bit 12: Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0)..

Allowed values:
0: Enabled: Analog noise filter enabled
1: Disabled: Analog noise filter disabled

TXDMAEN

Bit 14: DMA transmission requests enable.

Allowed values:
0: Disabled: DMA mode disabled for transmission
1: Enabled: DMA mode enabled for transmission

RXDMAEN

Bit 15: DMA reception requests enable.

Allowed values:
0: Disabled: DMA mode disabled for reception
1: Enabled: DMA mode enabled for reception

SBC

Bit 16: Slave byte control This bit is used to enable hardware byte control in slave mode..

Allowed values:
0: Disabled: Slave byte control disabled
1: Enabled: Slave byte control enabled

NOSTRETCH

Bit 17: Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0)..

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

WUPEN

Bit 18: Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation. Note: WUPEN can be set only when DNF = 0000.

Allowed values:
0: Disabled: Wakeup from Stop mode disabled
1: Enabled: Wakeup from Stop mode enabled

GCEN

Bit 19: General call enable.

Allowed values:
0: Disabled: General call disabled. Address 0b00000000 is NACKed
1: Enabled: General call enabled. Address 0b00000000 is ACKed

SMBHEN

Bit 20: SMBus Host address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
0: Disabled: Host address disabled. Address 0b0001000x is NACKed
1: Enabled: Host address enabled. Address 0b0001000x is ACKed

SMBDEN

Bit 21: SMBus Device Default address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
0: Disabled: Device default address disabled. Address 0b1100001x is NACKed
1: Enabled: Device default address enabled. Address 0b1100001x is ACKed

ALERTEN

Bit 22: SMBus alert enable Device mode (SMBHEN=0): Host mode (SMBHEN=1): Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
0: Disabled: In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
1: Enabled: In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported

PECEN

Bit 23: PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

CR2

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
r/w1s
AUTOEND
rw
RELOAD
rw
NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
r/w1s
STOP
r/w1s
START
r/w1s
HEAD10R
rw
ADD10
rw
RD_WRN
rw
SADD
rw
Toggle fields

SADD

Bits 0-9: Slave address bit 0 (master mode) In 7-bit addressing mode (ADD10 = 0): This bit is dont care In 10-bit addressing mode (ADD10 = 1): This bit should be written with bit 0 of the slave address to be sent Note: Changing these bits when the START bit is set is not allowed..

Allowed values: 0x0-0x3ff

RD_WRN

Bit 10: Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed..

Allowed values:
0: Write: Master requests a write transfer
1: Read: Master requests a read transfer

ADD10

Bit 11: 10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed..

Allowed values:
0: Bit7: The master operates in 7-bit addressing mode
1: Bit10: The master operates in 10-bit addressing mode

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed..

Allowed values:
0: Complete: The master sends the complete 10 bit slave address read sequence
1: Partial: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction

START

Bit 13: Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing 1 to the ADDRCF bit in the I2C_ICR register. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit will generate a START condition once the bus is free. Note: Writing 0 to this bit has no effect. The START bit can be set even if the bus is BUSY or I2C is in slave mode. This bit has no effect when RELOAD is set..

Allowed values:
0: NoStart: No Start generation
1: Start: Restart/Start generation

STOP

Bit 14: Stop generation (master mode) The bit is set by software, cleared by hardware when a Stop condition is detected, or when PE = 0. In Master Mode: Note: Writing 0 to this bit has no effect..

Allowed values:
0: NoStop: No Stop generation
1: Stop: Stop generation after current byte transfer

NACK

Bit 15: NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. Note: Writing 0 to this bit has no effect. This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value..

Allowed values:
0: Ack: an ACK is sent after current received byte
1: Nack: a NACK is sent after current received byte

NBYTES

Bits 16-23: Number of bytes The number of bytes to be transmitted/received is programmed there. This field is dont care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed..

Allowed values: 0x0-0xff

RELOAD

Bit 24: NBYTES reload mode This bit is set and cleared by software..

Allowed values:
0: Completed: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)
1: NotCompleted: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)

AUTOEND

Bit 25: Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set..

Allowed values:
0: Software: Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low
1: Automatic: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred

PECBYTE

Bit 26: Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. Note: Writing 0 to this bit has no effect. This bit has no effect when RELOAD is set. This bit has no effect is slave mode when SBC=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
0: NoPec: No PEC transfer
1: Pec: PEC transmission/reception is requested

OAR1

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw
OA1MODE
rw
OA1
rw
Toggle fields

OA1

Bits 0-9: Interface address 7-bit addressing mode: dont care 10-bit addressing mode: bits 9:8 of address Note: These bits can be written only when OA1EN=0. OA1[7:1]: Interface address Bits 7:1 of address Note: These bits can be written only when OA1EN=0. OA1[0]: Interface address 7-bit addressing mode: dont care 10-bit addressing mode: bit 0 of address Note: This bit can be written only when OA1EN=0..

Allowed values: 0x0-0x3ff

OA1MODE

Bit 10: Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0..

Allowed values:
0: Bit7: Own address 1 is a 7-bit address
1: Bit10: Own address 1 is a 10-bit address

OA1EN

Bit 15: Own Address 1 enable.

Allowed values:
0: Disabled: Own address 1 disabled. The received slave address OA1 is NACKed
1: Enabled: Own address 1 enabled. The received slave address OA1 is ACKed

OAR2

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw
OA2MSK
rw
OA2
rw
Toggle fields

OA2

Bits 1-7: Interface address bits 7:1 of address Note: These bits can be written only when OA2EN=0..

Allowed values: 0x0-0x7f

OA2MSK

Bits 8-10: Own Address 2 masks Note: These bits can be written only when OA2EN=0. As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches..

Allowed values:
0: NoMask: No mask
1: Mask1: OA2[1] is masked and don’t care. Only OA2[7:2] are compared
2: Mask2: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
3: Mask3: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
4: Mask4: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
5: Mask5: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
6: Mask6: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
7: Mask7: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged

OA2EN

Bit 15: Own Address 2 enable.

Allowed values:
0: Disabled: Own address 2 disabled. The received slave address OA2 is NACKed
1: Enabled: Own address 2 enabled. The received slave address OA2 is ACKed

TIMINGR

Access: No wait states

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw
SCLDEL
rw
SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw
SCLL
rw
Toggle fields

SCLL

Bits 0-7: SCL low period (master mode) This field is used to generate the SCL low period in master mode. tSCLL = (SCLL+1) x tPRESC Note: SCLL is also used to generate tBUF and tSU:STA timings..

Allowed values: 0x0-0xff

SCLH

Bits 8-15: SCL high period (master mode) This field is used to generate the SCL high period in master mode. tSCLH = (SCLH+1) x tPRESC Note: SCLH is also used to generate tSU:STO and tHD:STA timing..

Allowed values: 0x0-0xff

SDADEL

Bits 16-19: Data hold time This field is used to generate the delay tSDADEL between SCL falling edge and SDA edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSDADEL. tSDADEL= SDADEL x tPRESC Note: SDADEL is used to generate tHD:DAT timing..

Allowed values: 0x0-0xf

SCLDEL

Bits 20-23: Data setup time This field is used to generate a delay tSCLDEL between SDA edge and SCL rising edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSCLDEL. tSCLDEL = (SCLDEL+1) x tPRESC Note: tSCLDEL is used to generate tSU:DAT timing..

Allowed values: 0x0-0xf

PRESC

Bits 28-31: Timing prescaler This field is used to prescale I2CCLK in order to generate the clock period tPRESC used for data setup and hold counters (refer to I2C timings on page9) and for SCL high and low level counters (refer to I2C master initialization on page24). tPRESC = (PRESC+1) x tI2CCLK.

Allowed values: 0x0-0xf

TIMEOUTR

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw
TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw
TIDLE
rw
TIMEOUTA
rw
Toggle fields

TIMEOUTA

Bits 0-11: Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0..

Allowed values: 0x0-0xfff

TIDLE

Bit 12: Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0..

Allowed values:
0: Disabled: TIMEOUTA is used to detect SCL low timeout
1: Enabled: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)

TIMOUTEN

Bit 15: Clock timeout enable.

Allowed values:
0: Disabled: SCL timeout detection is disabled
1: Enabled: SCL timeout detection is enabled

TIMEOUTB

Bits 16-27: Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0..

Allowed values: 0x0-0xfff

TEXTEN

Bit 31: Extended clock timeout enable.

Allowed values:
0: Disabled: Extended clock timeout detection is disabled
1: Enabled: Extended clock timeout detection is enabled

ISR

Access: No wait states

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r
DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r
ALERT
r
TIMEOUT
r
PECERR
r
OVR
r
ARLO
r
BERR
r
TCR
r
TC
r
STOPF
r
NACKF
r
ADDR
r
RXNE
r
TXIS
r/w1s
TXE
r/w1s
Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters) This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software in order to flush the transmit data register I2C_TXDR. Note: This bit is set by hardware when PE=0..

Allowed values:
0: NotEmpty: TXDR register not empty
1: Empty: TXDR register empty

TXIS

Bit 1: Transmit interrupt status (transmitters) This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software when NOSTRETCH=1 only, in order to generate a TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN=1). Note: This bit is cleared by hardware when PE=0..

Allowed values:
0: NotEmpty: The TXDR register is not empty
1: Empty: The TXDR register is empty and the data to be transmitted must be written in the TXDR register

RXNE

Bit 2: Receive data register not empty (receivers) This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. Note: This bit is cleared by hardware when PE=0..

Allowed values:
0: Empty: The RXDR register is empty
1: NotEmpty: Received data is copied into the RXDR register, and is ready to be read

ADDR

Bit 3: Address matched (slave mode) This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. Note: This bit is cleared by hardware when PE=0..

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

NACKF

Bit 4: Not Acknowledge received flag This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. Note: This bit is cleared by hardware when PE=0..

Allowed values:
0: NoNack: No NACK has been received
1: Nack: NACK has been received

STOPF

Bit 5: Stop detection flag This flag is set by hardware when a Stop condition is detected on the bus and the peripheral is involved in this transfer: either as a master, provided that the STOP condition is generated by the peripheral. or as a slave, provided that the peripheral has been addressed previously during this transfer. It is cleared by software by setting the STOPCF bit. Note: This bit is cleared by hardware when PE=0..

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

TC

Bit 6: Transfer Complete (master mode) This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. Note: This bit is cleared by hardware when PE=0..

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

TCR

Bit 7: Transfer Complete Reload This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. Note: This bit is cleared by hardware when PE=0. This flag is only for master mode, or for slave mode when the SBC bit is set..

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

BERR

Bit 8: Bus error This flag is set by hardware when a misplaced Start or Stop condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting BERRCF bit. Note: This bit is cleared by hardware when PE=0..

Allowed values:
0: NoError: No bus error
1: Error: Misplaced Start and Stop condition is detected

ARLO

Bit 9: Arbitration lost This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. Note: This bit is cleared by hardware when PE=0..

Allowed values:
0: NotLost: No arbitration lost
1: Lost: Arbitration lost

OVR

Bit 10: Overrun/Underrun (slave mode) This flag is set by hardware in slave mode with NOSTRETCH=1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. Note: This bit is cleared by hardware when PE=0..

Allowed values:
0: NoOverrun: No overrun/underrun error occurs
1: Overrun: slave mode with NOSTRETCH=1, when an overrun/underrun error occurs

PECERR

Bit 11: PEC Error in reception This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
0: Match: Received PEC does match with PEC register
1: NoMatch: Received PEC does not match with PEC register

TIMEOUT

Bit 12: Timeout or tLOW detection flag This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared by software by setting the TIMEOUTCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
0: NoTimeout: No timeout occured
1: Timeout: Timeout occured

ALERT

Bit 13: SMBus alert This flag is set by hardware when SMBHEN=1 (SMBus host configuration), ALERTEN=1 and a SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by setting the ALERTCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
0: NoAlert: SMBA alert is not detected
1: Alert: SMBA alert event is detected on SMBA pin

BUSY

Bit 15: Bus busy This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a Stop condition is detected, or when PE=0..

Allowed values:
0: NotBusy: No communication is in progress on the bus
1: Busy: A communication is in progress on the bus

DIR

Bit 16: Transfer direction (Slave mode) This flag is updated when an address match event occurs (ADDR=1)..

Allowed values:
0: Write: Write transfer, slave enters receiver mode
1: Read: Read transfer, slave enters transmitter mode

ADDCODE

Bits 17-23: Address match code (Slave mode) These bits are updated with the received address when an address match event occurs (ADDR = 1). In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the 2 MSBs of the address..

Allowed values: 0x0-0x7f

ICR

Access: No wait states

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w1c
TIMOUTCF
w1c
PECCF
w1c
OVRCF
w1c
ARLOCF
w1c
BERRCF
w1c
STOPCF
w1c
NACKCF
w1c
ADDRCF
w1c
Toggle fields

ADDRCF

Bit 3: Address matched flag clear Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears the START bit in the I2C_CR2 register..

Allowed values:
1: Clear: Clears the ADDR flag in ISR register

NACKCF

Bit 4: Not Acknowledge flag clear Writing 1 to this bit clears the ACKF flag in I2C_ISR register..

Allowed values:
1: Clear: Clears the NACK flag in ISR register

STOPCF

Bit 5: Stop detection flag clear Writing 1 to this bit clears the STOPF flag in the I2C_ISR register..

Allowed values:
1: Clear: Clears the STOP flag in ISR register

BERRCF

Bit 8: Bus error flag clear Writing 1 to this bit clears the BERRF flag in the I2C_ISR register..

Allowed values:
1: Clear: Clears the BERR flag in ISR register

ARLOCF

Bit 9: Arbitration Lost flag clear Writing 1 to this bit clears the ARLO flag in the I2C_ISR register..

Allowed values:
1: Clear: Clears the ARLO flag in ISR register

OVRCF

Bit 10: Overrun/Underrun flag clear Writing 1 to this bit clears the OVR flag in the I2C_ISR register..

Allowed values:
1: Clear: Clears the OVR flag in ISR register

PECCF

Bit 11: PEC Error flag clear Writing 1 to this bit clears the PECERR flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
1: Clear: Clears the PEC flag in ISR register

TIMOUTCF

Bit 12: Timeout detection flag clear Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
1: Clear: Clears the TIMOUT flag in ISR register

ALERTCF

Bit 13: Alert flag clear Writing 1 to this bit clears the ALERT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
1: Clear: Clears the ALERT flag in ISR register

PECR

Access: No wait states

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle fields

PEC

Bits 0-7: Packet error checking register This field contains the internal PEC when PECEN=1. The PEC is cleared by hardware when PE=0..

Allowed values: 0x0-0xff

RXDR

Access: No wait states

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: 8-bit receive data Data byte received from the I2C bus..

Allowed values: 0x0-0xff

TXDR

Access: No wait states

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data Data byte to be transmitted to the I2C bus. Note: These bits can be written only when TXE=1..

Allowed values: 0x0-0xff

I2C2

0x40005800: I2C1

76/76 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 TIMINGR
0x14 TIMEOUTR
0x18 ISR
0x1c ICR
0x20 PECR
0x24 RXDR
0x28 TXDR
Toggle registers

CR1

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw
ALERTEN
rw
SMBDEN
rw
SMBHEN
rw
GCEN
rw
WUPEN
rw
NOSTRETCH
rw
SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw
TXDMAEN
rw
ANFOFF
rw
DNF
rw
ERRIE
rw
TCIE
rw
STOPIE
rw
NACKIE
rw
ADDRIE
rw
RXIE
rw
TXIE
rw
PE
rw
Toggle fields

PE

Bit 0: Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles..

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

TXIE

Bit 1: TX Interrupt enable.

Allowed values:
0: Disabled: Transmit (TXIS) interrupt disabled
1: Enabled: Transmit (TXIS) interrupt enabled

RXIE

Bit 2: RX Interrupt enable.

Allowed values:
0: Disabled: Receive (RXNE) interrupt disabled
1: Enabled: Receive (RXNE) interrupt enabled

ADDRIE

Bit 3: Address match Interrupt enable (slave only).

Allowed values:
0: Disabled: Address match (ADDR) interrupts disabled
1: Enabled: Address match (ADDR) interrupts enabled

NACKIE

Bit 4: Not acknowledge received Interrupt enable.

Allowed values:
0: Disabled: Not acknowledge (NACKF) received interrupts disabled
1: Enabled: Not acknowledge (NACKF) received interrupts enabled

STOPIE

Bit 5: STOP detection Interrupt enable.

Allowed values:
0: Disabled: Stop detection (STOPF) interrupt disabled
1: Enabled: Stop detection (STOPF) interrupt enabled

TCIE

Bit 6: Transfer Complete interrupt enable Note: Any of these events will generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR).

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

ERRIE

Bit 7: Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT).

Allowed values:
0: Disabled: Error detection interrupts disabled
1: Enabled: Error detection interrupts enabled

DNF

Bits 8-11: Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF[3:0] * tI2CCLK ... Note: If the analog filter is also enabled, the digital filter is added to the analog filter. This filter can only be programmed when the I2C is disabled (PE = 0)..

Allowed values:
0: NoFilter: Digital filter disabled
1: Filter1: Digital filter enabled and filtering capability up to 1 tI2CCLK
2: Filter2: Digital filter enabled and filtering capability up to 2 tI2CCLK
3: Filter3: Digital filter enabled and filtering capability up to 3 tI2CCLK
4: Filter4: Digital filter enabled and filtering capability up to 4 tI2CCLK
5: Filter5: Digital filter enabled and filtering capability up to 5 tI2CCLK
6: Filter6: Digital filter enabled and filtering capability up to 6 tI2CCLK
7: Filter7: Digital filter enabled and filtering capability up to 7 tI2CCLK
8: Filter8: Digital filter enabled and filtering capability up to 8 tI2CCLK
9: Filter9: Digital filter enabled and filtering capability up to 9 tI2CCLK
10: Filter10: Digital filter enabled and filtering capability up to 10 tI2CCLK
11: Filter11: Digital filter enabled and filtering capability up to 11 tI2CCLK
12: Filter12: Digital filter enabled and filtering capability up to 12 tI2CCLK
13: Filter13: Digital filter enabled and filtering capability up to 13 tI2CCLK
14: Filter14: Digital filter enabled and filtering capability up to 14 tI2CCLK
15: Filter15: Digital filter enabled and filtering capability up to 15 tI2CCLK

ANFOFF

Bit 12: Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0)..

Allowed values:
0: Enabled: Analog noise filter enabled
1: Disabled: Analog noise filter disabled

TXDMAEN

Bit 14: DMA transmission requests enable.

Allowed values:
0: Disabled: DMA mode disabled for transmission
1: Enabled: DMA mode enabled for transmission

RXDMAEN

Bit 15: DMA reception requests enable.

Allowed values:
0: Disabled: DMA mode disabled for reception
1: Enabled: DMA mode enabled for reception

SBC

Bit 16: Slave byte control This bit is used to enable hardware byte control in slave mode..

Allowed values:
0: Disabled: Slave byte control disabled
1: Enabled: Slave byte control enabled

NOSTRETCH

Bit 17: Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0)..

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

WUPEN

Bit 18: Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation. Note: WUPEN can be set only when DNF = 0000.

Allowed values:
0: Disabled: Wakeup from Stop mode disabled
1: Enabled: Wakeup from Stop mode enabled

GCEN

Bit 19: General call enable.

Allowed values:
0: Disabled: General call disabled. Address 0b00000000 is NACKed
1: Enabled: General call enabled. Address 0b00000000 is ACKed

SMBHEN

Bit 20: SMBus Host address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
0: Disabled: Host address disabled. Address 0b0001000x is NACKed
1: Enabled: Host address enabled. Address 0b0001000x is ACKed

SMBDEN

Bit 21: SMBus Device Default address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
0: Disabled: Device default address disabled. Address 0b1100001x is NACKed
1: Enabled: Device default address enabled. Address 0b1100001x is ACKed

ALERTEN

Bit 22: SMBus alert enable Device mode (SMBHEN=0): Host mode (SMBHEN=1): Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
0: Disabled: In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
1: Enabled: In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported

PECEN

Bit 23: PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

CR2

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
r/w1s
AUTOEND
rw
RELOAD
rw
NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
r/w1s
STOP
r/w1s
START
r/w1s
HEAD10R
rw
ADD10
rw
RD_WRN
rw
SADD
rw
Toggle fields

SADD

Bits 0-9: Slave address bit 0 (master mode) In 7-bit addressing mode (ADD10 = 0): This bit is dont care In 10-bit addressing mode (ADD10 = 1): This bit should be written with bit 0 of the slave address to be sent Note: Changing these bits when the START bit is set is not allowed..

Allowed values: 0x0-0x3ff

RD_WRN

Bit 10: Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed..

Allowed values:
0: Write: Master requests a write transfer
1: Read: Master requests a read transfer

ADD10

Bit 11: 10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed..

Allowed values:
0: Bit7: The master operates in 7-bit addressing mode
1: Bit10: The master operates in 10-bit addressing mode

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed..

Allowed values:
0: Complete: The master sends the complete 10 bit slave address read sequence
1: Partial: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction

START

Bit 13: Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing 1 to the ADDRCF bit in the I2C_ICR register. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit will generate a START condition once the bus is free. Note: Writing 0 to this bit has no effect. The START bit can be set even if the bus is BUSY or I2C is in slave mode. This bit has no effect when RELOAD is set..

Allowed values:
0: NoStart: No Start generation
1: Start: Restart/Start generation

STOP

Bit 14: Stop generation (master mode) The bit is set by software, cleared by hardware when a Stop condition is detected, or when PE = 0. In Master Mode: Note: Writing 0 to this bit has no effect..

Allowed values:
0: NoStop: No Stop generation
1: Stop: Stop generation after current byte transfer

NACK

Bit 15: NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. Note: Writing 0 to this bit has no effect. This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value..

Allowed values:
0: Ack: an ACK is sent after current received byte
1: Nack: a NACK is sent after current received byte

NBYTES

Bits 16-23: Number of bytes The number of bytes to be transmitted/received is programmed there. This field is dont care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed..

Allowed values: 0x0-0xff

RELOAD

Bit 24: NBYTES reload mode This bit is set and cleared by software..

Allowed values:
0: Completed: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)
1: NotCompleted: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)

AUTOEND

Bit 25: Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set..

Allowed values:
0: Software: Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low
1: Automatic: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred

PECBYTE

Bit 26: Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. Note: Writing 0 to this bit has no effect. This bit has no effect when RELOAD is set. This bit has no effect is slave mode when SBC=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
0: NoPec: No PEC transfer
1: Pec: PEC transmission/reception is requested

OAR1

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw
OA1MODE
rw
OA1
rw
Toggle fields

OA1

Bits 0-9: Interface address 7-bit addressing mode: dont care 10-bit addressing mode: bits 9:8 of address Note: These bits can be written only when OA1EN=0. OA1[7:1]: Interface address Bits 7:1 of address Note: These bits can be written only when OA1EN=0. OA1[0]: Interface address 7-bit addressing mode: dont care 10-bit addressing mode: bit 0 of address Note: This bit can be written only when OA1EN=0..

Allowed values: 0x0-0x3ff

OA1MODE

Bit 10: Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0..

Allowed values:
0: Bit7: Own address 1 is a 7-bit address
1: Bit10: Own address 1 is a 10-bit address

OA1EN

Bit 15: Own Address 1 enable.

Allowed values:
0: Disabled: Own address 1 disabled. The received slave address OA1 is NACKed
1: Enabled: Own address 1 enabled. The received slave address OA1 is ACKed

OAR2

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw
OA2MSK
rw
OA2
rw
Toggle fields

OA2

Bits 1-7: Interface address bits 7:1 of address Note: These bits can be written only when OA2EN=0..

Allowed values: 0x0-0x7f

OA2MSK

Bits 8-10: Own Address 2 masks Note: These bits can be written only when OA2EN=0. As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches..

Allowed values:
0: NoMask: No mask
1: Mask1: OA2[1] is masked and don’t care. Only OA2[7:2] are compared
2: Mask2: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
3: Mask3: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
4: Mask4: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
5: Mask5: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
6: Mask6: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
7: Mask7: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged

OA2EN

Bit 15: Own Address 2 enable.

Allowed values:
0: Disabled: Own address 2 disabled. The received slave address OA2 is NACKed
1: Enabled: Own address 2 enabled. The received slave address OA2 is ACKed

TIMINGR

Access: No wait states

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw
SCLDEL
rw
SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw
SCLL
rw
Toggle fields

SCLL

Bits 0-7: SCL low period (master mode) This field is used to generate the SCL low period in master mode. tSCLL = (SCLL+1) x tPRESC Note: SCLL is also used to generate tBUF and tSU:STA timings..

Allowed values: 0x0-0xff

SCLH

Bits 8-15: SCL high period (master mode) This field is used to generate the SCL high period in master mode. tSCLH = (SCLH+1) x tPRESC Note: SCLH is also used to generate tSU:STO and tHD:STA timing..

Allowed values: 0x0-0xff

SDADEL

Bits 16-19: Data hold time This field is used to generate the delay tSDADEL between SCL falling edge and SDA edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSDADEL. tSDADEL= SDADEL x tPRESC Note: SDADEL is used to generate tHD:DAT timing..

Allowed values: 0x0-0xf

SCLDEL

Bits 20-23: Data setup time This field is used to generate a delay tSCLDEL between SDA edge and SCL rising edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSCLDEL. tSCLDEL = (SCLDEL+1) x tPRESC Note: tSCLDEL is used to generate tSU:DAT timing..

Allowed values: 0x0-0xf

PRESC

Bits 28-31: Timing prescaler This field is used to prescale I2CCLK in order to generate the clock period tPRESC used for data setup and hold counters (refer to I2C timings on page9) and for SCL high and low level counters (refer to I2C master initialization on page24). tPRESC = (PRESC+1) x tI2CCLK.

Allowed values: 0x0-0xf

TIMEOUTR

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw
TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw
TIDLE
rw
TIMEOUTA
rw
Toggle fields

TIMEOUTA

Bits 0-11: Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0..

Allowed values: 0x0-0xfff

TIDLE

Bit 12: Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0..

Allowed values:
0: Disabled: TIMEOUTA is used to detect SCL low timeout
1: Enabled: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)

TIMOUTEN

Bit 15: Clock timeout enable.

Allowed values:
0: Disabled: SCL timeout detection is disabled
1: Enabled: SCL timeout detection is enabled

TIMEOUTB

Bits 16-27: Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0..

Allowed values: 0x0-0xfff

TEXTEN

Bit 31: Extended clock timeout enable.

Allowed values:
0: Disabled: Extended clock timeout detection is disabled
1: Enabled: Extended clock timeout detection is enabled

ISR

Access: No wait states

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r
DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r
ALERT
r
TIMEOUT
r
PECERR
r
OVR
r
ARLO
r
BERR
r
TCR
r
TC
r
STOPF
r
NACKF
r
ADDR
r
RXNE
r
TXIS
r/w1s
TXE
r/w1s
Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters) This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software in order to flush the transmit data register I2C_TXDR. Note: This bit is set by hardware when PE=0..

Allowed values:
0: NotEmpty: TXDR register not empty
1: Empty: TXDR register empty

TXIS

Bit 1: Transmit interrupt status (transmitters) This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software when NOSTRETCH=1 only, in order to generate a TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN=1). Note: This bit is cleared by hardware when PE=0..

Allowed values:
0: NotEmpty: The TXDR register is not empty
1: Empty: The TXDR register is empty and the data to be transmitted must be written in the TXDR register

RXNE

Bit 2: Receive data register not empty (receivers) This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. Note: This bit is cleared by hardware when PE=0..

Allowed values:
0: Empty: The RXDR register is empty
1: NotEmpty: Received data is copied into the RXDR register, and is ready to be read

ADDR

Bit 3: Address matched (slave mode) This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. Note: This bit is cleared by hardware when PE=0..

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

NACKF

Bit 4: Not Acknowledge received flag This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. Note: This bit is cleared by hardware when PE=0..

Allowed values:
0: NoNack: No NACK has been received
1: Nack: NACK has been received

STOPF

Bit 5: Stop detection flag This flag is set by hardware when a Stop condition is detected on the bus and the peripheral is involved in this transfer: either as a master, provided that the STOP condition is generated by the peripheral. or as a slave, provided that the peripheral has been addressed previously during this transfer. It is cleared by software by setting the STOPCF bit. Note: This bit is cleared by hardware when PE=0..

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

TC

Bit 6: Transfer Complete (master mode) This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. Note: This bit is cleared by hardware when PE=0..

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

TCR

Bit 7: Transfer Complete Reload This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. Note: This bit is cleared by hardware when PE=0. This flag is only for master mode, or for slave mode when the SBC bit is set..

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

BERR

Bit 8: Bus error This flag is set by hardware when a misplaced Start or Stop condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting BERRCF bit. Note: This bit is cleared by hardware when PE=0..

Allowed values:
0: NoError: No bus error
1: Error: Misplaced Start and Stop condition is detected

ARLO

Bit 9: Arbitration lost This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. Note: This bit is cleared by hardware when PE=0..

Allowed values:
0: NotLost: No arbitration lost
1: Lost: Arbitration lost

OVR

Bit 10: Overrun/Underrun (slave mode) This flag is set by hardware in slave mode with NOSTRETCH=1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. Note: This bit is cleared by hardware when PE=0..

Allowed values:
0: NoOverrun: No overrun/underrun error occurs
1: Overrun: slave mode with NOSTRETCH=1, when an overrun/underrun error occurs

PECERR

Bit 11: PEC Error in reception This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
0: Match: Received PEC does match with PEC register
1: NoMatch: Received PEC does not match with PEC register

TIMEOUT

Bit 12: Timeout or tLOW detection flag This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared by software by setting the TIMEOUTCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
0: NoTimeout: No timeout occured
1: Timeout: Timeout occured

ALERT

Bit 13: SMBus alert This flag is set by hardware when SMBHEN=1 (SMBus host configuration), ALERTEN=1 and a SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by setting the ALERTCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
0: NoAlert: SMBA alert is not detected
1: Alert: SMBA alert event is detected on SMBA pin

BUSY

Bit 15: Bus busy This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a Stop condition is detected, or when PE=0..

Allowed values:
0: NotBusy: No communication is in progress on the bus
1: Busy: A communication is in progress on the bus

DIR

Bit 16: Transfer direction (Slave mode) This flag is updated when an address match event occurs (ADDR=1)..

Allowed values:
0: Write: Write transfer, slave enters receiver mode
1: Read: Read transfer, slave enters transmitter mode

ADDCODE

Bits 17-23: Address match code (Slave mode) These bits are updated with the received address when an address match event occurs (ADDR = 1). In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the 2 MSBs of the address..

Allowed values: 0x0-0x7f

ICR

Access: No wait states

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w1c
TIMOUTCF
w1c
PECCF
w1c
OVRCF
w1c
ARLOCF
w1c
BERRCF
w1c
STOPCF
w1c
NACKCF
w1c
ADDRCF
w1c
Toggle fields

ADDRCF

Bit 3: Address matched flag clear Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears the START bit in the I2C_CR2 register..

Allowed values:
1: Clear: Clears the ADDR flag in ISR register

NACKCF

Bit 4: Not Acknowledge flag clear Writing 1 to this bit clears the ACKF flag in I2C_ISR register..

Allowed values:
1: Clear: Clears the NACK flag in ISR register

STOPCF

Bit 5: Stop detection flag clear Writing 1 to this bit clears the STOPF flag in the I2C_ISR register..

Allowed values:
1: Clear: Clears the STOP flag in ISR register

BERRCF

Bit 8: Bus error flag clear Writing 1 to this bit clears the BERRF flag in the I2C_ISR register..

Allowed values:
1: Clear: Clears the BERR flag in ISR register

ARLOCF

Bit 9: Arbitration Lost flag clear Writing 1 to this bit clears the ARLO flag in the I2C_ISR register..

Allowed values:
1: Clear: Clears the ARLO flag in ISR register

OVRCF

Bit 10: Overrun/Underrun flag clear Writing 1 to this bit clears the OVR flag in the I2C_ISR register..

Allowed values:
1: Clear: Clears the OVR flag in ISR register

PECCF

Bit 11: PEC Error flag clear Writing 1 to this bit clears the PECERR flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
1: Clear: Clears the PEC flag in ISR register

TIMOUTCF

Bit 12: Timeout detection flag clear Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
1: Clear: Clears the TIMOUT flag in ISR register

ALERTCF

Bit 13: Alert flag clear Writing 1 to this bit clears the ALERT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
1: Clear: Clears the ALERT flag in ISR register

PECR

Access: No wait states

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle fields

PEC

Bits 0-7: Packet error checking register This field contains the internal PEC when PECEN=1. The PEC is cleared by hardware when PE=0..

Allowed values: 0x0-0xff

RXDR

Access: No wait states

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: 8-bit receive data Data byte received from the I2C bus..

Allowed values: 0x0-0xff

TXDR

Access: No wait states

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data Data byte to be transmitted to the I2C bus. Note: These bits can be written only when TXE=1..

Allowed values: 0x0-0xff

I2C3

0x40005c00: I2C3

76/76 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 TIMINGR
0x14 TIMEOUTR
0x18 ISR
0x1c ICR
0x20 PECR
0x24 RXDR
0x28 TXDR
Toggle registers

CR1

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw
ALERTEN
rw
SMBDEN
rw
SMBHEN
rw
GCEN
rw
WUPEN
rw
NOSTRETCH
rw
SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw
TXDMAEN
rw
ANFOFF
rw
DNF
rw
ERRIE
rw
TCIE
rw
STOPIE
rw
NACKIE
rw
ADDRIE
rw
RXIE
rw
TXIE
rw
PE
rw
Toggle fields

PE

Bit 0: Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles..

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

TXIE

Bit 1: TX Interrupt enable.

Allowed values:
0: Disabled: Transmit (TXIS) interrupt disabled
1: Enabled: Transmit (TXIS) interrupt enabled

RXIE

Bit 2: RX Interrupt enable.

Allowed values:
0: Disabled: Receive (RXNE) interrupt disabled
1: Enabled: Receive (RXNE) interrupt enabled

ADDRIE

Bit 3: Address match Interrupt enable (slave only).

Allowed values:
0: Disabled: Address match (ADDR) interrupts disabled
1: Enabled: Address match (ADDR) interrupts enabled

NACKIE

Bit 4: Not acknowledge received Interrupt enable.

Allowed values:
0: Disabled: Not acknowledge (NACKF) received interrupts disabled
1: Enabled: Not acknowledge (NACKF) received interrupts enabled

STOPIE

Bit 5: STOP detection Interrupt enable.

Allowed values:
0: Disabled: Stop detection (STOPF) interrupt disabled
1: Enabled: Stop detection (STOPF) interrupt enabled

TCIE

Bit 6: Transfer Complete interrupt enable Note: Any of these events will generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR).

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

ERRIE

Bit 7: Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT).

Allowed values:
0: Disabled: Error detection interrupts disabled
1: Enabled: Error detection interrupts enabled

DNF

Bits 8-11: Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF[3:0] * tI2CCLK ... Note: If the analog filter is also enabled, the digital filter is added to the analog filter. This filter can only be programmed when the I2C is disabled (PE = 0)..

Allowed values:
0: NoFilter: Digital filter disabled
1: Filter1: Digital filter enabled and filtering capability up to 1 tI2CCLK
2: Filter2: Digital filter enabled and filtering capability up to 2 tI2CCLK
3: Filter3: Digital filter enabled and filtering capability up to 3 tI2CCLK
4: Filter4: Digital filter enabled and filtering capability up to 4 tI2CCLK
5: Filter5: Digital filter enabled and filtering capability up to 5 tI2CCLK
6: Filter6: Digital filter enabled and filtering capability up to 6 tI2CCLK
7: Filter7: Digital filter enabled and filtering capability up to 7 tI2CCLK
8: Filter8: Digital filter enabled and filtering capability up to 8 tI2CCLK
9: Filter9: Digital filter enabled and filtering capability up to 9 tI2CCLK
10: Filter10: Digital filter enabled and filtering capability up to 10 tI2CCLK
11: Filter11: Digital filter enabled and filtering capability up to 11 tI2CCLK
12: Filter12: Digital filter enabled and filtering capability up to 12 tI2CCLK
13: Filter13: Digital filter enabled and filtering capability up to 13 tI2CCLK
14: Filter14: Digital filter enabled and filtering capability up to 14 tI2CCLK
15: Filter15: Digital filter enabled and filtering capability up to 15 tI2CCLK

ANFOFF

Bit 12: Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0)..

Allowed values:
0: Enabled: Analog noise filter enabled
1: Disabled: Analog noise filter disabled

TXDMAEN

Bit 14: DMA transmission requests enable.

Allowed values:
0: Disabled: DMA mode disabled for transmission
1: Enabled: DMA mode enabled for transmission

RXDMAEN

Bit 15: DMA reception requests enable.

Allowed values:
0: Disabled: DMA mode disabled for reception
1: Enabled: DMA mode enabled for reception

SBC

Bit 16: Slave byte control This bit is used to enable hardware byte control in slave mode..

Allowed values:
0: Disabled: Slave byte control disabled
1: Enabled: Slave byte control enabled

NOSTRETCH

Bit 17: Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0)..

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

WUPEN

Bit 18: Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation. Note: WUPEN can be set only when DNF = 0000.

Allowed values:
0: Disabled: Wakeup from Stop mode disabled
1: Enabled: Wakeup from Stop mode enabled

GCEN

Bit 19: General call enable.

Allowed values:
0: Disabled: General call disabled. Address 0b00000000 is NACKed
1: Enabled: General call enabled. Address 0b00000000 is ACKed

SMBHEN

Bit 20: SMBus Host address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
0: Disabled: Host address disabled. Address 0b0001000x is NACKed
1: Enabled: Host address enabled. Address 0b0001000x is ACKed

SMBDEN

Bit 21: SMBus Device Default address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
0: Disabled: Device default address disabled. Address 0b1100001x is NACKed
1: Enabled: Device default address enabled. Address 0b1100001x is ACKed

ALERTEN

Bit 22: SMBus alert enable Device mode (SMBHEN=0): Host mode (SMBHEN=1): Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
0: Disabled: In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
1: Enabled: In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported

PECEN

Bit 23: PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

CR2

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
r/w1s
AUTOEND
rw
RELOAD
rw
NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
r/w1s
STOP
r/w1s
START
r/w1s
HEAD10R
rw
ADD10
rw
RD_WRN
rw
SADD
rw
Toggle fields

SADD

Bits 0-9: Slave address bit 0 (master mode) In 7-bit addressing mode (ADD10 = 0): This bit is dont care In 10-bit addressing mode (ADD10 = 1): This bit should be written with bit 0 of the slave address to be sent Note: Changing these bits when the START bit is set is not allowed..

Allowed values: 0x0-0x3ff

RD_WRN

Bit 10: Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed..

Allowed values:
0: Write: Master requests a write transfer
1: Read: Master requests a read transfer

ADD10

Bit 11: 10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed..

Allowed values:
0: Bit7: The master operates in 7-bit addressing mode
1: Bit10: The master operates in 10-bit addressing mode

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed..

Allowed values:
0: Complete: The master sends the complete 10 bit slave address read sequence
1: Partial: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction

START

Bit 13: Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing 1 to the ADDRCF bit in the I2C_ICR register. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit will generate a START condition once the bus is free. Note: Writing 0 to this bit has no effect. The START bit can be set even if the bus is BUSY or I2C is in slave mode. This bit has no effect when RELOAD is set..

Allowed values:
0: NoStart: No Start generation
1: Start: Restart/Start generation

STOP

Bit 14: Stop generation (master mode) The bit is set by software, cleared by hardware when a Stop condition is detected, or when PE = 0. In Master Mode: Note: Writing 0 to this bit has no effect..

Allowed values:
0: NoStop: No Stop generation
1: Stop: Stop generation after current byte transfer

NACK

Bit 15: NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. Note: Writing 0 to this bit has no effect. This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value..

Allowed values:
0: Ack: an ACK is sent after current received byte
1: Nack: a NACK is sent after current received byte

NBYTES

Bits 16-23: Number of bytes The number of bytes to be transmitted/received is programmed there. This field is dont care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed..

Allowed values: 0x0-0xff

RELOAD

Bit 24: NBYTES reload mode This bit is set and cleared by software..

Allowed values:
0: Completed: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)
1: NotCompleted: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)

AUTOEND

Bit 25: Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set..

Allowed values:
0: Software: Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low
1: Automatic: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred

PECBYTE

Bit 26: Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. Note: Writing 0 to this bit has no effect. This bit has no effect when RELOAD is set. This bit has no effect is slave mode when SBC=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
0: NoPec: No PEC transfer
1: Pec: PEC transmission/reception is requested

OAR1

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw
OA1MODE
rw
OA1
rw
Toggle fields

OA1

Bits 0-9: Interface address 7-bit addressing mode: dont care 10-bit addressing mode: bits 9:8 of address Note: These bits can be written only when OA1EN=0. OA1[7:1]: Interface address Bits 7:1 of address Note: These bits can be written only when OA1EN=0. OA1[0]: Interface address 7-bit addressing mode: dont care 10-bit addressing mode: bit 0 of address Note: This bit can be written only when OA1EN=0..

Allowed values: 0x0-0x3ff

OA1MODE

Bit 10: Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0..

Allowed values:
0: Bit7: Own address 1 is a 7-bit address
1: Bit10: Own address 1 is a 10-bit address

OA1EN

Bit 15: Own Address 1 enable.

Allowed values:
0: Disabled: Own address 1 disabled. The received slave address OA1 is NACKed
1: Enabled: Own address 1 enabled. The received slave address OA1 is ACKed

OAR2

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw
OA2MSK
rw
OA2
rw
Toggle fields

OA2

Bits 1-7: Interface address bits 7:1 of address Note: These bits can be written only when OA2EN=0..

Allowed values: 0x0-0x7f

OA2MSK

Bits 8-10: Own Address 2 masks Note: These bits can be written only when OA2EN=0. As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches..

Allowed values:
0: NoMask: No mask
1: Mask1: OA2[1] is masked and don’t care. Only OA2[7:2] are compared
2: Mask2: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
3: Mask3: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
4: Mask4: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
5: Mask5: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
6: Mask6: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
7: Mask7: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged

OA2EN

Bit 15: Own Address 2 enable.

Allowed values:
0: Disabled: Own address 2 disabled. The received slave address OA2 is NACKed
1: Enabled: Own address 2 enabled. The received slave address OA2 is ACKed

TIMINGR

Access: No wait states

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw
SCLDEL
rw
SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw
SCLL
rw
Toggle fields

SCLL

Bits 0-7: SCL low period (master mode) This field is used to generate the SCL low period in master mode. tSCLL = (SCLL+1) x tPRESC Note: SCLL is also used to generate tBUF and tSU:STA timings..

Allowed values: 0x0-0xff

SCLH

Bits 8-15: SCL high period (master mode) This field is used to generate the SCL high period in master mode. tSCLH = (SCLH+1) x tPRESC Note: SCLH is also used to generate tSU:STO and tHD:STA timing..

Allowed values: 0x0-0xff

SDADEL

Bits 16-19: Data hold time This field is used to generate the delay tSDADEL between SCL falling edge and SDA edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSDADEL. tSDADEL= SDADEL x tPRESC Note: SDADEL is used to generate tHD:DAT timing..

Allowed values: 0x0-0xf

SCLDEL

Bits 20-23: Data setup time This field is used to generate a delay tSCLDEL between SDA edge and SCL rising edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSCLDEL. tSCLDEL = (SCLDEL+1) x tPRESC Note: tSCLDEL is used to generate tSU:DAT timing..

Allowed values: 0x0-0xf

PRESC

Bits 28-31: Timing prescaler This field is used to prescale I2CCLK in order to generate the clock period tPRESC used for data setup and hold counters (refer to I2C timings on page9) and for SCL high and low level counters (refer to I2C master initialization on page24). tPRESC = (PRESC+1) x tI2CCLK.

Allowed values: 0x0-0xf

TIMEOUTR

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw
TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw
TIDLE
rw
TIMEOUTA
rw
Toggle fields

TIMEOUTA

Bits 0-11: Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0..

Allowed values: 0x0-0xfff

TIDLE

Bit 12: Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0..

Allowed values:
0: Disabled: TIMEOUTA is used to detect SCL low timeout
1: Enabled: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)

TIMOUTEN

Bit 15: Clock timeout enable.

Allowed values:
0: Disabled: SCL timeout detection is disabled
1: Enabled: SCL timeout detection is enabled

TIMEOUTB

Bits 16-27: Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0..

Allowed values: 0x0-0xfff

TEXTEN

Bit 31: Extended clock timeout enable.

Allowed values:
0: Disabled: Extended clock timeout detection is disabled
1: Enabled: Extended clock timeout detection is enabled

ISR

Access: No wait states

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r
DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r
ALERT
r
TIMEOUT
r
PECERR
r
OVR
r
ARLO
r
BERR
r
TCR
r
TC
r
STOPF
r
NACKF
r
ADDR
r
RXNE
r
TXIS
r/w1s
TXE
r/w1s
Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters) This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software in order to flush the transmit data register I2C_TXDR. Note: This bit is set by hardware when PE=0..

Allowed values:
0: NotEmpty: TXDR register not empty
1: Empty: TXDR register empty

TXIS

Bit 1: Transmit interrupt status (transmitters) This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software when NOSTRETCH=1 only, in order to generate a TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN=1). Note: This bit is cleared by hardware when PE=0..

Allowed values:
0: NotEmpty: The TXDR register is not empty
1: Empty: The TXDR register is empty and the data to be transmitted must be written in the TXDR register

RXNE

Bit 2: Receive data register not empty (receivers) This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. Note: This bit is cleared by hardware when PE=0..

Allowed values:
0: Empty: The RXDR register is empty
1: NotEmpty: Received data is copied into the RXDR register, and is ready to be read

ADDR

Bit 3: Address matched (slave mode) This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. Note: This bit is cleared by hardware when PE=0..

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

NACKF

Bit 4: Not Acknowledge received flag This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. Note: This bit is cleared by hardware when PE=0..

Allowed values:
0: NoNack: No NACK has been received
1: Nack: NACK has been received

STOPF

Bit 5: Stop detection flag This flag is set by hardware when a Stop condition is detected on the bus and the peripheral is involved in this transfer: either as a master, provided that the STOP condition is generated by the peripheral. or as a slave, provided that the peripheral has been addressed previously during this transfer. It is cleared by software by setting the STOPCF bit. Note: This bit is cleared by hardware when PE=0..

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

TC

Bit 6: Transfer Complete (master mode) This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. Note: This bit is cleared by hardware when PE=0..

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

TCR

Bit 7: Transfer Complete Reload This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. Note: This bit is cleared by hardware when PE=0. This flag is only for master mode, or for slave mode when the SBC bit is set..

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

BERR

Bit 8: Bus error This flag is set by hardware when a misplaced Start or Stop condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting BERRCF bit. Note: This bit is cleared by hardware when PE=0..

Allowed values:
0: NoError: No bus error
1: Error: Misplaced Start and Stop condition is detected

ARLO

Bit 9: Arbitration lost This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. Note: This bit is cleared by hardware when PE=0..

Allowed values:
0: NotLost: No arbitration lost
1: Lost: Arbitration lost

OVR

Bit 10: Overrun/Underrun (slave mode) This flag is set by hardware in slave mode with NOSTRETCH=1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. Note: This bit is cleared by hardware when PE=0..

Allowed values:
0: NoOverrun: No overrun/underrun error occurs
1: Overrun: slave mode with NOSTRETCH=1, when an overrun/underrun error occurs

PECERR

Bit 11: PEC Error in reception This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
0: Match: Received PEC does match with PEC register
1: NoMatch: Received PEC does not match with PEC register

TIMEOUT

Bit 12: Timeout or tLOW detection flag This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared by software by setting the TIMEOUTCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
0: NoTimeout: No timeout occured
1: Timeout: Timeout occured

ALERT

Bit 13: SMBus alert This flag is set by hardware when SMBHEN=1 (SMBus host configuration), ALERTEN=1 and a SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by setting the ALERTCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
0: NoAlert: SMBA alert is not detected
1: Alert: SMBA alert event is detected on SMBA pin

BUSY

Bit 15: Bus busy This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a Stop condition is detected, or when PE=0..

Allowed values:
0: NotBusy: No communication is in progress on the bus
1: Busy: A communication is in progress on the bus

DIR

Bit 16: Transfer direction (Slave mode) This flag is updated when an address match event occurs (ADDR=1)..

Allowed values:
0: Write: Write transfer, slave enters receiver mode
1: Read: Read transfer, slave enters transmitter mode

ADDCODE

Bits 17-23: Address match code (Slave mode) These bits are updated with the received address when an address match event occurs (ADDR = 1). In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the 2 MSBs of the address..

Allowed values: 0x0-0x7f

ICR

Access: No wait states

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w1c
TIMOUTCF
w1c
PECCF
w1c
OVRCF
w1c
ARLOCF
w1c
BERRCF
w1c
STOPCF
w1c
NACKCF
w1c
ADDRCF
w1c
Toggle fields

ADDRCF

Bit 3: Address matched flag clear Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears the START bit in the I2C_CR2 register..

Allowed values:
1: Clear: Clears the ADDR flag in ISR register

NACKCF

Bit 4: Not Acknowledge flag clear Writing 1 to this bit clears the ACKF flag in I2C_ISR register..

Allowed values:
1: Clear: Clears the NACK flag in ISR register

STOPCF

Bit 5: Stop detection flag clear Writing 1 to this bit clears the STOPF flag in the I2C_ISR register..

Allowed values:
1: Clear: Clears the STOP flag in ISR register

BERRCF

Bit 8: Bus error flag clear Writing 1 to this bit clears the BERRF flag in the I2C_ISR register..

Allowed values:
1: Clear: Clears the BERR flag in ISR register

ARLOCF

Bit 9: Arbitration Lost flag clear Writing 1 to this bit clears the ARLO flag in the I2C_ISR register..

Allowed values:
1: Clear: Clears the ARLO flag in ISR register

OVRCF

Bit 10: Overrun/Underrun flag clear Writing 1 to this bit clears the OVR flag in the I2C_ISR register..

Allowed values:
1: Clear: Clears the OVR flag in ISR register

PECCF

Bit 11: PEC Error flag clear Writing 1 to this bit clears the PECERR flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
1: Clear: Clears the PEC flag in ISR register

TIMOUTCF

Bit 12: Timeout detection flag clear Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
1: Clear: Clears the TIMOUT flag in ISR register

ALERTCF

Bit 13: Alert flag clear Writing 1 to this bit clears the ALERT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
1: Clear: Clears the ALERT flag in ISR register

PECR

Access: No wait states

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle fields

PEC

Bits 0-7: Packet error checking register This field contains the internal PEC when PECEN=1. The PEC is cleared by hardware when PE=0..

Allowed values: 0x0-0xff

RXDR

Access: No wait states

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: 8-bit receive data Data byte received from the I2C bus..

Allowed values: 0x0-0xff

TXDR

Access: No wait states

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data Data byte to be transmitted to the I2C bus. Note: These bits can be written only when TXE=1..

Allowed values: 0x0-0xff

I2C4

0x58001c00: I2C1

76/76 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 TIMINGR
0x14 TIMEOUTR
0x18 ISR
0x1c ICR
0x20 PECR
0x24 RXDR
0x28 TXDR
Toggle registers

CR1

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw
ALERTEN
rw
SMBDEN
rw
SMBHEN
rw
GCEN
rw
WUPEN
rw
NOSTRETCH
rw
SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw
TXDMAEN
rw
ANFOFF
rw
DNF
rw
ERRIE
rw
TCIE
rw
STOPIE
rw
NACKIE
rw
ADDRIE
rw
RXIE
rw
TXIE
rw
PE
rw
Toggle fields

PE

Bit 0: Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles..

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

TXIE

Bit 1: TX Interrupt enable.

Allowed values:
0: Disabled: Transmit (TXIS) interrupt disabled
1: Enabled: Transmit (TXIS) interrupt enabled

RXIE

Bit 2: RX Interrupt enable.

Allowed values:
0: Disabled: Receive (RXNE) interrupt disabled
1: Enabled: Receive (RXNE) interrupt enabled

ADDRIE

Bit 3: Address match Interrupt enable (slave only).

Allowed values:
0: Disabled: Address match (ADDR) interrupts disabled
1: Enabled: Address match (ADDR) interrupts enabled

NACKIE

Bit 4: Not acknowledge received Interrupt enable.

Allowed values:
0: Disabled: Not acknowledge (NACKF) received interrupts disabled
1: Enabled: Not acknowledge (NACKF) received interrupts enabled

STOPIE

Bit 5: STOP detection Interrupt enable.

Allowed values:
0: Disabled: Stop detection (STOPF) interrupt disabled
1: Enabled: Stop detection (STOPF) interrupt enabled

TCIE

Bit 6: Transfer Complete interrupt enable Note: Any of these events will generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR).

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

ERRIE

Bit 7: Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT).

Allowed values:
0: Disabled: Error detection interrupts disabled
1: Enabled: Error detection interrupts enabled

DNF

Bits 8-11: Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF[3:0] * tI2CCLK ... Note: If the analog filter is also enabled, the digital filter is added to the analog filter. This filter can only be programmed when the I2C is disabled (PE = 0)..

Allowed values:
0: NoFilter: Digital filter disabled
1: Filter1: Digital filter enabled and filtering capability up to 1 tI2CCLK
2: Filter2: Digital filter enabled and filtering capability up to 2 tI2CCLK
3: Filter3: Digital filter enabled and filtering capability up to 3 tI2CCLK
4: Filter4: Digital filter enabled and filtering capability up to 4 tI2CCLK
5: Filter5: Digital filter enabled and filtering capability up to 5 tI2CCLK
6: Filter6: Digital filter enabled and filtering capability up to 6 tI2CCLK
7: Filter7: Digital filter enabled and filtering capability up to 7 tI2CCLK
8: Filter8: Digital filter enabled and filtering capability up to 8 tI2CCLK
9: Filter9: Digital filter enabled and filtering capability up to 9 tI2CCLK
10: Filter10: Digital filter enabled and filtering capability up to 10 tI2CCLK
11: Filter11: Digital filter enabled and filtering capability up to 11 tI2CCLK
12: Filter12: Digital filter enabled and filtering capability up to 12 tI2CCLK
13: Filter13: Digital filter enabled and filtering capability up to 13 tI2CCLK
14: Filter14: Digital filter enabled and filtering capability up to 14 tI2CCLK
15: Filter15: Digital filter enabled and filtering capability up to 15 tI2CCLK

ANFOFF

Bit 12: Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0)..

Allowed values:
0: Enabled: Analog noise filter enabled
1: Disabled: Analog noise filter disabled

TXDMAEN

Bit 14: DMA transmission requests enable.

Allowed values:
0: Disabled: DMA mode disabled for transmission
1: Enabled: DMA mode enabled for transmission

RXDMAEN

Bit 15: DMA reception requests enable.

Allowed values:
0: Disabled: DMA mode disabled for reception
1: Enabled: DMA mode enabled for reception

SBC

Bit 16: Slave byte control This bit is used to enable hardware byte control in slave mode..

Allowed values:
0: Disabled: Slave byte control disabled
1: Enabled: Slave byte control enabled

NOSTRETCH

Bit 17: Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0)..

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

WUPEN

Bit 18: Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation. Note: WUPEN can be set only when DNF = 0000.

Allowed values:
0: Disabled: Wakeup from Stop mode disabled
1: Enabled: Wakeup from Stop mode enabled

GCEN

Bit 19: General call enable.

Allowed values:
0: Disabled: General call disabled. Address 0b00000000 is NACKed
1: Enabled: General call enabled. Address 0b00000000 is ACKed

SMBHEN

Bit 20: SMBus Host address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
0: Disabled: Host address disabled. Address 0b0001000x is NACKed
1: Enabled: Host address enabled. Address 0b0001000x is ACKed

SMBDEN

Bit 21: SMBus Device Default address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
0: Disabled: Device default address disabled. Address 0b1100001x is NACKed
1: Enabled: Device default address enabled. Address 0b1100001x is ACKed

ALERTEN

Bit 22: SMBus alert enable Device mode (SMBHEN=0): Host mode (SMBHEN=1): Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
0: Disabled: In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
1: Enabled: In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported

PECEN

Bit 23: PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

CR2

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
r/w1s
AUTOEND
rw
RELOAD
rw
NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
r/w1s
STOP
r/w1s
START
r/w1s
HEAD10R
rw
ADD10
rw
RD_WRN
rw
SADD
rw
Toggle fields

SADD

Bits 0-9: Slave address bit 0 (master mode) In 7-bit addressing mode (ADD10 = 0): This bit is dont care In 10-bit addressing mode (ADD10 = 1): This bit should be written with bit 0 of the slave address to be sent Note: Changing these bits when the START bit is set is not allowed..

Allowed values: 0x0-0x3ff

RD_WRN

Bit 10: Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed..

Allowed values:
0: Write: Master requests a write transfer
1: Read: Master requests a read transfer

ADD10

Bit 11: 10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed..

Allowed values:
0: Bit7: The master operates in 7-bit addressing mode
1: Bit10: The master operates in 10-bit addressing mode

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed..

Allowed values:
0: Complete: The master sends the complete 10 bit slave address read sequence
1: Partial: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction

START

Bit 13: Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing 1 to the ADDRCF bit in the I2C_ICR register. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit will generate a START condition once the bus is free. Note: Writing 0 to this bit has no effect. The START bit can be set even if the bus is BUSY or I2C is in slave mode. This bit has no effect when RELOAD is set..

Allowed values:
0: NoStart: No Start generation
1: Start: Restart/Start generation

STOP

Bit 14: Stop generation (master mode) The bit is set by software, cleared by hardware when a Stop condition is detected, or when PE = 0. In Master Mode: Note: Writing 0 to this bit has no effect..

Allowed values:
0: NoStop: No Stop generation
1: Stop: Stop generation after current byte transfer

NACK

Bit 15: NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. Note: Writing 0 to this bit has no effect. This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value..

Allowed values:
0: Ack: an ACK is sent after current received byte
1: Nack: a NACK is sent after current received byte

NBYTES

Bits 16-23: Number of bytes The number of bytes to be transmitted/received is programmed there. This field is dont care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed..

Allowed values: 0x0-0xff

RELOAD

Bit 24: NBYTES reload mode This bit is set and cleared by software..

Allowed values:
0: Completed: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)
1: NotCompleted: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)

AUTOEND

Bit 25: Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set..

Allowed values:
0: Software: Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low
1: Automatic: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred

PECBYTE

Bit 26: Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. Note: Writing 0 to this bit has no effect. This bit has no effect when RELOAD is set. This bit has no effect is slave mode when SBC=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
0: NoPec: No PEC transfer
1: Pec: PEC transmission/reception is requested

OAR1

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw
OA1MODE
rw
OA1
rw
Toggle fields

OA1

Bits 0-9: Interface address 7-bit addressing mode: dont care 10-bit addressing mode: bits 9:8 of address Note: These bits can be written only when OA1EN=0. OA1[7:1]: Interface address Bits 7:1 of address Note: These bits can be written only when OA1EN=0. OA1[0]: Interface address 7-bit addressing mode: dont care 10-bit addressing mode: bit 0 of address Note: This bit can be written only when OA1EN=0..

Allowed values: 0x0-0x3ff

OA1MODE

Bit 10: Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0..

Allowed values:
0: Bit7: Own address 1 is a 7-bit address
1: Bit10: Own address 1 is a 10-bit address

OA1EN

Bit 15: Own Address 1 enable.

Allowed values:
0: Disabled: Own address 1 disabled. The received slave address OA1 is NACKed
1: Enabled: Own address 1 enabled. The received slave address OA1 is ACKed

OAR2

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw
OA2MSK
rw
OA2
rw
Toggle fields

OA2

Bits 1-7: Interface address bits 7:1 of address Note: These bits can be written only when OA2EN=0..

Allowed values: 0x0-0x7f

OA2MSK

Bits 8-10: Own Address 2 masks Note: These bits can be written only when OA2EN=0. As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches..

Allowed values:
0: NoMask: No mask
1: Mask1: OA2[1] is masked and don’t care. Only OA2[7:2] are compared
2: Mask2: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
3: Mask3: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
4: Mask4: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
5: Mask5: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
6: Mask6: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
7: Mask7: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged

OA2EN

Bit 15: Own Address 2 enable.

Allowed values:
0: Disabled: Own address 2 disabled. The received slave address OA2 is NACKed
1: Enabled: Own address 2 enabled. The received slave address OA2 is ACKed

TIMINGR

Access: No wait states

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw
SCLDEL
rw
SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw
SCLL
rw
Toggle fields

SCLL

Bits 0-7: SCL low period (master mode) This field is used to generate the SCL low period in master mode. tSCLL = (SCLL+1) x tPRESC Note: SCLL is also used to generate tBUF and tSU:STA timings..

Allowed values: 0x0-0xff

SCLH

Bits 8-15: SCL high period (master mode) This field is used to generate the SCL high period in master mode. tSCLH = (SCLH+1) x tPRESC Note: SCLH is also used to generate tSU:STO and tHD:STA timing..

Allowed values: 0x0-0xff

SDADEL

Bits 16-19: Data hold time This field is used to generate the delay tSDADEL between SCL falling edge and SDA edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSDADEL. tSDADEL= SDADEL x tPRESC Note: SDADEL is used to generate tHD:DAT timing..

Allowed values: 0x0-0xf

SCLDEL

Bits 20-23: Data setup time This field is used to generate a delay tSCLDEL between SDA edge and SCL rising edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSCLDEL. tSCLDEL = (SCLDEL+1) x tPRESC Note: tSCLDEL is used to generate tSU:DAT timing..

Allowed values: 0x0-0xf

PRESC

Bits 28-31: Timing prescaler This field is used to prescale I2CCLK in order to generate the clock period tPRESC used for data setup and hold counters (refer to I2C timings on page9) and for SCL high and low level counters (refer to I2C master initialization on page24). tPRESC = (PRESC+1) x tI2CCLK.

Allowed values: 0x0-0xf

TIMEOUTR

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw
TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw
TIDLE
rw
TIMEOUTA
rw
Toggle fields

TIMEOUTA

Bits 0-11: Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0..

Allowed values: 0x0-0xfff

TIDLE

Bit 12: Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0..

Allowed values:
0: Disabled: TIMEOUTA is used to detect SCL low timeout
1: Enabled: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)

TIMOUTEN

Bit 15: Clock timeout enable.

Allowed values:
0: Disabled: SCL timeout detection is disabled
1: Enabled: SCL timeout detection is enabled

TIMEOUTB

Bits 16-27: Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0..

Allowed values: 0x0-0xfff

TEXTEN

Bit 31: Extended clock timeout enable.

Allowed values:
0: Disabled: Extended clock timeout detection is disabled
1: Enabled: Extended clock timeout detection is enabled

ISR

Access: No wait states

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r
DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r
ALERT
r
TIMEOUT
r
PECERR
r
OVR
r
ARLO
r
BERR
r
TCR
r
TC
r
STOPF
r
NACKF
r
ADDR
r
RXNE
r
TXIS
r/w1s
TXE
r/w1s
Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters) This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software in order to flush the transmit data register I2C_TXDR. Note: This bit is set by hardware when PE=0..

Allowed values:
0: NotEmpty: TXDR register not empty
1: Empty: TXDR register empty

TXIS

Bit 1: Transmit interrupt status (transmitters) This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software when NOSTRETCH=1 only, in order to generate a TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN=1). Note: This bit is cleared by hardware when PE=0..

Allowed values:
0: NotEmpty: The TXDR register is not empty
1: Empty: The TXDR register is empty and the data to be transmitted must be written in the TXDR register

RXNE

Bit 2: Receive data register not empty (receivers) This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. Note: This bit is cleared by hardware when PE=0..

Allowed values:
0: Empty: The RXDR register is empty
1: NotEmpty: Received data is copied into the RXDR register, and is ready to be read

ADDR

Bit 3: Address matched (slave mode) This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. Note: This bit is cleared by hardware when PE=0..

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

NACKF

Bit 4: Not Acknowledge received flag This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. Note: This bit is cleared by hardware when PE=0..

Allowed values:
0: NoNack: No NACK has been received
1: Nack: NACK has been received

STOPF

Bit 5: Stop detection flag This flag is set by hardware when a Stop condition is detected on the bus and the peripheral is involved in this transfer: either as a master, provided that the STOP condition is generated by the peripheral. or as a slave, provided that the peripheral has been addressed previously during this transfer. It is cleared by software by setting the STOPCF bit. Note: This bit is cleared by hardware when PE=0..

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

TC

Bit 6: Transfer Complete (master mode) This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. Note: This bit is cleared by hardware when PE=0..

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

TCR

Bit 7: Transfer Complete Reload This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. Note: This bit is cleared by hardware when PE=0. This flag is only for master mode, or for slave mode when the SBC bit is set..

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

BERR

Bit 8: Bus error This flag is set by hardware when a misplaced Start or Stop condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting BERRCF bit. Note: This bit is cleared by hardware when PE=0..

Allowed values:
0: NoError: No bus error
1: Error: Misplaced Start and Stop condition is detected

ARLO

Bit 9: Arbitration lost This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. Note: This bit is cleared by hardware when PE=0..

Allowed values:
0: NotLost: No arbitration lost
1: Lost: Arbitration lost

OVR

Bit 10: Overrun/Underrun (slave mode) This flag is set by hardware in slave mode with NOSTRETCH=1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. Note: This bit is cleared by hardware when PE=0..

Allowed values:
0: NoOverrun: No overrun/underrun error occurs
1: Overrun: slave mode with NOSTRETCH=1, when an overrun/underrun error occurs

PECERR

Bit 11: PEC Error in reception This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
0: Match: Received PEC does match with PEC register
1: NoMatch: Received PEC does not match with PEC register

TIMEOUT

Bit 12: Timeout or tLOW detection flag This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared by software by setting the TIMEOUTCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
0: NoTimeout: No timeout occured
1: Timeout: Timeout occured

ALERT

Bit 13: SMBus alert This flag is set by hardware when SMBHEN=1 (SMBus host configuration), ALERTEN=1 and a SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by setting the ALERTCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
0: NoAlert: SMBA alert is not detected
1: Alert: SMBA alert event is detected on SMBA pin

BUSY

Bit 15: Bus busy This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a Stop condition is detected, or when PE=0..

Allowed values:
0: NotBusy: No communication is in progress on the bus
1: Busy: A communication is in progress on the bus

DIR

Bit 16: Transfer direction (Slave mode) This flag is updated when an address match event occurs (ADDR=1)..

Allowed values:
0: Write: Write transfer, slave enters receiver mode
1: Read: Read transfer, slave enters transmitter mode

ADDCODE

Bits 17-23: Address match code (Slave mode) These bits are updated with the received address when an address match event occurs (ADDR = 1). In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the 2 MSBs of the address..

Allowed values: 0x0-0x7f

ICR

Access: No wait states

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w1c
TIMOUTCF
w1c
PECCF
w1c
OVRCF
w1c
ARLOCF
w1c
BERRCF
w1c
STOPCF
w1c
NACKCF
w1c
ADDRCF
w1c
Toggle fields

ADDRCF

Bit 3: Address matched flag clear Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears the START bit in the I2C_CR2 register..

Allowed values:
1: Clear: Clears the ADDR flag in ISR register

NACKCF

Bit 4: Not Acknowledge flag clear Writing 1 to this bit clears the ACKF flag in I2C_ISR register..

Allowed values:
1: Clear: Clears the NACK flag in ISR register

STOPCF

Bit 5: Stop detection flag clear Writing 1 to this bit clears the STOPF flag in the I2C_ISR register..

Allowed values:
1: Clear: Clears the STOP flag in ISR register

BERRCF

Bit 8: Bus error flag clear Writing 1 to this bit clears the BERRF flag in the I2C_ISR register..

Allowed values:
1: Clear: Clears the BERR flag in ISR register

ARLOCF

Bit 9: Arbitration Lost flag clear Writing 1 to this bit clears the ARLO flag in the I2C_ISR register..

Allowed values:
1: Clear: Clears the ARLO flag in ISR register

OVRCF

Bit 10: Overrun/Underrun flag clear Writing 1 to this bit clears the OVR flag in the I2C_ISR register..

Allowed values:
1: Clear: Clears the OVR flag in ISR register

PECCF

Bit 11: PEC Error flag clear Writing 1 to this bit clears the PECERR flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
1: Clear: Clears the PEC flag in ISR register

TIMOUTCF

Bit 12: Timeout detection flag clear Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
1: Clear: Clears the TIMOUT flag in ISR register

ALERTCF

Bit 13: Alert flag clear Writing 1 to this bit clears the ALERT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation..

Allowed values:
1: Clear: Clears the ALERT flag in ISR register

PECR

Access: No wait states

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle fields

PEC

Bits 0-7: Packet error checking register This field contains the internal PEC when PECEN=1. The PEC is cleared by hardware when PE=0..

Allowed values: 0x0-0xff

RXDR

Access: No wait states

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: 8-bit receive data Data byte received from the I2C bus..

Allowed values: 0x0-0xff

TXDR

Access: No wait states

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data Data byte to be transmitted to the I2C bus. Note: These bits can be written only when TXE=1..

Allowed values: 0x0-0xff

IWDG

0x58004800: IWDG

7/7 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) KR
0x4 (16-bit) PR
0x8 (16-bit) RLR
0xc (16-bit) SR
0x10 (16-bit) WINR
Toggle registers

KR

Key register

Offset: 0x0, size: 16, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-15: Key value (write only, read 0x0000) These bits must be written by software at regular intervals with the key value 0xAAAA, otherwise the watchdog generates a reset when the counter reaches 0. Writing the key value 0x5555 to enable access to the IWDG_PR, IWDG_RLR and IWDG_WINR registers (see Section23.3.6: Register access protection) Writing the key value CCCCh starts the watchdog (except if the hardware watchdog option is selected).

Allowed values:
21845: Unlock: Enable access to PR, RLR and WINR registers
43690: Feed: Feed watchdog with RLR register value
52428: Start: Start the watchdog

PR

Prescaler register

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PR
rw
Toggle fields

PR

Bits 0-2: Prescaler divider These bits are write access protected see Section23.3.6: Register access protection. They are written by software to select the prescaler divider feeding the counter clock. PVU bit of IWDG_SR must be reset in order to be able to change the prescaler divider. Note: Reading this register returns the prescaler value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the PVU bit in the IWDG_SR register is reset..

Allowed values:
0: DivideBy4: Divider /4
1: DivideBy8: Divider /8
2: DivideBy16: Divider /16
3: DivideBy32: Divider /32
4: DivideBy64: Divider /64
5: DivideBy128: Divider /128
6 (+): DivideBy256: Divider /256

RLR

Reload register

Offset: 0x8, size: 16, reset: 0x00000FFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RL
rw
Toggle fields

RL

Bits 0-11: Watchdog counter reload value These bits are write access protected see Section23.3.6. They are written by software to define the value to be loaded in the watchdog counter each time the value 0xAAAA is written in the IWDG_KR register. The watchdog counter counts down from this value. The timeout period is a function of this value and the clock prescaler. Refer to the datasheet for the timeout information. The RVU bit in the IWDG_SR register must be reset in order to be able to change the reload value. Note: Reading this register returns the reload value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing on this register. For this reason the value read from this register is valid only when the RVU bit in the IWDG_SR register is reset..

Allowed values: 0x0-0xfff

SR

Status register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WVU
r
RVU
r
PVU
r
Toggle fields

PVU

Bit 0: Watchdog prescaler value update This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by hardware when the prescaler update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). Prescaler value can be updated only when PVU bit is reset..

RVU

Bit 1: Watchdog counter reload value update This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). Reload value can be updated only when RVU bit is reset..

WVU

Bit 2: Watchdog counter window value update This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). Window value can be updated only when WVU bit is reset. This bit is generated only if generic window = 1.

WINR

Window register

Offset: 0x10, size: 16, reset: 0x00000FFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WIN
rw
Toggle fields

WIN

Bits 0-11: Watchdog counter window value These bits are write access protected see Section23.3.6. These bits contain the high limit of the window value to be compared to the downcounter. To prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 0x0 The WVU bit in the IWDG_SR register must be reset in order to be able to change the reload value. Note: Reading this register returns the reload value from the VDD voltage domain. This value may not be valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the WVU bit in the IWDG_SR register is reset..

Allowed values: 0x0-0xfff

JPEG

0x52003000: JPEG

8/55 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CONFR0
0x4 CONFR1
0x8 CONFR2
0xc CONFR3
0x10 CONFRN1
0x14 CONFRN2
0x18 CONFRN3
0x1c CONFRN4
0x30 CR
0x34 SR
0x38 CFR
0x40 DIR
0x44 DOR
Toggle registers

CONFR0

JPEG codec control register

Offset: 0x0, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
START
w
Toggle fields

START

Bit 0: Start This bit start or stop the encoding or decoding process. Read this register always return 0..

CONFR1

JPEG codec configuration register 1

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
YSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HDR
rw
NS
rw
COLORSPACE
rw
DE
rw
NF
rw
Toggle fields

NF

Bits 0-1: Number of color components This field defines the number of color components minus 1..

DE

Bit 3: Decoding Enable This bit selects the coding or decoding process.

COLORSPACE

Bits 4-5: Color Space This filed defines the number of quantization tables minus 1 to insert in the output stream..

NS

Bits 6-7: Number of components for Scan This field defines the number of components minus 1 for scan header marker segment..

HDR

Bit 8: Header Processing This bit enable the header processing (generation/parsing)..

YSIZE

Bits 16-31: Y Size This field defines the number of lines in source image..

CONFR2

JPEG codec configuration register 2

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NMCU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMCU
rw
Toggle fields

NMCU

Bits 0-25: Number of MCU For encoding: this field defines the number of MCU units minus 1 to encode. For decoding: this field indicates the number of complete MCU units minus 1 to be decoded (this field is updated after the JPEG header parsing). If the decoded image size has not a X or Y size multiple of 8 or 16 (depending on the sub-sampling process), the resulting incomplete or empty MCU must be added to this value to get the total number of MCU generated..

CONFR3

JPEG codec configuration register 3

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
XSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

XSIZE

Bits 16-31: X size This field defines the number of pixels per line..

CONFRN1

JPEG codec configuration register 4-7

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSF
rw
VSF
rw
NB
rw
QT
rw
HA
rw
HD
rw
Toggle fields

HD

Bit 0: Huffman DC Selects the Huffman table for encoding the DC coefficients..

HA

Bit 1: Huffman AC Selects the Huffman table for encoding the AC coefficients..

QT

Bits 2-3: Quantization Table Selects quantization table associated with a color component..

NB

Bits 4-7: Number of Block Number of data units minus 1 that belong to a particular color in the MCU..

VSF

Bits 8-11: Vertical Sampling Factor Vertical sampling factor for component i..

HSF

Bits 12-15: Horizontal Sampling Factor Horizontal sampling factor for component i..

CONFRN2

JPEG codec configuration register 4-7

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSF
rw
VSF
rw
NB
rw
QT
rw
HA
rw
HD
rw
Toggle fields

HD

Bit 0: Huffman DC Selects the Huffman table for encoding the DC coefficients..

HA

Bit 1: Huffman AC Selects the Huffman table for encoding the AC coefficients..

QT

Bits 2-3: Quantization Table Selects quantization table associated with a color component..

NB

Bits 4-7: Number of Block Number of data units minus 1 that belong to a particular color in the MCU..

VSF

Bits 8-11: Vertical Sampling Factor Vertical sampling factor for component i..

HSF

Bits 12-15: Horizontal Sampling Factor Horizontal sampling factor for component i..

CONFRN3

JPEG codec configuration register 4-7

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSF
rw
VSF
rw
NB
rw
QT
rw
HA
rw
HD
rw
Toggle fields

HD

Bit 0: Huffman DC Selects the Huffman table for encoding the DC coefficients..

HA

Bit 1: Huffman AC Selects the Huffman table for encoding the AC coefficients..

QT

Bits 2-3: Quantization Table Selects quantization table associated with a color component..

NB

Bits 4-7: Number of Block Number of data units minus 1 that belong to a particular color in the MCU..

VSF

Bits 8-11: Vertical Sampling Factor Vertical sampling factor for component i..

HSF

Bits 12-15: Horizontal Sampling Factor Horizontal sampling factor for component i..

CONFRN4

JPEG codec configuration register 4-7

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSF
rw
VSF
rw
NB
rw
QT
rw
HA
rw
HD
rw
Toggle fields

HD

Bit 0: Huffman DC Selects the Huffman table for encoding the DC coefficients..

HA

Bit 1: Huffman AC Selects the Huffman table for encoding the AC coefficients..

QT

Bits 2-3: Quantization Table Selects quantization table associated with a color component..

NB

Bits 4-7: Number of Block Number of data units minus 1 that belong to a particular color in the MCU..

VSF

Bits 8-11: Vertical Sampling Factor Vertical sampling factor for component i..

HSF

Bits 12-15: Horizontal Sampling Factor Horizontal sampling factor for component i..

CR

JPEG control register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFF
rw
IFF
rw
ODMAEN
rw
IDMAEN
rw
HPDIE
rw
EOCIE
rw
OFNEIE
rw
OFTIE
rw
IFNFIE
rw
IFTIE
rw
JCEN
rw
Toggle fields

JCEN

Bit 0: JPEG Core Enable Enable the JPEG codec Core..

IFTIE

Bit 1: Input FIFO Threshold Interrupt Enable This bit enables the interrupt generation when input FIFO reach the threshold..

IFNFIE

Bit 2: Input FIFO Not Full Interrupt Enable This bit enables the interrupt generation when input FIFO is not empty..

OFTIE

Bit 3: Output FIFO Threshold Interrupt Enable This bit enables the interrupt generation when output FIFO reach the threshold..

OFNEIE

Bit 4: Output FIFO Not Empty Interrupt Enable This bit enables the interrupt generation when output FIFO is not empty..

EOCIE

Bit 5: End of Conversion Interrupt Enable This bit enables the interrupt generation on the end of conversion..

HPDIE

Bit 6: Header Parsing Done Interrupt Enable This bit enables the interrupt generation on the Header Parsing Operation..

IDMAEN

Bit 11: Input DMA Enable Enable the DMA request generation for the input FIFO..

ODMAEN

Bit 12: Output DMA Enable Enable the DMA request generation for the output FIFO..

IFF

Bit 13: Input FIFO Flush This bit flush the input FIFO. This bit is always read as 0..

OFF

Bit 14: Output FIFO Flush This bit flush the output FIFO. This bit is always read as 0..

SR

JPEG status register

Offset: 0x34, size: 32, reset: 0x00000006, access: read-only

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COF
r
HPDF
r
EOCF
r
OFNEF
r
OFTF
r
IFNFF
r
IFTF
r
Toggle fields

IFTF

Bit 1: Input FIFO Threshold Flag This bit is set when the input FIFO is not full and is bellow its threshold..

IFNFF

Bit 2: Input FIFO Not Full Flag This bit is set when the input FIFO is not full (a data can be written)..

OFTF

Bit 3: Output FIFO Threshold Flag This bit is set when the output FIFO is not empty and has reach its threshold..

OFNEF

Bit 4: Output FIFO Not Empty Flag This bit is set when the output FIFO is not empty (a data is available)..

EOCF

Bit 5: End of Conversion Flag This bit is set when the JPEG codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO..

HPDF

Bit 6: Header Parsing Done Flag This bit is set in decode mode when the JPEG codec has finished the parsing of the headers and the internal registers have been updated..

COF

Bit 7: Codec Operation Flag This bit is set when when a JPEG codec operation is on going (encoding or decoding)..

CFR

JPEG clear flag register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHPDF
rw
CEOCF
rw
Toggle fields

CEOCF

Bit 5: Clear End of Conversion Flag Writing 1 clears the End of Conversion Flag of the JPEG Status Register..

CHPDF

Bit 6: Clear Header Parsing Done Flag Writing 1 clears the Header Parsing Done Flag of the JPEG Status Register..

DIR

JPEG data input register

Offset: 0x40, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAIN
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAIN
w
Toggle fields

DATAIN

Bits 0-31: Data Input FIFO Input FIFO data register..

DOR

JPEG data output register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAOUT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAOUT
r
Toggle fields

DATAOUT

Bits 0-31: Data Output FIFO Output FIFO data register..

LPTIM1

0x40002400: Low power timer

40/44 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 ICR
0x8 IER
0xc CFGR
0x10 CR
0x14 CMP
0x18 ARR
0x1c CNT
0x24 CFGR2
Toggle registers

ISR

Interrupt and Status Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWN
r
UP
r
ARROK
r
CMPOK
r
EXTTRIG
r
ARRM
r
CMPM
r
Toggle fields

CMPM

Bit 0: Compare match.

Allowed values:
1: Set: Compare match

ARRM

Bit 1: Autoreload match.

Allowed values:
1: Set: Autoreload match

EXTTRIG

Bit 2: External trigger edge event.

Allowed values:
1: Set: External trigger edge event

CMPOK

Bit 3: Compare register update OK.

Allowed values:
1: Set: Compare register update OK

ARROK

Bit 4: Autoreload register update OK.

Allowed values:
1: Set: Autoreload register update OK

UP

Bit 5: Counter direction change down to up.

Allowed values:
1: Set: Counter direction change down to up

DOWN

Bit 6: Counter direction change up to down.

Allowed values:
1: Set: Counter direction change up to down

ICR

Interrupt Clear Register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWNCF
w
UPCF
w
ARROKCF
w
CMPOKCF
w
EXTTRIGCF
w
ARRMCF
w
CMPMCF
w
Toggle fields

CMPMCF

Bit 0: compare match Clear Flag.

Allowed values:
1: Clear: Compare match Clear Flag

ARRMCF

Bit 1: Autoreload match Clear Flag.

Allowed values:
1: Clear: Autoreload match Clear Flag

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

Allowed values:
1: Clear: External trigger valid edge Clear Flag

CMPOKCF

Bit 3: Compare register update OK Clear Flag.

Allowed values:
1: Clear: Compare register update OK Clear Flag

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

Allowed values:
1: Clear: Autoreload register update OK Clear Flag

UPCF

Bit 5: Direction change to UP Clear Flag.

Allowed values:
1: Clear: Direction change to up Clear Flag

DOWNCF

Bit 6: Direction change to down Clear Flag.

Allowed values:
1: Clear: Direction change to down Clear Flag

IER

Interrupt Enable Register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWNIE
rw
UPIE
rw
ARROKIE
rw
CMPOKIE
rw
EXTTRIGIE
rw
ARRMIE
rw
CMPMIE
rw
Toggle fields

CMPMIE

Bit 0: Compare match Interrupt Enable.

Allowed values:
0: Disabled: CMPM interrupt disabled
1: Enabled: CMPM interrupt enabled

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

Allowed values:
0: Disabled: ARRM interrupt disabled
1: Enabled: ARRM interrupt enabled

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

Allowed values:
0: Disabled: EXTTRIG interrupt disabled
1: Enabled: EXTTRIG interrupt enabled

CMPOKIE

Bit 3: Compare register update OK Interrupt Enable.

Allowed values:
0: Disabled: CMPOK interrupt disabled
1: Enabled: CMPOK interrupt enabled

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

Allowed values:
0: Disabled: ARROK interrupt disabled
1: Enabled: ARROK interrupt enabled

UPIE

Bit 5: Direction change to UP Interrupt Enable.

Allowed values:
0: Disabled: UP interrupt disabled
1: Enabled: UP interrupt enabled

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

Allowed values:
0: Disabled: DOWN interrupt disabled
1: Enabled: DOWN interrupt enabled

CFGR

Configuration Register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENC
rw
COUNTMODE
rw
PRELOAD
rw
WAVPOL
rw
WAVE
rw
TIMOUT
rw
TRIGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIGSEL
rw
PRESC
rw
TRGFLT
rw
CKFLT
rw
CKPOL
rw
CKSEL
rw
Toggle fields

CKSEL

Bit 0: Clock selector.

Allowed values:
0: Internal: LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)
1: External: LPTIM is clocked by an external clock source through the LPTIM external Input1

CKPOL

Bits 1-2: Clock Polarity.

Allowed values:
0: RisingEdge: The rising edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 1 is active.
1: FallingEdge: The falling edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 2 is active.
2: BothEdges: Both edges are active edge. If LPTIM is in encoder mode: Encoder sub-mode 3 is active.

CKFLT

Bits 3-4: Configurable digital filter for external clock.

Allowed values:
0: Immediate: Any external clock signal level change is considered as a valid transition
1: Clocks2: External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition
2: Clocks4: External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition
3: Clocks8: External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition

TRGFLT

Bits 6-7: Configurable digital filter for trigger.

Allowed values:
0: Immediate: Any trigger active level change is considered as a valid trigger
1: Clocks2: Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger
2: Clocks4: Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger
3: Clocks8: Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger

PRESC

Bits 9-11: Clock prescaler.

Allowed values:
0: Div1: /1
1: Div2: /2
2: Div4: /4
3: Div8: /8
4: Div16: /16
5: Div32: /32
6: Div64: /64
7: Div128: /128

TRIGSEL

Bits 13-15: Trigger selector.

Allowed values:
0: Trig0: lptim_ext_trig0
1: Trig1: lptim_ext_trig1
2: Trig2: lptim_ext_trig2
3: Trig3: lptim_ext_trig3
4: Trig4: lptim_ext_trig4
5: Trig5: lptim_ext_trig5
6: Trig6: lptim_ext_trig6
7: Trig7: lptim_ext_trig7

TRIGEN

Bits 17-18: Trigger enable and polarity.

Allowed values:
0: SW: Software trigger (counting start is initiated by software)
1: RisingEdge: Rising edge is the active edge
2: FallingEdge: Falling edge is the active edge
3: BothEdges: Both edges are active edges

TIMOUT

Bit 19: Timeout enable.

Allowed values:
0: Disabled: A trigger event arriving when the timer is already started will be ignored
1: Enabled: A trigger event arriving when the timer is already started will reset and restart the counter

WAVE

Bit 20: Waveform shape.

Allowed values:
0: Inactive: Deactivate Set-once mode, PWM / One Pulse waveform (depending on OPMODE bit)
1: Active: Activate the Set-once mode

WAVPOL

Bit 21: Waveform shape polarity.

Allowed values:
0: Positive: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers
1: Negative: The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers

PRELOAD

Bit 22: Registers update mode.

Allowed values:
0: Immediate: Registers are updated after each APB bus write access
1: EndOfPeriod: Registers are updated at the end of the current LPTIM period

COUNTMODE

Bit 23: counter mode enabled.

Allowed values:
0: Internal: The counter is incremented following each internal clock pulse
1: External: The counter is incremented following each valid clock pulse on the LPTIM external Input1

ENC

Bit 24: Encoder mode enable.

Allowed values:
0: Disabled: Encoder mode disabled
1: Enabled: Encoder mode enabled

CR

Control Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

3/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSTARE
rw
COUNTRST
rw
CNTSTRT
rw
SNGSTRT
rw
ENABLE
rw
Toggle fields

ENABLE

Bit 0: LPTIM Enable.

Allowed values:
0: Disabled: LPTIM is disabled
1: Enabled: LPTIM is enabled

SNGSTRT

Bit 1: LPTIM start in single mode.

Allowed values:
1: Start: LPTIM start in Single mode

CNTSTRT

Bit 2: Timer start in continuous mode.

Allowed values:
1: Start: Timer start in Continuous mode

COUNTRST

Bit 3: Counter reset.

RSTARE

Bit 4: Reset after read enable.

CMP

Compare Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Compare value.

Allowed values: 0x0-0xffff

ARR

Autoreload Register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto reload value.

Allowed values: 0x0-0xffff

CNT

Counter Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-15: Counter value.

CFGR2

LPTIM configuration register 2

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IN2SEL
rw
IN1SEL
rw
Toggle fields

IN1SEL

Bits 0-1: LPTIM Input 1 selection.

IN2SEL

Bits 4-5: LPTIM Input 2 selection.

LPTIM2

0x58002400: Low power timer

40/44 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 ICR
0x8 IER
0xc CFGR
0x10 CR
0x14 CMP
0x18 ARR
0x1c CNT
0x24 CFGR2
Toggle registers

ISR

Interrupt and Status Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWN
r
UP
r
ARROK
r
CMPOK
r
EXTTRIG
r
ARRM
r
CMPM
r
Toggle fields

CMPM

Bit 0: Compare match.

Allowed values:
1: Set: Compare match

ARRM

Bit 1: Autoreload match.

Allowed values:
1: Set: Autoreload match

EXTTRIG

Bit 2: External trigger edge event.

Allowed values:
1: Set: External trigger edge event

CMPOK

Bit 3: Compare register update OK.

Allowed values:
1: Set: Compare register update OK

ARROK

Bit 4: Autoreload register update OK.

Allowed values:
1: Set: Autoreload register update OK

UP

Bit 5: Counter direction change down to up.

Allowed values:
1: Set: Counter direction change down to up

DOWN

Bit 6: Counter direction change up to down.

Allowed values:
1: Set: Counter direction change up to down

ICR

Interrupt Clear Register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWNCF
w
UPCF
w
ARROKCF
w
CMPOKCF
w
EXTTRIGCF
w
ARRMCF
w
CMPMCF
w
Toggle fields

CMPMCF

Bit 0: compare match Clear Flag.

Allowed values:
1: Clear: Compare match Clear Flag

ARRMCF

Bit 1: Autoreload match Clear Flag.

Allowed values:
1: Clear: Autoreload match Clear Flag

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

Allowed values:
1: Clear: External trigger valid edge Clear Flag

CMPOKCF

Bit 3: Compare register update OK Clear Flag.

Allowed values:
1: Clear: Compare register update OK Clear Flag

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

Allowed values:
1: Clear: Autoreload register update OK Clear Flag

UPCF

Bit 5: Direction change to UP Clear Flag.

Allowed values:
1: Clear: Direction change to up Clear Flag

DOWNCF

Bit 6: Direction change to down Clear Flag.

Allowed values:
1: Clear: Direction change to down Clear Flag

IER

Interrupt Enable Register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWNIE
rw
UPIE
rw
ARROKIE
rw
CMPOKIE
rw
EXTTRIGIE
rw
ARRMIE
rw
CMPMIE
rw
Toggle fields

CMPMIE

Bit 0: Compare match Interrupt Enable.

Allowed values:
0: Disabled: CMPM interrupt disabled
1: Enabled: CMPM interrupt enabled

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

Allowed values:
0: Disabled: ARRM interrupt disabled
1: Enabled: ARRM interrupt enabled

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

Allowed values:
0: Disabled: EXTTRIG interrupt disabled
1: Enabled: EXTTRIG interrupt enabled

CMPOKIE

Bit 3: Compare register update OK Interrupt Enable.

Allowed values:
0: Disabled: CMPOK interrupt disabled
1: Enabled: CMPOK interrupt enabled

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

Allowed values:
0: Disabled: ARROK interrupt disabled
1: Enabled: ARROK interrupt enabled

UPIE

Bit 5: Direction change to UP Interrupt Enable.

Allowed values:
0: Disabled: UP interrupt disabled
1: Enabled: UP interrupt enabled

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

Allowed values:
0: Disabled: DOWN interrupt disabled
1: Enabled: DOWN interrupt enabled

CFGR

Configuration Register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENC
rw
COUNTMODE
rw
PRELOAD
rw
WAVPOL
rw
WAVE
rw
TIMOUT
rw
TRIGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIGSEL
rw
PRESC
rw
TRGFLT
rw
CKFLT
rw
CKPOL
rw
CKSEL
rw
Toggle fields

CKSEL

Bit 0: Clock selector.

Allowed values:
0: Internal: LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)
1: External: LPTIM is clocked by an external clock source through the LPTIM external Input1

CKPOL

Bits 1-2: Clock Polarity.

Allowed values:
0: RisingEdge: The rising edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 1 is active.
1: FallingEdge: The falling edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 2 is active.
2: BothEdges: Both edges are active edge. If LPTIM is in encoder mode: Encoder sub-mode 3 is active.

CKFLT

Bits 3-4: Configurable digital filter for external clock.

Allowed values:
0: Immediate: Any external clock signal level change is considered as a valid transition
1: Clocks2: External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition
2: Clocks4: External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition
3: Clocks8: External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition

TRGFLT

Bits 6-7: Configurable digital filter for trigger.

Allowed values:
0: Immediate: Any trigger active level change is considered as a valid trigger
1: Clocks2: Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger
2: Clocks4: Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger
3: Clocks8: Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger

PRESC

Bits 9-11: Clock prescaler.

Allowed values:
0: Div1: /1
1: Div2: /2
2: Div4: /4
3: Div8: /8
4: Div16: /16
5: Div32: /32
6: Div64: /64
7: Div128: /128

TRIGSEL

Bits 13-15: Trigger selector.

Allowed values:
0: Trig0: lptim_ext_trig0
1: Trig1: lptim_ext_trig1
2: Trig2: lptim_ext_trig2
3: Trig3: lptim_ext_trig3
4: Trig4: lptim_ext_trig4
5: Trig5: lptim_ext_trig5
6: Trig6: lptim_ext_trig6
7: Trig7: lptim_ext_trig7

TRIGEN

Bits 17-18: Trigger enable and polarity.

Allowed values:
0: SW: Software trigger (counting start is initiated by software)
1: RisingEdge: Rising edge is the active edge
2: FallingEdge: Falling edge is the active edge
3: BothEdges: Both edges are active edges

TIMOUT

Bit 19: Timeout enable.

Allowed values:
0: Disabled: A trigger event arriving when the timer is already started will be ignored
1: Enabled: A trigger event arriving when the timer is already started will reset and restart the counter

WAVE

Bit 20: Waveform shape.

Allowed values:
0: Inactive: Deactivate Set-once mode, PWM / One Pulse waveform (depending on OPMODE bit)
1: Active: Activate the Set-once mode

WAVPOL

Bit 21: Waveform shape polarity.

Allowed values:
0: Positive: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers
1: Negative: The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers

PRELOAD

Bit 22: Registers update mode.

Allowed values:
0: Immediate: Registers are updated after each APB bus write access
1: EndOfPeriod: Registers are updated at the end of the current LPTIM period

COUNTMODE

Bit 23: counter mode enabled.

Allowed values:
0: Internal: The counter is incremented following each internal clock pulse
1: External: The counter is incremented following each valid clock pulse on the LPTIM external Input1

ENC

Bit 24: Encoder mode enable.

Allowed values:
0: Disabled: Encoder mode disabled
1: Enabled: Encoder mode enabled

CR

Control Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

3/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSTARE
rw
COUNTRST
rw
CNTSTRT
rw
SNGSTRT
rw
ENABLE
rw
Toggle fields

ENABLE

Bit 0: LPTIM Enable.

Allowed values:
0: Disabled: LPTIM is disabled
1: Enabled: LPTIM is enabled

SNGSTRT

Bit 1: LPTIM start in single mode.

Allowed values:
1: Start: LPTIM start in Single mode

CNTSTRT

Bit 2: Timer start in continuous mode.

Allowed values:
1: Start: Timer start in Continuous mode

COUNTRST

Bit 3: Counter reset.

RSTARE

Bit 4: Reset after read enable.

CMP

Compare Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Compare value.

Allowed values: 0x0-0xffff

ARR

Autoreload Register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto reload value.

Allowed values: 0x0-0xffff

CNT

Counter Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-15: Counter value.

CFGR2

LPTIM configuration register 2

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IN2SEL
rw
IN1SEL
rw
Toggle fields

IN1SEL

Bits 0-1: LPTIM Input 1 selection.

IN2SEL

Bits 4-5: LPTIM Input 2 selection.

LPTIM3

0x58002800: Low power timer

40/43 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 ICR
0x8 IER
0xc CFGR
0x10 CR
0x14 CMP
0x18 ARR
0x1c CNT
0x24 CFGR2
Toggle registers

ISR

Interrupt and Status Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWN
r
UP
r
ARROK
r
CMPOK
r
EXTTRIG
r
ARRM
r
CMPM
r
Toggle fields

CMPM

Bit 0: Compare match.

Allowed values:
1: Set: Compare match

ARRM

Bit 1: Autoreload match.

Allowed values:
1: Set: Autoreload match

EXTTRIG

Bit 2: External trigger edge event.

Allowed values:
1: Set: External trigger edge event

CMPOK

Bit 3: Compare register update OK.

Allowed values:
1: Set: Compare register update OK

ARROK

Bit 4: Autoreload register update OK.

Allowed values:
1: Set: Autoreload register update OK

UP

Bit 5: Counter direction change down to up.

Allowed values:
1: Set: Counter direction change down to up

DOWN

Bit 6: Counter direction change up to down.

Allowed values:
1: Set: Counter direction change up to down

ICR

Interrupt Clear Register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWNCF
w
UPCF
w
ARROKCF
w
CMPOKCF
w
EXTTRIGCF
w
ARRMCF
w
CMPMCF
w
Toggle fields

CMPMCF

Bit 0: compare match Clear Flag.

Allowed values:
1: Clear: Compare match Clear Flag

ARRMCF

Bit 1: Autoreload match Clear Flag.

Allowed values:
1: Clear: Autoreload match Clear Flag

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

Allowed values:
1: Clear: External trigger valid edge Clear Flag

CMPOKCF

Bit 3: Compare register update OK Clear Flag.

Allowed values:
1: Clear: Compare register update OK Clear Flag

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

Allowed values:
1: Clear: Autoreload register update OK Clear Flag

UPCF

Bit 5: Direction change to UP Clear Flag.

Allowed values:
1: Clear: Direction change to up Clear Flag

DOWNCF

Bit 6: Direction change to down Clear Flag.

Allowed values:
1: Clear: Direction change to down Clear Flag

IER

Interrupt Enable Register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWNIE
rw
UPIE
rw
ARROKIE
rw
CMPOKIE
rw
EXTTRIGIE
rw
ARRMIE
rw
CMPMIE
rw
Toggle fields

CMPMIE

Bit 0: Compare match Interrupt Enable.

Allowed values:
0: Disabled: CMPM interrupt disabled
1: Enabled: CMPM interrupt enabled

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

Allowed values:
0: Disabled: ARRM interrupt disabled
1: Enabled: ARRM interrupt enabled

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

Allowed values:
0: Disabled: EXTTRIG interrupt disabled
1: Enabled: EXTTRIG interrupt enabled

CMPOKIE

Bit 3: Compare register update OK Interrupt Enable.

Allowed values:
0: Disabled: CMPOK interrupt disabled
1: Enabled: CMPOK interrupt enabled

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

Allowed values:
0: Disabled: ARROK interrupt disabled
1: Enabled: ARROK interrupt enabled

UPIE

Bit 5: Direction change to UP Interrupt Enable.

Allowed values:
0: Disabled: UP interrupt disabled
1: Enabled: UP interrupt enabled

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

Allowed values:
0: Disabled: DOWN interrupt disabled
1: Enabled: DOWN interrupt enabled

CFGR

Configuration Register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENC
rw
COUNTMODE
rw
PRELOAD
rw
WAVPOL
rw
WAVE
rw
TIMOUT
rw
TRIGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIGSEL
rw
PRESC
rw
TRGFLT
rw
CKFLT
rw
CKPOL
rw
CKSEL
rw
Toggle fields

CKSEL

Bit 0: Clock selector.

Allowed values:
0: Internal: LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)
1: External: LPTIM is clocked by an external clock source through the LPTIM external Input1

CKPOL

Bits 1-2: Clock Polarity.

Allowed values:
0: RisingEdge: The rising edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 1 is active.
1: FallingEdge: The falling edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 2 is active.
2: BothEdges: Both edges are active edge. If LPTIM is in encoder mode: Encoder sub-mode 3 is active.

CKFLT

Bits 3-4: Configurable digital filter for external clock.

Allowed values:
0: Immediate: Any external clock signal level change is considered as a valid transition
1: Clocks2: External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition
2: Clocks4: External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition
3: Clocks8: External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition

TRGFLT

Bits 6-7: Configurable digital filter for trigger.

Allowed values:
0: Immediate: Any trigger active level change is considered as a valid trigger
1: Clocks2: Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger
2: Clocks4: Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger
3: Clocks8: Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger

PRESC

Bits 9-11: Clock prescaler.

Allowed values:
0: Div1: /1
1: Div2: /2
2: Div4: /4
3: Div8: /8
4: Div16: /16
5: Div32: /32
6: Div64: /64
7: Div128: /128

TRIGSEL

Bits 13-15: Trigger selector.

Allowed values:
0: Trig0: lptim_ext_trig0
1: Trig1: lptim_ext_trig1
2: Trig2: lptim_ext_trig2
3: Trig3: lptim_ext_trig3
4: Trig4: lptim_ext_trig4
5: Trig5: lptim_ext_trig5
6: Trig6: lptim_ext_trig6
7: Trig7: lptim_ext_trig7

TRIGEN

Bits 17-18: Trigger enable and polarity.

Allowed values:
0: SW: Software trigger (counting start is initiated by software)
1: RisingEdge: Rising edge is the active edge
2: FallingEdge: Falling edge is the active edge
3: BothEdges: Both edges are active edges

TIMOUT

Bit 19: Timeout enable.

Allowed values:
0: Disabled: A trigger event arriving when the timer is already started will be ignored
1: Enabled: A trigger event arriving when the timer is already started will reset and restart the counter

WAVE

Bit 20: Waveform shape.

Allowed values:
0: Inactive: Deactivate Set-once mode, PWM / One Pulse waveform (depending on OPMODE bit)
1: Active: Activate the Set-once mode

WAVPOL

Bit 21: Waveform shape polarity.

Allowed values:
0: Positive: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers
1: Negative: The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers

PRELOAD

Bit 22: Registers update mode.

Allowed values:
0: Immediate: Registers are updated after each APB bus write access
1: EndOfPeriod: Registers are updated at the end of the current LPTIM period

COUNTMODE

Bit 23: counter mode enabled.

Allowed values:
0: Internal: The counter is incremented following each internal clock pulse
1: External: The counter is incremented following each valid clock pulse on the LPTIM external Input1

ENC

Bit 24: Encoder mode enable.

Allowed values:
0: Disabled: Encoder mode disabled
1: Enabled: Encoder mode enabled

CR

Control Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

3/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSTARE
rw
COUNTRST
rw
CNTSTRT
rw
SNGSTRT
rw
ENABLE
rw
Toggle fields

ENABLE

Bit 0: LPTIM Enable.

Allowed values:
0: Disabled: LPTIM is disabled
1: Enabled: LPTIM is enabled

SNGSTRT

Bit 1: LPTIM start in single mode.

Allowed values:
1: Start: LPTIM start in Single mode

CNTSTRT

Bit 2: Timer start in continuous mode.

Allowed values:
1: Start: Timer start in Continuous mode

COUNTRST

Bit 3: Counter reset.

RSTARE

Bit 4: Reset after read enable.

CMP

Compare Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Compare value.

Allowed values: 0x0-0xffff

ARR

Autoreload Register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto reload value.

Allowed values: 0x0-0xffff

CNT

Counter Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-15: Counter value.

CFGR2

LPTIM configuration register 2

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IN1SEL
rw
Toggle fields

IN1SEL

Bits 0-1: LPTIM Input 1 selection.

LPUART1

0x58000c00: LPUART1

84/89 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

21/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw
TXFEIE
rw
FIFOEN
rw
M1
rw
DEAT
rw
DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMIE
rw
MME
rw
M0
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
UESM
rw
UE
rw
Toggle fields

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

DEDT

Bits 16-20: Driver Enable deassertion time.

Allowed values: 0x0-0x1f

DEAT

Bits 21-25: Driver Enable assertion time.

Allowed values: 0x0-0x1f

M1

Bit 28: Word length.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

FIFOEN

Bit 29: FIFO mode enable.

Allowed values:
0: Disabled: FIFO mode is disabled
1: Enabled: FIFO mode is enabled

TXFEIE

Bit 30: TXFIFO empty interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when TXFE = 1 in the USART_ISR register

RXFFIE

Bit 31: RXFIFO Full interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when RXFF = 1 in the USART_ISR register

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw
MSBFIRST
rw
DATAINV
rw
TXINV
rw
RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw
STOP
rw
ADDM7
rw
Toggle fields

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
2: Stop2: 2 stop bit

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0x0-0xff

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw
RXFTIE
rw
RXFTCFG
rw
TXFTIE
rw
WUFIE
rw
WUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw
DEM
rw
DDRE
rw
OVRDIS
rw
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
HDSEL
rw
EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

OVRDIS

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

TXFTIE

Bit 23: TXFIFO threshold interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration.

Allowed values:
0: Depth_1_8: RXFIFO reaches 1/8 of its depth
1: Depth_1_4: RXFIFO reaches 1/4 of its depth
2: Depth_1_2: RXFIFO reaches 1/2 of its depth
3: Depth_3_4: RXFIFO reaches 3/4 of its depth
4: Depth_7_8: RXFIFO reaches 7/8 of its depth
5: Full: RXFIFO becomes full

RXFTIE

Bit 28: RXFIFO threshold interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG

TXFTCFG

Bits 29-31: TXFIFO threshold configuration.

Allowed values:
0: Depth_1_8: TXFIFO reaches 1/8 of its depth
1: Depth_1_4: TXFIFO reaches 1/4 of its depth
2: Depth_1_2: TXFIFO reaches 1/2 of its depth
3: Depth_3_4: TXFIFO reaches 3/4 of its depth
4: Depth_7_8: TXFIFO reaches 7/8 of its depth
5: Empty: TXFIFO becomes empty

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-19: BRR.

Allowed values: 0x0-0xfffff

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw
PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw
RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

4/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w
RXFRQ
w
MMRQ
w
SBKRQ
w
ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: Transmit data flush request.

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

21/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r
RXFT
r
RXFF
r
TXFE
r
REACK
r
TEACK
r
WUF
r
RWU
r
SBKF
r
CMF
r
BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTS
r
CTSIF
r
TXE
r
TC
r
RXNE
r
IDLE
r
ORE
r
NE
r
FE
r
PE
r
Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NE

Bit 2: NE.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

Allowed values:
0: Active: Receiver in Active mode
1: Mute: Receiver in Mute mode

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFIFO Empty.

Allowed values:
0: NotEmpty: TXFIFO not empty.
1: Empty: TXFIFO empty.

RXFF

Bit 24: RXFIFO Full.

Allowed values:
0: NotFull: RXFIFO not full.
1: Full: RXFIFO Full.

RXFT

Bit 26: RXFIFO threshold flag.

Allowed values:
0: NotReached: Receive FIFO does not reach the programmed threshold.
1: Reached: Receive FIFO reached the programmed threshold.

TXFT

Bit 27: TXFIFO threshold flag.

Allowed values:
0: NotReached: TXFIFO does not reach the programmed threshold.
1: Reached: TXFIFO reached the programmed threshold.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w1c
CMCF
w1c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSCF
w1c
TCCF
w1c
IDLECF
w1c
ORECF
w1c
NCF
w1c
FECF
w1c
PECF
w1c
Toggle fields

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

Allowed values: 0x0-0x1ff

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

Allowed values: 0x0-0x1ff

PRESC

Prescaler register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: Clock prescaler.

Allowed values:
0: Div1: /1
1: Div2: /2
2: Div4: /4
3: Div6: /6
4: Div8: /8
5: Div10: /10
6: Div12: /12
7: Div16: /16
8: Div32: /32
9: Div64: /64
10: Div128: /128
11: Div256: /256

LTDC

0x50001000: LCD-TFT Controller

93/93 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x8 SSCR
0xc BPCR
0x10 AWCR
0x14 TWCR
0x18 GCR
0x24 SRCR
0x2c BCCR
0x34 IER
0x38 ISR
0x3c ICR
0x40 LIPCR
0x44 CPSR
0x48 CDSR
0x84 CR [1]
0x88 WHPCR [1]
0x8c WVPCR [1]
0x90 CKCR [1]
0x94 PFCR [1]
0x98 CACR [1]
0x9c DCCR [1]
0xa0 BFCR [1]
0xac CFBAR [1]
0xb0 CFBLR [1]
0xb4 CFBLNR [1]
0xc4 CLUTWR [1]
0x104 CR [2]
0x108 WHPCR [2]
0x10c WVPCR [2]
0x110 CKCR [2]
0x114 PFCR [2]
0x118 CACR [2]
0x11c DCCR [2]
0x120 BFCR [2]
0x12c CFBAR [2]
0x130 CFBLR [2]
0x134 CFBLNR [2]
0x144 CLUTWR [2]
Toggle registers

SSCR

Synchronization Size Configuration Register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HSW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VSH
rw
Toggle fields

VSH

Bits 0-10: Vertical Synchronization Height (in units of horizontal scan line).

Allowed values: 0x0-0x7ff

HSW

Bits 16-27: Horizontal Synchronization Width (in units of pixel clock period).

Allowed values: 0x0-0xfff

BPCR

Back Porch Configuration Register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AHBP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AVBP
rw
Toggle fields

AVBP

Bits 0-10: Accumulated Vertical back porch (in units of horizontal scan line).

Allowed values: 0x0-0x7ff

AHBP

Bits 16-27: Accumulated Horizontal back porch (in units of pixel clock period).

Allowed values: 0x0-0xfff

AWCR

Active Width Configuration Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AAW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AAH
rw
Toggle fields

AAH

Bits 0-10: Accumulated Active Height (in units of horizontal scan line).

Allowed values: 0x0-0x7ff

AAW

Bits 16-27: Accumulated Active Width (in units of pixel clock period).

Allowed values: 0x0-0xfff

TWCR

Total Width Configuration Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TOTALW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOTALH
rw
Toggle fields

TOTALH

Bits 0-10: Total Height (in units of horizontal scan line).

Allowed values: 0x0-0x7ff

TOTALW

Bits 16-27: Total Width (in units of pixel clock period).

Allowed values: 0x0-0xfff

GCR

Global Control Register

Offset: 0x18, size: 32, reset: 0x00002220, access: Unspecified

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HSPOL
rw
VSPOL
rw
DEPOL
rw
PCPOL
rw
DEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DRW
r
DGW
r
DBW
r
LTDCEN
rw
Toggle fields

LTDCEN

Bit 0: LCD-TFT controller enable bit.

Allowed values:
0: Disabled: LCD-TFT controller disabled
1: Enabled: LCD-TFT controller enabled

DBW

Bits 4-6: Dither Blue Width.

DGW

Bits 8-10: Dither Green Width.

DRW

Bits 12-14: Dither Red Width.

DEN

Bit 16: Dither Enable.

Allowed values:
0: Disabled: Dither disabled
1: Enabled: Dither enabled

PCPOL

Bit 28: Pixel Clock Polarity.

Allowed values:
0: RisingEdge: Pixel clock on rising edge
1: FallingEdge: Pixel clock on falling edge

DEPOL

Bit 29: Data Enable Polarity.

Allowed values:
0: ActiveLow: Data enable polarity is active low
1: ActiveHigh: Data enable polarity is active high

VSPOL

Bit 30: Vertical Synchronization Polarity.

Allowed values:
0: ActiveLow: Vertical synchronization polarity is active low
1: ActiveHigh: Vertical synchronization polarity is active high

HSPOL

Bit 31: Horizontal Synchronization Polarity.

Allowed values:
0: ActiveLow: Horizontal synchronization polarity is active low
1: ActiveHigh: Horizontal synchronization polarity is active high

SRCR

Shadow Reload Configuration Register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VBR
rw
IMR
rw
Toggle fields

IMR

Bit 0: Immediate Reload.

Allowed values:
0: NoEffect: This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set)
1: Reload: The shadow registers are reloaded immediately. This bit is set by software and cleared only by hardware after reload

VBR

Bit 1: Vertical Blanking Reload.

Allowed values:
0: NoEffect: This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set)
1: Reload: The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area).

BCCR

Background Color Configuration Register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BCRED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCGREEN
rw
BCBLUE
rw
Toggle fields

BCBLUE

Bits 0-7: Background Color Blue value.

Allowed values: 0x0-0xff

BCGREEN

Bits 8-15: Background Color Green value.

Allowed values: 0x0-0xff

BCRED

Bits 16-23: Background Color Red value.

Allowed values: 0x0-0xff

IER

Interrupt Enable Register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RRIE
rw
TERRIE
rw
FUIE
rw
LIE
rw
Toggle fields

LIE

Bit 0: Line Interrupt Enable.

Allowed values:
0: Disabled: Line interrupt disabled
1: Enabled: Line interrupt enabled

FUIE

Bit 1: FIFO Underrun Interrupt Enable.

Allowed values:
0: Disabled: FIFO underrun interrupt disabled
1: Enabled: FIFO underrun interrupt enabled

TERRIE

Bit 2: Transfer Error Interrupt Enable.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

RRIE

Bit 3: Register Reload interrupt enable.

Allowed values:
0: Disabled: Register reload interrupt disabled
1: Enabled: Register reload interrupt enabled

ISR

Interrupt Status Register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RRIF
r
TERRIF
r
FUIF
r
LIF
r
Toggle fields

LIF

Bit 0: Line Interrupt flag.

Allowed values:
0: NotReached: Programmed line not reached
1: Reached: Line interrupt generated when a programmed line is reached

FUIF

Bit 1: FIFO Underrun Interrupt flag.

Allowed values:
0: NoUnderrun: No FIFO underrun
1: Underrun: FIFO underrun interrupt generated, if one of the layer FIFOs is empty and pixel data is read from the FIFO

TERRIF

Bit 2: Transfer Error interrupt flag.

Allowed values:
0: NoError: No transfer error
1: Error: Transfer error interrupt generated when a bus error occurs

RRIF

Bit 3: Register Reload Interrupt Flag.

Allowed values:
0: NoReload: No register reload
1: Reload: Register reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached)

ICR

Interrupt Clear Register

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRRIF
w1c
CTERRIF
w1c
CFUIF
w1c
CLIF
w1c
Toggle fields

CLIF

Bit 0: Clears the Line Interrupt Flag.

Allowed values:
1: Clear: Clears the LIF flag in the ISR register

CFUIF

Bit 1: Clears the FIFO Underrun Interrupt flag.

Allowed values:
1: Clear: Clears the FUIF flag in the ISR register

CTERRIF

Bit 2: Clears the Transfer Error Interrupt Flag.

Allowed values:
1: Clear: Clears the TERRIF flag in the ISR register

CRRIF

Bit 3: Clears Register Reload Interrupt Flag.

Allowed values:
1: Clear: Clears the RRIF flag in the ISR register

LIPCR

Line Interrupt Position Configuration Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LIPOS
rw
Toggle fields

LIPOS

Bits 0-10: Line Interrupt Position.

Allowed values: 0x0-0x7ff

CPSR

Current Position Status Register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CXPOS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CYPOS
r
Toggle fields

CYPOS

Bits 0-15: Current Y Position.

CXPOS

Bits 16-31: Current X Position.

CDSR

Current Display Status Register

Offset: 0x48, size: 32, reset: 0x0000000F, access: read-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSYNCS
r
VSYNCS
r
HDES
r
VDES
r
Toggle fields

VDES

Bit 0: Vertical Data Enable display Status.

Allowed values:
0: NotActive: Currently not in vertical Data Enable phase
1: Active: Currently in vertical Data Enable phase

HDES

Bit 1: Horizontal Data Enable display Status.

Allowed values:
0: NotActive: Currently not in horizontal Data Enable phase
1: Active: Currently in horizontal Data Enable phase

VSYNCS

Bit 2: Vertical Synchronization display Status.

Allowed values:
0: NotActive: Currently not in VSYNC phase
1: Active: Currently in VSYNC phase

HSYNCS

Bit 3: Horizontal Synchronization display Status.

Allowed values:
0: NotActive: Currently not in HSYNC phase
1: Active: Currently in HSYNC phase

CR [1]

Layerx Control Register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLUTEN
rw
COLKEN
rw
LEN
rw
Toggle fields

LEN

Bit 0: Layer Enable.

Allowed values:
0: Disabled: Layer disabled
1: Enabled: Layer enabled

COLKEN

Bit 1: Color Keying Enable.

Allowed values:
0: Disabled: Color keying disabled
1: Enabled: Color keying enabled

CLUTEN

Bit 4: Color Look-Up Table Enable.

Allowed values:
0: Disabled: Color look-up table disabled
1: Enabled: Color look-up table enabled

WHPCR [1]

Layerx Window Horizontal Position Configuration Register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WHSPPOS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WHSTPOS
rw
Toggle fields

WHSTPOS

Bits 0-11: Window Horizontal Start Position.

Allowed values: 0x0-0xfff

WHSPPOS

Bits 16-27: Window Horizontal Stop Position.

Allowed values: 0x0-0xfff

WVPCR [1]

Layerx Window Vertical Position Configuration Register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WVSPPOS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WVSTPOS
rw
Toggle fields

WVSTPOS

Bits 0-10: Window Vertical Start Position.

Allowed values: 0x0-0x7ff

WVSPPOS

Bits 16-26: Window Vertical Stop Position.

Allowed values: 0x0-0x7ff

CKCR [1]

Layerx Color Keying Configuration Register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CKRED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKGREEN
rw
CKBLUE
rw
Toggle fields

CKBLUE

Bits 0-7: Color Key Blue value.

Allowed values: 0x0-0xff

CKGREEN

Bits 8-15: Color Key Green value.

Allowed values: 0x0-0xff

CKRED

Bits 16-23: Color Key Red value.

Allowed values: 0x0-0xff

PFCR [1]

Layerx Pixel Format Configuration Register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PF
rw
Toggle fields

PF

Bits 0-2: Pixel Format.

Allowed values:
0: ARGB8888: ARGB8888
1: RGB888: RGB888
2: RGB565: RGB565
3: ARGB1555: ARGB1555
4: ARGB4444: ARGB4444
5: L8: L8 (8-bit luminance)
6: AL44: AL44 (4-bit alpha, 4-bit luminance)
7: AL88: AL88 (8-bit alpha, 8-bit luminance)

CACR [1]

Layerx Constant Alpha Configuration Register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CONSTA
rw
Toggle fields

CONSTA

Bits 0-7: Constant Alpha.

Allowed values: 0x0-0xff

DCCR [1]

Layerx Default Color Configuration Register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DCALPHA
rw
DCRED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCGREEN
rw
DCBLUE
rw
Toggle fields

DCBLUE

Bits 0-7: Default Color Blue.

Allowed values: 0x0-0xff

DCGREEN

Bits 8-15: Default Color Green.

Allowed values: 0x0-0xff

DCRED

Bits 16-23: Default Color Red.

Allowed values: 0x0-0xff

DCALPHA

Bits 24-31: Default Color Alpha.

Allowed values: 0x0-0xff

BFCR [1]

Layerx Blending Factors Configuration Register

Offset: 0xa0, size: 32, reset: 0x00000607, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BF1
rw
BF2
rw
Toggle fields

BF2

Bits 0-2: Blending Factor 2.

Allowed values:
5: Constant: BF2 = 1 - constant alpha
7: Pixel: BF2 = 1 - pixel alpha * constant alpha

BF1

Bits 8-10: Blending Factor 1.

Allowed values:
4: Constant: BF1 = constant alpha
6: Pixel: BF1 = pixel alpha * constant alpha

CFBAR [1]

Layerx Color Frame Buffer Address Register

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CFBADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFBADD
rw
Toggle fields

CFBADD

Bits 0-31: Color Frame Buffer Start Address.

Allowed values: 0x0-0xffffffff

CFBLR [1]

Layerx Color Frame Buffer Length Register

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CFBP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFBLL
rw
Toggle fields

CFBLL

Bits 0-12: Color Frame Buffer Line Length.

Allowed values: 0x0-0x1fff

CFBP

Bits 16-28: Color Frame Buffer Pitch in bytes.

Allowed values: 0x0-0x1fff

CFBLNR [1]

Layerx ColorFrame Buffer Line Number Register

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFBLNBR
rw
Toggle fields

CFBLNBR

Bits 0-10: Frame Buffer Line Number.

Allowed values: 0x0-0x7ff

CLUTWR [1]

Layerx CLUT Write Register

Offset: 0xc4, size: 32, reset: 0x00000000, access: write-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLUTADD
w
RED
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GREEN
w
BLUE
w
Toggle fields

BLUE

Bits 0-7: Blue value.

Allowed values: 0x0-0xff

GREEN

Bits 8-15: Green value.

Allowed values: 0x0-0xff

RED

Bits 16-23: Red value.

Allowed values: 0x0-0xff

CLUTADD

Bits 24-31: CLUT Address.

Allowed values: 0x0-0xff

CR [2]

Layerx Control Register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLUTEN
rw
COLKEN
rw
LEN
rw
Toggle fields

LEN

Bit 0: Layer Enable.

Allowed values:
0: Disabled: Layer disabled
1: Enabled: Layer enabled

COLKEN

Bit 1: Color Keying Enable.

Allowed values:
0: Disabled: Color keying disabled
1: Enabled: Color keying enabled

CLUTEN

Bit 4: Color Look-Up Table Enable.

Allowed values:
0: Disabled: Color look-up table disabled
1: Enabled: Color look-up table enabled

WHPCR [2]

Layerx Window Horizontal Position Configuration Register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WHSPPOS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WHSTPOS
rw
Toggle fields

WHSTPOS

Bits 0-11: Window Horizontal Start Position.

Allowed values: 0x0-0xfff

WHSPPOS

Bits 16-27: Window Horizontal Stop Position.

Allowed values: 0x0-0xfff

WVPCR [2]

Layerx Window Vertical Position Configuration Register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WVSPPOS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WVSTPOS
rw
Toggle fields

WVSTPOS

Bits 0-10: Window Vertical Start Position.

Allowed values: 0x0-0x7ff

WVSPPOS

Bits 16-26: Window Vertical Stop Position.

Allowed values: 0x0-0x7ff

CKCR [2]

Layerx Color Keying Configuration Register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CKRED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKGREEN
rw
CKBLUE
rw
Toggle fields

CKBLUE

Bits 0-7: Color Key Blue value.

Allowed values: 0x0-0xff

CKGREEN

Bits 8-15: Color Key Green value.

Allowed values: 0x0-0xff

CKRED

Bits 16-23: Color Key Red value.

Allowed values: 0x0-0xff

PFCR [2]

Layerx Pixel Format Configuration Register

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PF
rw
Toggle fields

PF

Bits 0-2: Pixel Format.

Allowed values:
0: ARGB8888: ARGB8888
1: RGB888: RGB888
2: RGB565: RGB565
3: ARGB1555: ARGB1555
4: ARGB4444: ARGB4444
5: L8: L8 (8-bit luminance)
6: AL44: AL44 (4-bit alpha, 4-bit luminance)
7: AL88: AL88 (8-bit alpha, 8-bit luminance)

CACR [2]

Layerx Constant Alpha Configuration Register

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CONSTA
rw
Toggle fields

CONSTA

Bits 0-7: Constant Alpha.

Allowed values: 0x0-0xff

DCCR [2]

Layerx Default Color Configuration Register

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DCALPHA
rw
DCRED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCGREEN
rw
DCBLUE
rw
Toggle fields

DCBLUE

Bits 0-7: Default Color Blue.

Allowed values: 0x0-0xff

DCGREEN

Bits 8-15: Default Color Green.

Allowed values: 0x0-0xff

DCRED

Bits 16-23: Default Color Red.

Allowed values: 0x0-0xff

DCALPHA

Bits 24-31: Default Color Alpha.

Allowed values: 0x0-0xff

BFCR [2]

Layerx Blending Factors Configuration Register

Offset: 0x120, size: 32, reset: 0x00000607, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BF1
rw
BF2
rw
Toggle fields

BF2

Bits 0-2: Blending Factor 2.

Allowed values:
5: Constant: BF2 = 1 - constant alpha
7: Pixel: BF2 = 1 - pixel alpha * constant alpha

BF1

Bits 8-10: Blending Factor 1.

Allowed values:
4: Constant: BF1 = constant alpha
6: Pixel: BF1 = pixel alpha * constant alpha

CFBAR [2]

Layerx Color Frame Buffer Address Register

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CFBADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFBADD
rw
Toggle fields

CFBADD

Bits 0-31: Color Frame Buffer Start Address.

Allowed values: 0x0-0xffffffff

CFBLR [2]

Layerx Color Frame Buffer Length Register

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CFBP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFBLL
rw
Toggle fields

CFBLL

Bits 0-12: Color Frame Buffer Line Length.

Allowed values: 0x0-0x1fff

CFBP

Bits 16-28: Color Frame Buffer Pitch in bytes.

Allowed values: 0x0-0x1fff

CFBLNR [2]

Layerx ColorFrame Buffer Line Number Register

Offset: 0x134, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFBLNBR
rw
Toggle fields

CFBLNBR

Bits 0-10: Frame Buffer Line Number.

Allowed values: 0x0-0x7ff

CLUTWR [2]

Layerx CLUT Write Register

Offset: 0x144, size: 32, reset: 0x00000000, access: write-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLUTADD
w
RED
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GREEN
w
BLUE
w
Toggle fields

BLUE

Bits 0-7: Blue value.

Allowed values: 0x0-0xff

GREEN

Bits 8-15: Green value.

Allowed values: 0x0-0xff

RED

Bits 16-23: Red value.

Allowed values: 0x0-0xff

CLUTADD

Bits 24-31: CLUT Address.

Allowed values: 0x0-0xff

MDIOS

0x40009400: Management data input/output slave

37/80 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 WRFR
0x8 CWRFR
0xc RDFR
0x10 CRDFR
0x14 SR
0x18 CLRFR
0x1c DINR0
0x20 DINR1
0x24 DINR2
0x28 DINR3
0x2c DINR4
0x30 DINR5
0x34 DINR6
0x38 DINR7
0x3c DINR8
0x40 DINR9
0x44 DINR10
0x48 DINR11
0x4c DINR12
0x50 DINR13
0x54 DINR14
0x58 DINR15
0x5c DINR16
0x60 DINR17
0x64 DINR18
0x68 DINR19
0x6c DINR20
0x70 DINR21
0x74 DINR22
0x78 DINR23
0x7c DINR24
0x80 DINR25
0x84 DINR26
0x88 DINR27
0x8c DINR28
0x90 DINR29
0x94 DINR30
0x98 DINR31
0x9c DOUTR0
0xa0 DOUTR1
0xa4 DOUTR2
0xa8 DOUTR3
0xac DOUTR4
0xb0 DOUTR5
0xb4 DOUTR6
0xb8 DOUTR7
0xbc DOUTR8
0xc0 DOUTR9
0xc4 DOUTR10
0xc8 DOUTR11
0xcc DOUTR12
0xd0 DOUTR13
0xd4 DOUTR14
0xd8 DOUTR15
0xdc DOUTR16
0xe0 DOUTR17
0xe4 DOUTR18
0xe8 DOUTR19
0xec DOUTR20
0xf0 DOUTR21
0xf4 DOUTR22
0xf8 DOUTR23
0xfc DOUTR24
0x100 DOUTR25
0x104 DOUTR26
0x108 DOUTR27
0x10c DOUTR28
0x110 DOUTR29
0x114 DOUTR30
0x118 DOUTR31
Toggle registers

CR

MDIOS configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PORT_ADDRESS
rw
DPC
rw
EIE
rw
RDIE
rw
WRIE
rw
EN
rw
Toggle fields

EN

Bit 0: Peripheral enable.

WRIE

Bit 1: Register write interrupt enable.

RDIE

Bit 2: Register Read Interrupt Enable.

EIE

Bit 3: Error interrupt enable.

DPC

Bit 7: Disable Preamble Check.

PORT_ADDRESS

Bits 8-12: Slaves's address.

WRFR

MDIOS write flag register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRF
r
Toggle fields

WRF

Bits 0-31: Write flags for MDIO registers 0 to 31.

CWRFR

MDIOS clear write flag register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CWRF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CWRF
rw
Toggle fields

CWRF

Bits 0-31: Clear the write flag.

RDFR

MDIOS read flag register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDF
r
Toggle fields

RDF

Bits 0-31: Read flags for MDIO registers 0 to 31.

CRDFR

MDIOS clear read flag register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRDF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRDF
rw
Toggle fields

CRDF

Bits 0-31: Clear the read flag.

SR

MDIOS status register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TERF
r
SERF
r
PERF
r
Toggle fields

PERF

Bit 0: Preamble error flag.

SERF

Bit 1: Start error flag.

TERF

Bit 2: Turnaround error flag.

CLRFR

MDIOS clear flag register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTERF
rw
CSERF
rw
CPERF
rw
Toggle fields

CPERF

Bit 0: Clear the preamble error flag.

CSERF

Bit 1: Clear the start error flag.

CTERF

Bit 2: Clear the turnaround error flag.

DINR0

MDIOS input data register 0

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN0
r
Toggle fields

DIN0

Bits 0-15: Input data received from MDIO Master during write frames.

DINR1

MDIOS input data register 1

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN1
r
Toggle fields

DIN1

Bits 0-15: Input data received from MDIO Master during write frames.

DINR2

MDIOS input data register 2

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN2
r
Toggle fields

DIN2

Bits 0-15: Input data received from MDIO Master during write frames.

DINR3

MDIOS input data register 3

Offset: 0x28, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN3
r
Toggle fields

DIN3

Bits 0-15: Input data received from MDIO Master during write frames.

DINR4

MDIOS input data register 4

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN4
r
Toggle fields

DIN4

Bits 0-15: Input data received from MDIO Master during write frames.

DINR5

MDIOS input data register 5

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN5
r
Toggle fields

DIN5

Bits 0-15: Input data received from MDIO Master during write frames.

DINR6

MDIOS input data register 6

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN6
r
Toggle fields

DIN6

Bits 0-15: Input data received from MDIO Master during write frames.

DINR7

MDIOS input data register 7

Offset: 0x38, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN7
r
Toggle fields

DIN7

Bits 0-15: Input data received from MDIO Master during write frames.

DINR8

MDIOS input data register 8

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN8
r
Toggle fields

DIN8

Bits 0-15: Input data received from MDIO Master during write frames.

DINR9

MDIOS input data register 9

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN9
r
Toggle fields

DIN9

Bits 0-15: Input data received from MDIO Master during write frames.

DINR10

MDIOS input data register 10

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN10
r
Toggle fields

DIN10

Bits 0-15: Input data received from MDIO Master during write frames.

DINR11

MDIOS input data register 11

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN11
r
Toggle fields

DIN11

Bits 0-15: Input data received from MDIO Master during write frames.

DINR12

MDIOS input data register 12

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN12
r
Toggle fields

DIN12

Bits 0-15: Input data received from MDIO Master during write frames.

DINR13

MDIOS input data register 13

Offset: 0x50, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN13
r
Toggle fields

DIN13

Bits 0-15: Input data received from MDIO Master during write frames.

DINR14

MDIOS input data register 14

Offset: 0x54, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN14
r
Toggle fields

DIN14

Bits 0-15: Input data received from MDIO Master during write frames.

DINR15

MDIOS input data register 15

Offset: 0x58, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN15
r
Toggle fields

DIN15

Bits 0-15: Input data received from MDIO Master during write frames.

DINR16

MDIOS input data register 16

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN16
r
Toggle fields

DIN16

Bits 0-15: Input data received from MDIO Master during write frames.

DINR17

MDIOS input data register 17

Offset: 0x60, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN17
r
Toggle fields

DIN17

Bits 0-15: Input data received from MDIO Master during write frames.

DINR18

MDIOS input data register 18

Offset: 0x64, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN18
r
Toggle fields

DIN18

Bits 0-15: Input data received from MDIO Master during write frames.

DINR19

MDIOS input data register 19

Offset: 0x68, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN19
r
Toggle fields

DIN19

Bits 0-15: Input data received from MDIO Master during write frames.

DINR20

MDIOS input data register 20

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN20
r
Toggle fields

DIN20

Bits 0-15: Input data received from MDIO Master during write frames.

DINR21

MDIOS input data register 21

Offset: 0x70, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN21
r
Toggle fields

DIN21

Bits 0-15: Input data received from MDIO Master during write frames.

DINR22

MDIOS input data register 22

Offset: 0x74, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN22
r
Toggle fields

DIN22

Bits 0-15: Input data received from MDIO Master during write frames.

DINR23

MDIOS input data register 23

Offset: 0x78, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN23
r
Toggle fields

DIN23

Bits 0-15: Input data received from MDIO Master during write frames.

DINR24

MDIOS input data register 24

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN24
r
Toggle fields

DIN24

Bits 0-15: Input data received from MDIO Master during write frames.

DINR25

MDIOS input data register 25

Offset: 0x80, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN25
r
Toggle fields

DIN25

Bits 0-15: Input data received from MDIO Master during write frames.

DINR26

MDIOS input data register 26

Offset: 0x84, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN26
r
Toggle fields

DIN26

Bits 0-15: Input data received from MDIO Master during write frames.

DINR27

MDIOS input data register 27

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN27
r
Toggle fields

DIN27

Bits 0-15: Input data received from MDIO Master during write frames.

DINR28

MDIOS input data register 28

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN28
r
Toggle fields

DIN28

Bits 0-15: Input data received from MDIO Master during write frames.

DINR29

MDIOS input data register 29

Offset: 0x90, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN29
r
Toggle fields

DIN29

Bits 0-15: Input data received from MDIO Master during write frames.

DINR30

MDIOS input data register 30

Offset: 0x94, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN30
r
Toggle fields

DIN30

Bits 0-15: Input data received from MDIO Master during write frames.

DINR31

MDIOS input data register 31

Offset: 0x98, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN31
r
Toggle fields

DIN31

Bits 0-15: Input data received from MDIO Master during write frames.

DOUTR0

MDIOS output data register 0

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT0
rw
Toggle fields

DOUT0

Bits 0-15: Output data sent to MDIO Master during read frames.

DOUTR1

MDIOS output data register 1

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT1
rw
Toggle fields

DOUT1

Bits 0-15: Output data sent to MDIO Master during read frames.

DOUTR2

MDIOS output data register 2

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT2
rw
Toggle fields

DOUT2

Bits 0-15: Output data sent to MDIO Master during read frames.

DOUTR3

MDIOS output data register 3

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT3
rw
Toggle fields

DOUT3

Bits 0-15: Output data sent to MDIO Master during read frames.

DOUTR4

MDIOS output data register 4

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT4
rw
Toggle fields

DOUT4

Bits 0-15: Output data sent to MDIO Master during read frames.

DOUTR5

MDIOS output data register 5

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT5
rw
Toggle fields

DOUT5

Bits 0-15: Output data sent to MDIO Master during read frames.

DOUTR6

MDIOS output data register 6

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT6
rw
Toggle fields

DOUT6

Bits 0-15: Output data sent to MDIO Master during read frames.

DOUTR7

MDIOS output data register 7

Offset: 0xb8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT7
rw
Toggle fields

DOUT7

Bits 0-15: Output data sent to MDIO Master during read frames.

DOUTR8

MDIOS output data register 8

Offset: 0xbc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT8
rw
Toggle fields

DOUT8

Bits 0-15: Output data sent to MDIO Master during read frames.

DOUTR9

MDIOS output data register 9

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT9
rw
Toggle fields

DOUT9

Bits 0-15: Output data sent to MDIO Master during read frames.

DOUTR10

MDIOS output data register 10

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT10
rw
Toggle fields

DOUT10

Bits 0-15: Output data sent to MDIO Master during read frames.

DOUTR11

MDIOS output data register 11

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT11
rw
Toggle fields

DOUT11

Bits 0-15: Output data sent to MDIO Master during read frames.

DOUTR12

MDIOS output data register 12

Offset: 0xcc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT12
rw
Toggle fields

DOUT12

Bits 0-15: Output data sent to MDIO Master during read frames.

DOUTR13

MDIOS output data register 13

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT13
rw
Toggle fields

DOUT13

Bits 0-15: Output data sent to MDIO Master during read frames.

DOUTR14

MDIOS output data register 14

Offset: 0xd4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT14
rw
Toggle fields

DOUT14

Bits 0-15: Output data sent to MDIO Master during read frames.

DOUTR15

MDIOS output data register 15

Offset: 0xd8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT15
rw
Toggle fields

DOUT15

Bits 0-15: Output data sent to MDIO Master during read frames.

DOUTR16

MDIOS output data register 16

Offset: 0xdc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT16
rw
Toggle fields

DOUT16

Bits 0-15: Output data sent to MDIO Master during read frames.

DOUTR17

MDIOS output data register 17

Offset: 0xe0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT17
rw
Toggle fields

DOUT17

Bits 0-15: Output data sent to MDIO Master during read frames.

DOUTR18

MDIOS output data register 18

Offset: 0xe4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT18
rw
Toggle fields

DOUT18

Bits 0-15: Output data sent to MDIO Master during read frames.

DOUTR19

MDIOS output data register 19

Offset: 0xe8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT19
rw
Toggle fields

DOUT19

Bits 0-15: Output data sent to MDIO Master during read frames.

DOUTR20

MDIOS output data register 20

Offset: 0xec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT20
rw
Toggle fields

DOUT20

Bits 0-15: Output data sent to MDIO Master during read frames.

DOUTR21

MDIOS output data register 21

Offset: 0xf0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT21
rw
Toggle fields

DOUT21

Bits 0-15: Output data sent to MDIO Master during read frames.

DOUTR22

MDIOS output data register 22

Offset: 0xf4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT22
rw
Toggle fields

DOUT22

Bits 0-15: Output data sent to MDIO Master during read frames.

DOUTR23

MDIOS output data register 23

Offset: 0xf8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT23
rw
Toggle fields

DOUT23

Bits 0-15: Output data sent to MDIO Master during read frames.

DOUTR24

MDIOS output data register 24

Offset: 0xfc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT24
rw
Toggle fields

DOUT24

Bits 0-15: Output data sent to MDIO Master during read frames.

DOUTR25

MDIOS output data register 25

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT25
rw
Toggle fields

DOUT25

Bits 0-15: Output data sent to MDIO Master during read frames.

DOUTR26

MDIOS output data register 26

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT26
rw
Toggle fields

DOUT26

Bits 0-15: Output data sent to MDIO Master during read frames.

DOUTR27

MDIOS output data register 27

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT27
rw
Toggle fields

DOUT27

Bits 0-15: Output data sent to MDIO Master during read frames.

DOUTR28

MDIOS output data register 28

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT28
rw
Toggle fields

DOUT28

Bits 0-15: Output data sent to MDIO Master during read frames.

DOUTR29

MDIOS output data register 29

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT29
rw
Toggle fields

DOUT29

Bits 0-15: Output data sent to MDIO Master during read frames.

DOUTR30

MDIOS output data register 30

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT30
rw
Toggle fields

DOUT30

Bits 0-15: Output data sent to MDIO Master during read frames.

DOUTR31

MDIOS output data register 31

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT31
rw
Toggle fields

DOUT31

Bits 0-15: Output data sent to MDIO Master during read frames.

MDMA

0x52000000: MDMA

208/912 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 GISR0
0x40 ISR [0]
0x44 IFCR [0]
0x48 ESR [0]
0x4c CR [0]
0x50 TCR [0]
0x54 BNDTR [0]
0x58 SAR [0]
0x5c DAR [0]
0x60 BRUR [0]
0x64 LAR [0]
0x68 TBR [0]
0x70 MAR [0]
0x74 MDR [0]
0x80 ISR [1]
0x84 IFCR [1]
0x88 ESR [1]
0x8c CR [1]
0x90 TCR [1]
0x94 BNDTR [1]
0x98 SAR [1]
0x9c DAR [1]
0xa0 BRUR [1]
0xa4 LAR [1]
0xa8 TBR [1]
0xb0 MAR [1]
0xb4 MDR [1]
0xc0 ISR [2]
0xc4 IFCR [2]
0xc8 ESR [2]
0xcc CR [2]
0xd0 TCR [2]
0xd4 BNDTR [2]
0xd8 SAR [2]
0xdc DAR [2]
0xe0 BRUR [2]
0xe4 LAR [2]
0xe8 TBR [2]
0xf0 MAR [2]
0xf4 MDR [2]
0x100 ISR [3]
0x104 IFCR [3]
0x108 ESR [3]
0x10c CR [3]
0x110 TCR [3]
0x114 BNDTR [3]
0x118 SAR [3]
0x11c DAR [3]
0x120 BRUR [3]
0x124 LAR [3]
0x128 TBR [3]
0x130 MAR [3]
0x134 MDR [3]
0x140 ISR [4]
0x144 IFCR [4]
0x148 ESR [4]
0x14c CR [4]
0x150 TCR [4]
0x154 BNDTR [4]
0x158 SAR [4]
0x15c DAR [4]
0x160 BRUR [4]
0x164 LAR [4]
0x168 TBR [4]
0x170 MAR [4]
0x174 MDR [4]
0x180 ISR [5]
0x184 IFCR [5]
0x188 ESR [5]
0x18c CR [5]
0x190 TCR [5]
0x194 BNDTR [5]
0x198 SAR [5]
0x19c DAR [5]
0x1a0 BRUR [5]
0x1a4 LAR [5]
0x1a8 TBR [5]
0x1b0 MAR [5]
0x1b4 MDR [5]
0x1c0 ISR [6]
0x1c4 IFCR [6]
0x1c8 ESR [6]
0x1cc CR [6]
0x1d0 TCR [6]
0x1d4 BNDTR [6]
0x1d8 SAR [6]
0x1dc DAR [6]
0x1e0 BRUR [6]
0x1e4 LAR [6]
0x1e8 TBR [6]
0x1f0 MAR [6]
0x1f4 MDR [6]
0x200 ISR [7]
0x204 IFCR [7]
0x208 ESR [7]
0x20c CR [7]
0x210 TCR [7]
0x214 BNDTR [7]
0x218 SAR [7]
0x21c DAR [7]
0x220 BRUR [7]
0x224 LAR [7]
0x228 TBR [7]
0x230 MAR [7]
0x234 MDR [7]
0x240 ISR [8]
0x244 IFCR [8]
0x248 ESR [8]
0x24c CR [8]
0x250 TCR [8]
0x254 BNDTR [8]
0x258 SAR [8]
0x25c DAR [8]
0x260 BRUR [8]
0x264 LAR [8]
0x268 TBR [8]
0x270 MAR [8]
0x274 MDR [8]
0x280 ISR [9]
0x284 IFCR [9]
0x288 ESR [9]
0x28c CR [9]
0x290 TCR [9]
0x294 BNDTR [9]
0x298 SAR [9]
0x29c DAR [9]
0x2a0 BRUR [9]
0x2a4 LAR [9]
0x2a8 TBR [9]
0x2b0 MAR [9]
0x2b4 MDR [9]
0x2c0 ISR [10]
0x2c4 IFCR [10]
0x2c8 ESR [10]
0x2cc CR [10]
0x2d0 TCR [10]
0x2d4 BNDTR [10]
0x2d8 SAR [10]
0x2dc DAR [10]
0x2e0 BRUR [10]
0x2e4 LAR [10]
0x2e8 TBR [10]
0x2f0 MAR [10]
0x2f4 MDR [10]
0x300 ISR [11]
0x304 IFCR [11]
0x308 ESR [11]
0x30c CR [11]
0x310 TCR [11]
0x314 BNDTR [11]
0x318 SAR [11]
0x31c DAR [11]
0x320 BRUR [11]
0x324 LAR [11]
0x328 TBR [11]
0x330 MAR [11]
0x334 MDR [11]
0x340 ISR [12]
0x344 IFCR [12]
0x348 ESR [12]
0x34c CR [12]
0x350 TCR [12]
0x354 BNDTR [12]
0x358 SAR [12]
0x35c DAR [12]
0x360 BRUR [12]
0x364 LAR [12]
0x368 TBR [12]
0x370 MAR [12]
0x374 MDR [12]
0x380 ISR [13]
0x384 IFCR [13]
0x388 ESR [13]
0x38c CR [13]
0x390 TCR [13]
0x394 BNDTR [13]
0x398 SAR [13]
0x39c DAR [13]
0x3a0 BRUR [13]
0x3a4 LAR [13]
0x3a8 TBR [13]
0x3b0 MAR [13]
0x3b4 MDR [13]
0x3c0 ISR [14]
0x3c4 IFCR [14]
0x3c8 ESR [14]
0x3cc CR [14]
0x3d0 TCR [14]
0x3d4 BNDTR [14]
0x3d8 SAR [14]
0x3dc DAR [14]
0x3e0 BRUR [14]
0x3e4 LAR [14]
0x3e8 TBR [14]
0x3f0 MAR [14]
0x3f4 MDR [14]
0x400 ISR [15]
0x404 IFCR [15]
0x408 ESR [15]
0x40c CR [15]
0x410 TCR [15]
0x414 BNDTR [15]
0x418 SAR [15]
0x41c DAR [15]
0x420 BRUR [15]
0x424 LAR [15]
0x428 TBR [15]
0x430 MAR [15]
0x434 MDR [15]
Toggle registers

GISR0

MDMA Global Interrupt/Status Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

Toggle fields

GIF[0]

Bit 0: Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx).

GIF[1]

Bit 1: Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx).

GIF[2]

Bit 2: Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx).

GIF[3]

Bit 3: Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx).

GIF[4]

Bit 4: Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx).

GIF[5]

Bit 5: Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx).

GIF[6]

Bit 6: Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx).

GIF[7]

Bit 7: Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx).

GIF[8]

Bit 8: Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx).

GIF[9]

Bit 9: Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx).

GIF[10]

Bit 10: Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx).

GIF[11]

Bit 11: Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx).

GIF[12]

Bit 12: Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx).

GIF[13]

Bit 13: Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx).

GIF[14]

Bit 14: Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx).

GIF[15]

Bit 15: Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx).

ISR [0]

MDMA channel x interrupt/status register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r
BTIF
r
BRTIF
r
CTCIF
r
TEIF
r
Toggle fields

TEIF

Bit 0: Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

CTCIF

Bit 1: Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0..

BRTIF

Bit 2: Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

BTIF

Bit 3: Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

TCIF

Bit 4: channel x buffer transfer complete.

CRQA

Bit 16: channel x request active flag.

IFCR [0]

MDMA channel x interrupt flag clear register

Offset: 0x44, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w
CBTIF
w
CBRTIF
w
CCTCIF
w
CTEIF
w
Toggle fields

CTEIF

Bit 0: Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register.

CCTCIF

Bit 1: Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register.

CBRTIF

Bit 2: Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register.

CBTIF

Bit 3: Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register.

CLTCIF

Bit 4: CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register.

ESR [0]

MDMA Channel x error status register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r
ASE
r
TEMD
r
TELD
r
TED
r
TEA
r
Toggle fields

TEA

Bits 0-6: Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error..

TED

Bit 7: Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error..

TELD

Bit 8: Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

TEMD

Bit 9: Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

ASE

Bit 10: Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

BSE

Bit 11: Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

CR [0]

This register is used to control the concerned channel.

Offset: 0x4c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw
HEX
rw
BEX
rw
PL
rw
TCIE
rw
BTIE
rw
BRTIE
rw
CTCIE
rw
TEIE
rw
EN
rw
Toggle fields

EN

Bit 0: channel enable.

TEIE

Bit 1: Transfer error interrupt enable This bit is set and cleared by software..

CTCIE

Bit 2: Channel Transfer Complete interrupt enable This bit is set and cleared by software..

BRTIE

Bit 3: Block Repeat transfer interrupt enable This bit is set and cleared by software..

BTIE

Bit 4: Block Transfer interrupt enable This bit is set and cleared by software..

TCIE

Bit 5: buffer Transfer Complete interrupt enable This bit is set and cleared by software..

PL

Bits 6-7: Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0..

BEX

Bit 12: byte Endianness exchange.

HEX

Bit 13: Half word Endianes exchange.

WEX

Bit 14: Word Endianness exchange.

SWRQ

Bit 16: SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)..

TCR [0]

This register is used to configure the concerned channel.

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw
SWRM
rw
TRGM
rw
PAM
rw
PKE
rw
TLEN
rw
DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw
SBURST
rw
DINCOS
rw
SINCOS
rw
DSIZE
rw
SSIZE
rw
DINC
rw
SINC
rw
Toggle fields

SINC

Bits 0-1: Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)..

DINC

Bits 2-3: Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden..

SSIZE

Bits 4-5: Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS &lt; SSIZE and SINC &#8800; 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)..

DSIZE

Bits 6-7: Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS &lt; DSIZE and DINC &#8800; 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)..

SINCOS

Bits 8-9: source increment offset size.

DINCOS

Bits 10-11: Destination increment offset.

SBURST

Bits 12-14: source burst transfer configuration.

DBURST

Bits 15-17: Destination burst transfer configuration.

TLEN

Bits 18-24: buffer transfer lengh.

PKE

Bit 25: PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0.

PAM

Bits 26-27: Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0.

TRGM

Bits 28-29: Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0..

SWRM

Bit 30: SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0..

BWM

Bit 31: Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable..

BNDTR [0]

MDMA Channel x block number of data register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw
BRDUM
rw
BRSUM
rw
BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: block number of data to transfer.

BRSUM

Bit 18: Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0..

BRDUM

Bit 19: Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0..

BRC

Bits 20-31: Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0..

SAR [0]

MDMA channel x source address register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: source adr base.

DAR [0]

MDMA channel x destination address register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: Destination adr base.

BRUR [0]

MDMA channel x Block Repeat address Update register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: source adresse update value.

DUV

Bits 16-31: destination address update.

LAR [0]

MDMA channel x Link Address register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: Link address register.

TBR [0]

MDMA channel x Trigger and Bus selection Register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw
SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: Trigger selection.

SBUS

Bit 16: Source BUS select This bit is protected and can be written only if EN is 0..

DBUS

Bit 17: Destination BUS slect This bit is protected and can be written only if EN is 0..

MAR [0]

MDMA channel x Mask address register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: Mask address.

MDR [0]

MDMA channel x Mask Data register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: Mask data.

ISR [1]

MDMA channel x interrupt/status register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r
BTIF
r
BRTIF
r
CTCIF
r
TEIF
r
Toggle fields

TEIF

Bit 0: Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

CTCIF

Bit 1: Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0..

BRTIF

Bit 2: Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

BTIF

Bit 3: Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

TCIF

Bit 4: channel x buffer transfer complete.

CRQA

Bit 16: channel x request active flag.

IFCR [1]

MDMA channel x interrupt flag clear register

Offset: 0x84, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w
CBTIF
w
CBRTIF
w
CCTCIF
w
CTEIF
w
Toggle fields

CTEIF

Bit 0: Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register.

CCTCIF

Bit 1: Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register.

CBRTIF

Bit 2: Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register.

CBTIF

Bit 3: Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register.

CLTCIF

Bit 4: CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register.

ESR [1]

MDMA Channel x error status register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r
ASE
r
TEMD
r
TELD
r
TED
r
TEA
r
Toggle fields

TEA

Bits 0-6: Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error..

TED

Bit 7: Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error..

TELD

Bit 8: Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

TEMD

Bit 9: Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

ASE

Bit 10: Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

BSE

Bit 11: Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

CR [1]

This register is used to control the concerned channel.

Offset: 0x8c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw
HEX
rw
BEX
rw
PL
rw
TCIE
rw
BTIE
rw
BRTIE
rw
CTCIE
rw
TEIE
rw
EN
rw
Toggle fields

EN

Bit 0: channel enable.

TEIE

Bit 1: Transfer error interrupt enable This bit is set and cleared by software..

CTCIE

Bit 2: Channel Transfer Complete interrupt enable This bit is set and cleared by software..

BRTIE

Bit 3: Block Repeat transfer interrupt enable This bit is set and cleared by software..

BTIE

Bit 4: Block Transfer interrupt enable This bit is set and cleared by software..

TCIE

Bit 5: buffer Transfer Complete interrupt enable This bit is set and cleared by software..

PL

Bits 6-7: Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0..

BEX

Bit 12: byte Endianness exchange.

HEX

Bit 13: Half word Endianes exchange.

WEX

Bit 14: Word Endianness exchange.

SWRQ

Bit 16: SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)..

TCR [1]

This register is used to configure the concerned channel.

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw
SWRM
rw
TRGM
rw
PAM
rw
PKE
rw
TLEN
rw
DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw
SBURST
rw
DINCOS
rw
SINCOS
rw
DSIZE
rw
SSIZE
rw
DINC
rw
SINC
rw
Toggle fields

SINC

Bits 0-1: Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)..

DINC

Bits 2-3: Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden..

SSIZE

Bits 4-5: Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS &lt; SSIZE and SINC &#8800; 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)..

DSIZE

Bits 6-7: Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS &lt; DSIZE and DINC &#8800; 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)..

SINCOS

Bits 8-9: source increment offset size.

DINCOS

Bits 10-11: Destination increment offset.

SBURST

Bits 12-14: source burst transfer configuration.

DBURST

Bits 15-17: Destination burst transfer configuration.

TLEN

Bits 18-24: buffer transfer lengh.

PKE

Bit 25: PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0.

PAM

Bits 26-27: Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0.

TRGM

Bits 28-29: Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0..

SWRM

Bit 30: SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0..

BWM

Bit 31: Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable..

BNDTR [1]

MDMA Channel x block number of data register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw
BRDUM
rw
BRSUM
rw
BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: block number of data to transfer.

BRSUM

Bit 18: Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0..

BRDUM

Bit 19: Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0..

BRC

Bits 20-31: Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0..

SAR [1]

MDMA channel x source address register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: source adr base.

DAR [1]

MDMA channel x destination address register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: Destination adr base.

BRUR [1]

MDMA channel x Block Repeat address Update register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: source adresse update value.

DUV

Bits 16-31: destination address update.

LAR [1]

MDMA channel x Link Address register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: Link address register.

TBR [1]

MDMA channel x Trigger and Bus selection Register

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw
SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: Trigger selection.

SBUS

Bit 16: Source BUS select This bit is protected and can be written only if EN is 0..

DBUS

Bit 17: Destination BUS slect This bit is protected and can be written only if EN is 0..

MAR [1]

MDMA channel x Mask address register

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: Mask address.

MDR [1]

MDMA channel x Mask Data register

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: Mask data.

ISR [2]

MDMA channel x interrupt/status register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r
BTIF
r
BRTIF
r
CTCIF
r
TEIF
r
Toggle fields

TEIF

Bit 0: Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

CTCIF

Bit 1: Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0..

BRTIF

Bit 2: Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

BTIF

Bit 3: Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

TCIF

Bit 4: channel x buffer transfer complete.

CRQA

Bit 16: channel x request active flag.

IFCR [2]

MDMA channel x interrupt flag clear register

Offset: 0xc4, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w
CBTIF
w
CBRTIF
w
CCTCIF
w
CTEIF
w
Toggle fields

CTEIF

Bit 0: Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register.

CCTCIF

Bit 1: Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register.

CBRTIF

Bit 2: Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register.

CBTIF

Bit 3: Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register.

CLTCIF

Bit 4: CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register.

ESR [2]

MDMA Channel x error status register

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r
ASE
r
TEMD
r
TELD
r
TED
r
TEA
r
Toggle fields

TEA

Bits 0-6: Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error..

TED

Bit 7: Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error..

TELD

Bit 8: Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

TEMD

Bit 9: Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

ASE

Bit 10: Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

BSE

Bit 11: Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

CR [2]

This register is used to control the concerned channel.

Offset: 0xcc, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw
HEX
rw
BEX
rw
PL
rw
TCIE
rw
BTIE
rw
BRTIE
rw
CTCIE
rw
TEIE
rw
EN
rw
Toggle fields

EN

Bit 0: channel enable.

TEIE

Bit 1: Transfer error interrupt enable This bit is set and cleared by software..

CTCIE

Bit 2: Channel Transfer Complete interrupt enable This bit is set and cleared by software..

BRTIE

Bit 3: Block Repeat transfer interrupt enable This bit is set and cleared by software..

BTIE

Bit 4: Block Transfer interrupt enable This bit is set and cleared by software..

TCIE

Bit 5: buffer Transfer Complete interrupt enable This bit is set and cleared by software..

PL

Bits 6-7: Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0..

BEX

Bit 12: byte Endianness exchange.

HEX

Bit 13: Half word Endianes exchange.

WEX

Bit 14: Word Endianness exchange.

SWRQ

Bit 16: SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)..

TCR [2]

This register is used to configure the concerned channel.

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw
SWRM
rw
TRGM
rw
PAM
rw
PKE
rw
TLEN
rw
DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw
SBURST
rw
DINCOS
rw
SINCOS
rw
DSIZE
rw
SSIZE
rw
DINC
rw
SINC
rw
Toggle fields

SINC

Bits 0-1: Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)..

DINC

Bits 2-3: Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden..

SSIZE

Bits 4-5: Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS &lt; SSIZE and SINC &#8800; 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)..

DSIZE

Bits 6-7: Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS &lt; DSIZE and DINC &#8800; 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)..

SINCOS

Bits 8-9: source increment offset size.

DINCOS

Bits 10-11: Destination increment offset.

SBURST

Bits 12-14: source burst transfer configuration.

DBURST

Bits 15-17: Destination burst transfer configuration.

TLEN

Bits 18-24: buffer transfer lengh.

PKE

Bit 25: PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0.

PAM

Bits 26-27: Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0.

TRGM

Bits 28-29: Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0..

SWRM

Bit 30: SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0..

BWM

Bit 31: Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable..

BNDTR [2]

MDMA Channel x block number of data register

Offset: 0xd4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw
BRDUM
rw
BRSUM
rw
BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: block number of data to transfer.

BRSUM

Bit 18: Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0..

BRDUM

Bit 19: Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0..

BRC

Bits 20-31: Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0..

SAR [2]

MDMA channel x source address register

Offset: 0xd8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: source adr base.

DAR [2]

MDMA channel x destination address register

Offset: 0xdc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: Destination adr base.

BRUR [2]

MDMA channel x Block Repeat address Update register

Offset: 0xe0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: source adresse update value.

DUV

Bits 16-31: destination address update.

LAR [2]

MDMA channel x Link Address register

Offset: 0xe4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: Link address register.

TBR [2]

MDMA channel x Trigger and Bus selection Register

Offset: 0xe8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw
SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: Trigger selection.

SBUS

Bit 16: Source BUS select This bit is protected and can be written only if EN is 0..

DBUS

Bit 17: Destination BUS slect This bit is protected and can be written only if EN is 0..

MAR [2]

MDMA channel x Mask address register

Offset: 0xf0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: Mask address.

MDR [2]

MDMA channel x Mask Data register

Offset: 0xf4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: Mask data.

ISR [3]

MDMA channel x interrupt/status register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r
BTIF
r
BRTIF
r
CTCIF
r
TEIF
r
Toggle fields

TEIF

Bit 0: Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

CTCIF

Bit 1: Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0..

BRTIF

Bit 2: Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

BTIF

Bit 3: Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

TCIF

Bit 4: channel x buffer transfer complete.

CRQA

Bit 16: channel x request active flag.

IFCR [3]

MDMA channel x interrupt flag clear register

Offset: 0x104, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w
CBTIF
w
CBRTIF
w
CCTCIF
w
CTEIF
w
Toggle fields

CTEIF

Bit 0: Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register.

CCTCIF

Bit 1: Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register.

CBRTIF

Bit 2: Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register.

CBTIF

Bit 3: Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register.

CLTCIF

Bit 4: CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register.

ESR [3]

MDMA Channel x error status register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r
ASE
r
TEMD
r
TELD
r
TED
r
TEA
r
Toggle fields

TEA

Bits 0-6: Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error..

TED

Bit 7: Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error..

TELD

Bit 8: Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

TEMD

Bit 9: Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

ASE

Bit 10: Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

BSE

Bit 11: Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

CR [3]

This register is used to control the concerned channel.

Offset: 0x10c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw
HEX
rw
BEX
rw
PL
rw
TCIE
rw
BTIE
rw
BRTIE
rw
CTCIE
rw
TEIE
rw
EN
rw
Toggle fields

EN

Bit 0: channel enable.

TEIE

Bit 1: Transfer error interrupt enable This bit is set and cleared by software..

CTCIE

Bit 2: Channel Transfer Complete interrupt enable This bit is set and cleared by software..

BRTIE

Bit 3: Block Repeat transfer interrupt enable This bit is set and cleared by software..

BTIE

Bit 4: Block Transfer interrupt enable This bit is set and cleared by software..

TCIE

Bit 5: buffer Transfer Complete interrupt enable This bit is set and cleared by software..

PL

Bits 6-7: Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0..

BEX

Bit 12: byte Endianness exchange.

HEX

Bit 13: Half word Endianes exchange.

WEX

Bit 14: Word Endianness exchange.

SWRQ

Bit 16: SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)..

TCR [3]

This register is used to configure the concerned channel.

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw
SWRM
rw
TRGM
rw
PAM
rw
PKE
rw
TLEN
rw
DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw
SBURST
rw
DINCOS
rw
SINCOS
rw
DSIZE
rw
SSIZE
rw
DINC
rw
SINC
rw
Toggle fields

SINC

Bits 0-1: Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)..

DINC

Bits 2-3: Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden..

SSIZE

Bits 4-5: Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS &lt; SSIZE and SINC &#8800; 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)..

DSIZE

Bits 6-7: Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS &lt; DSIZE and DINC &#8800; 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)..

SINCOS

Bits 8-9: source increment offset size.

DINCOS

Bits 10-11: Destination increment offset.

SBURST

Bits 12-14: source burst transfer configuration.

DBURST

Bits 15-17: Destination burst transfer configuration.

TLEN

Bits 18-24: buffer transfer lengh.

PKE

Bit 25: PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0.

PAM

Bits 26-27: Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0.

TRGM

Bits 28-29: Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0..

SWRM

Bit 30: SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0..

BWM

Bit 31: Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable..

BNDTR [3]

MDMA Channel x block number of data register

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw
BRDUM
rw
BRSUM
rw
BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: block number of data to transfer.

BRSUM

Bit 18: Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0..

BRDUM

Bit 19: Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0..

BRC

Bits 20-31: Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0..

SAR [3]

MDMA channel x source address register

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: source adr base.

DAR [3]

MDMA channel x destination address register

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: Destination adr base.

BRUR [3]

MDMA channel x Block Repeat address Update register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: source adresse update value.

DUV

Bits 16-31: destination address update.

LAR [3]

MDMA channel x Link Address register

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: Link address register.

TBR [3]

MDMA channel x Trigger and Bus selection Register

Offset: 0x128, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw
SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: Trigger selection.

SBUS

Bit 16: Source BUS select This bit is protected and can be written only if EN is 0..

DBUS

Bit 17: Destination BUS slect This bit is protected and can be written only if EN is 0..

MAR [3]

MDMA channel x Mask address register

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: Mask address.

MDR [3]

MDMA channel x Mask Data register

Offset: 0x134, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: Mask data.

ISR [4]

MDMA channel x interrupt/status register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r
BTIF
r
BRTIF
r
CTCIF
r
TEIF
r
Toggle fields

TEIF

Bit 0: Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

CTCIF

Bit 1: Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0..

BRTIF

Bit 2: Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

BTIF

Bit 3: Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

TCIF

Bit 4: channel x buffer transfer complete.

CRQA

Bit 16: channel x request active flag.

IFCR [4]

MDMA channel x interrupt flag clear register

Offset: 0x144, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w
CBTIF
w
CBRTIF
w
CCTCIF
w
CTEIF
w
Toggle fields

CTEIF

Bit 0: Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register.

CCTCIF

Bit 1: Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register.

CBRTIF

Bit 2: Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register.

CBTIF

Bit 3: Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register.

CLTCIF

Bit 4: CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register.

ESR [4]

MDMA Channel x error status register

Offset: 0x148, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r
ASE
r
TEMD
r
TELD
r
TED
r
TEA
r
Toggle fields

TEA

Bits 0-6: Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error..

TED

Bit 7: Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error..

TELD

Bit 8: Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

TEMD

Bit 9: Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

ASE

Bit 10: Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

BSE

Bit 11: Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

CR [4]

This register is used to control the concerned channel.

Offset: 0x14c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw
HEX
rw
BEX
rw
PL
rw
TCIE
rw
BTIE
rw
BRTIE
rw
CTCIE
rw
TEIE
rw
EN
rw
Toggle fields

EN

Bit 0: channel enable.

TEIE

Bit 1: Transfer error interrupt enable This bit is set and cleared by software..

CTCIE

Bit 2: Channel Transfer Complete interrupt enable This bit is set and cleared by software..

BRTIE

Bit 3: Block Repeat transfer interrupt enable This bit is set and cleared by software..

BTIE

Bit 4: Block Transfer interrupt enable This bit is set and cleared by software..

TCIE

Bit 5: buffer Transfer Complete interrupt enable This bit is set and cleared by software..

PL

Bits 6-7: Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0..

BEX

Bit 12: byte Endianness exchange.

HEX

Bit 13: Half word Endianes exchange.

WEX

Bit 14: Word Endianness exchange.

SWRQ

Bit 16: SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)..

TCR [4]

This register is used to configure the concerned channel.

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw
SWRM
rw
TRGM
rw
PAM
rw
PKE
rw
TLEN
rw
DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw
SBURST
rw
DINCOS
rw
SINCOS
rw
DSIZE
rw
SSIZE
rw
DINC
rw
SINC
rw
Toggle fields

SINC

Bits 0-1: Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)..

DINC

Bits 2-3: Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden..

SSIZE

Bits 4-5: Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS &lt; SSIZE and SINC &#8800; 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)..

DSIZE

Bits 6-7: Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS &lt; DSIZE and DINC &#8800; 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)..

SINCOS

Bits 8-9: source increment offset size.

DINCOS

Bits 10-11: Destination increment offset.

SBURST

Bits 12-14: source burst transfer configuration.

DBURST

Bits 15-17: Destination burst transfer configuration.

TLEN

Bits 18-24: buffer transfer lengh.

PKE

Bit 25: PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0.

PAM

Bits 26-27: Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0.

TRGM

Bits 28-29: Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0..

SWRM

Bit 30: SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0..

BWM

Bit 31: Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable..

BNDTR [4]

MDMA Channel x block number of data register

Offset: 0x154, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw
BRDUM
rw
BRSUM
rw
BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: block number of data to transfer.

BRSUM

Bit 18: Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0..

BRDUM

Bit 19: Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0..

BRC

Bits 20-31: Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0..

SAR [4]

MDMA channel x source address register

Offset: 0x158, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: source adr base.

DAR [4]

MDMA channel x destination address register

Offset: 0x15c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: Destination adr base.

BRUR [4]

MDMA channel x Block Repeat address Update register

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: source adresse update value.

DUV

Bits 16-31: destination address update.

LAR [4]

MDMA channel x Link Address register

Offset: 0x164, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: Link address register.

TBR [4]

MDMA channel x Trigger and Bus selection Register

Offset: 0x168, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw
SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: Trigger selection.

SBUS

Bit 16: Source BUS select This bit is protected and can be written only if EN is 0..

DBUS

Bit 17: Destination BUS slect This bit is protected and can be written only if EN is 0..

MAR [4]

MDMA channel x Mask address register

Offset: 0x170, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: Mask address.

MDR [4]

MDMA channel x Mask Data register

Offset: 0x174, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: Mask data.

ISR [5]

MDMA channel x interrupt/status register

Offset: 0x180, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r
BTIF
r
BRTIF
r
CTCIF
r
TEIF
r
Toggle fields

TEIF

Bit 0: Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

CTCIF

Bit 1: Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0..

BRTIF

Bit 2: Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

BTIF

Bit 3: Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

TCIF

Bit 4: channel x buffer transfer complete.

CRQA

Bit 16: channel x request active flag.

IFCR [5]

MDMA channel x interrupt flag clear register

Offset: 0x184, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w
CBTIF
w
CBRTIF
w
CCTCIF
w
CTEIF
w
Toggle fields

CTEIF

Bit 0: Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register.

CCTCIF

Bit 1: Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register.

CBRTIF

Bit 2: Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register.

CBTIF

Bit 3: Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register.

CLTCIF

Bit 4: CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register.

ESR [5]

MDMA Channel x error status register

Offset: 0x188, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r
ASE
r
TEMD
r
TELD
r
TED
r
TEA
r
Toggle fields

TEA

Bits 0-6: Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error..

TED

Bit 7: Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error..

TELD

Bit 8: Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

TEMD

Bit 9: Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

ASE

Bit 10: Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

BSE

Bit 11: Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

CR [5]

This register is used to control the concerned channel.

Offset: 0x18c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw
HEX
rw
BEX
rw
PL
rw
TCIE
rw
BTIE
rw
BRTIE
rw
CTCIE
rw
TEIE
rw
EN
rw
Toggle fields

EN

Bit 0: channel enable.

TEIE

Bit 1: Transfer error interrupt enable This bit is set and cleared by software..

CTCIE

Bit 2: Channel Transfer Complete interrupt enable This bit is set and cleared by software..

BRTIE

Bit 3: Block Repeat transfer interrupt enable This bit is set and cleared by software..

BTIE

Bit 4: Block Transfer interrupt enable This bit is set and cleared by software..

TCIE

Bit 5: buffer Transfer Complete interrupt enable This bit is set and cleared by software..

PL

Bits 6-7: Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0..

BEX

Bit 12: byte Endianness exchange.

HEX

Bit 13: Half word Endianes exchange.

WEX

Bit 14: Word Endianness exchange.

SWRQ

Bit 16: SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)..

TCR [5]

This register is used to configure the concerned channel.

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw
SWRM
rw
TRGM
rw
PAM
rw
PKE
rw
TLEN
rw
DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw
SBURST
rw
DINCOS
rw
SINCOS
rw
DSIZE
rw
SSIZE
rw
DINC
rw
SINC
rw
Toggle fields

SINC

Bits 0-1: Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)..

DINC

Bits 2-3: Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden..

SSIZE

Bits 4-5: Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS &lt; SSIZE and SINC &#8800; 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)..

DSIZE

Bits 6-7: Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS &lt; DSIZE and DINC &#8800; 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)..

SINCOS

Bits 8-9: source increment offset size.

DINCOS

Bits 10-11: Destination increment offset.

SBURST

Bits 12-14: source burst transfer configuration.

DBURST

Bits 15-17: Destination burst transfer configuration.

TLEN

Bits 18-24: buffer transfer lengh.

PKE

Bit 25: PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0.

PAM

Bits 26-27: Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0.

TRGM

Bits 28-29: Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0..

SWRM

Bit 30: SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0..

BWM

Bit 31: Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable..

BNDTR [5]

MDMA Channel x block number of data register

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw
BRDUM
rw
BRSUM
rw
BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: block number of data to transfer.

BRSUM

Bit 18: Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0..

BRDUM

Bit 19: Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0..

BRC

Bits 20-31: Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0..

SAR [5]

MDMA channel x source address register

Offset: 0x198, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: source adr base.

DAR [5]

MDMA channel x destination address register

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: Destination adr base.

BRUR [5]

MDMA channel x Block Repeat address Update register

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: source adresse update value.

DUV

Bits 16-31: destination address update.

LAR [5]

MDMA channel x Link Address register

Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: Link address register.

TBR [5]

MDMA channel x Trigger and Bus selection Register

Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw
SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: Trigger selection.

SBUS

Bit 16: Source BUS select This bit is protected and can be written only if EN is 0..

DBUS

Bit 17: Destination BUS slect This bit is protected and can be written only if EN is 0..

MAR [5]

MDMA channel x Mask address register

Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: Mask address.

MDR [5]

MDMA channel x Mask Data register

Offset: 0x1b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: Mask data.

ISR [6]

MDMA channel x interrupt/status register

Offset: 0x1c0, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r
BTIF
r
BRTIF
r
CTCIF
r
TEIF
r
Toggle fields

TEIF

Bit 0: Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

CTCIF

Bit 1: Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0..

BRTIF

Bit 2: Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

BTIF

Bit 3: Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

TCIF

Bit 4: channel x buffer transfer complete.

CRQA

Bit 16: channel x request active flag.

IFCR [6]

MDMA channel x interrupt flag clear register

Offset: 0x1c4, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w
CBTIF
w
CBRTIF
w
CCTCIF
w
CTEIF
w
Toggle fields

CTEIF

Bit 0: Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register.

CCTCIF

Bit 1: Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register.

CBRTIF

Bit 2: Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register.

CBTIF

Bit 3: Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register.

CLTCIF

Bit 4: CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register.

ESR [6]

MDMA Channel x error status register

Offset: 0x1c8, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r
ASE
r
TEMD
r
TELD
r
TED
r
TEA
r
Toggle fields

TEA

Bits 0-6: Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error..

TED

Bit 7: Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error..

TELD

Bit 8: Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

TEMD

Bit 9: Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

ASE

Bit 10: Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

BSE

Bit 11: Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

CR [6]

This register is used to control the concerned channel.

Offset: 0x1cc, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw
HEX
rw
BEX
rw
PL
rw
TCIE
rw
BTIE
rw
BRTIE
rw
CTCIE
rw
TEIE
rw
EN
rw
Toggle fields

EN

Bit 0: channel enable.

TEIE

Bit 1: Transfer error interrupt enable This bit is set and cleared by software..

CTCIE

Bit 2: Channel Transfer Complete interrupt enable This bit is set and cleared by software..

BRTIE

Bit 3: Block Repeat transfer interrupt enable This bit is set and cleared by software..

BTIE

Bit 4: Block Transfer interrupt enable This bit is set and cleared by software..

TCIE

Bit 5: buffer Transfer Complete interrupt enable This bit is set and cleared by software..

PL

Bits 6-7: Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0..

BEX

Bit 12: byte Endianness exchange.

HEX

Bit 13: Half word Endianes exchange.

WEX

Bit 14: Word Endianness exchange.

SWRQ

Bit 16: SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)..

TCR [6]

This register is used to configure the concerned channel.

Offset: 0x1d0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw
SWRM
rw
TRGM
rw
PAM
rw
PKE
rw
TLEN
rw
DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw
SBURST
rw
DINCOS
rw
SINCOS
rw
DSIZE
rw
SSIZE
rw
DINC
rw
SINC
rw
Toggle fields

SINC

Bits 0-1: Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)..

DINC

Bits 2-3: Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden..

SSIZE

Bits 4-5: Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS &lt; SSIZE and SINC &#8800; 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)..

DSIZE

Bits 6-7: Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS &lt; DSIZE and DINC &#8800; 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)..

SINCOS

Bits 8-9: source increment offset size.

DINCOS

Bits 10-11: Destination increment offset.

SBURST

Bits 12-14: source burst transfer configuration.

DBURST

Bits 15-17: Destination burst transfer configuration.

TLEN

Bits 18-24: buffer transfer lengh.

PKE

Bit 25: PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0.

PAM

Bits 26-27: Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0.

TRGM

Bits 28-29: Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0..

SWRM

Bit 30: SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0..

BWM

Bit 31: Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable..

BNDTR [6]

MDMA Channel x block number of data register

Offset: 0x1d4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw
BRDUM
rw
BRSUM
rw
BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: block number of data to transfer.

BRSUM

Bit 18: Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0..

BRDUM

Bit 19: Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0..

BRC

Bits 20-31: Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0..

SAR [6]

MDMA channel x source address register

Offset: 0x1d8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: source adr base.

DAR [6]

MDMA channel x destination address register

Offset: 0x1dc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: Destination adr base.

BRUR [6]

MDMA channel x Block Repeat address Update register

Offset: 0x1e0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: source adresse update value.

DUV

Bits 16-31: destination address update.

LAR [6]

MDMA channel x Link Address register

Offset: 0x1e4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: Link address register.

TBR [6]

MDMA channel x Trigger and Bus selection Register

Offset: 0x1e8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw
SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: Trigger selection.

SBUS

Bit 16: Source BUS select This bit is protected and can be written only if EN is 0..

DBUS

Bit 17: Destination BUS slect This bit is protected and can be written only if EN is 0..

MAR [6]

MDMA channel x Mask address register

Offset: 0x1f0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: Mask address.

MDR [6]

MDMA channel x Mask Data register

Offset: 0x1f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: Mask data.

ISR [7]

MDMA channel x interrupt/status register

Offset: 0x200, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r
BTIF
r
BRTIF
r
CTCIF
r
TEIF
r
Toggle fields

TEIF

Bit 0: Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

CTCIF

Bit 1: Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0..

BRTIF

Bit 2: Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

BTIF

Bit 3: Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

TCIF

Bit 4: channel x buffer transfer complete.

CRQA

Bit 16: channel x request active flag.

IFCR [7]

MDMA channel x interrupt flag clear register

Offset: 0x204, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w
CBTIF
w
CBRTIF
w
CCTCIF
w
CTEIF
w
Toggle fields

CTEIF

Bit 0: Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register.

CCTCIF

Bit 1: Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register.

CBRTIF

Bit 2: Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register.

CBTIF

Bit 3: Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register.

CLTCIF

Bit 4: CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register.

ESR [7]

MDMA Channel x error status register

Offset: 0x208, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r
ASE
r
TEMD
r
TELD
r
TED
r
TEA
r
Toggle fields

TEA

Bits 0-6: Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error..

TED

Bit 7: Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error..

TELD

Bit 8: Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

TEMD

Bit 9: Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

ASE

Bit 10: Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

BSE

Bit 11: Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

CR [7]

This register is used to control the concerned channel.

Offset: 0x20c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw
HEX
rw
BEX
rw
PL
rw
TCIE
rw
BTIE
rw
BRTIE
rw
CTCIE
rw
TEIE
rw
EN
rw
Toggle fields

EN

Bit 0: channel enable.

TEIE

Bit 1: Transfer error interrupt enable This bit is set and cleared by software..

CTCIE

Bit 2: Channel Transfer Complete interrupt enable This bit is set and cleared by software..

BRTIE

Bit 3: Block Repeat transfer interrupt enable This bit is set and cleared by software..

BTIE

Bit 4: Block Transfer interrupt enable This bit is set and cleared by software..

TCIE

Bit 5: buffer Transfer Complete interrupt enable This bit is set and cleared by software..

PL

Bits 6-7: Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0..

BEX

Bit 12: byte Endianness exchange.

HEX

Bit 13: Half word Endianes exchange.

WEX

Bit 14: Word Endianness exchange.

SWRQ

Bit 16: SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)..

TCR [7]

This register is used to configure the concerned channel.

Offset: 0x210, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw
SWRM
rw
TRGM
rw
PAM
rw
PKE
rw
TLEN
rw
DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw
SBURST
rw
DINCOS
rw
SINCOS
rw
DSIZE
rw
SSIZE
rw
DINC
rw
SINC
rw
Toggle fields

SINC

Bits 0-1: Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)..

DINC

Bits 2-3: Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden..

SSIZE

Bits 4-5: Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS &lt; SSIZE and SINC &#8800; 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)..

DSIZE

Bits 6-7: Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS &lt; DSIZE and DINC &#8800; 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)..

SINCOS

Bits 8-9: source increment offset size.

DINCOS

Bits 10-11: Destination increment offset.

SBURST

Bits 12-14: source burst transfer configuration.

DBURST

Bits 15-17: Destination burst transfer configuration.

TLEN

Bits 18-24: buffer transfer lengh.

PKE

Bit 25: PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0.

PAM

Bits 26-27: Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0.

TRGM

Bits 28-29: Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0..

SWRM

Bit 30: SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0..

BWM

Bit 31: Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable..

BNDTR [7]

MDMA Channel x block number of data register

Offset: 0x214, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw
BRDUM
rw
BRSUM
rw
BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: block number of data to transfer.

BRSUM

Bit 18: Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0..

BRDUM

Bit 19: Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0..

BRC

Bits 20-31: Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0..

SAR [7]

MDMA channel x source address register

Offset: 0x218, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: source adr base.

DAR [7]

MDMA channel x destination address register

Offset: 0x21c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: Destination adr base.

BRUR [7]

MDMA channel x Block Repeat address Update register

Offset: 0x220, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: source adresse update value.

DUV

Bits 16-31: destination address update.

LAR [7]

MDMA channel x Link Address register

Offset: 0x224, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: Link address register.

TBR [7]

MDMA channel x Trigger and Bus selection Register

Offset: 0x228, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw
SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: Trigger selection.

SBUS

Bit 16: Source BUS select This bit is protected and can be written only if EN is 0..

DBUS

Bit 17: Destination BUS slect This bit is protected and can be written only if EN is 0..

MAR [7]

MDMA channel x Mask address register

Offset: 0x230, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: Mask address.

MDR [7]

MDMA channel x Mask Data register

Offset: 0x234, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: Mask data.

ISR [8]

MDMA channel x interrupt/status register

Offset: 0x240, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r
BTIF
r
BRTIF
r
CTCIF
r
TEIF
r
Toggle fields

TEIF

Bit 0: Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

CTCIF

Bit 1: Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0..

BRTIF

Bit 2: Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

BTIF

Bit 3: Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

TCIF

Bit 4: channel x buffer transfer complete.

CRQA

Bit 16: channel x request active flag.

IFCR [8]

MDMA channel x interrupt flag clear register

Offset: 0x244, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w
CBTIF
w
CBRTIF
w
CCTCIF
w
CTEIF
w
Toggle fields

CTEIF

Bit 0: Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register.

CCTCIF

Bit 1: Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register.

CBRTIF

Bit 2: Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register.

CBTIF

Bit 3: Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register.

CLTCIF

Bit 4: CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register.

ESR [8]

MDMA Channel x error status register

Offset: 0x248, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r
ASE
r
TEMD
r
TELD
r
TED
r
TEA
r
Toggle fields

TEA

Bits 0-6: Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error..

TED

Bit 7: Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error..

TELD

Bit 8: Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

TEMD

Bit 9: Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

ASE

Bit 10: Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

BSE

Bit 11: Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

CR [8]

This register is used to control the concerned channel.

Offset: 0x24c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw
HEX
rw
BEX
rw
PL
rw
TCIE
rw
BTIE
rw
BRTIE
rw
CTCIE
rw
TEIE
rw
EN
rw
Toggle fields

EN

Bit 0: channel enable.

TEIE

Bit 1: Transfer error interrupt enable This bit is set and cleared by software..

CTCIE

Bit 2: Channel Transfer Complete interrupt enable This bit is set and cleared by software..

BRTIE

Bit 3: Block Repeat transfer interrupt enable This bit is set and cleared by software..

BTIE

Bit 4: Block Transfer interrupt enable This bit is set and cleared by software..

TCIE

Bit 5: buffer Transfer Complete interrupt enable This bit is set and cleared by software..

PL

Bits 6-7: Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0..

BEX

Bit 12: byte Endianness exchange.

HEX

Bit 13: Half word Endianes exchange.

WEX

Bit 14: Word Endianness exchange.

SWRQ

Bit 16: SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)..

TCR [8]

This register is used to configure the concerned channel.

Offset: 0x250, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw
SWRM
rw
TRGM
rw
PAM
rw
PKE
rw
TLEN
rw
DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw
SBURST
rw
DINCOS
rw
SINCOS
rw
DSIZE
rw
SSIZE
rw
DINC
rw
SINC
rw
Toggle fields

SINC

Bits 0-1: Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)..

DINC

Bits 2-3: Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden..

SSIZE

Bits 4-5: Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS &lt; SSIZE and SINC &#8800; 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)..

DSIZE

Bits 6-7: Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS &lt; DSIZE and DINC &#8800; 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)..

SINCOS

Bits 8-9: source increment offset size.

DINCOS

Bits 10-11: Destination increment offset.

SBURST

Bits 12-14: source burst transfer configuration.

DBURST

Bits 15-17: Destination burst transfer configuration.

TLEN

Bits 18-24: buffer transfer lengh.

PKE

Bit 25: PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0.

PAM

Bits 26-27: Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0.

TRGM

Bits 28-29: Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0..

SWRM

Bit 30: SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0..

BWM

Bit 31: Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable..

BNDTR [8]

MDMA Channel x block number of data register

Offset: 0x254, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw
BRDUM
rw
BRSUM
rw
BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: block number of data to transfer.

BRSUM

Bit 18: Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0..

BRDUM

Bit 19: Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0..

BRC

Bits 20-31: Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0..

SAR [8]

MDMA channel x source address register

Offset: 0x258, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: source adr base.

DAR [8]

MDMA channel x destination address register

Offset: 0x25c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: Destination adr base.

BRUR [8]

MDMA channel x Block Repeat address Update register

Offset: 0x260, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: source adresse update value.

DUV

Bits 16-31: destination address update.

LAR [8]

MDMA channel x Link Address register

Offset: 0x264, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: Link address register.

TBR [8]

MDMA channel x Trigger and Bus selection Register

Offset: 0x268, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw
SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: Trigger selection.

SBUS

Bit 16: Source BUS select This bit is protected and can be written only if EN is 0..

DBUS

Bit 17: Destination BUS slect This bit is protected and can be written only if EN is 0..

MAR [8]

MDMA channel x Mask address register

Offset: 0x270, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: Mask address.

MDR [8]

MDMA channel x Mask Data register

Offset: 0x274, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: Mask data.

ISR [9]

MDMA channel x interrupt/status register

Offset: 0x280, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r
BTIF
r
BRTIF
r
CTCIF
r
TEIF
r
Toggle fields

TEIF

Bit 0: Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

CTCIF

Bit 1: Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0..

BRTIF

Bit 2: Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

BTIF

Bit 3: Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

TCIF

Bit 4: channel x buffer transfer complete.

CRQA

Bit 16: channel x request active flag.

IFCR [9]

MDMA channel x interrupt flag clear register

Offset: 0x284, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w
CBTIF
w
CBRTIF
w
CCTCIF
w
CTEIF
w
Toggle fields

CTEIF

Bit 0: Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register.

CCTCIF

Bit 1: Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register.

CBRTIF

Bit 2: Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register.

CBTIF

Bit 3: Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register.

CLTCIF

Bit 4: CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register.

ESR [9]

MDMA Channel x error status register

Offset: 0x288, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r
ASE
r
TEMD
r
TELD
r
TED
r
TEA
r
Toggle fields

TEA

Bits 0-6: Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error..

TED

Bit 7: Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error..

TELD

Bit 8: Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

TEMD

Bit 9: Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

ASE

Bit 10: Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

BSE

Bit 11: Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

CR [9]

This register is used to control the concerned channel.

Offset: 0x28c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw
HEX
rw
BEX
rw
PL
rw
TCIE
rw
BTIE
rw
BRTIE
rw
CTCIE
rw
TEIE
rw
EN
rw
Toggle fields

EN

Bit 0: channel enable.

TEIE

Bit 1: Transfer error interrupt enable This bit is set and cleared by software..

CTCIE

Bit 2: Channel Transfer Complete interrupt enable This bit is set and cleared by software..

BRTIE

Bit 3: Block Repeat transfer interrupt enable This bit is set and cleared by software..

BTIE

Bit 4: Block Transfer interrupt enable This bit is set and cleared by software..

TCIE

Bit 5: buffer Transfer Complete interrupt enable This bit is set and cleared by software..

PL

Bits 6-7: Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0..

BEX

Bit 12: byte Endianness exchange.

HEX

Bit 13: Half word Endianes exchange.

WEX

Bit 14: Word Endianness exchange.

SWRQ

Bit 16: SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)..

TCR [9]

This register is used to configure the concerned channel.

Offset: 0x290, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw
SWRM
rw
TRGM
rw
PAM
rw
PKE
rw
TLEN
rw
DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw
SBURST
rw
DINCOS
rw
SINCOS
rw
DSIZE
rw
SSIZE
rw
DINC
rw
SINC
rw
Toggle fields

SINC

Bits 0-1: Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)..

DINC

Bits 2-3: Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden..

SSIZE

Bits 4-5: Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS &lt; SSIZE and SINC &#8800; 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)..

DSIZE

Bits 6-7: Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS &lt; DSIZE and DINC &#8800; 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)..

SINCOS

Bits 8-9: source increment offset size.

DINCOS

Bits 10-11: Destination increment offset.

SBURST

Bits 12-14: source burst transfer configuration.

DBURST

Bits 15-17: Destination burst transfer configuration.

TLEN

Bits 18-24: buffer transfer lengh.

PKE

Bit 25: PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0.

PAM

Bits 26-27: Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0.

TRGM

Bits 28-29: Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0..

SWRM

Bit 30: SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0..

BWM

Bit 31: Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable..

BNDTR [9]

MDMA Channel x block number of data register

Offset: 0x294, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw
BRDUM
rw
BRSUM
rw
BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: block number of data to transfer.

BRSUM

Bit 18: Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0..

BRDUM

Bit 19: Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0..

BRC

Bits 20-31: Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0..

SAR [9]

MDMA channel x source address register

Offset: 0x298, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: source adr base.

DAR [9]

MDMA channel x destination address register

Offset: 0x29c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: Destination adr base.

BRUR [9]

MDMA channel x Block Repeat address Update register

Offset: 0x2a0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: source adresse update value.

DUV

Bits 16-31: destination address update.

LAR [9]

MDMA channel x Link Address register

Offset: 0x2a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: Link address register.

TBR [9]

MDMA channel x Trigger and Bus selection Register

Offset: 0x2a8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw
SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: Trigger selection.

SBUS

Bit 16: Source BUS select This bit is protected and can be written only if EN is 0..

DBUS

Bit 17: Destination BUS slect This bit is protected and can be written only if EN is 0..

MAR [9]

MDMA channel x Mask address register

Offset: 0x2b0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: Mask address.

MDR [9]

MDMA channel x Mask Data register

Offset: 0x2b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: Mask data.

ISR [10]

MDMA channel x interrupt/status register

Offset: 0x2c0, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r
BTIF
r
BRTIF
r
CTCIF
r
TEIF
r
Toggle fields

TEIF

Bit 0: Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

CTCIF

Bit 1: Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0..

BRTIF

Bit 2: Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

BTIF

Bit 3: Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

TCIF

Bit 4: channel x buffer transfer complete.

CRQA

Bit 16: channel x request active flag.

IFCR [10]

MDMA channel x interrupt flag clear register

Offset: 0x2c4, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w
CBTIF
w
CBRTIF
w
CCTCIF
w
CTEIF
w
Toggle fields

CTEIF

Bit 0: Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register.

CCTCIF

Bit 1: Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register.

CBRTIF

Bit 2: Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register.

CBTIF

Bit 3: Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register.

CLTCIF

Bit 4: CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register.

ESR [10]

MDMA Channel x error status register

Offset: 0x2c8, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r
ASE
r
TEMD
r
TELD
r
TED
r
TEA
r
Toggle fields

TEA

Bits 0-6: Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error..

TED

Bit 7: Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error..

TELD

Bit 8: Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

TEMD

Bit 9: Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

ASE

Bit 10: Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

BSE

Bit 11: Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

CR [10]

This register is used to control the concerned channel.

Offset: 0x2cc, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw
HEX
rw
BEX
rw
PL
rw
TCIE
rw
BTIE
rw
BRTIE
rw
CTCIE
rw
TEIE
rw
EN
rw
Toggle fields

EN

Bit 0: channel enable.

TEIE

Bit 1: Transfer error interrupt enable This bit is set and cleared by software..

CTCIE

Bit 2: Channel Transfer Complete interrupt enable This bit is set and cleared by software..

BRTIE

Bit 3: Block Repeat transfer interrupt enable This bit is set and cleared by software..

BTIE

Bit 4: Block Transfer interrupt enable This bit is set and cleared by software..

TCIE

Bit 5: buffer Transfer Complete interrupt enable This bit is set and cleared by software..

PL

Bits 6-7: Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0..

BEX

Bit 12: byte Endianness exchange.

HEX

Bit 13: Half word Endianes exchange.

WEX

Bit 14: Word Endianness exchange.

SWRQ

Bit 16: SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)..

TCR [10]

This register is used to configure the concerned channel.

Offset: 0x2d0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw
SWRM
rw
TRGM
rw
PAM
rw
PKE
rw
TLEN
rw
DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw
SBURST
rw
DINCOS
rw
SINCOS
rw
DSIZE
rw
SSIZE
rw
DINC
rw
SINC
rw
Toggle fields

SINC

Bits 0-1: Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)..

DINC

Bits 2-3: Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden..

SSIZE

Bits 4-5: Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS &lt; SSIZE and SINC &#8800; 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)..

DSIZE

Bits 6-7: Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS &lt; DSIZE and DINC &#8800; 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)..

SINCOS

Bits 8-9: source increment offset size.

DINCOS

Bits 10-11: Destination increment offset.

SBURST

Bits 12-14: source burst transfer configuration.

DBURST

Bits 15-17: Destination burst transfer configuration.

TLEN

Bits 18-24: buffer transfer lengh.

PKE

Bit 25: PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0.

PAM

Bits 26-27: Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0.

TRGM

Bits 28-29: Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0..

SWRM

Bit 30: SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0..

BWM

Bit 31: Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable..

BNDTR [10]

MDMA Channel x block number of data register

Offset: 0x2d4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw
BRDUM
rw
BRSUM
rw
BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: block number of data to transfer.

BRSUM

Bit 18: Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0..

BRDUM

Bit 19: Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0..

BRC

Bits 20-31: Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0..

SAR [10]

MDMA channel x source address register

Offset: 0x2d8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: source adr base.

DAR [10]

MDMA channel x destination address register

Offset: 0x2dc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: Destination adr base.

BRUR [10]

MDMA channel x Block Repeat address Update register

Offset: 0x2e0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: source adresse update value.

DUV

Bits 16-31: destination address update.

LAR [10]

MDMA channel x Link Address register

Offset: 0x2e4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: Link address register.

TBR [10]

MDMA channel x Trigger and Bus selection Register

Offset: 0x2e8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw
SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: Trigger selection.

SBUS

Bit 16: Source BUS select This bit is protected and can be written only if EN is 0..

DBUS

Bit 17: Destination BUS slect This bit is protected and can be written only if EN is 0..

MAR [10]

MDMA channel x Mask address register

Offset: 0x2f0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: Mask address.

MDR [10]

MDMA channel x Mask Data register

Offset: 0x2f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: Mask data.

ISR [11]

MDMA channel x interrupt/status register

Offset: 0x300, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r
BTIF
r
BRTIF
r
CTCIF
r
TEIF
r
Toggle fields

TEIF

Bit 0: Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

CTCIF

Bit 1: Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0..

BRTIF

Bit 2: Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

BTIF

Bit 3: Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

TCIF

Bit 4: channel x buffer transfer complete.

CRQA

Bit 16: channel x request active flag.

IFCR [11]

MDMA channel x interrupt flag clear register

Offset: 0x304, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w
CBTIF
w
CBRTIF
w
CCTCIF
w
CTEIF
w
Toggle fields

CTEIF

Bit 0: Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register.

CCTCIF

Bit 1: Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register.

CBRTIF

Bit 2: Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register.

CBTIF

Bit 3: Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register.

CLTCIF

Bit 4: CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register.

ESR [11]

MDMA Channel x error status register

Offset: 0x308, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r
ASE
r
TEMD
r
TELD
r
TED
r
TEA
r
Toggle fields

TEA

Bits 0-6: Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error..

TED

Bit 7: Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error..

TELD

Bit 8: Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

TEMD

Bit 9: Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

ASE

Bit 10: Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

BSE

Bit 11: Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

CR [11]

This register is used to control the concerned channel.

Offset: 0x30c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw
HEX
rw
BEX
rw
PL
rw
TCIE
rw
BTIE
rw
BRTIE
rw
CTCIE
rw
TEIE
rw
EN
rw
Toggle fields

EN

Bit 0: channel enable.

TEIE

Bit 1: Transfer error interrupt enable This bit is set and cleared by software..

CTCIE

Bit 2: Channel Transfer Complete interrupt enable This bit is set and cleared by software..

BRTIE

Bit 3: Block Repeat transfer interrupt enable This bit is set and cleared by software..

BTIE

Bit 4: Block Transfer interrupt enable This bit is set and cleared by software..

TCIE

Bit 5: buffer Transfer Complete interrupt enable This bit is set and cleared by software..

PL

Bits 6-7: Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0..

BEX

Bit 12: byte Endianness exchange.

HEX

Bit 13: Half word Endianes exchange.

WEX

Bit 14: Word Endianness exchange.

SWRQ

Bit 16: SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)..

TCR [11]

This register is used to configure the concerned channel.

Offset: 0x310, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw
SWRM
rw
TRGM
rw
PAM
rw
PKE
rw
TLEN
rw
DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw
SBURST
rw
DINCOS
rw
SINCOS
rw
DSIZE
rw
SSIZE
rw
DINC
rw
SINC
rw
Toggle fields

SINC

Bits 0-1: Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)..

DINC

Bits 2-3: Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden..

SSIZE

Bits 4-5: Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS &lt; SSIZE and SINC &#8800; 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)..

DSIZE

Bits 6-7: Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS &lt; DSIZE and DINC &#8800; 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)..

SINCOS

Bits 8-9: source increment offset size.

DINCOS

Bits 10-11: Destination increment offset.

SBURST

Bits 12-14: source burst transfer configuration.

DBURST

Bits 15-17: Destination burst transfer configuration.

TLEN

Bits 18-24: buffer transfer lengh.

PKE

Bit 25: PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0.

PAM

Bits 26-27: Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0.

TRGM

Bits 28-29: Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0..

SWRM

Bit 30: SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0..

BWM

Bit 31: Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable..

BNDTR [11]

MDMA Channel x block number of data register

Offset: 0x314, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw
BRDUM
rw
BRSUM
rw
BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: block number of data to transfer.

BRSUM

Bit 18: Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0..

BRDUM

Bit 19: Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0..

BRC

Bits 20-31: Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0..

SAR [11]

MDMA channel x source address register

Offset: 0x318, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: source adr base.

DAR [11]

MDMA channel x destination address register

Offset: 0x31c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: Destination adr base.

BRUR [11]

MDMA channel x Block Repeat address Update register

Offset: 0x320, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: source adresse update value.

DUV

Bits 16-31: destination address update.

LAR [11]

MDMA channel x Link Address register

Offset: 0x324, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: Link address register.

TBR [11]

MDMA channel x Trigger and Bus selection Register

Offset: 0x328, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw
SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: Trigger selection.

SBUS

Bit 16: Source BUS select This bit is protected and can be written only if EN is 0..

DBUS

Bit 17: Destination BUS slect This bit is protected and can be written only if EN is 0..

MAR [11]

MDMA channel x Mask address register

Offset: 0x330, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: Mask address.

MDR [11]

MDMA channel x Mask Data register

Offset: 0x334, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: Mask data.

ISR [12]

MDMA channel x interrupt/status register

Offset: 0x340, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r
BTIF
r
BRTIF
r
CTCIF
r
TEIF
r
Toggle fields

TEIF

Bit 0: Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

CTCIF

Bit 1: Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0..

BRTIF

Bit 2: Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

BTIF

Bit 3: Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

TCIF

Bit 4: channel x buffer transfer complete.

CRQA

Bit 16: channel x request active flag.

IFCR [12]

MDMA channel x interrupt flag clear register

Offset: 0x344, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w
CBTIF
w
CBRTIF
w
CCTCIF
w
CTEIF
w
Toggle fields

CTEIF

Bit 0: Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register.

CCTCIF

Bit 1: Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register.

CBRTIF

Bit 2: Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register.

CBTIF

Bit 3: Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register.

CLTCIF

Bit 4: CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register.

ESR [12]

MDMA Channel x error status register

Offset: 0x348, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r
ASE
r
TEMD
r
TELD
r
TED
r
TEA
r
Toggle fields

TEA

Bits 0-6: Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error..

TED

Bit 7: Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error..

TELD

Bit 8: Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

TEMD

Bit 9: Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

ASE

Bit 10: Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

BSE

Bit 11: Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

CR [12]

This register is used to control the concerned channel.

Offset: 0x34c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw
HEX
rw
BEX
rw
PL
rw
TCIE
rw
BTIE
rw
BRTIE
rw
CTCIE
rw
TEIE
rw
EN
rw
Toggle fields

EN

Bit 0: channel enable.

TEIE

Bit 1: Transfer error interrupt enable This bit is set and cleared by software..

CTCIE

Bit 2: Channel Transfer Complete interrupt enable This bit is set and cleared by software..

BRTIE

Bit 3: Block Repeat transfer interrupt enable This bit is set and cleared by software..

BTIE

Bit 4: Block Transfer interrupt enable This bit is set and cleared by software..

TCIE

Bit 5: buffer Transfer Complete interrupt enable This bit is set and cleared by software..

PL

Bits 6-7: Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0..

BEX

Bit 12: byte Endianness exchange.

HEX

Bit 13: Half word Endianes exchange.

WEX

Bit 14: Word Endianness exchange.

SWRQ

Bit 16: SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)..

TCR [12]

This register is used to configure the concerned channel.

Offset: 0x350, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw
SWRM
rw
TRGM
rw
PAM
rw
PKE
rw
TLEN
rw
DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw
SBURST
rw
DINCOS
rw
SINCOS
rw
DSIZE
rw
SSIZE
rw
DINC
rw
SINC
rw
Toggle fields

SINC

Bits 0-1: Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)..

DINC

Bits 2-3: Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden..

SSIZE

Bits 4-5: Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS &lt; SSIZE and SINC &#8800; 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)..

DSIZE

Bits 6-7: Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS &lt; DSIZE and DINC &#8800; 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)..

SINCOS

Bits 8-9: source increment offset size.

DINCOS

Bits 10-11: Destination increment offset.

SBURST

Bits 12-14: source burst transfer configuration.

DBURST

Bits 15-17: Destination burst transfer configuration.

TLEN

Bits 18-24: buffer transfer lengh.

PKE

Bit 25: PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0.

PAM

Bits 26-27: Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0.

TRGM

Bits 28-29: Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0..

SWRM

Bit 30: SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0..

BWM

Bit 31: Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable..

BNDTR [12]

MDMA Channel x block number of data register

Offset: 0x354, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw
BRDUM
rw
BRSUM
rw
BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: block number of data to transfer.

BRSUM

Bit 18: Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0..

BRDUM

Bit 19: Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0..

BRC

Bits 20-31: Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0..

SAR [12]

MDMA channel x source address register

Offset: 0x358, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: source adr base.

DAR [12]

MDMA channel x destination address register

Offset: 0x35c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: Destination adr base.

BRUR [12]

MDMA channel x Block Repeat address Update register

Offset: 0x360, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: source adresse update value.

DUV

Bits 16-31: destination address update.

LAR [12]

MDMA channel x Link Address register

Offset: 0x364, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: Link address register.

TBR [12]

MDMA channel x Trigger and Bus selection Register

Offset: 0x368, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw
SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: Trigger selection.

SBUS

Bit 16: Source BUS select This bit is protected and can be written only if EN is 0..

DBUS

Bit 17: Destination BUS slect This bit is protected and can be written only if EN is 0..

MAR [12]

MDMA channel x Mask address register

Offset: 0x370, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: Mask address.

MDR [12]

MDMA channel x Mask Data register

Offset: 0x374, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: Mask data.

ISR [13]

MDMA channel x interrupt/status register

Offset: 0x380, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r
BTIF
r
BRTIF
r
CTCIF
r
TEIF
r
Toggle fields

TEIF

Bit 0: Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

CTCIF

Bit 1: Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0..

BRTIF

Bit 2: Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

BTIF

Bit 3: Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

TCIF

Bit 4: channel x buffer transfer complete.

CRQA

Bit 16: channel x request active flag.

IFCR [13]

MDMA channel x interrupt flag clear register

Offset: 0x384, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w
CBTIF
w
CBRTIF
w
CCTCIF
w
CTEIF
w
Toggle fields

CTEIF

Bit 0: Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register.

CCTCIF

Bit 1: Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register.

CBRTIF

Bit 2: Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register.

CBTIF

Bit 3: Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register.

CLTCIF

Bit 4: CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register.

ESR [13]

MDMA Channel x error status register

Offset: 0x388, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r
ASE
r
TEMD
r
TELD
r
TED
r
TEA
r
Toggle fields

TEA

Bits 0-6: Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error..

TED

Bit 7: Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error..

TELD

Bit 8: Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

TEMD

Bit 9: Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

ASE

Bit 10: Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

BSE

Bit 11: Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

CR [13]

This register is used to control the concerned channel.

Offset: 0x38c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw
HEX
rw
BEX
rw
PL
rw
TCIE
rw
BTIE
rw
BRTIE
rw
CTCIE
rw
TEIE
rw
EN
rw
Toggle fields

EN

Bit 0: channel enable.

TEIE

Bit 1: Transfer error interrupt enable This bit is set and cleared by software..

CTCIE

Bit 2: Channel Transfer Complete interrupt enable This bit is set and cleared by software..

BRTIE

Bit 3: Block Repeat transfer interrupt enable This bit is set and cleared by software..

BTIE

Bit 4: Block Transfer interrupt enable This bit is set and cleared by software..

TCIE

Bit 5: buffer Transfer Complete interrupt enable This bit is set and cleared by software..

PL

Bits 6-7: Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0..

BEX

Bit 12: byte Endianness exchange.

HEX

Bit 13: Half word Endianes exchange.

WEX

Bit 14: Word Endianness exchange.

SWRQ

Bit 16: SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)..

TCR [13]

This register is used to configure the concerned channel.

Offset: 0x390, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw
SWRM
rw
TRGM
rw
PAM
rw
PKE
rw
TLEN
rw
DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw
SBURST
rw
DINCOS
rw
SINCOS
rw
DSIZE
rw
SSIZE
rw
DINC
rw
SINC
rw
Toggle fields

SINC

Bits 0-1: Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)..

DINC

Bits 2-3: Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden..

SSIZE

Bits 4-5: Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS &lt; SSIZE and SINC &#8800; 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)..

DSIZE

Bits 6-7: Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS &lt; DSIZE and DINC &#8800; 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)..

SINCOS

Bits 8-9: source increment offset size.

DINCOS

Bits 10-11: Destination increment offset.

SBURST

Bits 12-14: source burst transfer configuration.

DBURST

Bits 15-17: Destination burst transfer configuration.

TLEN

Bits 18-24: buffer transfer lengh.

PKE

Bit 25: PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0.

PAM

Bits 26-27: Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0.

TRGM

Bits 28-29: Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0..

SWRM

Bit 30: SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0..

BWM

Bit 31: Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable..

BNDTR [13]

MDMA Channel x block number of data register

Offset: 0x394, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw
BRDUM
rw
BRSUM
rw
BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: block number of data to transfer.

BRSUM

Bit 18: Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0..

BRDUM

Bit 19: Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0..

BRC

Bits 20-31: Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0..

SAR [13]

MDMA channel x source address register

Offset: 0x398, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: source adr base.

DAR [13]

MDMA channel x destination address register

Offset: 0x39c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: Destination adr base.

BRUR [13]

MDMA channel x Block Repeat address Update register

Offset: 0x3a0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: source adresse update value.

DUV

Bits 16-31: destination address update.

LAR [13]

MDMA channel x Link Address register

Offset: 0x3a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: Link address register.

TBR [13]

MDMA channel x Trigger and Bus selection Register

Offset: 0x3a8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw
SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: Trigger selection.

SBUS

Bit 16: Source BUS select This bit is protected and can be written only if EN is 0..

DBUS

Bit 17: Destination BUS slect This bit is protected and can be written only if EN is 0..

MAR [13]

MDMA channel x Mask address register

Offset: 0x3b0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: Mask address.

MDR [13]

MDMA channel x Mask Data register

Offset: 0x3b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: Mask data.

ISR [14]

MDMA channel x interrupt/status register

Offset: 0x3c0, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r
BTIF
r
BRTIF
r
CTCIF
r
TEIF
r
Toggle fields

TEIF

Bit 0: Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

CTCIF

Bit 1: Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0..

BRTIF

Bit 2: Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

BTIF

Bit 3: Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

TCIF

Bit 4: channel x buffer transfer complete.

CRQA

Bit 16: channel x request active flag.

IFCR [14]

MDMA channel x interrupt flag clear register

Offset: 0x3c4, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w
CBTIF
w
CBRTIF
w
CCTCIF
w
CTEIF
w
Toggle fields

CTEIF

Bit 0: Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register.

CCTCIF

Bit 1: Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register.

CBRTIF

Bit 2: Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register.

CBTIF

Bit 3: Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register.

CLTCIF

Bit 4: CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register.

ESR [14]

MDMA Channel x error status register

Offset: 0x3c8, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r
ASE
r
TEMD
r
TELD
r
TED
r
TEA
r
Toggle fields

TEA

Bits 0-6: Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error..

TED

Bit 7: Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error..

TELD

Bit 8: Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

TEMD

Bit 9: Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

ASE

Bit 10: Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

BSE

Bit 11: Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

CR [14]

This register is used to control the concerned channel.

Offset: 0x3cc, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw
HEX
rw
BEX
rw
PL
rw
TCIE
rw
BTIE
rw
BRTIE
rw
CTCIE
rw
TEIE
rw
EN
rw
Toggle fields

EN

Bit 0: channel enable.

TEIE

Bit 1: Transfer error interrupt enable This bit is set and cleared by software..

CTCIE

Bit 2: Channel Transfer Complete interrupt enable This bit is set and cleared by software..

BRTIE

Bit 3: Block Repeat transfer interrupt enable This bit is set and cleared by software..

BTIE

Bit 4: Block Transfer interrupt enable This bit is set and cleared by software..

TCIE

Bit 5: buffer Transfer Complete interrupt enable This bit is set and cleared by software..

PL

Bits 6-7: Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0..

BEX

Bit 12: byte Endianness exchange.

HEX

Bit 13: Half word Endianes exchange.

WEX

Bit 14: Word Endianness exchange.

SWRQ

Bit 16: SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)..

TCR [14]

This register is used to configure the concerned channel.

Offset: 0x3d0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw
SWRM
rw
TRGM
rw
PAM
rw
PKE
rw
TLEN
rw
DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw
SBURST
rw
DINCOS
rw
SINCOS
rw
DSIZE
rw
SSIZE
rw
DINC
rw
SINC
rw
Toggle fields

SINC

Bits 0-1: Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)..

DINC

Bits 2-3: Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden..

SSIZE

Bits 4-5: Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS &lt; SSIZE and SINC &#8800; 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)..

DSIZE

Bits 6-7: Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS &lt; DSIZE and DINC &#8800; 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)..

SINCOS

Bits 8-9: source increment offset size.

DINCOS

Bits 10-11: Destination increment offset.

SBURST

Bits 12-14: source burst transfer configuration.

DBURST

Bits 15-17: Destination burst transfer configuration.

TLEN

Bits 18-24: buffer transfer lengh.

PKE

Bit 25: PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0.

PAM

Bits 26-27: Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0.

TRGM

Bits 28-29: Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0..

SWRM

Bit 30: SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0..

BWM

Bit 31: Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable..

BNDTR [14]

MDMA Channel x block number of data register

Offset: 0x3d4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw
BRDUM
rw
BRSUM
rw
BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: block number of data to transfer.

BRSUM

Bit 18: Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0..

BRDUM

Bit 19: Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0..

BRC

Bits 20-31: Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0..

SAR [14]

MDMA channel x source address register

Offset: 0x3d8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: source adr base.

DAR [14]

MDMA channel x destination address register

Offset: 0x3dc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: Destination adr base.

BRUR [14]

MDMA channel x Block Repeat address Update register

Offset: 0x3e0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: source adresse update value.

DUV

Bits 16-31: destination address update.

LAR [14]

MDMA channel x Link Address register

Offset: 0x3e4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: Link address register.

TBR [14]

MDMA channel x Trigger and Bus selection Register

Offset: 0x3e8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw
SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: Trigger selection.

SBUS

Bit 16: Source BUS select This bit is protected and can be written only if EN is 0..

DBUS

Bit 17: Destination BUS slect This bit is protected and can be written only if EN is 0..

MAR [14]

MDMA channel x Mask address register

Offset: 0x3f0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: Mask address.

MDR [14]

MDMA channel x Mask Data register

Offset: 0x3f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: Mask data.

ISR [15]

MDMA channel x interrupt/status register

Offset: 0x400, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r
BTIF
r
BRTIF
r
CTCIF
r
TEIF
r
Toggle fields

TEIF

Bit 0: Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

CTCIF

Bit 1: Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0..

BRTIF

Bit 2: Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

BTIF

Bit 3: Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register..

TCIF

Bit 4: channel x buffer transfer complete.

CRQA

Bit 16: channel x request active flag.

IFCR [15]

MDMA channel x interrupt flag clear register

Offset: 0x404, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w
CBTIF
w
CBRTIF
w
CCTCIF
w
CTEIF
w
Toggle fields

CTEIF

Bit 0: Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register.

CCTCIF

Bit 1: Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register.

CBRTIF

Bit 2: Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register.

CBTIF

Bit 3: Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register.

CLTCIF

Bit 4: CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register.

ESR [15]

MDMA Channel x error status register

Offset: 0x408, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r
ASE
r
TEMD
r
TELD
r
TED
r
TEA
r
Toggle fields

TEA

Bits 0-6: Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error..

TED

Bit 7: Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error..

TELD

Bit 8: Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

TEMD

Bit 9: Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

ASE

Bit 10: Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

BSE

Bit 11: Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register..

CR [15]

This register is used to control the concerned channel.

Offset: 0x40c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw
HEX
rw
BEX
rw
PL
rw
TCIE
rw
BTIE
rw
BRTIE
rw
CTCIE
rw
TEIE
rw
EN
rw
Toggle fields

EN

Bit 0: channel enable.

TEIE

Bit 1: Transfer error interrupt enable This bit is set and cleared by software..

CTCIE

Bit 2: Channel Transfer Complete interrupt enable This bit is set and cleared by software..

BRTIE

Bit 3: Block Repeat transfer interrupt enable This bit is set and cleared by software..

BTIE

Bit 4: Block Transfer interrupt enable This bit is set and cleared by software..

TCIE

Bit 5: buffer Transfer Complete interrupt enable This bit is set and cleared by software..

PL

Bits 6-7: Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0..

BEX

Bit 12: byte Endianness exchange.

HEX

Bit 13: Half word Endianes exchange.

WEX

Bit 14: Word Endianness exchange.

SWRQ

Bit 16: SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)..

TCR [15]

This register is used to configure the concerned channel.

Offset: 0x410, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw
SWRM
rw
TRGM
rw
PAM
rw
PKE
rw
TLEN
rw
DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw
SBURST
rw
DINCOS
rw
SINCOS
rw
DSIZE
rw
SSIZE
rw
DINC
rw
SINC
rw
Toggle fields

SINC

Bits 0-1: Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)..

DINC

Bits 2-3: Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden..

SSIZE

Bits 4-5: Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS &lt; SSIZE and SINC &#8800; 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)..

DSIZE

Bits 6-7: Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS &lt; DSIZE and DINC &#8800; 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)..

SINCOS

Bits 8-9: source increment offset size.

DINCOS

Bits 10-11: Destination increment offset.

SBURST

Bits 12-14: source burst transfer configuration.

DBURST

Bits 15-17: Destination burst transfer configuration.

TLEN

Bits 18-24: buffer transfer lengh.

PKE

Bit 25: PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0.

PAM

Bits 26-27: Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0.

TRGM

Bits 28-29: Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0..

SWRM

Bit 30: SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0..

BWM

Bit 31: Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable..

BNDTR [15]

MDMA Channel x block number of data register

Offset: 0x414, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw
BRDUM
rw
BRSUM
rw
BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: block number of data to transfer.

BRSUM

Bit 18: Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0..

BRDUM

Bit 19: Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0..

BRC

Bits 20-31: Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0..

SAR [15]

MDMA channel x source address register

Offset: 0x418, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: source adr base.

DAR [15]

MDMA channel x destination address register

Offset: 0x41c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: Destination adr base.

BRUR [15]

MDMA channel x Block Repeat address Update register

Offset: 0x420, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: source adresse update value.

DUV

Bits 16-31: destination address update.

LAR [15]

MDMA channel x Link Address register

Offset: 0x424, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: Link address register.

TBR [15]

MDMA channel x Trigger and Bus selection Register

Offset: 0x428, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw
SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: Trigger selection.

SBUS

Bit 16: Source BUS select This bit is protected and can be written only if EN is 0..

DBUS

Bit 17: Destination BUS slect This bit is protected and can be written only if EN is 0..

MAR [15]

MDMA channel x Mask address register

Offset: 0x430, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: Mask address.

MDR [15]

MDMA channel x Mask Data register

Offset: 0x434, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: Mask data.

OCTOSPI1

0x52005000: OctoSPI

7/98 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x8 DCR1
0xc DCR2
0x10 DCR3
0x14 DCR4
0x20 SR
0x24 FCR
0x40 DLR
0x48 AR
0x50 DR
0x80 PSMKR
0x88 PSMAR
0x90 PIR
0x100 CCR
0x108 TCR
0x110 IR
0x120 ABR
0x130 LPTR
0x140 WPCCR
0x148 WPTCR
0x150 WPIR
0x160 WPABR
0x180 WCCR
0x188 WTCR
0x190 WIR
0x1a0 WABR
0x200 HLCR
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FMODE
rw
PMM
rw
APMS
rw
TOIE
rw
SMIE
rw
FTIE
rw
TCIE
rw
TEIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTHRES
rw
FSEL
rw
DQM
rw
TCEN
rw
DMAEN
rw
ABORT
rw
EN
rw
Toggle fields

EN

Bit 0: Enable.

ABORT

Bit 1: Abort request.

DMAEN

Bit 2: DMA enable.

TCEN

Bit 3: Timeout counter enable.

DQM

Bit 6: Dual-quad mode.

FSEL

Bit 7: FLASH memory selection.

FTHRES

Bits 8-12: IFO threshold level.

TEIE

Bit 16: Transfer error interrupt enable.

TCIE

Bit 17: Transfer complete interrupt enable.

FTIE

Bit 18: FIFO threshold interrupt enable.

SMIE

Bit 19: Status match interrupt enable.

TOIE

Bit 20: TimeOut interrupt enable.

APMS

Bit 22: Automatic poll mode stop.

PMM

Bit 23: Polling match mode.

FMODE

Bits 28-29: Functional mode.

DCR1

device configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MTYP
rw
DEVSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSHT
rw
DLYBYP
rw
FRCK
rw
CKMODE
rw
Toggle fields

CKMODE

Bit 0: Mode 0 / mode 3.

FRCK

Bit 1: Free running clock.

DLYBYP

Bit 3: Delay block bypass.

CSHT

Bits 8-10: Chip-select high time.

DEVSIZE

Bits 16-20: Device size.

MTYP

Bits 24-26: Memory type.

DCR2

device configuration register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRAPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-7: Clock prescaler.

WRAPSIZE

Bits 16-18: Wrap size.

DCR3

device configuration register 3

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSBOUND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAXTRAN
rw
Toggle fields

MAXTRAN

Bits 0-7: Maximum transfer.

CSBOUND

Bits 16-20: CS boundary.

DCR4

DCR4

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REFRESH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REFRESH
rw
Toggle fields

REFRESH

Bits 0-31: Refresh rate.

SR

status register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLEVEL
r
BUSY
r
TOF
r
SMF
r
FTF
r
TCF
r
TEF
r
Toggle fields

TEF

Bit 0: Transfer error flag.

TCF

Bit 1: Transfer complete flag.

FTF

Bit 2: FIFO threshold flag.

SMF

Bit 3: Status match flag.

TOF

Bit 4: Timeout flag.

BUSY

Bit 5: Busy.

FLEVEL

Bits 8-13: FIFO level.

FCR

flag clear register

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTOF
w
CSMF
w
CTCF
w
CTEF
w
Toggle fields

CTEF

Bit 0: Clear transfer error flag.

CTCF

Bit 1: Clear transfer complete flag.

CSMF

Bit 3: Clear status match flag.

CTOF

Bit 4: Clear timeout flag.

DLR

data length register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DL
rw
Toggle fields

DL

Bits 0-31: Data length.

AR

address register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDRESS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRESS
rw
Toggle fields

ADDRESS

Bits 0-31: Adress.

DR

data register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: Data.

PSMKR

polling status mask register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASK
rw
Toggle fields

MASK

Bits 0-31: Status mask.

PSMAR

polling status match register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MATCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MATCH
rw
Toggle fields

MATCH

Bits 0-31: Match.

PIR

OCTOSPI polling interval register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTERVAL
rw
Toggle fields

INTERVAL

Bits 0-15: Polling interval.

CCR

polling interval register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SIOO
rw
DQSE
rw
DDTR
rw
DMODE
rw
ABSIZE
rw
ABDTR
rw
ABMODE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADSIZE
rw
ADDTR
rw
ADMODE
rw
ISIZE
rw
IDTR
rw
IMODE
rw
Toggle fields

IMODE

Bits 0-2: Instruction mode.

IDTR

Bit 3: Instruction double transfer rate.

ISIZE

Bits 4-5: Instruction size.

ADMODE

Bits 8-10: Address mode.

ADDTR

Bit 11: Address double transfer rate.

ADSIZE

Bits 12-13: Address size.

ABMODE

Bits 16-18: Alternate byte mode.

ABDTR

Bit 19: Alternate bytes double transfer rate.

ABSIZE

Bits 20-21: Alternate bytes size.

DMODE

Bits 24-26: Data mode.

DDTR

Bit 27: Alternate bytes double transfer rate.

DQSE

Bit 29: DQS enable.

SIOO

Bit 31: Send instruction only once mode.

TCR

communication configuration register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSHIFT
rw
DHQC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCYC
rw
Toggle fields

DCYC

Bits 0-4: Number of dummy cycles.

DHQC

Bit 28: Delay hold quarter cycle.

SSHIFT

Bit 30: Sample shift.

IR

timing configuration register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INSTRUCTION
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INSTRUCTION
rw
Toggle fields

INSTRUCTION

Bits 0-31: INSTRUCTION.

ABR

instruction register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALTERNATE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALTERNATE
rw
Toggle fields

ALTERNATE

Bits 0-31: Alternate bytes.

LPTR

alternate bytes register

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMEOUT
rw
Toggle fields

TIMEOUT

Bits 0-15: Timeout period.

WPCCR

low-power timeout register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DQSE
rw
DDTR
rw
DMODE
rw
ABSIZE
rw
ABDTR
rw
ABMODE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADSIZE
rw
ADDTR
rw
ADMODE
rw
ISIZE
rw
IDTR
rw
IMODE
rw
Toggle fields

IMODE

Bits 0-2: Instruction mode.

IDTR

Bit 3: Instruction double transfer rate.

ISIZE

Bits 4-5: Instruction size.

ADMODE

Bits 8-10: Address mode.

ADDTR

Bit 11: Address double transfer rate.

ADSIZE

Bits 12-13: Address size.

ABMODE

Bits 16-18: Alternate byte mode.

ABDTR

Bit 19: Alternate bytes double transfer rate.

ABSIZE

Bits 20-21: Alternate bytes size.

DMODE

Bits 24-26: Data mode.

DDTR

Bit 27: alternate bytes double transfer rate.

DQSE

Bit 29: DQS enable.

WPTCR

wrap timing configuration register

Offset: 0x148, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSHIFT
rw
DHQC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCYC
rw
Toggle fields

DCYC

Bits 0-4: Number of dummy cycles.

DHQC

Bit 28: Delay hold quarter cycle.

SSHIFT

Bit 30: Sample shift.

WPIR

wrap instruction register

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INSTRUCTION
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INSTRUCTION
rw
Toggle fields

INSTRUCTION

Bits 0-31: INSTRUCTION.

WPABR

wrap alternate bytes register

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALTERNATE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALTERNATE
rw
Toggle fields

ALTERNATE

Bits 0-31: Alternate bytes.

WCCR

write communication configuration register

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DQSE
rw
DDTR
rw
DMODE
rw
ABSIZE
rw
ABDTR
rw
ABMODE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADSIZE
rw
ADDTR
rw
ADMODE
rw
ISIZE
rw
IDTR
rw
IMODE
rw
Toggle fields

IMODE

Bits 0-1: Instruction mode.

IDTR

Bit 2: Instruction double transfer rate.

ISIZE

Bit 3: Instruction size.

ADMODE

Bits 8-10: Address mode.

ADDTR

Bit 11: Address double transfer rate.

ADSIZE

Bits 12-13: Address size.

ABMODE

Bits 16-18: Alternate-byte mode.

ABDTR

Bit 19: Alternate bytes double transfer rate.

ABSIZE

Bits 20-21: Alternate bytes size.

DMODE

Bits 24-26: Data mode.

DDTR

Bit 27: DDTR.

DQSE

Bit 29: DQSE.

WTCR

write timing configuration register

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCYC
rw
Toggle fields

DCYC

Bits 0-4: DCYC.

WIR

instruction register

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INSTRUCTION
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INSTRUCTION
rw
Toggle fields

INSTRUCTION

Bits 0-31: INSTRUCTION.

WABR

write alternate bytes register

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALTERNATE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALTERNATE
rw
Toggle fields

ALTERNATE

Bits 0-31: Alternate bytes.

HLCR

HyperBusTM latency configuration register

Offset: 0x200, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TRWR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TACC
rw
WZL
rw
LM
rw
Toggle fields

LM

Bit 0: Latency mode.

WZL

Bit 1: Write zero latency.

TACC

Bits 8-15: Access time.

TRWR

Bits 16-23: Read write recovery time.

OCTOSPI2

0x5200a000: OctoSPI

7/98 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x8 DCR1
0xc DCR2
0x10 DCR3
0x14 DCR4
0x20 SR
0x24 FCR
0x40 DLR
0x48 AR
0x50 DR
0x80 PSMKR
0x88 PSMAR
0x90 PIR
0x100 CCR
0x108 TCR
0x110 IR
0x120 ABR
0x130 LPTR
0x140 WPCCR
0x148 WPTCR
0x150 WPIR
0x160 WPABR
0x180 WCCR
0x188 WTCR
0x190 WIR
0x1a0 WABR
0x200 HLCR
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FMODE
rw
PMM
rw
APMS
rw
TOIE
rw
SMIE
rw
FTIE
rw
TCIE
rw
TEIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTHRES
rw
FSEL
rw
DQM
rw
TCEN
rw
DMAEN
rw
ABORT
rw
EN
rw
Toggle fields

EN

Bit 0: Enable.

ABORT

Bit 1: Abort request.

DMAEN

Bit 2: DMA enable.

TCEN

Bit 3: Timeout counter enable.

DQM

Bit 6: Dual-quad mode.

FSEL

Bit 7: FLASH memory selection.

FTHRES

Bits 8-12: IFO threshold level.

TEIE

Bit 16: Transfer error interrupt enable.

TCIE

Bit 17: Transfer complete interrupt enable.

FTIE

Bit 18: FIFO threshold interrupt enable.

SMIE

Bit 19: Status match interrupt enable.

TOIE

Bit 20: TimeOut interrupt enable.

APMS

Bit 22: Automatic poll mode stop.

PMM

Bit 23: Polling match mode.

FMODE

Bits 28-29: Functional mode.

DCR1

device configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MTYP
rw
DEVSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSHT
rw
DLYBYP
rw
FRCK
rw
CKMODE
rw
Toggle fields

CKMODE

Bit 0: Mode 0 / mode 3.

FRCK

Bit 1: Free running clock.

DLYBYP

Bit 3: Delay block bypass.

CSHT

Bits 8-10: Chip-select high time.

DEVSIZE

Bits 16-20: Device size.

MTYP

Bits 24-26: Memory type.

DCR2

device configuration register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRAPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-7: Clock prescaler.

WRAPSIZE

Bits 16-18: Wrap size.

DCR3

device configuration register 3

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSBOUND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAXTRAN
rw
Toggle fields

MAXTRAN

Bits 0-7: Maximum transfer.

CSBOUND

Bits 16-20: CS boundary.

DCR4

DCR4

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REFRESH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REFRESH
rw
Toggle fields

REFRESH

Bits 0-31: Refresh rate.

SR

status register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLEVEL
r
BUSY
r
TOF
r
SMF
r
FTF
r
TCF
r
TEF
r
Toggle fields

TEF

Bit 0: Transfer error flag.

TCF

Bit 1: Transfer complete flag.

FTF

Bit 2: FIFO threshold flag.

SMF

Bit 3: Status match flag.

TOF

Bit 4: Timeout flag.

BUSY

Bit 5: Busy.

FLEVEL

Bits 8-13: FIFO level.

FCR

flag clear register

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTOF
w
CSMF
w
CTCF
w
CTEF
w
Toggle fields

CTEF

Bit 0: Clear transfer error flag.

CTCF

Bit 1: Clear transfer complete flag.

CSMF

Bit 3: Clear status match flag.

CTOF

Bit 4: Clear timeout flag.

DLR

data length register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DL
rw
Toggle fields

DL

Bits 0-31: Data length.

AR

address register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDRESS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRESS
rw
Toggle fields

ADDRESS

Bits 0-31: Adress.

DR

data register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: Data.

PSMKR

polling status mask register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASK
rw
Toggle fields

MASK

Bits 0-31: Status mask.

PSMAR

polling status match register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MATCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MATCH
rw
Toggle fields

MATCH

Bits 0-31: Match.

PIR

OCTOSPI polling interval register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTERVAL
rw
Toggle fields

INTERVAL

Bits 0-15: Polling interval.

CCR

polling interval register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SIOO
rw
DQSE
rw
DDTR
rw
DMODE
rw
ABSIZE
rw
ABDTR
rw
ABMODE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADSIZE
rw
ADDTR
rw
ADMODE
rw
ISIZE
rw
IDTR
rw
IMODE
rw
Toggle fields

IMODE

Bits 0-2: Instruction mode.

IDTR

Bit 3: Instruction double transfer rate.

ISIZE

Bits 4-5: Instruction size.

ADMODE

Bits 8-10: Address mode.

ADDTR

Bit 11: Address double transfer rate.

ADSIZE

Bits 12-13: Address size.

ABMODE

Bits 16-18: Alternate byte mode.

ABDTR

Bit 19: Alternate bytes double transfer rate.

ABSIZE

Bits 20-21: Alternate bytes size.

DMODE

Bits 24-26: Data mode.

DDTR

Bit 27: Alternate bytes double transfer rate.

DQSE

Bit 29: DQS enable.

SIOO

Bit 31: Send instruction only once mode.

TCR

communication configuration register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSHIFT
rw
DHQC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCYC
rw
Toggle fields

DCYC

Bits 0-4: Number of dummy cycles.

DHQC

Bit 28: Delay hold quarter cycle.

SSHIFT

Bit 30: Sample shift.

IR

timing configuration register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INSTRUCTION
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INSTRUCTION
rw
Toggle fields

INSTRUCTION

Bits 0-31: INSTRUCTION.

ABR

instruction register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALTERNATE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALTERNATE
rw
Toggle fields

ALTERNATE

Bits 0-31: Alternate bytes.

LPTR

alternate bytes register

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMEOUT
rw
Toggle fields

TIMEOUT

Bits 0-15: Timeout period.

WPCCR

low-power timeout register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DQSE
rw
DDTR
rw
DMODE
rw
ABSIZE
rw
ABDTR
rw
ABMODE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADSIZE
rw
ADDTR
rw
ADMODE
rw
ISIZE
rw
IDTR
rw
IMODE
rw
Toggle fields

IMODE

Bits 0-2: Instruction mode.

IDTR

Bit 3: Instruction double transfer rate.

ISIZE

Bits 4-5: Instruction size.

ADMODE

Bits 8-10: Address mode.

ADDTR

Bit 11: Address double transfer rate.

ADSIZE

Bits 12-13: Address size.

ABMODE

Bits 16-18: Alternate byte mode.

ABDTR

Bit 19: Alternate bytes double transfer rate.

ABSIZE

Bits 20-21: Alternate bytes size.

DMODE

Bits 24-26: Data mode.

DDTR

Bit 27: alternate bytes double transfer rate.

DQSE

Bit 29: DQS enable.

WPTCR

wrap timing configuration register

Offset: 0x148, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSHIFT
rw
DHQC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCYC
rw
Toggle fields

DCYC

Bits 0-4: Number of dummy cycles.

DHQC

Bit 28: Delay hold quarter cycle.

SSHIFT

Bit 30: Sample shift.

WPIR

wrap instruction register

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INSTRUCTION
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INSTRUCTION
rw
Toggle fields

INSTRUCTION

Bits 0-31: INSTRUCTION.

WPABR

wrap alternate bytes register

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALTERNATE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALTERNATE
rw
Toggle fields

ALTERNATE

Bits 0-31: Alternate bytes.

WCCR

write communication configuration register

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DQSE
rw
DDTR
rw
DMODE
rw
ABSIZE
rw
ABDTR
rw
ABMODE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADSIZE
rw
ADDTR
rw
ADMODE
rw
ISIZE
rw
IDTR
rw
IMODE
rw
Toggle fields

IMODE

Bits 0-1: Instruction mode.

IDTR

Bit 2: Instruction double transfer rate.

ISIZE

Bit 3: Instruction size.

ADMODE

Bits 8-10: Address mode.

ADDTR

Bit 11: Address double transfer rate.

ADSIZE

Bits 12-13: Address size.

ABMODE

Bits 16-18: Alternate-byte mode.

ABDTR

Bit 19: Alternate bytes double transfer rate.

ABSIZE

Bits 20-21: Alternate bytes size.

DMODE

Bits 24-26: Data mode.

DDTR

Bit 27: DDTR.

DQSE

Bit 29: DQSE.

WTCR

write timing configuration register

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCYC
rw
Toggle fields

DCYC

Bits 0-4: DCYC.

WIR

instruction register

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INSTRUCTION
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INSTRUCTION
rw
Toggle fields

INSTRUCTION

Bits 0-31: INSTRUCTION.

WABR

write alternate bytes register

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALTERNATE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALTERNATE
rw
Toggle fields

ALTERNATE

Bits 0-31: Alternate bytes.

HLCR

HyperBusTM latency configuration register

Offset: 0x200, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TRWR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TACC
rw
WZL
rw
LM
rw
Toggle fields

LM

Bit 0: Latency mode.

WZL

Bit 1: Write zero latency.

TACC

Bits 8-15: Access time.

TRWR

Bits 16-23: Read write recovery time.

OctoSPII_O_Manager

0x5200b400: OctoSPI IO Manager

0/22 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 P1CR
0x8 P2CR
Toggle registers

CR

OctoSPI IO Manager Control Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REQ2ACK_TIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUXEN
rw
Toggle fields

MUXEN

Bit 0: Multiplexed mode Enable.

REQ2ACK_TIME

Bits 16-23: REQ to ACK Time.

P1CR

OctoSPI IO Manager Port 1 configuration register

Offset: 0x4, size: 32, reset: 0x03010111, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IOHSRC
rw
IOHEN
rw
IOLSRC
rw
IOLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NCSSRC
rw
NCSEN
rw
DQSSRC
rw
DQSEN
rw
CLKSRC
rw
CLKEN
rw
Toggle fields

CLKEN

Bit 0: CLK/CLKn Enable for Port n.

CLKSRC

Bit 1: CLK/CLKn Source for Port n.

DQSEN

Bit 4: DQSEN.

DQSSRC

Bit 5: DQSSRC.

NCSEN

Bit 8: NCSEN.

NCSSRC

Bit 9: NCSSRC.

IOLEN

Bit 16: IOLEN.

IOLSRC

Bits 17-18: IOLSRC.

IOHEN

Bit 24: IOHEN.

IOHSRC

Bits 25-26: IOHSRC.

P2CR

OctoSPI IO Manager Port 2 configuration register

Offset: 0x8, size: 32, reset: 0x07050333, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IOHSRC
rw
IOHEN
rw
IOLSRC
rw
IOLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NCSSRC
rw
NCSEN
rw
DQSSRC
rw
DQSEN
rw
CLKSRC
rw
CLKEN
rw
Toggle fields

CLKEN

Bit 0: CLKEN.

CLKSRC

Bit 1: CLKSRC.

DQSEN

Bit 4: DQSEN.

DQSSRC

Bit 5: DQSSRC.

NCSEN

Bit 8: NCSEN.

NCSSRC

Bit 9: NCSSRC.

IOLEN

Bit 16: IOLEN.

IOLSRC

Bits 17-18: IOLSRC.

IOHEN

Bit 24: IOHEN.

IOHSRC

Bits 25-26: IOHSRC.

OPAMP

0x40009000: Operational amplifiers

0/29 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 OPAMP1_CSR
0x4 OPAMP1_OTR
0x8 OPAMP1_HSOTR
0x10 OPAMP2_CSR
0x14 OPAMP2_OTR
0x18 OPAMP2_HSOTR
Toggle registers

OPAMP1_CSR

OPAMP1 control/status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CALOUT
rw
TSTREF
rw
USERTRIM
rw
PGA_GAIN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PGA_GAIN
rw
CALSEL
rw
CALON
rw
OPAHSM
rw
VM_SEL
rw
VP_SEL
rw
FORCE_VP
rw
OPAEN
rw
Toggle fields

OPAEN

Bit 0: Operational amplifier Enable.

FORCE_VP

Bit 1: Force internal reference on VP (reserved for test.

VP_SEL

Bits 2-3: Operational amplifier PGA mode.

VM_SEL

Bits 5-6: Inverting input selection.

OPAHSM

Bit 8: Operational amplifier high-speed mode.

CALON

Bit 11: Calibration mode enabled.

CALSEL

Bits 12-13: Calibration selection.

PGA_GAIN

Bits 14-17: allows to switch from AOP offset trimmed values to AOP offset.

USERTRIM

Bit 18: User trimming enable.

TSTREF

Bit 29: OPAMP calibration reference voltage output control (reserved for test).

CALOUT

Bit 30: Operational amplifier calibration output.

OPAMP1_OTR

OPAMP1 offset trimming register in normal mode

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIMOFFSETP
rw
TRIMOFFSETN
rw
Toggle fields

TRIMOFFSETN

Bits 0-4: Trim for NMOS differential pairs.

TRIMOFFSETP

Bits 8-12: Trim for PMOS differential pairs.

OPAMP1_HSOTR

OPAMP1 offset trimming register in low-power mode

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIMLPOFFSETP
rw
TRIMLPOFFSETN
rw
Toggle fields

TRIMLPOFFSETN

Bits 0-4: Trim for NMOS differential pairs.

TRIMLPOFFSETP

Bits 8-12: Trim for PMOS differential pairs.

OPAMP2_CSR

OPAMP2 control/status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CALOUT
rw
TSTREF
rw
USERTRIM
rw
PGA_GAIN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PGA_GAIN
rw
CALSEL
rw
CALON
rw
OPAHSM
rw
VM_SEL
rw
FORCE_VP
rw
OPAEN
rw
Toggle fields

OPAEN

Bit 0: Operational amplifier Enable.

FORCE_VP

Bit 1: Force internal reference on VP (reserved for test).

VM_SEL

Bits 5-6: Inverting input selection.

OPAHSM

Bit 8: Operational amplifier high-speed mode.

CALON

Bit 11: Calibration mode enabled.

CALSEL

Bits 12-13: Calibration selection.

PGA_GAIN

Bits 14-17: Operational amplifier Programmable amplifier gain value.

USERTRIM

Bit 18: User trimming enable.

TSTREF

Bit 29: OPAMP calibration reference voltage output control (reserved for test).

CALOUT

Bit 30: Operational amplifier calibration output.

OPAMP2_OTR

OPAMP2 offset trimming register in normal mode

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIMOFFSETP
rw
TRIMOFFSETN
rw
Toggle fields

TRIMOFFSETN

Bits 0-4: Trim for NMOS differential pairs.

TRIMOFFSETP

Bits 8-12: Trim for PMOS differential pairs.

OPAMP2_HSOTR

OPAMP2 offset trimming register in low-power mode

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIMLPOFFSETP
rw
TRIMLPOFFSETN
rw
Toggle fields

TRIMLPOFFSETN

Bits 0-4: Trim for NMOS differential pairs.

TRIMLPOFFSETP

Bits 8-12: Trim for PMOS differential pairs.

OTFDEC1

0x5200b800: On-The-Fly Decryption engine

10/66 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x20 R1CFGR
0x24 R1STARTADDR
0x28 R1ENDADDR
0x2c R1NONCER0
0x30 R1NONCER1
0x34 R1KEYR0
0x38 R1KEYR1
0x3c R1KEYR2
0x40 R1KEYR3
0x50 R2CFGR
0x54 R2STARTADDR
0x58 R2ENDADDR
0x5c R2NONCER0
0x60 R2NONCER1
0x64 R2KEYR0
0x68 R2KEYR1
0x6c R2KEYR2
0x70 R2KEYR3
0x80 R3CFGR
0x84 R3STARTADDR
0x88 R3ENDADDR
0x8c R3NONCER0
0x8c R4ENDADDR
0x90 R3NONCER1
0x94 R3KEYR0
0x98 R3KEYR1
0x9c R3KEYR2
0xa0 R3KEYR3
0xb0 R4CFGR
0xb4 R4STARTADDR
0xbc R4NONCER0
0xc0 R4NONCER1
0xc4 R4KEYR0
0xc8 R4KEYR1
0xcc R4KEYR2
0xd0 R4KEYR3
0x300 ISR
0x304 ICR
0x308 IER
Toggle registers

CR

OTFDEC control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENC
rw
Toggle fields

ENC

Bit 0: Encryption mode bit.

R1CFGR

OTFDEC region x configuration register

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_VERSION
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEYCRC
r
MODE
rw
KEYLOCK
rw
CONFIGLOCK
rw
REG_EN
rw
Toggle fields

REG_EN

Bit 0: region on-the-fly decryption enable.

CONFIGLOCK

Bit 1: region config lock.

KEYLOCK

Bit 2: region key lock.

MODE

Bits 4-5: operating mode.

KEYCRC

Bits 8-15: region key 8-bit CRC.

REGx_VERSION

Bits 16-31: region firmware version.

R1STARTADDR

OTFDEC region x start address register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_START_ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_START_ADDR
rw
Toggle fields

REGx_START_ADDR

Bits 0-31: Region AXI start address.

R1ENDADDR

OTFDEC region x end address register

Offset: 0x28, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_END_ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_END_ADDR
rw
Toggle fields

REGx_END_ADDR

Bits 0-31: Region AXI end address.

R1NONCER0

OTFDEC region x nonce register 0

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_NONCE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_NONCE
rw
Toggle fields

REGx_NONCE

Bits 0-31: REGx_NONCE.

R1NONCER1

OTFDEC region x nonce register 1

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_NONCE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_NONCE
rw
Toggle fields

REGx_NONCE

Bits 0-31: Region nonce.

R1KEYR0

OTFDEC region x key register 0

Offset: 0x34, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R1KEYR1

OTFDEC region x key register 1

Offset: 0x38, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R1KEYR2

OTFDEC region x key register 2

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R1KEYR3

OTFDEC region x key register 3

Offset: 0x40, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R2CFGR

OTFDEC region x configuration register

Offset: 0x50, size: 32, reset: 0x00000000, access: Unspecified

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_VERSION
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEYCRC
r
MODE
rw
KEYLOCK
rw
CONFIGLOCK
rw
REG_EN
rw
Toggle fields

REG_EN

Bit 0: region on-the-fly decryption enable.

CONFIGLOCK

Bit 1: region config lock.

KEYLOCK

Bit 2: region key lock.

MODE

Bits 4-5: operating mode.

KEYCRC

Bits 8-15: region key 8-bit CRC.

REGx_VERSION

Bits 16-31: region firmware version.

R2STARTADDR

OTFDEC region x start address register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_START_ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_START_ADDR
rw
Toggle fields

REGx_START_ADDR

Bits 0-31: Region AXI start address.

R2ENDADDR

OTFDEC region x end address register

Offset: 0x58, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_END_ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_END_ADDR
rw
Toggle fields

REGx_END_ADDR

Bits 0-31: Region AXI end address.

R2NONCER0

OTFDEC region x nonce register 0

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_NONCE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_NONCE
rw
Toggle fields

REGx_NONCE

Bits 0-31: REGx_NONCE.

R2NONCER1

OTFDEC region x nonce register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_NONCE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_NONCE
rw
Toggle fields

REGx_NONCE

Bits 0-31: Region nonce, bits [63:32]REGx_NONCE[63:32].

R2KEYR0

OTFDEC region x key register 0

Offset: 0x64, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R2KEYR1

OTFDEC region x key register 1

Offset: 0x68, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R2KEYR2

OTFDEC region x key register 2

Offset: 0x6c, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY_
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY_
w
Toggle fields

REGx_KEY_

Bits 0-31: REGx_KEY.

R2KEYR3

OTFDEC region x key register 3

Offset: 0x70, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R3CFGR

OTFDEC region x configuration register

Offset: 0x80, size: 32, reset: 0x00000000, access: Unspecified

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_VERSION
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEYCRC
r
MODE
rw
KEYLOCK
rw
CONFIGLOCK
rw
REG_EN
rw
Toggle fields

REG_EN

Bit 0: region on-the-fly decryption enable.

CONFIGLOCK

Bit 1: region config lock.

KEYLOCK

Bit 2: region key lock.

MODE

Bits 4-5: operating mode.

KEYCRC

Bits 8-15: region key 8-bit CRC.

REGx_VERSION

Bits 16-31: region firmware version.

R3STARTADDR

OTFDEC region x start address register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_START_ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_START_ADDR
rw
Toggle fields

REGx_START_ADDR

Bits 0-31: Region AXI start address.

R3ENDADDR

OTFDEC region x end address register

Offset: 0x88, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_END_ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_END_ADDR
rw
Toggle fields

REGx_END_ADDR

Bits 0-31: Region AXI end address.

R3NONCER0

OTFDEC region x nonce register 0

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_NONCE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_NONCE
rw
Toggle fields

REGx_NONCE

Bits 0-31: REGx_NONCE.

R4ENDADDR

OTFDEC region x end address register

Offset: 0x8c, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_END_ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_END_ADDR
rw
Toggle fields

REGx_END_ADDR

Bits 0-31: Region AXI end address.

R3NONCER1

OTFDEC region x nonce register 1

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_NONCE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_NONCE
rw
Toggle fields

REGx_NONCE

Bits 0-31: REGx_NONCE.

R3KEYR0

OTFDEC region x key register 0

Offset: 0x94, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R3KEYR1

OTFDEC region x key register 1

Offset: 0x98, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R3KEYR2

OTFDEC region x key register 2

Offset: 0x9c, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R3KEYR3

OTFDEC region x key register 3

Offset: 0xa0, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R4CFGR

OTFDEC region x configuration register

Offset: 0xb0, size: 32, reset: 0x00000000, access: Unspecified

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_VERSION
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEYCRC
r
MODE
rw
KEYLOCK
rw
CONFIGLOCK
rw
REG_EN
rw
Toggle fields

REG_EN

Bit 0: region on-the-fly decryption enable.

CONFIGLOCK

Bit 1: region config lock.

KEYLOCK

Bit 2: region key lock.

MODE

Bits 4-5: operating mode.

KEYCRC

Bits 8-15: region key 8-bit CRC.

REGx_VERSION

Bits 16-31: region firmware version.

R4STARTADDR

OTFDEC region x start address register

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_START_ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_START_ADDR
rw
Toggle fields

REGx_START_ADDR

Bits 0-31: Region AXI start address.

R4NONCER0

OTFDEC region x nonce register 0

Offset: 0xbc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_NONCE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_NONCE
rw
Toggle fields

REGx_NONCE

Bits 0-31: REGx_NONCE.

R4NONCER1

OTFDEC region x nonce register 1

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_NONCE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_NONCE
rw
Toggle fields

REGx_NONCE

Bits 0-31: REGx_NONCE.

R4KEYR0

OTFDEC region x key register 0

Offset: 0xc4, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R4KEYR1

OTFDEC region x key register 1

Offset: 0xc8, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R4KEYR2

OTFDEC region x key register 2

Offset: 0xcc, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R4KEYR3

OTFDEC region x key register 3

Offset: 0xd0, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

ISR

OTFDEC interrupt status register

Offset: 0x300, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEIF
r
XONEIF
r
SEIF
r
Toggle fields

SEIF

Bit 0: Security Error Interrupt Flag status.

XONEIF

Bit 1: Execute-only execute-Never Error Interrupt Flag status.

KEIF

Bit 2: Key Error Interrupt Flag status.

ICR

OTFDEC interrupt clear register

Offset: 0x304, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEIF
r
XONEIF
r
SEIF
r
Toggle fields

SEIF

Bit 0: SEIF.

XONEIF

Bit 1: Execute-only execute-Never Error Interrupt Flag clear.

KEIF

Bit 2: KEIF.

IER

OTFDEC interrupt enable register

Offset: 0x308, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEIE
rw
XONEIE
rw
SEIE
rw
Toggle fields

SEIE

Bit 0: Security Error Interrupt Enable.

XONEIE

Bit 1: XONEIE.

KEIE

Bit 2: KEIE.

OTFDEC2

0x5200bc00: On-The-Fly Decryption engine

10/66 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x20 R1CFGR
0x24 R1STARTADDR
0x28 R1ENDADDR
0x2c R1NONCER0
0x30 R1NONCER1
0x34 R1KEYR0
0x38 R1KEYR1
0x3c R1KEYR2
0x40 R1KEYR3
0x50 R2CFGR
0x54 R2STARTADDR
0x58 R2ENDADDR
0x5c R2NONCER0
0x60 R2NONCER1
0x64 R2KEYR0
0x68 R2KEYR1
0x6c R2KEYR2
0x70 R2KEYR3
0x80 R3CFGR
0x84 R3STARTADDR
0x88 R3ENDADDR
0x8c R3NONCER0
0x8c R4ENDADDR
0x90 R3NONCER1
0x94 R3KEYR0
0x98 R3KEYR1
0x9c R3KEYR2
0xa0 R3KEYR3
0xb0 R4CFGR
0xb4 R4STARTADDR
0xbc R4NONCER0
0xc0 R4NONCER1
0xc4 R4KEYR0
0xc8 R4KEYR1
0xcc R4KEYR2
0xd0 R4KEYR3
0x300 ISR
0x304 ICR
0x308 IER
Toggle registers

CR

OTFDEC control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENC
rw
Toggle fields

ENC

Bit 0: Encryption mode bit.

R1CFGR

OTFDEC region x configuration register

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_VERSION
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEYCRC
r
MODE
rw
KEYLOCK
rw
CONFIGLOCK
rw
REG_EN
rw
Toggle fields

REG_EN

Bit 0: region on-the-fly decryption enable.

CONFIGLOCK

Bit 1: region config lock.

KEYLOCK

Bit 2: region key lock.

MODE

Bits 4-5: operating mode.

KEYCRC

Bits 8-15: region key 8-bit CRC.

REGx_VERSION

Bits 16-31: region firmware version.

R1STARTADDR

OTFDEC region x start address register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_START_ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_START_ADDR
rw
Toggle fields

REGx_START_ADDR

Bits 0-31: Region AXI start address.

R1ENDADDR

OTFDEC region x end address register

Offset: 0x28, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_END_ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_END_ADDR
rw
Toggle fields

REGx_END_ADDR

Bits 0-31: Region AXI end address.

R1NONCER0

OTFDEC region x nonce register 0

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_NONCE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_NONCE
rw
Toggle fields

REGx_NONCE

Bits 0-31: REGx_NONCE.

R1NONCER1

OTFDEC region x nonce register 1

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_NONCE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_NONCE
rw
Toggle fields

REGx_NONCE

Bits 0-31: Region nonce.

R1KEYR0

OTFDEC region x key register 0

Offset: 0x34, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R1KEYR1

OTFDEC region x key register 1

Offset: 0x38, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R1KEYR2

OTFDEC region x key register 2

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R1KEYR3

OTFDEC region x key register 3

Offset: 0x40, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R2CFGR

OTFDEC region x configuration register

Offset: 0x50, size: 32, reset: 0x00000000, access: Unspecified

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_VERSION
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEYCRC
r
MODE
rw
KEYLOCK
rw
CONFIGLOCK
rw
REG_EN
rw
Toggle fields

REG_EN

Bit 0: region on-the-fly decryption enable.

CONFIGLOCK

Bit 1: region config lock.

KEYLOCK

Bit 2: region key lock.

MODE

Bits 4-5: operating mode.

KEYCRC

Bits 8-15: region key 8-bit CRC.

REGx_VERSION

Bits 16-31: region firmware version.

R2STARTADDR

OTFDEC region x start address register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_START_ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_START_ADDR
rw
Toggle fields

REGx_START_ADDR

Bits 0-31: Region AXI start address.

R2ENDADDR

OTFDEC region x end address register

Offset: 0x58, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_END_ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_END_ADDR
rw
Toggle fields

REGx_END_ADDR

Bits 0-31: Region AXI end address.

R2NONCER0

OTFDEC region x nonce register 0

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_NONCE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_NONCE
rw
Toggle fields

REGx_NONCE

Bits 0-31: REGx_NONCE.

R2NONCER1

OTFDEC region x nonce register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_NONCE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_NONCE
rw
Toggle fields

REGx_NONCE

Bits 0-31: Region nonce, bits [63:32]REGx_NONCE[63:32].

R2KEYR0

OTFDEC region x key register 0

Offset: 0x64, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R2KEYR1

OTFDEC region x key register 1

Offset: 0x68, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R2KEYR2

OTFDEC region x key register 2

Offset: 0x6c, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY_
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY_
w
Toggle fields

REGx_KEY_

Bits 0-31: REGx_KEY.

R2KEYR3

OTFDEC region x key register 3

Offset: 0x70, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R3CFGR

OTFDEC region x configuration register

Offset: 0x80, size: 32, reset: 0x00000000, access: Unspecified

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_VERSION
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEYCRC
r
MODE
rw
KEYLOCK
rw
CONFIGLOCK
rw
REG_EN
rw
Toggle fields

REG_EN

Bit 0: region on-the-fly decryption enable.

CONFIGLOCK

Bit 1: region config lock.

KEYLOCK

Bit 2: region key lock.

MODE

Bits 4-5: operating mode.

KEYCRC

Bits 8-15: region key 8-bit CRC.

REGx_VERSION

Bits 16-31: region firmware version.

R3STARTADDR

OTFDEC region x start address register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_START_ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_START_ADDR
rw
Toggle fields

REGx_START_ADDR

Bits 0-31: Region AXI start address.

R3ENDADDR

OTFDEC region x end address register

Offset: 0x88, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_END_ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_END_ADDR
rw
Toggle fields

REGx_END_ADDR

Bits 0-31: Region AXI end address.

R3NONCER0

OTFDEC region x nonce register 0

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_NONCE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_NONCE
rw
Toggle fields

REGx_NONCE

Bits 0-31: REGx_NONCE.

R4ENDADDR

OTFDEC region x end address register

Offset: 0x8c, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_END_ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_END_ADDR
rw
Toggle fields

REGx_END_ADDR

Bits 0-31: Region AXI end address.

R3NONCER1

OTFDEC region x nonce register 1

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_NONCE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_NONCE
rw
Toggle fields

REGx_NONCE

Bits 0-31: REGx_NONCE.

R3KEYR0

OTFDEC region x key register 0

Offset: 0x94, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R3KEYR1

OTFDEC region x key register 1

Offset: 0x98, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R3KEYR2

OTFDEC region x key register 2

Offset: 0x9c, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R3KEYR3

OTFDEC region x key register 3

Offset: 0xa0, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R4CFGR

OTFDEC region x configuration register

Offset: 0xb0, size: 32, reset: 0x00000000, access: Unspecified

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_VERSION
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEYCRC
r
MODE
rw
KEYLOCK
rw
CONFIGLOCK
rw
REG_EN
rw
Toggle fields

REG_EN

Bit 0: region on-the-fly decryption enable.

CONFIGLOCK

Bit 1: region config lock.

KEYLOCK

Bit 2: region key lock.

MODE

Bits 4-5: operating mode.

KEYCRC

Bits 8-15: region key 8-bit CRC.

REGx_VERSION

Bits 16-31: region firmware version.

R4STARTADDR

OTFDEC region x start address register

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_START_ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_START_ADDR
rw
Toggle fields

REGx_START_ADDR

Bits 0-31: Region AXI start address.

R4NONCER0

OTFDEC region x nonce register 0

Offset: 0xbc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_NONCE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_NONCE
rw
Toggle fields

REGx_NONCE

Bits 0-31: REGx_NONCE.

R4NONCER1

OTFDEC region x nonce register 1

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_NONCE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_NONCE
rw
Toggle fields

REGx_NONCE

Bits 0-31: REGx_NONCE.

R4KEYR0

OTFDEC region x key register 0

Offset: 0xc4, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R4KEYR1

OTFDEC region x key register 1

Offset: 0xc8, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R4KEYR2

OTFDEC region x key register 2

Offset: 0xcc, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R4KEYR3

OTFDEC region x key register 3

Offset: 0xd0, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

ISR

OTFDEC interrupt status register

Offset: 0x300, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEIF
r
XONEIF
r
SEIF
r
Toggle fields

SEIF

Bit 0: Security Error Interrupt Flag status.

XONEIF

Bit 1: Execute-only execute-Never Error Interrupt Flag status.

KEIF

Bit 2: Key Error Interrupt Flag status.

ICR

OTFDEC interrupt clear register

Offset: 0x304, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEIF
r
XONEIF
r
SEIF
r
Toggle fields

SEIF

Bit 0: SEIF.

XONEIF

Bit 1: Execute-only execute-Never Error Interrupt Flag clear.

KEIF

Bit 2: KEIF.

IER

OTFDEC interrupt enable register

Offset: 0x308, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEIE
rw
XONEIE
rw
SEIE
rw
Toggle fields

SEIE

Bit 0: Security Error Interrupt Enable.

XONEIE

Bit 1: XONEIE.

KEIE

Bit 2: KEIE.

OTG1_HS_DEVICE

0x40040800: USB 1 on the go high speed

73/575 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 DCFG
0x4 DCTL
0x8 DSTS
0x10 DIEPMSK
0x14 DOEPMSK
0x18 DAINT
0x1c DAINTMSK
0x28 DVBUSDIS
0x2c DVBUSPULSE
0x30 DTHRCTL
0x34 DIEPEMPMSK
0x38 DEACHINT
0x3c DEACHINTMSK
0x44 DIEPEACHMSK1
0x84 DOEPEACHMSK1
0x100 CTL [0]
0x108 INT [0]
0x110 TSIZ [0]
0x114 DMA [0]
0x118 TXFSTS [0]
0x120 CTL [1]
0x128 INT [1]
0x130 TSIZ [1]
0x134 DMA [1]
0x138 TXFSTS [1]
0x140 CTL [2]
0x148 INT [2]
0x150 TSIZ [2]
0x154 DMA [2]
0x158 TXFSTS [2]
0x160 CTL [3]
0x168 INT [3]
0x170 TSIZ [3]
0x174 DMA [3]
0x178 TXFSTS [3]
0x180 CTL [4]
0x188 INT [4]
0x190 TSIZ [4]
0x194 DMA [4]
0x198 TXFSTS [4]
0x1a0 CTL [5]
0x1a8 INT [5]
0x1b0 TSIZ [5]
0x1b4 DMA [5]
0x1b8 TXFSTS [5]
0x1c0 CTL [6]
0x1c8 INT [6]
0x1d0 TSIZ [6]
0x1d4 DMA [6]
0x1d8 TXFSTS [6]
0x1e0 CTL [7]
0x1e8 INT [7]
0x1f0 TSIZ [7]
0x1f4 DMA [7]
0x1f8 TXFSTS [7]
0x200 CTL [8]
0x208 INT [8]
0x210 TSIZ [8]
0x214 DMA [8]
0x218 TXFSTS [8]
0x300 CTL [0]
0x308 INT [0]
0x310 TSIZ [0]
0x314 DMA [0]
0x320 CTL [1]
0x328 INT [1]
0x330 TSIZ [1]
0x334 DMA [1]
0x340 CTL [2]
0x348 INT [2]
0x350 TSIZ [2]
0x354 DMA [2]
0x360 CTL [3]
0x368 INT [3]
0x370 TSIZ [3]
0x374 DMA [3]
0x380 CTL [4]
0x388 INT [4]
0x390 TSIZ [4]
0x394 DMA [4]
0x3a0 CTL [5]
0x3a8 INT [5]
0x3b0 TSIZ [5]
0x3b4 DMA [5]
0x3c0 CTL [6]
0x3c8 INT [6]
0x3d0 TSIZ [6]
0x3d4 DMA [6]
0x3e0 CTL [7]
0x3e8 INT [7]
0x3f0 TSIZ [7]
0x3f4 DMA [7]
0x400 CTL [8]
0x408 INT [8]
0x410 TSIZ [8]
0x414 DMA [8]
Toggle registers

DCFG

OTG_HS device configuration register

Offset: 0x0, size: 32, reset: 0x02200000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PERSCHIVL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PFIVL
rw
DAD
rw
NZLSOHSK
rw
DSPD
rw
Toggle fields

DSPD

Bits 0-1: Device speed.

NZLSOHSK

Bit 2: Nonzero-length status OUT handshake.

DAD

Bits 4-10: Device address.

PFIVL

Bits 11-12: Periodic (micro)frame interval.

PERSCHIVL

Bits 24-25: Periodic scheduling interval.

DCTL

OTG_HS device control register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

2/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POPRGDNE
rw
CGONAK
w
SGONAK
w
CGINAK
w
SGINAK
w
TCTL
rw
GONSTS
r
GINSTS
r
SDIS
rw
RWUSIG
rw
Toggle fields

RWUSIG

Bit 0: Remote wakeup signaling.

SDIS

Bit 1: Soft disconnect.

GINSTS

Bit 2: Global IN NAK status.

GONSTS

Bit 3: Global OUT NAK status.

TCTL

Bits 4-6: Test control.

SGINAK

Bit 7: Set global IN NAK.

CGINAK

Bit 8: Clear global IN NAK.

SGONAK

Bit 9: Set global OUT NAK.

CGONAK

Bit 10: Clear global OUT NAK.

POPRGDNE

Bit 11: Power-on programming done.

DSTS

OTG_HS device status register

Offset: 0x8, size: 32, reset: 0x00000010, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FNSOF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FNSOF
r
EERR
r
ENUMSPD
r
SUSPSTS
r
Toggle fields

SUSPSTS

Bit 0: Suspend status.

ENUMSPD

Bits 1-2: Enumerated speed.

EERR

Bit 3: Erratic error.

FNSOF

Bits 8-21: Frame number of the received SOF.

DIEPMSK

OTG_HS device IN endpoint common interrupt mask register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIM
rw
TXFURM
rw
INEPNEM
rw
INEPNMM
rw
ITTXFEMSK
rw
TOM
rw
EPDM
rw
XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed interrupt mask.

EPDM

Bit 1: Endpoint disabled interrupt mask.

TOM

Bit 3: Timeout condition mask (nonisochronous endpoints).

ITTXFEMSK

Bit 4: IN token received when TxFIFO empty mask.

INEPNMM

Bit 5: IN token received with EP mismatch mask.

INEPNEM

Bit 6: IN endpoint NAK effective mask.

TXFURM

Bit 8: FIFO underrun mask.

BIM

Bit 9: BNA interrupt mask.

DOEPMSK

OTG_HS device OUT endpoint common interrupt mask register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOIM
rw
OPEM
rw
B2BSTUP
rw
OTEPDM
rw
STUPM
rw
EPDM
rw
XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed interrupt mask.

EPDM

Bit 1: Endpoint disabled interrupt mask.

STUPM

Bit 3: SETUP phase done mask.

OTEPDM

Bit 4: OUT token received when endpoint disabled mask.

B2BSTUP

Bit 6: Back-to-back SETUP packets received mask.

OPEM

Bit 8: OUT packet error mask.

BOIM

Bit 9: BNA interrupt mask.

DAINT

OTG_HS device all endpoints interrupt register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OEPINT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPINT
r
Toggle fields

IEPINT

Bits 0-15: IN endpoint interrupt bits.

OEPINT

Bits 16-31: OUT endpoint interrupt bits.

DAINTMSK

OTG_HS all endpoints interrupt mask register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OEPM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPM
rw
Toggle fields

IEPM

Bits 0-15: IN EP interrupt mask bits.

OEPM

Bits 16-31: OUT EP interrupt mask bits.

DVBUSDIS

OTG_HS device VBUS discharge time register

Offset: 0x28, size: 32, reset: 0x000017D7, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VBUSDT
rw
Toggle fields

VBUSDT

Bits 0-15: Device VBUS discharge time.

DVBUSPULSE

OTG_HS device VBUS pulsing time register

Offset: 0x2c, size: 32, reset: 0x000005B8, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DVBUSP
rw
Toggle fields

DVBUSP

Bits 0-11: Device VBUS pulsing time.

DTHRCTL

OTG_HS Device threshold control register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARPEN
rw
RXTHRLEN
rw
RXTHREN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXTHRLEN
rw
ISOTHREN
rw
NONISOTHREN
rw
Toggle fields

NONISOTHREN

Bit 0: Nonisochronous IN endpoints threshold enable.

ISOTHREN

Bit 1: ISO IN endpoint threshold enable.

TXTHRLEN

Bits 2-10: Transmit threshold length.

RXTHREN

Bit 16: Receive threshold enable.

RXTHRLEN

Bits 17-25: Receive threshold length.

ARPEN

Bit 27: Arbiter parking enable.

DIEPEMPMSK

OTG_HS device IN endpoint FIFO empty interrupt mask register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXFEM
rw
Toggle fields

INEPTXFEM

Bits 0-15: IN EP Tx FIFO empty interrupt mask bits.

DEACHINT

OTG_HS device each endpoint interrupt register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OEP1INT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEP1INT
rw
Toggle fields

IEP1INT

Bit 1: IN endpoint 1interrupt bit.

OEP1INT

Bit 17: OUT endpoint 1 interrupt bit.

DEACHINTMSK

OTG_HS device each endpoint interrupt register mask

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OEP1INTM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEP1INTM
rw
Toggle fields

IEP1INTM

Bit 1: IN Endpoint 1 interrupt mask bit.

OEP1INTM

Bit 17: OUT Endpoint 1 interrupt mask bit.

DIEPEACHMSK1

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAKM
rw
BNAM
rw
TXFURM
rw
INEPNEM
rw
ITTXFEMSK
rw
TOM
rw
AHBERRM
rw
EPDM
rw
XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed interrupt mask.

EPDM

Bit 1: Endpoint disabled interrupt mask.

AHBERRM

Bit 2: AHB error mask.

TOM

Bit 3: Timeout condition mask (Non-isochronous endpoints).

ITTXFEMSK

Bit 4: IN token received when TxFIFO empty mask.

INEPNEM

Bit 6: IN endpoint NAK effective mask.

TXFURM

Bit 8: FIFO underrun mask.

BNAM

Bit 9: BNA interrupt mask.

NAKM

Bit 13: NAK interrupt mask.

DOEPEACHMSK1

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NYETMSK
rw
NAKMSK
rw
BERRM
rw
BNAM
rw
OUTPKTERRM
rw
B2BSTUPM
rw
OTEPDM
rw
STUPM
rw
AHBERRM
rw
EPDM
rw
XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed interrupt mask.

EPDM

Bit 1: Endpoint disabled interrupt mask.

AHBERRM

Bit 2: AHB error mask.

STUPM

Bit 3: SETUP phase done mask.

OTEPDM

Bit 4: OUT token received when endpoint disabled mask.

B2BSTUPM

Bit 6: Back-to-back SETUP packets received mask.

OUTPKTERRM

Bit 8: Out packet error mask.

BNAM

Bit 9: BNA interrupt mask.

BERRM

Bit 12: Babble error interrupt mask.

NAKMSK

Bit 13: NAK interrupt mask.

NYETMSK

Bit 14: NYET interrupt mask.

CTL [0]

OTG device endpoint-0 control register

Offset: 0x100, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
TXFNUM
rw
STALL
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even/odd frame.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

STALL

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TxFIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

INT [0]

OTG device endpoint-0 interrupt register

Offset: 0x108, size: 32, reset: 0x00000080, access: Unspecified

1/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw
BERR
rw
PKTDRPSTS
rw
BNA
rw
TXFIFOUDRN
rw
TXFE
r
INEPNE
rw
ITTXFE
rw
TOC
rw
EPDISD
rw
XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

TOC

Bit 3: Timeout condition.

ITTXFE

Bit 4: IN token received when TxFIFO is empty.

INEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

TXFIFOUDRN

Bit 8: Transmit Fifo Underrun.

BNA

Bit 9: Buffer not available interrupt.

PKTDRPSTS

Bit 11: Packet dropped status.

BERR

Bit 12: Babble error interrupt.

NAK

Bit 13: NAK interrupt.

TSIZ [0]

OTG_HS device IN endpoint 0 transfer size register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PKTCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-6: Transfer size.

PKTCNT

Bits 19-20: Packet count.

DMA [0]

OTG_HS device endpoint-0 DMA address register

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

TXFSTS [0]

OTG_HS device IN endpoint transmit FIFO status register

Offset: 0x118, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle fields

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space avail.

CTL [1]

OTG device endpoint-1 control register

Offset: 0x120, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
TXFNUM
rw
STALL
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even/odd frame.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

STALL

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TxFIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

INT [1]

OTG device endpoint-1 interrupt register

Offset: 0x128, size: 32, reset: 0x00000080, access: Unspecified

1/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw
BERR
rw
PKTDRPSTS
rw
BNA
rw
TXFIFOUDRN
rw
TXFE
r
INEPNE
rw
ITTXFE
rw
TOC
rw
EPDISD
rw
XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

TOC

Bit 3: Timeout condition.

ITTXFE

Bit 4: IN token received when TxFIFO is empty.

INEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

TXFIFOUDRN

Bit 8: Transmit Fifo Underrun.

BNA

Bit 9: Buffer not available interrupt.

PKTDRPSTS

Bit 11: Packet dropped status.

BERR

Bit 12: Babble error interrupt.

NAK

Bit 13: NAK interrupt.

TSIZ [1]

OTG_HS device endpoint transfer size register

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

DMA [1]

OTG_HS device endpoint-1 DMA address register

Offset: 0x134, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

TXFSTS [1]

OTG_HS device IN endpoint transmit FIFO status register

Offset: 0x138, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle fields

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space avail.

CTL [2]

OTG device endpoint-1 control register

Offset: 0x140, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
TXFNUM
rw
STALL
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even/odd frame.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

STALL

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TxFIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

INT [2]

OTG device endpoint-1 interrupt register

Offset: 0x148, size: 32, reset: 0x00000080, access: Unspecified

1/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw
BERR
rw
PKTDRPSTS
rw
BNA
rw
TXFIFOUDRN
rw
TXFE
r
INEPNE
rw
ITTXFE
rw
TOC
rw
EPDISD
rw
XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

TOC

Bit 3: Timeout condition.

ITTXFE

Bit 4: IN token received when TxFIFO is empty.

INEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

TXFIFOUDRN

Bit 8: Transmit Fifo Underrun.

BNA

Bit 9: Buffer not available interrupt.

PKTDRPSTS

Bit 11: Packet dropped status.

BERR

Bit 12: Babble error interrupt.

NAK

Bit 13: NAK interrupt.

TSIZ [2]

OTG_HS device endpoint transfer size register

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

DMA [2]

OTG_HS device endpoint-1 DMA address register

Offset: 0x154, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

TXFSTS [2]

OTG_HS device IN endpoint transmit FIFO status register

Offset: 0x158, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle fields

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space avail.

CTL [3]

OTG device endpoint-1 control register

Offset: 0x160, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
TXFNUM
rw
STALL
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even/odd frame.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

STALL

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TxFIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

INT [3]

OTG device endpoint-1 interrupt register

Offset: 0x168, size: 32, reset: 0x00000080, access: Unspecified

1/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw
BERR
rw
PKTDRPSTS
rw
BNA
rw
TXFIFOUDRN
rw
TXFE
r
INEPNE
rw
ITTXFE
rw
TOC
rw
EPDISD
rw
XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

TOC

Bit 3: Timeout condition.

ITTXFE

Bit 4: IN token received when TxFIFO is empty.

INEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

TXFIFOUDRN

Bit 8: Transmit Fifo Underrun.

BNA

Bit 9: Buffer not available interrupt.

PKTDRPSTS

Bit 11: Packet dropped status.

BERR

Bit 12: Babble error interrupt.

NAK

Bit 13: NAK interrupt.

TSIZ [3]

OTG_HS device endpoint transfer size register

Offset: 0x170, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

DMA [3]

OTG_HS device endpoint-1 DMA address register

Offset: 0x174, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

TXFSTS [3]

OTG_HS device IN endpoint transmit FIFO status register

Offset: 0x178, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle fields

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space avail.

CTL [4]

OTG device endpoint-1 control register

Offset: 0x180, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
TXFNUM
rw
STALL
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even/odd frame.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

STALL

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TxFIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

INT [4]

OTG device endpoint-1 interrupt register

Offset: 0x188, size: 32, reset: 0x00000080, access: Unspecified

1/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw
BERR
rw
PKTDRPSTS
rw
BNA
rw
TXFIFOUDRN
rw
TXFE
r
INEPNE
rw
ITTXFE
rw
TOC
rw
EPDISD
rw
XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

TOC

Bit 3: Timeout condition.

ITTXFE

Bit 4: IN token received when TxFIFO is empty.

INEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

TXFIFOUDRN

Bit 8: Transmit Fifo Underrun.

BNA

Bit 9: Buffer not available interrupt.

PKTDRPSTS

Bit 11: Packet dropped status.

BERR

Bit 12: Babble error interrupt.

NAK

Bit 13: NAK interrupt.

TSIZ [4]

OTG_HS device endpoint transfer size register

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

DMA [4]

OTG_HS device endpoint-1 DMA address register

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

TXFSTS [4]

OTG_HS device IN endpoint transmit FIFO status register

Offset: 0x198, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle fields

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space avail.

CTL [5]

OTG device endpoint-1 control register

Offset: 0x1a0, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
TXFNUM
rw
STALL
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even/odd frame.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

STALL

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TxFIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

INT [5]

OTG device endpoint-1 interrupt register

Offset: 0x1a8, size: 32, reset: 0x00000080, access: Unspecified

1/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw
BERR
rw
PKTDRPSTS
rw
BNA
rw
TXFIFOUDRN
rw
TXFE
r
INEPNE
rw
ITTXFE
rw
TOC
rw
EPDISD
rw
XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

TOC

Bit 3: Timeout condition.

ITTXFE

Bit 4: IN token received when TxFIFO is empty.

INEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

TXFIFOUDRN

Bit 8: Transmit Fifo Underrun.

BNA

Bit 9: Buffer not available interrupt.

PKTDRPSTS

Bit 11: Packet dropped status.

BERR

Bit 12: Babble error interrupt.

NAK

Bit 13: NAK interrupt.

TSIZ [5]

OTG_HS device endpoint transfer size register

Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

DMA [5]

OTG_HS device endpoint-1 DMA address register

Offset: 0x1b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

TXFSTS [5]

OTG_HS device IN endpoint transmit FIFO status register

Offset: 0x1b8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle fields

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space avail.

CTL [6]

OTG device endpoint-1 control register

Offset: 0x1c0, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
TXFNUM
rw
STALL
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even/odd frame.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

STALL

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TxFIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

INT [6]

OTG device endpoint-1 interrupt register

Offset: 0x1c8, size: 32, reset: 0x00000080, access: Unspecified

1/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw
BERR
rw
PKTDRPSTS
rw
BNA
rw
TXFIFOUDRN
rw
TXFE
r
INEPNE
rw
ITTXFE
rw
TOC
rw
EPDISD
rw
XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

TOC

Bit 3: Timeout condition.

ITTXFE

Bit 4: IN token received when TxFIFO is empty.

INEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

TXFIFOUDRN

Bit 8: Transmit Fifo Underrun.

BNA

Bit 9: Buffer not available interrupt.

PKTDRPSTS

Bit 11: Packet dropped status.

BERR

Bit 12: Babble error interrupt.

NAK

Bit 13: NAK interrupt.

TSIZ [6]

OTG_HS device endpoint transfer size register

Offset: 0x1d0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

DMA [6]

OTG_HS device endpoint-1 DMA address register

Offset: 0x1d4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

TXFSTS [6]

OTG_HS device IN endpoint transmit FIFO status register

Offset: 0x1d8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle fields

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space avail.

CTL [7]

OTG device endpoint-1 control register

Offset: 0x1e0, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
TXFNUM
rw
STALL
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even/odd frame.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

STALL

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TxFIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

INT [7]

OTG device endpoint-1 interrupt register

Offset: 0x1e8, size: 32, reset: 0x00000080, access: Unspecified

1/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw
BERR
rw
PKTDRPSTS
rw
BNA
rw
TXFIFOUDRN
rw
TXFE
r
INEPNE
rw
ITTXFE
rw
TOC
rw
EPDISD
rw
XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

TOC

Bit 3: Timeout condition.

ITTXFE

Bit 4: IN token received when TxFIFO is empty.

INEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

TXFIFOUDRN

Bit 8: Transmit Fifo Underrun.

BNA

Bit 9: Buffer not available interrupt.

PKTDRPSTS

Bit 11: Packet dropped status.

BERR

Bit 12: Babble error interrupt.

NAK

Bit 13: NAK interrupt.

TSIZ [7]

OTG_HS device endpoint transfer size register

Offset: 0x1f0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

DMA [7]

OTG_HS device endpoint-1 DMA address register

Offset: 0x1f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

TXFSTS [7]

OTG_HS device IN endpoint transmit FIFO status register

Offset: 0x1f8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle fields

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space avail.

CTL [8]

OTG device endpoint-1 control register

Offset: 0x200, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
TXFNUM
rw
STALL
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even/odd frame.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

STALL

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TxFIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

INT [8]

OTG device endpoint-1 interrupt register

Offset: 0x208, size: 32, reset: 0x00000080, access: Unspecified

1/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw
BERR
rw
PKTDRPSTS
rw
BNA
rw
TXFIFOUDRN
rw
TXFE
r
INEPNE
rw
ITTXFE
rw
TOC
rw
EPDISD
rw
XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

TOC

Bit 3: Timeout condition.

ITTXFE

Bit 4: IN token received when TxFIFO is empty.

INEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

TXFIFOUDRN

Bit 8: Transmit Fifo Underrun.

BNA

Bit 9: Buffer not available interrupt.

PKTDRPSTS

Bit 11: Packet dropped status.

BERR

Bit 12: Babble error interrupt.

NAK

Bit 13: NAK interrupt.

TSIZ [8]

OTG_HS device endpoint transfer size register

Offset: 0x210, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

DMA [8]

OTG_HS device endpoint-1 DMA address register

Offset: 0x214, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

TXFSTS [8]

OTG_HS device IN endpoint transmit FIFO status register

Offset: 0x218, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle fields

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space avail.

CTL [0]

OTG_HS device control OUT endpoint 0 control register

Offset: 0x300, size: 32, reset: 0x00008000, access: Unspecified

5/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
r
SNAK
w
CNAK
w
STALL
rw
SNPM
rw
EPTYP
r
NAKSTS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
r
MPSIZ
r
Toggle fields

MPSIZ

Bits 0-1: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

SNPM

Bit 20: Snoop mode.

STALL

Bit 21: STALL handshake.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

INT [0]

OTG_HS device endpoint-0 interrupt register

Offset: 0x308, size: 32, reset: 0x00000080, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NYET
rw
B2BSTUP
rw
OTEPDIS
rw
STUP
rw
EPDISD
rw
XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

STUP

Bit 3: SETUP phase done.

OTEPDIS

Bit 4: OUT token received when endpoint disabled.

B2BSTUP

Bit 6: Back-to-back SETUP packets received.

NYET

Bit 14: NYET interrupt.

TSIZ [0]

OTG_HS device endpoint-0 transfer size register

Offset: 0x310, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STUPCNT
rw
PKTCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-6: Transfer size.

PKTCNT

Bit 19: Packet count.

STUPCNT

Bits 29-30: SETUP packet count.

DMA [0]

OTG_HS device endpoint-0 DMA address register

Offset: 0x314, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

CTL [1]

OTG device endpoint-1 control register

Offset: 0x320, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
STALL
rw
SNPM
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even odd frame/Endpoint data PID.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

SNPM

Bit 20: Snoop mode.

STALL

Bit 21: STALL handshake.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID/Set even frame.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

INT [1]

OTG_HS device endpoint-1 interrupt register

Offset: 0x328, size: 32, reset: 0x00000080, access: Unspecified

1/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw
BERR
rw
PKTDRPSTS
rw
BNA
rw
TXFIFOUDRN
rw
TXFE
r
INEPNE
rw
ITTXFE
rw
TOC
rw
EPDISD
rw
XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

TOC

Bit 3: Timeout condition.

ITTXFE

Bit 4: IN token received when TxFIFO is empty.

INEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

TXFIFOUDRN

Bit 8: Transmit Fifo Underrun.

BNA

Bit 9: Buffer not available interrupt.

PKTDRPSTS

Bit 11: Packet dropped status.

BERR

Bit 12: Babble error interrupt.

NAK

Bit 13: NAK interrupt.

TSIZ [1]

OTG_HS device endpoint-1 transfer size register

Offset: 0x330, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDPID_STUPCNT
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

RXDPID_STUPCNT

Bits 29-30: Received data PID/SETUP packet count.

DMA [1]

OTG_HS device endpoint-1 DMA address register

Offset: 0x334, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

CTL [2]

OTG device endpoint-1 control register

Offset: 0x340, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
STALL
rw
SNPM
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even odd frame/Endpoint data PID.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

SNPM

Bit 20: Snoop mode.

STALL

Bit 21: STALL handshake.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID/Set even frame.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

INT [2]

OTG_HS device endpoint-1 interrupt register

Offset: 0x348, size: 32, reset: 0x00000080, access: Unspecified

1/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw
BERR
rw
PKTDRPSTS
rw
BNA
rw
TXFIFOUDRN
rw
TXFE
r
INEPNE
rw
ITTXFE
rw
TOC
rw
EPDISD
rw
XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

TOC

Bit 3: Timeout condition.

ITTXFE

Bit 4: IN token received when TxFIFO is empty.

INEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

TXFIFOUDRN

Bit 8: Transmit Fifo Underrun.

BNA

Bit 9: Buffer not available interrupt.

PKTDRPSTS

Bit 11: Packet dropped status.

BERR

Bit 12: Babble error interrupt.

NAK

Bit 13: NAK interrupt.

TSIZ [2]

OTG_HS device endpoint-1 transfer size register

Offset: 0x350, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDPID_STUPCNT
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

RXDPID_STUPCNT

Bits 29-30: Received data PID/SETUP packet count.

DMA [2]

OTG_HS device endpoint-1 DMA address register

Offset: 0x354, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

CTL [3]

OTG device endpoint-1 control register

Offset: 0x360, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
STALL
rw
SNPM
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even odd frame/Endpoint data PID.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

SNPM

Bit 20: Snoop mode.

STALL

Bit 21: STALL handshake.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID/Set even frame.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

INT [3]

OTG_HS device endpoint-1 interrupt register

Offset: 0x368, size: 32, reset: 0x00000080, access: Unspecified

1/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw
BERR
rw
PKTDRPSTS
rw
BNA
rw
TXFIFOUDRN
rw
TXFE
r
INEPNE
rw
ITTXFE
rw
TOC
rw
EPDISD
rw
XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

TOC

Bit 3: Timeout condition.

ITTXFE

Bit 4: IN token received when TxFIFO is empty.

INEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

TXFIFOUDRN

Bit 8: Transmit Fifo Underrun.

BNA

Bit 9: Buffer not available interrupt.

PKTDRPSTS

Bit 11: Packet dropped status.

BERR

Bit 12: Babble error interrupt.

NAK

Bit 13: NAK interrupt.

TSIZ [3]

OTG_HS device endpoint-1 transfer size register

Offset: 0x370, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDPID_STUPCNT
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

RXDPID_STUPCNT

Bits 29-30: Received data PID/SETUP packet count.

DMA [3]

OTG_HS device endpoint-1 DMA address register

Offset: 0x374, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

CTL [4]

OTG device endpoint-1 control register

Offset: 0x380, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
STALL
rw
SNPM
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even odd frame/Endpoint data PID.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

SNPM

Bit 20: Snoop mode.

STALL

Bit 21: STALL handshake.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID/Set even frame.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

INT [4]

OTG_HS device endpoint-1 interrupt register

Offset: 0x388, size: 32, reset: 0x00000080, access: Unspecified

1/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw
BERR
rw
PKTDRPSTS
rw
BNA
rw
TXFIFOUDRN
rw
TXFE
r
INEPNE
rw
ITTXFE
rw
TOC
rw
EPDISD
rw
XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

TOC

Bit 3: Timeout condition.

ITTXFE

Bit 4: IN token received when TxFIFO is empty.

INEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

TXFIFOUDRN

Bit 8: Transmit Fifo Underrun.

BNA

Bit 9: Buffer not available interrupt.

PKTDRPSTS

Bit 11: Packet dropped status.

BERR

Bit 12: Babble error interrupt.

NAK

Bit 13: NAK interrupt.

TSIZ [4]

OTG_HS device endpoint-1 transfer size register

Offset: 0x390, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDPID_STUPCNT
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

RXDPID_STUPCNT

Bits 29-30: Received data PID/SETUP packet count.

DMA [4]

OTG_HS device endpoint-1 DMA address register

Offset: 0x394, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

CTL [5]

OTG device endpoint-1 control register

Offset: 0x3a0, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
STALL
rw
SNPM
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even odd frame/Endpoint data PID.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

SNPM

Bit 20: Snoop mode.

STALL

Bit 21: STALL handshake.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID/Set even frame.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

INT [5]

OTG_HS device endpoint-1 interrupt register

Offset: 0x3a8, size: 32, reset: 0x00000080, access: Unspecified

1/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw
BERR
rw
PKTDRPSTS
rw
BNA
rw
TXFIFOUDRN
rw
TXFE
r
INEPNE
rw
ITTXFE
rw
TOC
rw
EPDISD
rw
XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

TOC

Bit 3: Timeout condition.

ITTXFE

Bit 4: IN token received when TxFIFO is empty.

INEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

TXFIFOUDRN

Bit 8: Transmit Fifo Underrun.

BNA

Bit 9: Buffer not available interrupt.

PKTDRPSTS

Bit 11: Packet dropped status.

BERR

Bit 12: Babble error interrupt.

NAK

Bit 13: NAK interrupt.

TSIZ [5]

OTG_HS device endpoint-1 transfer size register

Offset: 0x3b0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDPID_STUPCNT
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

RXDPID_STUPCNT

Bits 29-30: Received data PID/SETUP packet count.

DMA [5]

OTG_HS device endpoint-1 DMA address register

Offset: 0x3b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

CTL [6]

OTG device endpoint-1 control register

Offset: 0x3c0, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
STALL
rw
SNPM
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even odd frame/Endpoint data PID.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

SNPM

Bit 20: Snoop mode.

STALL

Bit 21: STALL handshake.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID/Set even frame.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

INT [6]

OTG_HS device endpoint-1 interrupt register

Offset: 0x3c8, size: 32, reset: 0x00000080, access: Unspecified

1/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw
BERR
rw
PKTDRPSTS
rw
BNA
rw
TXFIFOUDRN
rw
TXFE
r
INEPNE
rw
ITTXFE
rw
TOC
rw
EPDISD
rw
XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

TOC

Bit 3: Timeout condition.

ITTXFE

Bit 4: IN token received when TxFIFO is empty.

INEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

TXFIFOUDRN

Bit 8: Transmit Fifo Underrun.

BNA

Bit 9: Buffer not available interrupt.

PKTDRPSTS

Bit 11: Packet dropped status.

BERR

Bit 12: Babble error interrupt.

NAK

Bit 13: NAK interrupt.

TSIZ [6]

OTG_HS device endpoint-1 transfer size register

Offset: 0x3d0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDPID_STUPCNT
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

RXDPID_STUPCNT

Bits 29-30: Received data PID/SETUP packet count.

DMA [6]

OTG_HS device endpoint-1 DMA address register

Offset: 0x3d4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

CTL [7]

OTG device endpoint-1 control register

Offset: 0x3e0, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
STALL
rw
SNPM
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even odd frame/Endpoint data PID.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

SNPM

Bit 20: Snoop mode.

STALL

Bit 21: STALL handshake.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID/Set even frame.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

INT [7]

OTG_HS device endpoint-1 interrupt register

Offset: 0x3e8, size: 32, reset: 0x00000080, access: Unspecified

1/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw
BERR
rw
PKTDRPSTS
rw
BNA
rw
TXFIFOUDRN
rw
TXFE
r
INEPNE
rw
ITTXFE
rw
TOC
rw
EPDISD
rw
XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

TOC

Bit 3: Timeout condition.

ITTXFE

Bit 4: IN token received when TxFIFO is empty.

INEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

TXFIFOUDRN

Bit 8: Transmit Fifo Underrun.

BNA

Bit 9: Buffer not available interrupt.

PKTDRPSTS

Bit 11: Packet dropped status.

BERR

Bit 12: Babble error interrupt.

NAK

Bit 13: NAK interrupt.

TSIZ [7]

OTG_HS device endpoint-1 transfer size register

Offset: 0x3f0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDPID_STUPCNT
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

RXDPID_STUPCNT

Bits 29-30: Received data PID/SETUP packet count.

DMA [7]

OTG_HS device endpoint-1 DMA address register

Offset: 0x3f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

CTL [8]

OTG device endpoint-1 control register

Offset: 0x400, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
STALL
rw
SNPM
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even odd frame/Endpoint data PID.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

SNPM

Bit 20: Snoop mode.

STALL

Bit 21: STALL handshake.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID/Set even frame.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

INT [8]

OTG_HS device endpoint-1 interrupt register

Offset: 0x408, size: 32, reset: 0x00000080, access: Unspecified

1/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw
BERR
rw
PKTDRPSTS
rw
BNA
rw
TXFIFOUDRN
rw
TXFE
r
INEPNE
rw
ITTXFE
rw
TOC
rw
EPDISD
rw
XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

TOC

Bit 3: Timeout condition.

ITTXFE

Bit 4: IN token received when TxFIFO is empty.

INEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

TXFIFOUDRN

Bit 8: Transmit Fifo Underrun.

BNA

Bit 9: Buffer not available interrupt.

PKTDRPSTS

Bit 11: Packet dropped status.

BERR

Bit 12: Babble error interrupt.

NAK

Bit 13: NAK interrupt.

TSIZ [8]

OTG_HS device endpoint-1 transfer size register

Offset: 0x410, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDPID_STUPCNT
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

RXDPID_STUPCNT

Bits 29-30: Received data PID/SETUP packet count.

DMA [8]

OTG_HS device endpoint-1 DMA address register

Offset: 0x414, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

OTG1_HS_GLOBAL

0x40040000: USB 1 on the go high speed

48/179 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 GOTGCTL
0x4 GOTGINT
0x8 GAHBCFG
0xc GUSBCFG
0x10 GRSTCTL
0x14 GINTSTS
0x18 GINTMSK
0x1c GRXSTSR_Device
0x1c GRXSTSR_Host
0x20 GRXSTSP_Device
0x20 GRXSTSP_Host
0x24 GRXFSIZ
0x28 DIEPTXF0
0x28 HNPTXFSIZ
0x2c HNPTXSTS
0x38 GCCFG
0x3c CID
0x54 GLPMCFG
0x100 HPTXFSIZ
0x104 DIEPTXF[1]
0x108 DIEPTXF[2]
0x10c DIEPTXF[3]
0x110 DIEPTXF[4]
0x114 DIEPTXF[5]
0x118 DIEPTXF[6]
0x11c DIEPTXF[7]
0x120 DIEPTXF[8]
Toggle registers

GOTGCTL

OTG_HS control and status register

Offset: 0x0, size: 32, reset: 0x00000800, access: Unspecified

7/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CURMOD
r
OTGVER
rw
BSVLD
r
ASVLD
r
DBCT
r
CIDSTS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EHEN
rw
DHNPEN
rw
HSHNPEN
rw
HNPRQ
rw
HNGSCS
r
BVALOVAL
rw
BVALOEN
rw
AVALOVAL
rw
AVALOEN
rw
VBVALOVAL
rw
VBVALOEN
rw
SRQ
rw
SRQSCS
r
Toggle fields

SRQSCS

Bit 0: Session request success.

SRQ

Bit 1: Session request.

VBVALOEN

Bit 2: V_BUS valid override enable.

VBVALOVAL

Bit 3: V_BUS valid override value.

AVALOEN

Bit 4: A-peripheral session valid override enable.

AVALOVAL

Bit 5: A-peripheral session valid override value.

BVALOEN

Bit 6: B-peripheral session valid override enable.

BVALOVAL

Bit 7: B-peripheral session valid override value.

HNGSCS

Bit 8: Host negotiation success.

HNPRQ

Bit 9: HNP request.

HSHNPEN

Bit 10: Host set HNP enable.

DHNPEN

Bit 11: Device HNP enabled.

EHEN

Bit 12: Embedded host enable.

CIDSTS

Bit 16: Connector ID status.

DBCT

Bit 17: Long/short debounce time.

ASVLD

Bit 18: A-session valid.

BSVLD

Bit 19: B-session valid.

OTGVER

Bit 20: OTG version.

CURMOD

Bit 21: Current mode of operation.

GOTGINT

OTG_HS interrupt register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDCHNG
rw
DBCDNE
rw
ADTOCHG
rw
HNGDET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HNSSCHG
rw
SRSSCHG
rw
SEDET
rw
Toggle fields

SEDET

Bit 2: Session end detected.

SRSSCHG

Bit 8: Session request success status change.

HNSSCHG

Bit 9: Host negotiation success status change.

HNGDET

Bit 17: Host negotiation detected.

ADTOCHG

Bit 18: A-device timeout change.

DBCDNE

Bit 19: Debounce done.

IDCHNG

Bit 20: ID input pin changed.

GAHBCFG

OTG_HS AHB configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTXFELVL
rw
TXFELVL
rw
DMAEN
rw
HBSTLEN
rw
GINT
rw
Toggle fields

GINT

Bit 0: Global interrupt mask.

HBSTLEN

Bits 1-4: Burst length/type.

DMAEN

Bit 5: DMA enable.

TXFELVL

Bit 7: TxFIFO empty level.

PTXFELVL

Bit 8: Periodic TxFIFO empty level.

GUSBCFG

OTG_HS USB configuration register

Offset: 0xc, size: 32, reset: 0x00000A00, access: Unspecified

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FDMOD
rw
FHMOD
rw
ULPIIPD
rw
PTCI
rw
PCCI
rw
TSDPS
rw
ULPIEVBUSI
rw
ULPIEVBUSD
rw
ULPICSM
rw
ULPIAR
rw
ULPIFSLS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PHYLPCS
rw
TRDT
rw
HNPCAP
rw
SRPCAP
rw
PHYSEL
w
TOCAL
rw
Toggle fields

TOCAL

Bits 0-2: FS timeout calibration.

PHYSEL

Bit 6: USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select.

SRPCAP

Bit 8: SRP-capable.

HNPCAP

Bit 9: HNP-capable.

TRDT

Bits 10-13: USB turnaround time.

PHYLPCS

Bit 15: PHY Low-power clock select.

ULPIFSLS

Bit 17: ULPI FS/LS select.

ULPIAR

Bit 18: ULPI Auto-resume.

ULPICSM

Bit 19: ULPI Clock SuspendM.

ULPIEVBUSD

Bit 20: ULPI External VBUS Drive.

ULPIEVBUSI

Bit 21: ULPI external VBUS indicator.

TSDPS

Bit 22: TermSel DLine pulsing selection.

PCCI

Bit 23: Indicator complement.

PTCI

Bit 24: Indicator pass through.

ULPIIPD

Bit 25: ULPI interface protect disable.

FHMOD

Bit 29: Forced host mode.

FDMOD

Bit 30: Forced peripheral mode.

GRSTCTL

OTG_HS reset register

Offset: 0x10, size: 32, reset: 0x20000000, access: Unspecified

2/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AHBIDL
r
DMAREQ
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFNUM
rw
TXFFLSH
rw
RXFFLSH
rw
FCRST
rw
HSRST
rw
CSRST
rw
Toggle fields

CSRST

Bit 0: Core soft reset.

HSRST

Bit 1: HCLK soft reset.

FCRST

Bit 2: Host frame counter reset.

RXFFLSH

Bit 4: RxFIFO flush.

TXFFLSH

Bit 5: TxFIFO flush.

TXFNUM

Bits 6-10: TxFIFO number.

DMAREQ

Bit 30: DMA request signal enabled for USB OTG HS.

AHBIDL

Bit 31: AHB master idle.

GINTSTS

OTG_HS core interrupt register

Offset: 0x14, size: 32, reset: 0x04000020, access: Unspecified

11/26 fields covered.

Toggle fields

CMOD

Bit 0: Current mode of operation.

MMIS

Bit 1: Mode mismatch interrupt.

OTGINT

Bit 2: OTG interrupt.

SOF

Bit 3: Start of frame.

RXFLVL

Bit 4: RxFIFO nonempty.

NPTXFE

Bit 5: Nonperiodic TxFIFO empty.

GINAKEFF

Bit 6: Global IN nonperiodic NAK effective.

BOUTNAKEFF

Bit 7: Global OUT NAK effective.

ESUSP

Bit 10: Early suspend.

USBSUSP

Bit 11: USB suspend.

USBRST

Bit 12: USB reset.

ENUMDNE

Bit 13: Enumeration done.

ISOODRP

Bit 14: Isochronous OUT packet dropped interrupt.

EOPF

Bit 15: End of periodic frame interrupt.

IEPINT

Bit 18: IN endpoint interrupt.

OEPINT

Bit 19: OUT endpoint interrupt.

IISOIXFR

Bit 20: Incomplete isochronous IN transfer.

PXFR_INCOMPISOOUT

Bit 21: Incomplete periodic transfer.

DATAFSUSP

Bit 22: Data fetch suspended.

HPRTINT

Bit 24: Host port interrupt.

HCINT

Bit 25: Host channels interrupt.

PTXFE

Bit 26: Periodic TxFIFO empty.

CIDSCHG

Bit 28: Connector ID status change.

DISCINT

Bit 29: Disconnect detected interrupt.

SRQINT

Bit 30: Session request/new session detected interrupt.

WKUINT

Bit 31: Resume/remote wakeup detected interrupt.

GINTMSK

OTG_HS interrupt mask register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

1/27 fields covered.

Toggle fields

MMISM

Bit 1: Mode mismatch interrupt mask.

OTGINT

Bit 2: OTG interrupt mask.

SOFM

Bit 3: Start of frame mask.

RXFLVLM

Bit 4: Receive FIFO nonempty mask.

NPTXFEM

Bit 5: Nonperiodic TxFIFO empty mask.

GINAKEFFM

Bit 6: Global nonperiodic IN NAK effective mask.

GONAKEFFM

Bit 7: Global OUT NAK effective mask.

ESUSPM

Bit 10: Early suspend mask.

USBSUSPM

Bit 11: USB suspend mask.

USBRST

Bit 12: USB reset mask.

ENUMDNEM

Bit 13: Enumeration done mask.

ISOODRPM

Bit 14: Isochronous OUT packet dropped interrupt mask.

EOPFM

Bit 15: End of periodic frame interrupt mask.

IEPINT

Bit 18: IN endpoints interrupt mask.

OEPINT

Bit 19: OUT endpoints interrupt mask.

IISOIXFRM

Bit 20: Incomplete isochronous IN transfer mask.

PXFRM_IISOOXFRM

Bit 21: Incomplete periodic transfer mask.

FSUSPM

Bit 22: Data fetch suspended mask.

RSTDE

Bit 23: Reset detected interrupt mask.

PRTIM

Bit 24: Host port interrupt mask.

HCIM

Bit 25: Host channels interrupt mask.

PTXFEM

Bit 26: Periodic TxFIFO empty mask.

LPMINTM

Bit 27: LPM interrupt mask.

CIDSCHGM

Bit 28: Connector ID status change mask.

DISCINT

Bit 29: Disconnect detected interrupt mask.

SRQIM

Bit 30: Session request/new session detected interrupt mask.

WUIM

Bit 31: Resume/remote wakeup detected interrupt mask.

GRXSTSR_Device

OTG_HS Receive status debug read register (peripheral mode mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FRMNUM
r
PKTSTS
r
DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPID
r
BCNT
r
EPNUM
r
Toggle fields

EPNUM

Bits 0-3: Endpoint number.

BCNT

Bits 4-14: Byte count.

DPID

Bits 15-16: Data PID.

PKTSTS

Bits 17-20: Packet status.

FRMNUM

Bits 21-24: Frame number.

GRXSTSR_Host

OTG_HS Receive status debug read register (host mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PKTSTS
r
DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPID
r
BCNT
r
CHNUM
r
Toggle fields

CHNUM

Bits 0-3: Channel number.

BCNT

Bits 4-14: Byte count.

DPID

Bits 15-16: Data PID.

PKTSTS

Bits 17-20: Packet status.

GRXSTSP_Device

OTG_HS status read and pop register (peripheral mode)

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FRMNUM
r
PKTSTS
r
DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPID
r
BCNT
r
EPNUM
r
Toggle fields

EPNUM

Bits 0-3: Endpoint number.

BCNT

Bits 4-14: Byte count.

DPID

Bits 15-16: Data PID.

PKTSTS

Bits 17-20: Packet status.

FRMNUM

Bits 21-24: Frame number.

GRXSTSP_Host

OTG_HS status read and pop register (host mode)

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PKTSTS
r
DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPID
r
BCNT
r
CHNUM
r
Toggle fields

CHNUM

Bits 0-3: Channel number.

BCNT

Bits 4-14: Byte count.

DPID

Bits 15-16: Data PID.

PKTSTS

Bits 17-20: Packet status.

GRXFSIZ

OTG_HS Receive FIFO size register

Offset: 0x24, size: 32, reset: 0x00000200, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXFD
rw
Toggle fields

RXFD

Bits 0-15: RxFIFO depth.

DIEPTXF0

Endpoint 0 transmit FIFO size (peripheral mode)

Offset: 0x28, size: 32, reset: 0x00000200, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TX0FD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TX0FSA
rw
Toggle fields

TX0FSA

Bits 0-15: Endpoint 0 transmit RAM start address.

TX0FD

Bits 16-31: Endpoint 0 TxFIFO depth.

HNPTXFSIZ

OTG_HS nonperiodic transmit FIFO size register (host mode)

Offset: 0x28, size: 32, reset: 0x00000200, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPTXFSA
rw
Toggle fields

NPTXFSA

Bits 0-15: Nonperiodic transmit RAM start address.

NPTXFD

Bits 16-31: Nonperiodic TxFIFO depth.

HNPTXSTS

OTG_HS nonperiodic transmit FIFO/queue status register

Offset: 0x2c, size: 32, reset: 0x00080200, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPTXQTOP
r
NPTQXSAV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPTXFSAV
r
Toggle fields

NPTXFSAV

Bits 0-15: Nonperiodic TxFIFO space available.

NPTQXSAV

Bits 16-23: Nonperiodic transmit request queue space available.

NPTXQTOP

Bits 24-30: Top of the nonperiodic transmit request queue.

GCCFG

OTG_HS general core configuration register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VBDEN
rw
SDEN
rw
PDEN
rw
DCDEN
rw
BCDEN
rw
PWRDWN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PS2DET
rw
SDET
rw
PDET
rw
DCDET
rw
Toggle fields

DCDET

Bit 0: Data contact detection (DCD) status.

PDET

Bit 1: Primary detection (PD) status.

SDET

Bit 2: Secondary detection (SD) status.

PS2DET

Bit 3: DM pull-up detection status.

PWRDWN

Bit 16: Power down.

BCDEN

Bit 17: Battery charging detector (BCD) enable.

DCDEN

Bit 18: Data contact detection (DCD) mode enable.

PDEN

Bit 19: Primary detection (PD) mode enable.

SDEN

Bit 20: Secondary detection (SD) mode enable.

VBDEN

Bit 21: USB VBUS detection enable.

CID

OTG_HS core ID register

Offset: 0x3c, size: 32, reset: 0x00001200, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRODUCT_ID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRODUCT_ID
rw
Toggle fields

PRODUCT_ID

Bits 0-31: Product ID field.

GLPMCFG

OTG core LPM configuration register

Offset: 0x54, size: 32, reset: 0x00000000, access: Unspecified

6/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENBESL
rw
LPMRCNTSTS
r
SNDLPM
rw
LPMRCNT
rw
LPMCHIDX
rw
L1RSMOK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLPSTS
r
LPMRST
r
L1DSEN
rw
BESLTHRS
rw
L1SSEN
rw
REMWAKE
r
BESL
r
LPMACK
rw
LPMEN
rw
Toggle fields

LPMEN

Bit 0: LPM support enable.

LPMACK

Bit 1: LPM token acknowledge enable.

BESL

Bits 2-5: Best effort service latency.

REMWAKE

Bit 6: bRemoteWake value.

L1SSEN

Bit 7: L1 Shallow Sleep enable.

BESLTHRS

Bits 8-11: BESL threshold.

L1DSEN

Bit 12: L1 deep sleep enable.

LPMRST

Bits 13-14: LPM response.

SLPSTS

Bit 15: Port sleep status.

L1RSMOK

Bit 16: Sleep State Resume OK.

LPMCHIDX

Bits 17-20: LPM Channel Index.

LPMRCNT

Bits 21-23: LPM retry count.

SNDLPM

Bit 24: Send LPM transaction.

LPMRCNTSTS

Bits 25-27: LPM retry count status.

ENBESL

Bit 28: Enable best effort service latency.

HPTXFSIZ

OTG_HS Host periodic transmit FIFO size register

Offset: 0x100, size: 32, reset: 0x02000600, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTXSA
rw
Toggle fields

PTXSA

Bits 0-15: Host periodic TxFIFO start address.

PTXFD

Bits 16-31: Host periodic TxFIFO depth.

DIEPTXF[1]

OTG_HS device IN endpoint transmit FIFO size register

Offset: 0x104, size: 32, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle fields

INEPTXSA

Bits 0-15: IN endpoint FIFOx transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

DIEPTXF[2]

OTG_HS device IN endpoint transmit FIFO size register

Offset: 0x108, size: 32, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle fields

INEPTXSA

Bits 0-15: IN endpoint FIFOx transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

DIEPTXF[3]

OTG_HS device IN endpoint transmit FIFO size register

Offset: 0x10c, size: 32, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle fields

INEPTXSA

Bits 0-15: IN endpoint FIFOx transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

DIEPTXF[4]

OTG_HS device IN endpoint transmit FIFO size register

Offset: 0x110, size: 32, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle fields

INEPTXSA

Bits 0-15: IN endpoint FIFOx transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

DIEPTXF[5]

OTG_HS device IN endpoint transmit FIFO size register

Offset: 0x114, size: 32, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle fields

INEPTXSA

Bits 0-15: IN endpoint FIFOx transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

DIEPTXF[6]

OTG_HS device IN endpoint transmit FIFO size register

Offset: 0x118, size: 32, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle fields

INEPTXSA

Bits 0-15: IN endpoint FIFOx transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

DIEPTXF[7]

OTG_HS device IN endpoint transmit FIFO size register

Offset: 0x11c, size: 32, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle fields

INEPTXSA

Bits 0-15: IN endpoint FIFOx transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

DIEPTXF[8]

OTG_HS device IN endpoint transmit FIFO size register

Offset: 0x120, size: 32, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle fields

INEPTXSA

Bits 0-15: IN endpoint FIFOx transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

OTG1_HS_HOST

0x40040400: USB 1 on the go high speed

10/679 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 HCFG
0x4 HFIR
0x8 HFNUM
0x10 HPTXSTS
0x14 HAINT
0x18 HAINTMSK
0x40 HPRT
0x100 CHAR [0]
0x104 SPLT [0]
0x108 INT [0]
0x10c INTMSK [0]
0x110 TSIZ [0]
0x114 DMA [0]
0x120 CHAR [1]
0x124 SPLT [1]
0x128 INT [1]
0x12c INTMSK [1]
0x130 TSIZ [1]
0x134 DMA [1]
0x140 CHAR [2]
0x144 SPLT [2]
0x148 INT [2]
0x14c INTMSK [2]
0x150 TSIZ [2]
0x154 DMA [2]
0x160 CHAR [3]
0x164 SPLT [3]
0x168 INT [3]
0x16c INTMSK [3]
0x170 TSIZ [3]
0x174 DMA [3]
0x180 CHAR [4]
0x184 SPLT [4]
0x188 INT [4]
0x18c INTMSK [4]
0x190 TSIZ [4]
0x194 DMA [4]
0x1a0 CHAR [5]
0x1a4 SPLT [5]
0x1a8 INT [5]
0x1ac INTMSK [5]
0x1b0 TSIZ [5]
0x1b4 DMA [5]
0x1c0 CHAR [6]
0x1c4 SPLT [6]
0x1c8 INT [6]
0x1cc INTMSK [6]
0x1d0 TSIZ [6]
0x1d4 DMA [6]
0x1e0 CHAR [7]
0x1e4 SPLT [7]
0x1e8 INT [7]
0x1ec INTMSK [7]
0x1f0 TSIZ [7]
0x1f4 DMA [7]
0x200 CHAR [8]
0x204 SPLT [8]
0x208 INT [8]
0x20c INTMSK [8]
0x210 TSIZ [8]
0x214 DMA [8]
0x220 CHAR [9]
0x224 SPLT [9]
0x228 INT [9]
0x22c INTMSK [9]
0x230 TSIZ [9]
0x234 DMA [9]
0x240 CHAR [10]
0x244 SPLT [10]
0x248 INT [10]
0x24c INTMSK [10]
0x250 TSIZ [10]
0x254 DMA [10]
0x260 CHAR [11]
0x264 SPLT [11]
0x268 INT [11]
0x26c INTMSK [11]
0x270 TSIZ [11]
0x274 DMA [11]
0x280 CHAR [12]
0x284 SPLT [12]
0x288 INT [12]
0x28c INTMSK [12]
0x290 TSIZ [12]
0x294 DMA [12]
0x2a0 CHAR [13]
0x2a4 SPLT [13]
0x2a8 INT [13]
0x2ac INTMSK [13]
0x2b0 TSIZ [13]
0x2b4 DMA [13]
0x2c0 CHAR [14]
0x2c4 SPLT [14]
0x2c8 INT [14]
0x2cc INTMSK [14]
0x2d0 TSIZ [14]
0x2d4 DMA [14]
0x2e0 CHAR [15]
0x2e4 SPLT [15]
0x2e8 INT [15]
0x2ec INTMSK [15]
0x2f0 TSIZ [15]
0x2f4 DMA [15]
Toggle registers

HCFG

OTG_HS host configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSLSS
r
FSLSPCS
rw
Toggle fields

FSLSPCS

Bits 0-1: FS/LS PHY clock select.

FSLSS

Bit 2: FS- and LS-only support.

HFIR

OTG_HS Host frame interval register

Offset: 0x4, size: 32, reset: 0x0000EA60, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FRIVL
rw
Toggle fields

FRIVL

Bits 0-15: Frame interval.

HFNUM

OTG_HS host frame number/frame time remaining register

Offset: 0x8, size: 32, reset: 0x00003FFF, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FTREM
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FRNUM
r
Toggle fields

FRNUM

Bits 0-15: Frame number.

FTREM

Bits 16-31: Frame time remaining.

HPTXSTS

OTG_HS_Host periodic transmit FIFO/queue status register

Offset: 0x10, size: 32, reset: 0x00080100, access: Unspecified

2/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTXQTOP
r
PTXQSAV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTXFSAVL
rw
Toggle fields

PTXFSAVL

Bits 0-15: Periodic transmit data FIFO space available.

PTXQSAV

Bits 16-23: Periodic transmit request queue space available.

PTXQTOP

Bits 24-31: Top of the periodic transmit request queue.

HAINT

OTG_HS Host all channels interrupt register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HAINT
r
Toggle fields

HAINT

Bits 0-15: Channel interrupts.

HAINTMSK

OTG_HS host all channels interrupt mask register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HAINTM
rw
Toggle fields

HAINTM

Bits 0-15: Channel interrupt mask.

HPRT

OTG_HS host port control and status register

Offset: 0x40, size: 32, reset: 0x00000000, access: Unspecified

4/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PSPD
r
PTCTL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTCTL
rw
PPWR
rw
PLSTS
r
PRST
rw
PSUSP
rw
PRES
rw
POCCHNG
rw
POCA
r
PENCHNG
rw
PENA
rw
PCDET
rw
PCSTS
r
Toggle fields

PCSTS

Bit 0: Port connect status.

PCDET

Bit 1: Port connect detected.

PENA

Bit 2: Port enable.

PENCHNG

Bit 3: Port enable/disable change.

POCA

Bit 4: Port overcurrent active.

POCCHNG

Bit 5: Port overcurrent change.

PRES

Bit 6: Port resume.

PSUSP

Bit 7: Port suspend.

PRST

Bit 8: Port reset.

PLSTS

Bits 10-11: Port line status.

PPWR

Bit 12: Port power.

PTCTL

Bits 13-16: Port test control.

PSPD

Bits 17-18: Port speed.

CHAR [0]

OTG_HS host channel-0 characteristics register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MC
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

SPLT [0]

OTG_HS host channel-0 split control register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw
COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw
HUBADDR
rw
PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

INT [0]

OTG_HS host channel-11 interrupt register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
NYET
rw
ACK
rw
NAK
rw
STALL
rw
AHBERR
rw
CHH
rw
XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

INTMSK [0]

OTG_HS host channel-11 interrupt mask register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
AHBERR
rw
CHHM
rw
XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

TSIZ [0]

OTG_HS host channel-11 transfer size register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

DMA [0]

OTG_HS host channel-0 DMA address register

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

CHAR [1]

OTG_HS host channel-0 characteristics register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MC
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

SPLT [1]

OTG_HS host channel-0 split control register

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw
COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw
HUBADDR
rw
PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

INT [1]

OTG_HS host channel-11 interrupt register

Offset: 0x128, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
NYET
rw
ACK
rw
NAK
rw
STALL
rw
AHBERR
rw
CHH
rw
XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

INTMSK [1]

OTG_HS host channel-11 interrupt mask register

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
AHBERR
rw
CHHM
rw
XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

TSIZ [1]

OTG_HS host channel-11 transfer size register

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

DMA [1]

OTG_HS host channel-0 DMA address register

Offset: 0x134, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

CHAR [2]

OTG_HS host channel-0 characteristics register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MC
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

SPLT [2]

OTG_HS host channel-0 split control register

Offset: 0x144, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw
COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw
HUBADDR
rw
PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

INT [2]

OTG_HS host channel-11 interrupt register

Offset: 0x148, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
NYET
rw
ACK
rw
NAK
rw
STALL
rw
AHBERR
rw
CHH
rw
XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

INTMSK [2]

OTG_HS host channel-11 interrupt mask register

Offset: 0x14c, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
AHBERR
rw
CHHM
rw
XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

TSIZ [2]

OTG_HS host channel-11 transfer size register

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

DMA [2]

OTG_HS host channel-0 DMA address register

Offset: 0x154, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

CHAR [3]

OTG_HS host channel-0 characteristics register

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MC
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

SPLT [3]

OTG_HS host channel-0 split control register

Offset: 0x164, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw
COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw
HUBADDR
rw
PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

INT [3]

OTG_HS host channel-11 interrupt register

Offset: 0x168, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
NYET
rw
ACK
rw
NAK
rw
STALL
rw
AHBERR
rw
CHH
rw
XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

INTMSK [3]

OTG_HS host channel-11 interrupt mask register

Offset: 0x16c, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
AHBERR
rw
CHHM
rw
XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

TSIZ [3]

OTG_HS host channel-11 transfer size register

Offset: 0x170, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

DMA [3]

OTG_HS host channel-0 DMA address register

Offset: 0x174, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

CHAR [4]

OTG_HS host channel-0 characteristics register

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MC
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

SPLT [4]

OTG_HS host channel-0 split control register

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw
COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw
HUBADDR
rw
PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

INT [4]

OTG_HS host channel-11 interrupt register

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
NYET
rw
ACK
rw
NAK
rw
STALL
rw
AHBERR
rw
CHH
rw
XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

INTMSK [4]

OTG_HS host channel-11 interrupt mask register

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
AHBERR
rw
CHHM
rw
XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

TSIZ [4]

OTG_HS host channel-11 transfer size register

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

DMA [4]

OTG_HS host channel-0 DMA address register

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

CHAR [5]

OTG_HS host channel-0 characteristics register

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MC
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

SPLT [5]

OTG_HS host channel-0 split control register

Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw
COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw
HUBADDR
rw
PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

INT [5]

OTG_HS host channel-11 interrupt register

Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
NYET
rw
ACK
rw
NAK
rw
STALL
rw
AHBERR
rw
CHH
rw
XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

INTMSK [5]

OTG_HS host channel-11 interrupt mask register

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
AHBERR
rw
CHHM
rw
XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

TSIZ [5]

OTG_HS host channel-11 transfer size register

Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

DMA [5]

OTG_HS host channel-0 DMA address register

Offset: 0x1b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

CHAR [6]

OTG_HS host channel-0 characteristics register

Offset: 0x1c0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MC
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

SPLT [6]

OTG_HS host channel-0 split control register

Offset: 0x1c4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw
COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw
HUBADDR
rw
PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

INT [6]

OTG_HS host channel-11 interrupt register

Offset: 0x1c8, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
NYET
rw
ACK
rw
NAK
rw
STALL
rw
AHBERR
rw
CHH
rw
XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

INTMSK [6]

OTG_HS host channel-11 interrupt mask register

Offset: 0x1cc, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
AHBERR
rw
CHHM
rw
XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

TSIZ [6]

OTG_HS host channel-11 transfer size register

Offset: 0x1d0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

DMA [6]

OTG_HS host channel-0 DMA address register

Offset: 0x1d4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

CHAR [7]

OTG_HS host channel-0 characteristics register

Offset: 0x1e0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MC
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

SPLT [7]

OTG_HS host channel-0 split control register

Offset: 0x1e4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw
COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw
HUBADDR
rw
PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

INT [7]

OTG_HS host channel-11 interrupt register

Offset: 0x1e8, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
NYET
rw
ACK
rw
NAK
rw
STALL
rw
AHBERR
rw
CHH
rw
XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

INTMSK [7]

OTG_HS host channel-11 interrupt mask register

Offset: 0x1ec, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
AHBERR
rw
CHHM
rw
XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

TSIZ [7]

OTG_HS host channel-11 transfer size register

Offset: 0x1f0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

DMA [7]

OTG_HS host channel-0 DMA address register

Offset: 0x1f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

CHAR [8]

OTG_HS host channel-0 characteristics register

Offset: 0x200, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MC
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

SPLT [8]

OTG_HS host channel-0 split control register

Offset: 0x204, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw
COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw
HUBADDR
rw
PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

INT [8]

OTG_HS host channel-11 interrupt register

Offset: 0x208, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
NYET
rw
ACK
rw
NAK
rw
STALL
rw
AHBERR
rw
CHH
rw
XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

INTMSK [8]

OTG_HS host channel-11 interrupt mask register

Offset: 0x20c, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
AHBERR
rw
CHHM
rw
XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

TSIZ [8]

OTG_HS host channel-11 transfer size register

Offset: 0x210, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

DMA [8]

OTG_HS host channel-0 DMA address register

Offset: 0x214, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

CHAR [9]

OTG_HS host channel-0 characteristics register

Offset: 0x220, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MC
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

SPLT [9]

OTG_HS host channel-0 split control register

Offset: 0x224, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw
COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw
HUBADDR
rw
PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

INT [9]

OTG_HS host channel-11 interrupt register

Offset: 0x228, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
NYET
rw
ACK
rw
NAK
rw
STALL
rw
AHBERR
rw
CHH
rw
XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

INTMSK [9]

OTG_HS host channel-11 interrupt mask register

Offset: 0x22c, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
AHBERR
rw
CHHM
rw
XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

TSIZ [9]

OTG_HS host channel-11 transfer size register

Offset: 0x230, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

DMA [9]

OTG_HS host channel-0 DMA address register

Offset: 0x234, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

CHAR [10]

OTG_HS host channel-0 characteristics register

Offset: 0x240, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MC
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

SPLT [10]

OTG_HS host channel-0 split control register

Offset: 0x244, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw
COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw
HUBADDR
rw
PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

INT [10]

OTG_HS host channel-11 interrupt register

Offset: 0x248, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
NYET
rw
ACK
rw
NAK
rw
STALL
rw
AHBERR
rw
CHH
rw
XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

INTMSK [10]

OTG_HS host channel-11 interrupt mask register

Offset: 0x24c, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
AHBERR
rw
CHHM
rw
XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

TSIZ [10]

OTG_HS host channel-11 transfer size register

Offset: 0x250, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

DMA [10]

OTG_HS host channel-0 DMA address register

Offset: 0x254, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

CHAR [11]

OTG_HS host channel-0 characteristics register

Offset: 0x260, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MC
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

SPLT [11]

OTG_HS host channel-0 split control register

Offset: 0x264, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw
COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw
HUBADDR
rw
PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

INT [11]

OTG_HS host channel-11 interrupt register

Offset: 0x268, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
NYET
rw
ACK
rw
NAK
rw
STALL
rw
AHBERR
rw
CHH
rw
XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

INTMSK [11]

OTG_HS host channel-11 interrupt mask register

Offset: 0x26c, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
AHBERR
rw
CHHM
rw
XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

TSIZ [11]

OTG_HS host channel-11 transfer size register

Offset: 0x270, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

DMA [11]

OTG_HS host channel-0 DMA address register

Offset: 0x274, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

CHAR [12]

OTG_HS host channel-0 characteristics register

Offset: 0x280, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MC
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

SPLT [12]

OTG_HS host channel-0 split control register

Offset: 0x284, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw
COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw
HUBADDR
rw
PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

INT [12]

OTG_HS host channel-11 interrupt register

Offset: 0x288, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
NYET
rw
ACK
rw
NAK
rw
STALL
rw
AHBERR
rw
CHH
rw
XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

INTMSK [12]

OTG_HS host channel-11 interrupt mask register

Offset: 0x28c, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
AHBERR
rw
CHHM
rw
XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

TSIZ [12]

OTG_HS host channel-11 transfer size register

Offset: 0x290, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

DMA [12]

OTG_HS host channel-0 DMA address register

Offset: 0x294, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

CHAR [13]

OTG_HS host channel-0 characteristics register

Offset: 0x2a0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MC
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

SPLT [13]

OTG_HS host channel-0 split control register

Offset: 0x2a4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw
COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw
HUBADDR
rw
PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

INT [13]

OTG_HS host channel-11 interrupt register

Offset: 0x2a8, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
NYET
rw
ACK
rw
NAK
rw
STALL
rw
AHBERR
rw
CHH
rw
XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

INTMSK [13]

OTG_HS host channel-11 interrupt mask register

Offset: 0x2ac, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
AHBERR
rw
CHHM
rw
XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

TSIZ [13]

OTG_HS host channel-11 transfer size register

Offset: 0x2b0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

DMA [13]

OTG_HS host channel-0 DMA address register

Offset: 0x2b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

CHAR [14]

OTG_HS host channel-0 characteristics register

Offset: 0x2c0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MC
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

SPLT [14]

OTG_HS host channel-0 split control register

Offset: 0x2c4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw
COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw
HUBADDR
rw
PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

INT [14]

OTG_HS host channel-11 interrupt register

Offset: 0x2c8, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
NYET
rw
ACK
rw
NAK
rw
STALL
rw
AHBERR
rw
CHH
rw
XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

INTMSK [14]

OTG_HS host channel-11 interrupt mask register

Offset: 0x2cc, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
AHBERR
rw
CHHM
rw
XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

TSIZ [14]

OTG_HS host channel-11 transfer size register

Offset: 0x2d0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

DMA [14]

OTG_HS host channel-0 DMA address register

Offset: 0x2d4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

CHAR [15]

OTG_HS host channel-0 characteristics register

Offset: 0x2e0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MC
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

SPLT [15]

OTG_HS host channel-0 split control register

Offset: 0x2e4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw
COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw
HUBADDR
rw
PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

INT [15]

OTG_HS host channel-11 interrupt register

Offset: 0x2e8, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
NYET
rw
ACK
rw
NAK
rw
STALL
rw
AHBERR
rw
CHH
rw
XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

INTMSK [15]

OTG_HS host channel-11 interrupt mask register

Offset: 0x2ec, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
AHBERR
rw
CHHM
rw
XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

TSIZ [15]

OTG_HS host channel-11 transfer size register

Offset: 0x2f0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

DMA [15]

OTG_HS host channel-0 DMA address register

Offset: 0x2f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMA address.

OTG1_HS_PWRCLK

0x40040e00: USB 1 on the go high speed

0/3 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 PCGCR
Toggle registers

PCGCR

Power and clock gating control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PHYSUSP
rw
GATEHCLK
rw
STPPCLK
rw
Toggle fields

STPPCLK

Bit 0: Stop PHY clock.

GATEHCLK

Bit 1: Gate HCLK.

PHYSUSP

Bit 4: PHY suspended.

PSSI

0x48020400: Parallel synchronous slave interface

4/18 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SR
0x8 RIS
0xc IER
0x10 MIS
0x14 ICR
0x28 DR
Toggle registers

CR

Offset: 0x0, size: 32, reset: 0x40000000, access: Unspecified

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OUTEN
rw
DMAEN
rw
DERDYCFG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENABLE
rw
EDM
rw
RDYPOL
rw
DEPOL
rw
CKPOL
rw
Toggle fields

CKPOL

Bit 5: Parallel data clock polarity This bit configures the capture edge of the parallel clock or the edge used for driving outputs, depending on OUTEN..

DEPOL

Bit 6: Data enable (PSSI_DE) polarity This bit indicates the level on the PSSI_DE pin when the data are not valid on the parallel interface..

RDYPOL

Bit 8: Ready (PSSI_RDY) polarity This bit indicates the level on the PSSI_RDY pin when the data are not valid on the parallel interface..

EDM

Bits 10-11: Extended data mode.

ENABLE

Bit 14: PSSI enable The contents of the FIFO are flushed when ENABLE is cleared to 0. Note: When ENABLE=1, the content of PSSI_CR must not be changed, except for the ENABLE bit itself. All configuration bits can change as soon as ENABLE changes from 0 to 1. The DMA controller and all PSSI configuration registers must be programmed correctly before setting the ENABLE bit to 1. The ENABLE bit and the DCMI ENABLE bit (bit 15 of DCMI_CR) must not be set to 1 at the same time..

DERDYCFG

Bits 18-20: Data enable and ready configuration When the PSSI_RDY function is mapped to the PSSI_DE pin (settings 101 or 111), it is still the RDYPOL bit which determines its polarity. Similarly, when the PSSI_DE function is mapped to the PSSI_RDY pin (settings 110 or 111), it is still the DEPOL bit which determines its polarity..

DMAEN

Bit 30: DMA enable bit.

OUTEN

Bit 31: Data direction selection bit.

SR

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTT1B
r
RTT4B
r
Toggle fields

RTT4B

Bit 2: FIFO is ready to transfer four bytes.

RTT1B

Bit 3: FIFO is ready to transfer one byte.

RIS

PSSI raw interrupt status register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVR_RIS
r
Toggle fields

OVR_RIS

Bit 1: Data buffer overrun/underrun raw interrupt status This bit is cleared by writing a 1 to the OVR_ISC bit in PSSI_ICR..

IER

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVR_IE
rw
Toggle fields

OVR_IE

Bit 1: Data buffer overrun/underrun interrupt enable.

MIS

PSSI masked interrupt status register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVR_MIS
r
Toggle fields

OVR_MIS

Bit 1: Data buffer overrun/underrun masked interrupt status This bit is set to 1 only when PSSI_IER/OVR_IE and PSSI_RIS/OVR_RIS are both set to 1..

ICR

PSSI interrupt clear register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVR_ISC
w
Toggle fields

OVR_ISC

Bit 1: Data buffer overrun/underrun interrupt status clear Writing this bit to 1 clears the OVR_RIS bit in PSSI_RIS..

DR

PSSI data register

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BYTE3
rw
BYTE2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BYTE1
rw
BYTE0
rw
Toggle fields

BYTE0

Bits 0-7: Data byte 0.

BYTE1

Bits 8-15: Data byte 1.

BYTE2

Bits 16-23: Data byte 2.

BYTE3

Bits 24-31: Data byte 3.

PWR

0x58024800: PWR

13/78 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CSR1
0x8 CR2
0xc CR3
0x10 CPUCR
0x18 SRDCR
0x20 WKUPCR
0x24 WKUPFR
0x28 WKUPEPR
Toggle registers

CR1

PWR control register 1

Offset: 0x0, size: 32, reset: 0xF000C000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRDRAMSO
rw
HSITFSO
rw
GFXSO
rw
ITCMSO
rw
AHBRAM2SO
rw
AHBRAM1SO
rw
AXIRAM3SO
rw
AXIRAM2SO
rw
AXIRAM1SO
rw
ALS
rw
AVDEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SVOS
rw
AVD_READY
rw
BOOSTE
rw
FLPS
rw
DBP
rw
PLS
rw
PVDE
rw
LPDS
rw
Toggle fields

LPDS

Bit 0: Low-power Deepsleep with SVOS3 (SVOS4 and SVOS5 always use low-power, regardless of the setting of this bit).

PVDE

Bit 4: Programmable voltage detector enable.

PLS

Bits 5-7: Programmable voltage detector level selection These bits select the voltage threshold detected by the PVD. Note: Refer to Section Electrical characteristics of the product datasheet for more details..

DBP

Bit 8: Disable backup domain write protection In reset state, the RCC_BDCR register, the RTC registers (including the backup registers), BREN and MOEN bits in PWR_CR2 register, are protected against parasitic write access. This bit must be set to enable write access to these registers..

FLPS

Bit 9: Flash low-power mode in DStop mode This bit allows to obtain the best trade-off between low-power consumption and restart time when exiting from DStop mode. When it is set, the Flash memory enters low-power mode when D1 domain is in DStop mode..

BOOSTE

Bit 12: BOOSTE.

AVD_READY

Bit 13: AVD_READY.

SVOS

Bits 14-15: System Stop mode voltage scaling selection These bits control the VCORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance..

AVDEN

Bit 16: Peripheral voltage monitor on VDDA enable.

ALS

Bits 17-18: Analog voltage detector level selection These bits select the voltage threshold detected by the AVD..

AXIRAM1SO

Bit 19: AXIRAM1SO.

AXIRAM2SO

Bit 20: AXIRAM2SO.

AXIRAM3SO

Bit 21: AXIRAM3SO.

AHBRAM1SO

Bit 22: AHBRAM1SO.

AHBRAM2SO

Bit 23: AHBRAM2SO.

ITCMSO

Bit 24: ITCMSO.

GFXSO

Bit 25: GFXSO.

HSITFSO

Bit 26: HSITFSO.

SRDRAMSO

Bit 27: SRDRAMSO.

CSR1

PWR control status register 1

Offset: 0x4, size: 32, reset: 0x00004000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMCVDO
r
AVDO
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACTVOS
r
ACTVOSRDY
r
PVDO
r
Toggle fields

PVDO

Bit 4: Programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. Note: since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set..

ACTVOSRDY

Bit 13: Voltage levels ready bit for currently used VOS and SDLEVEL This bit is set to 1 by hardware when the voltage regulator and the SD converter are both disabled and Bypass mode is selected in PWR control register 3 (PWR_CR3)..

ACTVOS

Bits 14-15: VOS currently applied for VCORE voltage scaling selection. These bits reflect the last VOS value applied to the PMU..

AVDO

Bit 16: Analog voltage detector output on VDDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the AVDEN bit is set..

MMCVDO

Bit 17: MMCVDO.

CR2

This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection.

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

3/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEMPH
r
TEMPL
r
BRRDY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MONEN
rw
BREN
rw
Toggle fields

BREN

Bit 0: Backup regulator enable When set, the Backup regulator (used to maintain the backup RAM content in Standby and VBAT modes) is enabled. If BREN is reset, the backup regulator is switched off. The backup RAM can still be used in Run and Stop modes. However, its content will be lost in Standby and VBAT modes. If BREN is set, the application must wait till the Backup Regulator Ready flag (BRRDY) is set to indicate that the data written into the SRAM will be maintained in Standby and VBAT modes..

MONEN

Bit 4: VBAT and temperature monitoring enable When set, the VBAT supply and temperature monitoring is enabled..

BRRDY

Bit 16: Backup regulator ready This bit is set by hardware to indicate that the Backup regulator is ready..

TEMPL

Bit 22: Temperature level monitoring versus low threshold.

TEMPH

Bit 23: Temperature level monitoring versus high threshold.

CR3

Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value.

Offset: 0xc, size: 32, reset: 0x00000006, access: Unspecified

2/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USB33RDY
r
USBREGEN
rw
USB33DEN
rw
SMPSEXTRDY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VBRS
rw
VBE
rw
SMPSLEVEL
rw
SMPSEXTHP
rw
SMPSEN
rw
LDOEN
rw
BYPASS
rw
Toggle fields

BYPASS

Bit 0: Power management unit bypass.

LDOEN

Bit 1: Low drop-out regulator enable.

SMPSEN

Bit 2: SMPSEN.

SMPSEXTHP

Bit 3: SMPSEXTHP.

SMPSLEVEL

Bits 4-5: SMPSLEVEL.

VBE

Bit 8: VBAT charging enable.

VBRS

Bit 9: VBAT charging resistor selection.

SMPSEXTRDY

Bit 16: SMPSEXTRDY.

USB33DEN

Bit 24: VDD33USB voltage level detector enable..

USBREGEN

Bit 25: USB regulator enable..

USB33RDY

Bit 26: USB supply ready..

CPUCR

This register allows controlling CPU1 power.

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

2/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RUN_SRD
rw
CSSF
rw
SBF
r
STOPF
r
PDDS_SRD
rw
RETDS_CD
rw
Toggle fields

RETDS_CD

Bit 0: RETDS_CD.

PDDS_SRD

Bit 2: PDDS_SRD.

STOPF

Bit 5: STOP flag This bit is set by hardware and cleared only by any reset or by setting the CPU1 CSSF bit..

SBF

Bit 6: System Standby flag This bit is set by hardware and cleared only by a POR (Power-on Reset) or by setting the CPU1 CSSF bit.

CSSF

Bit 9: Clear D1 domain CPU1 Standby, Stop and HOLD flags (always read as 0) This bit is cleared to 0 by hardware..

RUN_SRD

Bit 11: RUN_SRD.

SRDCR

This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software

Offset: 0x18, size: 32, reset: 0x00004000, access: Unspecified

1/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VOS
rw
VOSRDY
r
Toggle fields

VOSRDY

Bit 13: VOS Ready bit for VCORE voltage scaling output selection. This bit is set to 1 by hardware when Bypass mode is selected in PWR control register 3 (PWR_CR3)..

VOS

Bits 14-15: Voltage scaling selection according to performance These bits control the VCORE voltage level and allow to obtains the best trade-off between power consumption and performance: When increasing the performance, the voltage scaling shall be changed before increasing the system frequency. When decreasing performance, the system frequency shall first be decreased before changing the voltage scaling..

WKUPCR

reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared).

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WKUPC6
rw
WKUPC5
rw
WKUPC4
rw
WKUPC3
rw
WKUPC2
rw
WKUPC1
rw
Toggle fields

WKUPC1

Bit 0: Clear Wakeup pin flag for WKUP. These bits are always read as 0..

WKUPC2

Bit 1: Clear Wakeup pin flag for WKUP. These bits are always read as 0..

WKUPC3

Bit 2: Clear Wakeup pin flag for WKUP. These bits are always read as 0..

WKUPC4

Bit 3: Clear Wakeup pin flag for WKUP. These bits are always read as 0..

WKUPC5

Bit 4: Clear Wakeup pin flag for WKUP. These bits are always read as 0..

WKUPC6

Bit 5: Clear Wakeup pin flag for WKUP. These bits are always read as 0..

WKUPFR

reset only by system reset, not reset by wakeup from Standby mode

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WKUPF6
rw
WKUPF5
rw
WKUPF4
rw
WKUPF3
rw
WKUPF2
rw
WKUPF1
rw
Toggle fields

WKUPF1

Bit 0: Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR)..

WKUPF2

Bit 1: Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR)..

WKUPF3

Bit 2: Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR)..

WKUPF4

Bit 3: Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR)..

WKUPF5

Bit 4: Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR)..

WKUPF6

Bit 5: Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR)..

WKUPEPR

Reset only by system reset, not reset by wakeup from Standby mode

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WKUPPUPD6
rw
WKUPPUPD5
rw
WKUPPUPD4
rw
WKUPPUPD3
rw
WKUPPUPD2
rw
WKUPPUPD1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WKUPP6
rw
WKUPP5
rw
WKUPP4
rw
WKUPP3
rw
WKUPP2
rw
WKUPP1
rw
WKUPEN6
rw
WKUPEN5
rw
WKUPEN4
rw
WKUPEN3
rw
WKUPEN2
rw
WKUPEN1
rw
Toggle fields

WKUPEN1

Bit 0: Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge..

WKUPEN2

Bit 1: Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge..

WKUPEN3

Bit 2: Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge..

WKUPEN4

Bit 3: Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge..

WKUPEN5

Bit 4: Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge..

WKUPEN6

Bit 5: Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge..

WKUPP1

Bit 8: Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin..

WKUPP2

Bit 9: Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin..

WKUPP3

Bit 10: Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin..

WKUPP4

Bit 11: Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin..

WKUPP5

Bit 12: Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin..

WKUPP6

Bit 13: Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin..

WKUPPUPD1

Bits 16-17: Wakeup pin pull configuration.

WKUPPUPD2

Bits 18-19: Wakeup pin pull configuration.

WKUPPUPD3

Bits 20-21: Wakeup pin pull configuration.

WKUPPUPD4

Bits 22-23: Wakeup pin pull configuration.

WKUPPUPD5

Bits 24-25: Wakeup pin pull configuration.

WKUPPUPD6

Bits 26-27: Wakeup pin pull configuration for WKUP(truncate(n/2)-7) These bits define the I/O pad pull configuration used when WKUPEN(truncate(n/2)-7) = 1. The associated GPIO port pull configuration shall be set to the same value or to 00. The Wakeup pin pull configuration is kept in Standby mode..

RAMECC

0x52009000: ECC controller is associated to each RAM area

16/59 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 IER
0x20 M1CR
0x24 M1SR
0x28 M1FAR
0x2c M1FDRL
0x30 M1FDRH
0x34 M1FECR
0x40 M2CR
0x44 M2SR
0x48 M2FAR
0x4c M2FDRL
0x50 M2FDRH
0x58 M2FECR
0x60 M3CR
0x64 M3SR
0x68 M3FAR
0x6c M3FDRL
0x70 M3FDRH
0x7c M3FECR
0x80 M4CR
0x84 M4SR
0x88 M4FAR
0x8c M4FDRL
0x90 M4FDRH
0x90 M4FECR
0xa0 M5CR
0xa4 M5SR
0xa8 M5FAR
0xac M5FDRL
0xb0 M5FDRH
0xb4 M5FECR
Toggle registers

IER

RAMECC interrupt enable register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GECCDEBWIE
rw
GECCDEIE
rw
GECCSEIE_
rw
GIE
rw
Toggle fields

GIE

Bit 0: Global interrupt enable.

GECCSEIE_

Bit 1: Global ECC single error interrupt enable.

GECCDEIE

Bit 2: Global ECC double error interrupt enable.

GECCDEBWIE

Bit 3: Global ECC double error on byte write (BW) interrupt enable.

M1CR

RAMECC monitor x configuration register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECCELEN
rw
ECCDEBWIE
rw
ECCDEIE
rw
ECCSEIE
rw
Toggle fields

ECCSEIE

Bit 2: ECC single error interrupt enable.

ECCDEIE

Bit 3: ECC double error interrupt enable.

ECCDEBWIE

Bit 4: ECC double error on byte write (BW) interrupt enable.

ECCELEN

Bit 5: ECC error latching enable.

M1SR

RAMECC monitor x status register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECCELEN
rw
ECCDEBWIE
rw
ECCDEIE
rw
ECCSEIE
rw
Toggle fields

ECCSEIE

Bit 2: ECC single error interrupt enable.

ECCDEIE

Bit 3: ECC double error interrupt enable.

ECCDEBWIE

Bit 4: ECC double error on byte write (BW) interrupt enable.

ECCELEN

Bit 5: ECC error latching enable.

M1FAR

RAMECC monitor x failing address register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECCELEN
rw
ECCDEBWIE
rw
ECCDEIE
rw
ECCSEIE
rw
Toggle fields

ECCSEIE

Bit 2: ECC single error interrupt enable.

ECCDEIE

Bit 3: ECC double error interrupt enable.

ECCDEBWIE

Bit 4: ECC double error on byte write (BW) interrupt enable.

ECCELEN

Bit 5: ECC error latching enable.

M1FDRL

RAMECC monitor x failing data low register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECCELEN
rw
ECCDEBWIE
rw
ECCDEIE
rw
ECCSEIE
rw
Toggle fields

ECCSEIE

Bit 2: ECC single error interrupt enable.

ECCDEIE

Bit 3: ECC double error interrupt enable.

ECCDEBWIE

Bit 4: ECC double error on byte write (BW) interrupt enable.

ECCELEN

Bit 5: ECC error latching enable.

M1FDRH

RAMECC monitor x failing data high register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECCELEN
rw
ECCDEBWIE
rw
ECCDEIE
rw
ECCSEIE
rw
Toggle fields

ECCSEIE

Bit 2: ECC single error interrupt enable.

ECCDEIE

Bit 3: ECC double error interrupt enable.

ECCDEBWIE

Bit 4: ECC double error on byte write (BW) interrupt enable.

ECCELEN

Bit 5: ECC error latching enable.

M1FECR

RAMECC monitor x failing ECC error code register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEBWDF
rw
DEDF
rw
SEDCF
rw
Toggle fields

SEDCF

Bit 0: ECC single error detected and corrected flag.

DEDF

Bit 1: ECC double error detected flag.

DEBWDF

Bit 2: ECC double error on byte write (BW) detected flag.

M2CR

RAMECC monitor x configuration register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEBWDF
rw
DEDF
rw
SEDCF
rw
Toggle fields

SEDCF

Bit 0: ECC single error detected and corrected flag.

DEDF

Bit 1: ECC double error detected flag.

DEBWDF

Bit 2: ECC double error on byte write (BW) detected flag.

M2SR

RAMECC monitor x status register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEBWDF
rw
DEDF
rw
SEDCF
rw
Toggle fields

SEDCF

Bit 0: ECC single error detected and corrected flag.

DEDF

Bit 1: ECC double error detected flag.

DEBWDF

Bit 2: ECC double error on byte write (BW) detected flag.

M2FAR

RAMECC monitor x failing address register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEBWDF
rw
DEDF
rw
SEDCF
rw
Toggle fields

SEDCF

Bit 0: ECC single error detected and corrected flag.

DEDF

Bit 1: ECC double error detected flag.

DEBWDF

Bit 2: ECC double error on byte write (BW) detected flag.

M2FDRL

RAMECC monitor x failing data low register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEBWDF
rw
DEDF
rw
SEDCF
rw
Toggle fields

SEDCF

Bit 0: ECC single error detected and corrected flag.

DEDF

Bit 1: ECC double error detected flag.

DEBWDF

Bit 2: ECC double error on byte write (BW) detected flag.

M2FDRH

RAMECC monitor x failing data high register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FADD
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FADD
r
Toggle fields

FADD

Bits 0-31: ECC error failing address.

M2FECR

RAMECC monitor x failing ECC error code register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FADD
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FADD
r
Toggle fields

FADD

Bits 0-31: ECC error failing address.

M3CR

RAMECC monitor x configuration register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FADD
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FADD
r
Toggle fields

FADD

Bits 0-31: ECC error failing address.

M3SR

RAMECC monitor x status register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FADD
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FADD
r
Toggle fields

FADD

Bits 0-31: ECC error failing address.

M3FAR

RAMECC monitor x failing address register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FADD
rw
Toggle fields

FADD

Bits 0-31: ECC error failing address.

M3FDRL

RAMECC monitor x failing data low register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FDATAL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDATAL
r
Toggle fields

FDATAL

Bits 0-31: Failing data low.

M3FDRH

RAMECC monitor x failing data high register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FDATAL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDATAL
r
Toggle fields

FDATAL

Bits 0-31: Failing data low.

M3FECR

RAMECC monitor x failing ECC error code register

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FDATAL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDATAL
r
Toggle fields

FDATAL

Bits 0-31: Failing data low.

M4CR

RAMECC monitor x configuration register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FDATAL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDATAL
r
Toggle fields

FDATAL

Bits 0-31: Failing data low.

M4SR

RAMECC monitor x status register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FDATAL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDATAL
r
Toggle fields

FDATAL

Bits 0-31: Failing data low.

M4FAR

RAMECC monitor x failing address register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FDATAH
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDATAH
r
Toggle fields

FDATAH

Bits 0-31: Failing data high (64-bit memory).

M4FDRL

RAMECC monitor x failing data low register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FDATAH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDATAH
rw
Toggle fields

FDATAH

Bits 0-31: Failing data high (64-bit memory).

M4FDRH

RAMECC monitor x failing data high register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FDATAH
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDATAH
r
Toggle fields

FDATAH

Bits 0-31: Failing data high (64-bit memory).

M4FECR

RAMECC monitor x failing ECC error code register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FDATAH
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDATAH
r
Toggle fields

FDATAH

Bits 0-31: Failing data high (64-bit memory).

M5CR

RAMECC monitor x configuration register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FEC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEC
r
Toggle fields

FEC

Bits 0-31: Failing error code.

M5SR

RAMECC monitor x status register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FEC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEC
rw
Toggle fields

FEC

Bits 0-31: Failing error code.

M5FAR

RAMECC monitor x failing address register

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FEC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEC
rw
Toggle fields

FEC

Bits 0-31: Failing error code.

M5FDRL

RAMECC monitor x failing data low register

Offset: 0xac, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FEC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEC
r
Toggle fields

FEC

Bits 0-31: Failing error code.

M5FDRH

RAMECC monitor x failing data high register

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FEC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEC
r
Toggle fields

FEC

Bits 0-31: Failing error code.

M5FECR

RAMECC monitor x failing ECC error code register

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FEC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEC
r
Toggle fields

FEC

Bits 0-31: Failing error code.

RCC

0x58024400: Reset and clock control

466/495 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 HSICFGR
0x8 CRRCR
0xc CSICFGR
0x10 CFGR
0x18 CDCFGR1
0x1c CDCFGR2
0x20 SRDCFGR
0x28 PLLCKSELR
0x2c PLLCFGR
0x30 PLL1DIVR
0x34 PLL1FRACR
0x38 PLL2DIVR
0x3c PLL2FRACR
0x40 PLL3DIVR
0x44 PLL3FRACR
0x4c CDCCIPR
0x50 CDCCIP1R
0x54 CDCCIP2R
0x58 SRDCCIPR
0x60 CIER
0x64 CIFR
0x68 CICR
0x70 BDCR
0x74 CSR
0x7c AHB3RSTR
0x80 AHB1RSTR
0x84 AHB2RSTR
0x88 AHB4RSTR
0x8c APB3RSTR
0x90 APB1LRSTR
0x94 APB1HRSTR
0x98 APB2RSTR
0x9c APB4RSTR
0xa0 GCR
0xa8 SRDAMR
0xb0 CKGAENR
0x130 RSR
0x134 AHB3ENR
0x138 AHB1ENR
0x13c AHB2ENR
0x140 AHB4ENR
0x144 APB3ENR
0x148 APB1LENR
0x14c APB1HENR
0x150 APB2ENR
0x154 APB4ENR
0x15c AHB3LPENR
0x160 AHB1LPENR
0x164 AHB2LPENR
0x168 AHB4LPENR
0x16c APB3LPENR
0x170 APB1LLPENR
0x174 APB1HLPENR
0x178 APB2LPENR
0x17c APB4LPENR
Toggle registers

CR

Offset: 0x0, size: 32, reset: 0x00000025, access: Unspecified

22/23 fields covered.

Toggle fields

HSION

Bit 0: HSI clock enable Set and cleared by software. Set by hardware to force the HSI to ON when the product leaves Stop mode, if STOPWUCK = 0 or STOPKERWUCK = 0. Set by hardware to force the HSI to ON when the product leaves Standby mode or in case of a failure of the HSE which is used as the system clock source. This bit cannot be cleared if the HSI is used directly (via SW mux) as system clock, or if the HSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1)..

Allowed values:
0: Off: Clock Off
1: On: Clock On

HSIKERON

Bit 1: HSI clock enable in Stop mode Set and reset by software to force the HSI to ON, even in Stop mode, in order to be quickly available as kernel clock for peripherals. This bit has no effect on the value of HSION..

Allowed values:
0: Off: Clock Off
1: On: Clock On

HSIRDY

Bit 2: HSI clock ready flag Set by hardware to indicate that the HSI oscillator is stable..

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

HSIDIV

Bits 3-4: HSI clock divider Set and reset by software. These bits allow selecting a division ratio in order to configure the wanted HSI clock frequency. The HSIDIV cannot be changed if the HSI is selected as reference clock for at least one enabled PLL (PLLxON bit set to 1). In that case, the new HSIDIV value is ignored..

Allowed values:
0: Div1: No division
1: Div2: Division by 2
2: Div4: Division by 4
3: Div8: Division by 8

HSIDIVF

Bit 5: HSI divider flag Set and reset by hardware. As a write operation to HSIDIV has not an immediate effect on the frequency, this flag indicates the current status of the HSI divider. HSIDIVF goes immediately to 0 when HSIDIV value is changed, and is set back to 1 when the output frequency matches the value programmed into HSIDIV. clock setting is completed).

Allowed values:
0: NotPropagated: New HSIDIV ratio has not yet propagated to hsi_ck
1: Propagated: HSIDIV ratio has propagated to hsi_ck

CSION

Bit 7: CSI clock enable Set and reset by software to enable/disable CSI clock for system and/or peripheral. Set by hardware to force the CSI to ON when the system leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1. This bit cannot be cleared if the CSI is used directly (via SW mux) as system clock, or if the CSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1)..

Allowed values:
0: Off: Clock Off
1: On: Clock On

CSIRDY

Bit 8: CSI clock ready flag Set by hardware to indicate that the CSI oscillator is stable. This bit is activated only if the RC is enabled by CSION (it is not activated if the CSI is enabled by CSIKERON or by a peripheral request)..

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

CSIKERON

Bit 9: CSI clock enable in Stop mode Set and reset by software to force the CSI to ON, even in Stop mode, in order to be quickly available as kernel clock for some peripherals. This bit has no effect on the value of CSION..

Allowed values:
0: Off: Clock Off
1: On: Clock On

HSI48ON

Bit 12: HSI48 clock enable Set by software and cleared by software or by the hardware when the system enters to Stop or Standby mode..

Allowed values:
0: Off: Clock Off
1: On: Clock On

HSI48RDY

Bit 13: HSI48 clock ready flag Set by hardware to indicate that the HSI48 oscillator is stable..

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

CPUCKRDY

Bit 14: CPU related clocks ready flag Set by hardware to indicate that the CPU related clocks (CPU, APB3, AXI bus matrix and related memories) are available..

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

CDCKRDY

Bit 15: CPU domain clocks ready flag Set by hardware to indicate that the following CPU domain clocks are available: APB1, APB2, AHB bus matrix..

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

HSEON

Bit 16: HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE when entering Stop or Standby mode. This bit cannot be cleared if the HSE is used directly (via SW mux) as system clock, or if the HSE is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1)..

Allowed values:
0: Off: Clock Off
1: On: Clock On

HSERDY

Bit 17: HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable..

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

HSEBYP

Bit 18: HSE clock bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled..

Allowed values:
0: NotBypassed: HSE crystal oscillator not bypassed
1: Bypassed: HSE crystal oscillator bypassed with external clock

HSECSSON

Bit 19: HSE clock security system enable Set by software to enable clock security system on HSE. This bit is “set only” (disabled by a system reset or when the system enters in Standby mode). When HSECSSON is set, the clock detector is enabled by hardware when the HSE is ready and disabled by hardware if an oscillator failure is detected..

Allowed values:
0: Off: Clock Off
1: On: Clock On

HSEEXT

Bit 20: external high speed clock type in Bypass mode Set and reset by software to select the external clock type (analog or digital). The external clock must be enabled with the HSEON bit to be used by the device. The HSEEXT bit can be written only if the HSE oscillator is disabled..

PLL1ON

Bit 24: PLL1 enable Set and cleared by software to enable PLL1. Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock..

Allowed values:
0: Off: Clock Off
1: On: Clock On

PLL1RDY

Bit 25: PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked..

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

PLL2ON

Bit 26: PLL2 enable Set and cleared by software to enable PLL2. Cleared by hardware when entering Stop or Standby mode..

Allowed values:
0: Off: Clock Off
1: On: Clock On

PLL2RDY

Bit 27: PLL2 clock ready flag Set by hardware to indicate that the PLL2 is locked..

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

PLL3ON

Bit 28: PLL3 enable Set and cleared by software to enable PLL3. Cleared by hardware when entering Stop or Standby mode..

Allowed values:
0: Off: Clock Off
1: On: Clock On

PLL3RDY

Bit 29: PLL3 clock ready flag Set by hardware to indicate that the PLL3 is locked..

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

HSICFGR

RCC HSI calibration register

Offset: 0x4, size: 32, reset: 0x40000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HSITRIM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSICAL
r
Toggle fields

HSICAL

Bits 0-11: HSI clock calibration Set by hardware by option byte loading during system reset nreset. Adjusted by software through trimming bits HSITRIM. This field represents the sum of engineering option byte calibration value and HSITRIM bits value..

HSITRIM

Bits 24-30: HSI clock trimming Set by software to adjust calibration. HSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_HSI_opt) in order to form the calibration trimming value. HSICAL = HSITRIM + FLASH_HSI_opt. Note: The reset value of the field is 0x40..

Allowed values: 0x0-0x7f

CRRCR

RCC clock recovery RC register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSI48CAL
r
Toggle fields

HSI48CAL

Bits 0-9: Internal RC 48 MHz clock calibration Set by hardware by option byte loading during system reset nreset. Read-only..

CSICFGR

RCC CSI calibration register

Offset: 0xc, size: 32, reset: 0x20000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSITRIM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSICAL
r
Toggle fields

CSICAL

Bits 0-7: CSI clock calibration Set by hardware by option byte loading during system reset nreset. Adjusted by software through trimming bits CSITRIM. This field represents the sum of engineering option byte calibration value and CSITRIM bits value..

CSITRIM

Bits 24-29: CSI clock trimming Set by software to adjust calibration. CSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_CSI_opt) in order to form the calibration trimming value. CSICAL = CSITRIM + FLASH_CSI_opt. Note: The reset value of the field is 0x20..

Allowed values: 0x0-0x3f

CFGR

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCO2
rw
MCO2PRE
rw
MCO1
rw
MCO1PRE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMPRE
rw
RTCPRE
rw
STOPKERWUCK
rw
STOPWUCK
rw
SWS
r
SW
rw
Toggle fields

SW

Bits 0-2: system clock and trace clock switch Set and reset by software to select system clock and trace clock sources (sys_ck and traceclk). Set by hardware in order to: force the selection of the HSI or CSI (depending on STOPWUCK selection) when leaving a system Stop mode force the selection of the HSI in case of failure of the HSE when used directly or indirectly as system clock others: reserved.

Allowed values:
0: HSI: HSI selected as system clock
1: CSI: CSI selected as system clock
2: HSE: HSE selected as system clock
3: PLL1: PLL1 selected as system clock

SWS

Bits 3-5: system clock switch status Set and reset by hardware to indicate which clock source is used as system clock. others: reserved.

Allowed values:
0: HSI: HSI oscillator used as system clock
1: CSI: CSI oscillator used as system clock
2: HSE: HSE oscillator used as system clock
3: PLL1: PLL1 used as system clock

STOPWUCK

Bit 6: system clock selection after a wake up from system Stop Set and reset by software to select the system wakeup clock from system Stop. The selected clock is also used as emergency clock for the clock security system (CSS) on HSE. See for details. STOPWUCK must not be modified when CSS is enabled (by HSECSSON bit) and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW =10)..

Allowed values:
0: HSI: HSI selected as wake up clock from system Stop
1: CSI: CSI selected as wake up clock from system Stop

STOPKERWUCK

Bit 7: kernel clock selection after a wake up from system Stop Set and reset by software to select the kernel wakeup clock from system Stop. See for details..

Allowed values:
0: HSI: HSI selected as wake up clock from system Stop
1: CSI: CSI selected as wake up clock from system Stop

RTCPRE

Bits 8-13: HSE division factor for RTC clock Set and cleared by software to divide the HSE to generate a clock for RTC. Caution: The software must set these bits correctly to ensure that the clock supplied to the RTC is lower than 1 MHz. These bits must be configured if needed before selecting the RTC clock source. ....

Allowed values: 0x0-0x3f

TIMPRE

Bit 15: timers clocks prescaler selection This bit is set and reset by software to control the clock frequency of all the timers connected to APB1 and APB2 domains. Refer to for more details..

Allowed values:
0: DefaultX2: Timer kernel clock equal to 2x pclk by default
1: DefaultX4: Timer kernel clock equal to 4x pclk by default

MCO1PRE

Bits 18-21: MCO1 prescaler Set and cleared by software to configure the prescaler of the MCO1. Modification of this prescaler may generate glitches on MCO1. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs. ....

Allowed values: 0x0-0xf

MCO1

Bits 22-24: Microcontroller clock output 1 Set and cleared by software. Clock source selection may generate glitches on MCO1. It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs. others: reserved.

Allowed values:
0: HSI: HSI selected for micro-controller clock output
1: LSE: LSE selected for micro-controller clock output
2: HSE: HSE selected for micro-controller clock output
3: PLL1_Q: pll1_q selected for micro-controller clock output
4: HSI48: HSI48 selected for micro-controller clock output

MCO2PRE

Bits 25-28: MCO2 prescaler Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs. ....

Allowed values: 0x0-0xf

MCO2

Bits 29-31: microcontroller clock output 2 Set and cleared by software. Clock source selection may generate glitches on MCO2. It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs. others: reserved.

Allowed values:
0: SYSCLK: System clock selected for micro-controller clock output
1: PLL2_P: pll2_p selected for micro-controller clock output
2: HSE: HSE selected for micro-controller clock output
3: PLL1_P: pll1_p selected for micro-controller clock output
4: CSI: CSI selected for micro-controller clock output
5: LSI: LSI selected for micro-controller clock output

CDCFGR1

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CDCPRE
rw
CDPPRE
rw
HPRE
rw
Toggle fields

HPRE

Bits 0-3: CPU domain AHB prescaler Set and reset by software to control the division factor of rcc_hclk3 and rcc_aclk. Changing this division ratio has an impact on the frequency of all bus matrix clocks. 0xxx: rcc_hclk3 = sys_cdcpre_ck (default after reset) Note: The clocks are divided by the new prescaler factor from1 to 16 periods of the slowest APB clock among rcc_pclk[4:1] after HPRE update. Note: Note also that rcc_hclk3 = rcc_aclk..

Allowed values:
8: Div2: sys_ck divided by 2
9: Div4: sys_ck divided by 4
10: Div8: sys_ck divided by 8
11: Div16: sys_ck divided by 16
12: Div64: sys_ck divided by 64
13: Div128: sys_ck divided by 128
14: Div256: sys_ck divided by 256
15: Div512: sys_ck divided by 512
0 (+): Div1: sys_ck not divided

CDPPRE

Bits 4-6: CPU domain APB3 prescaler Set and reset by software to control the division factor of rcc_pclk3. The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk3 after CDPPRE write. 0xx: rcc_pclk3 = rcc_hclk3 (default after reset).

Allowed values:
4: Div2: rcc_hclk divided by 2
5: Div4: rcc_hclk divided by 4
6: Div8: rcc_hclk divided by 8
7: Div16: rcc_hclk divided by 16
0 (+): Div1: rcc_hclk not divided

CDCPRE

Bits 8-11: CPU domain core prescaler Set and reset by software to control the CPU domain CPU clock division factor. Changing this division ratio has an impact on the frequency of the CPU clock and all bus matrix clocks. After changing this prescaler value, it takes up to 16 periods of the slowest APB clock before the new division ratio is taken into account. The application can check if the new division factor is taken into account by reading back this register. 0xxx: sys_ck not divided (default after reset).

Allowed values:
8: Div2: sys_ck divided by 2
9: Div4: sys_ck divided by 4
10: Div8: sys_ck divided by 8
11: Div16: sys_ck divided by 16
12: Div64: sys_ck divided by 64
13: Div128: sys_ck divided by 128
14: Div256: sys_ck divided by 256
15: Div512: sys_ck divided by 512
0 (+): Div1: sys_ck not divided

CDCFGR2

Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CDPPRE2
rw
CDPPRE1
rw
Toggle fields

CDPPRE1

Bits 4-6: CPU domain APB1 prescaler Set and reset by software to control the CPU domain APB1 clock division factor. The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk1 after CDPPRE1 write. 0xx: rcc_pclk1 = rcc_hclk1 (default after reset).

Allowed values:
4: Div2: rcc_hclk divided by 2
5: Div4: rcc_hclk divided by 4
6: Div8: rcc_hclk divided by 8
7: Div16: rcc_hclk divided by 16
0 (+): Div1: rcc_hclk not divided

CDPPRE2

Bits 8-10: CPU domain APB2 prescaler Set and reset by software to control the CPU domain APB2 clock division factor. The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk1 after CDPPRE2 write. 0xx: rcc_pclk2 = rcc_hclk1 (default after reset).

Allowed values:
4: Div2: rcc_hclk divided by 2
5: Div4: rcc_hclk divided by 4
6: Div8: rcc_hclk divided by 8
7: Div16: rcc_hclk divided by 16
0 (+): Div1: rcc_hclk not divided

SRDCFGR

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRDPPRE
rw
Toggle fields

SRDPPRE

Bits 4-6: SmartRun domain APB4 prescaler Set and reset by software to control the SmartRun domain APB4 clock division factor. The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk4 after SRDPPRE write. 0xx: rcc_pclk4 = rcc_hclk4 (default after reset).

PLLCKSELR

Offset: 0x28, size: 32, reset: 0x02020200, access: Unspecified

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIVM3
rw
DIVM2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIVM2
rw
DIVM1
rw
PLLSRC
rw
Toggle fields

PLLSRC

Bits 0-1: DIVMx and PLLs clock source selection Set and reset by software to select the PLL clock source. These bits can be written only when all PLLs are disabled. In order to save power, when no PLL is used, the value of PLLSRC must be set to '11’..

Allowed values:
0: HSI: HSI selected as PLL clock
1: CSI: CSI selected as PLL clock
2: HSE: HSE selected as PLL clock
3: None: No clock sent to DIVMx dividers and PLLs

DIVM1

Bits 4-9: prescaler for PLL1 Set and cleared by software to configure the prescaler of the PLL1. The hardware does not allow any modification of this prescaler when PLL1 is enabled (PLL1ON = 1). In order to save power when PLL1 is not used, the value of DIVM1 must be set to 0. ... ....

Allowed values: 0x0-0x3f

DIVM2

Bits 12-17: prescaler for PLL2 Set and cleared by software to configure the prescaler of the PLL2. The hardware does not allow any modification of this prescaler when PLL2 is enabled (PLL2ON = 1). In order to save power when PLL2 is not used, the value of DIVM2 must be set to 0. ... ....

Allowed values: 0x0-0x3f

DIVM3

Bits 20-25: prescaler for PLL3 Set and cleared by software to configure the prescaler of the PLL3. The hardware does not allow any modification of this prescaler when PLL3 is enabled (PLL3ON = 1). In order to save power when PLL3 is not used, the value of DIVM3 must be set to 0. ... ....

Allowed values: 0x0-0x3f

PLLCFGR

Offset: 0x2c, size: 32, reset: 0x01FF0000, access: Unspecified

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIVR3EN
rw
DIVQ3EN
rw
DIVP3EN
rw
DIVR2EN
rw
DIVQ2EN
rw
DIVP2EN
rw
DIVR1EN
rw
DIVQ1EN
rw
DIVP1EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL3RGE
rw
PLL3VCOSEL
rw
PLL3FRACEN
rw
PLL2RGE
rw
PLL2VCOSEL
rw
PLL2FRACEN
rw
PLL1RGE
rw
PLL1VCOSEL
rw
PLL1FRACEN
rw
Toggle fields

PLL1FRACEN

Bit 0: PLL1 fractional latch enable Set and reset by software to latch the content of FRACN1 into the sigma-delta modulator. In order to latch the FRACN1 value into the sigma-delta modulator, PLL1FRACEN must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN1 into the modulator. Refer to for additional information..

Allowed values:
0: Reset: Reset latch to tranfer FRACN to the Sigma-Delta modulator
1: Set: Set latch to tranfer FRACN to the Sigma-Delta modulator

PLL1VCOSEL

Bit 1: PLL1 VCO selection Set and reset by software to select the proper VCO frequency range used for PLL1. These bits must be written before enabling the PLL1..

Allowed values:
0: WideVCO: VCO frequency range 192 to 836 MHz
1: MediumVCO: VCO frequency range 150 to 420 MHz

PLL1RGE

Bits 2-3: PLL1 input frequency range Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1..

Allowed values:
0: Range1: Frequency is between 1 and 2 MHz
1: Range2: Frequency is between 2 and 4 MHz
2: Range4: Frequency is between 4 and 8 MHz
3: Range8: Frequency is between 8 and 16 MHz

PLL2FRACEN

Bit 4: PLL2 fractional latch enable Set and reset by software to latch the content of FRACN2 into the sigma-delta modulator. In order to latch the FRACN2 value into the sigma-delta modulator, PLL2FRACEN must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN2 into the modulator. Refer to for additional information..

Allowed values:
0: Reset: Reset latch to tranfer FRACN to the Sigma-Delta modulator
1: Set: Set latch to tranfer FRACN to the Sigma-Delta modulator

PLL2VCOSEL

Bit 5: PLL2 VCO selection Set and reset by software to select the proper VCO frequency range used for PLL2. This bit must be written before enabling the PLL2..

Allowed values:
0: WideVCO: VCO frequency range 192 to 836 MHz
1: MediumVCO: VCO frequency range 150 to 420 MHz

PLL2RGE

Bits 6-7: PLL2 input frequency range Set and reset by software to select the proper reference frequency range used for PLL2. These bits must be written before enabling the PLL2..

Allowed values:
0: Range1: Frequency is between 1 and 2 MHz
1: Range2: Frequency is between 2 and 4 MHz
2: Range4: Frequency is between 4 and 8 MHz
3: Range8: Frequency is between 8 and 16 MHz

PLL3FRACEN

Bit 8: PLL3 fractional latch enable Set and reset by software to latch the content of FRACN3 into the sigma-delta modulator. In order to latch the FRACN3 value into the sigma-delta modulator, PLL3FRACEN must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN3 into the modulator. Refer to for additional information..

Allowed values:
0: Reset: Reset latch to tranfer FRACN to the Sigma-Delta modulator
1: Set: Set latch to tranfer FRACN to the Sigma-Delta modulator

PLL3VCOSEL

Bit 9: PLL3 VCO selection Set and reset by software to select the proper VCO frequency range used for PLL3. This bit must be written before enabling the PLL3..

Allowed values:
0: WideVCO: VCO frequency range 192 to 836 MHz
1: MediumVCO: VCO frequency range 150 to 420 MHz

PLL3RGE

Bits 10-11: PLL3 input frequency range Set and reset by software to select the proper reference frequency range used for PLL3. These bits must be written before enabling the PLL3..

Allowed values:
0: Range1: Frequency is between 1 and 2 MHz
1: Range2: Frequency is between 2 and 4 MHz
2: Range4: Frequency is between 4 and 8 MHz
3: Range8: Frequency is between 8 and 16 MHz

DIVP1EN

Bit 16: PLL1 DIVP divider output enable Set and reset by software to enable the pll1_p_ck output of the PLL1. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). In order to save power, when the pll1_p_ck output of the PLL1 is not used, the pll1_p_ck must be disabled..

Allowed values:
0: Disabled: Clock ouput is disabled
1: Enabled: Clock output is enabled

DIVQ1EN

Bit 17: PLL1 DIVQ divider output enable Set and reset by software to enable the pll1_q_ck output of the PLL1. In order to save power, when the pll1_q_ck output of the PLL1 is not used, the pll1_q_ck must be disabled. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)..

Allowed values:
0: Disabled: Clock ouput is disabled
1: Enabled: Clock output is enabled

DIVR1EN

Bit 18: PLL1 DIVR divider output enable Set and reset by software to enable the pll1_r_ck output of the PLL1. To save power, DIVR3EN and DIVR3 bits must be set to 0 when the pll3_r_ck is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)..

Allowed values:
0: Disabled: Clock ouput is disabled
1: Enabled: Clock output is enabled

DIVP2EN

Bit 19: PLL2 DIVP divider output enable Set and reset by software to enable the pll2_p_ck output of the PLL2. This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). To save power, DIVR3EN and DIVR3 bits must be set to 0 when the pll3_r_ck is not used..

Allowed values:
0: Disabled: Clock ouput is disabled
1: Enabled: Clock output is enabled

DIVQ2EN

Bit 20: PLL2 DIVQ divider output enable Set and reset by software to enable the pll2_q_ck output of the PLL2. To save power, DIVR3EN and DIVR3 bits must be set to 0 when the pll3_r_ck is not used. This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0)..

Allowed values:
0: Disabled: Clock ouput is disabled
1: Enabled: Clock output is enabled

DIVR2EN

Bit 21: PLL2 DIVR divider output enable Set and reset by software to enable the pll2_r_ck output of the PLL2. To save power, DIVR3EN and DIVR3 bits must be set to 0 when the pll3_r_ck is not used. This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0)..

Allowed values:
0: Disabled: Clock ouput is disabled
1: Enabled: Clock output is enabled

DIVP3EN

Bit 22: PLL3 DIVP divider output enable Set and reset by software to enable the pll3_p_ck output of the PLL3. This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). To save power, DIVR3EN and DIVR3 bits must be set to 0 when the pll3_r_ck is not used..

Allowed values:
0: Disabled: Clock ouput is disabled
1: Enabled: Clock output is enabled

DIVQ3EN

Bit 23: PLL3 DIVQ divider output enable Set and reset by software to enable the pll3_q_ck output of the PLL3. To save power, DIVR3EN and DIVR3 bits must be set to 0 when the pll3_r_ck is not used. This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0)..

Allowed values:
0: Disabled: Clock ouput is disabled
1: Enabled: Clock output is enabled

DIVR3EN

Bit 24: PLL3 DIVR divider output enable Set and reset by software to enable the pll3_r_ck output of the PLL3. To save power, DIVR3EN and DIVR3 bits must be set to 0 when the pll3_r_ck is not used. This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0)..

Allowed values:
0: Disabled: Clock ouput is disabled
1: Enabled: Clock output is enabled

PLL1DIVR

Offset: 0x30, size: 32, reset: 0x01010280, access: Unspecified

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIVR1
rw
DIVQ1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIVP1
rw
DIVN1
rw
Toggle fields

DIVN1

Bits 0-8: multiplication factor for PLL1 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL1ON = PLL1RDY = 0). ..........: not used ... ... Others: wrong configurations The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is: 128 to 560 MHz if PLL1VCOSEL = 0 150 to 420 MHz if PLL1VCOSEL = 1 VCO output frequency = Fref1_ck x DIVN1, when fractional value 0 has been loaded into FRACN1, with: DIVN1 between 8 and 420 The input frequency Fref1_ck must be between 1 and 16 MHz..

Allowed values: 0x3-0x1ff

DIVP1

Bits 9-15: PLL1 DIVP division factor Set and reset by software to control the frequency of the pll1_p_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). Note that odd division factors are not allowed. ....

Allowed values:
0: Div1: pll_p_ck = vco_ck
1: Div2: pll_p_ck = vco_ck / 2
3: Div4: pll_p_ck = vco_ck / 4
5: Div6: pll_p_ck = vco_ck / 6
7: Div8: pll_p_ck = vco_ck / 8
9: Div10: pll_p_ck = vco_ck / 10
11: Div12: pll_p_ck = vco_ck / 12
13: Div14: pll_p_ck = vco_ck / 14
15: Div16: pll_p_ck = vco_ck / 16
17: Div18: pll_p_ck = vco_ck / 18
19: Div20: pll_p_ck = vco_ck / 20
21: Div22: pll_p_ck = vco_ck / 22
23: Div24: pll_p_ck = vco_ck / 24
25: Div26: pll_p_ck = vco_ck / 26
27: Div28: pll_p_ck = vco_ck / 28
29: Div30: pll_p_ck = vco_ck / 30
31: Div32: pll_p_ck = vco_ck / 32
33: Div34: pll_p_ck = vco_ck / 34
35: Div36: pll_p_ck = vco_ck / 36
37: Div38: pll_p_ck = vco_ck / 38
39: Div40: pll_p_ck = vco_ck / 40
41: Div42: pll_p_ck = vco_ck / 42
43: Div44: pll_p_ck = vco_ck / 44
45: Div46: pll_p_ck = vco_ck / 46
47: Div48: pll_p_ck = vco_ck / 48
49: Div50: pll_p_ck = vco_ck / 50
51: Div52: pll_p_ck = vco_ck / 52
53: Div54: pll_p_ck = vco_ck / 54
55: Div56: pll_p_ck = vco_ck / 56
57: Div58: pll_p_ck = vco_ck / 58
59: Div60: pll_p_ck = vco_ck / 60
61: Div62: pll_p_ck = vco_ck / 62
63: Div64: pll_p_ck = vco_ck / 64
65: Div66: pll_p_ck = vco_ck / 66
67: Div68: pll_p_ck = vco_ck / 68
69: Div70: pll_p_ck = vco_ck / 70
71: Div72: pll_p_ck = vco_ck / 72
73: Div74: pll_p_ck = vco_ck / 74
75: Div76: pll_p_ck = vco_ck / 76
77: Div78: pll_p_ck = vco_ck / 78
79: Div80: pll_p_ck = vco_ck / 80
81: Div82: pll_p_ck = vco_ck / 82
83: Div84: pll_p_ck = vco_ck / 84
85: Div86: pll_p_ck = vco_ck / 86
87: Div88: pll_p_ck = vco_ck / 88
89: Div90: pll_p_ck = vco_ck / 90
91: Div92: pll_p_ck = vco_ck / 92
93: Div94: pll_p_ck = vco_ck / 94
95: Div96: pll_p_ck = vco_ck / 96
97: Div98: pll_p_ck = vco_ck / 98
99: Div100: pll_p_ck = vco_ck / 100
101: Div102: pll_p_ck = vco_ck / 102
103: Div104: pll_p_ck = vco_ck / 104
105: Div106: pll_p_ck = vco_ck / 106
107: Div108: pll_p_ck = vco_ck / 108
109: Div110: pll_p_ck = vco_ck / 110
111: Div112: pll_p_ck = vco_ck / 112
113: Div114: pll_p_ck = vco_ck / 114
115: Div116: pll_p_ck = vco_ck / 116
117: Div118: pll_p_ck = vco_ck / 118
119: Div120: pll_p_ck = vco_ck / 120
121: Div122: pll_p_ck = vco_ck / 122
123: Div124: pll_p_ck = vco_ck / 124
125: Div126: pll_p_ck = vco_ck / 126
127: Div128: pll_p_ck = vco_ck / 128

DIVQ1

Bits 16-22: PLL1 DIVQ division factor Set and reset by software to control the frequency of the pll1_q_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ....

Allowed values: 0x0-0x7f

DIVR1

Bits 24-30: PLL1 DIVR division factor Set and reset by software to control the frequency of the pll1_r_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ....

Allowed values: 0x0-0x7f

PLL1FRACR

Offset: 0x34, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FRACN1
rw
Toggle fields

FRACN1

Bits 3-15: fractional part of the multiplication factor for PLL1 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO. The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is: 128 to 560 MHz if PLL1VCOSEL = 0 150 to 420 MHz if PLL1VCOSEL = 1 VCO output frequency = Fref1_ck x (DIVN1 + (FRACN1 / 213)), with DIVN1 between 8 and 420 FRACN1 can be between 0 and 213- 1 The input frequency Fref1_ck must be between 1 and 16 MHz. To change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: Set the bit PLL1FRACEN to 0. Write the new fractional value into FRACN1. Set the bit PLL1FRACEN to 1..

Allowed values: 0x0-0x1fff

PLL2DIVR

Offset: 0x38, size: 32, reset: 0x01010280, access: Unspecified

3/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIVR2
rw
DIVQ2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIVP2
rw
DIVN2
rw
Toggle fields

DIVN2

Bits 0-8: multiplication factor for PLL2 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL2ON = PLL2RDY = 0). ..........: not used ... ... Others: wrong configurations The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is: 128 to 560 MHz if PLL2VCOSEL = 0 150 to 420 MHz if PLL2VCOSEL = 1 VCO output frequency = Fref2_ck x DIVN2, when fractional value 0 has been loaded into FRACN2, with DIVN2 between 8 and 420 The input frequency Fref2_ck must be between 1 and 16MHz..

Allowed values: 0x3-0x1ff

DIVP2

Bits 9-15: PLL2 DIVP division factor Set and reset by software to control the frequency of the pll2_p_ck clock. These bits can be written only when the PLL2 is disabled (PLL2ON = PLL2RDY = 0). ....

DIVQ2

Bits 16-22: PLL2 DIVQ division factor Set and reset by software to control the frequency of the pll2_q_ck clock. These bits can be written only when the PLL2 is disabled (PLL2ON = PLL2RDY = 0). ....

Allowed values: 0x0-0x7f

DIVR2

Bits 24-30: PLL2 DIVR division factor Set and reset by software to control the frequency of the pll2_r_ck clock. These bits can be written only when the PLL2 is disabled (PLL2ON = PLL2RDY = 0). ....

Allowed values: 0x0-0x7f

PLL2FRACR

Offset: 0x3c, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FRACN2
rw
Toggle fields

FRACN2

Bits 3-15: fractional part of the multiplication factor for PLL2 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO. The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is: 128 to 560 MHz if PLL2VCOSEL = 0 150 to 420 MHz if PLL2VCOSEL = 1 VCO output frequency = Fref2_ck x (DIVN2 + (FRACN2 / 213)), with DIVN2 between 8 and 420 FRACN2 can be between 0 and 213 - 1 The input frequency Fref2_ck must be between 1 and 16 MHz. In order to change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: Set the bit PLL2FRACEN to 0. Write the new fractional value into FRACN2. Set the bit PLL2FRACEN to 1..

Allowed values: 0x0-0x1fff

PLL3DIVR

Offset: 0x40, size: 32, reset: 0x01010280, access: Unspecified

3/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIVR3
rw
DIVQ3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIVP3
rw
DIVN3
rw
Toggle fields

DIVN3

Bits 0-8: Multiplication factor for PLL3 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL3ON = PLL3RDY = 0). ...........: not used ... ... Others: wrong configurations The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is: 128 to 560 MHz if PLL3VCOSEL = 0 150 to 420 MHz if PLL3VCOSEL = 1 VCO output frequency = Fref3_ck x DIVN3, when fractional value 0 has been loaded into FRACN3, with: DIVN3 between 8 and 420 The input frequency Fref3_ck must be between 1 and 16MHz.

Allowed values: 0x3-0x1ff

DIVP3

Bits 9-15: PLL3 DIVP division factor Set and reset by software to control the frequency of the pll3_p_ck clock. These bits can be written only when the PLL3 is disabled (PLL3ON = PLL3RDY = 0). ....

DIVQ3

Bits 16-22: PLL3 DIVQ division factor Set and reset by software to control the frequency of the pll3_q_ck clock. These bits can be written only when the PLL3 is disabled (PLL3ON = PLL3RDY = 0). ....

Allowed values: 0x0-0x7f

DIVR3

Bits 24-30: PLL3 DIVR division factor Set and reset by software to control the frequency of the pll3_r_ck clock. These bits can be written only when the PLL3 is disabled (PLL3ON = PLL3RDY = 0). ....

Allowed values: 0x0-0x7f

PLL3FRACR

Offset: 0x44, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FRACN3
rw
Toggle fields

FRACN3

Bits 3-15: fractional part of the multiplication factor for PLL3 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO. The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is: 128 to 560 MHz if PLL3VCOSEL = 0 150 to 420 MHz if PLL3VCOSEL = 1 VCO output frequency = Fref3_ck x (DIVN3 + (FRACN3 / 213)), with DIVN3 between 8 and 420 FRACN3 can be between 0 and 213 - 1 The input frequency Fref3_ck must be between 1 and 16 MHz. In order to change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: Set the bit PLL1FRACEN to 0. Write the new fractional value into FRACN1. Set the bit PLL1FRACEN to 1..

Allowed values: 0x0-0x1fff

CDCCIPR

RCC CPU domain kernel clock configuration register

Offset: 0x4c, size: 32, reset: 0x00000000, access: Unspecified

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CKPERSEL
rw
SDMMCSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTOSPISEL
rw
FMCSEL
rw
Toggle fields

FMCSEL

Bits 0-1: FMC kernel clock source selection.

Allowed values:
0: RCC_HCLK3: rcc_hclk3 selected as peripheral clock
1: PLL1_Q: pll1_q selected as peripheral clock
2: PLL2_R: pll2_r selected as peripheral clock
3: PER: PER selected as peripheral clock

OCTOSPISEL

Bits 4-5: OCTOSPI kernel clock source selection.

Allowed values:
0: RCC_HCLK3: rcc_hclk3 selected as peripheral clock
1: PLL1_Q: pll1_q selected as peripheral clock
2: PLL2_R: pll2_r selected as peripheral clock
3: PER: PER selected as peripheral clock

SDMMCSEL

Bit 16: SDMMC kernel clock source selection.

Allowed values:
0: PLL1_Q: pll1_q selected as peripheral clock
1: PLL2_R: pll2_r selected as peripheral clock

CKPERSEL

Bits 28-29: per_ck clock source selection.

Allowed values:
0: HSI: HSI selected as peripheral clock
1: CSI: CSI selected as peripheral clock
2: HSE: HSE selected as peripheral clock

CDCCIP1R

RCC CPU domain kernel clock configuration register

Offset: 0x50, size: 32, reset: 0x00000000, access: Unspecified

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWPMISEL
rw
FDCANSEL
rw
DFSDM1SEL
rw
SPDIFRXSEL
rw
SPI45SEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI123SEL
rw
SAI2BSEL
rw
SAI2ASEL
rw
SAI1SEL
rw
Toggle fields

SAI1SEL

Bits 0-2: SAI1 and DFSDM1 kernel Aclk clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it isnot be possible to switch to another clock. Refer to for additional information. Note: DFSDM1 clock source selection is done by DFSDM1SEL. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin..

Allowed values:
0: PLL1_Q: pll1_q selected as peripheral clock
1: PLL2_P: pll2_p selected as peripheral clock
2: PLL3_P: pll3_p selected as peripheral clock
3: I2S_CKIN: I2S_CKIN selected as peripheral clock
4: PER: PER selected as peripheral clock

SAI2ASEL

Bits 6-8: SAI2 kernel clock source A selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not be possible to switch to another clock. Refer to for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. spdifrx_symb_ck is the symbol clock generated by the SPDIFRX (see )..

Allowed values:
0: PLL1_Q: pll1_q selected as peripheral clock
1: PLL2_P: pll2_p selected as peripheral clock
2: PLL3_P: pll3_p selected as peripheral clock
3: I2S_CKIN: i2s_ckin selected as peripheral clock
4: PER: PER selected as peripheral clock

SAI2BSEL

Bits 9-11: SAI2 kernel clock B source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not be possible to switch to another clock. Refer to for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. spdifrx_symb_ck is the symbol clock generated by the spdifrx (see )..

Allowed values:
0: PLL1_Q: pll1_q selected as peripheral clock
1: PLL2_P: pll2_p selected as peripheral clock
2: PLL3_P: pll3_p selected as peripheral clock
3: I2S_CKIN: i2s_ckin selected as peripheral clock
4: PER: PER selected as peripheral clock

SPI123SEL

Bits 12-14: SPI/I2S1,2 and 3 kernel clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not be possible to switch to another clock. Refer to for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin..

Allowed values:
0: PLL1_Q: pll1_q selected as peripheral clock
1: PLL2_P: pll2_p selected as peripheral clock
2: PLL3_P: pll3_p selected as peripheral clock
3: I2S_CKIN: I2S_CKIN selected as peripheral clock
4: PER: PER selected as peripheral clock

SPI45SEL

Bits 16-18: SPI4 and 5 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.

Allowed values:
0: APB: APB clock selected as peripheral clock
1: PLL2_Q: pll2_q selected as peripheral clock
2: PLL3_Q: pll3_q selected as peripheral clock
3: HSI_KER: hsi_ker selected as peripheral clock
4: CSI_KER: csi_ker selected as peripheral clock
5: HSE: HSE selected as peripheral clock

SPDIFRXSEL

Bits 20-21: SPDIFRX kernel clock source selection.

Allowed values:
0: PLL1_Q: pll1_q selected as peripheral clock
1: PLL2_R: pll2_r selected as peripheral clock
2: PLL3_R: pll3_r selected as peripheral clock
3: HSI_KER: hsi_ker selected as peripheral clock

DFSDM1SEL

Bit 24: DFSDM1 kernel clock Clk source selection Set and reset by software. Note: the DFSDM1 Aclk clock source selection is done by SAI1SEL (see )..

Allowed values:
0: RCC_PCLK2: rcc_pclk2 selected as peripheral clock
1: SYS: System clock selected as peripheral clock

FDCANSEL

Bits 28-29: FDCAN kernel clock source selection Set and reset by software..

Allowed values:
0: HSE: HSE selected as peripheral clock
1: PLL1_Q: pll1_q selected as peripheral clock
2: PLL2_Q: pll2_q selected as peripheral clock

SWPMISEL

Bit 31: SWPMI kernel clock source selection Set and reset by software..

Allowed values:
0: PCLK: pclk selected as peripheral clock
1: HSI_KER: hsi_ker selected as peripheral clock

CDCCIP2R

RCC CPU domain kernel clock configuration register

Offset: 0x54, size: 32, reset: 0x00000000, access: Unspecified

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1SEL
rw
CECSEL
rw
USBSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2C123SEL
rw
RNGSEL
rw
USART16910SEL
rw
USART234578SEL
rw
Toggle fields

USART234578SEL

Bits 0-2: USART2/3, UART4,5, 7 and 8 (APB1) kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.

Allowed values:
0: RCC_PCLK1: rcc_pclk1 selected as peripheral clock
1: PLL2_Q: pll2_q selected as peripheral clock
2: PLL3_Q: pll3_q selected as peripheral clock
3: HSI_KER: hsi_ker selected as peripheral clock
4: CSI_KER: csi_ker selected as peripheral clock
5: LSE: LSE selected as peripheral clock

USART16910SEL

Bits 3-5: USART1, 6, 9 and 10 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.

Allowed values:
0: RCC_PCLK2: rcc_pclk2 selected as peripheral clock
1: PLL2_Q: pll2_q selected as peripheral clock
2: PLL3_Q: pll3_q selected as peripheral clock
3: HSI_KER: hsi_ker selected as peripheral clock
4: CSI_KER: csi_ker selected as peripheral clock
5: LSE: LSE selected as peripheral clock

RNGSEL

Bits 8-9: RNG kernel clock source selection Set and reset by software..

Allowed values:
0: HSI48: HSI48 selected as peripheral clock
1: PLL1_Q: pll1_q selected as peripheral clock
2: LSE: LSE selected as peripheral clock
3: LSI: LSI selected as peripheral clock

I2C123SEL

Bits 12-13: I2C1,2,3 kernel clock source selection Set and reset by software..

Allowed values:
0: RCC_PCLK1: rcc_pclk1 selected as peripheral clock
1: PLL3_R: pll3_r selected as peripheral clock
2: HSI_KER: hsi_ker selected as peripheral clock
3: CSI_KER: csi_ker selected as peripheral clock

USBSEL

Bits 20-21: USBOTG 1 and 2 kernel clock source selection Set and reset by software..

Allowed values:
0: DISABLE: Disable the kernel clock
1: PLL1_Q: pll1_q selected as peripheral clock
2: PLL3_Q: pll3_q selected as peripheral clock
3: HSI48: HSI48 selected as peripheral clock

CECSEL

Bits 22-23: HDMI-CEC kernel clock source selection Set and reset by software..

Allowed values:
0: LSE: LSE selected as peripheral clock
1: LSI: LSI selected as peripheral clock
2: CSI_KER: csi_ker selected as peripheral clock

LPTIM1SEL

Bits 28-30: LPTIM1 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.

Allowed values:
0: RCC_PCLK1: rcc_pclk1 selected as peripheral clock
1: PLL2_P: pll2_p selected as peripheral clock
2: PLL3_R: pll3_r selected as peripheral clock
3: LSE: LSE selected as peripheral clock
4: LSI: LSI selected as peripheral clock
5: PER: PER selected as peripheral clock

SRDCCIPR

RCC SmartRun domain kernel clock configuration register

Offset: 0x58, size: 32, reset: 0x00000000, access: Unspecified

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPI6SEL
rw
DFSDM2SEL
rw
ADCSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPTIM3SEL
rw
LPTIM2SEL
rw
I2C4SEL
rw
LPUART1SEL
rw
Toggle fields

LPUART1SEL

Bits 0-2: LPUART1 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.

Allowed values:
0: RCC_PCLK_D3: rcc_pclk_d3 selected as peripheral clock
1: PLL2_Q: pll2_q selected as peripheral clock
2: PLL3_Q: pll3_q selected as peripheral clock
3: HSI_KER: hsi_ker selected as peripheral clock
4: CSI_KER: csi_ker selected as peripheral clock
5: LSE: LSE selected as peripheral clock

I2C4SEL

Bits 8-9: I2C4 kernel clock source selection Set and reset by software..

Allowed values:
0: RCC_PCLK4: rcc_pclk4 selected as peripheral clock
1: PLL3_R: pll3_r selected as peripheral clock
2: HSI_KER: hsi_ker selected as peripheral clock
3: CSI_KER: csi_ker selected as peripheral clock

LPTIM2SEL

Bits 10-12: LPTIM2 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.

Allowed values:
0: RCC_PCLK4: rcc_pclk4 selected as peripheral clock
1: PLL2_P: pll2_p selected as peripheral clock
2: PLL3_R: pll3_r selected as peripheral clock
3: LSE: LSE selected as peripheral clock
4: LSI: LSI selected as peripheral clock
5: PER: PER selected as peripheral clock

LPTIM3SEL

Bits 13-15: LPTIM3 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.

ADCSEL

Bits 16-17: SAR ADC kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.

Allowed values:
0: PLL2_P: pll2_p selected as peripheral clock
1: PLL3_R: pll3_r selected as peripheral clock
2: PER: PER selected as peripheral clock

DFSDM2SEL

Bit 27: DFSDM2 kernel Clk clock source selection Set and reset by software. Note: The DFSDM2 Aclk clock source selection is done by SPI6SEL (see and )..

SPI6SEL

Bits 28-30: SPI6 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.

Allowed values:
0: RCC_PCLK4: rcc_pclk4 selected as peripheral clock
1: PLL2_Q: pll2_q selected as peripheral clock
2: PLL3_Q: pll3_q selected as peripheral clock
3: HSI_KER: hsi_ker selected as peripheral clock
4: CSI_KER: csi_ker selected as peripheral clock
5: HSE: HSE selected as peripheral clock

CIER

Offset: 0x60, size: 32, reset: 0x00000000, access: Unspecified

10/10 fields covered.

Toggle fields

LSIRDYIE

Bit 0: LSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the LSI oscillator stabilization..

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

LSERDYIE

Bit 1: LSE ready interrupt enable Set and reset by software to enable/disable interrupt caused by the LSE oscillator stabilization..

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

HSIRDYIE

Bit 2: HSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSI oscillator stabilization..

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

HSERDYIE

Bit 3: HSE ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSE oscillator stabilization..

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CSIRDYIE

Bit 4: CSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the CSI oscillator stabilization..

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

HSI48RDYIE

Bit 5: HSI48 ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSI48 oscillator stabilization..

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

PLL1RDYIE

Bit 6: PLL1 ready interrupt enable Set and reset by software to enable/disable interrupt caused by PLL1 lock..

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

PLL2RDYIE

Bit 7: PLL2 ready interrupt enable Set and reset by software to enable/disable interrupt caused by PLL2 lock..

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

PLL3RDYIE

Bit 8: PLL3 ready interrupt enable Set and reset by software to enable/disable interrupt caused by PLL3 lock..

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

LSECSSIE

Bit 9: LSE clock security system interrupt enable Set and reset by software to enable/disable interrupt caused by the clock security system (CSS) on external 32 kHz oscillator..

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CIFR

Offset: 0x64, size: 32, reset: 0x00000000, access: Unspecified

11/11 fields covered.

Toggle fields

LSIRDYF

Bit 0: LSI ready interrupt flag Reset by software by writing LSIRDYC bit. Set by hardware when the LSI clock becomes stable and LSIRDYIE is set..

Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt

LSERDYF

Bit 1: LSE ready interrupt flag Reset by software by writing LSERDYC bit. Set by hardware when the LSE clock becomes stable and LSERDYIE is set..

Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt

HSIRDYF

Bit 2: HSI ready interrupt flag Reset by software by writing HSIRDYC bit. Set by hardware when the HSI clock becomes stable and HSIRDYIE is set..

Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt

HSERDYF

Bit 3: HSE ready interrupt flag Reset by software by writing HSERDYC bit. Set by hardware when the HSE clock becomes stable and HSERDYIE is set..

Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt

CSIRDYF

Bit 4: CSI ready interrupt flag Reset by software by writing CSIRDYC bit. Set by hardware when the CSI clock becomes stable and CSIRDYIE is set..

Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt

HSI48RDYF

Bit 5: HSI48 ready interrupt flag Reset by software by writing HSI48RDYC bit. Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set..

Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt

PLL1RDYF

Bit 6: PLL1 ready interrupt flag Reset by software by writing PLL1RDYC bit. Set by hardware when the PLL1 locks and PLL1RDYIE is set..

Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt

PLL2RDYF

Bit 7: PLL2 ready interrupt flag Reset by software by writing PLL2RDYC bit. Set by hardware when the PLL2 locks and PLL2RDYIE is set..

Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt

PLL3RDYF

Bit 8: PLL3 ready interrupt flag Reset by software by writing PLL3RDYC bit. Set by hardware when the PLL3 locks and PLL3RDYIE is set..

Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt

LSECSSF

Bit 9: LSE clock security system interrupt flag Reset by software by writing LSECSSC bit. Set by hardware when a failure is detected on the external 32 kHz oscillator and LSECSSIE is set..

HSECSSF

Bit 10: HSE clock security system interrupt flag Reset by software by writing HSECSSC bit. Set by hardware in case of HSE clock failure..

CICR

Offset: 0x68, size: 32, reset: 0x00000000, access: Unspecified

11/11 fields covered.

Toggle fields

LSIRDYC

Bit 0: LSI ready interrupt clear Set by software to clear LSIRDYF. Reset by hardware when clear done..

Allowed values:
1: Clear: Clear interrupt flag

LSERDYC

Bit 1: LSE ready interrupt clear Set by software to clear LSERDYF. Reset by hardware when clear done..

Allowed values:
1: Clear: Clear interrupt flag

HSIRDYC

Bit 2: HSI ready interrupt clear Set by software to clear HSIRDYF. Reset by hardware when clear done..

Allowed values:
1: Clear: Clear interrupt flag

HSERDYC

Bit 3: HSE ready interrupt clear Set by software to clear HSERDYF. Reset by hardware when clear done..

Allowed values:
1: Clear: Clear interrupt flag

CSIRDYC

Bit 4: CSI ready interrupt clear Set by software to clear CSIRDYF. Reset by hardware when clear done..

Allowed values:
1: Clear: Clear interrupt flag

HSI48RDYC

Bit 5: HSI48 ready interrupt clear Set by software to clear HSI48RDYF. Reset by hardware when clear done..

Allowed values:
1: Clear: Clear interrupt flag

PLL1RDYC

Bit 6: PLL1 ready interrupt clear Set by software to clear PLL1RDYF. Reset by hardware when clear done..

Allowed values:
1: Clear: Clear interrupt flag

PLL2RDYC

Bit 7: PLL2 ready interrupt clear Set by software to clear PLL2RDYF. Reset by hardware when clear done..

Allowed values:
1: Clear: Clear interrupt flag

PLL3RDYC

Bit 8: PLL3 ready interrupt clear Set by software to clear PLL3RDYF. Reset by hardware when clear done..

Allowed values:
1: Clear: Clear interrupt flag

LSECSSC

Bit 9: LSE clock security system interrupt clear Set by software to clear LSECSSF. Reset by hardware when clear done..

Allowed values:
1: Clear: Clear interrupt flag

HSECSSC

Bit 10: HSE clock security system interrupt clear Set by software to clear HSECSSF. Reset by hardware when clear done..

Allowed values:
1: Clear: Clear interrupt flag

BDCR

RCC Backup domain control register

Offset: 0x70, size: 32, reset: 0x00000000, access: Unspecified

9/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VSWRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCEN
rw
RTCSEL
N/A
LSEEXT
rw
LSECSSD
r
LSECSSON
rw
LSEDRV
rw
LSEBYP
rw
LSERDY
r
LSEON
rw
Toggle fields

LSEON

Bit 0: LSE oscillator enabled Set and reset by software..

Allowed values:
0: Off: LSE oscillator Off
1: On: LSE oscillator On

LSERDY

Bit 1: LSE oscillator ready Set and reset by hardware to indicate when the LSE is stable. This bit needs 6 cycles of lse_ck clock to fall down after LSEON has been set to 0..

Allowed values:
0: NotReady: LSE oscillator not ready
1: Ready: LSE oscillator ready

LSEBYP

Bit 2: LSE oscillator bypass Set and reset by software to bypass oscillator in debug mode. This bit must not be written when the LSE is enabled (by LSEON) or ready (LSERDY = 1).

Allowed values:
0: NotBypassed: LSE crystal oscillator not bypassed
1: Bypassed: LSE crystal oscillator bypassed with external clock

LSEDRV

Bits 3-4: LSE oscillator driving capability Set by software to select the driving capability of the LSE oscillator..

Allowed values:
0: Lowest: Lowest LSE oscillator driving capability
1: MediumLow: Medium low LSE oscillator driving capability
2: MediumHigh: Medium high LSE oscillator driving capability
3: Highest: Highest LSE oscillator driving capability

LSECSSON

Bit 5: LSE clock security system enable Set by software to enable the clock security system on 32 kHz oscillator. LSECSSON must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware) and after RTCSEL is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD = 1). In that case the software must disable LSECSSON..

Allowed values:
0: SecurityOff: Clock security system on 32 kHz oscillator off
1: SecurityOn: Clock security system on 32 kHz oscillator on

LSECSSD

Bit 6: LSE clock security system failure detection Set by hardware to indicate when a failure has been detected by the clock security system on the external 32 kHz oscillator..

Allowed values:
0: NoFailure: No failure detected on 32 kHz oscillator
1: Failure: Failure detected on 32 kHz oscillator

LSEEXT

Bit 7: low-speed external clock type in Bypass mode Set and reset by software to select the external clock type (analog or digital). The external clock must be enabled with the LSEON bit, to be used by the device. The LSEEXT bit can be written only if the LSE oscillator is disabled..

RTCSEL

Bits 8-9: RTC clock source selection Set by software to select the clock source for the RTC. These bits can be written only one time (except in case of failure detection on LSE). These bits must be written before LSECSSON is enabled. The VSWRST bit can be used to reset them, then it can be written one time again. If HSE is selected as RTC clock, this clock is lost when the system is in Stop mode or in case of a pin reset (NRST)..

Allowed values:
0: NoClock: No clock
1: LSE: LSE oscillator clock used as RTC clock
2: LSI: LSI oscillator clock used as RTC clock
3: HSE: HSE oscillator clock divided by a prescaler used as RTC clock

RTCEN

Bit 15: RTC clock enable Set and reset by software..

Allowed values:
0: Disabled: RTC clock disabled
1: Enabled: RTC clock enabled

VSWRST

Bit 16: VSwitch domain software reset Set and reset by software..

Allowed values:
0: NotActivated: Reset not activated
1: Reset: Resets the entire VSW domain

CSR

RCC clock control and status register

Offset: 0x74, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSIRDY
r
LSION
rw
Toggle fields

LSION

Bit 0: LSI oscillator enable Set and reset by software..

Allowed values:
0: Off: LSI oscillator Off
1: On: LSI oscillator On

LSIRDY

Bit 1: LSI oscillator ready Set and reset by hardware to indicate when the low-speed internal RC oscillator is stable. This bit needs 3 cycles of lsi_ck clock to fall down after LSION has been set to 0. This bit can be set even when LSION is not enabled if there is a request for LSI clock by the clock security system on LSE or by the low-speed watchdog or by the RTC..

Allowed values:
0: NotReady: LSI oscillator not ready
1: Ready: LSI oscillator ready

AHB3RSTR

Offset: 0x7c, size: 32, reset: 0x00000000, access: Unspecified

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GFXMMURST
rw
OTFD2RST
rw
OTFD1RST
rw
OCTOSPIMRST
rw
OCTOSPI2RST
rw
SDMMC1RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTOSPI1RST
rw
FMCRST
rw
JPGDECRST
rw
DMA2DRST
rw
MDMARST
rw
Toggle fields

MDMARST

Bit 0: MDMA block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

DMA2DRST

Bit 4: DMA2D block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

JPGDECRST

Bit 5: JPGDEC block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

FMCRST

Bit 12: FMC block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

OCTOSPI1RST

Bit 14: OCTOSPI1 and OCTOSPI1 delay blocks reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

SDMMC1RST

Bit 16: SDMMC1 and SDMMC1 delay blocks reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

OCTOSPI2RST

Bit 19: OCTOSPI2 and OCTOSPI2 delay block reset Set and reset by software.

Allowed values:
1: Reset: Reset the selected module

OCTOSPIMRST

Bit 21: OCTOSPIM reset Set and reset by software.

Allowed values:
1: Reset: Reset the selected module

OTFD1RST

Bit 22: OTFD1 reset Set and reset by software Take care that resetting the OTFD means loosing the decryption key loaded during secure boot..

Allowed values:
1: Reset: Reset the selected module

OTFD2RST

Bit 23: OTFD2 reset Set and reset by software Take care that resetting the OTFD means loosing the decryption key loaded during secure boot..

Allowed values:
1: Reset: Reset the selected module

GFXMMURST

Bit 24: GFXMMU reset Set and reset by software.

Allowed values:
1: Reset: Reset the selected module

AHB1RSTR

Offset: 0x80, size: 32, reset: 0x00000000, access: Unspecified

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USB1OTGRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCRST
rw
ADC12RST
rw
DMA2RST
rw
DMA1RST
rw
Toggle fields

DMA1RST

Bit 0: DMA1 and DMAMUX1 blocks reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

DMA2RST

Bit 1: DMA2 and DMAMUX2 blocks reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

ADC12RST

Bit 5: ADC1 and 2 blocks reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

CRCRST

Bit 9: CRC block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

USB1OTGRST

Bit 25: USB1OTG block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

AHB2RSTR

Offset: 0x84, size: 32, reset: 0x00000000, access: Unspecified

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BDMA1RST
rw
SDMMC2RST
rw
RNGRST
rw
HASHRST
rw
CRYPTRST
rw
HSEMRST
rw
DCMI_PSSIRST
rw
Toggle fields

DCMI_PSSIRST

Bit 0: digital camera interface block reset (DCMI or PSSI depending which IP is active) Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

HSEMRST

Bit 2: HSEM block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

CRYPTRST

Bit 4: cryptography block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

HASHRST

Bit 5: hash block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

RNGRST

Bit 6: random number generator block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

SDMMC2RST

Bit 9: SDMMC2 and SDMMC2 delay blocks reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

BDMA1RST

Bit 11: BDMA1 reset (DFSDM dedicated DMA) Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

AHB4RSTR

Offset: 0x88, size: 32, reset: 0x00000000, access: Unspecified

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BDMA2RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOKRST
rw
GPIOJRST
rw
GPIOIRST
rw
GPIOHRST
rw
GPIOGRST
rw
GPIOFRST
rw
GPIOERST
rw
GPIODRST
rw
GPIOCRST
rw
GPIOBRST
rw
GPIOARST
rw
Toggle fields

GPIOARST

Bit 0: GPIOA block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

GPIOBRST

Bit 1: GPIOB block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

GPIOCRST

Bit 2: GPIOC block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

GPIODRST

Bit 3: GPIOD block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

GPIOERST

Bit 4: GPIOE block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

GPIOFRST

Bit 5: GPIOF block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

GPIOGRST

Bit 6: GPIOG block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

GPIOHRST

Bit 7: GPIOH block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

GPIOIRST

Bit 8: GPIOI block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

GPIOJRST

Bit 9: GPIOJ block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

GPIOKRST

Bit 10: GPIOK block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

BDMA2RST

Bit 21: SmartRun domain DMA and DMAMUX blocks reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

APB3RSTR

Offset: 0x8c, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LTDCRST
rw
Toggle fields

LTDCRST

Bit 3: LTDC block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

APB1LRSTR

Offset: 0x90, size: 32, reset: 0x00000000, access: Unspecified

24/24 fields covered.

Toggle fields

TIM2RST

Bit 0: TIM2 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

TIM3RST

Bit 1: TIM3 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

TIM4RST

Bit 2: TIM4 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

TIM5RST

Bit 3: TIM5 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

TIM6RST

Bit 4: TIM6 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

TIM7RST

Bit 5: TIM7 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

TIM12RST

Bit 6: TIM12 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

TIM13RST

Bit 7: TIM13 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

TIM14RST

Bit 8: TIM14 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

LPTIM1RST

Bit 9: LPTIM1 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

SPI2RST

Bit 14: SPI2 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

SPI3RST

Bit 15: SPI3 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

SPDIFRXRST

Bit 16: SPDIFRX block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

USART2RST

Bit 17: USART2 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

USART3RST

Bit 18: USART3 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

UART4RST

Bit 19: UART4 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

UART5RST

Bit 20: UART5 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

I2C1RST

Bit 21: I2C1 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

I2C2RST

Bit 22: I2C2 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

I2C3RST

Bit 23: I2C3 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

CECRST

Bit 27: HDMI-CEC block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

DAC1RST

Bit 29: DAC1 (containing two converters) reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

UART7RST

Bit 30: UART7 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

UART8RST

Bit 31: UART8 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

APB1HRSTR

Offset: 0x94, size: 32, reset: 0x00000000, access: Unspecified

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDCANRST
rw
MDIOSRST
rw
OPAMPRST
rw
SWPMIRST
rw
CRSRST
rw
Toggle fields

CRSRST

Bit 1: clock recovery system reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

SWPMIRST

Bit 2: SWPMI block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

OPAMPRST

Bit 4: OPAMP block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

MDIOSRST

Bit 5: MDIOS block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

FDCANRST

Bit 8: FDCAN block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

APB2RSTR

Offset: 0x98, size: 32, reset: 0x00000000, access: Unspecified

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDM1RST
rw
SAI2RST
rw
SAI1RST
rw
SPI5RST
rw
TIM17RST
rw
TIM16RST
rw
TIM15RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI4RST
rw
SPI1RST
rw
USART10RST
rw
UART9RST
rw
USART6RST
rw
USART1RST
rw
TIM8RST
rw
TIM1RST
rw
Toggle fields

TIM1RST

Bit 0: TIM1 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

TIM8RST

Bit 1: TIM8 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

USART1RST

Bit 4: USART1 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

USART6RST

Bit 5: USART6 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

UART9RST

Bit 6: UART9 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

USART10RST

Bit 7: USART10 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

SPI1RST

Bit 12: SPI1 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

SPI4RST

Bit 13: SPI4 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

TIM15RST

Bit 16: TIM15 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

TIM16RST

Bit 17: TIM16 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

TIM17RST

Bit 18: TIM17 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

SPI5RST

Bit 20: SPI5 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

SAI1RST

Bit 22: SAI1 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

SAI2RST

Bit 23: SAI2 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

DFSDM1RST

Bit 30: DFSDM1 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

APB4RSTR

Offset: 0x9c, size: 32, reset: 0x00000000, access: Unspecified

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDM2RST
rw
DTSRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VREFRST
rw
COMP12RST
rw
DAC2RST
rw
LPTIM3RST
rw
LPTIM2RST
rw
I2C4RST
rw
SPI6RST
rw
LPUART1RST
rw
SYSCFGRST
rw
Toggle fields

SYSCFGRST

Bit 1: SYSCFG block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

LPUART1RST

Bit 3: LPUART1 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

SPI6RST

Bit 5: SPI6 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

I2C4RST

Bit 7: I2C4 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

LPTIM2RST

Bit 9: LPTIM2 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

LPTIM3RST

Bit 10: LPTIM3 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

DAC2RST

Bit 13: DAC2 (containing one converter) reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

COMP12RST

Bit 14: COMP1 and 2 blocks reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

VREFRST

Bit 15: VREF block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

DTSRST

Bit 26: Digital temperature sensor block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

DFSDM2RST

Bit 27: DFSDM2 block reset Set and reset by software..

Allowed values:
1: Reset: Reset the selected module

GCR

Global Control Register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WW1RSC
rw
Toggle fields

WW1RSC

Bit 0: WWDG1 reset scope control.

Allowed values:
0: Clear: Clear WWDG1 scope control
1: Set: Set WWDG1 scope control

SRDAMR

RCC SmartRun domain Autonomous mode register

Offset: 0xa8, size: 32, reset: 0x00000000, access: Unspecified

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRDSRAMAMEN
rw
BKPRAMAMEN
rw
DFSDM2AMEN
rw
DTSAMEN
rw
RTCAMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VREFAMEN
rw
COMP12AMEN
rw
DAC2AMEN
rw
LPTIM3AMEN
rw
LPTIM2AMEN
rw
I2C4AMEN
rw
SPI6AMEN
rw
LPUART1AMEN
rw
GPIOAMEN
rw
BDMA2AMEN
rw
Toggle fields

BDMA2AMEN

Bit 0: SmartRun domain DMA and DMAMUX Autonomous mode enable Set and reset by software. Refer to for additional information..

Allowed values:
0: Disabled: Clock disabled in autonomous mode
1: Enabled: Clock enabled in autonomous mode

GPIOAMEN

Bit 1: GPIO Autonomous mode enable Set and reset by software. Refer to for additional information..

Allowed values:
0: Disabled: Clock disabled in autonomous mode
1: Enabled: Clock enabled in autonomous mode

LPUART1AMEN

Bit 3: LPUART1 Autonomous mode enable Set and reset by software. Refer to for additional information..

Allowed values:
0: Disabled: Clock disabled in autonomous mode
1: Enabled: Clock enabled in autonomous mode

SPI6AMEN

Bit 5: SPI6 Autonomous mode enable Set and reset by software. Refer to for additional information..

Allowed values:
0: Disabled: Clock disabled in autonomous mode
1: Enabled: Clock enabled in autonomous mode

I2C4AMEN

Bit 7: I2C4 Autonomous mode enable Set and reset by software. Refer to for additional information..

Allowed values:
0: Disabled: Clock disabled in autonomous mode
1: Enabled: Clock enabled in autonomous mode

LPTIM2AMEN

Bit 9: LPTIM2 Autonomous mode enable Set and reset by software. Refer to for additional information.

Allowed values:
0: Disabled: Clock disabled in autonomous mode
1: Enabled: Clock enabled in autonomous mode

LPTIM3AMEN

Bit 10: LPTIM3 Autonomous mode enable Set and reset by software. Refer to for additional information..

Allowed values:
0: Disabled: Clock disabled in autonomous mode
1: Enabled: Clock enabled in autonomous mode

DAC2AMEN

Bit 13: DAC2 (containing one converter) Autonomous mode enable Set and reset by software. Refer to for additional information..

Allowed values:
0: Disabled: Clock disabled in autonomous mode
1: Enabled: Clock enabled in autonomous mode

COMP12AMEN

Bit 14: COMP1 and 2 Autonomous mode enable Set and reset by software. Refer to for additional information..

Allowed values:
0: Disabled: Clock disabled in autonomous mode
1: Enabled: Clock enabled in autonomous mode

VREFAMEN

Bit 15: VREF Autonomous mode enable Set and reset by software. Refer to for additional information..

Allowed values:
0: Disabled: Clock disabled in autonomous mode
1: Enabled: Clock enabled in autonomous mode

RTCAMEN

Bit 16: RTC Autonomous mode enable Set and reset by software. Refer to for additional information..

Allowed values:
0: Disabled: Clock disabled in autonomous mode
1: Enabled: Clock enabled in autonomous mode

DTSAMEN

Bit 26: Digital temperature sensor Autonomous mode enable Set and reset by software. Refer to for additional information..

Allowed values:
0: Disabled: Clock disabled in autonomous mode
1: Enabled: Clock enabled in autonomous mode

DFSDM2AMEN

Bit 27: DFSDM2 Autonomous mode enable Set and reset by software. Refer to for additional information..

Allowed values:
0: Disabled: Clock disabled in autonomous mode
1: Enabled: Clock enabled in autonomous mode

BKPRAMAMEN

Bit 28: Backup RAM Autonomous mode enable Set and reset by software. Refer to for additional information..

Allowed values:
0: Disabled: Clock disabled in autonomous mode
1: Enabled: Clock enabled in autonomous mode

SRDSRAMAMEN

Bit 29: SmartRun domain SRAM Autonomous mode enable Set and reset by software. Refer to for additional information..

Allowed values:
0: Disabled: Clock disabled in autonomous mode
1: Enabled: Clock enabled in autonomous mode

CKGAENR

RCC AXI clocks gating enable register

Offset: 0xb0, size: 32, reset: 0x00000000, access: Unspecified

0/21 fields covered.

Toggle fields

AXICKG

Bit 0: AXI interconnect matrix clock gating This bit is set and reset by software..

AHBCKG

Bit 1: AXI master AHB clock gating This bit is set and reset by software..

CPUCKG

Bit 2: AXI master CPU clock gating This bit is set and reset by software..

SDMMCCKG

Bit 3: AXI master SDMMC clock gating This bit is set and reset by software..

MDMACKG

Bit 4: AXI master MDMA clock gating This bit is set and reset by software..

DMA2DCKG

Bit 5: AXI master DMA2D clock gating This bit is set and reset by software..

LTDCCKG

Bit 6: AXI master LTDC clock gating This bit is set and reset by software..

GFXMMUMCKG

Bit 7: AXI master GFXMMU clock gating This bit is set and reset by software..

AHB12CKG

Bit 8: AXI slave AHB12 clock gating This bit is set and reset by software..

AHB34CKG

Bit 9: AXI slave AHB34 clock gating This bit is set and reset by software..

FLIFTCKG

Bit 10: AXI slave Flash interface (FLIFT) clock gating This bit is set and reset by software..

OCTOSPI2CKG

Bit 11: AXI slave OCTOSPI2 clock gating This bit is set and reset by software..

FMCCKG

Bit 12: AXI slave FMC clock gating This bit is set and reset by software..

OCTOSPI1CKG

Bit 13: AXI slave OCTOSPI1 clock gating This bit is set and reset by software..

AXIRAM1CKG

Bit 14: AXI slave SRAM1 clock gating This bit is set and reset by software..

AXIRAM2CKG

Bit 15: AXI matrix slave SRAM2 clock gating This bit is set and reset by software..

AXIRAM3CKG

Bit 16: AXI matrix slave SRAM3 clock gating This bit is set and reset by software..

GFXMMUSCKG

Bit 17: AXI matrix slave GFXMMU clock gating This bit is set and reset by software..

ECCRAMCKG

Bit 29: RAM error code correction (ECC) clock gating This bit is set and reset by software..

EXTICKG

Bit 30: EXTI clock gating This bit is set and reset by software..

JTAGCKG

Bit 31: JTAG automatic clock gating This bit is set and reset by software..

RSR

RCC reset status register

Offset: 0x130, size: 32, reset: 0x00E80000, access: Unspecified

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPWRRSTF
r
WWDGRSTF
r
IWDGRSTF
r
SFTRSTF
r
PORRSTF
r
PINRSTF
r
BORRSTF
r
CDRSTF
r
RMVF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

RMVF

Bit 16: remove reset flag Set and reset by software to reset the value of the reset flags..

Allowed values:
0: NotActivated: Reset not activated
1: Reset: Reset the reset status flags

CDRSTF

Bit 19: CPU domain power-switch reset flag Reset by software by writing the RMVF bit. Set by hardware when a the CPU domain exits from DStop or after of power-on reset. Set also when the CPU domain exists DStop2 but only when a pad reset has occurred during DStop2 (PINRST bit also set by hardware).

Allowed values:
0: NoResetOccurred: No reset occurred for block
1: ResetOccurred: Reset occurred for block

BORRSTF

Bit 21: BOR reset flag Reset by software by writing the RMVF bit. Set by hardware when a BOR reset occurs (pwr_bor_rst)..

Allowed values:
0: NoResetOccurred: No reset occurred for block
1: ResetOccurred: Reset occurred for block

PINRSTF

Bit 22: pin reset flag (NRST) Reset by software by writing the RMVF bit. Set by hardware when a reset from pin occurs..

Allowed values:
0: NoResetOccurred: No reset occurred for block
1: ResetOccurred: Reset occurred for block

PORRSTF

Bit 23: POR/PDR reset flag Reset by software by writing the RMVF bit. Set by hardware when a POR/PDR reset occurs..

Allowed values:
0: NoResetOccurred: No reset occurred for block
1: ResetOccurred: Reset occurred for block

SFTRSTF

Bit 24: system reset from CPU reset flag Reset by software by writing the RMVF bit. Set by hardware when the system reset is due to CPU.The CPU can generate a system reset by writing SYSRESETREQ bit of AIRCR register of the core M7..

Allowed values:
0: NoResetOccurred: No reset occurred for block
1: ResetOccurred: Reset occurred for block

IWDGRSTF

Bit 26: independent watchdog reset flag Reset by software by writing the RMVF bit. Set by hardware when an independent watchdog reset occurs..

Allowed values:
0: NoResetOccurred: No reset occurred for block
1: ResetOccurred: Reset occurred for block

WWDGRSTF

Bit 28: window watchdog reset flag Reset by software by writing the RMVF bit. Set by hardware when a window watchdog reset occurs..

Allowed values:
0: NoResetOccurred: No reset occurred for block
1: ResetOccurred: Reset occurred for block

LPWRRSTF

Bit 30: reset due to illegal CD DStop or CD DStop2 or CPU CStop flag Reset by software by writing the RMVF bit. Set by hardware when the CPU domain goes erroneously in DStop or DStop2, or when the CPU goes erroneously in CStop..

Allowed values:
0: NoResetOccurred: No reset occurred for block
1: ResetOccurred: Reset occurred for block

AHB3ENR

Offset: 0x134, size: 32, reset: 0x00000000, access: Unspecified

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AXISRAMEN
N/A
ITCM1EN
N/A
DTCM2EN
N/A
DTCM1EN
N/A
GFXMMUEN
rw
OTFD2EN
rw
OTFD1EN
rw
OCTOSPIMEN
rw
OCTOSPI2EN
rw
SDMMC1EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTOSPI1EN
rw
FMCEN
rw
JPGDECEN
rw
DMA2DEN
rw
MDMAEN
rw
Toggle fields

MDMAEN

Bit 0: MDMA peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

DMA2DEN

Bit 4: DMA2D peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

JPGDECEN

Bit 5: JPGDEC peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

FMCEN

Bit 12: FMC peripheral clocks enable Set and reset by software. The peripheral clocks of the FMC are the kernel clock selected by FMCSEL and provided to fmc_ker_ck input, and the rcc_hclk3 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

OCTOSPI1EN

Bit 14: OCTOSPI1 and OCTOSPI1 delay clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SDMMC1EN

Bit 16: SDMMC1 and SDMMC1 delay clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

OCTOSPI2EN

Bit 19: OCTOSPI2 clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

OCTOSPIMEN

Bit 21: OCTOSPIM clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

OTFD1EN

Bit 22: OTFD1 clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

OTFD2EN

Bit 23: OTFD2 clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GFXMMUEN

Bit 24: GFXMMU clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

DTCM1EN

Bit 28: D1 DTCM1 block enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

DTCM2EN

Bit 29: D1 DTCM2 block enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

ITCM1EN

Bit 30: D1 ITCM block enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

AXISRAMEN

Bit 31: AXISRAM block enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

AHB1ENR

Offset: 0x138, size: 32, reset: 0x00000000, access: Unspecified

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USB1ULPIEN
rw
USB1OTGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCEN
rw
ADC12EN
rw
DMA2EN
rw
DMA1EN
rw
Toggle fields

DMA1EN

Bit 0: DMA1 clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

DMA2EN

Bit 1: DMA2 clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

ADC12EN

Bit 5: ADC1 and 2 peripheral clocks enable Set and reset by software. The peripheral clocks of the ADC1 and 2 are the kernel clock selected by ADCSEL and provided to adc_ker_ck input, and the rcc_hclk1 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

CRCEN

Bit 9: CRC peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USB1OTGEN

Bit 25: USB1OTG peripheral clocks enable Set and reset by software. The peripheral clocks of the USB1OTG are the kernel clock selected by USBSEL and the rcc_hclk1 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USB1ULPIEN

Bit 26: USB_PHY1 clocks enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

AHB2ENR

Offset: 0x13c, size: 32, reset: 0x00000000, access: Unspecified

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AHBSRAM2EN
rw
AHBSRAM1EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BDMA1EN
rw
SDMMC2EN
rw
RNGEN
rw
HASHEN
rw
CRYPTEN
rw
HSEMEN
rw
DCMI_PSSIEN
rw
Toggle fields

DCMI_PSSIEN

Bit 0: digital camera interface peripheral clock enable (DCMI or PSSI depending which IP is active) Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

HSEMEN

Bit 2: HSEM peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

CRYPTEN

Bit 4: CRYPT peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

HASHEN

Bit 5: HASH peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

RNGEN

Bit 6: RNG peripheral clocks enable Set and reset by software. The peripheral clocks of the RNG are the kernel clock selected by RNGSEL and provided to rng_clk input, and the rcc_hclk2 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SDMMC2EN

Bit 9: SDMMC2 and SDMMC2 delay clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

BDMA1EN

Bit 11: DMA clock enable (DFSDM dedicated DMA) Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

AHBSRAM1EN

Bit 29: AHBSRAM1 block enable Set and reset by software. When set, this bit indicates that the SRAM1 is allocated by the CPU. It causes the CPU domain to take into account also the CPU operation modes, keeping the CPU domain in DRun when the CPU is in CRun..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

AHBSRAM2EN

Bit 30: AHBSRAM2 block enable Set and reset by software. When set, this bit indicates that the SRAM2 is allocated by the CPU. It causes the CPU domain to take into account also the CPU operation modes, keeping the CPU domain in DRun when the CPU is in CRun..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

AHB4ENR

Offset: 0x140, size: 32, reset: 0x00000000, access: Unspecified

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRDSRAMEN
rw
BKPRAMEN
rw
BDMA2EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOKEN
rw
GPIOJEN
rw
GPIOIEN
rw
GPIOHEN
rw
GPIOGEN
rw
GPIOFEN
rw
GPIOEEN
rw
GPIODEN
rw
GPIOCEN
rw
GPIOBEN
rw
GPIOAEN
rw
Toggle fields

GPIOAEN

Bit 0: GPIOA peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOBEN

Bit 1: GPIOB peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOCEN

Bit 2: GPIOC peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIODEN

Bit 3: GPIOD peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOEEN

Bit 4: GPIOE peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOFEN

Bit 5: GPIOF peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOGEN

Bit 6: GPIOG peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOHEN

Bit 7: GPIOH peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOIEN

Bit 8: GPIOI peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOJEN

Bit 9: GPIOJ peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOKEN

Bit 10: GPIOK peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

BDMA2EN

Bit 21: SmartRun domain DMA and DMAMUX clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

BKPRAMEN

Bit 28: Backup RAM clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SRDSRAMEN

Bit 29: SmartRun domain SRAM clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

APB3ENR

Offset: 0x144, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WWDGEN
rw
LTDCEN
rw
Toggle fields

LTDCEN

Bit 3: LTDC clock enable Provides the clock (ltdc_pclk, ltdc_aclk, ltdc_ker_ck) to the LTDC block. Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

WWDGEN

Bit 6: WWDG clock enable Set by software, and reset by hardware when a system reset occurs. Note that in order to work properly, before enabling the WWDG, the bit WW1RSC must be set to 1..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

APB1LENR

Offset: 0x148, size: 32, reset: 0x00000000, access: Unspecified

24/24 fields covered.

Toggle fields

TIM2EN

Bit 0: TIM2 peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM3EN

Bit 1: TIM3 peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM4EN

Bit 2: TIM4 peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM5EN

Bit 3: TIM5 peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM6EN

Bit 4: TIM6 peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM7EN

Bit 5: TIM7 peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM12EN

Bit 6: TIM12 peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM13EN

Bit 7: TIM13 peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM14EN

Bit 8: TIM14 peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

LPTIM1EN

Bit 9: LPTIM1 peripheral clocks enable Set and reset by software. The peripheral clocks of the LPTIM1 are the kernel clock selected by LPTIM1SEL and provided to lptim_ker_ck input, and the rcc_pclk1 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SPI2EN

Bit 14: SPI2 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI2 are the kernel clock selected by I2S123SRC and provided to spi_ker_ck input, and the rcc_pclk1 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SPI3EN

Bit 15: SPI3 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI3 are the kernel clock selected by I2S123SRC and provided to spi_ker_ck input, and the rcc_pclk1 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SPDIFRXEN

Bit 16: SPDIFRX peripheral clocks enable Set and reset by software. The peripheral clocks of the SPDIFRX are the kernel clock selected by SPDIFRXSEL and provided to spdifrx_ker_ck input, and the rcc_pclk1 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USART2EN

Bit 17: USART2peripheral clocks enable Set and reset by software. The peripheral clocks of the USART2 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USART3EN

Bit 18: USART3 peripheral clocks enable Set and reset by software. The peripheral clocks of the USART3 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

UART4EN

Bit 19: UART4 peripheral clocks enable Set and reset by software. The peripheral clocks of the UART4 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

UART5EN

Bit 20: UART5 peripheral clocks enable Set and reset by software. The peripheral clocks of the UART5 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

I2C1EN

Bit 21: I2C1 peripheral clocks enable Set and reset by software. The peripheral clocks of the I2C1 are the kernel clock selected by I2C123SEL and provided to i2C_ker_ck input, and the rcc_pclk1 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

I2C2EN

Bit 22: I2C2 peripheral clocks enable Set and reset by software. The peripheral clocks of the I2C2 are the kernel clock selected by I2C123SEL and provided to i2C_ker_ck input, and the rcc_pclk1 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

I2C3EN

Bit 23: I2C3 peripheral clocks enable Set and reset by software. The peripheral clocks of the I2C3 are the kernel clock selected by I2C123SEL and provided to i2C_ker_ck input, and the rcc_pclk1 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

CECEN

Bit 27: HDMI-CEC peripheral clock enable Set and reset by software. The peripheral clocks of the HDMI-CEC are the kernel clock selected by CECSEL and provided to cec_ker_ck input, and the rcc_pclk1 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

DAC1EN

Bit 29: DAC1 (containing two converters) peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

UART7EN

Bit 30: UART7 peripheral clocks enable Set and reset by software. The peripheral clocks of the UART7 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

UART8EN

Bit 31: UART8 peripheral clocks enable Set and reset by software. The peripheral clocks of the UART8 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

APB1HENR

Offset: 0x14c, size: 32, reset: 0x00000000, access: Unspecified

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDCANEN
rw
MDIOSEN
rw
OPAMPEN
rw
SWPMIEN
rw
CRSEN
rw
Toggle fields

CRSEN

Bit 1: clock recovery system peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SWPMIEN

Bit 2: SWPMI peripheral clocks enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

OPAMPEN

Bit 4: OPAMP peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

MDIOSEN

Bit 5: MDIOS peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

FDCANEN

Bit 8: FDCAN peripheral clocks enable Set and reset by software. The peripheral clocks of the FDCAN are the kernel clock selected by FDCANSEL and provided to fdcan_ker_ck input, and the rcc_pclk1 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

APB2ENR

Offset: 0x150, size: 32, reset: 0x00000000, access: Unspecified

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDM1EN
rw
SAI2EN
rw
SAI1EN
rw
SPI5EN
rw
TIM17EN
rw
TIM16EN
rw
TIM15EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI4EN
rw
SPI1EN
rw
USART10EN
rw
UART9EN
rw
USART6EN
rw
USART1EN
rw
TIM8EN
rw
TIM1EN
rw
Toggle fields

TIM1EN

Bit 0: TIM1 peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM8EN

Bit 1: TIM8 peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USART1EN

Bit 4: USART1 peripheral clocks enable Set and reset by software. The peripheral clocks of the USART1 are the kernel clock selected by USART16910SEL and provided to UCKL input, and the rcc_pclk2 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USART6EN

Bit 5: USART6 peripheral clocks enable Set and reset by software. The peripheral clocks of the USART6 are the kernel clock selected by USART16910SEL and provided to UCKL input, and the rcc_pclk2 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

UART9EN

Bit 6: UART9 peripheral clocks enable Set and reset by software. The peripheral clocks of the UART9 are the kernel clock selected by USART16910SEL and provided to UCKL input, and the rcc_pclk2 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USART10EN

Bit 7: USART10 peripheral clocks enable Set and reset by software. The peripheral clocks of the USART10 are the kernel clock selected by USART16910SEL and provided to UCKL input, and the rcc_pclk2 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SPI1EN

Bit 12: SPI1 Peripheral Clocks Enable Set and reset by software. The peripheral clocks of the SPI1 are: the kernel clock selected by I2S123SRC and provided to spi_ker_ck input, and the rcc_pclk2 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SPI4EN

Bit 13: SPI4 Peripheral Clocks Enable Set and reset by software. The peripheral clocks of the SPI4 are: the kernel clock selected by SPI45SEL and provided to spi_ker_ck input, and the rcc_pclk2 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM15EN

Bit 16: TIM15 peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM16EN

Bit 17: TIM16 peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM17EN

Bit 18: TIM17 peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SPI5EN

Bit 20: SPI5 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI5 are the kernel clock selected by SPI45SEL and provided to spi_ker_ck input, and the rcc_pclk2 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SAI1EN

Bit 22: SAI1 peripheral clocks enable Set and reset by software. The peripheral clocks of the SAI1 are: the kernel clock selected by SAI1SEL and provided to sai_a_ker_ck and sai_b_ker_ck inputs, and the rcc_pclk2 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SAI2EN

Bit 23: SAI2 peripheral clocks enable Set and reset by software. The peripheral clocks of the SAI2 are the kernel clock selected by SAI2SEL and provided to sai_a_ker_ck and sai_b_ker_ck inputs, and the rcc_pclk2 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

DFSDM1EN

Bit 30: DFSDM1 peripheral clocks enable Set and reset by software. DFSDM1 peripheral clocks are the kernel clocks selected by SAI1SEL and DFSDM1SEL and provided to Aclk and clk inputs respectively,.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

APB4ENR

Offset: 0x154, size: 32, reset: 0x00010000, access: Unspecified

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDM2EN
rw
DTSEN
rw
RTCAPBEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VREFEN
rw
COMP12EN
rw
DAC2EN
rw
LPTIM3EN
rw
LPTIM2EN
rw
I2C4EN
rw
SPI6EN
rw
LPUART1EN
rw
SYSCFGEN
rw
Toggle fields

SYSCFGEN

Bit 1: SYSCFG peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

LPUART1EN

Bit 3: LPUART1 peripheral clocks enable Set and reset by software. The peripheral clocks of the LPUART1 are the kernel clock selected by LPUART1SEL and provided to lpuart_ker_ck input, and the rcc_pclk4 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SPI6EN

Bit 5: SPI6 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI6 are the kernel clock selected by SPI6SEL and provided to spi_ker_ck input, and the rcc_pclk4 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

I2C4EN

Bit 7: I2C4 peripheral clocks enable Set and reset by software. The peripheral clocks of the I2C4 are the kernel clock selected by I2C4SEL and provided to i2C_ker_ck input, and the rcc_pclk4 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

LPTIM2EN

Bit 9: LPTIM2 peripheral clocks enable Set and reset by software. The peripheral clocks of the LPTIM2 are the kernel clock selected by LPTIM2SEL and provided to lptim_ker_ck input, and the rcc_pclk4 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

LPTIM3EN

Bit 10: LPTIM3 peripheral clocks enable Set and reset by software. The peripheral clocks of the LPTIM3 are the kernel clock selected by LPTIM345SEL and provided to lptim_ker_ck input, and the rcc_pclk4 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

DAC2EN

Bit 13: DAC2 (containing one converter) peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

COMP12EN

Bit 14: COMP1 and 2 peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

VREFEN

Bit 15: VREF peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

RTCAPBEN

Bit 16: RTC APB clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

DTSEN

Bit 26: Digital temperature sensor peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

DFSDM2EN

Bit 27: DFSDM2peripheral clock enable Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

AHB3LPENR

Offset: 0x15c, size: 32, reset: 0xFDE95131, access: Unspecified

17/18 fields covered.

Toggle fields

MDMALPEN

Bit 0: MDMA clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

DMA2DLPEN

Bit 4: DMA2D clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

JPGDECLPEN

Bit 5: JPGDEC clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

FLASHPREN

Bit 8: Flash interface clock enable during csleep mode.

FMCLPEN

Bit 12: FMC peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the FMC are the kernel clock selected by FMCSEL and provided to fmc_ker_ck input, and the rcc_hclk3 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

OCTOSPI1LPEN

Bit 14: OCTOSPI1 and OCTOSPI1 delay clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

SDMMC1LPEN

Bit 16: SDMMC1 and SDMMC1 delay clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

OCTOSPI2LPEN

Bit 19: OCTOSPI2 and OCTOSPI2 delay clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

OCTOSPIMLPEN

Bit 21: OCTOSPIM block clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

OTFD1LPEN

Bit 22: OTFD1 block clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

OTFD2LPEN

Bit 23: OTFD2 block clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

GFXMMULPEN

Bit 24: GFXMMU block clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

AXISRAM2LPEN

Bit 26: AXISRAM2 block clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

AXISRAM3LPEN

Bit 27: AXISRAM3 block clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

DTCM1LPEN

Bit 28: DTCM1 block clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

DTCM2LPEN

Bit 29: DTCM2 block clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

ITCMLPEN

Bit 30: ITCM block clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

AXISRAM1LPEN

Bit 31: AXISRAM1 block clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

AHB1LPENR

Offset: 0x160, size: 32, reset: 0x06000223, access: Unspecified

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USB1ULPILPEN
rw
USB1OTGLPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCLPEN
rw
ADC12LPEN
rw
DMA2LPEN
rw
DMA1LPEN
rw
Toggle fields

DMA1LPEN

Bit 0: DMA1 clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

DMA2LPEN

Bit 1: DMA2 clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

ADC12LPEN

Bit 5: ADC1 and 2 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the ADC1 and 2 are the kernel clock selected by ADCSEL and provided to adc_ker_ck input, and the rcc_hclk1 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

CRCLPEN

Bit 9: CRC peripheral clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

USB1OTGLPEN

Bit 25: USB1OTG peripheral clock enable during CSleep mode Set and reset by software. The peripheral clocks of the USB1OTG are the kernel clock selected by USBSEL and the rcc_hclk1 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

USB1ULPILPEN

Bit 26: USB_PHY1 clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

AHB2LPENR

Offset: 0x164, size: 32, reset: 0x60000A71, access: Unspecified

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AHBSRAM2LPEN
rw
AHBSRAM1LPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DFSDMDMALPEN
rw
SDMMC2LPEN
rw
RNGLPEN
rw
HASHLPEN
rw
CRYPTLPEN
rw
DCMI_PSSILPEN
rw
Toggle fields

DCMI_PSSILPEN

Bit 0: digital camera interface peripheral clock enable during CSleep mode (DCMI or PSSI depending which IP is active) Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

CRYPTLPEN

Bit 4: CRYPT peripheral clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

HASHLPEN

Bit 5: HASH peripheral clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

RNGLPEN

Bit 6: RNG peripheral clock enable during CSleep mode Set and reset by software. The peripheral clocks of the RNG are the kernel clock selected by RNGSEL and provided to rng_clk input, and the rcc_hclk2 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

SDMMC2LPEN

Bit 9: SDMMC2 and SDMMC2 delay clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

DFSDMDMALPEN

Bit 11: DFSDMDMA clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

AHBSRAM1LPEN

Bit 29: AHBSRAM1 clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

AHBSRAM2LPEN

Bit 30: AHBSRAM2 clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

AHB4LPENR

Offset: 0x168, size: 32, reset: 0x302007FF, access: Unspecified

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRDSRAMLPEN
rw
BKPRAMLPEN
rw
BDMA2LPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOKLPEN
rw
GPIOJLPEN
rw
GPIOILPEN
rw
GPIOHLPEN
rw
GPIOGLPEN
rw
GPIOFLPEN
rw
GPIOELPEN
rw
GPIODLPEN
rw
GPIOCLPEN
rw
GPIOBLPEN
rw
GPIOALPEN
rw
Toggle fields

GPIOALPEN

Bit 0: GPIOA peripheral clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

GPIOBLPEN

Bit 1: GPIOB peripheral clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

GPIOCLPEN

Bit 2: GPIOC peripheral clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

GPIODLPEN

Bit 3: GPIOD peripheral clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

GPIOELPEN

Bit 4: GPIOE peripheral clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

GPIOFLPEN

Bit 5: GPIOF peripheral clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

GPIOGLPEN

Bit 6: GPIOG peripheral clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

GPIOHLPEN

Bit 7: GPIOH peripheral clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

GPIOILPEN

Bit 8: GPIOI peripheral clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

GPIOJLPEN

Bit 9: GPIOJ peripheral clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

GPIOKLPEN

Bit 10: GPIOK peripheral clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

BDMA2LPEN

Bit 21: SmartRun domain DMA and DMAMUX clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

BKPRAMLPEN

Bit 28: Backup RAM clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

SRDSRAMLPEN

Bit 29: SmartRun domain SRAM clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

APB3LPENR

Offset: 0x16c, size: 32, reset: 0x00000048, access: Unspecified

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WWDGLPEN
rw
LTDCLPEN
rw
Toggle fields

LTDCLPEN

Bit 3: LTDC peripheral clock enable during CSleep mode Set and reset by software. The LTDC peripheral clocks are the kernel clock provided to ltdc_ker_ck input and the rcc_pclk3 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

WWDGLPEN

Bit 6: WWDG clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

APB1LLPENR

Offset: 0x170, size: 32, reset: 0xE8FFC3FF, access: Unspecified

24/24 fields covered.

Toggle fields

TIM2LPEN

Bit 0: TIM2 peripheral clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

TIM3LPEN

Bit 1: TIM3 peripheral clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

TIM4LPEN

Bit 2: TIM4 peripheral clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

TIM5LPEN

Bit 3: TIM5 peripheral clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

TIM6LPEN

Bit 4: TIM6 peripheral clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

TIM7LPEN

Bit 5: TIM7 peripheral clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

TIM12LPEN

Bit 6: TIM12 peripheral clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

TIM13LPEN

Bit 7: TIM13 peripheral clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

TIM14LPEN

Bit 8: TIM14 peripheral clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

LPTIM1LPEN

Bit 9: LPTIM1 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the LPTIM1 are the kernel clock selected by LPTIM1SEL and provided to lptim_ker_ck input, and the rcc_pclk1 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

SPI2LPEN

Bit 14: SPI2 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the SPI2 are the kernel clock selected by I2S123SRC and provided to spi_ker_ck input, and the rcc_pclk1 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

SPI3LPEN

Bit 15: SPI3 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the SPI3 are the kernel clock selected by I2S123SRC and provided to spi_ker_ck input, and the rcc_pclk1 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

SPDIFRXLPEN

Bit 16: SPDIFRX peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the SPDIFRX are: the kernel clock selected by SPDIFRXSEL and provided to spdifrx_ker_ck input, and the rcc_pclk1 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

USART2LPEN

Bit 17: USART2 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the USART2 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

USART3LPEN

Bit 18: USART3 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the USART3 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

UART4LPEN

Bit 19: UART4 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the UART4 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

UART5LPEN

Bit 20: UART5 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the UART5 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

I2C1LPEN

Bit 21: I2C1 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the I2C1 are the kernel clock selected by I2C123SEL and provided to i2C_ker_ck input, and the rcc_pclk1 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

I2C2LPEN

Bit 22: I2C2 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the I2C2 are the kernel clock selected by I2C123SEL and provided to i2C_ker_ck input, and the rcc_pclk1 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

I2C3LPEN

Bit 23: I2C3 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the I2C3 are the kernel clock selected by I2C123SEL and provided to i2C_ker_ck input, and the rcc_pclk1 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

CECLPEN

Bit 27: HDMI-CEC peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the HDMI-CEC are the kernel clock selected by CECSEL and provided to cec_ker_ck input, and the rcc_pclk1 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

DAC1LPEN

Bit 29: DAC1 (containing two converters) peripheral clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

UART7LPEN

Bit 30: UART7 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the UART7 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

UART8LPEN

Bit 31: UART8 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the UART8 are the kernel clock selected by USART234578SEL and provided to usart_ker_ck input, and the rcc_pclk1 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

APB1HLPENR

Offset: 0x174, size: 32, reset: 0x00000136, access: Unspecified

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDCANLPEN
rw
MDIOSLPEN
rw
OPAMPLPEN
rw
SWPMILPEN
rw
CRSLPEN
rw
Toggle fields

CRSLPEN

Bit 1: clock recovery system peripheral clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

SWPMILPEN

Bit 2: SWPMI peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the SWPMI are the kernel clock selected by SWPMISEL and provided to swpmi_ker_ck input, and the rcc_pclk1 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

OPAMPLPEN

Bit 4: OPAMP peripheral clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

MDIOSLPEN

Bit 5: MDIOS peripheral clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

FDCANLPEN

Bit 8: FDCAN peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the FDCAN are: the kernel clock selected by FDCANSEL and provided to fdcan_clk input, and the rcc_pclk1 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

APB2LPENR

Offset: 0x178, size: 32, reset: 0x40D730F3, access: Unspecified

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDM1LPEN
rw
SAI2LPEN
rw
SAI1LPEN
rw
SPI5LPEN
rw
TIM17LPEN
rw
TIM16LPEN
rw
TIM15LPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI4LPEN
rw
SPI1LPEN
rw
USART10LPEN
rw
UART9LPEN
rw
USART6LPEN
rw
USART1LPEN
rw
TIM8LPEN
rw
TIM1LPEN
rw
Toggle fields

TIM1LPEN

Bit 0: TIM1 peripheral clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

TIM8LPEN

Bit 1: TIM8 peripheral clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

USART1LPEN

Bit 4: USART1 peripheral clock enable during CSleep mode Set and reset by software. The peripheral clocks of the USART1 are the kernel clock selected by USART16910SEL and provided to usart_ker_ck inputs, and the rcc_pclk2 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

USART6LPEN

Bit 5: USART6 peripheral clock enable during CSleep mode Set and reset by software. The peripheral clocks of the USART6 are the kernel clock selected by USART16910SEL and provided to usart_ker_ck input, and the rcc_pclk2 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

UART9LPEN

Bit 6: UART9 peripheral clock enable during CSleep mode Set and reset by software. The peripheral clocks of the UART9 are the kernel clock selected by USART16910SEL and provided to usart_ker_ck input, and the rcc_pclk2 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

USART10LPEN

Bit 7: USART10 peripheral clock enable during CSleep mode Set and reset by software. The peripheral clocks of the USART10 are the kernel clock selected by USART16910SEL and provided to usart_ker_ck input, and the rcc_pclk2 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

SPI1LPEN

Bit 12: SPI1 peripheral clock enable during CSleep mode Set and reset by software. The peripheral clocks of the SPI1 are: the kernel clock selected by I2S123SRC and provided to spi_ker_ck input, and the rcc_pclk2 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

SPI4LPEN

Bit 13: SPI4 peripheral clock enable during CSleep mode Set and reset by software. The peripheral clocks of the SPI4 are: the kernel clock selected by SPI45SEL and provided to spi_ker_ck input, and the rcc_pclk2 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

TIM15LPEN

Bit 16: TIM15 peripheral clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

TIM16LPEN

Bit 17: TIM16 peripheral clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

TIM17LPEN

Bit 18: TIM17 peripheral clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

SPI5LPEN

Bit 20: SPI5 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the SPI5 are the kernel clock selected by SPI45SEL and provided to spi_ker_ck input, and the rcc_pclk2 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

SAI1LPEN

Bit 22: SAI1 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the SAI1 are: the kernel clock selected by SAI1SEL and provided to sai_a_ker_ck and sai_b_ker_ck inputs, and the rcc_pclk2 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

SAI2LPEN

Bit 23: SAI2 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the SAI2 are the kernel clock selected by SAI23EL and provided to sai_a_ker_ck and sai_b_ker_ck inputs, and the rcc_pclk2 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

DFSDM1LPEN

Bit 30: DFSDM1 peripheral clocks enable during CSleep mode Set and reset by software. DFSDM1 peripheral clocks are the kernel clocks selected by SAI1SEL and DFSDM1SEL and provided to Aclk and clk inputs respectively, and the rcc_pclk2 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

APB4LPENR

Offset: 0x17c, size: 32, reset: 0x0C01E6AA, access: Unspecified

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDM2LPEN
rw
DTSLPEN
rw
RTCAPBLPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VREFLPEN
rw
COMP12LPEN
rw
DAC2LPEN
rw
LPTIM3LPEN
rw
LPTIM2LPEN
rw
I2C4LPEN
rw
SPI6LPEN
rw
LPUART1LPEN
rw
SYSCFGLPEN
rw
Toggle fields

SYSCFGLPEN

Bit 1: SYSCFG peripheral clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

LPUART1LPEN

Bit 3: LPUART1 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the LPUART1 are the kernel clock selected by LPUART1SEL and provided to lpuart_ker_ck input, and the rcc_pclk4 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

SPI6LPEN

Bit 5: SPI6 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the SPI6 are the kernel clock selected by SPI6SEL and provided to com_ck input, and the rcc_pclk4 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

I2C4LPEN

Bit 7: I2C4 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the I2C4 are the kernel clock selected by I2C4SEL and provided to i2C_ker_ck input, and the rcc_pclk4 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

LPTIM2LPEN

Bit 9: LPTIM2 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the LPTIM2 are the kernel clock selected by LPTIM2SEL and provided to lptim_ker_ck input, and the rcc_pclk4 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

LPTIM3LPEN

Bit 10: LPTIM3 peripheral clocks enable during CSleep mode Set and reset by software. The peripheral clocks of the LPTIM3 are the kernel clock selected by LPTIM345SEL and provided to lptim_ker_ck input, and the rcc_pclk4 bus interface clock..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

DAC2LPEN

Bit 13: DAC2 (containing one converter) peripheral clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

COMP12LPEN

Bit 14: COMP1 and 2 peripheral clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

VREFLPEN

Bit 15: VREF peripheral clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

RTCAPBLPEN

Bit 16: RTC APB clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

DTSLPEN

Bit 26: temperature sensor peripheral clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

DFSDM2LPEN

Bit 27: DFSDM2 peripheral clock enable during CSleep mode Set and reset by software..

Allowed values:
0: Disabled: The selected clock is disabled during csleep mode
1: Enabled: The selected clock is enabled during csleep mode

RNG

0x48021800: RNG

7/9 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SR
0x8 DR
Toggle registers

CR

RNG control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CED
rw
IE
rw
RNGEN
rw
Toggle fields

RNGEN

Bit 2: Random number generator enable.

Allowed values:
0: Disabled: Random number generator is disabled
1: Enabled: Random number generator is enabled

IE

Bit 3: Interrupt enable.

Allowed values:
0: Disabled: RNG interrupt is disabled
1: Enabled: RNG interrupt is enabled

CED

Bit 5: Clock error detection Note: The clock error detection can be used only when ck_rc48 or ck_pll1_q (ck_pll1_q = 48MHz) source is selected otherwise, CED bit must be equal to 1. The clock error detection cannot be enabled nor disabled on the fly when RNG peripheral is enabled, to enable or disable CED the RNG must be disabled..

Allowed values:
0: Enabled: Clock error detection is enabled
1: Disabled: Clock error detection is disabled

SR

RNG status register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

3/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEIS
rw
CEIS
rw
SECS
r
CECS
r
DRDY
r
Toggle fields

DRDY

Bit 0: Data ready Note: If IE=1 in RNG_CR, an interrupt is generated when DRDY=1. It can rise when the peripheral is disabled. When the output buffer becomes empty (after reading RNG_DR), this bit returns to 0 until a new random value is generated..

CECS

Bit 1: Clock error current status Note: This bit is meaningless if CED (Clock error detection) bit in RNG_CR is equal to 1..

SECS

Bit 2: Seed error current status ** More than 64 consecutive bits at the same value (0 or 1) ** More than 32 consecutive alternances of 0 and 1 (0101010101...01).

CEIS

Bit 5: Clock error interrupt status This bit is set at the same time as CECS. It is cleared by writing it to 0. An interrupt is pending if IE = 1 in the RNG_CR register. Note: This bit is meaningless if CED (Clock error detection) bit in RNG_CR is equal to 1..

SEIS

Bit 6: Seed error interrupt status This bit is set at the same time as SECS. It is cleared by writing it to 0. ** More than 64 consecutive bits at the same value (0 or 1) ** More than 32 consecutive alternances of 0 and 1 (0101010101...01) An interrupt is pending if IE = 1 in the RNG_CR register..

DR

The RNG_DR register is a read-only register that delivers a 32-bit random value when read. The content of this register is valid when DRDY= 1, even if RNGEN=0.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RNDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RNDATA
r
Toggle fields

RNDATA

Bits 0-31: Random data 32-bit random data which are valid when DRDY=1..

RTC

0x58004000: RTC

123/126 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 TR
0x4 DR
0x8 SSR
0xc ICSR
0x10 PRER
0x14 WUTR
0x18 CR
0x24 WPR
0x28 CALR
0x2c SHIFTR
0x30 TSTR
0x34 TSDR
0x38 TSSSR
0x40 ALRM[A]R
0x44 ALRM[A]SSR
0x48 ALRM[B]R
0x4c ALRM[B]SSR
0x50 SR
0x54 MISR
0x5c SCR
0x60 CFGR
Toggle registers

TR

RTC time register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PM
rw
HT
rw
HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MNT
rw
MNU
rw
ST
rw
SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

Allowed values: 0x0-0xf

ST

Bits 4-6: Second tens in BCD format.

Allowed values: 0x0-0x7

MNU

Bits 8-11: Minute units in BCD format.

Allowed values: 0x0-0xf

MNT

Bits 12-14: Minute tens in BCD format.

Allowed values: 0x0-0x7

HU

Bits 16-19: Hour units in BCD format.

Allowed values: 0x0-0xf

HT

Bits 20-21: Hour tens in BCD format.

Allowed values: 0x0-0x3

PM

Bit 22: AM/PM notation.

Allowed values:
0: AM: AM or 24-hour format
1: PM: PM

DR

RTC date register

Offset: 0x4, size: 32, reset: 0x00002101, access: Unspecified

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
YT
rw
YU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDU
rw
MT
rw
MU
rw
DT
rw
DU
rw
Toggle fields

DU

Bits 0-3: Date units in BCD format.

Allowed values: 0x0-0xf

DT

Bits 4-5: Date tens in BCD format.

Allowed values: 0x0-0x3

MU

Bits 8-11: Month units in BCD format.

Allowed values: 0x0-0xf

MT

Bit 12: Month tens in BCD format.

Allowed values: 0x0-0x1

WDU

Bits 13-15: Week day units ....

Allowed values: 0x1-0x7

YU

Bits 16-19: Year units in BCD format.

Allowed values: 0x0-0xf

YT

Bits 20-23: Year tens in BCD format.

Allowed values: 0x0-0xf

SSR

RTC sub second register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
r
Toggle fields

SS

Bits 0-15: Sub second value SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given by the formula below: Second fraction = (PREDIV_S - SS) / (PREDIV_S + 1) Note: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct time/date is one second less than as indicated by RTC_TR/RTC_DR..

Allowed values: 0x0-0xffff

ICSR

RTC initialization control and status register

Offset: 0xc, size: 32, reset: 0x00000007, access: Unspecified

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RECALPF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INIT
rw
INITF
r
RSF
r/w0c
INITS
r
SHPF
r
WUTWF
r
ALR[B]WF
r
ALR[A]WF
r
Toggle fields

ALR[A]WF

Bit 0: Alarm A write flag.

ALR[B]WF

Bit 1: Alarm B write flag.

WUTWF

Bit 2: Wakeup timer write flag This bit is set by hardware when WUT value can be changed, after the WUTE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode..

Allowed values:
0: UpdateNotAllowed: Wakeup timer configuration update not allowed
1: UpdateAllowed: Wakeup timer configuration update allowed

SHPF

Bit 3: Shift operation pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect..

Allowed values:
0: NoShiftPending: No shift operation is pending
1: ShiftPending: A shift operation is pending

INITS

Bit 4: Initialization status flag This bit is set by hardware when the calendar year field is different from 0 (Backup domain reset state)..

Allowed values:
0: NotInitalized: Calendar has not been initialized
1: Initalized: Calendar has been initialized

RSF

Bit 5: Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSRx, RTC_TRx and RTC_DRx). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF = 1), or when in bypass shadow register mode (BYPSHAD = 1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode..

Allowed values:
0: NotSynced: Calendar shadow registers not yet synchronized
1: Synced: Calendar shadow registers synchronized

INITF

Bit 6: Initialization flag When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated..

Allowed values:
0: NotAllowed: Calendar registers update is not allowed
1: Allowed: Calendar registers update is allowed

INIT

Bit 7: Initialization mode.

Allowed values:
0: FreeRunningMode: Free running mode
1: InitMode: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.

RECALPF

Bit 16: Recalibration pending Flag The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0. Refer to ..

Allowed values:
1: Pending: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0

PRER

RTC prescaler register

Offset: 0x10, size: 32, reset: 0x007F00FF, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PREDIV_A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PREDIV_S
rw
Toggle fields

PREDIV_S

Bits 0-14: Synchronous prescaler factor This is the synchronous division factor: ck_spre frequency = ck_apre frequency/(PREDIV_S+1).

Allowed values: 0x0-0x7fff

PREDIV_A

Bits 16-22: Asynchronous prescaler factor This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1).

Allowed values: 0x0-0x7f

WUTR

RTC wakeup timer register

Offset: 0x14, size: 32, reset: 0x0000FFFF, access: Unspecified

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WUT
rw
Toggle fields

WUT

Bits 0-15: Wakeup auto-reload value bits When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0] + 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register. When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer. The first assertion of WUTF occurs between WUT and (WUT + 1) ck_wut cycles after WUTE is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] = 011 (RTCCLK/2) is forbidden..

Allowed values: 0x0-0xffff

CR

RTC control register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

26/26 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OUT2EN
rw
TAMPALRM_TYPE
rw
TAMPALRM_PU
rw
TAMPOE
rw
TAMPTS
rw
ITSE
rw
COE
rw
OSEL
rw
POL
rw
COSEL
rw
BKP
rw
SUB1H
w
ADD1H
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSIE
rw
WUTIE
rw
ALR[B]IE
rw
ALR[A]IE
rw
TSE
rw
WUTE
rw
ALR[B]E
rw
ALR[A]E
rw
FMT
rw
BYPSHAD
rw
REFCKON
rw
TSEDGE
rw
WUCKSEL
rw
Toggle fields

WUCKSEL

Bits 0-2: ck_wut wakeup clock selection 10x: ck_spre (usually 1 Hz) clock is selected 11x: ck_spre (usually 1 Hz) clock is selected and 216 is added to the WUT counter value.

Allowed values:
0: Div16: RTC/16 clock is selected
1: Div8: RTC/8 clock is selected
2: Div4: RTC/4 clock is selected
3: Div2: RTC/2 clock is selected
4: ClockSpare: ck_spre (usually 1 Hz) clock is selected
6: ClockSpareWithOffset: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value

TSEDGE

Bit 3: Timestamp event active edge TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting..

Allowed values:
0: RisingEdge: RTC_TS input rising edge generates a time-stamp event
1: FallingEdge: RTC_TS input falling edge generates a time-stamp event

REFCKON

Bit 4: RTC_REFIN reference clock detection enable (50 or 60 Hz) Note: PREDIV_S must be 0x00FF..

Allowed values:
0: Disabled: RTC_REFIN detection disabled
1: Enabled: RTC_REFIN detection enabled

BYPSHAD

Bit 5: Bypass the shadow registers Note: If the frequency of the APB1 clock is less than seven times the frequency of RTCCLK, BYPSHAD must be set to 1..

Allowed values:
0: ShadowReg: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles
1: BypassShadowReg: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters

FMT

Bit 6: Hour format.

Allowed values:
0: TwentyFourHour: 24 hour/day format
1: AmPm: AM/PM hour format

ALR[A]E

Bit 8: Alarm A enable.

Allowed values:
0: Disabled: Alarm disabled
1: Enabled: Alarm enabled

ALR[B]E

Bit 9: Alarm B enable.

Allowed values:
0: Disabled: Alarm disabled
1: Enabled: Alarm enabled

WUTE

Bit 10: Wakeup timer enable Note: When the wakeup timer is disabled, wait for WUTWF=1 before enabling it again..

Allowed values:
0: Disabled: Wakeup timer disabled
1: Enabled: Wakeup timer enabled

TSE

Bit 11: timestamp enable.

Allowed values:
0: Disabled: Timestamp disabled
1: Enabled: Timestamp enabled

ALR[A]IE

Bit 12: Alarm A interrupt enable.

Allowed values:
0: Disabled: Alarm Interrupt disabled
1: Enabled: Alarm Interrupt enabled

ALR[B]IE

Bit 13: Alarm B interrupt enable.

Allowed values:
0: Disabled: Alarm Interrupt disabled
1: Enabled: Alarm Interrupt enabled

WUTIE

Bit 14: Wakeup timer interrupt enable.

Allowed values:
0: Disabled: Wakeup timer interrupt disabled
1: Enabled: Wakeup timer interrupt enabled

TSIE

Bit 15: Timestamp interrupt enable.

Allowed values:
0: Disabled: Time-stamp Interrupt disabled
1: Enabled: Time-stamp Interrupt enabled

ADD1H

Bit 16: Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0..

Allowed values:
1: Add1: Adds 1 hour to the current time. This can be used for summer time change outside initialization mode

SUB1H

Bit 17: Subtract 1 hour (winter time change) When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. Setting this bit has no effect when current hour is 0..

Allowed values:
1: Sub1: Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode

BKP

Bit 18: Backup This bit can be written by the user to memorize whether the daylight saving time change has been performed or not..

Allowed values:
0: DSTNotChanged: Daylight Saving Time change has not been performed
1: DSTChanged: Daylight Saving Time change has been performed

COSEL

Bit 19: Calibration output selection When COE = 1, this bit selects which signal is output on CALIB. These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values (PREDIV_A = 127 and PREDIV_S = 255). Refer to ..

Allowed values:
0: CalFreq_512Hz: Calibration output is 512 Hz (with default prescaler setting)
1: CalFreq_1Hz: Calibration output is 1 Hz (with default prescaler setting)

POL

Bit 20: Output polarity This bit is used to configure the polarity of TAMPALRM output..

Allowed values:
0: High: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])
1: Low: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])

OSEL

Bits 21-22: Output selection These bits are used to select the flag to be routed to TAMPALRM output..

Allowed values:
0: Disabled: Output disabled
1: AlarmA: Alarm A output enabled
2: AlarmB: Alarm B output enabled
3: Wakeup: Wakeup output enabled

COE

Bit 23: Calibration output enable This bit enables the CALIB output.

Allowed values:
0: Disabled: Calibration output disabled
1: Enabled: Calibration output enabled

ITSE

Bit 24: timestamp on internal event enable.

Allowed values:
0: Disabled: Internal event timestamp disabled
1: Enabled: Internal event timestamp enabled

TAMPTS

Bit 25: Activate timestamp on tamper detection event TAMPTS is valid even if TSE = 0 in the RTC_CR register. Timestamp flag is set after the tamper flags, therefore if TAMPTS and TSIE are set, it is recommended to disable the tamper interrupts in order to avoid servicing 2 interrupts..

Allowed values:
0: Disabled: Tamper detection event does not cause a RTC timestamp to be saved
1: Enabled: Save RTC timestamp on tamper detection event

TAMPOE

Bit 26: Tamper detection output enable on TAMPALRM.

Allowed values:
0: Disabled: The tamper flag is not routed on TAMPALRM
1: Enabled: The tamper flag is routed on TAMPALRM, combined with the signal provided by OSEL and with the polarity provided by POL

TAMPALRM_PU

Bit 29: TAMPALRM pull-up enable.

Allowed values:
0: NoPullUp: No pull-up is applied on TAMPALRM output
1: PullUp: A pull-up is applied on TAMPALRM output

TAMPALRM_TYPE

Bit 30: TAMPALRM output type.

Allowed values:
0: PushPull: TAMPALRM is push-pull output
1: OpenDrain: TAMPALRM is open-drain output

OUT2EN

Bit 31: RTC_OUT2 output enable Setting this bit allows to remap the RTC outputs on RTC_OUT2 as follows: OUT2EN = 0: RTC output 2 disable If OSEL ≠ 00 or TAMPOE = 1: TAMPALRM is output on RTC_OUT1 If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT1 OUT2EN = 1: RTC output 2 enable If (OSEL ≠ 00 or TAMPOE = 1) and COE = 0: TAMPALRM is output on RTC_OUT2 If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT2 If (OSEL≠ 00 or TAMPOE = 1) and COE = 1: CALIB is output on RTC_OUT2 and TAMPALRM is output on RTC_OUT1..

Allowed values:
0: Disabled: RTC output 2 disable
1: Enabled: RTC output 2 enable

WPR

RTC write protection register

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-7: Write protection key This byte is written by software. Reading this byte always returns 0x00. Refer to for a description of how to unlock RTC register write protection..

Allowed values:
0: Activate: Activate write protection (any value that is not the keys)
83: Deactivate2: Key 2
202: Deactivate1: Key 1

CALR

RTC calibration register

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALP
rw
CALW8
rw
CALW16
rw
CALM
rw
Toggle fields

CALM

Bits 0-8: Calibration minus The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32 seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar with a resolution of 0.9537 ppm. To increase the frequency of the calendar, this feature should be used in conjunction with CALP. See ..

Allowed values: 0x0-0x1ff

CALW16

Bit 13: Use a 16-second calibration cycle period When CALW16 is set to 1, the 16-second calibration cycle period is selected. This bit must not be set to 1 if CALW8 = 1. Note: CALM[0] is stuck at 0 when CALW16 = 1. Refer to calibration..

Allowed values:
1: SixteenSeconds: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1

CALW8

Bit 14: Use an 8-second calibration cycle period When CALW8 is set to 1, the 8-second calibration cycle period is selected. Note: CALM[1:0] are stuck at 00 when CALW8 = 1. Refer to digital calibration..

Allowed values:
1: EightSeconds: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected

CALP

Bit 15: Increase frequency of RTC by 488.5 ppm This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of RTCCLK pulses added during a 32-second window is calculated as follows: (512 × CALP) - CALM. Refer to ..

Allowed values:
0: NoChange: No RTCCLK pulses are added
1: IncreaseFreq: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm)

SHIFTR

RTC shift control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD1S
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUBFS
w
Toggle fields

SUBFS

Bits 0-14: Subtract a fraction of a second These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). The value which is written to SUBFS is added to the synchronous prescaler counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by: Delay (seconds) = SUBFS / (PREDIV_S + 1) A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by: Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))). Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF = 1 to be sure that the shadow registers have been updated with the shifted time..

Allowed values: 0x0-0x7fff

ADD1S

Bit 31: Add one second This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation..

Allowed values:
1: Add1: Add one second to the clock/calendar

TSTR

RTC timestamp time register

Offset: 0x30, size: 32, reset: 0x00000000, access: Unspecified

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PM
rw
HT
rw
HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MNT
rw
MNU
rw
ST
rw
SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

Allowed values: 0x0-0xf

ST

Bits 4-6: Second tens in BCD format.

Allowed values: 0x0-0x7

MNU

Bits 8-11: Minute units in BCD format.

Allowed values: 0x0-0xf

MNT

Bits 12-14: Minute tens in BCD format.

Allowed values: 0x0-0x7

HU

Bits 16-19: Hour units in BCD format.

Allowed values: 0x0-0xf

HT

Bits 20-21: Hour tens in BCD format.

Allowed values: 0x0-0x3

PM

Bit 22: AM/PM notation.

Allowed values:
0: AM: AM or 24-hour format
1: PM: PM

TSDR

RTC timestamp date register

Offset: 0x34, size: 32, reset: 0x00002101, access: Unspecified

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
YT
rw
YU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDU
rw
MT
rw
MU
rw
DT
rw
DU
rw
Toggle fields

DU

Bits 0-3: Date units in BCD format.

Allowed values: 0x0-0xf

DT

Bits 4-5: Date tens in BCD format.

Allowed values: 0x0-0x3

MU

Bits 8-11: Month units in BCD format.

Allowed values: 0x0-0xf

MT

Bit 12: Month tens in BCD format.

Allowed values: 0x0-0x1

WDU

Bits 13-15: Week day units ....

Allowed values: 0x1-0x7

YU

Bits 16-19: Year units in BCD format.

Allowed values: 0x0-0xf

YT

Bits 20-23: Year tens in BCD format.

Allowed values: 0x0-0xf

TSSSR

RTC timestamp sub second register

Offset: 0x38, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
r
Toggle fields

SS

Bits 0-15: Sub second value SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given by the formula below: Second fraction = (PREDIV_S - SS) / (PREDIV_S + 1) Note: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct time/date is one second less than as indicated by RTC_TR/RTC_DR..

Allowed values: 0x0-0xffff

ALRM[A]R

Alarm A register

Offset: 0x40, size: 32, reset: 0x00000000, access: Unspecified

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSK4
rw
WDSEL
rw
DT
rw
DU
rw
MSK3
rw
PM
rw
HT
rw
HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSK2
rw
MNT
rw
MNU
rw
MSK1
rw
ST
rw
SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

Allowed values: 0x0-0xf

ST

Bits 4-6: Second tens in BCD format.

Allowed values: 0x0-0x7

MSK1

Bit 7: Alarm seconds mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

MNU

Bits 8-11: Minute units in BCD format.

Allowed values: 0x0-0xf

MNT

Bits 12-14: Minute tens in BCD format.

Allowed values: 0x0-0x7

MSK2

Bit 15: Alarm minutes mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

HU

Bits 16-19: Hour units in BCD format.

Allowed values: 0x0-0xf

HT

Bits 20-21: Hour tens in BCD format.

Allowed values: 0x0-0x3

PM

Bit 22: AM/PM notation.

Allowed values:
0: AM: AM or 24-hour format
1: PM: PM

MSK3

Bit 23: Alarm hours mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

DU

Bits 24-27: Date units or day in BCD format.

Allowed values: 0x0-0xf

DT

Bits 28-29: Date tens in BCD format.

Allowed values: 0x0-0x3

WDSEL

Bit 30: Week day selection.

Allowed values:
0: DateUnits: DU[3:0] represents the date units
1: WeekDay: DU[3:0] represents the week day. DT[1:0] is don’t care.

MSK4

Bit 31: Alarm date mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

ALRM[A]SSR

Alarm A sub-second register

Offset: 0x44, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASKSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
rw
Toggle fields

SS

Bits 0-14: Sub seconds value This value is compared with the contents of the synchronous prescaler counter to determine if alarm A is to be activated. Only bits 0 up MASKSS-1 are compared..

Allowed values: 0x0-0x7fff

MASKSS

Bits 24-27: Mask the most-significant bits starting at this bit 2: SS[14:2] are don't care in alarm A comparison. Only SS[1:0] are compared. 3: SS[14:3] are don't care in alarm A comparison. Only SS[2:0] are compared. ... 12: SS[14:12] are don't care in alarm A comparison. SS[11:0] are compared. 13: SS[14:13] are don't care in alarm A comparison. SS[12:0] are compared. 14: SS[14] is don't care in alarm A comparison. SS[13:0] are compared. 15: All 15 SS bits are compared and must match to activate alarm. The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. Note: The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation..

ALRM[B]R

Alarm B register

Offset: 0x48, size: 32, reset: 0x00000000, access: Unspecified

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSK4
rw
WDSEL
rw
DT
rw
DU
rw
MSK3
rw
PM
rw
HT
rw
HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSK2
rw
MNT
rw
MNU
rw
MSK1
rw
ST
rw
SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

Allowed values: 0x0-0xf

ST

Bits 4-6: Second tens in BCD format.

Allowed values: 0x0-0x7

MSK1

Bit 7: Alarm seconds mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

MNU

Bits 8-11: Minute units in BCD format.

Allowed values: 0x0-0xf

MNT

Bits 12-14: Minute tens in BCD format.

Allowed values: 0x0-0x7

MSK2

Bit 15: Alarm minutes mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

HU

Bits 16-19: Hour units in BCD format.

Allowed values: 0x0-0xf

HT

Bits 20-21: Hour tens in BCD format.

Allowed values: 0x0-0x3

PM

Bit 22: AM/PM notation.

Allowed values:
0: AM: AM or 24-hour format
1: PM: PM

MSK3

Bit 23: Alarm hours mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

DU

Bits 24-27: Date units or day in BCD format.

Allowed values: 0x0-0xf

DT

Bits 28-29: Date tens in BCD format.

Allowed values: 0x0-0x3

WDSEL

Bit 30: Week day selection.

Allowed values:
0: DateUnits: DU[3:0] represents the date units
1: WeekDay: DU[3:0] represents the week day. DT[1:0] is don’t care.

MSK4

Bit 31: Alarm date mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

ALRM[B]SSR

Alarm B sub-second register

Offset: 0x4c, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASKSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
rw
Toggle fields

SS

Bits 0-14: Sub seconds value This value is compared with the contents of the synchronous prescaler counter to determine if alarm A is to be activated. Only bits 0 up MASKSS-1 are compared..

Allowed values: 0x0-0x7fff

MASKSS

Bits 24-27: Mask the most-significant bits starting at this bit 2: SS[14:2] are don't care in alarm A comparison. Only SS[1:0] are compared. 3: SS[14:3] are don't care in alarm A comparison. Only SS[2:0] are compared. ... 12: SS[14:12] are don't care in alarm A comparison. SS[11:0] are compared. 13: SS[14:13] are don't care in alarm A comparison. SS[12:0] are compared. 14: SS[14] is don't care in alarm A comparison. SS[13:0] are compared. 15: All 15 SS bits are compared and must match to activate alarm. The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. Note: The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation..

SR

RTC status register

Offset: 0x50, size: 32, reset: 0x00000000, access: Unspecified

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITSF
r
TSOVF
r
TSF
r
WUTF
r
ALR[B]F
r
ALR[A]F
r
Toggle fields

ALR[A]F

Bit 0: Alarm A flag.

Allowed values:
1: Match: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRxBR)

ALR[B]F

Bit 1: Alarm B flag.

Allowed values:
1: Match: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRxBR)

WUTF

Bit 2: Wakeup timer flag This flag is set by hardware when the wakeup auto-reload counter reaches 0. This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again..

Allowed values:
1: Zero: This flag is set by hardware when the wakeup auto-reload counter reaches 0

TSF

Bit 3: Timestamp flag This flag is set by hardware when a timestamp event occurs. If ITSF flag is set, TSF must be cleared together with ITSF..

Allowed values:
1: TimestampEvent: This flag is set by hardware when a time-stamp event occurs

TSOVF

Bit 4: Timestamp overflow flag This flag is set by hardware when a timestamp event occurs while TSF is already set. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared..

Allowed values:
1: Overflow: This flag is set by hardware when a time-stamp event occurs while TSF is already set

ITSF

Bit 5: Internal timestamp flag This flag is set by hardware when a timestamp on the internal event occurs..

Allowed values:
1: TimestampEvent: This flag is set by hardware when a timestamp on the internal event occurs

MISR

RTC masked interrupt status register

Offset: 0x54, size: 32, reset: 0x00000000, access: Unspecified

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITSMF
r
TSOVMF
r
TSMF
r
WUTMF
r
ALR[B]MF
r
ALR[A]MF
r
Toggle fields

ALR[A]MF

Bit 0: Alarm A masked flag.

Allowed values:
1: Match: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR)

ALR[B]MF

Bit 1: Alarm B masked flag.

Allowed values:
1: Match: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR)

WUTMF

Bit 2: Wakeup timer masked flag This flag is set by hardware when the wakeup timer interrupt occurs. This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again..

Allowed values:
1: Zero: This flag is set by hardware when the wakeup auto-reload counter reaches 0

TSMF

Bit 3: Timestamp masked flag This flag is set by hardware when a timestamp interrupt occurs. If ITSF flag is set, TSF must be cleared together with ITSF..

Allowed values:
1: TimestampEvent: This flag is set by hardware when a time-stamp event occurs

TSOVMF

Bit 4: Timestamp overflow masked flag This flag is set by hardware when a timestamp interrupt occurs while TSMF is already set. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared..

Allowed values:
1: Overflow: This flag is set by hardware when a time-stamp event occurs while TSF is already set

ITSMF

Bit 5: Internal timestamp masked flag This flag is set by hardware when a timestamp on the internal event occurs and timestampinterrupt is raised..

Allowed values:
1: TimestampEvent: This flag is set by hardware when a timestamp on the internal event occurs

SCR

RTC status clear register

Offset: 0x5c, size: 32, reset: 0x00000000, access: Unspecified

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CITSF
w
CTSOVF
w
CTSF
w
CWUTF
w
CALRBF
w
CALRAF
w
Toggle fields

CALRAF

Bit 0: Clear alarm A flag Writing 1 in this bit clears the ALRBF bit in the RTC_SR register..

Allowed values:
1: Clear: Clear interrupt flag

CALRBF

Bit 1: Clear alarm B flag Writing 1 in this bit clears the ALRBF bit in the RTC_SR register..

Allowed values:
1: Clear: Clear interrupt flag

CWUTF

Bit 2: Clear wakeup timer flag Writing 1 in this bit clears the WUTF bit in the RTC_SR register..

Allowed values:
1: Clear: Clear interrupt flag

CTSF

Bit 3: Clear timestamp flag Writing 1 in this bit clears the TSOVF bit in the RTC_SR register. If ITSF flag is set, TSF must be cleared together with ITSF by setting CRSF and CITSF..

Allowed values:
1: Clear: Clear interrupt flag

CTSOVF

Bit 4: Clear timestamp overflow flag Writing 1 in this bit clears the TSOVF bit in the RTC_SR register. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared..

Allowed values:
1: Clear: Clear interrupt flag

CITSF

Bit 5: Clear internal timestamp flag Writing 1 in this bit clears the ITSF bit in the RTC_SR register..

Allowed values:
1: Clear: Clear interrupt flag

CFGR

RTC configuration register

Offset: 0x60, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUT2_RMP
rw
Toggle fields

OUT2_RMP

Bit 0: RTC_OUT2 mapping.

SAI1

0x40015800: SAI

86/122 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 GCR
0x4 CR1 [A]
0x8 CR2 [A]
0xc FRCR [A]
0x10 SLOTR [A]
0x14 IM [A]
0x18 SR [A]
0x1c CLRFR [A]
0x20 DR [A]
0x24 CR1 [B]
0x28 CR2 [B]
0x2c FRCR [B]
0x30 SLOTR [B]
0x34 IM [B]
0x38 SR [B]
0x3c CLRFR [B]
0x40 DR [B]
0x44 PDMCR
0x48 PDMDLY
Toggle registers

GCR

Global configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNCOUT
rw
SYNCIN
rw
Toggle fields

SYNCIN

Bits 0-1: Synchronization inputs.

SYNCOUT

Bits 4-5: Synchronization outputs These bits are set and cleared by software..

CR1 [A]

Configuration register 1

Offset: 0x4, size: 32, reset: 0x00000040, access: read-write

11/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCKEN
rw
OSR
rw
MCKDIV
rw
NODIV
rw
DMAEN
rw
SAIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTDRIV
rw
MONO
rw
SYNCEN
rw
CKSTR
rw
LSBFIRST
rw
DS
rw
PRTCFG
rw
MODE
rw
Toggle fields

MODE

Bits 0-1: SAIx audio block mode immediately.

Allowed values:
0: MasterTx: Master transmitter
1: MasterRx: Master receiver
2: SlaveTx: Slave transmitter
3: SlaveRx: Slave receiver

PRTCFG

Bits 2-3: Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled..

Allowed values:
0: Free: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol
1: Spdif: SPDIF protocol
2: Ac97: AC’97 protocol

DS

Bits 5-7: Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled..

Allowed values:
2: Bit8: 8 bits
3: Bit10: 10 bits
4: Bit16: 16 bits
5: Bit20: 20 bits
6: Bit24: 24 bits
7: Bit32: 32 bits

LSBFIRST

Bit 8: Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first..

Allowed values:
0: MsbFirst: Data are transferred with MSB first
1: LsbFirst: Data are transferred with LSB first

CKSTR

Bit 9: Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol..

Allowed values:
0: FallingEdge: Data strobing edge is falling edge of SCK
1: RisingEdge: Data strobing edge is rising edge of SCK

SYNCEN

Bits 10-11: Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled..

Allowed values:
0: Asynchronous: audio sub-block in asynchronous mode
1: Internal: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode
2: External: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode

MONO

Bit 12: Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details..

Allowed values:
0: Stereo: Stereo mode
1: Mono: Mono mode

OUTDRIV

Bit 13: Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration..

Allowed values:
0: OnStart: Audio block output driven when SAIEN is set
1: Immediately: Audio block output driven immediately after the setting of this bit

SAIEN

Bit 16: Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit..

Allowed values:
0: Disabled: SAI audio block disabled
1: Enabled: SAI audio block enabled

DMAEN

Bit 17: DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode..

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

NODIV

Bit 19: No fixed divider between MCLK and FS.

Allowed values:
0: MasterClock: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value
1: NoDiv: MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.

MCKDIV

Bits 20-25: Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula:.

OSR

Bit 26: Oversampling ratio for master clock.

MCKEN

Bit 27: Master clock generation enable.

CR2 [A]

Configuration register 2

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

6/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP
rw
CPL
rw
MUTECNT
rw
MUTEVAL
rw
MUTE
rw
TRIS
rw
FFLUSH
w
FTH
rw
Toggle fields

FTH

Bits 0-2: FIFO threshold. This bit is set and cleared by software..

Allowed values:
0: Empty: FIFO empty
1: Quarter1: 1⁄4 FIFO
2: Quarter2: 1⁄2 FIFO
3: Quarter3: 3⁄4 FIFO
4: Full: FIFO full

FFLUSH

Bit 3: FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled..

Allowed values:
0: NoFlush: No FIFO flush
1: Flush: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared

TRIS

Bit 4: Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details..

MUTE

Bit 5: Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks..

Allowed values:
0: Disabled: No mute mode
1: Enabled: Mute mode enabled

MUTEVAL

Bit 6: Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks..

Allowed values:
0: SendZero: Bit value 0 is sent during the mute mode
1: SendLast: Last values are sent during the mute mode

MUTECNT

Bits 7-12: Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details..

CPL

Bit 13: Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm..

Allowed values:
0: OnesComplement: 1’s complement representation
1: TwosComplement: 2’s complement representation

COMP

Bits 14-15: Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected..

Allowed values:
0: NoCompanding: No companding algorithm
2: MuLaw: μ-Law algorithm
3: ALaw: A-Law algorithm

FRCR [A]

This register has no meaning in AC97 and SPDIF audio protocol

Offset: 0xc, size: 32, reset: 0x00000007, access: Unspecified

3/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSOFF
rw
FSPOL
rw
FSDEF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSALL
rw
FRL
rw
Toggle fields

FRL

Bits 0-7: Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration..

FSALL

Bits 8-14: Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled..

FSDEF

Bit 16: Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled..

FSPOL

Bit 17: Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled..

Allowed values:
0: FallingEdge: FS is active low (falling edge)
1: RisingEdge: FS is active high (rising edge)

FSOFF

Bit 18: Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled..

Allowed values:
0: OnFirst: FS is asserted on the first bit of the slot 0
1: BeforeFirst: FS is asserted one bit before the first bit of the slot 0

SLOTR [A]

This register has no meaning in AC97 and SPDIF audio protocol

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLOTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBSLOT
rw
SLOTSZ
rw
FBOFF
rw
Toggle fields

FBOFF

Bits 0-4: First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode..

SLOTSZ

Bits 6-7: Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode..

Allowed values:
0: DataSize: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)
1: Bit16: 16-bit
2: Bit32: 32-bit

NBSLOT

Bits 8-11: Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode..

SLOTEN

Bits 16-31: Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode..

Allowed values:
0: Inactive: Inactive slot
1: Active: Active slot

IM [A]

Interrupt mask register 2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDETIE
rw
AFSDETIE
rw
CNRDYIE
rw
FREQIE
rw
WCKCFGIE
rw
MUTEDETIE
rw
OVRUDRIE
rw
Toggle fields

OVRUDRIE

Bit 0: Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set..

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

MUTEDETIE

Bit 1: Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode..

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

WCKCFGIE

Bit 2: Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes..

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

FREQIE

Bit 3: FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode,.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

CNRDYIE

Bit 4: Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver..

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

AFSDETIE

Bit 5: Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master..

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

LFSDETIE

Bit 6: Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master..

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

SR [A]

Status register

Offset: 0x18, size: 32, reset: 0x00000008, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLVL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDET
r
AFSDET
r
CNRDY
r
FREQ
r
WCKCFG
r
MUTEDET
r
OVRUDR
r
Toggle fields

OVRUDR

Bit 0: Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register..

Allowed values:
0: NoError: No overrun/underrun error
1: Overrun: Overrun/underrun error detection

MUTEDET

Bit 1: Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register..

Allowed values:
0: NoMute: No MUTE detection on the SD input line
1: Mute: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame

WCKCFG

Bit 2: Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register..

Allowed values:
0: Correct: Clock configuration is correct
1: Wrong: Clock configuration does not respect the rule concerning the frame length specification

FREQ

Bit 3: FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register..

Allowed values:
0: NoRequest: No FIFO request
1: Request: FIFO request to read or to write the SAI_xDR

CNRDY

Bit 4: Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register..

Allowed values:
0: Ready: External AC’97 Codec is ready
1: NotReady: External AC’97 Codec is not ready

AFSDET

Bit 5: Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register..

Allowed values:
0: NoError: No error
1: EarlySync: Frame synchronization signal is detected earlier than expected

LFSDET

Bit 6: Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register.

Allowed values:
0: NoError: No error
1: NoSync: Frame synchronization signal is not present at the right time

FLVL

Bits 16-18: FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver:.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: FIFO <= 1⁄4 but not empty
2: Quarter2: 1⁄4 < FIFO <= 1⁄2
3: Quarter3: 1⁄2 < FIFO <= 3⁄4
4: Quarter4: 3⁄4 < FIFO but not full
5: Full: FIFO full

CLRFR [A]

Clear flag register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLFSDET
w
CAFSDET
w
CCNRDY
w
CWCKCFG
w
CMUTEDET
w
COVRUDR
w
Toggle fields

COVRUDR

Bit 0: Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0..

Allowed values:
1: Clear: Clears the OVRUDR flag

CMUTEDET

Bit 1: Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0..

Allowed values:
1: Clear: Clears the MUTEDET flag

CWCKCFG

Bit 2: Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0..

Allowed values:
1: Clear: Clears the WCKCFG flag

CCNRDY

Bit 4: Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0..

Allowed values:
1: Clear: Clears the CNRDY flag

CAFSDET

Bit 5: Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0..

Allowed values:
1: Clear: Clears the AFSDET flag

CLFSDET

Bit 6: Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0..

Allowed values:
1: Clear: Clears the LFSDET flag

DR [A]

Data register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty..

CR1 [B]

Configuration register 1

Offset: 0x24, size: 32, reset: 0x00000040, access: read-write

11/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCKEN
rw
OSR
rw
MCKDIV
rw
NODIV
rw
DMAEN
rw
SAIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTDRIV
rw
MONO
rw
SYNCEN
rw
CKSTR
rw
LSBFIRST
rw
DS
rw
PRTCFG
rw
MODE
rw
Toggle fields

MODE

Bits 0-1: SAIx audio block mode immediately.

Allowed values:
0: MasterTx: Master transmitter
1: MasterRx: Master receiver
2: SlaveTx: Slave transmitter
3: SlaveRx: Slave receiver

PRTCFG

Bits 2-3: Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled..

Allowed values:
0: Free: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol
1: Spdif: SPDIF protocol
2: Ac97: AC’97 protocol

DS

Bits 5-7: Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled..

Allowed values:
2: Bit8: 8 bits
3: Bit10: 10 bits
4: Bit16: 16 bits
5: Bit20: 20 bits
6: Bit24: 24 bits
7: Bit32: 32 bits

LSBFIRST

Bit 8: Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first..

Allowed values:
0: MsbFirst: Data are transferred with MSB first
1: LsbFirst: Data are transferred with LSB first

CKSTR

Bit 9: Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol..

Allowed values:
0: FallingEdge: Data strobing edge is falling edge of SCK
1: RisingEdge: Data strobing edge is rising edge of SCK

SYNCEN

Bits 10-11: Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled..

Allowed values:
0: Asynchronous: audio sub-block in asynchronous mode
1: Internal: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode
2: External: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode

MONO

Bit 12: Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details..

Allowed values:
0: Stereo: Stereo mode
1: Mono: Mono mode

OUTDRIV

Bit 13: Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration..

Allowed values:
0: OnStart: Audio block output driven when SAIEN is set
1: Immediately: Audio block output driven immediately after the setting of this bit

SAIEN

Bit 16: Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit..

Allowed values:
0: Disabled: SAI audio block disabled
1: Enabled: SAI audio block enabled

DMAEN

Bit 17: DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode..

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

NODIV

Bit 19: No fixed divider between MCLK and FS.

Allowed values:
0: MasterClock: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value
1: NoDiv: MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.

MCKDIV

Bits 20-25: Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula:.

OSR

Bit 26: Oversampling ratio for master clock.

MCKEN

Bit 27: Master clock generation enable.

CR2 [B]

Configuration register 2

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

6/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP
rw
CPL
rw
MUTECNT
rw
MUTEVAL
rw
MUTE
rw
TRIS
rw
FFLUSH
w
FTH
rw
Toggle fields

FTH

Bits 0-2: FIFO threshold. This bit is set and cleared by software..

Allowed values:
0: Empty: FIFO empty
1: Quarter1: 1⁄4 FIFO
2: Quarter2: 1⁄2 FIFO
3: Quarter3: 3⁄4 FIFO
4: Full: FIFO full

FFLUSH

Bit 3: FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled..

Allowed values:
0: NoFlush: No FIFO flush
1: Flush: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared

TRIS

Bit 4: Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details..

MUTE

Bit 5: Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks..

Allowed values:
0: Disabled: No mute mode
1: Enabled: Mute mode enabled

MUTEVAL

Bit 6: Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks..

Allowed values:
0: SendZero: Bit value 0 is sent during the mute mode
1: SendLast: Last values are sent during the mute mode

MUTECNT

Bits 7-12: Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details..

CPL

Bit 13: Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm..

Allowed values:
0: OnesComplement: 1’s complement representation
1: TwosComplement: 2’s complement representation

COMP

Bits 14-15: Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected..

Allowed values:
0: NoCompanding: No companding algorithm
2: MuLaw: μ-Law algorithm
3: ALaw: A-Law algorithm

FRCR [B]

This register has no meaning in AC97 and SPDIF audio protocol

Offset: 0x2c, size: 32, reset: 0x00000007, access: Unspecified

3/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSOFF
rw
FSPOL
rw
FSDEF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSALL
rw
FRL
rw
Toggle fields

FRL

Bits 0-7: Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration..

FSALL

Bits 8-14: Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled..

FSDEF

Bit 16: Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled..

FSPOL

Bit 17: Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled..

Allowed values:
0: FallingEdge: FS is active low (falling edge)
1: RisingEdge: FS is active high (rising edge)

FSOFF

Bit 18: Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled..

Allowed values:
0: OnFirst: FS is asserted on the first bit of the slot 0
1: BeforeFirst: FS is asserted one bit before the first bit of the slot 0

SLOTR [B]

This register has no meaning in AC97 and SPDIF audio protocol

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLOTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBSLOT
rw
SLOTSZ
rw
FBOFF
rw
Toggle fields

FBOFF

Bits 0-4: First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode..

SLOTSZ

Bits 6-7: Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode..

Allowed values:
0: DataSize: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)
1: Bit16: 16-bit
2: Bit32: 32-bit

NBSLOT

Bits 8-11: Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode..

SLOTEN

Bits 16-31: Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode..

Allowed values:
0: Inactive: Inactive slot
1: Active: Active slot

IM [B]

Interrupt mask register 2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDETIE
rw
AFSDETIE
rw
CNRDYIE
rw
FREQIE
rw
WCKCFGIE
rw
MUTEDETIE
rw
OVRUDRIE
rw
Toggle fields

OVRUDRIE

Bit 0: Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set..

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

MUTEDETIE

Bit 1: Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode..

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

WCKCFGIE

Bit 2: Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes..

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

FREQIE

Bit 3: FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode,.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

CNRDYIE

Bit 4: Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver..

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

AFSDETIE

Bit 5: Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master..

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

LFSDETIE

Bit 6: Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master..

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

SR [B]

Status register

Offset: 0x38, size: 32, reset: 0x00000008, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLVL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDET
r
AFSDET
r
CNRDY
r
FREQ
r
WCKCFG
r
MUTEDET
r
OVRUDR
r
Toggle fields

OVRUDR

Bit 0: Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register..

Allowed values:
0: NoError: No overrun/underrun error
1: Overrun: Overrun/underrun error detection

MUTEDET

Bit 1: Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register..

Allowed values:
0: NoMute: No MUTE detection on the SD input line
1: Mute: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame

WCKCFG

Bit 2: Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register..

Allowed values:
0: Correct: Clock configuration is correct
1: Wrong: Clock configuration does not respect the rule concerning the frame length specification

FREQ

Bit 3: FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register..

Allowed values:
0: NoRequest: No FIFO request
1: Request: FIFO request to read or to write the SAI_xDR

CNRDY

Bit 4: Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register..

Allowed values:
0: Ready: External AC’97 Codec is ready
1: NotReady: External AC’97 Codec is not ready

AFSDET

Bit 5: Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register..

Allowed values:
0: NoError: No error
1: EarlySync: Frame synchronization signal is detected earlier than expected

LFSDET

Bit 6: Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register.

Allowed values:
0: NoError: No error
1: NoSync: Frame synchronization signal is not present at the right time

FLVL

Bits 16-18: FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver:.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: FIFO <= 1⁄4 but not empty
2: Quarter2: 1⁄4 < FIFO <= 1⁄2
3: Quarter3: 1⁄2 < FIFO <= 3⁄4
4: Quarter4: 3⁄4 < FIFO but not full
5: Full: FIFO full

CLRFR [B]

Clear flag register

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLFSDET
w
CAFSDET
w
CCNRDY
w
CWCKCFG
w
CMUTEDET
w
COVRUDR
w
Toggle fields

COVRUDR

Bit 0: Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0..

Allowed values:
1: Clear: Clears the OVRUDR flag

CMUTEDET

Bit 1: Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0..

Allowed values:
1: Clear: Clears the MUTEDET flag

CWCKCFG

Bit 2: Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0..

Allowed values:
1: Clear: Clears the WCKCFG flag

CCNRDY

Bit 4: Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0..

Allowed values:
1: Clear: Clears the CNRDY flag

CAFSDET

Bit 5: Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0..

Allowed values:
1: Clear: Clears the AFSDET flag

CLFSDET

Bit 6: Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0..

Allowed values:
1: Clear: Clears the LFSDET flag

DR [B]

Data register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty..

PDMCR

PDM control register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKEN4
rw
CKEN3
rw
CKEN2
rw
CKEN1
rw
MICNBR
rw
PDMEN
rw
Toggle fields

PDMEN

Bit 0: PDM enable.

MICNBR

Bits 4-5: Number of microphones.

CKEN1

Bit 8: Clock enable of bitstream clock number 1.

CKEN2

Bit 9: Clock enable of bitstream clock number 2.

CKEN3

Bit 10: Clock enable of bitstream clock number 3.

CKEN4

Bit 11: Clock enable of bitstream clock number 4.

PDMDLY

PDM delay register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLYM[4]R
rw
DLYM[4]L
rw
DLYM[3]R
rw
DLYM[3]L
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYM[2]R
rw
DLYM[2]L
rw
DLYM[1]R
rw
DLYM[1]L
rw
Toggle fields

DLYM[1]L

Bits 0-2: Delay line adjust for first microphone of pair 1.

DLYM[1]R

Bits 4-6: Delay line adjust for second microphone of pair 1.

DLYM[2]L

Bits 8-10: Delay line adjust for first microphone of pair 2.

DLYM[2]R

Bits 12-14: Delay line adjust for second microphone of pair 2.

DLYM[3]L

Bits 16-18: Delay line adjust for first microphone of pair 3.

DLYM[3]R

Bits 20-22: Delay line adjust for second microphone of pair 3.

DLYM[4]L

Bits 24-26: Delay line adjust for first microphone of pair 4.

DLYM[4]R

Bits 28-30: Delay line adjust for second microphone of pair 4.

SAI2

0x40015c00: SAI

86/122 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 GCR
0x4 CR1 [A]
0x8 CR2 [A]
0xc FRCR [A]
0x10 SLOTR [A]
0x14 IM [A]
0x18 SR [A]
0x1c CLRFR [A]
0x20 DR [A]
0x24 CR1 [B]
0x28 CR2 [B]
0x2c FRCR [B]
0x30 SLOTR [B]
0x34 IM [B]
0x38 SR [B]
0x3c CLRFR [B]
0x40 DR [B]
0x44 PDMCR
0x48 PDMDLY
Toggle registers

GCR

Global configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNCOUT
rw
SYNCIN
rw
Toggle fields

SYNCIN

Bits 0-1: Synchronization inputs.

SYNCOUT

Bits 4-5: Synchronization outputs These bits are set and cleared by software..

CR1 [A]

Configuration register 1

Offset: 0x4, size: 32, reset: 0x00000040, access: read-write

11/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCKEN
rw
OSR
rw
MCKDIV
rw
NODIV
rw
DMAEN
rw
SAIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTDRIV
rw
MONO
rw
SYNCEN
rw
CKSTR
rw
LSBFIRST
rw
DS
rw
PRTCFG
rw
MODE
rw
Toggle fields

MODE

Bits 0-1: SAIx audio block mode immediately.

Allowed values:
0: MasterTx: Master transmitter
1: MasterRx: Master receiver
2: SlaveTx: Slave transmitter
3: SlaveRx: Slave receiver

PRTCFG

Bits 2-3: Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled..

Allowed values:
0: Free: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol
1: Spdif: SPDIF protocol
2: Ac97: AC’97 protocol

DS

Bits 5-7: Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled..

Allowed values:
2: Bit8: 8 bits
3: Bit10: 10 bits
4: Bit16: 16 bits
5: Bit20: 20 bits
6: Bit24: 24 bits
7: Bit32: 32 bits

LSBFIRST

Bit 8: Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first..

Allowed values:
0: MsbFirst: Data are transferred with MSB first
1: LsbFirst: Data are transferred with LSB first

CKSTR

Bit 9: Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol..

Allowed values:
0: FallingEdge: Data strobing edge is falling edge of SCK
1: RisingEdge: Data strobing edge is rising edge of SCK

SYNCEN

Bits 10-11: Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled..

Allowed values:
0: Asynchronous: audio sub-block in asynchronous mode
1: Internal: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode
2: External: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode

MONO

Bit 12: Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details..

Allowed values:
0: Stereo: Stereo mode
1: Mono: Mono mode

OUTDRIV

Bit 13: Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration..

Allowed values:
0: OnStart: Audio block output driven when SAIEN is set
1: Immediately: Audio block output driven immediately after the setting of this bit

SAIEN

Bit 16: Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit..

Allowed values:
0: Disabled: SAI audio block disabled
1: Enabled: SAI audio block enabled

DMAEN

Bit 17: DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode..

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

NODIV

Bit 19: No fixed divider between MCLK and FS.

Allowed values:
0: MasterClock: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value
1: NoDiv: MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.

MCKDIV

Bits 20-25: Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula:.

OSR

Bit 26: Oversampling ratio for master clock.

MCKEN

Bit 27: Master clock generation enable.

CR2 [A]

Configuration register 2

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

6/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP
rw
CPL
rw
MUTECNT
rw
MUTEVAL
rw
MUTE
rw
TRIS
rw
FFLUSH
w
FTH
rw
Toggle fields

FTH

Bits 0-2: FIFO threshold. This bit is set and cleared by software..

Allowed values:
0: Empty: FIFO empty
1: Quarter1: 1⁄4 FIFO
2: Quarter2: 1⁄2 FIFO
3: Quarter3: 3⁄4 FIFO
4: Full: FIFO full

FFLUSH

Bit 3: FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled..

Allowed values:
0: NoFlush: No FIFO flush
1: Flush: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared

TRIS

Bit 4: Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details..

MUTE

Bit 5: Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks..

Allowed values:
0: Disabled: No mute mode
1: Enabled: Mute mode enabled

MUTEVAL

Bit 6: Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks..

Allowed values:
0: SendZero: Bit value 0 is sent during the mute mode
1: SendLast: Last values are sent during the mute mode

MUTECNT

Bits 7-12: Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details..

CPL

Bit 13: Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm..

Allowed values:
0: OnesComplement: 1’s complement representation
1: TwosComplement: 2’s complement representation

COMP

Bits 14-15: Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected..

Allowed values:
0: NoCompanding: No companding algorithm
2: MuLaw: μ-Law algorithm
3: ALaw: A-Law algorithm

FRCR [A]

This register has no meaning in AC97 and SPDIF audio protocol

Offset: 0xc, size: 32, reset: 0x00000007, access: Unspecified

3/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSOFF
rw
FSPOL
rw
FSDEF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSALL
rw
FRL
rw
Toggle fields

FRL

Bits 0-7: Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration..

FSALL

Bits 8-14: Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled..

FSDEF

Bit 16: Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled..

FSPOL

Bit 17: Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled..

Allowed values:
0: FallingEdge: FS is active low (falling edge)
1: RisingEdge: FS is active high (rising edge)

FSOFF

Bit 18: Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled..

Allowed values:
0: OnFirst: FS is asserted on the first bit of the slot 0
1: BeforeFirst: FS is asserted one bit before the first bit of the slot 0

SLOTR [A]

This register has no meaning in AC97 and SPDIF audio protocol

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLOTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBSLOT
rw
SLOTSZ
rw
FBOFF
rw
Toggle fields

FBOFF

Bits 0-4: First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode..

SLOTSZ

Bits 6-7: Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode..

Allowed values:
0: DataSize: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)
1: Bit16: 16-bit
2: Bit32: 32-bit

NBSLOT

Bits 8-11: Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode..

SLOTEN

Bits 16-31: Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode..

Allowed values:
0: Inactive: Inactive slot
1: Active: Active slot

IM [A]

Interrupt mask register 2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDETIE
rw
AFSDETIE
rw
CNRDYIE
rw
FREQIE
rw
WCKCFGIE
rw
MUTEDETIE
rw
OVRUDRIE
rw
Toggle fields

OVRUDRIE

Bit 0: Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set..

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

MUTEDETIE

Bit 1: Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode..

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

WCKCFGIE

Bit 2: Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes..

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

FREQIE

Bit 3: FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode,.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

CNRDYIE

Bit 4: Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver..

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

AFSDETIE

Bit 5: Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master..

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

LFSDETIE

Bit 6: Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master..

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

SR [A]

Status register

Offset: 0x18, size: 32, reset: 0x00000008, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLVL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDET
r
AFSDET
r
CNRDY
r
FREQ
r
WCKCFG
r
MUTEDET
r
OVRUDR
r
Toggle fields

OVRUDR

Bit 0: Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register..

Allowed values:
0: NoError: No overrun/underrun error
1: Overrun: Overrun/underrun error detection

MUTEDET

Bit 1: Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register..

Allowed values:
0: NoMute: No MUTE detection on the SD input line
1: Mute: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame

WCKCFG

Bit 2: Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register..

Allowed values:
0: Correct: Clock configuration is correct
1: Wrong: Clock configuration does not respect the rule concerning the frame length specification

FREQ

Bit 3: FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register..

Allowed values:
0: NoRequest: No FIFO request
1: Request: FIFO request to read or to write the SAI_xDR

CNRDY

Bit 4: Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register..

Allowed values:
0: Ready: External AC’97 Codec is ready
1: NotReady: External AC’97 Codec is not ready

AFSDET

Bit 5: Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register..

Allowed values:
0: NoError: No error
1: EarlySync: Frame synchronization signal is detected earlier than expected

LFSDET

Bit 6: Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register.

Allowed values:
0: NoError: No error
1: NoSync: Frame synchronization signal is not present at the right time

FLVL

Bits 16-18: FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver:.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: FIFO <= 1⁄4 but not empty
2: Quarter2: 1⁄4 < FIFO <= 1⁄2
3: Quarter3: 1⁄2 < FIFO <= 3⁄4
4: Quarter4: 3⁄4 < FIFO but not full
5: Full: FIFO full

CLRFR [A]

Clear flag register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLFSDET
w
CAFSDET
w
CCNRDY
w
CWCKCFG
w
CMUTEDET
w
COVRUDR
w
Toggle fields

COVRUDR

Bit 0: Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0..

Allowed values:
1: Clear: Clears the OVRUDR flag

CMUTEDET

Bit 1: Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0..

Allowed values:
1: Clear: Clears the MUTEDET flag

CWCKCFG

Bit 2: Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0..

Allowed values:
1: Clear: Clears the WCKCFG flag

CCNRDY

Bit 4: Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0..

Allowed values:
1: Clear: Clears the CNRDY flag

CAFSDET

Bit 5: Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0..

Allowed values:
1: Clear: Clears the AFSDET flag

CLFSDET

Bit 6: Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0..

Allowed values:
1: Clear: Clears the LFSDET flag

DR [A]

Data register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty..

CR1 [B]

Configuration register 1

Offset: 0x24, size: 32, reset: 0x00000040, access: read-write

11/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCKEN
rw
OSR
rw
MCKDIV
rw
NODIV
rw
DMAEN
rw
SAIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTDRIV
rw
MONO
rw
SYNCEN
rw
CKSTR
rw
LSBFIRST
rw
DS
rw
PRTCFG
rw
MODE
rw
Toggle fields

MODE

Bits 0-1: SAIx audio block mode immediately.

Allowed values:
0: MasterTx: Master transmitter
1: MasterRx: Master receiver
2: SlaveTx: Slave transmitter
3: SlaveRx: Slave receiver

PRTCFG

Bits 2-3: Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled..

Allowed values:
0: Free: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol
1: Spdif: SPDIF protocol
2: Ac97: AC’97 protocol

DS

Bits 5-7: Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled..

Allowed values:
2: Bit8: 8 bits
3: Bit10: 10 bits
4: Bit16: 16 bits
5: Bit20: 20 bits
6: Bit24: 24 bits
7: Bit32: 32 bits

LSBFIRST

Bit 8: Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first..

Allowed values:
0: MsbFirst: Data are transferred with MSB first
1: LsbFirst: Data are transferred with LSB first

CKSTR

Bit 9: Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol..

Allowed values:
0: FallingEdge: Data strobing edge is falling edge of SCK
1: RisingEdge: Data strobing edge is rising edge of SCK

SYNCEN

Bits 10-11: Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled..

Allowed values:
0: Asynchronous: audio sub-block in asynchronous mode
1: Internal: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode
2: External: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode

MONO

Bit 12: Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details..

Allowed values:
0: Stereo: Stereo mode
1: Mono: Mono mode

OUTDRIV

Bit 13: Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration..

Allowed values:
0: OnStart: Audio block output driven when SAIEN is set
1: Immediately: Audio block output driven immediately after the setting of this bit

SAIEN

Bit 16: Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit..

Allowed values:
0: Disabled: SAI audio block disabled
1: Enabled: SAI audio block enabled

DMAEN

Bit 17: DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode..

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

NODIV

Bit 19: No fixed divider between MCLK and FS.

Allowed values:
0: MasterClock: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value
1: NoDiv: MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.

MCKDIV

Bits 20-25: Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula:.

OSR

Bit 26: Oversampling ratio for master clock.

MCKEN

Bit 27: Master clock generation enable.

CR2 [B]

Configuration register 2

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

6/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP
rw
CPL
rw
MUTECNT
rw
MUTEVAL
rw
MUTE
rw
TRIS
rw
FFLUSH
w
FTH
rw
Toggle fields

FTH

Bits 0-2: FIFO threshold. This bit is set and cleared by software..

Allowed values:
0: Empty: FIFO empty
1: Quarter1: 1⁄4 FIFO
2: Quarter2: 1⁄2 FIFO
3: Quarter3: 3⁄4 FIFO
4: Full: FIFO full

FFLUSH

Bit 3: FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled..

Allowed values:
0: NoFlush: No FIFO flush
1: Flush: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared

TRIS

Bit 4: Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details..

MUTE

Bit 5: Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks..

Allowed values:
0: Disabled: No mute mode
1: Enabled: Mute mode enabled

MUTEVAL

Bit 6: Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks..

Allowed values:
0: SendZero: Bit value 0 is sent during the mute mode
1: SendLast: Last values are sent during the mute mode

MUTECNT

Bits 7-12: Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details..

CPL

Bit 13: Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm..

Allowed values:
0: OnesComplement: 1’s complement representation
1: TwosComplement: 2’s complement representation

COMP

Bits 14-15: Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected..

Allowed values:
0: NoCompanding: No companding algorithm
2: MuLaw: μ-Law algorithm
3: ALaw: A-Law algorithm

FRCR [B]

This register has no meaning in AC97 and SPDIF audio protocol

Offset: 0x2c, size: 32, reset: 0x00000007, access: Unspecified

3/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSOFF
rw
FSPOL
rw
FSDEF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSALL
rw
FRL
rw
Toggle fields

FRL

Bits 0-7: Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration..

FSALL

Bits 8-14: Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled..

FSDEF

Bit 16: Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled..

FSPOL

Bit 17: Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled..

Allowed values:
0: FallingEdge: FS is active low (falling edge)
1: RisingEdge: FS is active high (rising edge)

FSOFF

Bit 18: Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled..

Allowed values:
0: OnFirst: FS is asserted on the first bit of the slot 0
1: BeforeFirst: FS is asserted one bit before the first bit of the slot 0

SLOTR [B]

This register has no meaning in AC97 and SPDIF audio protocol

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLOTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBSLOT
rw
SLOTSZ
rw
FBOFF
rw
Toggle fields

FBOFF

Bits 0-4: First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode..

SLOTSZ

Bits 6-7: Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode..

Allowed values:
0: DataSize: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)
1: Bit16: 16-bit
2: Bit32: 32-bit

NBSLOT

Bits 8-11: Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode..

SLOTEN

Bits 16-31: Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode..

Allowed values:
0: Inactive: Inactive slot
1: Active: Active slot

IM [B]

Interrupt mask register 2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDETIE
rw
AFSDETIE
rw
CNRDYIE
rw
FREQIE
rw
WCKCFGIE
rw
MUTEDETIE
rw
OVRUDRIE
rw
Toggle fields

OVRUDRIE

Bit 0: Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set..

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

MUTEDETIE

Bit 1: Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode..

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

WCKCFGIE

Bit 2: Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes..

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

FREQIE

Bit 3: FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode,.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

CNRDYIE

Bit 4: Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver..

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

AFSDETIE

Bit 5: Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master..

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

LFSDETIE

Bit 6: Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master..

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

SR [B]

Status register

Offset: 0x38, size: 32, reset: 0x00000008, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLVL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDET
r
AFSDET
r
CNRDY
r
FREQ
r
WCKCFG
r
MUTEDET
r
OVRUDR
r
Toggle fields

OVRUDR

Bit 0: Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register..

Allowed values:
0: NoError: No overrun/underrun error
1: Overrun: Overrun/underrun error detection

MUTEDET

Bit 1: Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register..

Allowed values:
0: NoMute: No MUTE detection on the SD input line
1: Mute: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame

WCKCFG

Bit 2: Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register..

Allowed values:
0: Correct: Clock configuration is correct
1: Wrong: Clock configuration does not respect the rule concerning the frame length specification

FREQ

Bit 3: FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register..

Allowed values:
0: NoRequest: No FIFO request
1: Request: FIFO request to read or to write the SAI_xDR

CNRDY

Bit 4: Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register..

Allowed values:
0: Ready: External AC’97 Codec is ready
1: NotReady: External AC’97 Codec is not ready

AFSDET

Bit 5: Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register..

Allowed values:
0: NoError: No error
1: EarlySync: Frame synchronization signal is detected earlier than expected

LFSDET

Bit 6: Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register.

Allowed values:
0: NoError: No error
1: NoSync: Frame synchronization signal is not present at the right time

FLVL

Bits 16-18: FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver:.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: FIFO <= 1⁄4 but not empty
2: Quarter2: 1⁄4 < FIFO <= 1⁄2
3: Quarter3: 1⁄2 < FIFO <= 3⁄4
4: Quarter4: 3⁄4 < FIFO but not full
5: Full: FIFO full

CLRFR [B]

Clear flag register

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLFSDET
w
CAFSDET
w
CCNRDY
w
CWCKCFG
w
CMUTEDET
w
COVRUDR
w
Toggle fields

COVRUDR

Bit 0: Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0..

Allowed values:
1: Clear: Clears the OVRUDR flag

CMUTEDET

Bit 1: Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0..

Allowed values:
1: Clear: Clears the MUTEDET flag

CWCKCFG

Bit 2: Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0..

Allowed values:
1: Clear: Clears the WCKCFG flag

CCNRDY

Bit 4: Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0..

Allowed values:
1: Clear: Clears the CNRDY flag

CAFSDET

Bit 5: Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0..

Allowed values:
1: Clear: Clears the AFSDET flag

CLFSDET

Bit 6: Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0..

Allowed values:
1: Clear: Clears the LFSDET flag

DR [B]

Data register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty..

PDMCR

PDM control register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKEN4
rw
CKEN3
rw
CKEN2
rw
CKEN1
rw
MICNBR
rw
PDMEN
rw
Toggle fields

PDMEN

Bit 0: PDM enable.

MICNBR

Bits 4-5: Number of microphones.

CKEN1

Bit 8: Clock enable of bitstream clock number 1.

CKEN2

Bit 9: Clock enable of bitstream clock number 2.

CKEN3

Bit 10: Clock enable of bitstream clock number 3.

CKEN4

Bit 11: Clock enable of bitstream clock number 4.

PDMDLY

PDM delay register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLYM[4]R
rw
DLYM[4]L
rw
DLYM[3]R
rw
DLYM[3]L
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYM[2]R
rw
DLYM[2]L
rw
DLYM[1]R
rw
DLYM[1]L
rw
Toggle fields

DLYM[1]L

Bits 0-2: Delay line adjust for first microphone of pair 1.

DLYM[1]R

Bits 4-6: Delay line adjust for second microphone of pair 1.

DLYM[2]L

Bits 8-10: Delay line adjust for first microphone of pair 2.

DLYM[2]R

Bits 12-14: Delay line adjust for second microphone of pair 2.

DLYM[3]L

Bits 16-18: Delay line adjust for first microphone of pair 3.

DLYM[3]R

Bits 20-22: Delay line adjust for second microphone of pair 3.

DLYM[4]L

Bits 24-26: Delay line adjust for first microphone of pair 4.

DLYM[4]R

Bits 28-30: Delay line adjust for second microphone of pair 4.

SDMMC1

0x52007000: SDMMC1

38/125 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 POWER
0x4 CLKCR
0x8 ARGR
0xc CMDR
0x10 RESPCMDR
0x14 RESP1R
0x18 RESP2R
0x1c RESP3R
0x20 RESP4R
0x24 DTIMER
0x28 DLENR
0x2c DCTRL
0x30 DCNTR
0x34 STAR
0x38 ICR
0x3c MASKR
0x40 ACKTIMER
0x50 IDMACTRLR
0x54 IDMABSIZER
0x58 IDMABASE0R
0x5c IDMABASE1R
0x80 FIFOR
0x3f4 VER
0x3f8 ID
Toggle registers

POWER

SDMMC power control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIRPOL
rw
VSWITCHEN
rw
VSWITCH
rw
PWRCTRL
rw
Toggle fields

PWRCTRL

Bits 0-1: SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL?11). These bits are used to define the functional state of the SDMMC signals: Any further write will be ignored, PWRCTRL value will keep 11..

VSWITCH

Bit 2: Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence:.

VSWITCHEN

Bit 3: Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response:.

DIRPOL

Bit 4: Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00)..

CLKCR

The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width.

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SELCLKRX
rw
BUSSPEED
rw
DDR
rw
HWFC_EN
rw
NEGEDGE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WIDBUS
rw
PWRSAV
rw
CLKDIV
rw
Toggle fields

CLKDIV

Bits 0-9: Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc...

PWRSAV

Bit 12: Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:.

WIDBUS

Bits 14-15: Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0).

NEGEDGE

Bit 16: SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division &gt;1 (CLKDIV &gt; 0) &amp; DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge..

HWFC_EN

Bit 17: Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11..

DDR

Bit 18: Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS &gt; 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division &gt;1. (CLKDIV &gt; 0).

BUSSPEED

Bit 19: Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0).

SELCLKRX

Bits 20-21: Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0).

ARGR

The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CMDARG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMDARG
rw
Toggle fields

CMDARG

Bits 0-31: Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register..

CMDR

The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM).

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CMDSUSPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOTEN
rw
BOOTMODE
rw
DTHOLD
rw
CPSMEN
rw
WAITPEND
rw
WAITINT
rw
WAITRESP
rw
CMDSTOP
rw
CMDTRANS
rw
CMDINDEX
rw
Toggle fields

CMDINDEX

Bits 0-5: Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message..

CMDTRANS

Bit 6: The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent..

CMDSTOP

Bit 7: The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent..

WAITRESP

Bits 8-9: Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response..

WAITINT

Bit 10: CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode..

WAITPEND

Bit 11: CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card..

CPSMEN

Bit 12: Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0..

DTHOLD

Bit 13: Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state..

BOOTMODE

Bit 14: Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0).

BOOTEN

Bit 15: Enable boot mode procedure..

CMDSUSPEND

Bit 16: The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1..

RESPCMDR

SDMMC command response register

Offset: 0x10, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESPCMD
r
Toggle fields

RESPCMD

Bits 0-5: Response command index.

RESP1R

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS1
r
Toggle fields

CARDSTATUS1

Bits 0-31: see Table 432.

RESP2R

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS2
r
Toggle fields

CARDSTATUS2

Bits 0-31: see Table404..

RESP3R

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS3
r
Toggle fields

CARDSTATUS3

Bits 0-31: see Table404..

RESP4R

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS4
r
Toggle fields

CARDSTATUS4

Bits 0-31: see Table404..

DTIMER

The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set.

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATATIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATATIME
rw
Toggle fields

DATATIME

Bits 0-31: Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods..

DLENR

The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts.

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATALENGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATALENGTH
rw
Toggle fields

DATALENGTH

Bits 0-24: Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0..

DCTRL

The SDMMC_DCTRL register control the data path state machine (DPSM).

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFORST
rw
BOOTACKEN
rw
SDIOEN
rw
RWMOD
rw
RWSTOP
rw
RWSTART
rw
DBLOCKSIZE
rw
DTMODE
rw
DTDIR
rw
DTEN
rw
Toggle fields

DTEN

Bit 0: Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards..

DTDIR

Bit 1: Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

DTMODE

Bits 2-3: Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

DBLOCKSIZE

Bits 4-7: Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered).

RWSTART

Bit 8: Read wait start. If this bit is set, read wait operation starts..

RWSTOP

Bit 9: Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state..

RWMOD

Bit 10: Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

SDIOEN

Bit 11: SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation..

BOOTACKEN

Bit 12: Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

FIFORST

Bit 13: FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs..

DCNTR

The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set.

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATACOUNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATACOUNT
r
Toggle fields

DATACOUNT

Bits 0-24: Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect..

STAR

The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

29/29 fields covered.

Toggle fields

CCRCFAIL

Bit 0: Command response received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

DCRCFAIL

Bit 1: Data block sent/received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

CTIMEOUT

Bit 2: Command response timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. The Command Timeout period has a fixed value of 64 SDMMC_CK clock periods..

DTIMEOUT

Bit 3: Data timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

TXUNDERR

Bit 4: Transmit FIFO underrun error or IDMA read transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

RXOVERR

Bit 5: Received FIFO overrun error or IDMA write transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

CMDREND

Bit 6: Command response received (CRC check passed, or no CRC). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

CMDSENT

Bit 7: Command sent (no response required). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

DATAEND

Bit 8: Data transfer ended correctly. (data counter, DATACOUNT is zero and no errors occur). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

DHOLD

Bit 9: Data transfer Hold. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

DBCKEND

Bit 10: Data block sent/received. (CRC check passed) and DPSM moves to the READWAIT state. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

DABORT

Bit 11: Data transfer aborted by CMD12. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

DPSMACT

Bit 12: Data path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt..

CPSMACT

Bit 13: Command path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt..

TXFIFOHE

Bit 14: Transmit FIFO half empty At least half the number of words can be written into the FIFO. This bit is cleared when the FIFO becomes half+1 full..

RXFIFOHF

Bit 15: Receive FIFO half full There are at least half the number of words in the FIFO. This bit is cleared when the FIFO becomes half+1 empty..

TXFIFOF

Bit 16: Transmit FIFO full This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes empty..

RXFIFOF

Bit 17: Receive FIFO full This bit is cleared when one FIFO location becomes empty..

TXFIFOE

Bit 18: Transmit FIFO empty This bit is cleared when one FIFO location becomes full..

RXFIFOE

Bit 19: Receive FIFO empty This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes full..

BUSYD0

Bit 20: Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response. This bit is reset to not busy when the SDMMCD0 line changes from busy to not busy. This bit does not signal busy due to data transfer. This is a hardware status flag only, it does not generate an interrupt..

BUSYD0END

Bit 21: end of SDMMC_D0 Busy following a CMD response detected. This indicates only end of busy following a CMD response. This bit does not signal busy due to data transfer. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

SDIOIT

Bit 22: SDIO interrupt received. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

ACKFAIL

Bit 23: Boot acknowledgment received (boot acknowledgment check fail). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

ACKTIMEOUT

Bit 24: Boot acknowledgment timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

VSWEND

Bit 25: Voltage switch critical timing section completion. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

CKSTOP

Bit 26: SDMMC_CK stopped in Voltage switch procedure. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

IDMATE

Bit 27: IDMA transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

IDMABTC

Bit 28: IDMA buffer transfer complete. interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

ICR

The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register.

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

Toggle fields

CCRCFAILC

Bit 0: CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag..

DCRCFAILC

Bit 1: DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag..

CTIMEOUTC

Bit 2: CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag..

DTIMEOUTC

Bit 3: DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag..

TXUNDERRC

Bit 4: TXUNDERR flag clear bit Set by software to clear TXUNDERR flag..

RXOVERRC

Bit 5: RXOVERR flag clear bit Set by software to clear the RXOVERR flag..

CMDRENDC

Bit 6: CMDREND flag clear bit Set by software to clear the CMDREND flag..

CMDSENTC

Bit 7: CMDSENT flag clear bit Set by software to clear the CMDSENT flag..

DATAENDC

Bit 8: DATAEND flag clear bit Set by software to clear the DATAEND flag..

DHOLDC

Bit 9: DHOLD flag clear bit Set by software to clear the DHOLD flag..

DBCKENDC

Bit 10: DBCKEND flag clear bit Set by software to clear the DBCKEND flag..

DABORTC

Bit 11: DABORT flag clear bit Set by software to clear the DABORT flag..

BUSYD0ENDC

Bit 21: BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag..

SDIOITC

Bit 22: SDIOIT flag clear bit Set by software to clear the SDIOIT flag..

ACKFAILC

Bit 23: ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag..

ACKTIMEOUTC

Bit 24: ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag..

VSWENDC

Bit 25: VSWEND flag clear bit Set by software to clear the VSWEND flag..

CKSTOPC

Bit 26: CKSTOP flag clear bit Set by software to clear the CKSTOP flag..

IDMATEC

Bit 27: IDMA transfer error clear bit Set by software to clear the IDMATE flag..

IDMABTCC

Bit 28: IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag..

MASKR

The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1.

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/23 fields covered.

Toggle fields

CCRCFAILIE

Bit 0: Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure..

DCRCFAILIE

Bit 1: Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure..

CTIMEOUTIE

Bit 2: Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout..

DTIMEOUTIE

Bit 3: Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout..

TXUNDERRIE

Bit 4: Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error..

RXOVERRIE

Bit 5: Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error..

CMDRENDIE

Bit 6: Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response..

CMDSENTIE

Bit 7: Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command..

DATAENDIE

Bit 8: Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end..

DHOLDIE

Bit 9: Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state..

DBCKENDIE

Bit 10: Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end..

DABORTIE

Bit 11: Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted..

TXFIFOHEIE

Bit 14: Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty..

RXFIFOHFIE

Bit 15: Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full..

RXFIFOFIE

Bit 17: Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full..

TXFIFOEIE

Bit 18: Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty..

BUSYD0ENDIE

Bit 21: BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response..

SDIOITIE

Bit 22: SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt..

ACKFAILIE

Bit 23: Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail..

ACKTIMEOUTIE

Bit 24: Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout..

VSWENDIE

Bit 25: Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion..

CKSTOPIE

Bit 26: Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped..

IDMABTCIE

Bit 28: IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer..

ACKTIMER

The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set.

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACKTIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACKTIME
rw
Toggle fields

ACKTIME

Bits 0-24: Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods..

IDMACTRLR

The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMABACT
rw
IDMABMODE
rw
IDMAEN
rw
Toggle fields

IDMAEN

Bit 0: IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

IDMABMODE

Bit 1: Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

IDMABACT

Bit 2: Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware..

IDMABSIZER

The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration.

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMABNDT
rw
Toggle fields

IDMABNDT

Bits 5-12: Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

IDMABASE0R

The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration.

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDMABASE0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMABASE0
rw
Toggle fields

IDMABASE0

Bits 0-31: Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1)..

IDMABASE1R

The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address.

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDMABASE1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMABASE1
rw
Toggle fields

IDMABASE1

Bits 0-31: Buffer 1 memory base address, shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0)..

FIFOR

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words..

VER

SDMMC IP version register

Offset: 0x3f4, size: 32, reset: 0x00000010, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r
MINREV
r
Toggle fields

MINREV

Bits 0-3: IP minor revision number..

MAJREV

Bits 4-7: IP major revision number..

ID

SDMMC IP identification register

Offset: 0x3f8, size: 32, reset: 0x00140022, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IP_ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IP_ID
r
Toggle fields

IP_ID

Bits 0-31: SDMMC IP identification..

SDMMC2

0x48022400: SDMMC1

38/125 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 POWER
0x4 CLKCR
0x8 ARGR
0xc CMDR
0x10 RESPCMDR
0x14 RESP1R
0x18 RESP2R
0x1c RESP3R
0x20 RESP4R
0x24 DTIMER
0x28 DLENR
0x2c DCTRL
0x30 DCNTR
0x34 STAR
0x38 ICR
0x3c MASKR
0x40 ACKTIMER
0x50 IDMACTRLR
0x54 IDMABSIZER
0x58 IDMABASE0R
0x5c IDMABASE1R
0x80 FIFOR
0x3f4 VER
0x3f8 ID
Toggle registers

POWER

SDMMC power control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIRPOL
rw
VSWITCHEN
rw
VSWITCH
rw
PWRCTRL
rw
Toggle fields

PWRCTRL

Bits 0-1: SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL?11). These bits are used to define the functional state of the SDMMC signals: Any further write will be ignored, PWRCTRL value will keep 11..

VSWITCH

Bit 2: Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence:.

VSWITCHEN

Bit 3: Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response:.

DIRPOL

Bit 4: Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00)..

CLKCR

The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width.

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SELCLKRX
rw
BUSSPEED
rw
DDR
rw
HWFC_EN
rw
NEGEDGE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WIDBUS
rw
PWRSAV
rw
CLKDIV
rw
Toggle fields

CLKDIV

Bits 0-9: Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc...

PWRSAV

Bit 12: Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:.

WIDBUS

Bits 14-15: Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0).

NEGEDGE

Bit 16: SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division &gt;1 (CLKDIV &gt; 0) &amp; DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge..

HWFC_EN

Bit 17: Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11..

DDR

Bit 18: Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS &gt; 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division &gt;1. (CLKDIV &gt; 0).

BUSSPEED

Bit 19: Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0).

SELCLKRX

Bits 20-21: Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0).

ARGR

The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CMDARG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMDARG
rw
Toggle fields

CMDARG

Bits 0-31: Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register..

CMDR

The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM).

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CMDSUSPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOTEN
rw
BOOTMODE
rw
DTHOLD
rw
CPSMEN
rw
WAITPEND
rw
WAITINT
rw
WAITRESP
rw
CMDSTOP
rw
CMDTRANS
rw
CMDINDEX
rw
Toggle fields

CMDINDEX

Bits 0-5: Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message..

CMDTRANS

Bit 6: The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent..

CMDSTOP

Bit 7: The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent..

WAITRESP

Bits 8-9: Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response..

WAITINT

Bit 10: CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode..

WAITPEND

Bit 11: CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card..

CPSMEN

Bit 12: Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0..

DTHOLD

Bit 13: Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state..

BOOTMODE

Bit 14: Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0).

BOOTEN

Bit 15: Enable boot mode procedure..

CMDSUSPEND

Bit 16: The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1..

RESPCMDR

SDMMC command response register

Offset: 0x10, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESPCMD
r
Toggle fields

RESPCMD

Bits 0-5: Response command index.

RESP1R

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS1
r
Toggle fields

CARDSTATUS1

Bits 0-31: see Table 432.

RESP2R

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS2
r
Toggle fields

CARDSTATUS2

Bits 0-31: see Table404..

RESP3R

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS3
r
Toggle fields

CARDSTATUS3

Bits 0-31: see Table404..

RESP4R

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS4
r
Toggle fields

CARDSTATUS4

Bits 0-31: see Table404..

DTIMER

The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set.

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATATIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATATIME
rw
Toggle fields

DATATIME

Bits 0-31: Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods..

DLENR

The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts.

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATALENGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATALENGTH
rw
Toggle fields

DATALENGTH

Bits 0-24: Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0..

DCTRL

The SDMMC_DCTRL register control the data path state machine (DPSM).

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFORST
rw
BOOTACKEN
rw
SDIOEN
rw
RWMOD
rw
RWSTOP
rw
RWSTART
rw
DBLOCKSIZE
rw
DTMODE
rw
DTDIR
rw
DTEN
rw
Toggle fields

DTEN

Bit 0: Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards..

DTDIR

Bit 1: Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

DTMODE

Bits 2-3: Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

DBLOCKSIZE

Bits 4-7: Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered).

RWSTART

Bit 8: Read wait start. If this bit is set, read wait operation starts..

RWSTOP

Bit 9: Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state..

RWMOD

Bit 10: Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

SDIOEN

Bit 11: SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation..

BOOTACKEN

Bit 12: Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

FIFORST

Bit 13: FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs..

DCNTR

The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set.

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATACOUNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATACOUNT
r
Toggle fields

DATACOUNT

Bits 0-24: Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect..

STAR

The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

29/29 fields covered.

Toggle fields

CCRCFAIL

Bit 0: Command response received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

DCRCFAIL

Bit 1: Data block sent/received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

CTIMEOUT

Bit 2: Command response timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. The Command Timeout period has a fixed value of 64 SDMMC_CK clock periods..

DTIMEOUT

Bit 3: Data timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

TXUNDERR

Bit 4: Transmit FIFO underrun error or IDMA read transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

RXOVERR

Bit 5: Received FIFO overrun error or IDMA write transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

CMDREND

Bit 6: Command response received (CRC check passed, or no CRC). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

CMDSENT

Bit 7: Command sent (no response required). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

DATAEND

Bit 8: Data transfer ended correctly. (data counter, DATACOUNT is zero and no errors occur). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

DHOLD

Bit 9: Data transfer Hold. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

DBCKEND

Bit 10: Data block sent/received. (CRC check passed) and DPSM moves to the READWAIT state. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

DABORT

Bit 11: Data transfer aborted by CMD12. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

DPSMACT

Bit 12: Data path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt..

CPSMACT

Bit 13: Command path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt..

TXFIFOHE

Bit 14: Transmit FIFO half empty At least half the number of words can be written into the FIFO. This bit is cleared when the FIFO becomes half+1 full..

RXFIFOHF

Bit 15: Receive FIFO half full There are at least half the number of words in the FIFO. This bit is cleared when the FIFO becomes half+1 empty..

TXFIFOF

Bit 16: Transmit FIFO full This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes empty..

RXFIFOF

Bit 17: Receive FIFO full This bit is cleared when one FIFO location becomes empty..

TXFIFOE

Bit 18: Transmit FIFO empty This bit is cleared when one FIFO location becomes full..

RXFIFOE

Bit 19: Receive FIFO empty This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes full..

BUSYD0

Bit 20: Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response. This bit is reset to not busy when the SDMMCD0 line changes from busy to not busy. This bit does not signal busy due to data transfer. This is a hardware status flag only, it does not generate an interrupt..

BUSYD0END

Bit 21: end of SDMMC_D0 Busy following a CMD response detected. This indicates only end of busy following a CMD response. This bit does not signal busy due to data transfer. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

SDIOIT

Bit 22: SDIO interrupt received. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

ACKFAIL

Bit 23: Boot acknowledgment received (boot acknowledgment check fail). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

ACKTIMEOUT

Bit 24: Boot acknowledgment timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

VSWEND

Bit 25: Voltage switch critical timing section completion. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

CKSTOP

Bit 26: SDMMC_CK stopped in Voltage switch procedure. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

IDMATE

Bit 27: IDMA transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

IDMABTC

Bit 28: IDMA buffer transfer complete. interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

ICR

The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register.

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

Toggle fields

CCRCFAILC

Bit 0: CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag..

DCRCFAILC

Bit 1: DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag..

CTIMEOUTC

Bit 2: CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag..

DTIMEOUTC

Bit 3: DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag..

TXUNDERRC

Bit 4: TXUNDERR flag clear bit Set by software to clear TXUNDERR flag..

RXOVERRC

Bit 5: RXOVERR flag clear bit Set by software to clear the RXOVERR flag..

CMDRENDC

Bit 6: CMDREND flag clear bit Set by software to clear the CMDREND flag..

CMDSENTC

Bit 7: CMDSENT flag clear bit Set by software to clear the CMDSENT flag..

DATAENDC

Bit 8: DATAEND flag clear bit Set by software to clear the DATAEND flag..

DHOLDC

Bit 9: DHOLD flag clear bit Set by software to clear the DHOLD flag..

DBCKENDC

Bit 10: DBCKEND flag clear bit Set by software to clear the DBCKEND flag..

DABORTC

Bit 11: DABORT flag clear bit Set by software to clear the DABORT flag..

BUSYD0ENDC

Bit 21: BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag..

SDIOITC

Bit 22: SDIOIT flag clear bit Set by software to clear the SDIOIT flag..

ACKFAILC

Bit 23: ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag..

ACKTIMEOUTC

Bit 24: ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag..

VSWENDC

Bit 25: VSWEND flag clear bit Set by software to clear the VSWEND flag..

CKSTOPC

Bit 26: CKSTOP flag clear bit Set by software to clear the CKSTOP flag..

IDMATEC

Bit 27: IDMA transfer error clear bit Set by software to clear the IDMATE flag..

IDMABTCC

Bit 28: IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag..

MASKR

The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1.

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/23 fields covered.

Toggle fields

CCRCFAILIE

Bit 0: Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure..

DCRCFAILIE

Bit 1: Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure..

CTIMEOUTIE

Bit 2: Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout..

DTIMEOUTIE

Bit 3: Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout..

TXUNDERRIE

Bit 4: Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error..

RXOVERRIE

Bit 5: Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error..

CMDRENDIE

Bit 6: Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response..

CMDSENTIE

Bit 7: Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command..

DATAENDIE

Bit 8: Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end..

DHOLDIE

Bit 9: Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state..

DBCKENDIE

Bit 10: Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end..

DABORTIE

Bit 11: Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted..

TXFIFOHEIE

Bit 14: Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty..

RXFIFOHFIE

Bit 15: Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full..

RXFIFOFIE

Bit 17: Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full..

TXFIFOEIE

Bit 18: Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty..

BUSYD0ENDIE

Bit 21: BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response..

SDIOITIE

Bit 22: SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt..

ACKFAILIE

Bit 23: Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail..

ACKTIMEOUTIE

Bit 24: Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout..

VSWENDIE

Bit 25: Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion..

CKSTOPIE

Bit 26: Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped..

IDMABTCIE

Bit 28: IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer..

ACKTIMER

The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set.

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACKTIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACKTIME
rw
Toggle fields

ACKTIME

Bits 0-24: Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods..

IDMACTRLR

The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMABACT
rw
IDMABMODE
rw
IDMAEN
rw
Toggle fields

IDMAEN

Bit 0: IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

IDMABMODE

Bit 1: Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

IDMABACT

Bit 2: Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware..

IDMABSIZER

The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration.

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMABNDT
rw
Toggle fields

IDMABNDT

Bits 5-12: Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

IDMABASE0R

The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration.

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDMABASE0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMABASE0
rw
Toggle fields

IDMABASE0

Bits 0-31: Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1)..

IDMABASE1R

The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address.

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDMABASE1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMABASE1
rw
Toggle fields

IDMABASE1

Bits 0-31: Buffer 1 memory base address, shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0)..

FIFOR

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words..

VER

SDMMC IP version register

Offset: 0x3f4, size: 32, reset: 0x00000010, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r
MINREV
r
Toggle fields

MINREV

Bits 0-3: IP minor revision number..

MAJREV

Bits 4-7: IP major revision number..

ID

SDMMC IP identification register

Offset: 0x3f8, size: 32, reset: 0x00140022, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IP_ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IP_ID
r
Toggle fields

IP_ID

Bits 0-31: SDMMC IP identification..

SPDIFRX

0x40004000: Receiver Interface

33/59 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 IMR
0x8 SR
0xc IFCR
0x10 DR_00
0x10 DR_01
0x10 DR_10
0x14 CSR
0x18 DIR
0x3f4 VERR
0x3f8 IDR
0x3fc SIDR
Toggle registers

CR

Control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CKSBKPEN
rw
CKSEN
rw
INSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WFA
rw
NBTR
rw
CHSEL
rw
CBDMAEN
rw
PTMSK
rw
CUMSK
rw
VMSK
rw
PMSK
rw
DRFMT
rw
RXSTEO
rw
RXDMAEN
rw
SPDIFRXEN
rw
Toggle fields

SPDIFRXEN

Bits 0-1: Peripheral Block Enable.

RXDMAEN

Bit 2: Receiver DMA ENable for data flow.

RXSTEO

Bit 3: STerEO Mode.

DRFMT

Bits 4-5: RX Data format.

PMSK

Bit 6: Mask Parity error bit.

VMSK

Bit 7: Mask of Validity bit.

CUMSK

Bit 8: Mask of channel status and user bits.

PTMSK

Bit 9: Mask of Preamble Type bits.

CBDMAEN

Bit 10: Control Buffer DMA ENable for control flow.

CHSEL

Bit 11: Channel Selection.

NBTR

Bits 12-13: Maximum allowed re-tries during synchronization phase.

WFA

Bit 14: Wait For Activity.

INSEL

Bits 16-18: input selection.

CKSEN

Bit 20: Symbol Clock Enable.

CKSBKPEN

Bit 21: Backup Symbol Clock Enable.

IMR

Interrupt mask register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IFEIE
rw
SYNCDIE
rw
SBLKIE
rw
OVRIE
rw
PERRIE
rw
CSRNEIE
rw
RXNEIE
rw
Toggle fields

RXNEIE

Bit 0: RXNE interrupt enable.

CSRNEIE

Bit 1: Control Buffer Ready Interrupt Enable.

PERRIE

Bit 2: Parity error interrupt enable.

OVRIE

Bit 3: Overrun error Interrupt Enable.

SBLKIE

Bit 4: Synchronization Block Detected Interrupt Enable.

SYNCDIE

Bit 5: Synchronization Done.

IFEIE

Bit 6: Serial Interface Error Interrupt Enable.

SR

Status register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WIDTH5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TERR
r
SERR
r
FERR
r
SYNCD
r
SBD
r
OVR
r
PERR
r
CSRNE
r
RXNE
r
Toggle fields

RXNE

Bit 0: Read data register not empty.

CSRNE

Bit 1: Control Buffer register is not empty.

PERR

Bit 2: Parity error.

OVR

Bit 3: Overrun error.

SBD

Bit 4: Synchronization Block Detected.

SYNCD

Bit 5: Synchronization Done.

FERR

Bit 6: Framing error.

SERR

Bit 7: Synchronization error.

TERR

Bit 8: Time-out error.

WIDTH5

Bits 16-30: Duration of 5 symbols counted with SPDIF_CLK.

IFCR

Interrupt Flag Clear register

Offset: 0xc, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNCDCF
w
SBDCF
w
OVRCF
w
PERRCF
w
Toggle fields

PERRCF

Bit 2: Clears the Parity error flag.

OVRCF

Bit 3: Clears the Overrun error flag.

SBDCF

Bit 4: Clears the Synchronization Block Detected flag.

SYNCDCF

Bit 5: Clears the Synchronization Done flag.

DR_00

Data input register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PT
r
C
r
U
r
V
r
PE
r
DR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
r
Toggle fields

DR

Bits 0-23: Parity Error bit.

PE

Bit 24: Parity Error bit.

V

Bit 25: Validity bit.

U

Bit 26: User bit.

C

Bit 27: Channel Status bit.

PT

Bits 28-29: Preamble Type.

DR_01

Data input register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
r
PT
r
C
r
U
r
V
r
PE
r
Toggle fields

PE

Bit 0: Parity Error bit.

V

Bit 1: Validity bit.

U

Bit 2: User bit.

C

Bit 3: Channel Status bit.

PT

Bits 4-5: Preamble Type.

DR

Bits 8-31: Data value.

DR_10

Data input register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DRNL2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DRNL1
r
Toggle fields

DRNL1

Bits 0-15: Data value.

DRNL2

Bits 16-31: Data value.

CSR

Channel Status register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SOB
r
CS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USR
r
Toggle fields

USR

Bits 0-15: User data information.

CS

Bits 16-23: Channel A status information.

SOB

Bit 24: Start Of Block.

DIR

Debug Information register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TLO
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
THI
r
Toggle fields

THI

Bits 0-12: Threshold HIGH.

TLO

Bits 16-28: Threshold LOW.

VERR

SPDIFRX version register

Offset: 0x3f4, size: 32, reset: 0x00000012, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r
MINREV
r
Toggle fields

MINREV

Bits 0-3: Minor revision.

MAJREV

Bits 4-7: Major revision.

IDR

SPDIFRX identification register

Offset: 0x3f8, size: 32, reset: 0x00130041, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: SPDIFRX identifier.

SIDR

SPDIFRX size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: Size identification.

SPI1

0x40013000: Serial peripheral interface

93/94 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CFG1
0xc CFG2
0x10 IER
0x14 SR
0x18 IFCR
0x20 TXDR
0x20 (16-bit) TXDR16
0x20 (8-bit) TXDR8
0x30 RXDR
0x30 (16-bit) RXDR16
0x30 (8-bit) RXDR8
0x40 CRCPOLY
0x44 TXCRC
0x48 RXCRC
0x4c UDRDR
0x50 I2SCFGR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IOLOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCRCINI
rw
RCRCINI
rw
CRC33_17
rw
SSI
rw
HDDIR
rw
CSUSP
w
CSTART
rw
MASRX
rw
SPE
rw
Toggle fields

SPE

Bit 0: Serial Peripheral Enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

MASRX

Bit 8: Master automatic SUSP in Receive mode.

Allowed values:
0: Disabled: Automatic suspend in master receive-only mode disabled
1: Enabled: Automatic suspend in master receive-only mode enabled

CSTART

Bit 9: Master transfer start.

Allowed values:
0: NotStarted: Do not start master transfer
1: Started: Start master transfer

CSUSP

Bit 10: Master SUSPend request.

Allowed values:
0: NotRequested: Do not request master suspend
1: Requested: Request master suspend

HDDIR

Bit 11: Rx/Tx direction at Half-duplex mode.

Allowed values:
0: Receiver: Receiver in half duplex mode
1: Transmitter: Transmitter in half duplex mode

SSI

Bit 12: Internal SS signal input level.

Allowed values:
0: SlaveSelected: 0 is forced onto the SS signal and the I/O value of the SS pin is ignored
1: SlaveNotSelected: 1 is forced onto the SS signal and the I/O value of the SS pin is ignored

CRC33_17

Bit 13: 32-bit CRC polynomial configuration.

Allowed values:
0: Disabled: Full size (33/17 bit) CRC polynomial is not used
1: Enabled: Full size (33/17 bit) CRC polynomial is used

RCRCINI

Bit 14: CRC calculation initialization pattern control for receiver.

Allowed values:
0: AllZeros: All zeros RX CRC initialization pattern
1: AllOnes: All ones RX CRC initialization pattern

TCRCINI

Bit 15: CRC calculation initialization pattern control for transmitter.

Allowed values:
0: AllZeros: All zeros TX CRC initialization pattern
1: AllOnes: All ones TX CRC initialization pattern

IOLOCK

Bit 16: Locking the AF configuration of associated IOs.

Allowed values:
0: Unlocked: IO configuration unlocked
1: Locked: IO configuration locked

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSER
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSIZE
rw
Toggle fields

TSIZE

Bits 0-15: Number of data at current transfer.

Allowed values: 0x0-0xffff

TSER

Bits 16-31: Number of data transfer extension to be reload into TSIZE just when a previous.

Allowed values: 0x0-0xffff

CFG1

configuration register 1

Offset: 0x8, size: 32, reset: 0x00070007, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBR
rw
CRCEN
rw
CRCSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDMAEN
rw
RXDMAEN
rw
UDRDET
rw
UDRCFG
rw
FTHLV
rw
DSIZE
rw
Toggle fields

DSIZE

Bits 0-4: Number of bits in at single SPI data frame.

Allowed values: 0x0-0x1f

FTHLV

Bits 5-8: threshold level.

Allowed values:
0: OneFrame: 1 frame
1: TwoFrames: 2 frames
2: ThreeFrames: 3 frames
3: FourFrames: 4 frames
4: FiveFrames: 5 frames
5: SixFrames: 6 frames
6: SevenFrames: 7 frames
7: EightFrames: 8 frames
8: NineFrames: 9 frames
9: TenFrames: 10 frames
10: ElevenFrames: 11 frames
11: TwelveFrames: 12 frames
12: ThirteenFrames: 13 frames
13: FourteenFrames: 14 frames
14: FifteenFrames: 15 frames
15: SixteenFrames: 16 frames

UDRCFG

Bits 9-10: Behavior of slave transmitter at underrun condition.

Allowed values:
0: Constant: Slave sends a constant underrun pattern
1: RepeatReceived: Slave repeats last received data frame from master
2: RepeatTransmitted: Slave repeats last transmitted data frame

UDRDET

Bits 11-12: Detection of underrun condition at slave transmitter.

Allowed values:
0: StartOfFrame: Underrun is detected at begin of data frame
1: EndOfFrame: Underrun is detected at end of last data frame
2: StartOfSlaveSelect: Underrun is detected at begin of active SS signal

RXDMAEN

Bit 14: Rx DMA stream enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 15: Tx DMA stream enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

CRCSIZE

Bits 16-20: Length of CRC frame to be transacted and compared.

Allowed values: 0x0-0x1f

CRCEN

Bit 22: Hardware CRC computation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

MBR

Bits 28-30: Master baud rate.

Allowed values:
0: Div2: f_spi_ker_ck / 2
1: Div4: f_spi_ker_ck / 4
2: Div8: f_spi_ker_ck / 8
3: Div16: f_spi_ker_ck / 16
4: Div32: f_spi_ker_ck / 32
5: Div64: f_spi_ker_ck / 64
6: Div128: f_spi_ker_ck / 128
7: Div256: f_spi_ker_ck / 256

CFG2

configuration register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFCNTR
rw
SSOM
rw
SSOE
rw
SSIOP
rw
SSM
rw
CPOL
rw
CPHA
rw
LSBFRST
rw
MASTER
rw
SP
rw
COMM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSWP
rw
MIDI
rw
MSSI
rw
Toggle fields

MSSI

Bits 0-3: Master SS Idleness.

Allowed values: 0x0-0xf

MIDI

Bits 4-7: Master Inter-Data Idleness.

Allowed values: 0x0-0xf

IOSWP

Bit 15: Swap functionality of MISO and MOSI pins.

Allowed values:
0: Disabled: MISO and MOSI not swapped
1: Enabled: MISO and MOSI swapped

COMM

Bits 17-18: SPI Communication Mode.

Allowed values:
0: FullDuplex: Full duplex
1: Transmitter: Simplex transmitter only
2: Receiver: Simplex receiver only
3: HalfDuplex: Half duplex

SP

Bits 19-21: Serial Protocol.

Allowed values:
0: Motorola: Motorola SPI protocol
1: TI: TI SPI protocol

MASTER

Bit 22: SPI Master.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

LSBFRST

Bit 23: Data frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

CPHA

Bit 24: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 25: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

SSM

Bit 26: Software management of SS signal input.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

SSIOP

Bit 28: SS input/output polarity.

Allowed values:
0: ActiveLow: Low level is active for SS signal
1: ActiveHigh: High level is active for SS signal

SSOE

Bit 29: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

SSOM

Bit 30: SS output management in master mode.

Allowed values:
0: Asserted: SS is asserted until data transfer complete
1: NotAsserted: Data frames interleaved with SS not asserted during MIDI

AFCNTR

Bit 31: Alternate function GPIOs control.

Allowed values:
0: NotControlled: Peripheral takes no control of GPIOs while disabled
1: Controlled: Peripheral controls GPIOs while disabled

IER

Interrupt Enable Register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

11/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSERFIE
rw
MODFIE
rw
TIFREIE
rw
CRCEIE
rw
OVRIE
rw
UDRIE
rw
TXTFIE
rw
EOTIE
rw
DXPIE
rw
TXPIE
rw
RXPIE
rw
Toggle fields

RXPIE

Bit 0: RXP Interrupt Enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TXPIE

Bit 1: TXP interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

DXPIE

Bit 2: DXP interrupt enabled.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

EOTIE

Bit 3: EOT, SUSP and TXC interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TXTFIE

Bit 4: TXTFIE interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

UDRIE

Bit 5: UDR interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

OVRIE

Bit 6: OVR interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CRCEIE

Bit 7: CRC Interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TIFREIE

Bit 8: TIFRE interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

MODFIE

Bit 9: Mode Fault interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TSERFIE

Bit 10: Additional number of transactions reload interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

SR

Status Register

Offset: 0x14, size: 32, reset: 0x00001002, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTSIZE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXWNE
r
RXPLVL
r
TXC
r
SUSP
r
TSERF
r
MODF
r
TIFRE
r
CRCE
r
OVR
r
UDR
r
TXTF
r
EOT
r
DXP
r
TXP
r
RXP
r
Toggle fields

RXP

Bit 0: Rx-Packet available.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXP

Bit 1: Tx-Packet space available.

Allowed values:
0: Full: Tx buffer full
1: NotFull: Tx buffer not full

DXP

Bit 2: Duplex Packet.

Allowed values:
0: Unavailable: Duplex packet unavailable: no space for transmission and/or no data received
1: Available: Duplex packet available: space for transmission and data received

EOT

Bit 3: End Of Transfer.

Allowed values:
0: NotCompleted: Transfer ongoing or not started
1: Completed: Transfer complete

TXTF

Bit 4: Transmission Transfer Filled.

Allowed values:
0: NotCompleted: Transmission buffer incomplete
1: Completed: Transmission buffer filled with at least one transfer

UDR

Bit 5: Underrun at slave transmission mode.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

OVR

Bit 6: Overrun.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

CRCE

Bit 7: CRC Error.

Allowed values:
0: NoError: No CRC error detected
1: Error: CRC error detected

TIFRE

Bit 8: TI frame format error.

Allowed values:
0: NoError: TI frame format error detected
1: Error: TI frame format error detected

MODF

Bit 9: Mode Fault.

Allowed values:
0: NoFault: No mode fault detected
1: Fault: Mode fault detected

TSERF

Bit 10: Additional number of SPI data to be transacted was reload.

Allowed values:
0: NotLoaded: Additional number of SPI data to be transacted not yet loaded
1: Loaded: Additional number of SPI data to be transacted was reloaded

SUSP

Bit 11: SUSPend.

Allowed values:
0: NotSuspended: Master not suspended
1: Suspended: Master suspended

TXC

Bit 12: TxFIFO transmission complete.

Allowed values:
0: Ongoing: Transmission ongoing
1: Completed: Transmission completed

RXPLVL

Bits 13-14: RxFIFO Packing LeVeL.

Allowed values:
0: ZeroFrames: Zero frames beyond packing ratio available
1: OneFrame: One frame beyond packing ratio available
2: TwoFrames: Two frame beyond packing ratio available
3: ThreeFrames: Three frame beyond packing ratio available

RXWNE

Bit 15: RxFIFO Word Not Empty.

Allowed values:
0: LessThan32: Less than 32-bit data frame received
1: AtLeast32: At least 32-bit data frame received

CTSIZE

Bits 16-31: Number of data frames remaining in current TSIZE session.

Allowed values: 0x0-0xffff

IFCR

Interrupt/Status Flags Clear Register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSPC
w1c
TSERFC
w1c
MODFC
w1c
TIFREC
w1c
CRCEC
w1c
OVRC
w1c
UDRC
w1c
TXTFC
w1c
EOTC
w1c
Toggle fields

EOTC

Bit 3: End Of Transfer flag clear.

Allowed values:
1: Clear: Clear interrupt flag

TXTFC

Bit 4: Transmission Transfer Filled flag clear.

Allowed values:
1: Clear: Clear interrupt flag

UDRC

Bit 5: Underrun flag clear.

Allowed values:
1: Clear: Clear interrupt flag

OVRC

Bit 6: Overrun flag clear.

Allowed values:
1: Clear: Clear interrupt flag

CRCEC

Bit 7: CRC Error flag clear.

Allowed values:
1: Clear: Clear interrupt flag

TIFREC

Bit 8: TI frame format error flag clear.

Allowed values:
1: Clear: Clear interrupt flag

MODFC

Bit 9: Mode Fault flag clear.

Allowed values:
1: Clear: Clear interrupt flag

TSERFC

Bit 10: TSERFC flag clear.

Allowed values:
1: Clear: Clear interrupt flag

SUSPC

Bit 11: SUSPend flag clear.

Allowed values:
1: Clear: Clear interrupt flag

TXDR

Transmit Data Register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXDR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDR
w
Toggle fields

TXDR

Bits 0-31: Transmit data register.

Allowed values: 0x0-0xffffffff

TXDR16

Direct 16-bit access to transmit data register

Offset: 0x20, size: 16, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDR
w
Toggle fields

TXDR

Bits 0-15: Transmit data register.

Allowed values: 0x0-0xffff

TXDR8

Direct 8-bit access to transmit data register

Offset: 0x20, size: 8, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDR
w
Toggle fields

TXDR

Bits 0-7: Transmit data register.

Allowed values: 0x0-0xff

RXDR

Receive Data Register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDR
r
Toggle fields

RXDR

Bits 0-31: Receive data register.

RXDR16

Direct 16-bit access to receive data register

Offset: 0x30, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDR
r
Toggle fields

RXDR

Bits 0-15: Receive data register.

RXDR8

Direct 8-bit access to receive data register

Offset: 0x30, size: 8, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDR
r
Toggle fields

RXDR

Bits 0-7: Receive data register.

CRCPOLY

Polynomial Register

Offset: 0x40, size: 32, reset: 0x00000107, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRCPOLY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-31: CRC polynomial register.

Allowed values: 0x0-0xffffffff

TXCRC

Transmitter CRC Register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXCRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXCRC
r
Toggle fields

TXCRC

Bits 0-31: CRC register for transmitter.

Allowed values: 0x0-0xffffffff

RXCRC

Receiver CRC Register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXCRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXCRC
r
Toggle fields

RXCRC

Bits 0-31: CRC register for receiver.

Allowed values: 0x0-0xffffffff

UDRDR

Underrun Data Register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UDRDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRDR
rw
Toggle fields

UDRDR

Bits 0-31: Data at slave underrun condition.

Allowed values: 0x0-0xffffffff

I2SCFGR

configuration register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

12/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCKOE
rw
ODD
rw
I2SDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATFMT
rw
WSINV
rw
FIXCH
rw
CKPOL
rw
CHLEN
rw
DATLEN
rw
PCMSYNC
rw
I2SSTD
rw
I2SCFG
rw
I2SMOD
rw
Toggle fields

I2SMOD

Bit 0: I2S mode selection.

Allowed values:
0: SPI: SPI mode selected
1: I2S: I2S/PCM mode selected

I2SCFG

Bits 1-3: I2S configuration mode.

Allowed values:
0: SlaveTransmit: Slave, transmit
1: SlaveReceive: Slave, recteive
2: MasterTransmit: Master, transmit
3: MasterReceive: Master, receive
4: SlaveFullDuplex: Slave, full duplex
5: MasterFullDuplex: Master, full duplex

I2SSTD

Bits 4-5: I2S standard selection.

Allowed values:
0: Philips: I2S Philips standard
1: LeftAligned: MSB/left justified standard
2: RightAligned: LSB/right justified standard
3: PCM: PCM standard

PCMSYNC

Bit 7: PCM frame synchronization.

Allowed values:
0: Short: Short PCM frame synchronization
1: Long: Long PCM frame synchronization

DATLEN

Bits 8-9: Data length to be transferred.

Allowed values:
0: Bits16: 16 bit data length
1: Bits24: 24 bit data length
2: Bits32: 32 bit data length

CHLEN

Bit 10: Channel length (number of bits per audio channel).

Allowed values:
0: Bits16: 16 bit per channel
1: Bits32: 32 bit per channel

CKPOL

Bit 11: Serial audio clock polarity.

Allowed values:
0: SampleOnRising: Signals are sampled on rising and changed on falling clock edges
1: SampleOnFalling: Signals are sampled on falling and changed on rising clock edges

FIXCH

Bit 12: Word select inversion.

Allowed values:
0: NotFixed: The channel length in slave mode is different from 16 or 32 bits (CHLEN not taken into account)
1: Fixed: The channel length in slave mode is supposed to be 16 or 32 bits (according to CHLEN)

WSINV

Bit 13: Fixed channel length in SLAVE.

Allowed values:
0: Disabled: Word select inversion disabled
1: Enabled: Word select inversion enabled

DATFMT

Bit 14: Data format.

Allowed values:
0: RightAligned: The data inside RXDR and TXDR are right aligned
1: LeftAligned: The data inside RXDR and TXDR are left aligned

I2SDIV

Bits 16-23: I2S linear prescaler.

ODD

Bit 24: Odd factor for the prescaler.

Allowed values:
0: Even: Real divider value is I2SDIV*2
1: Odd: Real divider value is I2SDIV*2 + 1

MCKOE

Bit 25: Master clock output enable.

Allowed values:
0: Disabled: Master clock output disabled
1: Enabled: Master clock output enabled

SPI2

0x40003800: Serial peripheral interface

93/94 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CFG1
0xc CFG2
0x10 IER
0x14 SR
0x18 IFCR
0x20 TXDR
0x20 (16-bit) TXDR16
0x20 (8-bit) TXDR8
0x30 RXDR
0x30 (16-bit) RXDR16
0x30 (8-bit) RXDR8
0x40 CRCPOLY
0x44 TXCRC
0x48 RXCRC
0x4c UDRDR
0x50 I2SCFGR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IOLOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCRCINI
rw
RCRCINI
rw
CRC33_17
rw
SSI
rw
HDDIR
rw
CSUSP
w
CSTART
rw
MASRX
rw
SPE
rw
Toggle fields

SPE

Bit 0: Serial Peripheral Enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

MASRX

Bit 8: Master automatic SUSP in Receive mode.

Allowed values:
0: Disabled: Automatic suspend in master receive-only mode disabled
1: Enabled: Automatic suspend in master receive-only mode enabled

CSTART

Bit 9: Master transfer start.

Allowed values:
0: NotStarted: Do not start master transfer
1: Started: Start master transfer

CSUSP

Bit 10: Master SUSPend request.

Allowed values:
0: NotRequested: Do not request master suspend
1: Requested: Request master suspend

HDDIR

Bit 11: Rx/Tx direction at Half-duplex mode.

Allowed values:
0: Receiver: Receiver in half duplex mode
1: Transmitter: Transmitter in half duplex mode

SSI

Bit 12: Internal SS signal input level.

Allowed values:
0: SlaveSelected: 0 is forced onto the SS signal and the I/O value of the SS pin is ignored
1: SlaveNotSelected: 1 is forced onto the SS signal and the I/O value of the SS pin is ignored

CRC33_17

Bit 13: 32-bit CRC polynomial configuration.

Allowed values:
0: Disabled: Full size (33/17 bit) CRC polynomial is not used
1: Enabled: Full size (33/17 bit) CRC polynomial is used

RCRCINI

Bit 14: CRC calculation initialization pattern control for receiver.

Allowed values:
0: AllZeros: All zeros RX CRC initialization pattern
1: AllOnes: All ones RX CRC initialization pattern

TCRCINI

Bit 15: CRC calculation initialization pattern control for transmitter.

Allowed values:
0: AllZeros: All zeros TX CRC initialization pattern
1: AllOnes: All ones TX CRC initialization pattern

IOLOCK

Bit 16: Locking the AF configuration of associated IOs.

Allowed values:
0: Unlocked: IO configuration unlocked
1: Locked: IO configuration locked

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSER
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSIZE
rw
Toggle fields

TSIZE

Bits 0-15: Number of data at current transfer.

Allowed values: 0x0-0xffff

TSER

Bits 16-31: Number of data transfer extension to be reload into TSIZE just when a previous.

Allowed values: 0x0-0xffff

CFG1

configuration register 1

Offset: 0x8, size: 32, reset: 0x00070007, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBR
rw
CRCEN
rw
CRCSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDMAEN
rw
RXDMAEN
rw
UDRDET
rw
UDRCFG
rw
FTHLV
rw
DSIZE
rw
Toggle fields

DSIZE

Bits 0-4: Number of bits in at single SPI data frame.

Allowed values: 0x0-0x1f

FTHLV

Bits 5-8: threshold level.

Allowed values:
0: OneFrame: 1 frame
1: TwoFrames: 2 frames
2: ThreeFrames: 3 frames
3: FourFrames: 4 frames
4: FiveFrames: 5 frames
5: SixFrames: 6 frames
6: SevenFrames: 7 frames
7: EightFrames: 8 frames
8: NineFrames: 9 frames
9: TenFrames: 10 frames
10: ElevenFrames: 11 frames
11: TwelveFrames: 12 frames
12: ThirteenFrames: 13 frames
13: FourteenFrames: 14 frames
14: FifteenFrames: 15 frames
15: SixteenFrames: 16 frames

UDRCFG

Bits 9-10: Behavior of slave transmitter at underrun condition.

Allowed values:
0: Constant: Slave sends a constant underrun pattern
1: RepeatReceived: Slave repeats last received data frame from master
2: RepeatTransmitted: Slave repeats last transmitted data frame

UDRDET

Bits 11-12: Detection of underrun condition at slave transmitter.

Allowed values:
0: StartOfFrame: Underrun is detected at begin of data frame
1: EndOfFrame: Underrun is detected at end of last data frame
2: StartOfSlaveSelect: Underrun is detected at begin of active SS signal

RXDMAEN

Bit 14: Rx DMA stream enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 15: Tx DMA stream enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

CRCSIZE

Bits 16-20: Length of CRC frame to be transacted and compared.

Allowed values: 0x0-0x1f

CRCEN

Bit 22: Hardware CRC computation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

MBR

Bits 28-30: Master baud rate.

Allowed values:
0: Div2: f_spi_ker_ck / 2
1: Div4: f_spi_ker_ck / 4
2: Div8: f_spi_ker_ck / 8
3: Div16: f_spi_ker_ck / 16
4: Div32: f_spi_ker_ck / 32
5: Div64: f_spi_ker_ck / 64
6: Div128: f_spi_ker_ck / 128
7: Div256: f_spi_ker_ck / 256

CFG2

configuration register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFCNTR
rw
SSOM
rw
SSOE
rw
SSIOP
rw
SSM
rw
CPOL
rw
CPHA
rw
LSBFRST
rw
MASTER
rw
SP
rw
COMM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSWP
rw
MIDI
rw
MSSI
rw
Toggle fields

MSSI

Bits 0-3: Master SS Idleness.

Allowed values: 0x0-0xf

MIDI

Bits 4-7: Master Inter-Data Idleness.

Allowed values: 0x0-0xf

IOSWP

Bit 15: Swap functionality of MISO and MOSI pins.

Allowed values:
0: Disabled: MISO and MOSI not swapped
1: Enabled: MISO and MOSI swapped

COMM

Bits 17-18: SPI Communication Mode.

Allowed values:
0: FullDuplex: Full duplex
1: Transmitter: Simplex transmitter only
2: Receiver: Simplex receiver only
3: HalfDuplex: Half duplex

SP

Bits 19-21: Serial Protocol.

Allowed values:
0: Motorola: Motorola SPI protocol
1: TI: TI SPI protocol

MASTER

Bit 22: SPI Master.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

LSBFRST

Bit 23: Data frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

CPHA

Bit 24: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 25: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

SSM

Bit 26: Software management of SS signal input.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

SSIOP

Bit 28: SS input/output polarity.

Allowed values:
0: ActiveLow: Low level is active for SS signal
1: ActiveHigh: High level is active for SS signal

SSOE

Bit 29: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

SSOM

Bit 30: SS output management in master mode.

Allowed values:
0: Asserted: SS is asserted until data transfer complete
1: NotAsserted: Data frames interleaved with SS not asserted during MIDI

AFCNTR

Bit 31: Alternate function GPIOs control.

Allowed values:
0: NotControlled: Peripheral takes no control of GPIOs while disabled
1: Controlled: Peripheral controls GPIOs while disabled

IER

Interrupt Enable Register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

11/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSERFIE
rw
MODFIE
rw
TIFREIE
rw
CRCEIE
rw
OVRIE
rw
UDRIE
rw
TXTFIE
rw
EOTIE
rw
DXPIE
rw
TXPIE
rw
RXPIE
rw
Toggle fields

RXPIE

Bit 0: RXP Interrupt Enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TXPIE

Bit 1: TXP interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

DXPIE

Bit 2: DXP interrupt enabled.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

EOTIE

Bit 3: EOT, SUSP and TXC interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TXTFIE

Bit 4: TXTFIE interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

UDRIE

Bit 5: UDR interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

OVRIE

Bit 6: OVR interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CRCEIE

Bit 7: CRC Interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TIFREIE

Bit 8: TIFRE interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

MODFIE

Bit 9: Mode Fault interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TSERFIE

Bit 10: Additional number of transactions reload interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

SR

Status Register

Offset: 0x14, size: 32, reset: 0x00001002, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTSIZE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXWNE
r
RXPLVL
r
TXC
r
SUSP
r
TSERF
r
MODF
r
TIFRE
r
CRCE
r
OVR
r
UDR
r
TXTF
r
EOT
r
DXP
r
TXP
r
RXP
r
Toggle fields

RXP

Bit 0: Rx-Packet available.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXP

Bit 1: Tx-Packet space available.

Allowed values:
0: Full: Tx buffer full
1: NotFull: Tx buffer not full

DXP

Bit 2: Duplex Packet.

Allowed values:
0: Unavailable: Duplex packet unavailable: no space for transmission and/or no data received
1: Available: Duplex packet available: space for transmission and data received

EOT

Bit 3: End Of Transfer.

Allowed values:
0: NotCompleted: Transfer ongoing or not started
1: Completed: Transfer complete

TXTF

Bit 4: Transmission Transfer Filled.

Allowed values:
0: NotCompleted: Transmission buffer incomplete
1: Completed: Transmission buffer filled with at least one transfer

UDR

Bit 5: Underrun at slave transmission mode.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

OVR

Bit 6: Overrun.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

CRCE

Bit 7: CRC Error.

Allowed values:
0: NoError: No CRC error detected
1: Error: CRC error detected

TIFRE

Bit 8: TI frame format error.

Allowed values:
0: NoError: TI frame format error detected
1: Error: TI frame format error detected

MODF

Bit 9: Mode Fault.

Allowed values:
0: NoFault: No mode fault detected
1: Fault: Mode fault detected

TSERF

Bit 10: Additional number of SPI data to be transacted was reload.

Allowed values:
0: NotLoaded: Additional number of SPI data to be transacted not yet loaded
1: Loaded: Additional number of SPI data to be transacted was reloaded

SUSP

Bit 11: SUSPend.

Allowed values:
0: NotSuspended: Master not suspended
1: Suspended: Master suspended

TXC

Bit 12: TxFIFO transmission complete.

Allowed values:
0: Ongoing: Transmission ongoing
1: Completed: Transmission completed

RXPLVL

Bits 13-14: RxFIFO Packing LeVeL.

Allowed values:
0: ZeroFrames: Zero frames beyond packing ratio available
1: OneFrame: One frame beyond packing ratio available
2: TwoFrames: Two frame beyond packing ratio available
3: ThreeFrames: Three frame beyond packing ratio available

RXWNE

Bit 15: RxFIFO Word Not Empty.

Allowed values:
0: LessThan32: Less than 32-bit data frame received
1: AtLeast32: At least 32-bit data frame received

CTSIZE

Bits 16-31: Number of data frames remaining in current TSIZE session.

Allowed values: 0x0-0xffff

IFCR

Interrupt/Status Flags Clear Register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSPC
w1c
TSERFC
w1c
MODFC
w1c
TIFREC
w1c
CRCEC
w1c
OVRC
w1c
UDRC
w1c
TXTFC
w1c
EOTC
w1c
Toggle fields

EOTC

Bit 3: End Of Transfer flag clear.

Allowed values:
1: Clear: Clear interrupt flag

TXTFC

Bit 4: Transmission Transfer Filled flag clear.

Allowed values:
1: Clear: Clear interrupt flag

UDRC

Bit 5: Underrun flag clear.

Allowed values:
1: Clear: Clear interrupt flag

OVRC

Bit 6: Overrun flag clear.

Allowed values:
1: Clear: Clear interrupt flag

CRCEC

Bit 7: CRC Error flag clear.

Allowed values:
1: Clear: Clear interrupt flag

TIFREC

Bit 8: TI frame format error flag clear.

Allowed values:
1: Clear: Clear interrupt flag

MODFC

Bit 9: Mode Fault flag clear.

Allowed values:
1: Clear: Clear interrupt flag

TSERFC

Bit 10: TSERFC flag clear.

Allowed values:
1: Clear: Clear interrupt flag

SUSPC

Bit 11: SUSPend flag clear.

Allowed values:
1: Clear: Clear interrupt flag

TXDR

Transmit Data Register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXDR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDR
w
Toggle fields

TXDR

Bits 0-31: Transmit data register.

Allowed values: 0x0-0xffffffff

TXDR16

Direct 16-bit access to transmit data register

Offset: 0x20, size: 16, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDR
w
Toggle fields

TXDR

Bits 0-15: Transmit data register.

Allowed values: 0x0-0xffff

TXDR8

Direct 8-bit access to transmit data register

Offset: 0x20, size: 8, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDR
w
Toggle fields

TXDR

Bits 0-7: Transmit data register.

Allowed values: 0x0-0xff

RXDR

Receive Data Register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDR
r
Toggle fields

RXDR

Bits 0-31: Receive data register.

RXDR16

Direct 16-bit access to receive data register

Offset: 0x30, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDR
r
Toggle fields

RXDR

Bits 0-15: Receive data register.

RXDR8

Direct 8-bit access to receive data register

Offset: 0x30, size: 8, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDR
r
Toggle fields

RXDR

Bits 0-7: Receive data register.

CRCPOLY

Polynomial Register

Offset: 0x40, size: 32, reset: 0x00000107, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRCPOLY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-31: CRC polynomial register.

Allowed values: 0x0-0xffffffff

TXCRC

Transmitter CRC Register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXCRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXCRC
r
Toggle fields

TXCRC

Bits 0-31: CRC register for transmitter.

Allowed values: 0x0-0xffffffff

RXCRC

Receiver CRC Register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXCRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXCRC
r
Toggle fields

RXCRC

Bits 0-31: CRC register for receiver.

Allowed values: 0x0-0xffffffff

UDRDR

Underrun Data Register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UDRDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRDR
rw
Toggle fields

UDRDR

Bits 0-31: Data at slave underrun condition.

Allowed values: 0x0-0xffffffff

I2SCFGR

configuration register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

12/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCKOE
rw
ODD
rw
I2SDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATFMT
rw
WSINV
rw
FIXCH
rw
CKPOL
rw
CHLEN
rw
DATLEN
rw
PCMSYNC
rw
I2SSTD
rw
I2SCFG
rw
I2SMOD
rw
Toggle fields

I2SMOD

Bit 0: I2S mode selection.

Allowed values:
0: SPI: SPI mode selected
1: I2S: I2S/PCM mode selected

I2SCFG

Bits 1-3: I2S configuration mode.

Allowed values:
0: SlaveTransmit: Slave, transmit
1: SlaveReceive: Slave, recteive
2: MasterTransmit: Master, transmit
3: MasterReceive: Master, receive
4: SlaveFullDuplex: Slave, full duplex
5: MasterFullDuplex: Master, full duplex

I2SSTD

Bits 4-5: I2S standard selection.

Allowed values:
0: Philips: I2S Philips standard
1: LeftAligned: MSB/left justified standard
2: RightAligned: LSB/right justified standard
3: PCM: PCM standard

PCMSYNC

Bit 7: PCM frame synchronization.

Allowed values:
0: Short: Short PCM frame synchronization
1: Long: Long PCM frame synchronization

DATLEN

Bits 8-9: Data length to be transferred.

Allowed values:
0: Bits16: 16 bit data length
1: Bits24: 24 bit data length
2: Bits32: 32 bit data length

CHLEN

Bit 10: Channel length (number of bits per audio channel).

Allowed values:
0: Bits16: 16 bit per channel
1: Bits32: 32 bit per channel

CKPOL

Bit 11: Serial audio clock polarity.

Allowed values:
0: SampleOnRising: Signals are sampled on rising and changed on falling clock edges
1: SampleOnFalling: Signals are sampled on falling and changed on rising clock edges

FIXCH

Bit 12: Word select inversion.

Allowed values:
0: NotFixed: The channel length in slave mode is different from 16 or 32 bits (CHLEN not taken into account)
1: Fixed: The channel length in slave mode is supposed to be 16 or 32 bits (according to CHLEN)

WSINV

Bit 13: Fixed channel length in SLAVE.

Allowed values:
0: Disabled: Word select inversion disabled
1: Enabled: Word select inversion enabled

DATFMT

Bit 14: Data format.

Allowed values:
0: RightAligned: The data inside RXDR and TXDR are right aligned
1: LeftAligned: The data inside RXDR and TXDR are left aligned

I2SDIV

Bits 16-23: I2S linear prescaler.

ODD

Bit 24: Odd factor for the prescaler.

Allowed values:
0: Even: Real divider value is I2SDIV*2
1: Odd: Real divider value is I2SDIV*2 + 1

MCKOE

Bit 25: Master clock output enable.

Allowed values:
0: Disabled: Master clock output disabled
1: Enabled: Master clock output enabled

SPI3

0x40003c00: Serial peripheral interface

93/94 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CFG1
0xc CFG2
0x10 IER
0x14 SR
0x18 IFCR
0x20 TXDR
0x20 (16-bit) TXDR16
0x20 (8-bit) TXDR8
0x30 RXDR
0x30 (16-bit) RXDR16
0x30 (8-bit) RXDR8
0x40 CRCPOLY
0x44 TXCRC
0x48 RXCRC
0x4c UDRDR
0x50 I2SCFGR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IOLOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCRCINI
rw
RCRCINI
rw
CRC33_17
rw
SSI
rw
HDDIR
rw
CSUSP
w
CSTART
rw
MASRX
rw
SPE
rw
Toggle fields

SPE

Bit 0: Serial Peripheral Enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

MASRX

Bit 8: Master automatic SUSP in Receive mode.

Allowed values:
0: Disabled: Automatic suspend in master receive-only mode disabled
1: Enabled: Automatic suspend in master receive-only mode enabled

CSTART

Bit 9: Master transfer start.

Allowed values:
0: NotStarted: Do not start master transfer
1: Started: Start master transfer

CSUSP

Bit 10: Master SUSPend request.

Allowed values:
0: NotRequested: Do not request master suspend
1: Requested: Request master suspend

HDDIR

Bit 11: Rx/Tx direction at Half-duplex mode.

Allowed values:
0: Receiver: Receiver in half duplex mode
1: Transmitter: Transmitter in half duplex mode

SSI

Bit 12: Internal SS signal input level.

Allowed values:
0: SlaveSelected: 0 is forced onto the SS signal and the I/O value of the SS pin is ignored
1: SlaveNotSelected: 1 is forced onto the SS signal and the I/O value of the SS pin is ignored

CRC33_17

Bit 13: 32-bit CRC polynomial configuration.

Allowed values:
0: Disabled: Full size (33/17 bit) CRC polynomial is not used
1: Enabled: Full size (33/17 bit) CRC polynomial is used

RCRCINI

Bit 14: CRC calculation initialization pattern control for receiver.

Allowed values:
0: AllZeros: All zeros RX CRC initialization pattern
1: AllOnes: All ones RX CRC initialization pattern

TCRCINI

Bit 15: CRC calculation initialization pattern control for transmitter.

Allowed values:
0: AllZeros: All zeros TX CRC initialization pattern
1: AllOnes: All ones TX CRC initialization pattern

IOLOCK

Bit 16: Locking the AF configuration of associated IOs.

Allowed values:
0: Unlocked: IO configuration unlocked
1: Locked: IO configuration locked

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSER
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSIZE
rw
Toggle fields

TSIZE

Bits 0-15: Number of data at current transfer.

Allowed values: 0x0-0xffff

TSER

Bits 16-31: Number of data transfer extension to be reload into TSIZE just when a previous.

Allowed values: 0x0-0xffff

CFG1

configuration register 1

Offset: 0x8, size: 32, reset: 0x00070007, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBR
rw
CRCEN
rw
CRCSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDMAEN
rw
RXDMAEN
rw
UDRDET
rw
UDRCFG
rw
FTHLV
rw
DSIZE
rw
Toggle fields

DSIZE

Bits 0-4: Number of bits in at single SPI data frame.

Allowed values: 0x0-0x1f

FTHLV

Bits 5-8: threshold level.

Allowed values:
0: OneFrame: 1 frame
1: TwoFrames: 2 frames
2: ThreeFrames: 3 frames
3: FourFrames: 4 frames
4: FiveFrames: 5 frames
5: SixFrames: 6 frames
6: SevenFrames: 7 frames
7: EightFrames: 8 frames
8: NineFrames: 9 frames
9: TenFrames: 10 frames
10: ElevenFrames: 11 frames
11: TwelveFrames: 12 frames
12: ThirteenFrames: 13 frames
13: FourteenFrames: 14 frames
14: FifteenFrames: 15 frames
15: SixteenFrames: 16 frames

UDRCFG

Bits 9-10: Behavior of slave transmitter at underrun condition.

Allowed values:
0: Constant: Slave sends a constant underrun pattern
1: RepeatReceived: Slave repeats last received data frame from master
2: RepeatTransmitted: Slave repeats last transmitted data frame

UDRDET

Bits 11-12: Detection of underrun condition at slave transmitter.

Allowed values:
0: StartOfFrame: Underrun is detected at begin of data frame
1: EndOfFrame: Underrun is detected at end of last data frame
2: StartOfSlaveSelect: Underrun is detected at begin of active SS signal

RXDMAEN

Bit 14: Rx DMA stream enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 15: Tx DMA stream enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

CRCSIZE

Bits 16-20: Length of CRC frame to be transacted and compared.

Allowed values: 0x0-0x1f

CRCEN

Bit 22: Hardware CRC computation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

MBR

Bits 28-30: Master baud rate.

Allowed values:
0: Div2: f_spi_ker_ck / 2
1: Div4: f_spi_ker_ck / 4
2: Div8: f_spi_ker_ck / 8
3: Div16: f_spi_ker_ck / 16
4: Div32: f_spi_ker_ck / 32
5: Div64: f_spi_ker_ck / 64
6: Div128: f_spi_ker_ck / 128
7: Div256: f_spi_ker_ck / 256

CFG2

configuration register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFCNTR
rw
SSOM
rw
SSOE
rw
SSIOP
rw
SSM
rw
CPOL
rw
CPHA
rw
LSBFRST
rw
MASTER
rw
SP
rw
COMM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSWP
rw
MIDI
rw
MSSI
rw
Toggle fields

MSSI

Bits 0-3: Master SS Idleness.

Allowed values: 0x0-0xf

MIDI

Bits 4-7: Master Inter-Data Idleness.

Allowed values: 0x0-0xf

IOSWP

Bit 15: Swap functionality of MISO and MOSI pins.

Allowed values:
0: Disabled: MISO and MOSI not swapped
1: Enabled: MISO and MOSI swapped

COMM

Bits 17-18: SPI Communication Mode.

Allowed values:
0: FullDuplex: Full duplex
1: Transmitter: Simplex transmitter only
2: Receiver: Simplex receiver only
3: HalfDuplex: Half duplex

SP

Bits 19-21: Serial Protocol.

Allowed values:
0: Motorola: Motorola SPI protocol
1: TI: TI SPI protocol

MASTER

Bit 22: SPI Master.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

LSBFRST

Bit 23: Data frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

CPHA

Bit 24: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 25: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

SSM

Bit 26: Software management of SS signal input.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

SSIOP

Bit 28: SS input/output polarity.

Allowed values:
0: ActiveLow: Low level is active for SS signal
1: ActiveHigh: High level is active for SS signal

SSOE

Bit 29: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

SSOM

Bit 30: SS output management in master mode.

Allowed values:
0: Asserted: SS is asserted until data transfer complete
1: NotAsserted: Data frames interleaved with SS not asserted during MIDI

AFCNTR

Bit 31: Alternate function GPIOs control.

Allowed values:
0: NotControlled: Peripheral takes no control of GPIOs while disabled
1: Controlled: Peripheral controls GPIOs while disabled

IER

Interrupt Enable Register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

11/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSERFIE
rw
MODFIE
rw
TIFREIE
rw
CRCEIE
rw
OVRIE
rw
UDRIE
rw
TXTFIE
rw
EOTIE
rw
DXPIE
rw
TXPIE
rw
RXPIE
rw
Toggle fields

RXPIE

Bit 0: RXP Interrupt Enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TXPIE

Bit 1: TXP interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

DXPIE

Bit 2: DXP interrupt enabled.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

EOTIE

Bit 3: EOT, SUSP and TXC interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TXTFIE

Bit 4: TXTFIE interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

UDRIE

Bit 5: UDR interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

OVRIE

Bit 6: OVR interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CRCEIE

Bit 7: CRC Interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TIFREIE

Bit 8: TIFRE interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

MODFIE

Bit 9: Mode Fault interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TSERFIE

Bit 10: Additional number of transactions reload interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

SR

Status Register

Offset: 0x14, size: 32, reset: 0x00001002, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTSIZE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXWNE
r
RXPLVL
r
TXC
r
SUSP
r
TSERF
r
MODF
r
TIFRE
r
CRCE
r
OVR
r
UDR
r
TXTF
r
EOT
r
DXP
r
TXP
r
RXP
r
Toggle fields

RXP

Bit 0: Rx-Packet available.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXP

Bit 1: Tx-Packet space available.

Allowed values:
0: Full: Tx buffer full
1: NotFull: Tx buffer not full

DXP

Bit 2: Duplex Packet.

Allowed values:
0: Unavailable: Duplex packet unavailable: no space for transmission and/or no data received
1: Available: Duplex packet available: space for transmission and data received

EOT

Bit 3: End Of Transfer.

Allowed values:
0: NotCompleted: Transfer ongoing or not started
1: Completed: Transfer complete

TXTF

Bit 4: Transmission Transfer Filled.

Allowed values:
0: NotCompleted: Transmission buffer incomplete
1: Completed: Transmission buffer filled with at least one transfer

UDR

Bit 5: Underrun at slave transmission mode.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

OVR

Bit 6: Overrun.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

CRCE

Bit 7: CRC Error.

Allowed values:
0: NoError: No CRC error detected
1: Error: CRC error detected

TIFRE

Bit 8: TI frame format error.

Allowed values:
0: NoError: TI frame format error detected
1: Error: TI frame format error detected

MODF

Bit 9: Mode Fault.

Allowed values:
0: NoFault: No mode fault detected
1: Fault: Mode fault detected

TSERF

Bit 10: Additional number of SPI data to be transacted was reload.

Allowed values:
0: NotLoaded: Additional number of SPI data to be transacted not yet loaded
1: Loaded: Additional number of SPI data to be transacted was reloaded

SUSP

Bit 11: SUSPend.

Allowed values:
0: NotSuspended: Master not suspended
1: Suspended: Master suspended

TXC

Bit 12: TxFIFO transmission complete.

Allowed values:
0: Ongoing: Transmission ongoing
1: Completed: Transmission completed

RXPLVL

Bits 13-14: RxFIFO Packing LeVeL.

Allowed values:
0: ZeroFrames: Zero frames beyond packing ratio available
1: OneFrame: One frame beyond packing ratio available
2: TwoFrames: Two frame beyond packing ratio available
3: ThreeFrames: Three frame beyond packing ratio available

RXWNE

Bit 15: RxFIFO Word Not Empty.

Allowed values:
0: LessThan32: Less than 32-bit data frame received
1: AtLeast32: At least 32-bit data frame received

CTSIZE

Bits 16-31: Number of data frames remaining in current TSIZE session.

Allowed values: 0x0-0xffff

IFCR

Interrupt/Status Flags Clear Register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSPC
w1c
TSERFC
w1c
MODFC
w1c
TIFREC
w1c
CRCEC
w1c
OVRC
w1c
UDRC
w1c
TXTFC
w1c
EOTC
w1c
Toggle fields

EOTC

Bit 3: End Of Transfer flag clear.

Allowed values:
1: Clear: Clear interrupt flag

TXTFC

Bit 4: Transmission Transfer Filled flag clear.

Allowed values:
1: Clear: Clear interrupt flag

UDRC

Bit 5: Underrun flag clear.

Allowed values:
1: Clear: Clear interrupt flag

OVRC

Bit 6: Overrun flag clear.

Allowed values:
1: Clear: Clear interrupt flag

CRCEC

Bit 7: CRC Error flag clear.

Allowed values:
1: Clear: Clear interrupt flag

TIFREC

Bit 8: TI frame format error flag clear.

Allowed values:
1: Clear: Clear interrupt flag

MODFC

Bit 9: Mode Fault flag clear.

Allowed values:
1: Clear: Clear interrupt flag

TSERFC

Bit 10: TSERFC flag clear.

Allowed values:
1: Clear: Clear interrupt flag

SUSPC

Bit 11: SUSPend flag clear.

Allowed values:
1: Clear: Clear interrupt flag

TXDR

Transmit Data Register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXDR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDR
w
Toggle fields

TXDR

Bits 0-31: Transmit data register.

Allowed values: 0x0-0xffffffff

TXDR16

Direct 16-bit access to transmit data register

Offset: 0x20, size: 16, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDR
w
Toggle fields

TXDR

Bits 0-15: Transmit data register.

Allowed values: 0x0-0xffff

TXDR8

Direct 8-bit access to transmit data register

Offset: 0x20, size: 8, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDR
w
Toggle fields

TXDR

Bits 0-7: Transmit data register.

Allowed values: 0x0-0xff

RXDR

Receive Data Register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDR
r
Toggle fields

RXDR

Bits 0-31: Receive data register.

RXDR16

Direct 16-bit access to receive data register

Offset: 0x30, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDR
r
Toggle fields

RXDR

Bits 0-15: Receive data register.

RXDR8

Direct 8-bit access to receive data register

Offset: 0x30, size: 8, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDR
r
Toggle fields

RXDR

Bits 0-7: Receive data register.

CRCPOLY

Polynomial Register

Offset: 0x40, size: 32, reset: 0x00000107, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRCPOLY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-31: CRC polynomial register.

Allowed values: 0x0-0xffffffff

TXCRC

Transmitter CRC Register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXCRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXCRC
r
Toggle fields

TXCRC

Bits 0-31: CRC register for transmitter.

Allowed values: 0x0-0xffffffff

RXCRC

Receiver CRC Register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXCRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXCRC
r
Toggle fields

RXCRC

Bits 0-31: CRC register for receiver.

Allowed values: 0x0-0xffffffff

UDRDR

Underrun Data Register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UDRDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRDR
rw
Toggle fields

UDRDR

Bits 0-31: Data at slave underrun condition.

Allowed values: 0x0-0xffffffff

I2SCFGR

configuration register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

12/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCKOE
rw
ODD
rw
I2SDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATFMT
rw
WSINV
rw
FIXCH
rw
CKPOL
rw
CHLEN
rw
DATLEN
rw
PCMSYNC
rw
I2SSTD
rw
I2SCFG
rw
I2SMOD
rw
Toggle fields

I2SMOD

Bit 0: I2S mode selection.

Allowed values:
0: SPI: SPI mode selected
1: I2S: I2S/PCM mode selected

I2SCFG

Bits 1-3: I2S configuration mode.

Allowed values:
0: SlaveTransmit: Slave, transmit
1: SlaveReceive: Slave, recteive
2: MasterTransmit: Master, transmit
3: MasterReceive: Master, receive
4: SlaveFullDuplex: Slave, full duplex
5: MasterFullDuplex: Master, full duplex

I2SSTD

Bits 4-5: I2S standard selection.

Allowed values:
0: Philips: I2S Philips standard
1: LeftAligned: MSB/left justified standard
2: RightAligned: LSB/right justified standard
3: PCM: PCM standard

PCMSYNC

Bit 7: PCM frame synchronization.

Allowed values:
0: Short: Short PCM frame synchronization
1: Long: Long PCM frame synchronization

DATLEN

Bits 8-9: Data length to be transferred.

Allowed values:
0: Bits16: 16 bit data length
1: Bits24: 24 bit data length
2: Bits32: 32 bit data length

CHLEN

Bit 10: Channel length (number of bits per audio channel).

Allowed values:
0: Bits16: 16 bit per channel
1: Bits32: 32 bit per channel

CKPOL

Bit 11: Serial audio clock polarity.

Allowed values:
0: SampleOnRising: Signals are sampled on rising and changed on falling clock edges
1: SampleOnFalling: Signals are sampled on falling and changed on rising clock edges

FIXCH

Bit 12: Word select inversion.

Allowed values:
0: NotFixed: The channel length in slave mode is different from 16 or 32 bits (CHLEN not taken into account)
1: Fixed: The channel length in slave mode is supposed to be 16 or 32 bits (according to CHLEN)

WSINV

Bit 13: Fixed channel length in SLAVE.

Allowed values:
0: Disabled: Word select inversion disabled
1: Enabled: Word select inversion enabled

DATFMT

Bit 14: Data format.

Allowed values:
0: RightAligned: The data inside RXDR and TXDR are right aligned
1: LeftAligned: The data inside RXDR and TXDR are left aligned

I2SDIV

Bits 16-23: I2S linear prescaler.

ODD

Bit 24: Odd factor for the prescaler.

Allowed values:
0: Even: Real divider value is I2SDIV*2
1: Odd: Real divider value is I2SDIV*2 + 1

MCKOE

Bit 25: Master clock output enable.

Allowed values:
0: Disabled: Master clock output disabled
1: Enabled: Master clock output enabled

SPI4

0x40013400: Serial peripheral interface

93/94 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CFG1
0xc CFG2
0x10 IER
0x14 SR
0x18 IFCR
0x20 TXDR
0x20 (16-bit) TXDR16
0x20 (8-bit) TXDR8
0x30 RXDR
0x30 (16-bit) RXDR16
0x30 (8-bit) RXDR8
0x40 CRCPOLY
0x44 TXCRC
0x48 RXCRC
0x4c UDRDR
0x50 I2SCFGR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IOLOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCRCINI
rw
RCRCINI
rw
CRC33_17
rw
SSI
rw
HDDIR
rw
CSUSP
w
CSTART
rw
MASRX
rw
SPE
rw
Toggle fields

SPE

Bit 0: Serial Peripheral Enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

MASRX

Bit 8: Master automatic SUSP in Receive mode.

Allowed values:
0: Disabled: Automatic suspend in master receive-only mode disabled
1: Enabled: Automatic suspend in master receive-only mode enabled

CSTART

Bit 9: Master transfer start.

Allowed values:
0: NotStarted: Do not start master transfer
1: Started: Start master transfer

CSUSP

Bit 10: Master SUSPend request.

Allowed values:
0: NotRequested: Do not request master suspend
1: Requested: Request master suspend

HDDIR

Bit 11: Rx/Tx direction at Half-duplex mode.

Allowed values:
0: Receiver: Receiver in half duplex mode
1: Transmitter: Transmitter in half duplex mode

SSI

Bit 12: Internal SS signal input level.

Allowed values:
0: SlaveSelected: 0 is forced onto the SS signal and the I/O value of the SS pin is ignored
1: SlaveNotSelected: 1 is forced onto the SS signal and the I/O value of the SS pin is ignored

CRC33_17

Bit 13: 32-bit CRC polynomial configuration.

Allowed values:
0: Disabled: Full size (33/17 bit) CRC polynomial is not used
1: Enabled: Full size (33/17 bit) CRC polynomial is used

RCRCINI

Bit 14: CRC calculation initialization pattern control for receiver.

Allowed values:
0: AllZeros: All zeros RX CRC initialization pattern
1: AllOnes: All ones RX CRC initialization pattern

TCRCINI

Bit 15: CRC calculation initialization pattern control for transmitter.

Allowed values:
0: AllZeros: All zeros TX CRC initialization pattern
1: AllOnes: All ones TX CRC initialization pattern

IOLOCK

Bit 16: Locking the AF configuration of associated IOs.

Allowed values:
0: Unlocked: IO configuration unlocked
1: Locked: IO configuration locked

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSER
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSIZE
rw
Toggle fields

TSIZE

Bits 0-15: Number of data at current transfer.

Allowed values: 0x0-0xffff

TSER

Bits 16-31: Number of data transfer extension to be reload into TSIZE just when a previous.

Allowed values: 0x0-0xffff

CFG1

configuration register 1

Offset: 0x8, size: 32, reset: 0x00070007, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBR
rw
CRCEN
rw
CRCSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDMAEN
rw
RXDMAEN
rw
UDRDET
rw
UDRCFG
rw
FTHLV
rw
DSIZE
rw
Toggle fields

DSIZE

Bits 0-4: Number of bits in at single SPI data frame.

Allowed values: 0x0-0x1f

FTHLV

Bits 5-8: threshold level.

Allowed values:
0: OneFrame: 1 frame
1: TwoFrames: 2 frames
2: ThreeFrames: 3 frames
3: FourFrames: 4 frames
4: FiveFrames: 5 frames
5: SixFrames: 6 frames
6: SevenFrames: 7 frames
7: EightFrames: 8 frames
8: NineFrames: 9 frames
9: TenFrames: 10 frames
10: ElevenFrames: 11 frames
11: TwelveFrames: 12 frames
12: ThirteenFrames: 13 frames
13: FourteenFrames: 14 frames
14: FifteenFrames: 15 frames
15: SixteenFrames: 16 frames

UDRCFG

Bits 9-10: Behavior of slave transmitter at underrun condition.

Allowed values:
0: Constant: Slave sends a constant underrun pattern
1: RepeatReceived: Slave repeats last received data frame from master
2: RepeatTransmitted: Slave repeats last transmitted data frame

UDRDET

Bits 11-12: Detection of underrun condition at slave transmitter.

Allowed values:
0: StartOfFrame: Underrun is detected at begin of data frame
1: EndOfFrame: Underrun is detected at end of last data frame
2: StartOfSlaveSelect: Underrun is detected at begin of active SS signal

RXDMAEN

Bit 14: Rx DMA stream enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 15: Tx DMA stream enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

CRCSIZE

Bits 16-20: Length of CRC frame to be transacted and compared.

Allowed values: 0x0-0x1f

CRCEN

Bit 22: Hardware CRC computation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

MBR

Bits 28-30: Master baud rate.

Allowed values:
0: Div2: f_spi_ker_ck / 2
1: Div4: f_spi_ker_ck / 4
2: Div8: f_spi_ker_ck / 8
3: Div16: f_spi_ker_ck / 16
4: Div32: f_spi_ker_ck / 32
5: Div64: f_spi_ker_ck / 64
6: Div128: f_spi_ker_ck / 128
7: Div256: f_spi_ker_ck / 256

CFG2

configuration register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFCNTR
rw
SSOM
rw
SSOE
rw
SSIOP
rw
SSM
rw
CPOL
rw
CPHA
rw
LSBFRST
rw
MASTER
rw
SP
rw
COMM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSWP
rw
MIDI
rw
MSSI
rw
Toggle fields

MSSI

Bits 0-3: Master SS Idleness.

Allowed values: 0x0-0xf

MIDI

Bits 4-7: Master Inter-Data Idleness.

Allowed values: 0x0-0xf

IOSWP

Bit 15: Swap functionality of MISO and MOSI pins.

Allowed values:
0: Disabled: MISO and MOSI not swapped
1: Enabled: MISO and MOSI swapped

COMM

Bits 17-18: SPI Communication Mode.

Allowed values:
0: FullDuplex: Full duplex
1: Transmitter: Simplex transmitter only
2: Receiver: Simplex receiver only
3: HalfDuplex: Half duplex

SP

Bits 19-21: Serial Protocol.

Allowed values:
0: Motorola: Motorola SPI protocol
1: TI: TI SPI protocol

MASTER

Bit 22: SPI Master.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

LSBFRST

Bit 23: Data frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

CPHA

Bit 24: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 25: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

SSM

Bit 26: Software management of SS signal input.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

SSIOP

Bit 28: SS input/output polarity.

Allowed values:
0: ActiveLow: Low level is active for SS signal
1: ActiveHigh: High level is active for SS signal

SSOE

Bit 29: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

SSOM

Bit 30: SS output management in master mode.

Allowed values:
0: Asserted: SS is asserted until data transfer complete
1: NotAsserted: Data frames interleaved with SS not asserted during MIDI

AFCNTR

Bit 31: Alternate function GPIOs control.

Allowed values:
0: NotControlled: Peripheral takes no control of GPIOs while disabled
1: Controlled: Peripheral controls GPIOs while disabled

IER

Interrupt Enable Register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

11/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSERFIE
rw
MODFIE
rw
TIFREIE
rw
CRCEIE
rw
OVRIE
rw
UDRIE
rw
TXTFIE
rw
EOTIE
rw
DXPIE
rw
TXPIE
rw
RXPIE
rw
Toggle fields

RXPIE

Bit 0: RXP Interrupt Enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TXPIE

Bit 1: TXP interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

DXPIE

Bit 2: DXP interrupt enabled.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

EOTIE

Bit 3: EOT, SUSP and TXC interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TXTFIE

Bit 4: TXTFIE interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

UDRIE

Bit 5: UDR interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

OVRIE

Bit 6: OVR interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CRCEIE

Bit 7: CRC Interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TIFREIE

Bit 8: TIFRE interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

MODFIE

Bit 9: Mode Fault interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TSERFIE

Bit 10: Additional number of transactions reload interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

SR

Status Register

Offset: 0x14, size: 32, reset: 0x00001002, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTSIZE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXWNE
r
RXPLVL
r
TXC
r
SUSP
r
TSERF
r
MODF
r
TIFRE
r
CRCE
r
OVR
r
UDR
r
TXTF
r
EOT
r
DXP
r
TXP
r
RXP
r
Toggle fields

RXP

Bit 0: Rx-Packet available.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXP

Bit 1: Tx-Packet space available.

Allowed values:
0: Full: Tx buffer full
1: NotFull: Tx buffer not full

DXP

Bit 2: Duplex Packet.

Allowed values:
0: Unavailable: Duplex packet unavailable: no space for transmission and/or no data received
1: Available: Duplex packet available: space for transmission and data received

EOT

Bit 3: End Of Transfer.

Allowed values:
0: NotCompleted: Transfer ongoing or not started
1: Completed: Transfer complete

TXTF

Bit 4: Transmission Transfer Filled.

Allowed values:
0: NotCompleted: Transmission buffer incomplete
1: Completed: Transmission buffer filled with at least one transfer

UDR

Bit 5: Underrun at slave transmission mode.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

OVR

Bit 6: Overrun.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

CRCE

Bit 7: CRC Error.

Allowed values:
0: NoError: No CRC error detected
1: Error: CRC error detected

TIFRE

Bit 8: TI frame format error.

Allowed values:
0: NoError: TI frame format error detected
1: Error: TI frame format error detected

MODF

Bit 9: Mode Fault.

Allowed values:
0: NoFault: No mode fault detected
1: Fault: Mode fault detected

TSERF

Bit 10: Additional number of SPI data to be transacted was reload.

Allowed values:
0: NotLoaded: Additional number of SPI data to be transacted not yet loaded
1: Loaded: Additional number of SPI data to be transacted was reloaded

SUSP

Bit 11: SUSPend.

Allowed values:
0: NotSuspended: Master not suspended
1: Suspended: Master suspended

TXC

Bit 12: TxFIFO transmission complete.

Allowed values:
0: Ongoing: Transmission ongoing
1: Completed: Transmission completed

RXPLVL

Bits 13-14: RxFIFO Packing LeVeL.

Allowed values:
0: ZeroFrames: Zero frames beyond packing ratio available
1: OneFrame: One frame beyond packing ratio available
2: TwoFrames: Two frame beyond packing ratio available
3: ThreeFrames: Three frame beyond packing ratio available

RXWNE

Bit 15: RxFIFO Word Not Empty.

Allowed values:
0: LessThan32: Less than 32-bit data frame received
1: AtLeast32: At least 32-bit data frame received

CTSIZE

Bits 16-31: Number of data frames remaining in current TSIZE session.

Allowed values: 0x0-0xffff

IFCR

Interrupt/Status Flags Clear Register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSPC
w1c
TSERFC
w1c
MODFC
w1c
TIFREC
w1c
CRCEC
w1c
OVRC
w1c
UDRC
w1c
TXTFC
w1c
EOTC
w1c
Toggle fields

EOTC

Bit 3: End Of Transfer flag clear.

Allowed values:
1: Clear: Clear interrupt flag

TXTFC

Bit 4: Transmission Transfer Filled flag clear.

Allowed values:
1: Clear: Clear interrupt flag

UDRC

Bit 5: Underrun flag clear.

Allowed values:
1: Clear: Clear interrupt flag

OVRC

Bit 6: Overrun flag clear.

Allowed values:
1: Clear: Clear interrupt flag

CRCEC

Bit 7: CRC Error flag clear.

Allowed values:
1: Clear: Clear interrupt flag

TIFREC

Bit 8: TI frame format error flag clear.

Allowed values:
1: Clear: Clear interrupt flag

MODFC

Bit 9: Mode Fault flag clear.

Allowed values:
1: Clear: Clear interrupt flag

TSERFC

Bit 10: TSERFC flag clear.

Allowed values:
1: Clear: Clear interrupt flag

SUSPC

Bit 11: SUSPend flag clear.

Allowed values:
1: Clear: Clear interrupt flag

TXDR

Transmit Data Register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXDR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDR
w
Toggle fields

TXDR

Bits 0-31: Transmit data register.

Allowed values: 0x0-0xffffffff

TXDR16

Direct 16-bit access to transmit data register

Offset: 0x20, size: 16, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDR
w
Toggle fields

TXDR

Bits 0-15: Transmit data register.

Allowed values: 0x0-0xffff

TXDR8

Direct 8-bit access to transmit data register

Offset: 0x20, size: 8, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDR
w
Toggle fields

TXDR

Bits 0-7: Transmit data register.

Allowed values: 0x0-0xff

RXDR

Receive Data Register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDR
r
Toggle fields

RXDR

Bits 0-31: Receive data register.

RXDR16

Direct 16-bit access to receive data register

Offset: 0x30, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDR
r
Toggle fields

RXDR

Bits 0-15: Receive data register.

RXDR8

Direct 8-bit access to receive data register

Offset: 0x30, size: 8, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDR
r
Toggle fields

RXDR

Bits 0-7: Receive data register.

CRCPOLY

Polynomial Register

Offset: 0x40, size: 32, reset: 0x00000107, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRCPOLY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-31: CRC polynomial register.

Allowed values: 0x0-0xffffffff

TXCRC

Transmitter CRC Register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXCRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXCRC
r
Toggle fields

TXCRC

Bits 0-31: CRC register for transmitter.

Allowed values: 0x0-0xffffffff

RXCRC

Receiver CRC Register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXCRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXCRC
r
Toggle fields

RXCRC

Bits 0-31: CRC register for receiver.

Allowed values: 0x0-0xffffffff

UDRDR

Underrun Data Register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UDRDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRDR
rw
Toggle fields

UDRDR

Bits 0-31: Data at slave underrun condition.

Allowed values: 0x0-0xffffffff

I2SCFGR

configuration register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

12/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCKOE
rw
ODD
rw
I2SDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATFMT
rw
WSINV
rw
FIXCH
rw
CKPOL
rw
CHLEN
rw
DATLEN
rw
PCMSYNC
rw
I2SSTD
rw
I2SCFG
rw
I2SMOD
rw
Toggle fields

I2SMOD

Bit 0: I2S mode selection.

Allowed values:
0: SPI: SPI mode selected
1: I2S: I2S/PCM mode selected

I2SCFG

Bits 1-3: I2S configuration mode.

Allowed values:
0: SlaveTransmit: Slave, transmit
1: SlaveReceive: Slave, recteive
2: MasterTransmit: Master, transmit
3: MasterReceive: Master, receive
4: SlaveFullDuplex: Slave, full duplex
5: MasterFullDuplex: Master, full duplex

I2SSTD

Bits 4-5: I2S standard selection.

Allowed values:
0: Philips: I2S Philips standard
1: LeftAligned: MSB/left justified standard
2: RightAligned: LSB/right justified standard
3: PCM: PCM standard

PCMSYNC

Bit 7: PCM frame synchronization.

Allowed values:
0: Short: Short PCM frame synchronization
1: Long: Long PCM frame synchronization

DATLEN

Bits 8-9: Data length to be transferred.

Allowed values:
0: Bits16: 16 bit data length
1: Bits24: 24 bit data length
2: Bits32: 32 bit data length

CHLEN

Bit 10: Channel length (number of bits per audio channel).

Allowed values:
0: Bits16: 16 bit per channel
1: Bits32: 32 bit per channel

CKPOL

Bit 11: Serial audio clock polarity.

Allowed values:
0: SampleOnRising: Signals are sampled on rising and changed on falling clock edges
1: SampleOnFalling: Signals are sampled on falling and changed on rising clock edges

FIXCH

Bit 12: Word select inversion.

Allowed values:
0: NotFixed: The channel length in slave mode is different from 16 or 32 bits (CHLEN not taken into account)
1: Fixed: The channel length in slave mode is supposed to be 16 or 32 bits (according to CHLEN)

WSINV

Bit 13: Fixed channel length in SLAVE.

Allowed values:
0: Disabled: Word select inversion disabled
1: Enabled: Word select inversion enabled

DATFMT

Bit 14: Data format.

Allowed values:
0: RightAligned: The data inside RXDR and TXDR are right aligned
1: LeftAligned: The data inside RXDR and TXDR are left aligned

I2SDIV

Bits 16-23: I2S linear prescaler.

ODD

Bit 24: Odd factor for the prescaler.

Allowed values:
0: Even: Real divider value is I2SDIV*2
1: Odd: Real divider value is I2SDIV*2 + 1

MCKOE

Bit 25: Master clock output enable.

Allowed values:
0: Disabled: Master clock output disabled
1: Enabled: Master clock output enabled

SPI5

0x40015000: Serial peripheral interface

93/94 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CFG1
0xc CFG2
0x10 IER
0x14 SR
0x18 IFCR
0x20 TXDR
0x20 (16-bit) TXDR16
0x20 (8-bit) TXDR8
0x30 RXDR
0x30 (16-bit) RXDR16
0x30 (8-bit) RXDR8
0x40 CRCPOLY
0x44 TXCRC
0x48 RXCRC
0x4c UDRDR
0x50 I2SCFGR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IOLOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCRCINI
rw
RCRCINI
rw
CRC33_17
rw
SSI
rw
HDDIR
rw
CSUSP
w
CSTART
rw
MASRX
rw
SPE
rw
Toggle fields

SPE

Bit 0: Serial Peripheral Enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

MASRX

Bit 8: Master automatic SUSP in Receive mode.

Allowed values:
0: Disabled: Automatic suspend in master receive-only mode disabled
1: Enabled: Automatic suspend in master receive-only mode enabled

CSTART

Bit 9: Master transfer start.

Allowed values:
0: NotStarted: Do not start master transfer
1: Started: Start master transfer

CSUSP

Bit 10: Master SUSPend request.

Allowed values:
0: NotRequested: Do not request master suspend
1: Requested: Request master suspend

HDDIR

Bit 11: Rx/Tx direction at Half-duplex mode.

Allowed values:
0: Receiver: Receiver in half duplex mode
1: Transmitter: Transmitter in half duplex mode

SSI

Bit 12: Internal SS signal input level.

Allowed values:
0: SlaveSelected: 0 is forced onto the SS signal and the I/O value of the SS pin is ignored
1: SlaveNotSelected: 1 is forced onto the SS signal and the I/O value of the SS pin is ignored

CRC33_17

Bit 13: 32-bit CRC polynomial configuration.

Allowed values:
0: Disabled: Full size (33/17 bit) CRC polynomial is not used
1: Enabled: Full size (33/17 bit) CRC polynomial is used

RCRCINI

Bit 14: CRC calculation initialization pattern control for receiver.

Allowed values:
0: AllZeros: All zeros RX CRC initialization pattern
1: AllOnes: All ones RX CRC initialization pattern

TCRCINI

Bit 15: CRC calculation initialization pattern control for transmitter.

Allowed values:
0: AllZeros: All zeros TX CRC initialization pattern
1: AllOnes: All ones TX CRC initialization pattern

IOLOCK

Bit 16: Locking the AF configuration of associated IOs.

Allowed values:
0: Unlocked: IO configuration unlocked
1: Locked: IO configuration locked

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSER
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSIZE
rw
Toggle fields

TSIZE

Bits 0-15: Number of data at current transfer.

Allowed values: 0x0-0xffff

TSER

Bits 16-31: Number of data transfer extension to be reload into TSIZE just when a previous.

Allowed values: 0x0-0xffff

CFG1

configuration register 1

Offset: 0x8, size: 32, reset: 0x00070007, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBR
rw
CRCEN
rw
CRCSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDMAEN
rw
RXDMAEN
rw
UDRDET
rw
UDRCFG
rw
FTHLV
rw
DSIZE
rw
Toggle fields

DSIZE

Bits 0-4: Number of bits in at single SPI data frame.

Allowed values: 0x0-0x1f

FTHLV

Bits 5-8: threshold level.

Allowed values:
0: OneFrame: 1 frame
1: TwoFrames: 2 frames
2: ThreeFrames: 3 frames
3: FourFrames: 4 frames
4: FiveFrames: 5 frames
5: SixFrames: 6 frames
6: SevenFrames: 7 frames
7: EightFrames: 8 frames
8: NineFrames: 9 frames
9: TenFrames: 10 frames
10: ElevenFrames: 11 frames
11: TwelveFrames: 12 frames
12: ThirteenFrames: 13 frames
13: FourteenFrames: 14 frames
14: FifteenFrames: 15 frames
15: SixteenFrames: 16 frames

UDRCFG

Bits 9-10: Behavior of slave transmitter at underrun condition.

Allowed values:
0: Constant: Slave sends a constant underrun pattern
1: RepeatReceived: Slave repeats last received data frame from master
2: RepeatTransmitted: Slave repeats last transmitted data frame

UDRDET

Bits 11-12: Detection of underrun condition at slave transmitter.

Allowed values:
0: StartOfFrame: Underrun is detected at begin of data frame
1: EndOfFrame: Underrun is detected at end of last data frame
2: StartOfSlaveSelect: Underrun is detected at begin of active SS signal

RXDMAEN

Bit 14: Rx DMA stream enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 15: Tx DMA stream enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

CRCSIZE

Bits 16-20: Length of CRC frame to be transacted and compared.

Allowed values: 0x0-0x1f

CRCEN

Bit 22: Hardware CRC computation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

MBR

Bits 28-30: Master baud rate.

Allowed values:
0: Div2: f_spi_ker_ck / 2
1: Div4: f_spi_ker_ck / 4
2: Div8: f_spi_ker_ck / 8
3: Div16: f_spi_ker_ck / 16
4: Div32: f_spi_ker_ck / 32
5: Div64: f_spi_ker_ck / 64
6: Div128: f_spi_ker_ck / 128
7: Div256: f_spi_ker_ck / 256

CFG2

configuration register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFCNTR
rw
SSOM
rw
SSOE
rw
SSIOP
rw
SSM
rw
CPOL
rw
CPHA
rw
LSBFRST
rw
MASTER
rw
SP
rw
COMM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSWP
rw
MIDI
rw
MSSI
rw
Toggle fields

MSSI

Bits 0-3: Master SS Idleness.

Allowed values: 0x0-0xf

MIDI

Bits 4-7: Master Inter-Data Idleness.

Allowed values: 0x0-0xf

IOSWP

Bit 15: Swap functionality of MISO and MOSI pins.

Allowed values:
0: Disabled: MISO and MOSI not swapped
1: Enabled: MISO and MOSI swapped

COMM

Bits 17-18: SPI Communication Mode.

Allowed values:
0: FullDuplex: Full duplex
1: Transmitter: Simplex transmitter only
2: Receiver: Simplex receiver only
3: HalfDuplex: Half duplex

SP

Bits 19-21: Serial Protocol.

Allowed values:
0: Motorola: Motorola SPI protocol
1: TI: TI SPI protocol

MASTER

Bit 22: SPI Master.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

LSBFRST

Bit 23: Data frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

CPHA

Bit 24: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 25: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

SSM

Bit 26: Software management of SS signal input.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

SSIOP

Bit 28: SS input/output polarity.

Allowed values:
0: ActiveLow: Low level is active for SS signal
1: ActiveHigh: High level is active for SS signal

SSOE

Bit 29: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

SSOM

Bit 30: SS output management in master mode.

Allowed values:
0: Asserted: SS is asserted until data transfer complete
1: NotAsserted: Data frames interleaved with SS not asserted during MIDI

AFCNTR

Bit 31: Alternate function GPIOs control.

Allowed values:
0: NotControlled: Peripheral takes no control of GPIOs while disabled
1: Controlled: Peripheral controls GPIOs while disabled

IER

Interrupt Enable Register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

11/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSERFIE
rw
MODFIE
rw
TIFREIE
rw
CRCEIE
rw
OVRIE
rw
UDRIE
rw
TXTFIE
rw
EOTIE
rw
DXPIE
rw
TXPIE
rw
RXPIE
rw
Toggle fields

RXPIE

Bit 0: RXP Interrupt Enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TXPIE

Bit 1: TXP interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

DXPIE

Bit 2: DXP interrupt enabled.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

EOTIE

Bit 3: EOT, SUSP and TXC interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TXTFIE

Bit 4: TXTFIE interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

UDRIE

Bit 5: UDR interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

OVRIE

Bit 6: OVR interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CRCEIE

Bit 7: CRC Interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TIFREIE

Bit 8: TIFRE interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

MODFIE

Bit 9: Mode Fault interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TSERFIE

Bit 10: Additional number of transactions reload interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

SR

Status Register

Offset: 0x14, size: 32, reset: 0x00001002, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTSIZE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXWNE
r
RXPLVL
r
TXC
r
SUSP
r
TSERF
r
MODF
r
TIFRE
r
CRCE
r
OVR
r
UDR
r
TXTF
r
EOT
r
DXP
r
TXP
r
RXP
r
Toggle fields

RXP

Bit 0: Rx-Packet available.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXP

Bit 1: Tx-Packet space available.

Allowed values:
0: Full: Tx buffer full
1: NotFull: Tx buffer not full

DXP

Bit 2: Duplex Packet.

Allowed values:
0: Unavailable: Duplex packet unavailable: no space for transmission and/or no data received
1: Available: Duplex packet available: space for transmission and data received

EOT

Bit 3: End Of Transfer.

Allowed values:
0: NotCompleted: Transfer ongoing or not started
1: Completed: Transfer complete

TXTF

Bit 4: Transmission Transfer Filled.

Allowed values:
0: NotCompleted: Transmission buffer incomplete
1: Completed: Transmission buffer filled with at least one transfer

UDR

Bit 5: Underrun at slave transmission mode.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

OVR

Bit 6: Overrun.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

CRCE

Bit 7: CRC Error.

Allowed values:
0: NoError: No CRC error detected
1: Error: CRC error detected

TIFRE

Bit 8: TI frame format error.

Allowed values:
0: NoError: TI frame format error detected
1: Error: TI frame format error detected

MODF

Bit 9: Mode Fault.

Allowed values:
0: NoFault: No mode fault detected
1: Fault: Mode fault detected

TSERF

Bit 10: Additional number of SPI data to be transacted was reload.

Allowed values:
0: NotLoaded: Additional number of SPI data to be transacted not yet loaded
1: Loaded: Additional number of SPI data to be transacted was reloaded

SUSP

Bit 11: SUSPend.

Allowed values:
0: NotSuspended: Master not suspended
1: Suspended: Master suspended

TXC

Bit 12: TxFIFO transmission complete.

Allowed values:
0: Ongoing: Transmission ongoing
1: Completed: Transmission completed

RXPLVL

Bits 13-14: RxFIFO Packing LeVeL.

Allowed values:
0: ZeroFrames: Zero frames beyond packing ratio available
1: OneFrame: One frame beyond packing ratio available
2: TwoFrames: Two frame beyond packing ratio available
3: ThreeFrames: Three frame beyond packing ratio available

RXWNE

Bit 15: RxFIFO Word Not Empty.

Allowed values:
0: LessThan32: Less than 32-bit data frame received
1: AtLeast32: At least 32-bit data frame received

CTSIZE

Bits 16-31: Number of data frames remaining in current TSIZE session.

Allowed values: 0x0-0xffff

IFCR

Interrupt/Status Flags Clear Register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSPC
w1c
TSERFC
w1c
MODFC
w1c
TIFREC
w1c
CRCEC
w1c
OVRC
w1c
UDRC
w1c
TXTFC
w1c
EOTC
w1c
Toggle fields

EOTC

Bit 3: End Of Transfer flag clear.

Allowed values:
1: Clear: Clear interrupt flag

TXTFC

Bit 4: Transmission Transfer Filled flag clear.

Allowed values:
1: Clear: Clear interrupt flag

UDRC

Bit 5: Underrun flag clear.

Allowed values:
1: Clear: Clear interrupt flag

OVRC

Bit 6: Overrun flag clear.

Allowed values:
1: Clear: Clear interrupt flag

CRCEC

Bit 7: CRC Error flag clear.

Allowed values:
1: Clear: Clear interrupt flag

TIFREC

Bit 8: TI frame format error flag clear.

Allowed values:
1: Clear: Clear interrupt flag

MODFC

Bit 9: Mode Fault flag clear.

Allowed values:
1: Clear: Clear interrupt flag

TSERFC

Bit 10: TSERFC flag clear.

Allowed values:
1: Clear: Clear interrupt flag

SUSPC

Bit 11: SUSPend flag clear.

Allowed values:
1: Clear: Clear interrupt flag

TXDR

Transmit Data Register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXDR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDR
w
Toggle fields

TXDR

Bits 0-31: Transmit data register.

Allowed values: 0x0-0xffffffff

TXDR16

Direct 16-bit access to transmit data register

Offset: 0x20, size: 16, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDR
w
Toggle fields

TXDR

Bits 0-15: Transmit data register.

Allowed values: 0x0-0xffff

TXDR8

Direct 8-bit access to transmit data register

Offset: 0x20, size: 8, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDR
w
Toggle fields

TXDR

Bits 0-7: Transmit data register.

Allowed values: 0x0-0xff

RXDR

Receive Data Register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDR
r
Toggle fields

RXDR

Bits 0-31: Receive data register.

RXDR16

Direct 16-bit access to receive data register

Offset: 0x30, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDR
r
Toggle fields

RXDR

Bits 0-15: Receive data register.

RXDR8

Direct 8-bit access to receive data register

Offset: 0x30, size: 8, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDR
r
Toggle fields

RXDR

Bits 0-7: Receive data register.

CRCPOLY

Polynomial Register

Offset: 0x40, size: 32, reset: 0x00000107, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRCPOLY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-31: CRC polynomial register.

Allowed values: 0x0-0xffffffff

TXCRC

Transmitter CRC Register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXCRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXCRC
r
Toggle fields

TXCRC

Bits 0-31: CRC register for transmitter.

Allowed values: 0x0-0xffffffff

RXCRC

Receiver CRC Register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXCRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXCRC
r
Toggle fields

RXCRC

Bits 0-31: CRC register for receiver.

Allowed values: 0x0-0xffffffff

UDRDR

Underrun Data Register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UDRDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRDR
rw
Toggle fields

UDRDR

Bits 0-31: Data at slave underrun condition.

Allowed values: 0x0-0xffffffff

I2SCFGR

configuration register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

12/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCKOE
rw
ODD
rw
I2SDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATFMT
rw
WSINV
rw
FIXCH
rw
CKPOL
rw
CHLEN
rw
DATLEN
rw
PCMSYNC
rw
I2SSTD
rw
I2SCFG
rw
I2SMOD
rw
Toggle fields

I2SMOD

Bit 0: I2S mode selection.

Allowed values:
0: SPI: SPI mode selected
1: I2S: I2S/PCM mode selected

I2SCFG

Bits 1-3: I2S configuration mode.

Allowed values:
0: SlaveTransmit: Slave, transmit
1: SlaveReceive: Slave, recteive
2: MasterTransmit: Master, transmit
3: MasterReceive: Master, receive
4: SlaveFullDuplex: Slave, full duplex
5: MasterFullDuplex: Master, full duplex

I2SSTD

Bits 4-5: I2S standard selection.

Allowed values:
0: Philips: I2S Philips standard
1: LeftAligned: MSB/left justified standard
2: RightAligned: LSB/right justified standard
3: PCM: PCM standard

PCMSYNC

Bit 7: PCM frame synchronization.

Allowed values:
0: Short: Short PCM frame synchronization
1: Long: Long PCM frame synchronization

DATLEN

Bits 8-9: Data length to be transferred.

Allowed values:
0: Bits16: 16 bit data length
1: Bits24: 24 bit data length
2: Bits32: 32 bit data length

CHLEN

Bit 10: Channel length (number of bits per audio channel).

Allowed values:
0: Bits16: 16 bit per channel
1: Bits32: 32 bit per channel

CKPOL

Bit 11: Serial audio clock polarity.

Allowed values:
0: SampleOnRising: Signals are sampled on rising and changed on falling clock edges
1: SampleOnFalling: Signals are sampled on falling and changed on rising clock edges

FIXCH

Bit 12: Word select inversion.

Allowed values:
0: NotFixed: The channel length in slave mode is different from 16 or 32 bits (CHLEN not taken into account)
1: Fixed: The channel length in slave mode is supposed to be 16 or 32 bits (according to CHLEN)

WSINV

Bit 13: Fixed channel length in SLAVE.

Allowed values:
0: Disabled: Word select inversion disabled
1: Enabled: Word select inversion enabled

DATFMT

Bit 14: Data format.

Allowed values:
0: RightAligned: The data inside RXDR and TXDR are right aligned
1: LeftAligned: The data inside RXDR and TXDR are left aligned

I2SDIV

Bits 16-23: I2S linear prescaler.

ODD

Bit 24: Odd factor for the prescaler.

Allowed values:
0: Even: Real divider value is I2SDIV*2
1: Odd: Real divider value is I2SDIV*2 + 1

MCKOE

Bit 25: Master clock output enable.

Allowed values:
0: Disabled: Master clock output disabled
1: Enabled: Master clock output enabled

SPI6

0x58001400: Serial peripheral interface

93/94 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CFG1
0xc CFG2
0x10 IER
0x14 SR
0x18 IFCR
0x20 TXDR
0x20 (16-bit) TXDR16
0x20 (8-bit) TXDR8
0x30 RXDR
0x30 (16-bit) RXDR16
0x30 (8-bit) RXDR8
0x40 CRCPOLY
0x44 TXCRC
0x48 RXCRC
0x4c UDRDR
0x50 I2SCFGR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IOLOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCRCINI
rw
RCRCINI
rw
CRC33_17
rw
SSI
rw
HDDIR
rw
CSUSP
w
CSTART
rw
MASRX
rw
SPE
rw
Toggle fields

SPE

Bit 0: Serial Peripheral Enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

MASRX

Bit 8: Master automatic SUSP in Receive mode.

Allowed values:
0: Disabled: Automatic suspend in master receive-only mode disabled
1: Enabled: Automatic suspend in master receive-only mode enabled

CSTART

Bit 9: Master transfer start.

Allowed values:
0: NotStarted: Do not start master transfer
1: Started: Start master transfer

CSUSP

Bit 10: Master SUSPend request.

Allowed values:
0: NotRequested: Do not request master suspend
1: Requested: Request master suspend

HDDIR

Bit 11: Rx/Tx direction at Half-duplex mode.

Allowed values:
0: Receiver: Receiver in half duplex mode
1: Transmitter: Transmitter in half duplex mode

SSI

Bit 12: Internal SS signal input level.

Allowed values:
0: SlaveSelected: 0 is forced onto the SS signal and the I/O value of the SS pin is ignored
1: SlaveNotSelected: 1 is forced onto the SS signal and the I/O value of the SS pin is ignored

CRC33_17

Bit 13: 32-bit CRC polynomial configuration.

Allowed values:
0: Disabled: Full size (33/17 bit) CRC polynomial is not used
1: Enabled: Full size (33/17 bit) CRC polynomial is used

RCRCINI

Bit 14: CRC calculation initialization pattern control for receiver.

Allowed values:
0: AllZeros: All zeros RX CRC initialization pattern
1: AllOnes: All ones RX CRC initialization pattern

TCRCINI

Bit 15: CRC calculation initialization pattern control for transmitter.

Allowed values:
0: AllZeros: All zeros TX CRC initialization pattern
1: AllOnes: All ones TX CRC initialization pattern

IOLOCK

Bit 16: Locking the AF configuration of associated IOs.

Allowed values:
0: Unlocked: IO configuration unlocked
1: Locked: IO configuration locked

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSER
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSIZE
rw
Toggle fields

TSIZE

Bits 0-15: Number of data at current transfer.

Allowed values: 0x0-0xffff

TSER

Bits 16-31: Number of data transfer extension to be reload into TSIZE just when a previous.

Allowed values: 0x0-0xffff

CFG1

configuration register 1

Offset: 0x8, size: 32, reset: 0x00070007, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBR
rw
CRCEN
rw
CRCSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDMAEN
rw
RXDMAEN
rw
UDRDET
rw
UDRCFG
rw
FTHLV
rw
DSIZE
rw
Toggle fields

DSIZE

Bits 0-4: Number of bits in at single SPI data frame.

Allowed values: 0x0-0x1f

FTHLV

Bits 5-8: threshold level.

Allowed values:
0: OneFrame: 1 frame
1: TwoFrames: 2 frames
2: ThreeFrames: 3 frames
3: FourFrames: 4 frames
4: FiveFrames: 5 frames
5: SixFrames: 6 frames
6: SevenFrames: 7 frames
7: EightFrames: 8 frames
8: NineFrames: 9 frames
9: TenFrames: 10 frames
10: ElevenFrames: 11 frames
11: TwelveFrames: 12 frames
12: ThirteenFrames: 13 frames
13: FourteenFrames: 14 frames
14: FifteenFrames: 15 frames
15: SixteenFrames: 16 frames

UDRCFG

Bits 9-10: Behavior of slave transmitter at underrun condition.

Allowed values:
0: Constant: Slave sends a constant underrun pattern
1: RepeatReceived: Slave repeats last received data frame from master
2: RepeatTransmitted: Slave repeats last transmitted data frame

UDRDET

Bits 11-12: Detection of underrun condition at slave transmitter.

Allowed values:
0: StartOfFrame: Underrun is detected at begin of data frame
1: EndOfFrame: Underrun is detected at end of last data frame
2: StartOfSlaveSelect: Underrun is detected at begin of active SS signal

RXDMAEN

Bit 14: Rx DMA stream enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 15: Tx DMA stream enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

CRCSIZE

Bits 16-20: Length of CRC frame to be transacted and compared.

Allowed values: 0x0-0x1f

CRCEN

Bit 22: Hardware CRC computation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

MBR

Bits 28-30: Master baud rate.

Allowed values:
0: Div2: f_spi_ker_ck / 2
1: Div4: f_spi_ker_ck / 4
2: Div8: f_spi_ker_ck / 8
3: Div16: f_spi_ker_ck / 16
4: Div32: f_spi_ker_ck / 32
5: Div64: f_spi_ker_ck / 64
6: Div128: f_spi_ker_ck / 128
7: Div256: f_spi_ker_ck / 256

CFG2

configuration register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFCNTR
rw
SSOM
rw
SSOE
rw
SSIOP
rw
SSM
rw
CPOL
rw
CPHA
rw
LSBFRST
rw
MASTER
rw
SP
rw
COMM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSWP
rw
MIDI
rw
MSSI
rw
Toggle fields

MSSI

Bits 0-3: Master SS Idleness.

Allowed values: 0x0-0xf

MIDI

Bits 4-7: Master Inter-Data Idleness.

Allowed values: 0x0-0xf

IOSWP

Bit 15: Swap functionality of MISO and MOSI pins.

Allowed values:
0: Disabled: MISO and MOSI not swapped
1: Enabled: MISO and MOSI swapped

COMM

Bits 17-18: SPI Communication Mode.

Allowed values:
0: FullDuplex: Full duplex
1: Transmitter: Simplex transmitter only
2: Receiver: Simplex receiver only
3: HalfDuplex: Half duplex

SP

Bits 19-21: Serial Protocol.

Allowed values:
0: Motorola: Motorola SPI protocol
1: TI: TI SPI protocol

MASTER

Bit 22: SPI Master.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

LSBFRST

Bit 23: Data frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

CPHA

Bit 24: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 25: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

SSM

Bit 26: Software management of SS signal input.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

SSIOP

Bit 28: SS input/output polarity.

Allowed values:
0: ActiveLow: Low level is active for SS signal
1: ActiveHigh: High level is active for SS signal

SSOE

Bit 29: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

SSOM

Bit 30: SS output management in master mode.

Allowed values:
0: Asserted: SS is asserted until data transfer complete
1: NotAsserted: Data frames interleaved with SS not asserted during MIDI

AFCNTR

Bit 31: Alternate function GPIOs control.

Allowed values:
0: NotControlled: Peripheral takes no control of GPIOs while disabled
1: Controlled: Peripheral controls GPIOs while disabled

IER

Interrupt Enable Register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

11/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSERFIE
rw
MODFIE
rw
TIFREIE
rw
CRCEIE
rw
OVRIE
rw
UDRIE
rw
TXTFIE
rw
EOTIE
rw
DXPIE
rw
TXPIE
rw
RXPIE
rw
Toggle fields

RXPIE

Bit 0: RXP Interrupt Enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TXPIE

Bit 1: TXP interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

DXPIE

Bit 2: DXP interrupt enabled.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

EOTIE

Bit 3: EOT, SUSP and TXC interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TXTFIE

Bit 4: TXTFIE interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

UDRIE

Bit 5: UDR interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

OVRIE

Bit 6: OVR interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

CRCEIE

Bit 7: CRC Interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TIFREIE

Bit 8: TIFRE interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

MODFIE

Bit 9: Mode Fault interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TSERFIE

Bit 10: Additional number of transactions reload interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

SR

Status Register

Offset: 0x14, size: 32, reset: 0x00001002, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTSIZE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXWNE
r
RXPLVL
r
TXC
r
SUSP
r
TSERF
r
MODF
r
TIFRE
r
CRCE
r
OVR
r
UDR
r
TXTF
r
EOT
r
DXP
r
TXP
r
RXP
r
Toggle fields

RXP

Bit 0: Rx-Packet available.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXP

Bit 1: Tx-Packet space available.

Allowed values:
0: Full: Tx buffer full
1: NotFull: Tx buffer not full

DXP

Bit 2: Duplex Packet.

Allowed values:
0: Unavailable: Duplex packet unavailable: no space for transmission and/or no data received
1: Available: Duplex packet available: space for transmission and data received

EOT

Bit 3: End Of Transfer.

Allowed values:
0: NotCompleted: Transfer ongoing or not started
1: Completed: Transfer complete

TXTF

Bit 4: Transmission Transfer Filled.

Allowed values:
0: NotCompleted: Transmission buffer incomplete
1: Completed: Transmission buffer filled with at least one transfer

UDR

Bit 5: Underrun at slave transmission mode.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

OVR

Bit 6: Overrun.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

CRCE

Bit 7: CRC Error.

Allowed values:
0: NoError: No CRC error detected
1: Error: CRC error detected

TIFRE

Bit 8: TI frame format error.

Allowed values:
0: NoError: TI frame format error detected
1: Error: TI frame format error detected

MODF

Bit 9: Mode Fault.

Allowed values:
0: NoFault: No mode fault detected
1: Fault: Mode fault detected

TSERF

Bit 10: Additional number of SPI data to be transacted was reload.

Allowed values:
0: NotLoaded: Additional number of SPI data to be transacted not yet loaded
1: Loaded: Additional number of SPI data to be transacted was reloaded

SUSP

Bit 11: SUSPend.

Allowed values:
0: NotSuspended: Master not suspended
1: Suspended: Master suspended

TXC

Bit 12: TxFIFO transmission complete.

Allowed values:
0: Ongoing: Transmission ongoing
1: Completed: Transmission completed

RXPLVL

Bits 13-14: RxFIFO Packing LeVeL.

Allowed values:
0: ZeroFrames: Zero frames beyond packing ratio available
1: OneFrame: One frame beyond packing ratio available
2: TwoFrames: Two frame beyond packing ratio available
3: ThreeFrames: Three frame beyond packing ratio available

RXWNE

Bit 15: RxFIFO Word Not Empty.

Allowed values:
0: LessThan32: Less than 32-bit data frame received
1: AtLeast32: At least 32-bit data frame received

CTSIZE

Bits 16-31: Number of data frames remaining in current TSIZE session.

Allowed values: 0x0-0xffff

IFCR

Interrupt/Status Flags Clear Register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSPC
w1c
TSERFC
w1c
MODFC
w1c
TIFREC
w1c
CRCEC
w1c
OVRC
w1c
UDRC
w1c
TXTFC
w1c
EOTC
w1c
Toggle fields

EOTC

Bit 3: End Of Transfer flag clear.

Allowed values:
1: Clear: Clear interrupt flag

TXTFC

Bit 4: Transmission Transfer Filled flag clear.

Allowed values:
1: Clear: Clear interrupt flag

UDRC

Bit 5: Underrun flag clear.

Allowed values:
1: Clear: Clear interrupt flag

OVRC

Bit 6: Overrun flag clear.

Allowed values:
1: Clear: Clear interrupt flag

CRCEC

Bit 7: CRC Error flag clear.

Allowed values:
1: Clear: Clear interrupt flag

TIFREC

Bit 8: TI frame format error flag clear.

Allowed values:
1: Clear: Clear interrupt flag

MODFC

Bit 9: Mode Fault flag clear.

Allowed values:
1: Clear: Clear interrupt flag

TSERFC

Bit 10: TSERFC flag clear.

Allowed values:
1: Clear: Clear interrupt flag

SUSPC

Bit 11: SUSPend flag clear.

Allowed values:
1: Clear: Clear interrupt flag

TXDR

Transmit Data Register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXDR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDR
w
Toggle fields

TXDR

Bits 0-31: Transmit data register.

Allowed values: 0x0-0xffffffff

TXDR16

Direct 16-bit access to transmit data register

Offset: 0x20, size: 16, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDR
w
Toggle fields

TXDR

Bits 0-15: Transmit data register.

Allowed values: 0x0-0xffff

TXDR8

Direct 8-bit access to transmit data register

Offset: 0x20, size: 8, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDR
w
Toggle fields

TXDR

Bits 0-7: Transmit data register.

Allowed values: 0x0-0xff

RXDR

Receive Data Register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDR
r
Toggle fields

RXDR

Bits 0-31: Receive data register.

RXDR16

Direct 16-bit access to receive data register

Offset: 0x30, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDR
r
Toggle fields

RXDR

Bits 0-15: Receive data register.

RXDR8

Direct 8-bit access to receive data register

Offset: 0x30, size: 8, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDR
r
Toggle fields

RXDR

Bits 0-7: Receive data register.

CRCPOLY

Polynomial Register

Offset: 0x40, size: 32, reset: 0x00000107, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRCPOLY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-31: CRC polynomial register.

Allowed values: 0x0-0xffffffff

TXCRC

Transmitter CRC Register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXCRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXCRC
r
Toggle fields

TXCRC

Bits 0-31: CRC register for transmitter.

Allowed values: 0x0-0xffffffff

RXCRC

Receiver CRC Register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXCRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXCRC
r
Toggle fields

RXCRC

Bits 0-31: CRC register for receiver.

Allowed values: 0x0-0xffffffff

UDRDR

Underrun Data Register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UDRDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRDR
rw
Toggle fields

UDRDR

Bits 0-31: Data at slave underrun condition.

Allowed values: 0x0-0xffffffff

I2SCFGR

configuration register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

12/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCKOE
rw
ODD
rw
I2SDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATFMT
rw
WSINV
rw
FIXCH
rw
CKPOL
rw
CHLEN
rw
DATLEN
rw
PCMSYNC
rw
I2SSTD
rw
I2SCFG
rw
I2SMOD
rw
Toggle fields

I2SMOD

Bit 0: I2S mode selection.

Allowed values:
0: SPI: SPI mode selected
1: I2S: I2S/PCM mode selected

I2SCFG

Bits 1-3: I2S configuration mode.

Allowed values:
0: SlaveTransmit: Slave, transmit
1: SlaveReceive: Slave, recteive
2: MasterTransmit: Master, transmit
3: MasterReceive: Master, receive
4: SlaveFullDuplex: Slave, full duplex
5: MasterFullDuplex: Master, full duplex

I2SSTD

Bits 4-5: I2S standard selection.

Allowed values:
0: Philips: I2S Philips standard
1: LeftAligned: MSB/left justified standard
2: RightAligned: LSB/right justified standard
3: PCM: PCM standard

PCMSYNC

Bit 7: PCM frame synchronization.

Allowed values:
0: Short: Short PCM frame synchronization
1: Long: Long PCM frame synchronization

DATLEN

Bits 8-9: Data length to be transferred.

Allowed values:
0: Bits16: 16 bit data length
1: Bits24: 24 bit data length
2: Bits32: 32 bit data length

CHLEN

Bit 10: Channel length (number of bits per audio channel).

Allowed values:
0: Bits16: 16 bit per channel
1: Bits32: 32 bit per channel

CKPOL

Bit 11: Serial audio clock polarity.

Allowed values:
0: SampleOnRising: Signals are sampled on rising and changed on falling clock edges
1: SampleOnFalling: Signals are sampled on falling and changed on rising clock edges

FIXCH

Bit 12: Word select inversion.

Allowed values:
0: NotFixed: The channel length in slave mode is different from 16 or 32 bits (CHLEN not taken into account)
1: Fixed: The channel length in slave mode is supposed to be 16 or 32 bits (according to CHLEN)

WSINV

Bit 13: Fixed channel length in SLAVE.

Allowed values:
0: Disabled: Word select inversion disabled
1: Enabled: Word select inversion enabled

DATFMT

Bit 14: Data format.

Allowed values:
0: RightAligned: The data inside RXDR and TXDR are right aligned
1: LeftAligned: The data inside RXDR and TXDR are left aligned

I2SDIV

Bits 16-23: I2S linear prescaler.

ODD

Bit 24: Odd factor for the prescaler.

Allowed values:
0: Even: Real divider value is I2SDIV*2
1: Odd: Real divider value is I2SDIV*2 + 1

MCKOE

Bit 25: Master clock output enable.

Allowed values:
0: Disabled: Master clock output disabled
1: Enabled: Master clock output enabled

SWPMI

0x40008800: Single Wire Protocol Master Interface

14/44 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 BRR
0xc ISR
0x10 ICR
0x14 IER
0x18 RFL
0x1c TDR
0x20 RDR
0x24 OR
Toggle registers

CR

SWPMI Configuration/Control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWPTEN
rw
DEACT
rw
SWPACT
rw
LPBK
rw
TXMODE
rw
RXMODE
rw
TXDMA
rw
RXDMA
rw
Toggle fields

RXDMA

Bit 0: Reception DMA enable.

TXDMA

Bit 1: Transmission DMA enable.

RXMODE

Bit 2: Reception buffering mode.

TXMODE

Bit 3: Transmission buffering mode.

LPBK

Bit 4: Loopback mode enable.

SWPACT

Bit 5: Single wire protocol master interface activate.

DEACT

Bit 10: Single wire protocol master interface deactivate.

SWPTEN

Bit 11: Single wire protocol master transceiver enable.

BRR

SWPMI Bitrate register

Offset: 0x4, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR
rw
Toggle fields

BR

Bits 0-7: Bitrate prescaler.

ISR

SWPMI Interrupt and Status register

Offset: 0xc, size: 32, reset: 0x000002C2, access: read-only

12/12 fields covered.

Toggle fields

RXBFF

Bit 0: Receive buffer full flag.

TXBEF

Bit 1: Transmit buffer empty flag.

RXBERF

Bit 2: Receive CRC error flag.

RXOVRF

Bit 3: Receive overrun error flag.

TXUNRF

Bit 4: Transmit underrun error flag.

RXNE

Bit 5: Receive data register not empty.

TXE

Bit 6: Transmit data register empty.

TCF

Bit 7: Transfer complete flag.

SRF

Bit 8: Slave resume flag.

SUSP

Bit 9: SUSPEND flag.

DEACTF

Bit 10: DEACTIVATED flag.

RDYF

Bit 11: transceiver ready flag.

ICR

SWPMI Interrupt Flag Clear register

Offset: 0x10, size: 32, reset: 0x00000000, access: write-only

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRDYF
w
CSRF
w
CTCF
w
CTXUNRF
w
CRXOVRF
w
CRXBERF
w
CTXBEF
w
CRXBFF
w
Toggle fields

CRXBFF

Bit 0: Clear receive buffer full flag.

CTXBEF

Bit 1: Clear transmit buffer empty flag.

CRXBERF

Bit 2: Clear receive CRC error flag.

CRXOVRF

Bit 3: Clear receive overrun error flag.

CTXUNRF

Bit 4: Clear transmit underrun error flag.

CTCF

Bit 7: Clear transfer complete flag.

CSRF

Bit 8: Clear slave resume flag.

CRDYF

Bit 11: Clear transceiver ready flag.

IER

SWPMI Interrupt Enable register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDYIE
rw
SRIE
rw
TCIE
rw
TIE
rw
RIE
rw
TXUNRIE
rw
RXOVRIE
rw
RXBERIE
rw
TXBEIE
rw
RXBFIE
rw
Toggle fields

RXBFIE

Bit 0: Receive buffer full interrupt enable.

TXBEIE

Bit 1: Transmit buffer empty interrupt enable.

RXBERIE

Bit 2: Receive CRC error interrupt enable.

RXOVRIE

Bit 3: Receive overrun error interrupt enable.

TXUNRIE

Bit 4: Transmit underrun error interrupt enable.

RIE

Bit 5: Receive interrupt enable.

TIE

Bit 6: Transmit interrupt enable.

TCIE

Bit 7: Transmit complete interrupt enable.

SRIE

Bit 8: Slave resume interrupt enable.

RDYIE

Bit 11: Transceiver ready interrupt enable.

RFL

SWPMI Receive Frame Length register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFL
r
Toggle fields

RFL

Bits 0-4: Receive frame length.

TDR

SWPMI Transmit data register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TD
w
Toggle fields

TD

Bits 0-31: Transmit data.

RDR

SWPMI Receive data register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RD
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RD
r
Toggle fields

RD

Bits 0-31: received data.

OR

SWPMI Option register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWP_CLASS
rw
SWP_TBYP
rw
Toggle fields

SWP_TBYP

Bit 0: SWP transceiver bypass.

SWP_CLASS

Bit 1: SWP class selection.

SYSCFG

0x58000400: System configuration controller

2/41 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x4 PMCR
0x8 EXTICR1
0xc EXTICR2
0x10 EXTICR3
0x14 EXTICR4
0x18 CFGR
0x20 CCCSR
0x24 CCVR
0x28 CCCR
Toggle registers

PMCR

peripheral mode configuration register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PC3SO
rw
PC2SO
rw
PA1SO
rw
PA0SO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PB9FMP
rw
PB8FMP
rw
PB7FMP
rw
PB6FMP
rw
I2C4FMP
rw
I2C3FMP
rw
I2C2FMP
rw
I2C1FMP
rw
Toggle fields

I2C1FMP

Bit 0: I2C1 Fm+.

I2C2FMP

Bit 1: I2C2 Fm+.

I2C3FMP

Bit 2: I2C3 Fm+.

I2C4FMP

Bit 3: I2C4 Fm+.

PB6FMP

Bit 4: PB(6) Fm+.

PB7FMP

Bit 5: PB(7) Fast Mode Plus.

PB8FMP

Bit 6: PB(8) Fast Mode Plus.

PB9FMP

Bit 7: PB(9) Fm+.

PA0SO

Bit 24: PA0 Switch Open.

PA1SO

Bit 25: PA1 Switch Open.

PC2SO

Bit 26: PC2 Switch Open.

PC3SO

Bit 27: PC3 Switch Open.

EXTICR1

external interrupt configuration register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI3
rw
EXTI2
rw
EXTI1
rw
EXTI0
rw
Toggle fields

EXTI0

Bits 0-3: EXTI x configuration (x = 0 to 3).

EXTI1

Bits 4-7: EXTI x configuration (x = 0 to 3).

EXTI2

Bits 8-11: EXTI x configuration (x = 0 to 3).

EXTI3

Bits 12-15: EXTI x configuration (x = 0 to 3).

EXTICR2

external interrupt configuration register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI7
rw
EXTI6
rw
EXTI5
rw
EXTI4
rw
Toggle fields

EXTI4

Bits 0-3: EXTI x configuration (x = 4 to 7).

EXTI5

Bits 4-7: EXTI x configuration (x = 4 to 7).

EXTI6

Bits 8-11: EXTI x configuration (x = 4 to 7).

EXTI7

Bits 12-15: EXTI x configuration (x = 4 to 7).

EXTICR3

external interrupt configuration register 3

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI11
rw
EXTI10
rw
EXTI9
rw
EXTI8
rw
Toggle fields

EXTI8

Bits 0-3: EXTI x configuration (x = 8 to 11).

EXTI9

Bits 4-7: EXTI x configuration (x = 8 to 11).

EXTI10

Bits 8-11: EXTI10.

EXTI11

Bits 12-15: EXTI x configuration (x = 8 to 11).

EXTICR4

external interrupt configuration register 4

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI15
rw
EXTI14
rw
EXTI13
rw
EXTI12
rw
Toggle fields

EXTI12

Bits 0-3: EXTI x configuration (x = 12 to 15).

EXTI13

Bits 4-7: EXTI x configuration (x = 12 to 15).

EXTI14

Bits 8-11: EXTI x configuration (x = 12 to 15).

EXTI15

Bits 12-15: EXTI x configuration (x = 12 to 15).

CFGR

SYSCFG timer break lockup register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITCML
rw
DTCML
rw
CM7L
rw
FLASHL
rw
PVDL
rw
Toggle fields

PVDL

Bit 2: PVD lock enable bit..

FLASHL

Bit 3: Flash double ECC error lock bit.

CM7L

Bit 6: Cortex®-M7 LOCKUP (HardFault) output enable bit.

DTCML

Bit 13: D1TCM or D0TCM double ECC error signal lock.

ITCML

Bit 14: ITCM double ECC error signal lock.

CCCSR

compensation cell control/status register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HSLV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
READY
rw
CS
rw
EN
rw
Toggle fields

EN

Bit 0: enable.

CS

Bit 1: Code selection.

READY

Bit 8: Compensation cell ready flag.

HSLV

Bit 16: High-speed at low-voltage.

CCVR

SYSCFG compensation cell value register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCV
r
NCV
r
Toggle fields

NCV

Bits 0-3: NMOS compensation value.

PCV

Bits 4-7: PMOS compensation value.

CCCR

SYSCFG compensation cell code register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCC
rw
NCC
rw
Toggle fields

NCC

Bits 0-3: NMOS compensation code.

PCC

Bits 4-7: PMOS compensation code.

TAMP

0x58004400: Tamper and backup

24/111 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc FLTCR
0x10 ATCR1
0x14 ATSEEDR
0x18 ATOR
0x2c IER
0x30 SR
0x34 MISR
0x3c SCR
0x40 COUNTR
0x50 CFGR
0x100 BKP0R
0x104 BKP1R
0x108 BKP2R
0x10c BKP3R
0x110 BKP4R
0x114 BKP5R
0x118 BKP6R
0x11c BKP7R
0x120 BKP8R
0x124 BKP9R
0x128 BKP10R
0x12c BKP11R
0x130 BKP12R
0x134 BKP13R
0x138 BKP14R
0x13c BKP15R
0x140 BKP16R
0x144 BKP17R
0x148 BKP18R
0x14c BKP19R
0x150 BKP20R
0x154 BKP21R
0x158 BKP22R
0x15c BKP23R
0x160 BKP24R
0x164 BKP25R
0x168 BKP26R
0x16c BKP27R
0x170 BKP28R
0x174 BKP29R
0x178 BKP30R
0x17c BKP31R
Toggle registers

CR1

TAMP control register 1

Offset: 0x0, size: 32, reset: 0xFFFF0000, access: Unspecified

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP8E
rw
ITAMP6E
rw
ITAMP5E
rw
ITAMP4E
rw
ITAMP3E
rw
ITAMP2E
rw
ITAMP1E
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP3E
rw
TAMP2E
rw
TAMP1E
rw
Toggle fields

TAMP1E

Bit 0: Tamper detection on TAMP_IN1 enable.

TAMP2E

Bit 1: Tamper detection on TAMP_IN2 enable.

TAMP3E

Bit 2: Tamper detection on TAMP_IN3 enable.

ITAMP1E

Bit 16: Internal tamper 1 enable: RTC power domain supply monitoring.

ITAMP2E

Bit 17: Internal tamper 2 enable: Temperature monitoring.

ITAMP3E

Bit 18: Internal tamper 3 enable: LSE monitoring.

ITAMP4E

Bit 19: Internal tamper 4 enable: HSE monitoring.

ITAMP5E

Bit 20: Internal tamper 5 enable: RTC calendar overflow.

ITAMP6E

Bit 21: Internal tamper 6 enable: ST manufacturer readout.

ITAMP8E

Bit 23: Internal tamper 8 enable: monotonic counter overflow.

CR2

TAMP control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TAMP3TRG
rw
TAMP2TRG
rw
TAMP1TRG
rw
TAMP3MSK
rw
TAMP2MSK
rw
TAMP1MSK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP3NOER
rw
TAMP2NOER
rw
TAMP1NOER
rw
Toggle fields

TAMP1NOER

Bit 0: Tamper 1 no erase.

TAMP2NOER

Bit 1: Tamper 2 no erase.

TAMP3NOER

Bit 2: Tamper 3 no erase.

TAMP1MSK

Bit 16: Tamper 1 mask The tamper 1 interrupt must not be enabled when TAMP1MSK is set..

TAMP2MSK

Bit 17: Tamper 2 mask The tamper 2 interrupt must not be enabled when TAMP2MSK is set..

TAMP3MSK

Bit 18: Tamper 3 mask The tamper 3 interrupt must not be enabled when TAMP3MSK is set..

TAMP1TRG

Bit 24: Active level for tamper 1 input (active mode disabled) If TAMPFLT = 00 Tamper 1 input rising edge and high level triggers a tamper detection event. If TAMPFLT = 00 Tamper 1 input falling edge and low level triggers a tamper detection event..

TAMP2TRG

Bit 25: Active level for tamper 2 input (active mode disabled) If TAMPFLT = 00 Tamper 2 input rising edge and high level triggers a tamper detection event. If TAMPFLT = 00 Tamper 2 input falling edge and low level triggers a tamper detection event..

TAMP3TRG

Bit 26: Active level for tamper 3 input (active mode disabled) If TAMPFLT = 00 Tamper 3 input rising edge and high level triggers a tamper detection event. If TAMPFLT = 00 Tamper 3 input falling edge and low level triggers a tamper detection event..

FLTCR

TAMP filter control register

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMPPUDIS
rw
TAMPPRCH
rw
TAMPFLT
rw
TAMPFREQ
rw
Toggle fields

TAMPFREQ

Bits 0-2: Tamper sampling frequency Determines the frequency at which each of the TAMP_INx inputs are sampled..

TAMPFLT

Bits 3-4: TAMP_INx filter count These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a tamper event. TAMPFLT is valid for each of the TAMP_INx inputs..

TAMPPRCH

Bits 5-6: TAMP_INx precharge duration These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the TAMP_INx inputs..

TAMPPUDIS

Bit 7: TAMP_INx pull-up disable This bit determines if each of the TAMPx pins are precharged before each sample..

ATCR1

TAMP active tamper control register 1

Offset: 0x10, size: 32, reset: 0x00070000, access: Unspecified

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLTEN
rw
ATOSHARE
rw
ATPER
rw
ATCKSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATOSEL3
rw
ATOSEL2
rw
ATOSEL1
rw
TAMP3AM
rw
TAMP2AM
rw
TAMP1AM
rw
Toggle fields

TAMP1AM

Bit 0: Tamper 1 active mode.

TAMP2AM

Bit 1: Tamper 2 active mode.

TAMP3AM

Bit 2: Tamper 3 active mode.

ATOSEL1

Bits 8-9: Active tamper shared output 1 selection The selected output must be available in the package pinout.

ATOSEL2

Bits 10-11: Active tamper shared output 2 selection The selected output must be available in the package pinout.

ATOSEL3

Bits 12-13: Active tamper shared output 3 selection The selected output must be available in the package pinout.

ATCKSEL

Bits 16-18: Active tamper RTC asynchronous prescaler clock selection These bits selects the RTC asynchronous prescaler stage output.The selected clock is CK_ATPRE. fCK_ATPRE = fRTCCLK / 2ATCKSEL when (PREDIV_A+1) = 128. ... Note: These bits can be written only when all active tampers are disabled. The write protection remains for up to 1.5 ck_atpre cycles after all the active tampers are disable..

ATPER

Bits 24-26: Active tamper output change period The tamper output is changed every CK_ATPER = (2ATPER x CK_ATPRE) cycles. Refer to ..

ATOSHARE

Bit 30: Active tamper output sharing.

FLTEN

Bit 31: Active tamper filter enable.

ATSEEDR

TAMP active tamper seed register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SEED
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEED
w
Toggle fields

SEED

Bits 0-31: Pseudo-random generator seed value This register must be written four times with 32-bit values to provide the 128-bit seed to the PRNG. Writing to this register automatically sends the seed value to the PRNG..

ATOR

TAMP active tamper output register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INITS
r
SEEDF
r
PRNG
r
Toggle fields

PRNG

Bits 0-7: Pseudo-random generator value This field provides the values of the PRNG output. Because of potential inconsistencies due to synchronization delays, PRNG must be read at least twice. The read value is correct if it is equal to previous read value..

SEEDF

Bit 14: Seed running flag This flag is set by hardware when a new seed is written in the TAMP_ATSEEDR. It is cleared by hardware when the PRNG has absorbed this new seed, and by system reset. The TAMP APB cock must not be switched off as long as SEEDF is set..

INITS

Bit 15: Active tamper initialization status This flag is set by hardware when the PRNG has absorbed the first 128-bit seed, meaning that the enabled active tampers are functional. This flag is left unchanged when the active tampers are disabled..

IER

TAMP interrupt enable register

Offset: 0x2c, size: 32, reset: 0x00000000, access: Unspecified

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP8IE
rw
ITAMP6IE
rw
ITAMP5IE
rw
ITAMP4IE
rw
ITAMP3IE
rw
ITAMP2IE
rw
ITAMP1IE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP3IE
rw
TAMP2IE
rw
TAMP1IE
rw
Toggle fields

TAMP1IE

Bit 0: Tamper 1 interrupt enable.

TAMP2IE

Bit 1: Tamper 2 interrupt enable.

TAMP3IE

Bit 2: Tamper 3 interrupt enable.

ITAMP1IE

Bit 16: Internal tamper 1 interrupt enable: RTC power domain supply monitoring.

ITAMP2IE

Bit 17: Internal tamper 2 interrupt enable: Temperature monitoring.

ITAMP3IE

Bit 18: Internal tamper 3 interrupt enable: LSE monitoring.

ITAMP4IE

Bit 19: Internal tamper 4 interrupt enable: HSE monitoring.

ITAMP5IE

Bit 20: Internal tamper 5 interrupt enable: RTC calendar overflow.

ITAMP6IE

Bit 21: Internal tamper 6 interrupt enable: ST manufacturer readout.

ITAMP8IE

Bit 23: Internal tamper 8 interrupt enable: monotonic counter overflow.

SR

TAMP status register

Offset: 0x30, size: 32, reset: 0x00000000, access: Unspecified

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP8F
r
ITAMP6F
r
ITAMP5F
r
ITAMP4F
r
ITAMP3F
r
ITAMP2F
r
ITAMP1F
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP3F
r
TAMP2F
r
TAMP1F
r
Toggle fields

TAMP1F

Bit 0: TAMP1 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP1 input..

TAMP2F

Bit 1: TAMP2 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP2 input..

TAMP3F

Bit 2: TAMP3 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP3 input..

ITAMP1F

Bit 16: RTC power domain voltage monitoring tamper detection flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 1..

ITAMP2F

Bit 17: Temperature monitoring tamper detection flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 2..

ITAMP3F

Bit 18: LSE monitoring tamper detection flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 3..

ITAMP4F

Bit 19: HSE monitoring tamper detection flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 4..

ITAMP5F

Bit 20: RTC calendar overflow tamper detection flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 5..

ITAMP6F

Bit 21: ST manufacturer readout tamper detection flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 6..

ITAMP8F

Bit 23: Monotonic counter overflow tamper flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 8..

MISR

TAMP masked interrupt status register

Offset: 0x34, size: 32, reset: 0x00000000, access: Unspecified

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP8MF
r
ITAMP6MF
r
ITAMP5MF
r
ITAMP4MF
r
ITAMP3MF
r
ITAMP2MF
r
ITAMP1MF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP3MF
r
TAMP2MF
r
TAMP1MF
r
Toggle fields

TAMP1MF

Bit 0: TAMP1 interrupt masked flag This flag is set by hardware when the tamper 1 interrupt is raised..

TAMP2MF

Bit 1: TAMP2 interrupt masked flag This flag is set by hardware when the tamper 2 interrupt is raised..

TAMP3MF

Bit 2: TAMP3 interrupt masked flag This flag is set by hardware when the tamper 3 interrupt is raised..

ITAMP1MF

Bit 16: RTC power domain voltage monitoring tamper interrupt masked flag This flag is set by hardware when the internal tamper 1 interrupt is raised..

ITAMP2MF

Bit 17: Temperature monitoring tamper interrupt masked flag This flag is set by hardware when the internal tamper 2 interrupt is raised..

ITAMP3MF

Bit 18: LSE monitoring tamper interrupt masked flag This flag is set by hardware when the internal tamper 3 interrupt is raised..

ITAMP4MF

Bit 19: HSE monitoring tamper interrupt masked flag This flag is set by hardware when the internal tamper 4 interrupt is raised..

ITAMP5MF

Bit 20: RTC calendar overflow tamper interrupt masked flag This flag is set by hardware when the internal tamper 5 interrupt is raised..

ITAMP6MF

Bit 21: ST manufacturer readout tamper interrupt masked flag This flag is set by hardware when the internal tamper 6 interrupt is raised..

ITAMP8MF

Bit 23: Monotonic counter overflow interrupt masked flag This flag is set by hardware when the internal tamper 8 interrupt is raised..

SCR

TAMP status clear register

Offset: 0x3c, size: 32, reset: 0x00000000, access: Unspecified

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CITAMP8F
w
CITAMP6F
w
CITAMP5F
w
CITAMP4F
w
CITAMP3F
w
CITAMP2F
w
CITAMP1F
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTAMP3F
w
CTAMP2F
w
CTAMP1F
w
Toggle fields

CTAMP1F

Bit 0: Clear TAMP1 detection flag Writing 1 in this bit clears the TAMP1F bit in the TAMP_SR register..

CTAMP2F

Bit 1: Clear TAMP2 detection flag Writing 1 in this bit clears the TAMP2F bit in the TAMP_SR register..

CTAMP3F

Bit 2: Clear TAMP3 detection flag Writing 1 in this bit clears the TAMP3F bit in the TAMP_SR register..

CITAMP1F

Bit 16: Clear ITAMP1 detection flag Writing 1 in this bit clears the ITAMP1F bit in the TAMP_SR register..

CITAMP2F

Bit 17: Clear ITAMP2 detection flag Writing 1 in this bit clears the ITAMP2F bit in the TAMP_SR register..

CITAMP3F

Bit 18: Clear ITAMP3 detection flag Writing 1 in this bit clears the ITAMP3F bit in the TAMP_SR register..

CITAMP4F

Bit 19: Clear ITAMP4 detection flag Writing 1 in this bit clears the ITAMP4F bit in the TAMP_SR register..

CITAMP5F

Bit 20: Clear ITAMP5 detection flag Writing 1 in this bit clears the ITAMP5F bit in the TAMP_SR register..

CITAMP6F

Bit 21: Clear ITAMP6 detection flag Writing 1 in this bit clears the ITAMP6F bit in the TAMP_SR register..

CITAMP8F

Bit 23: Clear ITAMP8 detection flag Writing 1 in this bit clears the ITAMP8F bit in the TAMP_SR register..

COUNTR

TAMP monotonic counter register

Offset: 0x40, size: 32, reset: 0x00000000, access: Unspecified

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COUNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COUNT
r
Toggle fields

COUNT

Bits 0-31: This register is read-only only and is incremented by one when a write access is done to this register. This register cannot roll-over and is frozen when reaching the maximum value..

CFGR

TAMP configuration register

Offset: 0x50, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUT3_RMP
rw
Toggle fields

OUT3_RMP

Bit 0: TAMP_OUT3 mapping.

BKP0R

TAMP backup 0 register

Offset: 0x100, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled..

BKP1R

TAMP backup 1 register

Offset: 0x104, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled..

BKP2R

TAMP backup 2 register

Offset: 0x108, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled..

BKP3R

TAMP backup 3 register

Offset: 0x10c, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled..

BKP4R

TAMP backup 4 register

Offset: 0x110, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled..

BKP5R

TAMP backup 5 register

Offset: 0x114, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled..

BKP6R

TAMP backup 6 register

Offset: 0x118, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled..

BKP7R

TAMP backup 7 register

Offset: 0x11c, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled..

BKP8R

TAMP backup 8 register

Offset: 0x120, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled..

BKP9R

TAMP backup 9 register

Offset: 0x124, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled..

BKP10R

TAMP backup 10 register

Offset: 0x128, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled..

BKP11R

TAMP backup 11 register

Offset: 0x12c, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled..

BKP12R

TAMP backup 12 register

Offset: 0x130, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled..

BKP13R

TAMP backup 13 register

Offset: 0x134, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled..

BKP14R

TAMP backup 14 register

Offset: 0x138, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled..

BKP15R

TAMP backup 15 register

Offset: 0x13c, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled..

BKP16R

TAMP backup 16 register

Offset: 0x140, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled..

BKP17R

TAMP backup 17 register

Offset: 0x144, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled..

BKP18R

TAMP backup 18 register

Offset: 0x148, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled..

BKP19R

TAMP backup 19 register

Offset: 0x14c, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled..

BKP20R

TAMP backup 20 register

Offset: 0x150, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled..

BKP21R

TAMP backup 21 register

Offset: 0x154, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled..

BKP22R

TAMP backup 22 register

Offset: 0x158, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled..

BKP23R

TAMP backup 23 register

Offset: 0x15c, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled..

BKP24R

TAMP backup 24 register

Offset: 0x160, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled..

BKP25R

TAMP backup 25 register

Offset: 0x164, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled..

BKP26R

TAMP backup 26 register

Offset: 0x168, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled..

BKP27R

TAMP backup 27 register

Offset: 0x16c, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled..

BKP28R

TAMP backup 28 register

Offset: 0x170, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled..

BKP29R

TAMP backup 29 register

Offset: 0x174, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled..

BKP30R

TAMP backup 30 register

Offset: 0x178, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled..

BKP31R

TAMP backup 31 register

Offset: 0x17c, size: 32, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled..

TIM1

0x40010000: Advanced-timers

157/186 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR[1]
0x38 CCR[2]
0x3c CCR[3]
0x40 CCR[4]
0x44 BDTR
0x48 DCR
0x4c DMAR
0x54 CCMR3_Output
0x58 CCR5
0x5c CCR6
0x60 AF1
0x64 AF2
0x68 TISEL
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
CMS
rw
DIR
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

14/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMS2
rw
OIS[6]
rw
OIS[5]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS[4]
rw
OIS[3]N
rw
OIS[3]
rw
OIS[2]N
rw
OIS[2]
rw
OIS[1]N
rw
OIS[1]
rw
TI1S
rw
MMS
rw
CCDS
rw
CCUS
rw
CCPC
rw
Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

Allowed values:
0: NotPreloaded: CCxE, CCxNE and OCxM bits are not preloaded
1: Preloaded: CCxE, CCxNE and OCxM bits are preloaded

CCUS

Bit 2: Capture/compare control update selection.

Allowed values:
0: Sw: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
1: SwOrEdge: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

OIS[1]

Bit 8: Output Idle state (OC1 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[1]N

Bit 9: Output Idle state (OC1N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[2]

Bit 10: Output Idle state (OC2 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[2]N

Bit 11: Output Idle state (OC2N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[3]

Bit 12: Output Idle state (OC3 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[3]N

Bit 13: Output Idle state (OC3N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[4]

Bit 14: Output Idle state (OC4 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[5]

Bit 16: Output Idle state (OC5 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[6]

Bit 18: Output Idle state (OC6 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

MMS2

Bits 20-23: Master mode selection 2.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

7/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS2
rw
SMS_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw
ECE
rw
ETPS
rw
ETF
rw
MSM
rw
TS
rw
SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

SMS_3

Bit 16: Slave mode selection - bit 3.

TS2

Bits 20-21: Trigger selection - bit 4:3.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

COMIE

Bit 5: COM interrupt enable.

Allowed values:
0: Disabled: COM interrupt disabled
1: Enabled: COM interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

BIE

Bit 7: Break interrupt enable.

Allowed values:
0: Disabled: Break interrupt disabled
1: Enabled: Break interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

COMDE

Bit 13: COM DMA request enable.

Allowed values:
0: Disabled: COM DMA request disabled
1: Enabled: COM DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC6IF
r/w0c
CC5IF
r/w0c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SBIF
r/w0c
CC[4]OF
r/w0c
CC[3]OF
r/w0c
CC[2]OF
r/w0c
CC[1]OF
r/w0c
B2IF
r/w0c
BIF
r/w0c
TIF
r/w0c
COMIF
r/w0c
CC[4]IF
r/w0c
CC[3]IF
r/w0c
CC[2]IF
r/w0c
CC[1]IF
r/w0c
UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

COMIF

Bit 5: COM interrupt flag.

Allowed values:
0: NoCOM: No COM event occurred
1: COM: COM interrupt pending

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

BIF

Bit 7: Break interrupt flag.

Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register

B2IF

Bit 8: Break 2 interrupt flag.

Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

SBIF

Bit 13: System Break interrupt flag.

Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register

CC5IF

Bit 16: Compare 5 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC6IF

Bit 17: Compare 6 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2G
w
BG
w
TG
w
COMG
w
CC[4]G
w
CC[3]G
w
CC[2]G
w
CC[1]G
w
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

COMG

Bit 5: Capture/Compare control update generation.

Allowed values:
1: Trigger: When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

BG

Bit 7: Break generation.

Allowed values:
1: Trigger: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled

B2G

Bit 8: Break 2 generation.

Allowed values:
1: Trigger: A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw
IC[2]PSC
rw
CC2S
rw
IC[1]F
rw
IC[1]PSC
rw
CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[2]M_3
rw
OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]CE
rw
OC[2]M
rw
OC[2]PE
rw
OC[2]FE
rw
CC[2]S
rw
OC[1]CE
rw
OC[1]M
rw
OC[1]PE
rw
OC[1]FE
rw
CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[2]M_3

Bit 24: Output compare 2 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[4]F
rw
IC[4]PSC
rw
CC4S
rw
IC[3]F
rw
IC[3]PSC
rw
CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC4S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[4]M_3
rw
OC[3]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[4]CE
rw
OC[4]M
rw
OC[4]PE
rw
OC[4]FE
rw
CC[4]S
rw
OC[3]CE
rw
OC[3]M
rw
OC[3]PE
rw
OC[3]FE
rw
CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[3]M_3

Bit 16: Output compare 3 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[4]M_3

Bit 24: Output compare 4 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC[6]P
rw
CC[6]E
rw
CC[5]P
rw
CC[5]E
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]NP
rw
CC[4]P
rw
CC[4]E
rw
CC[3]NP
rw
CC[3]NE
rw
CC[3]P
rw
CC[3]E
rw
CC[2]NP
rw
CC[2]NE
rw
CC[2]P
rw
CC[2]E
rw
CC[1]NP
rw
CC[1]NE
rw
CC[1]P
rw
CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[1]NE

Bit 2: Capture/Compare 1 complementary output enable.

Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CC[2]E

Bit 4: Capture/Compare 2 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[2]NE

Bit 6: Capture/Compare 2 complementary output enable.

Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CC[3]E

Bit 8: Capture/Compare 3 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[3]NE

Bit 10: Capture/Compare 3 complementary output enable.

Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CC[4]E

Bit 12: Capture/Compare 4 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[4]NP

Bit 15: Capture/Compare 4 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CC[5]E

Bit 16: Capture/Compare 5 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[5]P

Bit 17: Capture/Compare 5 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[6]E

Bit 20: Capture/Compare 6 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[6]P

Bit 21: Capture/Compare 6 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

Allowed values: 0x0-0xffff

UIFCPY

Bit 31: UIF copy.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-15: Repetition counter value.

Allowed values: 0x0-0xffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

10/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BK2P
rw
BK2E
rw
BK2F
rw
BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw
AOE
rw
BKP
rw
BKE
rw
OSSR
rw
OSSI
rw
LOCK
rw
DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

Allowed values: 0x0-0xff

LOCK

Bits 8-9: Lock configuration.

Allowed values:
0: Off: No bit is write protected
1: Level1: Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
2: Level2: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
3: Level3: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written

OSSI

Bit 10: Off-state selection for Idle mode.

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are forced to idle level

OSSR

Bit 11: Off-state selection for Run mode.

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are enabled with their inactive level

BKE

Bit 12: Break enable.

Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x enabled

BKP

Bit 13: Break polarity.

Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high

AOE

Bit 14: Automatic output enable.

Allowed values:
0: Manual: MOE can be set only by software
1: Automatic: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)

MOE

Bit 15: Main output enable.

Allowed values:
0: DisabledIdle: OC/OCN are disabled or forced idle depending on OSSI
1: Enabled: OC/OCN are enabled if CCxE/CCxNE are set

BKF

Bits 16-19: Break filter.

BK2F

Bits 20-23: Break 2 filter.

BK2E

Bit 24: Break 2 enable.

Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x enabled

BK2P

Bit 25: Break 2 polarity.

Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-31: DMA register for burst accesses.

CCMR3_Output

capture/compare mode register 3 (output mode)

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[6]M_3
rw
OC[5]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[6]CE
rw
OC[6]M
rw
OC[6]PE
rw
OC[6]FE
rw
OC[5]CE
rw
OC[5]M
rw
OC[5]PE
rw
OC[5]FE
rw
Toggle fields

OC[5]FE

Bit 2: Output compare 5 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[5]PE

Bit 3: Output compare 5 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[5]M

Bits 4-6: Output compare 5 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[5]CE

Bit 7: Output compare 5 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[6]FE

Bit 10: Output compare 6 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[6]PE

Bit 11: Output compare 6 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[6]M

Bits 12-14: Output compare 6 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[6]CE

Bit 15: Output compare 6 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[5]M_3

Bit 16: Output compare 5 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[6]M_3

Bit 24: Output compare 6 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCR5

capture/compare register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GC5C3
rw
GC5C2
rw
GC5C1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

GC5C1

Bit 29: Group Channel 5 and Channel 1.

GC5C2

Bit 30: Group Channel 5 and Channel 2.

GC5C3

Bit 31: Group Channel 5 and Channel 3.

CCR6

capture/compare register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

AF1

TIM1 alternate function option register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw
BKCMP2P
rw
BKCMP1P
rw
BKINP
rw
BKDF1BK0E
rw
BKCMP2E
rw
BKCMP1E
rw
BKINE
rw
Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKDF1BK0E

Bit 8: BRK dfsdm1_break[0] enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarity.

ETRSEL

Bits 14-17: ETR source selection.

AF2

TIM1 Alternate function odfsdm1_breakster 2

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BK2CMP2P
rw
BK2CMP1P
rw
BK2INP
rw
BK2DF1BK1E
rw
BK2CMP2E
rw
BK2CMP1E
rw
BK2INE
rw
Toggle fields

BK2INE

Bit 0: BRK2 BKIN input enable.

BK2CMP1E

Bit 1: BRK2 COMP1 enable.

BK2CMP2E

Bit 2: BRK2 COMP2 enable.

BK2DF1BK1E

Bit 8: BRK2 dfsdm1_break[1] enable.

BK2INP

Bit 9: BRK2 BKIN2 input polarity.

BK2CMP1P

Bit 10: BRK2 COMP1 input polarit.

BK2CMP2P

Bit 11: BRK2 COMP2 input polarity.

TISEL

TIM1 timer input selection register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TI4SEL
rw
TI3SEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI2SEL
rw
TI1SEL
rw
Toggle fields

TI1SEL

Bits 0-3: selects TI1[0] to TI1[15] input.

TI2SEL

Bits 8-11: selects TI2[0] to TI2[15] input.

TI3SEL

Bits 16-19: selects TI3[0] to TI3[15] input.

TI4SEL

Bits 24-27: selects TI4[0] to TI4[15] input.

TIM12

0x40001800: General purpose timers

45/59 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR[1]
0x38 CCR[2]
0x68 TISEL
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

6/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw
MMS
rw
Toggle fields

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS2
rw
SMS_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSM
rw
TS
rw
SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

SMS_3

Bit 16: Slave mode selection - bit 3.

TS2

Bits 20-21: Trigger selection.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIE
rw
CC[2]IE
rw
CC[1]IE
rw
UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[2]OF
r/w0c
CC[1]OF
r/w0c
TIF
r/w0c
CC[2]IF
r/w0c
CC[1]IF
r/w0c
UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w
CC[2]G
w
CC[1]G
w
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw
IC[2]PSC
rw
CC2S
rw
IC[1]F
rw
IC[1]PSC
rw
CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

10/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[2]M_3
rw
OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]CE
rw
OC[2]M
rw
OC[2]PE
rw
OC[2]FE
rw
CC[2]S
rw
OC[1]CE
rw
OC[1]M
rw
OC[1]PE
rw
OC[1]FE
rw
CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / Reserved
7: PwmMode2: Inversely to PwmMode1 / Reserved

OC[1]CE

Bit 7: Output compare 1 clear enable.

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / Reserved
7: PwmMode2: Inversely to PwmMode1 / Reserved

OC[2]CE

Bit 15: Output compare 2 clear enable.

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[2]M_3

Bit 24: Output compare 2 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

4/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[2]NP
rw
CC[2]P
rw
CC[2]E
rw
CC[1]NP
rw
CC[1]P
rw
CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: Counter value.

Allowed values: 0x0-0xffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

TISEL

TIM timer input selection register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI2SEL
rw
TI1SEL
rw
Toggle fields

TI1SEL

Bits 0-3: TI1[0] to TI1[15] input selection.

TI2SEL

Bits 8-11: TI2[0] to TI2[15] input selection.

TIM13

0x40001c00: General purpose timers

26/31 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR[1]
0x68 TISEL
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

6/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]IE
rw
UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]OF
r/w0c
CC[1]IF
r/w0c
UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]G
w
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[1]F
rw
IC[1]PSC
rw
CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[1]CE
rw
OC[1]M
rw
OC[1]PE
rw
OC[1]FE
rw
CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

2/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]NP
rw
CC[1]P
rw
CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: Counter value.

Allowed values: 0x0-0xffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

TISEL

TIM timer input selection register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1SEL
rw
Toggle fields

TI1SEL

Bits 0-3: TI1[0] to TI1[15] input selection.

TIM14

0x40002000: General purpose timers

26/31 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR[1]
0x68 TISEL
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

6/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]IE
rw
UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]OF
r/w0c
CC[1]IF
r/w0c
UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]G
w
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[1]F
rw
IC[1]PSC
rw
CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[1]CE
rw
OC[1]M
rw
OC[1]PE
rw
OC[1]FE
rw
CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

2/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]NP
rw
CC[1]P
rw
CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: Counter value.

Allowed values: 0x0-0xffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

TISEL

TIM timer input selection register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1SEL
rw
Toggle fields

TI1SEL

Bits 0-3: TI1[0] to TI1[15] input selection.

TIM15

0x40014000: General purpose timers

75/96 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR[1]
0x38 CCR[2]
0x44 BDTR
0x48 DCR
0x4c DMAR
0x60 AF1
0x68 TISEL
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

6/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

6/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS[2]
rw
OIS[1]N
rw
OIS[1]
rw
TI1S
rw
MMS
rw
CCDS
rw
CCUS
rw
CCPC
rw
Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

Allowed values:
0: NotPreloaded: CCxE, CCxNE and OCxM bits are not preloaded
1: Preloaded: CCxE, CCxNE and OCxM bits are preloaded

CCUS

Bit 2: Capture/compare control update selection.

Allowed values:
0: Sw: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
1: SwOrEdge: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

OIS[1]

Bit 8: Output Idle state (OC1 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[1]N

Bit 9: Output Idle state (OC1N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[2]

Bit 10: Output Idle state (OC2 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS2
rw
SMS_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSM
rw
TS
rw
SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

SMS_3

Bit 16: Slave mode selection bit 3.

TS2

Bits 20-21: Trigger selection - bit 4:3.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw
COMDE
rw
CC[2]DE
rw
CC[1]DE
rw
UDE
rw
BIE
rw
TIE
rw
COMIE
rw
CC[2]IE
rw
CC[1]IE
rw
UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

COMIE

Bit 5: COM interrupt enable.

Allowed values:
0: Disabled: COM interrupt disabled
1: Enabled: COM interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

BIE

Bit 7: Break interrupt enable.

Allowed values:
0: Disabled: Break interrupt disabled
1: Enabled: Break interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

COMDE

Bit 13: COM DMA request enable.

Allowed values:
0: Disabled: COM DMA request disabled
1: Enabled: COM DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[2]OF
r/w0c
CC[1]OF
r/w0c
BIF
r/w0c
TIF
r/w0c
COMIF
r/w0c
CC[2]IF
r/w0c
CC[1]IF
r/w0c
UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

COMIF

Bit 5: COM interrupt flag.

Allowed values:
0: NoCOM: No COM event occurred
1: COM: COM interrupt pending

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

BIF

Bit 7: Break interrupt flag.

Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w
TG
w
COMG
w
CC[2]G
w
CC[1]G
w
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

COMG

Bit 5: Capture/Compare control update generation.

Allowed values:
1: Trigger: When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

BG

Bit 7: Break generation.

Allowed values:
1: Trigger: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw
IC[2]PSC
rw
CC2S
rw
IC[1]F
rw
IC[1]PSC
rw
CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[2]M_3
rw
OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]M
rw
OC[2]PE
rw
OC[2]FE
rw
CC[2]S
rw
OC[1]M
rw
OC[1]PE
rw
OC[1]FE
rw
CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / Reserved
7: PwmMode2: Inversely to PwmMode1 / Reserved

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / Reserved
7: PwmMode2: Inversely to PwmMode1 / Reserved

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[2]M_3

Bit 24: Output compare 2 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[2]NP
rw
CC[2]P
rw
CC[2]E
rw
CC[1]NP
rw
CC[1]NE
rw
CC[1]P
rw
CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[1]NE

Bit 2: Capture/Compare 1 complementary output enable.

Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CC[2]E

Bit 4: Capture/Compare 2 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

Allowed values: 0x0-0xffff

UIFCPY

Bit 31: UIF copy.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition counter value.

Allowed values: 0x0-0xff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

8/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw
AOE
rw
BKP
rw
BKE
rw
OSSR
rw
OSSI
rw
LOCK
rw
DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

Allowed values: 0x0-0xff

LOCK

Bits 8-9: Lock configuration.

Allowed values:
0: Off: No bit is write protected
1: Level1: Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
2: Level2: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
3: Level3: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written

OSSI

Bit 10: Off-state selection for Idle mode.

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are forced to idle level

OSSR

Bit 11: Off-state selection for Run mode.

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are enabled with their inactive level

BKE

Bit 12: Break enable.

Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x enabled

BKP

Bit 13: Break polarity.

Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high

AOE

Bit 14: Automatic output enable.

Allowed values:
0: Manual: MOE can be set only by software
1: Automatic: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)

MOE

Bit 15: Main output enable.

Allowed values:
0: DisabledIdle: OC/OCN are disabled or forced idle depending on OSSI
1: Enabled: OC/OCN are enabled if CCxE/CCxNE are set

BKF

Bits 16-19: Break filter.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

AF1

TIM15 alternate fdfsdm1_breakon register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKCMP2P
rw
BKCMP1P
rw
BKINP
rw
BKDF1BK0E
rw
BKCMP2E
rw
BKCMP1E
rw
BKINE
rw
Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKDF1BK0E

Bit 8: BRK dfsdm1_break[0] enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarity.

TISEL

TIM15 input selection register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI2SEL
rw
TI1SEL
rw
Toggle fields

TI1SEL

Bits 0-3: selects TI1[0] to TI1[15] input.

TI2SEL

Bits 8-11: selects TI2[0] to TI2[15] input.

TIM16

0x40014400: General-purpose-timers

51/66 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR[1]
0x44 BDTR
0x48 DCR
0x4c DMAR
0x60 TIM16_AF1
0x68 TIM16_TISEL
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

6/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS[1]N
rw
OIS[1]
rw
CCDS
rw
CCUS
rw
CCPC
rw
Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

Allowed values:
0: NotPreloaded: CCxE, CCxNE and OCxM bits are not preloaded
1: Preloaded: CCxE, CCxNE and OCxM bits are preloaded

CCUS

Bit 2: Capture/compare control update selection.

Allowed values:
0: Sw: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
1: SwOrEdge: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

OIS[1]

Bit 8: Output Idle state (OC1 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[1]N

Bit 9: Output Idle state (OC1N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

6/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMDE
rw
CC[1]DE
rw
UDE
rw
BIE
rw
COMIE
rw
CC[1]IE
rw
UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

COMIE

Bit 5: COM interrupt enable.

Allowed values:
0: Disabled: COM interrupt disabled
1: Enabled: COM interrupt enabled

BIE

Bit 7: Break interrupt enable.

Allowed values:
0: Disabled: Break interrupt disabled
1: Enabled: Break interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

COMDE

Bit 13: COM DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]OF
r/w0c
BIF
r/w0c
COMIF
r/w0c
CC[1]IF
r/w0c
UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

COMIF

Bit 5: COM interrupt flag.

Allowed values:
0: NoCOM: No COM event occurred
1: COM: COM interrupt pending

BIF

Bit 7: Break interrupt flag.

Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w
COMG
w
CC[1]G
w
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

COMG

Bit 5: Capture/Compare control update generation.

Allowed values:
1: Trigger: When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated

BG

Bit 7: Break generation.

Allowed values:
1: Trigger: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[1]F
rw
IC[1]PSC
rw
CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[1]M
rw
OC[1]PE
rw
OC[1]FE
rw
CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]NP
rw
CC[1]NE
rw
CC[1]P
rw
CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[1]NE

Bit 2: Capture/Compare 1 complementary output enable.

Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

Allowed values: 0x0-0xffff

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition counter value.

Allowed values: 0x0-0xff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

8/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw
AOE
rw
BKP
rw
BKE
rw
OSSR
rw
OSSI
rw
LOCK
rw
DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

Allowed values: 0x0-0xff

LOCK

Bits 8-9: Lock configuration.

Allowed values:
0: Off: No bit is write protected
1: Level1: Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
2: Level2: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
3: Level3: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written

OSSI

Bit 10: Off-state selection for Idle mode.

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are forced to idle level

OSSR

Bit 11: Off-state selection for Run mode.

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are enabled with their inactive level

BKE

Bit 12: Break enable.

Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x enabled

BKP

Bit 13: Break polarity.

Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high

AOE

Bit 14: Automatic output enable.

Allowed values:
0: Manual: MOE can be set only by software
1: Automatic: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)

MOE

Bit 15: Main output enable.

Allowed values:
0: DisabledIdle: OC/OCN are disabled or forced idle depending on OSSI
1: Enabled: OC/OCN are enabled if CCxE/CCxNE are set

BKF

Bits 16-19: Break filter.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

TIM16_AF1

TIM16 alternate function register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKCMP2P
rw
BKCMP1P
rw
BKINP
rw
BKDFBK1E
rw
BKCMP2E
rw
BKCMP1E
rw
BKINE
rw
Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKDFBK1E

Bit 8: BRK dfsdm1_break[1] enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarity.

TIM16_TISEL

TIM16 input selection register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1SEL
rw
Toggle fields

TI1SEL

Bits 0-3: selects TI1[0] to TI1[15] input.

TIM17

0x40014800: General-purpose-timers

51/66 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR[1]
0x44 BDTR
0x48 DCR
0x4c DMAR
0x60 TIM17_AF1
0x68 TIM17_TISEL
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

6/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS[1]N
rw
OIS[1]
rw
CCDS
rw
CCUS
rw
CCPC
rw
Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

Allowed values:
0: NotPreloaded: CCxE, CCxNE and OCxM bits are not preloaded
1: Preloaded: CCxE, CCxNE and OCxM bits are preloaded

CCUS

Bit 2: Capture/compare control update selection.

Allowed values:
0: Sw: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
1: SwOrEdge: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

OIS[1]

Bit 8: Output Idle state (OC1 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[1]N

Bit 9: Output Idle state (OC1N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

6/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMDE
rw
CC[1]DE
rw
UDE
rw
BIE
rw
COMIE
rw
CC[1]IE
rw
UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

COMIE

Bit 5: COM interrupt enable.

Allowed values:
0: Disabled: COM interrupt disabled
1: Enabled: COM interrupt enabled

BIE

Bit 7: Break interrupt enable.

Allowed values:
0: Disabled: Break interrupt disabled
1: Enabled: Break interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

COMDE

Bit 13: COM DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]OF
r/w0c
BIF
r/w0c
COMIF
r/w0c
CC[1]IF
r/w0c
UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

COMIF

Bit 5: COM interrupt flag.

Allowed values:
0: NoCOM: No COM event occurred
1: COM: COM interrupt pending

BIF

Bit 7: Break interrupt flag.

Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w
COMG
w
CC[1]G
w
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

COMG

Bit 5: Capture/Compare control update generation.

Allowed values:
1: Trigger: When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated

BG

Bit 7: Break generation.

Allowed values:
1: Trigger: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[1]F
rw
IC[1]PSC
rw
CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[1]M
rw
OC[1]PE
rw
OC[1]FE
rw
CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]NP
rw
CC[1]NE
rw
CC[1]P
rw
CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[1]NE

Bit 2: Capture/Compare 1 complementary output enable.

Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

Allowed values: 0x0-0xffff

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition counter value.

Allowed values: 0x0-0xff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

8/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw
AOE
rw
BKP
rw
BKE
rw
OSSR
rw
OSSI
rw
LOCK
rw
DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

Allowed values: 0x0-0xff

LOCK

Bits 8-9: Lock configuration.

Allowed values:
0: Off: No bit is write protected
1: Level1: Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
2: Level2: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
3: Level3: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written

OSSI

Bit 10: Off-state selection for Idle mode.

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are forced to idle level

OSSR

Bit 11: Off-state selection for Run mode.

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are enabled with their inactive level

BKE

Bit 12: Break enable.

Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x enabled

BKP

Bit 13: Break polarity.

Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high

AOE

Bit 14: Automatic output enable.

Allowed values:
0: Manual: MOE can be set only by software
1: Automatic: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)

MOE

Bit 15: Main output enable.

Allowed values:
0: DisabledIdle: OC/OCN are disabled or forced idle depending on OSSI
1: Enabled: OC/OCN are enabled if CCxE/CCxNE are set

BKF

Bits 16-19: Break filter.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

TIM17_AF1

TIM17 alternate function register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKCMP2P
rw
BKCMP1P
rw
BKINP
rw
BKDFBK1E
rw
BKCMP2E
rw
BKCMP1E
rw
BKINE
rw
Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKDFBK1E

Bit 8: BRK dfsdm1_break[1] enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarity.

TIM17_TISEL

TIM17 input selection register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1SEL
rw
Toggle fields

TI1SEL

Bits 0-3: selects TI1[0] to TI1[15] input.

TIM2

0x40000000: General purpose timers

99/112 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR[1]
0x38 CCR[2]
0x3c CCR[3]
0x40 CCR[4]
0x48 DCR
0x4c DMAR
0x60 AF1
0x68 TISEL
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
CMS
rw
DIR
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw
MMS
rw
CCDS
rw
Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

7/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS2
rw
SMS_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw
ECE
rw
ETPS
rw
ETF
rw
MSM
rw
TS
rw
SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

SMS_3

Bit 16: Slave mode selection - bit 3.

TS2

Bits 20-21: Trigger selection.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw
CC[4]DE
rw
CC[3]DE
rw
CC[2]DE
rw
CC[1]DE
rw
UDE
rw
TIE
rw
CC[4]IE
rw
CC[3]IE
rw
CC[2]IE
rw
CC[1]IE
rw
UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]OF
r/w0c
CC[3]OF
r/w0c
CC[2]OF
r/w0c
CC[1]OF
r/w0c
TIF
r/w0c
CC[4]IF
r/w0c
CC[3]IF
r/w0c
CC[2]IF
r/w0c
CC[1]IF
r/w0c
UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w
CC[4]G
w
CC[3]G
w
CC[2]G
w
CC[1]G
w
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw
IC[2]PSC
rw
CC2S
rw
IC[1]F
rw
IC[1]PSC
rw
CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[2]M_3
rw
OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]CE
rw
OC[2]M
rw
OC[2]PE
rw
OC[2]FE
rw
CC[2]S
rw
OC[1]CE
rw
OC[1]M
rw
OC[1]PE
rw
OC[1]FE
rw
CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[2]M_3

Bit 24: Output compare 2 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[4]F
rw
IC[4]PSC
rw
CC4S
rw
IC[3]F
rw
IC[3]PSC
rw
CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC4S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[4]M_3
rw
OC[3]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[4]CE
rw
OC[4]M
rw
OC[4]PE
rw
OC[4]FE
rw
CC[4]S
rw
OC[3]CE
rw
OC[3]M
rw
OC[3]PE
rw
OC[3]FE
rw
CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[3]M_3

Bit 16: Output compare 3 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[4]M_3

Bit 24: Output compare 4 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/12 fields covered.

Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CC[3]E

Bit 8: Capture/Compare 3 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

CC[4]E

Bit 12: Capture/Compare 4 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[4]NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-31: low counter value.

Allowed values: 0x0-0xffffffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-31: Auto-reload value.

Allowed values: 0x0-0xffffffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

AF1

TIM alternate function option register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw
Toggle fields

ETRSEL

Bits 14-17: ETR source selection.

TISEL

TIM timer input selection register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TI4SEL
rw
TI3SEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI2SEL
rw
TI1SEL
rw
Toggle fields

TI1SEL

Bits 0-3: TI1[0] to TI1[15] input selection.

TI2SEL

Bits 8-11: TI2[0] to TI2[15] input selection.

TI3SEL

Bits 16-19: TI3[0] to TI3[15] input selection.

TI4SEL

Bits 24-27: TI4[0] to TI4[15] input selection.

TIM3

0x40000400: General purpose timers

99/112 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR[1]
0x38 CCR[2]
0x3c CCR[3]
0x40 CCR[4]
0x48 DCR
0x4c DMAR
0x60 AF1
0x68 TISEL
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
CMS
rw
DIR
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw
MMS
rw
CCDS
rw
Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

7/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS2
rw
SMS_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw
ECE
rw
ETPS
rw
ETF
rw
MSM
rw
TS
rw
SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

SMS_3

Bit 16: Slave mode selection - bit 3.

TS2

Bits 20-21: Trigger selection.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw
CC[4]DE
rw
CC[3]DE
rw
CC[2]DE
rw
CC[1]DE
rw
UDE
rw
TIE
rw
CC[4]IE
rw
CC[3]IE
rw
CC[2]IE
rw
CC[1]IE
rw
UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]OF
r/w0c
CC[3]OF
r/w0c
CC[2]OF
r/w0c
CC[1]OF
r/w0c
TIF
r/w0c
CC[4]IF
r/w0c
CC[3]IF
r/w0c
CC[2]IF
r/w0c
CC[1]IF
r/w0c
UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w
CC[4]G
w
CC[3]G
w
CC[2]G
w
CC[1]G
w
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw
IC[2]PSC
rw
CC2S
rw
IC[1]F
rw
IC[1]PSC
rw
CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[2]M_3
rw
OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]CE
rw
OC[2]M
rw
OC[2]PE
rw
OC[2]FE
rw
CC[2]S
rw
OC[1]CE
rw
OC[1]M
rw
OC[1]PE
rw
OC[1]FE
rw
CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[2]M_3

Bit 24: Output compare 2 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[4]F
rw
IC[4]PSC
rw
CC4S
rw
IC[3]F
rw
IC[3]PSC
rw
CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC4S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[4]M_3
rw
OC[3]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[4]CE
rw
OC[4]M
rw
OC[4]PE
rw
OC[4]FE
rw
CC[4]S
rw
OC[3]CE
rw
OC[3]M
rw
OC[3]PE
rw
OC[3]FE
rw
CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[3]M_3

Bit 16: Output compare 3 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[4]M_3

Bit 24: Output compare 4 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/12 fields covered.

Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CC[3]E

Bit 8: Capture/Compare 3 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

CC[4]E

Bit 12: Capture/Compare 4 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[4]NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: Counter value.

Allowed values: 0x0-0xffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

AF1

TIM alternate function option register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw
Toggle fields

ETRSEL

Bits 14-17: ETR source selection.

TISEL

TIM timer input selection register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TI4SEL
rw
TI3SEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI2SEL
rw
TI1SEL
rw
Toggle fields

TI1SEL

Bits 0-3: TI1[0] to TI1[15] input selection.

TI2SEL

Bits 8-11: TI2[0] to TI2[15] input selection.

TI3SEL

Bits 16-19: TI3[0] to TI3[15] input selection.

TI4SEL

Bits 24-27: TI4[0] to TI4[15] input selection.

TIM4

0x40000800: General purpose timers

99/112 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR[1]
0x38 CCR[2]
0x3c CCR[3]
0x40 CCR[4]
0x48 DCR
0x4c DMAR
0x60 AF1
0x68 TISEL
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
CMS
rw
DIR
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw
MMS
rw
CCDS
rw
Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

7/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS2
rw
SMS_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw
ECE
rw
ETPS
rw
ETF
rw
MSM
rw
TS
rw
SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

SMS_3

Bit 16: Slave mode selection - bit 3.

TS2

Bits 20-21: Trigger selection.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw
CC[4]DE
rw
CC[3]DE
rw
CC[2]DE
rw
CC[1]DE
rw
UDE
rw
TIE
rw
CC[4]IE
rw
CC[3]IE
rw
CC[2]IE
rw
CC[1]IE
rw
UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]OF
r/w0c
CC[3]OF
r/w0c
CC[2]OF
r/w0c
CC[1]OF
r/w0c
TIF
r/w0c
CC[4]IF
r/w0c
CC[3]IF
r/w0c
CC[2]IF
r/w0c
CC[1]IF
r/w0c
UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w
CC[4]G
w
CC[3]G
w
CC[2]G
w
CC[1]G
w
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw
IC[2]PSC
rw
CC2S
rw
IC[1]F
rw
IC[1]PSC
rw
CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[2]M_3
rw
OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]CE
rw
OC[2]M
rw
OC[2]PE
rw
OC[2]FE
rw
CC[2]S
rw
OC[1]CE
rw
OC[1]M
rw
OC[1]PE
rw
OC[1]FE
rw
CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[2]M_3

Bit 24: Output compare 2 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[4]F
rw
IC[4]PSC
rw
CC4S
rw
IC[3]F
rw
IC[3]PSC
rw
CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC4S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[4]M_3
rw
OC[3]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[4]CE
rw
OC[4]M
rw
OC[4]PE
rw
OC[4]FE
rw
CC[4]S
rw
OC[3]CE
rw
OC[3]M
rw
OC[3]PE
rw
OC[3]FE
rw
CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[3]M_3

Bit 16: Output compare 3 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[4]M_3

Bit 24: Output compare 4 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/12 fields covered.

Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CC[3]E

Bit 8: Capture/Compare 3 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

CC[4]E

Bit 12: Capture/Compare 4 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[4]NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: Counter value.

Allowed values: 0x0-0xffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

AF1

TIM alternate function option register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw
Toggle fields

ETRSEL

Bits 14-17: ETR source selection.

TISEL

TIM timer input selection register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TI4SEL
rw
TI3SEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI2SEL
rw
TI1SEL
rw
Toggle fields

TI1SEL

Bits 0-3: TI1[0] to TI1[15] input selection.

TI2SEL

Bits 8-11: TI2[0] to TI2[15] input selection.

TI3SEL

Bits 16-19: TI3[0] to TI3[15] input selection.

TI4SEL

Bits 24-27: TI4[0] to TI4[15] input selection.

TIM5

0x40000c00: General purpose timers

99/112 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR[1]
0x38 CCR[2]
0x3c CCR[3]
0x40 CCR[4]
0x48 DCR
0x4c DMAR
0x60 AF1
0x68 TISEL
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
CMS
rw
DIR
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw
MMS
rw
CCDS
rw
Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

7/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS2
rw
SMS_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw
ECE
rw
ETPS
rw
ETF
rw
MSM
rw
TS
rw
SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

SMS_3

Bit 16: Slave mode selection - bit 3.

TS2

Bits 20-21: Trigger selection.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw
CC[4]DE
rw
CC[3]DE
rw
CC[2]DE
rw
CC[1]DE
rw
UDE
rw
TIE
rw
CC[4]IE
rw
CC[3]IE
rw
CC[2]IE
rw
CC[1]IE
rw
UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]OF
r/w0c
CC[3]OF
r/w0c
CC[2]OF
r/w0c
CC[1]OF
r/w0c
TIF
r/w0c
CC[4]IF
r/w0c
CC[3]IF
r/w0c
CC[2]IF
r/w0c
CC[1]IF
r/w0c
UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w
CC[4]G
w
CC[3]G
w
CC[2]G
w
CC[1]G
w
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw
IC[2]PSC
rw
CC2S
rw
IC[1]F
rw
IC[1]PSC
rw
CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[2]M_3
rw
OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]CE
rw
OC[2]M
rw
OC[2]PE
rw
OC[2]FE
rw
CC[2]S
rw
OC[1]CE
rw
OC[1]M
rw
OC[1]PE
rw
OC[1]FE
rw
CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[2]M_3

Bit 24: Output compare 2 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[4]F
rw
IC[4]PSC
rw
CC4S
rw
IC[3]F
rw
IC[3]PSC
rw
CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC4S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[4]M_3
rw
OC[3]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[4]CE
rw
OC[4]M
rw
OC[4]PE
rw
OC[4]FE
rw
CC[4]S
rw
OC[3]CE
rw
OC[3]M
rw
OC[3]PE
rw
OC[3]FE
rw
CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[3]M_3

Bit 16: Output compare 3 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[4]M_3

Bit 24: Output compare 4 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/12 fields covered.

Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CC[3]E

Bit 8: Capture/Compare 3 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

CC[4]E

Bit 12: Capture/Compare 4 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[4]NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-31: low counter value.

Allowed values: 0x0-0xffffffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-31: Auto-reload value.

Allowed values: 0x0-0xffffffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

AF1

TIM alternate function option register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw
Toggle fields

ETRSEL

Bits 14-17: ETR source selection.

TISEL

TIM timer input selection register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TI4SEL
rw
TI3SEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI2SEL
rw
TI1SEL
rw
Toggle fields

TI1SEL

Bits 0-3: TI1[0] to TI1[15] input selection.

TI2SEL

Bits 8-11: TI2[0] to TI2[15] input selection.

TI3SEL

Bits 16-19: TI3[0] to TI3[15] input selection.

TI4SEL

Bits 24-27: TI4[0] to TI4[15] input selection.

TIM6

0x40001000: Basic timers

13/15 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x24 CNT
0x28 PSC
0x2c ARR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

5/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
ARPE
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle fields

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: Use UG bit from TIMx_EGR register
1: Enable: Use CNT bit from TIMx_CEN register
2: Update: Use the update event

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDE
rw
UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: Low counter value.

Allowed values: 0x0-0xffff

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Low Auto-reload value.

Allowed values: 0x0-0xffff

TIM7

0x40001400: Basic timers

13/15 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x24 CNT
0x28 PSC
0x2c ARR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

5/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
ARPE
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle fields

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: Use UG bit from TIMx_EGR register
1: Enable: Use CNT bit from TIMx_CEN register
2: Update: Use the update event

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDE
rw
UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: Low counter value.

Allowed values: 0x0-0xffff

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Low Auto-reload value.

Allowed values: 0x0-0xffff

TIM8

0x40010400: Advanced-timers

157/186 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR[1]
0x38 CCR[2]
0x3c CCR[3]
0x40 CCR[4]
0x44 BDTR
0x48 DCR
0x4c DMAR
0x54 CCMR3_Output
0x58 CCR5
0x5c CCR6
0x60 AF1
0x64 AF2
0x68 TISEL
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
CMS
rw
DIR
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

14/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMS2
rw
OIS[6]
rw
OIS[5]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS[4]
rw
OIS[3]N
rw
OIS[3]
rw
OIS[2]N
rw
OIS[2]
rw
OIS[1]N
rw
OIS[1]
rw
TI1S
rw
MMS
rw
CCDS
rw
CCUS
rw
CCPC
rw
Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

Allowed values:
0: NotPreloaded: CCxE, CCxNE and OCxM bits are not preloaded
1: Preloaded: CCxE, CCxNE and OCxM bits are preloaded

CCUS

Bit 2: Capture/compare control update selection.

Allowed values:
0: Sw: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
1: SwOrEdge: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

OIS[1]

Bit 8: Output Idle state (OC1 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[1]N

Bit 9: Output Idle state (OC1N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[2]

Bit 10: Output Idle state (OC2 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[2]N

Bit 11: Output Idle state (OC2N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[3]

Bit 12: Output Idle state (OC3 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[3]N

Bit 13: Output Idle state (OC3N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[4]

Bit 14: Output Idle state (OC4 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[5]

Bit 16: Output Idle state (OC5 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[6]

Bit 18: Output Idle state (OC6 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

MMS2

Bits 20-23: Master mode selection 2.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

7/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS2
rw
SMS_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw
ECE
rw
ETPS
rw
ETF
rw
MSM
rw
TS
rw
SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

SMS_3

Bit 16: Slave mode selection - bit 3.

TS2

Bits 20-21: Trigger selection - bit 4:3.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

COMIE

Bit 5: COM interrupt enable.

Allowed values:
0: Disabled: COM interrupt disabled
1: Enabled: COM interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

BIE

Bit 7: Break interrupt enable.

Allowed values:
0: Disabled: Break interrupt disabled
1: Enabled: Break interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

COMDE

Bit 13: COM DMA request enable.

Allowed values:
0: Disabled: COM DMA request disabled
1: Enabled: COM DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC6IF
r/w0c
CC5IF
r/w0c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SBIF
r/w0c
CC[4]OF
r/w0c
CC[3]OF
r/w0c
CC[2]OF
r/w0c
CC[1]OF
r/w0c
B2IF
r/w0c
BIF
r/w0c
TIF
r/w0c
COMIF
r/w0c
CC[4]IF
r/w0c
CC[3]IF
r/w0c
CC[2]IF
r/w0c
CC[1]IF
r/w0c
UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

COMIF

Bit 5: COM interrupt flag.

Allowed values:
0: NoCOM: No COM event occurred
1: COM: COM interrupt pending

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

BIF

Bit 7: Break interrupt flag.

Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register

B2IF

Bit 8: Break 2 interrupt flag.

Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

SBIF

Bit 13: System Break interrupt flag.

Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register

CC5IF

Bit 16: Compare 5 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC6IF

Bit 17: Compare 6 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2G
w
BG
w
TG
w
COMG
w
CC[4]G
w
CC[3]G
w
CC[2]G
w
CC[1]G
w
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

COMG

Bit 5: Capture/Compare control update generation.

Allowed values:
1: Trigger: When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

BG

Bit 7: Break generation.

Allowed values:
1: Trigger: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled

B2G

Bit 8: Break 2 generation.

Allowed values:
1: Trigger: A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw
IC[2]PSC
rw
CC2S
rw
IC[1]F
rw
IC[1]PSC
rw
CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[2]M_3
rw
OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]CE
rw
OC[2]M
rw
OC[2]PE
rw
OC[2]FE
rw
CC[2]S
rw
OC[1]CE
rw
OC[1]M
rw
OC[1]PE
rw
OC[1]FE
rw
CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[2]M_3

Bit 24: Output compare 2 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[4]F
rw
IC[4]PSC
rw
CC4S
rw
IC[3]F
rw
IC[3]PSC
rw
CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC4S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[4]M_3
rw
OC[3]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[4]CE
rw
OC[4]M
rw
OC[4]PE
rw
OC[4]FE
rw
CC[4]S
rw
OC[3]CE
rw
OC[3]M
rw
OC[3]PE
rw
OC[3]FE
rw
CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[3]M_3

Bit 16: Output compare 3 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[4]M_3

Bit 24: Output compare 4 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC[6]P
rw
CC[6]E
rw
CC[5]P
rw
CC[5]E
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]NP
rw
CC[4]P
rw
CC[4]E
rw
CC[3]NP
rw
CC[3]NE
rw
CC[3]P
rw
CC[3]E
rw
CC[2]NP
rw
CC[2]NE
rw
CC[2]P
rw
CC[2]E
rw
CC[1]NP
rw
CC[1]NE
rw
CC[1]P
rw
CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[1]NE

Bit 2: Capture/Compare 1 complementary output enable.

Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CC[2]E

Bit 4: Capture/Compare 2 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[2]NE

Bit 6: Capture/Compare 2 complementary output enable.

Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CC[3]E

Bit 8: Capture/Compare 3 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[3]NE

Bit 10: Capture/Compare 3 complementary output enable.

Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CC[4]E

Bit 12: Capture/Compare 4 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[4]NP

Bit 15: Capture/Compare 4 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CC[5]E

Bit 16: Capture/Compare 5 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[5]P

Bit 17: Capture/Compare 5 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[6]E

Bit 20: Capture/Compare 6 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[6]P

Bit 21: Capture/Compare 6 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

Allowed values: 0x0-0xffff

UIFCPY

Bit 31: UIF copy.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-15: Repetition counter value.

Allowed values: 0x0-0xffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

10/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BK2P
rw
BK2E
rw
BK2F
rw
BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw
AOE
rw
BKP
rw
BKE
rw
OSSR
rw
OSSI
rw
LOCK
rw
DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

Allowed values: 0x0-0xff

LOCK

Bits 8-9: Lock configuration.

Allowed values:
0: Off: No bit is write protected
1: Level1: Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
2: Level2: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
3: Level3: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written

OSSI

Bit 10: Off-state selection for Idle mode.

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are forced to idle level

OSSR

Bit 11: Off-state selection for Run mode.

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are enabled with their inactive level

BKE

Bit 12: Break enable.

Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x enabled

BKP

Bit 13: Break polarity.

Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high

AOE

Bit 14: Automatic output enable.

Allowed values:
0: Manual: MOE can be set only by software
1: Automatic: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)

MOE

Bit 15: Main output enable.

Allowed values:
0: DisabledIdle: OC/OCN are disabled or forced idle depending on OSSI
1: Enabled: OC/OCN are enabled if CCxE/CCxNE are set

BKF

Bits 16-19: Break filter.

BK2F

Bits 20-23: Break 2 filter.

BK2E

Bit 24: Break 2 enable.

Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x enabled

BK2P

Bit 25: Break 2 polarity.

Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-31: DMA register for burst accesses.

CCMR3_Output

capture/compare mode register 3 (output mode)

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[6]M_3
rw
OC[5]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[6]CE
rw
OC[6]M
rw
OC[6]PE
rw
OC[6]FE
rw
OC[5]CE
rw
OC[5]M
rw
OC[5]PE
rw
OC[5]FE
rw
Toggle fields

OC[5]FE

Bit 2: Output compare 5 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[5]PE

Bit 3: Output compare 5 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[5]M

Bits 4-6: Output compare 5 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[5]CE

Bit 7: Output compare 5 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[6]FE

Bit 10: Output compare 6 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[6]PE

Bit 11: Output compare 6 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[6]M

Bits 12-14: Output compare 6 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[6]CE

Bit 15: Output compare 6 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[5]M_3

Bit 16: Output compare 5 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[6]M_3

Bit 24: Output compare 6 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCR5

capture/compare register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GC5C3
rw
GC5C2
rw
GC5C1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

GC5C1

Bit 29: Group Channel 5 and Channel 1.

GC5C2

Bit 30: Group Channel 5 and Channel 2.

GC5C3

Bit 31: Group Channel 5 and Channel 3.

CCR6

capture/compare register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

AF1

TIM1 alternate function option register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw
BKCMP2P
rw
BKCMP1P
rw
BKINP
rw
BKDF1BK0E
rw
BKCMP2E
rw
BKCMP1E
rw
BKINE
rw
Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKDF1BK0E

Bit 8: BRK dfsdm1_break[0] enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarity.

ETRSEL

Bits 14-17: ETR source selection.

AF2

TIM1 Alternate function odfsdm1_breakster 2

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BK2CMP2P
rw
BK2CMP1P
rw
BK2INP
rw
BK2DF1BK1E
rw
BK2CMP2E
rw
BK2CMP1E
rw
BK2INE
rw
Toggle fields

BK2INE

Bit 0: BRK2 BKIN input enable.

BK2CMP1E

Bit 1: BRK2 COMP1 enable.

BK2CMP2E

Bit 2: BRK2 COMP2 enable.

BK2DF1BK1E

Bit 8: BRK2 dfsdm1_break[1] enable.

BK2INP

Bit 9: BRK2 BKIN2 input polarity.

BK2CMP1P

Bit 10: BRK2 COMP1 input polarit.

BK2CMP2P

Bit 11: BRK2 COMP2 input polarity.

TISEL

TIM1 timer input selection register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TI4SEL
rw
TI3SEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI2SEL
rw
TI1SEL
rw
Toggle fields

TI1SEL

Bits 0-3: selects TI1[0] to TI1[15] input.

TI2SEL

Bits 8-11: selects TI2[0] to TI2[15] input.

TI3SEL

Bits 16-19: selects TI3[0] to TI3[15] input.

TI4SEL

Bits 24-27: selects TI4[0] to TI4[15] input.

UART4

0x40004c00: Universal synchronous asynchronous receiver transmitter

124/124 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw
TXFEIE
rw
FIFOEN
rw
M1
rw
EOBIE
rw
RTOIE
rw
DEAT
rw
DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw
CMIE
rw
MME
rw
M0
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
UESM
rw
UE
rw
Toggle fields

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8

DEDT

Bits 16-20: Driver Enable de-assertion time.

Allowed values: 0x0-0x1f

DEAT

Bits 21-25: Driver Enable assertion time.

Allowed values: 0x0-0x1f

RTOIE

Bit 26: Receiver timeout interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register

EOBIE

Bit 27: End of Block interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register

M1

Bit 28: Word length.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

FIFOEN

Bit 29: FIFO mode enable.

Allowed values:
0: Disabled: FIFO mode is disabled
1: Enabled: FIFO mode is enabled

TXFEIE

Bit 30: TXFIFO empty interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when TXFE = 1 in the USART_ISR register

RXFFIE

Bit 31: RXFIFO Full interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when RXFF = 1 in the USART_ISR register

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw
RTOEN
rw
ABRMOD
rw
ABREN
rw
MSBFIRST
rw
DATAINV
rw
TXINV
rw
RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw
LINEN
rw
STOP
rw
CLKEN
rw
CPOL
rw
CPHA
rw
LBCL
rw
LBDIE
rw
LBDL
rw
ADDM7
rw
DIS_NSS
rw
SLVEN
rw
Toggle fields

SLVEN

Bit 0: Synchronous Slave mode enable.

Allowed values:
0: Disabled: Slave mode disabled
1: Enabled: Slave mode enabled

DIS_NSS

Bit 3: When the DSI_NSS bit is set, the NSS pin input is ignored.

Allowed values:
0: Disabled: SPI slave selection depends on NSS input pin
1: Enabled: SPI slave is always selected and NSS input pin is ignored

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

LBDL

Bit 5: LIN break detection length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register

LBCL

Bit 8: Last bit clock pulse.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ABREN

Bit 20: Auto baud rate enable.

Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled

ABRMOD

Bits 21-22: Auto baud rate mode.

Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable.

Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0x0-0xff

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw
RXFTIE
rw
RXFTCFG
rw
TCBGTIE
rw
TXFTIE
rw
WUFIE
rw
WUS
rw
SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw
DEM
rw
DDRE
rw
OVRDIS
rw
ONEBIT
rw
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
SCEN
rw
NACK
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

IREN

Bit 1: Ir mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: Ir low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

OVRDIS

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

SCARCNT

Bits 17-19: Smartcard auto-retry count.

Allowed values: 0x0-0x7

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

TXFTIE

Bit 23: TXFIFO threshold interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG

TCBGTIE

Bit 24: Transmission Complete before guard time, interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated whenever TCBGT=1 in the USART_ISR register

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration.

Allowed values:
0: Depth_1_8: RXFIFO reaches 1/8 of its depth
1: Depth_1_4: RXFIFO reaches 1/4 of its depth
2: Depth_1_2: RXFIFO reaches 1/2 of its depth
3: Depth_3_4: RXFIFO reaches 3/4 of its depth
4: Depth_7_8: RXFIFO reaches 7/8 of its depth
5: Full: RXFIFO becomes full

RXFTIE

Bit 28: RXFIFO threshold interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG

TXFTCFG

Bits 29-31: TXFIFO threshold configuration.

Allowed values:
0: Depth_1_8: TXFIFO reaches 1/8 of its depth
1: Depth_1_4: TXFIFO reaches 1/4 of its depth
2: Depth_1_2: TXFIFO reaches 1/2 of its depth
3: Depth_3_4: TXFIFO reaches 3/4 of its depth
4: Depth_7_8: TXFIFO reaches 7/8 of its depth
5: Empty: TXFIFO becomes empty

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: DIV_Mantissa.

Allowed values: 0x0-0xffff

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw
PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

Allowed values: 0x0-0xff

GT

Bits 8-15: Guard time value.

Allowed values: 0x0-0xff

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw
RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

Allowed values: 0x0-0xffffff

BLEN

Bits 24-31: Block Length.

Allowed values: 0x0-0xff

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w
RXFRQ
w
MMRQ
w
SBKRQ
w
ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: Transmit data flush request.

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r
RXFT
r
TCBGT
r
RXFF
r
TXFE
r
REACK
r
TEACK
r
WUF
r
RWU
r
SBKF
r
CMF
r
BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r
ABRE
r
UDR
r
EOBF
r
RTOF
r
CTS
r
CTSIF
r
LBDF
r
TXE
r
TC
r
RXNE
r
IDLE
r
ORE
r
NF
r
FE
r
PE
r
Toggle fields

PE

Bit 0: PE.

Allowed values:
0: NoError: No parity error
1: Error: Parity error

FE

Bit 1: FE.

Allowed values:
0: NoError: No Framing error is detected
1: Error: Framing error or break character is detected

NF

Bit 2: NF.

Allowed values:
0: NoNoise: No noise is detected
1: Noise: Noise is detected

ORE

Bit 3: ORE.

Allowed values:
0: NoOverrun: No Overrun error
1: Overrun: Overrun error is detected

IDLE

Bit 4: IDLE.

Allowed values:
0: NoIdle: No Idle Line is detected
1: Idle: Idle Line is detected

RXNE

Bit 5: RXNE.

Allowed values:
0: NoData: Data is not received
1: DataReady: Received data is ready to be read

TC

Bit 6: TC.

Allowed values:
0: TxNotComplete: Transmission is not complete
1: TxComplete: Transmission is complete

TXE

Bit 7: TXE.

Allowed values:
0: Full: Transmit FIFO is full
1: NotFull: Transmit FIFO is not full

LBDF

Bit 8: LBDF.

Allowed values:
0: NotDetected: LIN break not detected
1: Detected: LIN break detected

CTSIF

Bit 9: CTSIF.

Allowed values:
0: NotChanged: No change occurred on the CTS status line
1: Changed: A change occurred on the CTS status line

CTS

Bit 10: CTS.

Allowed values:
0: Set: CTS line set
1: Reset: CTS line reset

RTOF

Bit 11: RTOF.

Allowed values:
0: NotReached: Timeout value not reached
1: Reached: Timeout value reached without any data reception

EOBF

Bit 12: EOBF.

Allowed values:
0: NotReached: End of Block not reached
1: Reached: End of Block (number of characters) reached

UDR

Bit 13: SPI slave underrun error flag.

Allowed values:
0: NoUnderrun: No underrun error
1: Underrun: underrun error

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

Allowed values:
0: Idle: USART is idle (no reception)
1: Busy: Reception on going

CMF

Bit 17: CMF.

Allowed values:
0: NoMatch: No Character match detected
1: Match: Character match detected

SBKF

Bit 18: SBKF.

Allowed values:
0: NoBreak: No break character transmitted
1: Break: Break character transmitted

RWU

Bit 19: RWU.

Allowed values:
0: Active: Receiver in Active mode
1: Mute: Receiver in Mute mode

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFIFO Empty.

Allowed values:
0: NotEmpty: TXFIFO not empty.
1: Empty: TXFIFO empty.

RXFF

Bit 24: RXFIFO Full.

Allowed values:
0: NotFull: RXFIFO not full.
1: Full: RXFIFO Full.

TCBGT

Bit 25: Transmission complete before guard time flag.

Allowed values:
0: NotCompleted: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
1: Completed: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)

RXFT

Bit 26: RXFIFO threshold flag.

Allowed values:
0: NotReached: Receive FIFO does not reach the programmed threshold.
1: Reached: Receive FIFO reached the programmed threshold.

TXFT

Bit 27: TXFIFO threshold flag.

Allowed values:
0: NotReached: TXFIFO does not reach the programmed threshold.
1: Reached: TXFIFO reached the programmed threshold.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w1c
CMCF
w1c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w1c
EOBCF
w1c
RTOCF
w1c
CTSCF
w1c
LBDCF
w1c
TCBGTCF
w1c
TCCF
w1c
TXFECF
w1c
IDLECF
w1c
ORECF
w1c
NCF
w1c
FECF
w1c
PECF
w1c
Toggle fields

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TXFECF

Bit 5: TXFIFO empty clear flag.

Allowed values:
1: Clear: Clear the TXFE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag.

Allowed values:
1: Clear: Clear the TCBGT flag in the ISR register

LBDCF

Bit 8: LIN break detection clear flag.

Allowed values:
1: Clear: Clears the LBDF flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

RTOCF

Bit 11: Receiver timeout clear flag.

Allowed values:
1: Clear: Clears the RTOF flag in the ISR register

EOBCF

Bit 12: End of block clear flag.

Allowed values:
1: Clear: Clears the EOBF flag in the ISR register

UDRCF

Bit 13: SPI slave underrun clear flag.

Allowed values:
1: Clear: Clear the UDR flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

Allowed values: 0x0-0x1ff

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

Allowed values: 0x0-0x1ff

PRESC

USART prescaler register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: Clock prescaler.

Allowed values:
0: Div1: Input clock divided by 1
1: Div2: Input clock divided by 2
2: Div4: Input clock divided by 4
3: Div6: Input clock divided by 6
4: Div8: Input clock divided by 8
5: Div10: Input clock divided by 10
6: Div12: Input clock divided by 12
7: Div16: Input clock divided by 16
8: Div32: Input clock divided by 32
9: Div64: Input clock divided by 64
10: Div128: Input clock divided by 128
11: Div256: Input clock divided by 256

UART5

0x40005000: Universal synchronous asynchronous receiver transmitter

124/124 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw
TXFEIE
rw
FIFOEN
rw
M1
rw
EOBIE
rw
RTOIE
rw
DEAT
rw
DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw
CMIE
rw
MME
rw
M0
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
UESM
rw
UE
rw
Toggle fields

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8

DEDT

Bits 16-20: Driver Enable de-assertion time.

Allowed values: 0x0-0x1f

DEAT

Bits 21-25: Driver Enable assertion time.

Allowed values: 0x0-0x1f

RTOIE

Bit 26: Receiver timeout interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register

EOBIE

Bit 27: End of Block interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register

M1

Bit 28: Word length.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

FIFOEN

Bit 29: FIFO mode enable.

Allowed values:
0: Disabled: FIFO mode is disabled
1: Enabled: FIFO mode is enabled

TXFEIE

Bit 30: TXFIFO empty interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when TXFE = 1 in the USART_ISR register

RXFFIE

Bit 31: RXFIFO Full interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when RXFF = 1 in the USART_ISR register

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw
RTOEN
rw
ABRMOD
rw
ABREN
rw
MSBFIRST
rw
DATAINV
rw
TXINV
rw
RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw
LINEN
rw
STOP
rw
CLKEN
rw
CPOL
rw
CPHA
rw
LBCL
rw
LBDIE
rw
LBDL
rw
ADDM7
rw
DIS_NSS
rw
SLVEN
rw
Toggle fields

SLVEN

Bit 0: Synchronous Slave mode enable.

Allowed values:
0: Disabled: Slave mode disabled
1: Enabled: Slave mode enabled

DIS_NSS

Bit 3: When the DSI_NSS bit is set, the NSS pin input is ignored.

Allowed values:
0: Disabled: SPI slave selection depends on NSS input pin
1: Enabled: SPI slave is always selected and NSS input pin is ignored

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

LBDL

Bit 5: LIN break detection length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register

LBCL

Bit 8: Last bit clock pulse.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ABREN

Bit 20: Auto baud rate enable.

Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled

ABRMOD

Bits 21-22: Auto baud rate mode.

Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable.

Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0x0-0xff

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw
RXFTIE
rw
RXFTCFG
rw
TCBGTIE
rw
TXFTIE
rw
WUFIE
rw
WUS
rw
SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw
DEM
rw
DDRE
rw
OVRDIS
rw
ONEBIT
rw
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
SCEN
rw
NACK
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

IREN

Bit 1: Ir mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: Ir low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

OVRDIS

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

SCARCNT

Bits 17-19: Smartcard auto-retry count.

Allowed values: 0x0-0x7

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

TXFTIE

Bit 23: TXFIFO threshold interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG

TCBGTIE

Bit 24: Transmission Complete before guard time, interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated whenever TCBGT=1 in the USART_ISR register

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration.

Allowed values:
0: Depth_1_8: RXFIFO reaches 1/8 of its depth
1: Depth_1_4: RXFIFO reaches 1/4 of its depth
2: Depth_1_2: RXFIFO reaches 1/2 of its depth
3: Depth_3_4: RXFIFO reaches 3/4 of its depth
4: Depth_7_8: RXFIFO reaches 7/8 of its depth
5: Full: RXFIFO becomes full

RXFTIE

Bit 28: RXFIFO threshold interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG

TXFTCFG

Bits 29-31: TXFIFO threshold configuration.

Allowed values:
0: Depth_1_8: TXFIFO reaches 1/8 of its depth
1: Depth_1_4: TXFIFO reaches 1/4 of its depth
2: Depth_1_2: TXFIFO reaches 1/2 of its depth
3: Depth_3_4: TXFIFO reaches 3/4 of its depth
4: Depth_7_8: TXFIFO reaches 7/8 of its depth
5: Empty: TXFIFO becomes empty

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: DIV_Mantissa.

Allowed values: 0x0-0xffff

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw
PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

Allowed values: 0x0-0xff

GT

Bits 8-15: Guard time value.

Allowed values: 0x0-0xff

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw
RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

Allowed values: 0x0-0xffffff

BLEN

Bits 24-31: Block Length.

Allowed values: 0x0-0xff

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w
RXFRQ
w
MMRQ
w
SBKRQ
w
ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: Transmit data flush request.

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r
RXFT
r
TCBGT
r
RXFF
r
TXFE
r
REACK
r
TEACK
r
WUF
r
RWU
r
SBKF
r
CMF
r
BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r
ABRE
r
UDR
r
EOBF
r
RTOF
r
CTS
r
CTSIF
r
LBDF
r
TXE
r
TC
r
RXNE
r
IDLE
r
ORE
r
NF
r
FE
r
PE
r
Toggle fields

PE

Bit 0: PE.

Allowed values:
0: NoError: No parity error
1: Error: Parity error

FE

Bit 1: FE.

Allowed values:
0: NoError: No Framing error is detected
1: Error: Framing error or break character is detected

NF

Bit 2: NF.

Allowed values:
0: NoNoise: No noise is detected
1: Noise: Noise is detected

ORE

Bit 3: ORE.

Allowed values:
0: NoOverrun: No Overrun error
1: Overrun: Overrun error is detected

IDLE

Bit 4: IDLE.

Allowed values:
0: NoIdle: No Idle Line is detected
1: Idle: Idle Line is detected

RXNE

Bit 5: RXNE.

Allowed values:
0: NoData: Data is not received
1: DataReady: Received data is ready to be read

TC

Bit 6: TC.

Allowed values:
0: TxNotComplete: Transmission is not complete
1: TxComplete: Transmission is complete

TXE

Bit 7: TXE.

Allowed values:
0: Full: Transmit FIFO is full
1: NotFull: Transmit FIFO is not full

LBDF

Bit 8: LBDF.

Allowed values:
0: NotDetected: LIN break not detected
1: Detected: LIN break detected

CTSIF

Bit 9: CTSIF.

Allowed values:
0: NotChanged: No change occurred on the CTS status line
1: Changed: A change occurred on the CTS status line

CTS

Bit 10: CTS.

Allowed values:
0: Set: CTS line set
1: Reset: CTS line reset

RTOF

Bit 11: RTOF.

Allowed values:
0: NotReached: Timeout value not reached
1: Reached: Timeout value reached without any data reception

EOBF

Bit 12: EOBF.

Allowed values:
0: NotReached: End of Block not reached
1: Reached: End of Block (number of characters) reached

UDR

Bit 13: SPI slave underrun error flag.

Allowed values:
0: NoUnderrun: No underrun error
1: Underrun: underrun error

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

Allowed values:
0: Idle: USART is idle (no reception)
1: Busy: Reception on going

CMF

Bit 17: CMF.

Allowed values:
0: NoMatch: No Character match detected
1: Match: Character match detected

SBKF

Bit 18: SBKF.

Allowed values:
0: NoBreak: No break character transmitted
1: Break: Break character transmitted

RWU

Bit 19: RWU.

Allowed values:
0: Active: Receiver in Active mode
1: Mute: Receiver in Mute mode

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFIFO Empty.

Allowed values:
0: NotEmpty: TXFIFO not empty.
1: Empty: TXFIFO empty.

RXFF

Bit 24: RXFIFO Full.

Allowed values:
0: NotFull: RXFIFO not full.
1: Full: RXFIFO Full.

TCBGT

Bit 25: Transmission complete before guard time flag.

Allowed values:
0: NotCompleted: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
1: Completed: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)

RXFT

Bit 26: RXFIFO threshold flag.

Allowed values:
0: NotReached: Receive FIFO does not reach the programmed threshold.
1: Reached: Receive FIFO reached the programmed threshold.

TXFT

Bit 27: TXFIFO threshold flag.

Allowed values:
0: NotReached: TXFIFO does not reach the programmed threshold.
1: Reached: TXFIFO reached the programmed threshold.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w1c
CMCF
w1c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w1c
EOBCF
w1c
RTOCF
w1c
CTSCF
w1c
LBDCF
w1c
TCBGTCF
w1c
TCCF
w1c
TXFECF
w1c
IDLECF
w1c
ORECF
w1c
NCF
w1c
FECF
w1c
PECF
w1c
Toggle fields

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TXFECF

Bit 5: TXFIFO empty clear flag.

Allowed values:
1: Clear: Clear the TXFE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag.

Allowed values:
1: Clear: Clear the TCBGT flag in the ISR register

LBDCF

Bit 8: LIN break detection clear flag.

Allowed values:
1: Clear: Clears the LBDF flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

RTOCF

Bit 11: Receiver timeout clear flag.

Allowed values:
1: Clear: Clears the RTOF flag in the ISR register

EOBCF

Bit 12: End of block clear flag.

Allowed values:
1: Clear: Clears the EOBF flag in the ISR register

UDRCF

Bit 13: SPI slave underrun clear flag.

Allowed values:
1: Clear: Clear the UDR flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

Allowed values: 0x0-0x1ff

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

Allowed values: 0x0-0x1ff

PRESC

USART prescaler register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: Clock prescaler.

Allowed values:
0: Div1: Input clock divided by 1
1: Div2: Input clock divided by 2
2: Div4: Input clock divided by 4
3: Div6: Input clock divided by 6
4: Div8: Input clock divided by 8
5: Div10: Input clock divided by 10
6: Div12: Input clock divided by 12
7: Div16: Input clock divided by 16
8: Div32: Input clock divided by 32
9: Div64: Input clock divided by 64
10: Div128: Input clock divided by 128
11: Div256: Input clock divided by 256

UART7

0x40007800: Universal synchronous asynchronous receiver transmitter

124/124 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw
TXFEIE
rw
FIFOEN
rw
M1
rw
EOBIE
rw
RTOIE
rw
DEAT
rw
DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw
CMIE
rw
MME
rw
M0
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
UESM
rw
UE
rw
Toggle fields

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8

DEDT

Bits 16-20: Driver Enable de-assertion time.

Allowed values: 0x0-0x1f

DEAT

Bits 21-25: Driver Enable assertion time.

Allowed values: 0x0-0x1f

RTOIE

Bit 26: Receiver timeout interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register

EOBIE

Bit 27: End of Block interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register

M1

Bit 28: Word length.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

FIFOEN

Bit 29: FIFO mode enable.

Allowed values:
0: Disabled: FIFO mode is disabled
1: Enabled: FIFO mode is enabled

TXFEIE

Bit 30: TXFIFO empty interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when TXFE = 1 in the USART_ISR register

RXFFIE

Bit 31: RXFIFO Full interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when RXFF = 1 in the USART_ISR register

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw
RTOEN
rw
ABRMOD
rw
ABREN
rw
MSBFIRST
rw
DATAINV
rw
TXINV
rw
RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw
LINEN
rw
STOP
rw
CLKEN
rw
CPOL
rw
CPHA
rw
LBCL
rw
LBDIE
rw
LBDL
rw
ADDM7
rw
DIS_NSS
rw
SLVEN
rw
Toggle fields

SLVEN

Bit 0: Synchronous Slave mode enable.

Allowed values:
0: Disabled: Slave mode disabled
1: Enabled: Slave mode enabled

DIS_NSS

Bit 3: When the DSI_NSS bit is set, the NSS pin input is ignored.

Allowed values:
0: Disabled: SPI slave selection depends on NSS input pin
1: Enabled: SPI slave is always selected and NSS input pin is ignored

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

LBDL

Bit 5: LIN break detection length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register

LBCL

Bit 8: Last bit clock pulse.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ABREN

Bit 20: Auto baud rate enable.

Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled

ABRMOD

Bits 21-22: Auto baud rate mode.

Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable.

Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0x0-0xff

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw
RXFTIE
rw
RXFTCFG
rw
TCBGTIE
rw
TXFTIE
rw
WUFIE
rw
WUS
rw
SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw
DEM
rw
DDRE
rw
OVRDIS
rw
ONEBIT
rw
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
SCEN
rw
NACK
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

IREN

Bit 1: Ir mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: Ir low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

OVRDIS

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

SCARCNT

Bits 17-19: Smartcard auto-retry count.

Allowed values: 0x0-0x7

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

TXFTIE

Bit 23: TXFIFO threshold interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG

TCBGTIE

Bit 24: Transmission Complete before guard time, interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated whenever TCBGT=1 in the USART_ISR register

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration.

Allowed values:
0: Depth_1_8: RXFIFO reaches 1/8 of its depth
1: Depth_1_4: RXFIFO reaches 1/4 of its depth
2: Depth_1_2: RXFIFO reaches 1/2 of its depth
3: Depth_3_4: RXFIFO reaches 3/4 of its depth
4: Depth_7_8: RXFIFO reaches 7/8 of its depth
5: Full: RXFIFO becomes full

RXFTIE

Bit 28: RXFIFO threshold interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG

TXFTCFG

Bits 29-31: TXFIFO threshold configuration.

Allowed values:
0: Depth_1_8: TXFIFO reaches 1/8 of its depth
1: Depth_1_4: TXFIFO reaches 1/4 of its depth
2: Depth_1_2: TXFIFO reaches 1/2 of its depth
3: Depth_3_4: TXFIFO reaches 3/4 of its depth
4: Depth_7_8: TXFIFO reaches 7/8 of its depth
5: Empty: TXFIFO becomes empty

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: DIV_Mantissa.

Allowed values: 0x0-0xffff

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw
PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

Allowed values: 0x0-0xff

GT

Bits 8-15: Guard time value.

Allowed values: 0x0-0xff

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw
RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

Allowed values: 0x0-0xffffff

BLEN

Bits 24-31: Block Length.

Allowed values: 0x0-0xff

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w
RXFRQ
w
MMRQ
w
SBKRQ
w
ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: Transmit data flush request.

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r
RXFT
r
TCBGT
r
RXFF
r
TXFE
r
REACK
r
TEACK
r
WUF
r
RWU
r
SBKF
r
CMF
r
BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r
ABRE
r
UDR
r
EOBF
r
RTOF
r
CTS
r
CTSIF
r
LBDF
r
TXE
r
TC
r
RXNE
r
IDLE
r
ORE
r
NF
r
FE
r
PE
r
Toggle fields

PE

Bit 0: PE.

Allowed values:
0: NoError: No parity error
1: Error: Parity error

FE

Bit 1: FE.

Allowed values:
0: NoError: No Framing error is detected
1: Error: Framing error or break character is detected

NF

Bit 2: NF.

Allowed values:
0: NoNoise: No noise is detected
1: Noise: Noise is detected

ORE

Bit 3: ORE.

Allowed values:
0: NoOverrun: No Overrun error
1: Overrun: Overrun error is detected

IDLE

Bit 4: IDLE.

Allowed values:
0: NoIdle: No Idle Line is detected
1: Idle: Idle Line is detected

RXNE

Bit 5: RXNE.

Allowed values:
0: NoData: Data is not received
1: DataReady: Received data is ready to be read

TC

Bit 6: TC.

Allowed values:
0: TxNotComplete: Transmission is not complete
1: TxComplete: Transmission is complete

TXE

Bit 7: TXE.

Allowed values:
0: Full: Transmit FIFO is full
1: NotFull: Transmit FIFO is not full

LBDF

Bit 8: LBDF.

Allowed values:
0: NotDetected: LIN break not detected
1: Detected: LIN break detected

CTSIF

Bit 9: CTSIF.

Allowed values:
0: NotChanged: No change occurred on the CTS status line
1: Changed: A change occurred on the CTS status line

CTS

Bit 10: CTS.

Allowed values:
0: Set: CTS line set
1: Reset: CTS line reset

RTOF

Bit 11: RTOF.

Allowed values:
0: NotReached: Timeout value not reached
1: Reached: Timeout value reached without any data reception

EOBF

Bit 12: EOBF.

Allowed values:
0: NotReached: End of Block not reached
1: Reached: End of Block (number of characters) reached

UDR

Bit 13: SPI slave underrun error flag.

Allowed values:
0: NoUnderrun: No underrun error
1: Underrun: underrun error

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

Allowed values:
0: Idle: USART is idle (no reception)
1: Busy: Reception on going

CMF

Bit 17: CMF.

Allowed values:
0: NoMatch: No Character match detected
1: Match: Character match detected

SBKF

Bit 18: SBKF.

Allowed values:
0: NoBreak: No break character transmitted
1: Break: Break character transmitted

RWU

Bit 19: RWU.

Allowed values:
0: Active: Receiver in Active mode
1: Mute: Receiver in Mute mode

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFIFO Empty.

Allowed values:
0: NotEmpty: TXFIFO not empty.
1: Empty: TXFIFO empty.

RXFF

Bit 24: RXFIFO Full.

Allowed values:
0: NotFull: RXFIFO not full.
1: Full: RXFIFO Full.

TCBGT

Bit 25: Transmission complete before guard time flag.

Allowed values:
0: NotCompleted: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
1: Completed: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)

RXFT

Bit 26: RXFIFO threshold flag.

Allowed values:
0: NotReached: Receive FIFO does not reach the programmed threshold.
1: Reached: Receive FIFO reached the programmed threshold.

TXFT

Bit 27: TXFIFO threshold flag.

Allowed values:
0: NotReached: TXFIFO does not reach the programmed threshold.
1: Reached: TXFIFO reached the programmed threshold.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w1c
CMCF
w1c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w1c
EOBCF
w1c
RTOCF
w1c
CTSCF
w1c
LBDCF
w1c
TCBGTCF
w1c
TCCF
w1c
TXFECF
w1c
IDLECF
w1c
ORECF
w1c
NCF
w1c
FECF
w1c
PECF
w1c
Toggle fields

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TXFECF

Bit 5: TXFIFO empty clear flag.

Allowed values:
1: Clear: Clear the TXFE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag.

Allowed values:
1: Clear: Clear the TCBGT flag in the ISR register

LBDCF

Bit 8: LIN break detection clear flag.

Allowed values:
1: Clear: Clears the LBDF flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

RTOCF

Bit 11: Receiver timeout clear flag.

Allowed values:
1: Clear: Clears the RTOF flag in the ISR register

EOBCF

Bit 12: End of block clear flag.

Allowed values:
1: Clear: Clears the EOBF flag in the ISR register

UDRCF

Bit 13: SPI slave underrun clear flag.

Allowed values:
1: Clear: Clear the UDR flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

Allowed values: 0x0-0x1ff

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

Allowed values: 0x0-0x1ff

PRESC

USART prescaler register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: Clock prescaler.

Allowed values:
0: Div1: Input clock divided by 1
1: Div2: Input clock divided by 2
2: Div4: Input clock divided by 4
3: Div6: Input clock divided by 6
4: Div8: Input clock divided by 8
5: Div10: Input clock divided by 10
6: Div12: Input clock divided by 12
7: Div16: Input clock divided by 16
8: Div32: Input clock divided by 32
9: Div64: Input clock divided by 64
10: Div128: Input clock divided by 128
11: Div256: Input clock divided by 256

UART8

0x40007c00: Universal synchronous asynchronous receiver transmitter

124/124 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw
TXFEIE
rw
FIFOEN
rw
M1
rw
EOBIE
rw
RTOIE
rw
DEAT
rw
DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw
CMIE
rw
MME
rw
M0
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
UESM
rw
UE
rw
Toggle fields

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8

DEDT

Bits 16-20: Driver Enable de-assertion time.

Allowed values: 0x0-0x1f

DEAT

Bits 21-25: Driver Enable assertion time.

Allowed values: 0x0-0x1f

RTOIE

Bit 26: Receiver timeout interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register

EOBIE

Bit 27: End of Block interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register

M1

Bit 28: Word length.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

FIFOEN

Bit 29: FIFO mode enable.

Allowed values:
0: Disabled: FIFO mode is disabled
1: Enabled: FIFO mode is enabled

TXFEIE

Bit 30: TXFIFO empty interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when TXFE = 1 in the USART_ISR register

RXFFIE

Bit 31: RXFIFO Full interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when RXFF = 1 in the USART_ISR register

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw
RTOEN
rw
ABRMOD
rw
ABREN
rw
MSBFIRST
rw
DATAINV
rw
TXINV
rw
RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw
LINEN
rw
STOP
rw
CLKEN
rw
CPOL
rw
CPHA
rw
LBCL
rw
LBDIE
rw
LBDL
rw
ADDM7
rw
DIS_NSS
rw
SLVEN
rw
Toggle fields

SLVEN

Bit 0: Synchronous Slave mode enable.

Allowed values:
0: Disabled: Slave mode disabled
1: Enabled: Slave mode enabled

DIS_NSS

Bit 3: When the DSI_NSS bit is set, the NSS pin input is ignored.

Allowed values:
0: Disabled: SPI slave selection depends on NSS input pin
1: Enabled: SPI slave is always selected and NSS input pin is ignored

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

LBDL

Bit 5: LIN break detection length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register

LBCL

Bit 8: Last bit clock pulse.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ABREN

Bit 20: Auto baud rate enable.

Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled

ABRMOD

Bits 21-22: Auto baud rate mode.

Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable.

Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0x0-0xff

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw
RXFTIE
rw
RXFTCFG
rw
TCBGTIE
rw
TXFTIE
rw
WUFIE
rw
WUS
rw
SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw
DEM
rw
DDRE
rw
OVRDIS
rw
ONEBIT
rw
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
SCEN
rw
NACK
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

IREN

Bit 1: Ir mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: Ir low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

OVRDIS

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

SCARCNT

Bits 17-19: Smartcard auto-retry count.

Allowed values: 0x0-0x7

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

TXFTIE

Bit 23: TXFIFO threshold interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG

TCBGTIE

Bit 24: Transmission Complete before guard time, interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated whenever TCBGT=1 in the USART_ISR register

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration.

Allowed values:
0: Depth_1_8: RXFIFO reaches 1/8 of its depth
1: Depth_1_4: RXFIFO reaches 1/4 of its depth
2: Depth_1_2: RXFIFO reaches 1/2 of its depth
3: Depth_3_4: RXFIFO reaches 3/4 of its depth
4: Depth_7_8: RXFIFO reaches 7/8 of its depth
5: Full: RXFIFO becomes full

RXFTIE

Bit 28: RXFIFO threshold interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG

TXFTCFG

Bits 29-31: TXFIFO threshold configuration.

Allowed values:
0: Depth_1_8: TXFIFO reaches 1/8 of its depth
1: Depth_1_4: TXFIFO reaches 1/4 of its depth
2: Depth_1_2: TXFIFO reaches 1/2 of its depth
3: Depth_3_4: TXFIFO reaches 3/4 of its depth
4: Depth_7_8: TXFIFO reaches 7/8 of its depth
5: Empty: TXFIFO becomes empty

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: DIV_Mantissa.

Allowed values: 0x0-0xffff

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw
PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

Allowed values: 0x0-0xff

GT

Bits 8-15: Guard time value.

Allowed values: 0x0-0xff

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw
RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

Allowed values: 0x0-0xffffff

BLEN

Bits 24-31: Block Length.

Allowed values: 0x0-0xff

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w
RXFRQ
w
MMRQ
w
SBKRQ
w
ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: Transmit data flush request.

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r
RXFT
r
TCBGT
r
RXFF
r
TXFE
r
REACK
r
TEACK
r
WUF
r
RWU
r
SBKF
r
CMF
r
BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r
ABRE
r
UDR
r
EOBF
r
RTOF
r
CTS
r
CTSIF
r
LBDF
r
TXE
r
TC
r
RXNE
r
IDLE
r
ORE
r
NF
r
FE
r
PE
r
Toggle fields

PE

Bit 0: PE.

Allowed values:
0: NoError: No parity error
1: Error: Parity error

FE

Bit 1: FE.

Allowed values:
0: NoError: No Framing error is detected
1: Error: Framing error or break character is detected

NF

Bit 2: NF.

Allowed values:
0: NoNoise: No noise is detected
1: Noise: Noise is detected

ORE

Bit 3: ORE.

Allowed values:
0: NoOverrun: No Overrun error
1: Overrun: Overrun error is detected

IDLE

Bit 4: IDLE.

Allowed values:
0: NoIdle: No Idle Line is detected
1: Idle: Idle Line is detected

RXNE

Bit 5: RXNE.

Allowed values:
0: NoData: Data is not received
1: DataReady: Received data is ready to be read

TC

Bit 6: TC.

Allowed values:
0: TxNotComplete: Transmission is not complete
1: TxComplete: Transmission is complete

TXE

Bit 7: TXE.

Allowed values:
0: Full: Transmit FIFO is full
1: NotFull: Transmit FIFO is not full

LBDF

Bit 8: LBDF.

Allowed values:
0: NotDetected: LIN break not detected
1: Detected: LIN break detected

CTSIF

Bit 9: CTSIF.

Allowed values:
0: NotChanged: No change occurred on the CTS status line
1: Changed: A change occurred on the CTS status line

CTS

Bit 10: CTS.

Allowed values:
0: Set: CTS line set
1: Reset: CTS line reset

RTOF

Bit 11: RTOF.

Allowed values:
0: NotReached: Timeout value not reached
1: Reached: Timeout value reached without any data reception

EOBF

Bit 12: EOBF.

Allowed values:
0: NotReached: End of Block not reached
1: Reached: End of Block (number of characters) reached

UDR

Bit 13: SPI slave underrun error flag.

Allowed values:
0: NoUnderrun: No underrun error
1: Underrun: underrun error

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

Allowed values:
0: Idle: USART is idle (no reception)
1: Busy: Reception on going

CMF

Bit 17: CMF.

Allowed values:
0: NoMatch: No Character match detected
1: Match: Character match detected

SBKF

Bit 18: SBKF.

Allowed values:
0: NoBreak: No break character transmitted
1: Break: Break character transmitted

RWU

Bit 19: RWU.

Allowed values:
0: Active: Receiver in Active mode
1: Mute: Receiver in Mute mode

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFIFO Empty.

Allowed values:
0: NotEmpty: TXFIFO not empty.
1: Empty: TXFIFO empty.

RXFF

Bit 24: RXFIFO Full.

Allowed values:
0: NotFull: RXFIFO not full.
1: Full: RXFIFO Full.

TCBGT

Bit 25: Transmission complete before guard time flag.

Allowed values:
0: NotCompleted: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
1: Completed: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)

RXFT

Bit 26: RXFIFO threshold flag.

Allowed values:
0: NotReached: Receive FIFO does not reach the programmed threshold.
1: Reached: Receive FIFO reached the programmed threshold.

TXFT

Bit 27: TXFIFO threshold flag.

Allowed values:
0: NotReached: TXFIFO does not reach the programmed threshold.
1: Reached: TXFIFO reached the programmed threshold.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w1c
CMCF
w1c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w1c
EOBCF
w1c
RTOCF
w1c
CTSCF
w1c
LBDCF
w1c
TCBGTCF
w1c
TCCF
w1c
TXFECF
w1c
IDLECF
w1c
ORECF
w1c
NCF
w1c
FECF
w1c
PECF
w1c
Toggle fields

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TXFECF

Bit 5: TXFIFO empty clear flag.

Allowed values:
1: Clear: Clear the TXFE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag.

Allowed values:
1: Clear: Clear the TCBGT flag in the ISR register

LBDCF

Bit 8: LIN break detection clear flag.

Allowed values:
1: Clear: Clears the LBDF flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

RTOCF

Bit 11: Receiver timeout clear flag.

Allowed values:
1: Clear: Clears the RTOF flag in the ISR register

EOBCF

Bit 12: End of block clear flag.

Allowed values:
1: Clear: Clears the EOBF flag in the ISR register

UDRCF

Bit 13: SPI slave underrun clear flag.

Allowed values:
1: Clear: Clear the UDR flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

Allowed values: 0x0-0x1ff

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

Allowed values: 0x0-0x1ff

PRESC

USART prescaler register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: Clock prescaler.

Allowed values:
0: Div1: Input clock divided by 1
1: Div2: Input clock divided by 2
2: Div4: Input clock divided by 4
3: Div6: Input clock divided by 6
4: Div8: Input clock divided by 8
5: Div10: Input clock divided by 10
6: Div12: Input clock divided by 12
7: Div16: Input clock divided by 16
8: Div32: Input clock divided by 32
9: Div64: Input clock divided by 64
10: Div128: Input clock divided by 128
11: Div256: Input clock divided by 256

UART9

0x40011800: Universal synchronous asynchronous receiver transmitter

124/124 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw
TXFEIE
rw
FIFOEN
rw
M1
rw
EOBIE
rw
RTOIE
rw
DEAT
rw
DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw
CMIE
rw
MME
rw
M0
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
UESM
rw
UE
rw
Toggle fields

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8

DEDT

Bits 16-20: Driver Enable de-assertion time.

Allowed values: 0x0-0x1f

DEAT

Bits 21-25: Driver Enable assertion time.

Allowed values: 0x0-0x1f

RTOIE

Bit 26: Receiver timeout interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register

EOBIE

Bit 27: End of Block interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register

M1

Bit 28: Word length.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

FIFOEN

Bit 29: FIFO mode enable.

Allowed values:
0: Disabled: FIFO mode is disabled
1: Enabled: FIFO mode is enabled

TXFEIE

Bit 30: TXFIFO empty interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when TXFE = 1 in the USART_ISR register

RXFFIE

Bit 31: RXFIFO Full interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when RXFF = 1 in the USART_ISR register

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw
RTOEN
rw
ABRMOD
rw
ABREN
rw
MSBFIRST
rw
DATAINV
rw
TXINV
rw
RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw
LINEN
rw
STOP
rw
CLKEN
rw
CPOL
rw
CPHA
rw
LBCL
rw
LBDIE
rw
LBDL
rw
ADDM7
rw
DIS_NSS
rw
SLVEN
rw
Toggle fields

SLVEN

Bit 0: Synchronous Slave mode enable.

Allowed values:
0: Disabled: Slave mode disabled
1: Enabled: Slave mode enabled

DIS_NSS

Bit 3: When the DSI_NSS bit is set, the NSS pin input is ignored.

Allowed values:
0: Disabled: SPI slave selection depends on NSS input pin
1: Enabled: SPI slave is always selected and NSS input pin is ignored

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

LBDL

Bit 5: LIN break detection length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register

LBCL

Bit 8: Last bit clock pulse.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ABREN

Bit 20: Auto baud rate enable.

Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled

ABRMOD

Bits 21-22: Auto baud rate mode.

Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable.

Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0x0-0xff

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw
RXFTIE
rw
RXFTCFG
rw
TCBGTIE
rw
TXFTIE
rw
WUFIE
rw
WUS
rw
SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw
DEM
rw
DDRE
rw
OVRDIS
rw
ONEBIT
rw
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
SCEN
rw
NACK
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

IREN

Bit 1: Ir mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: Ir low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

OVRDIS

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

SCARCNT

Bits 17-19: Smartcard auto-retry count.

Allowed values: 0x0-0x7

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

TXFTIE

Bit 23: TXFIFO threshold interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG

TCBGTIE

Bit 24: Transmission Complete before guard time, interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated whenever TCBGT=1 in the USART_ISR register

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration.

Allowed values:
0: Depth_1_8: RXFIFO reaches 1/8 of its depth
1: Depth_1_4: RXFIFO reaches 1/4 of its depth
2: Depth_1_2: RXFIFO reaches 1/2 of its depth
3: Depth_3_4: RXFIFO reaches 3/4 of its depth
4: Depth_7_8: RXFIFO reaches 7/8 of its depth
5: Full: RXFIFO becomes full

RXFTIE

Bit 28: RXFIFO threshold interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG

TXFTCFG

Bits 29-31: TXFIFO threshold configuration.

Allowed values:
0: Depth_1_8: TXFIFO reaches 1/8 of its depth
1: Depth_1_4: TXFIFO reaches 1/4 of its depth
2: Depth_1_2: TXFIFO reaches 1/2 of its depth
3: Depth_3_4: TXFIFO reaches 3/4 of its depth
4: Depth_7_8: TXFIFO reaches 7/8 of its depth
5: Empty: TXFIFO becomes empty

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: DIV_Mantissa.

Allowed values: 0x0-0xffff

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw
PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

Allowed values: 0x0-0xff

GT

Bits 8-15: Guard time value.

Allowed values: 0x0-0xff

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw
RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

Allowed values: 0x0-0xffffff

BLEN

Bits 24-31: Block Length.

Allowed values: 0x0-0xff

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w
RXFRQ
w
MMRQ
w
SBKRQ
w
ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: Transmit data flush request.

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r
RXFT
r
TCBGT
r
RXFF
r
TXFE
r
REACK
r
TEACK
r
WUF
r
RWU
r
SBKF
r
CMF
r
BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r
ABRE
r
UDR
r
EOBF
r
RTOF
r
CTS
r
CTSIF
r
LBDF
r
TXE
r
TC
r
RXNE
r
IDLE
r
ORE
r
NF
r
FE
r
PE
r
Toggle fields

PE

Bit 0: PE.

Allowed values:
0: NoError: No parity error
1: Error: Parity error

FE

Bit 1: FE.

Allowed values:
0: NoError: No Framing error is detected
1: Error: Framing error or break character is detected

NF

Bit 2: NF.

Allowed values:
0: NoNoise: No noise is detected
1: Noise: Noise is detected

ORE

Bit 3: ORE.

Allowed values:
0: NoOverrun: No Overrun error
1: Overrun: Overrun error is detected

IDLE

Bit 4: IDLE.

Allowed values:
0: NoIdle: No Idle Line is detected
1: Idle: Idle Line is detected

RXNE

Bit 5: RXNE.

Allowed values:
0: NoData: Data is not received
1: DataReady: Received data is ready to be read

TC

Bit 6: TC.

Allowed values:
0: TxNotComplete: Transmission is not complete
1: TxComplete: Transmission is complete

TXE

Bit 7: TXE.

Allowed values:
0: Full: Transmit FIFO is full
1: NotFull: Transmit FIFO is not full

LBDF

Bit 8: LBDF.

Allowed values:
0: NotDetected: LIN break not detected
1: Detected: LIN break detected

CTSIF

Bit 9: CTSIF.

Allowed values:
0: NotChanged: No change occurred on the CTS status line
1: Changed: A change occurred on the CTS status line

CTS

Bit 10: CTS.

Allowed values:
0: Set: CTS line set
1: Reset: CTS line reset

RTOF

Bit 11: RTOF.

Allowed values:
0: NotReached: Timeout value not reached
1: Reached: Timeout value reached without any data reception

EOBF

Bit 12: EOBF.

Allowed values:
0: NotReached: End of Block not reached
1: Reached: End of Block (number of characters) reached

UDR

Bit 13: SPI slave underrun error flag.

Allowed values:
0: NoUnderrun: No underrun error
1: Underrun: underrun error

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

Allowed values:
0: Idle: USART is idle (no reception)
1: Busy: Reception on going

CMF

Bit 17: CMF.

Allowed values:
0: NoMatch: No Character match detected
1: Match: Character match detected

SBKF

Bit 18: SBKF.

Allowed values:
0: NoBreak: No break character transmitted
1: Break: Break character transmitted

RWU

Bit 19: RWU.

Allowed values:
0: Active: Receiver in Active mode
1: Mute: Receiver in Mute mode

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFIFO Empty.

Allowed values:
0: NotEmpty: TXFIFO not empty.
1: Empty: TXFIFO empty.

RXFF

Bit 24: RXFIFO Full.

Allowed values:
0: NotFull: RXFIFO not full.
1: Full: RXFIFO Full.

TCBGT

Bit 25: Transmission complete before guard time flag.

Allowed values:
0: NotCompleted: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
1: Completed: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)

RXFT

Bit 26: RXFIFO threshold flag.

Allowed values:
0: NotReached: Receive FIFO does not reach the programmed threshold.
1: Reached: Receive FIFO reached the programmed threshold.

TXFT

Bit 27: TXFIFO threshold flag.

Allowed values:
0: NotReached: TXFIFO does not reach the programmed threshold.
1: Reached: TXFIFO reached the programmed threshold.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w1c
CMCF
w1c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w1c
EOBCF
w1c
RTOCF
w1c
CTSCF
w1c
LBDCF
w1c
TCBGTCF
w1c
TCCF
w1c
TXFECF
w1c
IDLECF
w1c
ORECF
w1c
NCF
w1c
FECF
w1c
PECF
w1c
Toggle fields

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TXFECF

Bit 5: TXFIFO empty clear flag.

Allowed values:
1: Clear: Clear the TXFE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag.

Allowed values:
1: Clear: Clear the TCBGT flag in the ISR register

LBDCF

Bit 8: LIN break detection clear flag.

Allowed values:
1: Clear: Clears the LBDF flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

RTOCF

Bit 11: Receiver timeout clear flag.

Allowed values:
1: Clear: Clears the RTOF flag in the ISR register

EOBCF

Bit 12: End of block clear flag.

Allowed values:
1: Clear: Clears the EOBF flag in the ISR register

UDRCF

Bit 13: SPI slave underrun clear flag.

Allowed values:
1: Clear: Clear the UDR flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

Allowed values: 0x0-0x1ff

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

Allowed values: 0x0-0x1ff

PRESC

USART prescaler register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: Clock prescaler.

Allowed values:
0: Div1: Input clock divided by 1
1: Div2: Input clock divided by 2
2: Div4: Input clock divided by 4
3: Div6: Input clock divided by 6
4: Div8: Input clock divided by 8
5: Div10: Input clock divided by 10
6: Div12: Input clock divided by 12
7: Div16: Input clock divided by 16
8: Div32: Input clock divided by 32
9: Div64: Input clock divided by 64
10: Div128: Input clock divided by 128
11: Div256: Input clock divided by 256

USART1

0x40011000: Universal synchronous asynchronous receiver transmitter

124/124 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw
TXFEIE
rw
FIFOEN
rw
M1
rw
EOBIE
rw
RTOIE
rw
DEAT
rw
DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw
CMIE
rw
MME
rw
M0
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
UESM
rw
UE
rw
Toggle fields

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8

DEDT

Bits 16-20: Driver Enable de-assertion time.

Allowed values: 0x0-0x1f

DEAT

Bits 21-25: Driver Enable assertion time.

Allowed values: 0x0-0x1f

RTOIE

Bit 26: Receiver timeout interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register

EOBIE

Bit 27: End of Block interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register

M1

Bit 28: Word length.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

FIFOEN

Bit 29: FIFO mode enable.

Allowed values:
0: Disabled: FIFO mode is disabled
1: Enabled: FIFO mode is enabled

TXFEIE

Bit 30: TXFIFO empty interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when TXFE = 1 in the USART_ISR register

RXFFIE

Bit 31: RXFIFO Full interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when RXFF = 1 in the USART_ISR register

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw
RTOEN
rw
ABRMOD
rw
ABREN
rw
MSBFIRST
rw
DATAINV
rw
TXINV
rw
RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw
LINEN
rw
STOP
rw
CLKEN
rw
CPOL
rw
CPHA
rw
LBCL
rw
LBDIE
rw
LBDL
rw
ADDM7
rw
DIS_NSS
rw
SLVEN
rw
Toggle fields

SLVEN

Bit 0: Synchronous Slave mode enable.

Allowed values:
0: Disabled: Slave mode disabled
1: Enabled: Slave mode enabled

DIS_NSS

Bit 3: When the DSI_NSS bit is set, the NSS pin input is ignored.

Allowed values:
0: Disabled: SPI slave selection depends on NSS input pin
1: Enabled: SPI slave is always selected and NSS input pin is ignored

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

LBDL

Bit 5: LIN break detection length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register

LBCL

Bit 8: Last bit clock pulse.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ABREN

Bit 20: Auto baud rate enable.

Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled

ABRMOD

Bits 21-22: Auto baud rate mode.

Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable.

Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0x0-0xff

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw
RXFTIE
rw
RXFTCFG
rw
TCBGTIE
rw
TXFTIE
rw
WUFIE
rw
WUS
rw
SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw
DEM
rw
DDRE
rw
OVRDIS
rw
ONEBIT
rw
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
SCEN
rw
NACK
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

IREN

Bit 1: Ir mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: Ir low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

OVRDIS

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

SCARCNT

Bits 17-19: Smartcard auto-retry count.

Allowed values: 0x0-0x7

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

TXFTIE

Bit 23: TXFIFO threshold interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG

TCBGTIE

Bit 24: Transmission Complete before guard time, interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated whenever TCBGT=1 in the USART_ISR register

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration.

Allowed values:
0: Depth_1_8: RXFIFO reaches 1/8 of its depth
1: Depth_1_4: RXFIFO reaches 1/4 of its depth
2: Depth_1_2: RXFIFO reaches 1/2 of its depth
3: Depth_3_4: RXFIFO reaches 3/4 of its depth
4: Depth_7_8: RXFIFO reaches 7/8 of its depth
5: Full: RXFIFO becomes full

RXFTIE

Bit 28: RXFIFO threshold interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG

TXFTCFG

Bits 29-31: TXFIFO threshold configuration.

Allowed values:
0: Depth_1_8: TXFIFO reaches 1/8 of its depth
1: Depth_1_4: TXFIFO reaches 1/4 of its depth
2: Depth_1_2: TXFIFO reaches 1/2 of its depth
3: Depth_3_4: TXFIFO reaches 3/4 of its depth
4: Depth_7_8: TXFIFO reaches 7/8 of its depth
5: Empty: TXFIFO becomes empty

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: DIV_Mantissa.

Allowed values: 0x0-0xffff

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw
PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

Allowed values: 0x0-0xff

GT

Bits 8-15: Guard time value.

Allowed values: 0x0-0xff

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw
RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

Allowed values: 0x0-0xffffff

BLEN

Bits 24-31: Block Length.

Allowed values: 0x0-0xff

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w
RXFRQ
w
MMRQ
w
SBKRQ
w
ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: Transmit data flush request.

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r
RXFT
r
TCBGT
r
RXFF
r
TXFE
r
REACK
r
TEACK
r
WUF
r
RWU
r
SBKF
r
CMF
r
BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r
ABRE
r
UDR
r
EOBF
r
RTOF
r
CTS
r
CTSIF
r
LBDF
r
TXE
r
TC
r
RXNE
r
IDLE
r
ORE
r
NF
r
FE
r
PE
r
Toggle fields

PE

Bit 0: PE.

Allowed values:
0: NoError: No parity error
1: Error: Parity error

FE

Bit 1: FE.

Allowed values:
0: NoError: No Framing error is detected
1: Error: Framing error or break character is detected

NF

Bit 2: NF.

Allowed values:
0: NoNoise: No noise is detected
1: Noise: Noise is detected

ORE

Bit 3: ORE.

Allowed values:
0: NoOverrun: No Overrun error
1: Overrun: Overrun error is detected

IDLE

Bit 4: IDLE.

Allowed values:
0: NoIdle: No Idle Line is detected
1: Idle: Idle Line is detected

RXNE

Bit 5: RXNE.

Allowed values:
0: NoData: Data is not received
1: DataReady: Received data is ready to be read

TC

Bit 6: TC.

Allowed values:
0: TxNotComplete: Transmission is not complete
1: TxComplete: Transmission is complete

TXE

Bit 7: TXE.

Allowed values:
0: Full: Transmit FIFO is full
1: NotFull: Transmit FIFO is not full

LBDF

Bit 8: LBDF.

Allowed values:
0: NotDetected: LIN break not detected
1: Detected: LIN break detected

CTSIF

Bit 9: CTSIF.

Allowed values:
0: NotChanged: No change occurred on the CTS status line
1: Changed: A change occurred on the CTS status line

CTS

Bit 10: CTS.

Allowed values:
0: Set: CTS line set
1: Reset: CTS line reset

RTOF

Bit 11: RTOF.

Allowed values:
0: NotReached: Timeout value not reached
1: Reached: Timeout value reached without any data reception

EOBF

Bit 12: EOBF.

Allowed values:
0: NotReached: End of Block not reached
1: Reached: End of Block (number of characters) reached

UDR

Bit 13: SPI slave underrun error flag.

Allowed values:
0: NoUnderrun: No underrun error
1: Underrun: underrun error

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

Allowed values:
0: Idle: USART is idle (no reception)
1: Busy: Reception on going

CMF

Bit 17: CMF.

Allowed values:
0: NoMatch: No Character match detected
1: Match: Character match detected

SBKF

Bit 18: SBKF.

Allowed values:
0: NoBreak: No break character transmitted
1: Break: Break character transmitted

RWU

Bit 19: RWU.

Allowed values:
0: Active: Receiver in Active mode
1: Mute: Receiver in Mute mode

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFIFO Empty.

Allowed values:
0: NotEmpty: TXFIFO not empty.
1: Empty: TXFIFO empty.

RXFF

Bit 24: RXFIFO Full.

Allowed values:
0: NotFull: RXFIFO not full.
1: Full: RXFIFO Full.

TCBGT

Bit 25: Transmission complete before guard time flag.

Allowed values:
0: NotCompleted: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
1: Completed: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)

RXFT

Bit 26: RXFIFO threshold flag.

Allowed values:
0: NotReached: Receive FIFO does not reach the programmed threshold.
1: Reached: Receive FIFO reached the programmed threshold.

TXFT

Bit 27: TXFIFO threshold flag.

Allowed values:
0: NotReached: TXFIFO does not reach the programmed threshold.
1: Reached: TXFIFO reached the programmed threshold.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w1c
CMCF
w1c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w1c
EOBCF
w1c
RTOCF
w1c
CTSCF
w1c
LBDCF
w1c
TCBGTCF
w1c
TCCF
w1c
TXFECF
w1c
IDLECF
w1c
ORECF
w1c
NCF
w1c
FECF
w1c
PECF
w1c
Toggle fields

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TXFECF

Bit 5: TXFIFO empty clear flag.

Allowed values:
1: Clear: Clear the TXFE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag.

Allowed values:
1: Clear: Clear the TCBGT flag in the ISR register

LBDCF

Bit 8: LIN break detection clear flag.

Allowed values:
1: Clear: Clears the LBDF flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

RTOCF

Bit 11: Receiver timeout clear flag.

Allowed values:
1: Clear: Clears the RTOF flag in the ISR register

EOBCF

Bit 12: End of block clear flag.

Allowed values:
1: Clear: Clears the EOBF flag in the ISR register

UDRCF

Bit 13: SPI slave underrun clear flag.

Allowed values:
1: Clear: Clear the UDR flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

Allowed values: 0x0-0x1ff

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

Allowed values: 0x0-0x1ff

PRESC

USART prescaler register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: Clock prescaler.

Allowed values:
0: Div1: Input clock divided by 1
1: Div2: Input clock divided by 2
2: Div4: Input clock divided by 4
3: Div6: Input clock divided by 6
4: Div8: Input clock divided by 8
5: Div10: Input clock divided by 10
6: Div12: Input clock divided by 12
7: Div16: Input clock divided by 16
8: Div32: Input clock divided by 32
9: Div64: Input clock divided by 64
10: Div128: Input clock divided by 128
11: Div256: Input clock divided by 256

USART10

0x40011c00: Universal synchronous asynchronous receiver transmitter

124/124 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw
TXFEIE
rw
FIFOEN
rw
M1
rw
EOBIE
rw
RTOIE
rw
DEAT
rw
DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw
CMIE
rw
MME
rw
M0
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
UESM
rw
UE
rw
Toggle fields

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8

DEDT

Bits 16-20: Driver Enable de-assertion time.

Allowed values: 0x0-0x1f

DEAT

Bits 21-25: Driver Enable assertion time.

Allowed values: 0x0-0x1f

RTOIE

Bit 26: Receiver timeout interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register

EOBIE

Bit 27: End of Block interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register

M1

Bit 28: Word length.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

FIFOEN

Bit 29: FIFO mode enable.

Allowed values:
0: Disabled: FIFO mode is disabled
1: Enabled: FIFO mode is enabled

TXFEIE

Bit 30: TXFIFO empty interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when TXFE = 1 in the USART_ISR register

RXFFIE

Bit 31: RXFIFO Full interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when RXFF = 1 in the USART_ISR register

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw
RTOEN
rw
ABRMOD
rw
ABREN
rw
MSBFIRST
rw
DATAINV
rw
TXINV
rw
RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw
LINEN
rw
STOP
rw
CLKEN
rw
CPOL
rw
CPHA
rw
LBCL
rw
LBDIE
rw
LBDL
rw
ADDM7
rw
DIS_NSS
rw
SLVEN
rw
Toggle fields

SLVEN

Bit 0: Synchronous Slave mode enable.

Allowed values:
0: Disabled: Slave mode disabled
1: Enabled: Slave mode enabled

DIS_NSS

Bit 3: When the DSI_NSS bit is set, the NSS pin input is ignored.

Allowed values:
0: Disabled: SPI slave selection depends on NSS input pin
1: Enabled: SPI slave is always selected and NSS input pin is ignored

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

LBDL

Bit 5: LIN break detection length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register

LBCL

Bit 8: Last bit clock pulse.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ABREN

Bit 20: Auto baud rate enable.

Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled

ABRMOD

Bits 21-22: Auto baud rate mode.

Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable.

Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0x0-0xff

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw
RXFTIE
rw
RXFTCFG
rw
TCBGTIE
rw
TXFTIE
rw
WUFIE
rw
WUS
rw
SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw
DEM
rw
DDRE
rw
OVRDIS
rw
ONEBIT
rw
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
SCEN
rw
NACK
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

IREN

Bit 1: Ir mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: Ir low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

OVRDIS

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

SCARCNT

Bits 17-19: Smartcard auto-retry count.

Allowed values: 0x0-0x7

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

TXFTIE

Bit 23: TXFIFO threshold interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG

TCBGTIE

Bit 24: Transmission Complete before guard time, interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated whenever TCBGT=1 in the USART_ISR register

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration.

Allowed values:
0: Depth_1_8: RXFIFO reaches 1/8 of its depth
1: Depth_1_4: RXFIFO reaches 1/4 of its depth
2: Depth_1_2: RXFIFO reaches 1/2 of its depth
3: Depth_3_4: RXFIFO reaches 3/4 of its depth
4: Depth_7_8: RXFIFO reaches 7/8 of its depth
5: Full: RXFIFO becomes full

RXFTIE

Bit 28: RXFIFO threshold interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG

TXFTCFG

Bits 29-31: TXFIFO threshold configuration.

Allowed values:
0: Depth_1_8: TXFIFO reaches 1/8 of its depth
1: Depth_1_4: TXFIFO reaches 1/4 of its depth
2: Depth_1_2: TXFIFO reaches 1/2 of its depth
3: Depth_3_4: TXFIFO reaches 3/4 of its depth
4: Depth_7_8: TXFIFO reaches 7/8 of its depth
5: Empty: TXFIFO becomes empty

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: DIV_Mantissa.

Allowed values: 0x0-0xffff

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw
PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

Allowed values: 0x0-0xff

GT

Bits 8-15: Guard time value.

Allowed values: 0x0-0xff

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw
RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

Allowed values: 0x0-0xffffff

BLEN

Bits 24-31: Block Length.

Allowed values: 0x0-0xff

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w
RXFRQ
w
MMRQ
w
SBKRQ
w
ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: Transmit data flush request.

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r
RXFT
r
TCBGT
r
RXFF
r
TXFE
r
REACK
r
TEACK
r
WUF
r
RWU
r
SBKF
r
CMF
r
BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r
ABRE
r
UDR
r
EOBF
r
RTOF
r
CTS
r
CTSIF
r
LBDF
r
TXE
r
TC
r
RXNE
r
IDLE
r
ORE
r
NF
r
FE
r
PE
r
Toggle fields

PE

Bit 0: PE.

Allowed values:
0: NoError: No parity error
1: Error: Parity error

FE

Bit 1: FE.

Allowed values:
0: NoError: No Framing error is detected
1: Error: Framing error or break character is detected

NF

Bit 2: NF.

Allowed values:
0: NoNoise: No noise is detected
1: Noise: Noise is detected

ORE

Bit 3: ORE.

Allowed values:
0: NoOverrun: No Overrun error
1: Overrun: Overrun error is detected

IDLE

Bit 4: IDLE.

Allowed values:
0: NoIdle: No Idle Line is detected
1: Idle: Idle Line is detected

RXNE

Bit 5: RXNE.

Allowed values:
0: NoData: Data is not received
1: DataReady: Received data is ready to be read

TC

Bit 6: TC.

Allowed values:
0: TxNotComplete: Transmission is not complete
1: TxComplete: Transmission is complete

TXE

Bit 7: TXE.

Allowed values:
0: Full: Transmit FIFO is full
1: NotFull: Transmit FIFO is not full

LBDF

Bit 8: LBDF.

Allowed values:
0: NotDetected: LIN break not detected
1: Detected: LIN break detected

CTSIF

Bit 9: CTSIF.

Allowed values:
0: NotChanged: No change occurred on the CTS status line
1: Changed: A change occurred on the CTS status line

CTS

Bit 10: CTS.

Allowed values:
0: Set: CTS line set
1: Reset: CTS line reset

RTOF

Bit 11: RTOF.

Allowed values:
0: NotReached: Timeout value not reached
1: Reached: Timeout value reached without any data reception

EOBF

Bit 12: EOBF.

Allowed values:
0: NotReached: End of Block not reached
1: Reached: End of Block (number of characters) reached

UDR

Bit 13: SPI slave underrun error flag.

Allowed values:
0: NoUnderrun: No underrun error
1: Underrun: underrun error

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

Allowed values:
0: Idle: USART is idle (no reception)
1: Busy: Reception on going

CMF

Bit 17: CMF.

Allowed values:
0: NoMatch: No Character match detected
1: Match: Character match detected

SBKF

Bit 18: SBKF.

Allowed values:
0: NoBreak: No break character transmitted
1: Break: Break character transmitted

RWU

Bit 19: RWU.

Allowed values:
0: Active: Receiver in Active mode
1: Mute: Receiver in Mute mode

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFIFO Empty.

Allowed values:
0: NotEmpty: TXFIFO not empty.
1: Empty: TXFIFO empty.

RXFF

Bit 24: RXFIFO Full.

Allowed values:
0: NotFull: RXFIFO not full.
1: Full: RXFIFO Full.

TCBGT

Bit 25: Transmission complete before guard time flag.

Allowed values:
0: NotCompleted: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
1: Completed: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)

RXFT

Bit 26: RXFIFO threshold flag.

Allowed values:
0: NotReached: Receive FIFO does not reach the programmed threshold.
1: Reached: Receive FIFO reached the programmed threshold.

TXFT

Bit 27: TXFIFO threshold flag.

Allowed values:
0: NotReached: TXFIFO does not reach the programmed threshold.
1: Reached: TXFIFO reached the programmed threshold.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w1c
CMCF
w1c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w1c
EOBCF
w1c
RTOCF
w1c
CTSCF
w1c
LBDCF
w1c
TCBGTCF
w1c
TCCF
w1c
TXFECF
w1c
IDLECF
w1c
ORECF
w1c
NCF
w1c
FECF
w1c
PECF
w1c
Toggle fields

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TXFECF

Bit 5: TXFIFO empty clear flag.

Allowed values:
1: Clear: Clear the TXFE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag.

Allowed values:
1: Clear: Clear the TCBGT flag in the ISR register

LBDCF

Bit 8: LIN break detection clear flag.

Allowed values:
1: Clear: Clears the LBDF flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

RTOCF

Bit 11: Receiver timeout clear flag.

Allowed values:
1: Clear: Clears the RTOF flag in the ISR register

EOBCF

Bit 12: End of block clear flag.

Allowed values:
1: Clear: Clears the EOBF flag in the ISR register

UDRCF

Bit 13: SPI slave underrun clear flag.

Allowed values:
1: Clear: Clear the UDR flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

Allowed values: 0x0-0x1ff

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

Allowed values: 0x0-0x1ff

PRESC

USART prescaler register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: Clock prescaler.

Allowed values:
0: Div1: Input clock divided by 1
1: Div2: Input clock divided by 2
2: Div4: Input clock divided by 4
3: Div6: Input clock divided by 6
4: Div8: Input clock divided by 8
5: Div10: Input clock divided by 10
6: Div12: Input clock divided by 12
7: Div16: Input clock divided by 16
8: Div32: Input clock divided by 32
9: Div64: Input clock divided by 64
10: Div128: Input clock divided by 128
11: Div256: Input clock divided by 256

USART2

0x40004400: Universal synchronous asynchronous receiver transmitter

124/124 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw
TXFEIE
rw
FIFOEN
rw
M1
rw
EOBIE
rw
RTOIE
rw
DEAT
rw
DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw
CMIE
rw
MME
rw
M0
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
UESM
rw
UE
rw
Toggle fields

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8

DEDT

Bits 16-20: Driver Enable de-assertion time.

Allowed values: 0x0-0x1f

DEAT

Bits 21-25: Driver Enable assertion time.

Allowed values: 0x0-0x1f

RTOIE

Bit 26: Receiver timeout interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register

EOBIE

Bit 27: End of Block interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register

M1

Bit 28: Word length.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

FIFOEN

Bit 29: FIFO mode enable.

Allowed values:
0: Disabled: FIFO mode is disabled
1: Enabled: FIFO mode is enabled

TXFEIE

Bit 30: TXFIFO empty interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when TXFE = 1 in the USART_ISR register

RXFFIE

Bit 31: RXFIFO Full interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when RXFF = 1 in the USART_ISR register

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw
RTOEN
rw
ABRMOD
rw
ABREN
rw
MSBFIRST
rw
DATAINV
rw
TXINV
rw
RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw
LINEN
rw
STOP
rw
CLKEN
rw
CPOL
rw
CPHA
rw
LBCL
rw
LBDIE
rw
LBDL
rw
ADDM7
rw
DIS_NSS
rw
SLVEN
rw
Toggle fields

SLVEN

Bit 0: Synchronous Slave mode enable.

Allowed values:
0: Disabled: Slave mode disabled
1: Enabled: Slave mode enabled

DIS_NSS

Bit 3: When the DSI_NSS bit is set, the NSS pin input is ignored.

Allowed values:
0: Disabled: SPI slave selection depends on NSS input pin
1: Enabled: SPI slave is always selected and NSS input pin is ignored

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

LBDL

Bit 5: LIN break detection length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register

LBCL

Bit 8: Last bit clock pulse.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ABREN

Bit 20: Auto baud rate enable.

Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled

ABRMOD

Bits 21-22: Auto baud rate mode.

Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable.

Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0x0-0xff

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw
RXFTIE
rw
RXFTCFG
rw
TCBGTIE
rw
TXFTIE
rw
WUFIE
rw
WUS
rw
SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw
DEM
rw
DDRE
rw
OVRDIS
rw
ONEBIT
rw
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
SCEN
rw
NACK
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

IREN

Bit 1: Ir mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: Ir low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

OVRDIS

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

SCARCNT

Bits 17-19: Smartcard auto-retry count.

Allowed values: 0x0-0x7

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

TXFTIE

Bit 23: TXFIFO threshold interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG

TCBGTIE

Bit 24: Transmission Complete before guard time, interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated whenever TCBGT=1 in the USART_ISR register

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration.

Allowed values:
0: Depth_1_8: RXFIFO reaches 1/8 of its depth
1: Depth_1_4: RXFIFO reaches 1/4 of its depth
2: Depth_1_2: RXFIFO reaches 1/2 of its depth
3: Depth_3_4: RXFIFO reaches 3/4 of its depth
4: Depth_7_8: RXFIFO reaches 7/8 of its depth
5: Full: RXFIFO becomes full

RXFTIE

Bit 28: RXFIFO threshold interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG

TXFTCFG

Bits 29-31: TXFIFO threshold configuration.

Allowed values:
0: Depth_1_8: TXFIFO reaches 1/8 of its depth
1: Depth_1_4: TXFIFO reaches 1/4 of its depth
2: Depth_1_2: TXFIFO reaches 1/2 of its depth
3: Depth_3_4: TXFIFO reaches 3/4 of its depth
4: Depth_7_8: TXFIFO reaches 7/8 of its depth
5: Empty: TXFIFO becomes empty

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: DIV_Mantissa.

Allowed values: 0x0-0xffff

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw
PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

Allowed values: 0x0-0xff

GT

Bits 8-15: Guard time value.

Allowed values: 0x0-0xff

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw
RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

Allowed values: 0x0-0xffffff

BLEN

Bits 24-31: Block Length.

Allowed values: 0x0-0xff

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w
RXFRQ
w
MMRQ
w
SBKRQ
w
ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: Transmit data flush request.

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r
RXFT
r
TCBGT
r
RXFF
r
TXFE
r
REACK
r
TEACK
r
WUF
r
RWU
r
SBKF
r
CMF
r
BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r
ABRE
r
UDR
r
EOBF
r
RTOF
r
CTS
r
CTSIF
r
LBDF
r
TXE
r
TC
r
RXNE
r
IDLE
r
ORE
r
NF
r
FE
r
PE
r
Toggle fields

PE

Bit 0: PE.

Allowed values:
0: NoError: No parity error
1: Error: Parity error

FE

Bit 1: FE.

Allowed values:
0: NoError: No Framing error is detected
1: Error: Framing error or break character is detected

NF

Bit 2: NF.

Allowed values:
0: NoNoise: No noise is detected
1: Noise: Noise is detected

ORE

Bit 3: ORE.

Allowed values:
0: NoOverrun: No Overrun error
1: Overrun: Overrun error is detected

IDLE

Bit 4: IDLE.

Allowed values:
0: NoIdle: No Idle Line is detected
1: Idle: Idle Line is detected

RXNE

Bit 5: RXNE.

Allowed values:
0: NoData: Data is not received
1: DataReady: Received data is ready to be read

TC

Bit 6: TC.

Allowed values:
0: TxNotComplete: Transmission is not complete
1: TxComplete: Transmission is complete

TXE

Bit 7: TXE.

Allowed values:
0: Full: Transmit FIFO is full
1: NotFull: Transmit FIFO is not full

LBDF

Bit 8: LBDF.

Allowed values:
0: NotDetected: LIN break not detected
1: Detected: LIN break detected

CTSIF

Bit 9: CTSIF.

Allowed values:
0: NotChanged: No change occurred on the CTS status line
1: Changed: A change occurred on the CTS status line

CTS

Bit 10: CTS.

Allowed values:
0: Set: CTS line set
1: Reset: CTS line reset

RTOF

Bit 11: RTOF.

Allowed values:
0: NotReached: Timeout value not reached
1: Reached: Timeout value reached without any data reception

EOBF

Bit 12: EOBF.

Allowed values:
0: NotReached: End of Block not reached
1: Reached: End of Block (number of characters) reached

UDR

Bit 13: SPI slave underrun error flag.

Allowed values:
0: NoUnderrun: No underrun error
1: Underrun: underrun error

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

Allowed values:
0: Idle: USART is idle (no reception)
1: Busy: Reception on going

CMF

Bit 17: CMF.

Allowed values:
0: NoMatch: No Character match detected
1: Match: Character match detected

SBKF

Bit 18: SBKF.

Allowed values:
0: NoBreak: No break character transmitted
1: Break: Break character transmitted

RWU

Bit 19: RWU.

Allowed values:
0: Active: Receiver in Active mode
1: Mute: Receiver in Mute mode

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFIFO Empty.

Allowed values:
0: NotEmpty: TXFIFO not empty.
1: Empty: TXFIFO empty.

RXFF

Bit 24: RXFIFO Full.

Allowed values:
0: NotFull: RXFIFO not full.
1: Full: RXFIFO Full.

TCBGT

Bit 25: Transmission complete before guard time flag.

Allowed values:
0: NotCompleted: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
1: Completed: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)

RXFT

Bit 26: RXFIFO threshold flag.

Allowed values:
0: NotReached: Receive FIFO does not reach the programmed threshold.
1: Reached: Receive FIFO reached the programmed threshold.

TXFT

Bit 27: TXFIFO threshold flag.

Allowed values:
0: NotReached: TXFIFO does not reach the programmed threshold.
1: Reached: TXFIFO reached the programmed threshold.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w1c
CMCF
w1c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w1c
EOBCF
w1c
RTOCF
w1c
CTSCF
w1c
LBDCF
w1c
TCBGTCF
w1c
TCCF
w1c
TXFECF
w1c
IDLECF
w1c
ORECF
w1c
NCF
w1c
FECF
w1c
PECF
w1c
Toggle fields

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TXFECF

Bit 5: TXFIFO empty clear flag.

Allowed values:
1: Clear: Clear the TXFE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag.

Allowed values:
1: Clear: Clear the TCBGT flag in the ISR register

LBDCF

Bit 8: LIN break detection clear flag.

Allowed values:
1: Clear: Clears the LBDF flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

RTOCF

Bit 11: Receiver timeout clear flag.

Allowed values:
1: Clear: Clears the RTOF flag in the ISR register

EOBCF

Bit 12: End of block clear flag.

Allowed values:
1: Clear: Clears the EOBF flag in the ISR register

UDRCF

Bit 13: SPI slave underrun clear flag.

Allowed values:
1: Clear: Clear the UDR flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

Allowed values: 0x0-0x1ff

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

Allowed values: 0x0-0x1ff

PRESC

USART prescaler register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: Clock prescaler.

Allowed values:
0: Div1: Input clock divided by 1
1: Div2: Input clock divided by 2
2: Div4: Input clock divided by 4
3: Div6: Input clock divided by 6
4: Div8: Input clock divided by 8
5: Div10: Input clock divided by 10
6: Div12: Input clock divided by 12
7: Div16: Input clock divided by 16
8: Div32: Input clock divided by 32
9: Div64: Input clock divided by 64
10: Div128: Input clock divided by 128
11: Div256: Input clock divided by 256

USART3

0x40004800: Universal synchronous asynchronous receiver transmitter

124/124 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw
TXFEIE
rw
FIFOEN
rw
M1
rw
EOBIE
rw
RTOIE
rw
DEAT
rw
DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw
CMIE
rw
MME
rw
M0
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
UESM
rw
UE
rw
Toggle fields

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8

DEDT

Bits 16-20: Driver Enable de-assertion time.

Allowed values: 0x0-0x1f

DEAT

Bits 21-25: Driver Enable assertion time.

Allowed values: 0x0-0x1f

RTOIE

Bit 26: Receiver timeout interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register

EOBIE

Bit 27: End of Block interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register

M1

Bit 28: Word length.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

FIFOEN

Bit 29: FIFO mode enable.

Allowed values:
0: Disabled: FIFO mode is disabled
1: Enabled: FIFO mode is enabled

TXFEIE

Bit 30: TXFIFO empty interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when TXFE = 1 in the USART_ISR register

RXFFIE

Bit 31: RXFIFO Full interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when RXFF = 1 in the USART_ISR register

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw
RTOEN
rw
ABRMOD
rw
ABREN
rw
MSBFIRST
rw
DATAINV
rw
TXINV
rw
RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw
LINEN
rw
STOP
rw
CLKEN
rw
CPOL
rw
CPHA
rw
LBCL
rw
LBDIE
rw
LBDL
rw
ADDM7
rw
DIS_NSS
rw
SLVEN
rw
Toggle fields

SLVEN

Bit 0: Synchronous Slave mode enable.

Allowed values:
0: Disabled: Slave mode disabled
1: Enabled: Slave mode enabled

DIS_NSS

Bit 3: When the DSI_NSS bit is set, the NSS pin input is ignored.

Allowed values:
0: Disabled: SPI slave selection depends on NSS input pin
1: Enabled: SPI slave is always selected and NSS input pin is ignored

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

LBDL

Bit 5: LIN break detection length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register

LBCL

Bit 8: Last bit clock pulse.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ABREN

Bit 20: Auto baud rate enable.

Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled

ABRMOD

Bits 21-22: Auto baud rate mode.

Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable.

Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0x0-0xff

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw
RXFTIE
rw
RXFTCFG
rw
TCBGTIE
rw
TXFTIE
rw
WUFIE
rw
WUS
rw
SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw
DEM
rw
DDRE
rw
OVRDIS
rw
ONEBIT
rw
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
SCEN
rw
NACK
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

IREN

Bit 1: Ir mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: Ir low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

OVRDIS

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

SCARCNT

Bits 17-19: Smartcard auto-retry count.

Allowed values: 0x0-0x7

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

TXFTIE

Bit 23: TXFIFO threshold interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG

TCBGTIE

Bit 24: Transmission Complete before guard time, interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated whenever TCBGT=1 in the USART_ISR register

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration.

Allowed values:
0: Depth_1_8: RXFIFO reaches 1/8 of its depth
1: Depth_1_4: RXFIFO reaches 1/4 of its depth
2: Depth_1_2: RXFIFO reaches 1/2 of its depth
3: Depth_3_4: RXFIFO reaches 3/4 of its depth
4: Depth_7_8: RXFIFO reaches 7/8 of its depth
5: Full: RXFIFO becomes full

RXFTIE

Bit 28: RXFIFO threshold interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG

TXFTCFG

Bits 29-31: TXFIFO threshold configuration.

Allowed values:
0: Depth_1_8: TXFIFO reaches 1/8 of its depth
1: Depth_1_4: TXFIFO reaches 1/4 of its depth
2: Depth_1_2: TXFIFO reaches 1/2 of its depth
3: Depth_3_4: TXFIFO reaches 3/4 of its depth
4: Depth_7_8: TXFIFO reaches 7/8 of its depth
5: Empty: TXFIFO becomes empty

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: DIV_Mantissa.

Allowed values: 0x0-0xffff

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw
PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

Allowed values: 0x0-0xff

GT

Bits 8-15: Guard time value.

Allowed values: 0x0-0xff

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw
RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

Allowed values: 0x0-0xffffff

BLEN

Bits 24-31: Block Length.

Allowed values: 0x0-0xff

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w
RXFRQ
w
MMRQ
w
SBKRQ
w
ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: Transmit data flush request.

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r
RXFT
r
TCBGT
r
RXFF
r
TXFE
r
REACK
r
TEACK
r
WUF
r
RWU
r
SBKF
r
CMF
r
BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r
ABRE
r
UDR
r
EOBF
r
RTOF
r
CTS
r
CTSIF
r
LBDF
r
TXE
r
TC
r
RXNE
r
IDLE
r
ORE
r
NF
r
FE
r
PE
r
Toggle fields

PE

Bit 0: PE.

Allowed values:
0: NoError: No parity error
1: Error: Parity error

FE

Bit 1: FE.

Allowed values:
0: NoError: No Framing error is detected
1: Error: Framing error or break character is detected

NF

Bit 2: NF.

Allowed values:
0: NoNoise: No noise is detected
1: Noise: Noise is detected

ORE

Bit 3: ORE.

Allowed values:
0: NoOverrun: No Overrun error
1: Overrun: Overrun error is detected

IDLE

Bit 4: IDLE.

Allowed values:
0: NoIdle: No Idle Line is detected
1: Idle: Idle Line is detected

RXNE

Bit 5: RXNE.

Allowed values:
0: NoData: Data is not received
1: DataReady: Received data is ready to be read

TC

Bit 6: TC.

Allowed values:
0: TxNotComplete: Transmission is not complete
1: TxComplete: Transmission is complete

TXE

Bit 7: TXE.

Allowed values:
0: Full: Transmit FIFO is full
1: NotFull: Transmit FIFO is not full

LBDF

Bit 8: LBDF.

Allowed values:
0: NotDetected: LIN break not detected
1: Detected: LIN break detected

CTSIF

Bit 9: CTSIF.

Allowed values:
0: NotChanged: No change occurred on the CTS status line
1: Changed: A change occurred on the CTS status line

CTS

Bit 10: CTS.

Allowed values:
0: Set: CTS line set
1: Reset: CTS line reset

RTOF

Bit 11: RTOF.

Allowed values:
0: NotReached: Timeout value not reached
1: Reached: Timeout value reached without any data reception

EOBF

Bit 12: EOBF.

Allowed values:
0: NotReached: End of Block not reached
1: Reached: End of Block (number of characters) reached

UDR

Bit 13: SPI slave underrun error flag.

Allowed values:
0: NoUnderrun: No underrun error
1: Underrun: underrun error

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

Allowed values:
0: Idle: USART is idle (no reception)
1: Busy: Reception on going

CMF

Bit 17: CMF.

Allowed values:
0: NoMatch: No Character match detected
1: Match: Character match detected

SBKF

Bit 18: SBKF.

Allowed values:
0: NoBreak: No break character transmitted
1: Break: Break character transmitted

RWU

Bit 19: RWU.

Allowed values:
0: Active: Receiver in Active mode
1: Mute: Receiver in Mute mode

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFIFO Empty.

Allowed values:
0: NotEmpty: TXFIFO not empty.
1: Empty: TXFIFO empty.

RXFF

Bit 24: RXFIFO Full.

Allowed values:
0: NotFull: RXFIFO not full.
1: Full: RXFIFO Full.

TCBGT

Bit 25: Transmission complete before guard time flag.

Allowed values:
0: NotCompleted: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
1: Completed: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)

RXFT

Bit 26: RXFIFO threshold flag.

Allowed values:
0: NotReached: Receive FIFO does not reach the programmed threshold.
1: Reached: Receive FIFO reached the programmed threshold.

TXFT

Bit 27: TXFIFO threshold flag.

Allowed values:
0: NotReached: TXFIFO does not reach the programmed threshold.
1: Reached: TXFIFO reached the programmed threshold.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w1c
CMCF
w1c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w1c
EOBCF
w1c
RTOCF
w1c
CTSCF
w1c
LBDCF
w1c
TCBGTCF
w1c
TCCF
w1c
TXFECF
w1c
IDLECF
w1c
ORECF
w1c
NCF
w1c
FECF
w1c
PECF
w1c
Toggle fields

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TXFECF

Bit 5: TXFIFO empty clear flag.

Allowed values:
1: Clear: Clear the TXFE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag.

Allowed values:
1: Clear: Clear the TCBGT flag in the ISR register

LBDCF

Bit 8: LIN break detection clear flag.

Allowed values:
1: Clear: Clears the LBDF flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

RTOCF

Bit 11: Receiver timeout clear flag.

Allowed values:
1: Clear: Clears the RTOF flag in the ISR register

EOBCF

Bit 12: End of block clear flag.

Allowed values:
1: Clear: Clears the EOBF flag in the ISR register

UDRCF

Bit 13: SPI slave underrun clear flag.

Allowed values:
1: Clear: Clear the UDR flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

Allowed values: 0x0-0x1ff

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

Allowed values: 0x0-0x1ff

PRESC

USART prescaler register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: Clock prescaler.

Allowed values:
0: Div1: Input clock divided by 1
1: Div2: Input clock divided by 2
2: Div4: Input clock divided by 4
3: Div6: Input clock divided by 6
4: Div8: Input clock divided by 8
5: Div10: Input clock divided by 10
6: Div12: Input clock divided by 12
7: Div16: Input clock divided by 16
8: Div32: Input clock divided by 32
9: Div64: Input clock divided by 64
10: Div128: Input clock divided by 128
11: Div256: Input clock divided by 256

USART6

0x40011400: Universal synchronous asynchronous receiver transmitter

124/124 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw
TXFEIE
rw
FIFOEN
rw
M1
rw
EOBIE
rw
RTOIE
rw
DEAT
rw
DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw
CMIE
rw
MME
rw
M0
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
UESM
rw
UE
rw
Toggle fields

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8

DEDT

Bits 16-20: Driver Enable de-assertion time.

Allowed values: 0x0-0x1f

DEAT

Bits 21-25: Driver Enable assertion time.

Allowed values: 0x0-0x1f

RTOIE

Bit 26: Receiver timeout interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register

EOBIE

Bit 27: End of Block interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register

M1

Bit 28: Word length.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

FIFOEN

Bit 29: FIFO mode enable.

Allowed values:
0: Disabled: FIFO mode is disabled
1: Enabled: FIFO mode is enabled

TXFEIE

Bit 30: TXFIFO empty interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when TXFE = 1 in the USART_ISR register

RXFFIE

Bit 31: RXFIFO Full interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when RXFF = 1 in the USART_ISR register

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw
RTOEN
rw
ABRMOD
rw
ABREN
rw
MSBFIRST
rw
DATAINV
rw
TXINV
rw
RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw
LINEN
rw
STOP
rw
CLKEN
rw
CPOL
rw
CPHA
rw
LBCL
rw
LBDIE
rw
LBDL
rw
ADDM7
rw
DIS_NSS
rw
SLVEN
rw
Toggle fields

SLVEN

Bit 0: Synchronous Slave mode enable.

Allowed values:
0: Disabled: Slave mode disabled
1: Enabled: Slave mode enabled

DIS_NSS

Bit 3: When the DSI_NSS bit is set, the NSS pin input is ignored.

Allowed values:
0: Disabled: SPI slave selection depends on NSS input pin
1: Enabled: SPI slave is always selected and NSS input pin is ignored

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

LBDL

Bit 5: LIN break detection length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register

LBCL

Bit 8: Last bit clock pulse.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ABREN

Bit 20: Auto baud rate enable.

Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled

ABRMOD

Bits 21-22: Auto baud rate mode.

Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable.

Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0x0-0xff

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw
RXFTIE
rw
RXFTCFG
rw
TCBGTIE
rw
TXFTIE
rw
WUFIE
rw
WUS
rw
SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw
DEM
rw
DDRE
rw
OVRDIS
rw
ONEBIT
rw
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
SCEN
rw
NACK
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

IREN

Bit 1: Ir mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: Ir low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

OVRDIS

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

SCARCNT

Bits 17-19: Smartcard auto-retry count.

Allowed values: 0x0-0x7

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

TXFTIE

Bit 23: TXFIFO threshold interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG

TCBGTIE

Bit 24: Transmission Complete before guard time, interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated whenever TCBGT=1 in the USART_ISR register

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration.

Allowed values:
0: Depth_1_8: RXFIFO reaches 1/8 of its depth
1: Depth_1_4: RXFIFO reaches 1/4 of its depth
2: Depth_1_2: RXFIFO reaches 1/2 of its depth
3: Depth_3_4: RXFIFO reaches 3/4 of its depth
4: Depth_7_8: RXFIFO reaches 7/8 of its depth
5: Full: RXFIFO becomes full

RXFTIE

Bit 28: RXFIFO threshold interrupt enable.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG

TXFTCFG

Bits 29-31: TXFIFO threshold configuration.

Allowed values:
0: Depth_1_8: TXFIFO reaches 1/8 of its depth
1: Depth_1_4: TXFIFO reaches 1/4 of its depth
2: Depth_1_2: TXFIFO reaches 1/2 of its depth
3: Depth_3_4: TXFIFO reaches 3/4 of its depth
4: Depth_7_8: TXFIFO reaches 7/8 of its depth
5: Empty: TXFIFO becomes empty

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: DIV_Mantissa.

Allowed values: 0x0-0xffff

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw
PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

Allowed values: 0x0-0xff

GT

Bits 8-15: Guard time value.

Allowed values: 0x0-0xff

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw
RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

Allowed values: 0x0-0xffffff

BLEN

Bits 24-31: Block Length.

Allowed values: 0x0-0xff

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w
RXFRQ
w
MMRQ
w
SBKRQ
w
ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: Transmit data flush request.

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r
RXFT
r
TCBGT
r
RXFF
r
TXFE
r
REACK
r
TEACK
r
WUF
r
RWU
r
SBKF
r
CMF
r
BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r
ABRE
r
UDR
r
EOBF
r
RTOF
r
CTS
r
CTSIF
r
LBDF
r
TXE
r
TC
r
RXNE
r
IDLE
r
ORE
r
NF
r
FE
r
PE
r
Toggle fields

PE

Bit 0: PE.

Allowed values:
0: NoError: No parity error
1: Error: Parity error

FE

Bit 1: FE.

Allowed values:
0: NoError: No Framing error is detected
1: Error: Framing error or break character is detected

NF

Bit 2: NF.

Allowed values:
0: NoNoise: No noise is detected
1: Noise: Noise is detected

ORE

Bit 3: ORE.

Allowed values:
0: NoOverrun: No Overrun error
1: Overrun: Overrun error is detected

IDLE

Bit 4: IDLE.

Allowed values:
0: NoIdle: No Idle Line is detected
1: Idle: Idle Line is detected

RXNE

Bit 5: RXNE.

Allowed values:
0: NoData: Data is not received
1: DataReady: Received data is ready to be read

TC

Bit 6: TC.

Allowed values:
0: TxNotComplete: Transmission is not complete
1: TxComplete: Transmission is complete

TXE

Bit 7: TXE.

Allowed values:
0: Full: Transmit FIFO is full
1: NotFull: Transmit FIFO is not full

LBDF

Bit 8: LBDF.

Allowed values:
0: NotDetected: LIN break not detected
1: Detected: LIN break detected

CTSIF

Bit 9: CTSIF.

Allowed values:
0: NotChanged: No change occurred on the CTS status line
1: Changed: A change occurred on the CTS status line

CTS

Bit 10: CTS.

Allowed values:
0: Set: CTS line set
1: Reset: CTS line reset

RTOF

Bit 11: RTOF.

Allowed values:
0: NotReached: Timeout value not reached
1: Reached: Timeout value reached without any data reception

EOBF

Bit 12: EOBF.

Allowed values:
0: NotReached: End of Block not reached
1: Reached: End of Block (number of characters) reached

UDR

Bit 13: SPI slave underrun error flag.

Allowed values:
0: NoUnderrun: No underrun error
1: Underrun: underrun error

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

Allowed values:
0: Idle: USART is idle (no reception)
1: Busy: Reception on going

CMF

Bit 17: CMF.

Allowed values:
0: NoMatch: No Character match detected
1: Match: Character match detected

SBKF

Bit 18: SBKF.

Allowed values:
0: NoBreak: No break character transmitted
1: Break: Break character transmitted

RWU

Bit 19: RWU.

Allowed values:
0: Active: Receiver in Active mode
1: Mute: Receiver in Mute mode

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFIFO Empty.

Allowed values:
0: NotEmpty: TXFIFO not empty.
1: Empty: TXFIFO empty.

RXFF

Bit 24: RXFIFO Full.

Allowed values:
0: NotFull: RXFIFO not full.
1: Full: RXFIFO Full.

TCBGT

Bit 25: Transmission complete before guard time flag.

Allowed values:
0: NotCompleted: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
1: Completed: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)

RXFT

Bit 26: RXFIFO threshold flag.

Allowed values:
0: NotReached: Receive FIFO does not reach the programmed threshold.
1: Reached: Receive FIFO reached the programmed threshold.

TXFT

Bit 27: TXFIFO threshold flag.

Allowed values:
0: NotReached: TXFIFO does not reach the programmed threshold.
1: Reached: TXFIFO reached the programmed threshold.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w1c
CMCF
w1c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w1c
EOBCF
w1c
RTOCF
w1c
CTSCF
w1c
LBDCF
w1c
TCBGTCF
w1c
TCCF
w1c
TXFECF
w1c
IDLECF
w1c
ORECF
w1c
NCF
w1c
FECF
w1c
PECF
w1c
Toggle fields

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TXFECF

Bit 5: TXFIFO empty clear flag.

Allowed values:
1: Clear: Clear the TXFE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag.

Allowed values:
1: Clear: Clear the TCBGT flag in the ISR register

LBDCF

Bit 8: LIN break detection clear flag.

Allowed values:
1: Clear: Clears the LBDF flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

RTOCF

Bit 11: Receiver timeout clear flag.

Allowed values:
1: Clear: Clears the RTOF flag in the ISR register

EOBCF

Bit 12: End of block clear flag.

Allowed values:
1: Clear: Clears the EOBF flag in the ISR register

UDRCF

Bit 13: SPI slave underrun clear flag.

Allowed values:
1: Clear: Clear the UDR flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

Allowed values: 0x0-0x1ff

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

Allowed values: 0x0-0x1ff

PRESC

USART prescaler register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: Clock prescaler.

Allowed values:
0: Div1: Input clock divided by 1
1: Div2: Input clock divided by 2
2: Div4: Input clock divided by 4
3: Div6: Input clock divided by 6
4: Div8: Input clock divided by 8
5: Div10: Input clock divided by 10
6: Div12: Input clock divided by 12
7: Div16: Input clock divided by 16
8: Div32: Input clock divided by 32
9: Div64: Input clock divided by 64
10: Div128: Input clock divided by 128
11: Div256: Input clock divided by 256

VREFBUF

0x58003c00: VREFBUF

1/5 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CSR
0x4 CCR
Toggle registers

CSR

VREFBUF control and status register

Offset: 0x0, size: 32, reset: 0x00000002, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VRS
rw
VRR
r
HIZ
rw
ENVR
rw
Toggle fields

ENVR

Bit 0: Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode..

HIZ

Bit 1: High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to Table196: VREF buffer modes for the mode descriptions depending on ENVR bit configuration..

VRR

Bit 3: Voltage reference buffer ready.

VRS

Bits 4-6: Voltage reference scale These bits select the value generated by the voltage reference buffer. Other: Reserved.

CCR

VREFBUF calibration control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIM
rw
Toggle fields

TRIM

Bits 0-5: Trimming code These bits are automatically initialized after reset with the trimming value stored in the Flash memory during the production test. Writing into these bits allows to tune the internal reference buffer voltage..

WWDG

0x50003000: WWDG

6/6 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) CR
0x4 (16-bit) CFR
0x8 (16-bit) SR
Toggle registers

CR

Control register

Offset: 0x0, size: 16, reset: 0x0000007F, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDGA
rw
T
rw
Toggle fields

T

Bits 0-6: 7-bit counter (MSB to LSB) These bits contain the value of the watchdog counter. It is decremented every (4096 x 2WDGTB[1:0]) PCLK cycles. A reset is produced when it is decremented from 0x40 to 0x3F (T6 becomes cleared)..

Allowed values: 0x0-0x7f

WDGA

Bit 7: Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA=1, the watchdog can generate a reset..

Allowed values:
0: Disabled: Watchdog disabled
1: Enabled: Watchdog enabled

CFR

Configuration register

Offset: 0x4, size: 16, reset: 0x0000007F, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDGTB
rw
EWI
rw
W
rw
Toggle fields

W

Bits 0-6: 7-bit window value These bits contain the window value to be compared to the downcounter..

Allowed values: 0x0-0x7f

EWI

Bit 9: Early wakeup interrupt When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is only cleared by hardware after a reset..

Allowed values:
1: Enable: interrupt occurs whenever the counter reaches the value 0x40

WDGTB

Bits 11-13: Timer base The time base of the prescaler can be modified as follows:.

Allowed values:
0: Div1: Counter clock (PCLK1 div 4096) div 1
1: Div2: Counter clock (PCLK1 div 4096) div 2
2: Div4: Counter clock (PCLK1 div 4096) div 4
3: Div8: Counter clock (PCLK1 div 4096) div 8
4: Div16: Counter clock (PCLK1 div 4096) div 16
5: Div32: Counter clock (PCLK1 div 4096) div 32
6: Div64: Counter clock (PCLK1 div 4096) div 64
7: Div128: Counter clock (PCLK1 div 4096) div 128

SR

Status register

Offset: 0x8, size: 16, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWIF
r/w0c
Toggle fields

EWIF

Bit 0: Early wakeup interrupt flag This bit is set by hardware when the counter has reached the value 0x40. It must be cleared by software by writing 0. A write of 1 has no effect. This bit is also set if the interrupt is not enabled..

Allowed values:
0: Finished: The EWI Interrupt Service Routine has been serviced
1: Pending: The EWI Interrupt Service Routine has been triggered